2 * ipr.h -- driver for IBM Power Linux RAID adapters
4 * Written By: Brian King <brking@us.ibm.com>, IBM Corporation
6 * Copyright (C) 2003, 2004 IBM Corporation
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 * Alan Cox <alan@lxorguk.ukuu.org.uk> - Removed several careless u32/dma_addr_t errors
23 * that broke 64bit platforms.
29 #include <linux/types.h>
30 #include <linux/completion.h>
31 #include <linux/libata.h>
32 #include <linux/list.h>
33 #include <linux/kref.h>
34 #include <scsi/scsi.h>
35 #include <scsi/scsi_cmnd.h>
40 #define IPR_DRIVER_VERSION "2.5.0"
41 #define IPR_DRIVER_DATE "(February 11, 2010)"
44 * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
45 * ops per device for devices not running tagged command queuing.
46 * This can be adjusted at runtime through sysfs device attributes.
48 #define IPR_MAX_CMD_PER_LUN 6
49 #define IPR_MAX_CMD_PER_ATA_LUN 1
52 * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of
53 * ops the mid-layer can send to the adapter.
55 #define IPR_NUM_BASE_CMD_BLKS 100
57 #define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339
59 #define PCI_DEVICE_ID_IBM_CROC_FPGA_E2 0x033D
60 #define PCI_DEVICE_ID_IBM_CROC_ASIC_E2 0x034A
62 #define IPR_SUBS_DEV_ID_2780 0x0264
63 #define IPR_SUBS_DEV_ID_5702 0x0266
64 #define IPR_SUBS_DEV_ID_5703 0x0278
65 #define IPR_SUBS_DEV_ID_572E 0x028D
66 #define IPR_SUBS_DEV_ID_573E 0x02D3
67 #define IPR_SUBS_DEV_ID_573D 0x02D4
68 #define IPR_SUBS_DEV_ID_571A 0x02C0
69 #define IPR_SUBS_DEV_ID_571B 0x02BE
70 #define IPR_SUBS_DEV_ID_571E 0x02BF
71 #define IPR_SUBS_DEV_ID_571F 0x02D5
72 #define IPR_SUBS_DEV_ID_572A 0x02C1
73 #define IPR_SUBS_DEV_ID_572B 0x02C2
74 #define IPR_SUBS_DEV_ID_572F 0x02C3
75 #define IPR_SUBS_DEV_ID_574E 0x030A
76 #define IPR_SUBS_DEV_ID_575B 0x030D
77 #define IPR_SUBS_DEV_ID_575C 0x0338
78 #define IPR_SUBS_DEV_ID_57B3 0x033A
79 #define IPR_SUBS_DEV_ID_57B7 0x0360
80 #define IPR_SUBS_DEV_ID_57B8 0x02C2
82 #define IPR_SUBS_DEV_ID_57B4 0x033B
83 #define IPR_SUBS_DEV_ID_57B2 0x035F
84 #define IPR_SUBS_DEV_ID_57C6 0x0357
86 #define IPR_SUBS_DEV_ID_57B5 0x033C
87 #define IPR_SUBS_DEV_ID_57CE 0x035E
88 #define IPR_SUBS_DEV_ID_57B1 0x0355
90 #define IPR_SUBS_DEV_ID_574D 0x0356
91 #define IPR_SUBS_DEV_ID_575D 0x035D
93 #define IPR_NAME "ipr"
98 #define IPR_RC_JOB_CONTINUE 1
99 #define IPR_RC_JOB_RETURN 2
104 #define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200
105 #define IPR_IOASC_NR_IOA_RESET_REQUIRED 0x02048000
106 #define IPR_IOASC_SYNC_REQUIRED 0x023f0000
107 #define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00
108 #define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000
109 #define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500
110 #define IPR_IOASC_IOASC_MASK 0xFFFFFF00
111 #define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF
112 #define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT 0x05240000
113 #define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000
114 #define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100
115 #define IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000
116 #define IPR_IOASC_BUS_WAS_RESET 0x06290000
117 #define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000
118 #define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000
120 #define IPR_FIRST_DRIVER_IOASC 0x10000000
121 #define IPR_IOASC_IOA_WAS_RESET 0x10000001
122 #define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002
124 /* Driver data flags */
125 #define IPR_USE_LONG_TRANSOP_TIMEOUT 0x00000001
126 #define IPR_USE_PCI_WARM_RESET 0x00000002
128 #define IPR_DEFAULT_MAX_ERROR_DUMP 984
129 #define IPR_NUM_LOG_HCAMS 2
130 #define IPR_NUM_CFG_CHG_HCAMS 2
131 #define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
133 #define IPR_MAX_SIS64_TARGETS_PER_BUS 1024
134 #define IPR_MAX_SIS64_LUNS_PER_TARGET 0xffffffff
136 #define IPR_MAX_NUM_TARGETS_PER_BUS 256
137 #define IPR_MAX_NUM_LUNS_PER_TARGET 256
138 #define IPR_MAX_NUM_VSET_LUNS_PER_TARGET 8
139 #define IPR_VSET_BUS 0xff
140 #define IPR_IOA_BUS 0xff
141 #define IPR_IOA_TARGET 0xff
142 #define IPR_IOA_LUN 0xff
143 #define IPR_MAX_NUM_BUSES 16
144 #define IPR_MAX_BUS_TO_SCAN IPR_MAX_NUM_BUSES
146 #define IPR_NUM_RESET_RELOAD_RETRIES 3
148 /* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */
149 #define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \
150 ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 4)
152 #define IPR_MAX_COMMANDS IPR_NUM_BASE_CMD_BLKS
153 #define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \
154 IPR_NUM_INTERNAL_CMD_BLKS)
156 #define IPR_MAX_PHYSICAL_DEVS 192
157 #define IPR_DEFAULT_SIS64_DEVS 1024
158 #define IPR_MAX_SIS64_DEVS 4096
160 #define IPR_MAX_SGLIST 64
161 #define IPR_IOA_MAX_SECTORS 32767
162 #define IPR_VSET_MAX_SECTORS 512
163 #define IPR_MAX_CDB_LEN 16
164 #define IPR_MAX_HRRQ_RETRIES 3
166 #define IPR_DEFAULT_BUS_WIDTH 16
167 #define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
168 #define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
169 #define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
170 #define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8))
172 #define IPR_IOA_RES_HANDLE 0xffffffff
173 #define IPR_INVALID_RES_HANDLE 0
174 #define IPR_IOA_RES_ADDR 0x00ffffff
179 #define IPR_QUERY_RSRC_STATE 0xC2
180 #define IPR_RESET_DEVICE 0xC3
181 #define IPR_RESET_TYPE_SELECT 0x80
182 #define IPR_LUN_RESET 0x40
183 #define IPR_TARGET_RESET 0x20
184 #define IPR_BUS_RESET 0x10
185 #define IPR_ATA_PHY_RESET 0x80
186 #define IPR_ID_HOST_RR_Q 0xC4
187 #define IPR_QUERY_IOA_CONFIG 0xC5
188 #define IPR_CANCEL_ALL_REQUESTS 0xCE
189 #define IPR_HOST_CONTROLLED_ASYNC 0xCF
190 #define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01
191 #define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02
192 #define IPR_SET_SUPPORTED_DEVICES 0xFB
193 #define IPR_SET_ALL_SUPPORTED_DEVICES 0x80
194 #define IPR_IOA_SHUTDOWN 0xF7
195 #define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05
200 #define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ)
201 #define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ)
202 #define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ)
203 #define IPR_DUAL_IOA_ABBR_SHUTDOWN_TO (2 * 60 * HZ)
204 #define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
205 #define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
206 #define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
207 #define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
208 #define IPR_WRITE_BUFFER_TIMEOUT (10 * 60 * HZ)
209 #define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ)
210 #define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ)
211 #define IPR_OPERATIONAL_TIMEOUT (5 * 60)
212 #define IPR_LONG_OPERATIONAL_TIMEOUT (12 * 60)
213 #define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ)
214 #define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10)
215 #define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ)
216 #define IPR_PCI_RESET_TIMEOUT (HZ / 2)
217 #define IPR_DUMP_TIMEOUT (15 * HZ)
222 #define IPR_VENDOR_ID_LEN 8
223 #define IPR_PROD_ID_LEN 16
224 #define IPR_SERIAL_NUM_LEN 8
229 #define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff
230 #define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000
231 #define IPR_FMT2_MKR_BAR_SEL_SHIFT 28
232 #define IPR_GET_FMT2_BAR_SEL(mbx) \
233 (((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT)
234 #define IPR_SDT_FMT2_BAR0_SEL 0x0
235 #define IPR_SDT_FMT2_BAR1_SEL 0x1
236 #define IPR_SDT_FMT2_BAR2_SEL 0x2
237 #define IPR_SDT_FMT2_BAR3_SEL 0x3
238 #define IPR_SDT_FMT2_BAR4_SEL 0x4
239 #define IPR_SDT_FMT2_BAR5_SEL 0x5
240 #define IPR_SDT_FMT2_EXP_ROM_SEL 0x8
241 #define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2
242 #define IPR_FMT3_SDT_READY_TO_USE 0xC4D4E3F3
243 #define IPR_DOORBELL 0x82800000
244 #define IPR_RUNTIME_RESET 0x40000000
246 #define IPR_IPL_INIT_MIN_STAGE_TIME 5
247 #define IPR_IPL_INIT_DEFAULT_STAGE_TIME 15
248 #define IPR_IPL_INIT_STAGE_UNKNOWN 0x0
249 #define IPR_IPL_INIT_STAGE_TRANSOP 0xB0000000
250 #define IPR_IPL_INIT_STAGE_MASK 0xff000000
251 #define IPR_IPL_INIT_STAGE_TIME_MASK 0x0000ffff
252 #define IPR_PCII_IPL_STAGE_CHANGE (0x80000000 >> 0)
254 #define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0)
255 #define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3)
256 #define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4)
257 #define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5)
258 #define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6)
259 #define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7)
260 #define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27)
261 #define IPR_PCII_MMIO_ERROR (0x80000000 >> 28)
262 #define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29)
263 #define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30)
264 #define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31)
266 #define IPR_PCII_ERROR_INTERRUPTS \
267 (IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \
268 IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR)
270 #define IPR_PCII_OPER_INTERRUPTS \
271 (IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER)
273 #define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7)
274 #define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9)
276 #define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */
277 #define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */
282 #define IPR_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024)
283 #define IPR_NUM_SDT_ENTRIES 511
284 #define IPR_MAX_NUM_DUMP_PAGES ((IPR_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
289 #define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST
292 * Adapter interface types
295 struct ipr_res_addr {
300 #define IPR_GET_PHYS_LOC(res_addr) \
301 (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun)
302 }__attribute__((packed, aligned (4)));
304 struct ipr_std_inq_vpids {
305 u8 vendor_id[IPR_VENDOR_ID_LEN];
306 u8 product_id[IPR_PROD_ID_LEN];
307 }__attribute__((packed));
310 struct ipr_std_inq_vpids vpids;
311 u8 sn[IPR_SERIAL_NUM_LEN];
312 }__attribute__((packed));
317 }__attribute__((packed));
319 struct ipr_std_inq_data {
320 u8 peri_qual_dev_type;
321 #define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5)
322 #define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F)
324 u8 removeable_medium_rsvd;
325 #define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80
327 #define IPR_IS_DASD_DEVICE(std_inq) \
328 ((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \
329 !(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM))
331 #define IPR_IS_SES_DEVICE(std_inq) \
332 (IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE)
341 struct ipr_std_inq_vpids vpids;
343 u8 ros_rsvd_ram_rsvd[4];
345 u8 serial_num[IPR_SERIAL_NUM_LEN];
346 }__attribute__ ((packed));
348 #define IPR_RES_TYPE_AF_DASD 0x00
349 #define IPR_RES_TYPE_GENERIC_SCSI 0x01
350 #define IPR_RES_TYPE_VOLUME_SET 0x02
351 #define IPR_RES_TYPE_REMOTE_AF_DASD 0x03
352 #define IPR_RES_TYPE_GENERIC_ATA 0x04
353 #define IPR_RES_TYPE_ARRAY 0x05
354 #define IPR_RES_TYPE_IOAFP 0xff
356 struct ipr_config_table_entry {
358 #define IPR_PROTO_SATA 0x02
359 #define IPR_PROTO_SATA_ATAPI 0x03
360 #define IPR_PROTO_SAS_STP 0x06
361 #define IPR_PROTO_SAS_STP_ATAPI 0x07
364 #define IPR_IS_IOA_RESOURCE 0x80
367 #define IPR_QUEUEING_MODEL(res) ((((res)->flags) & 0x70) >> 4)
368 #define IPR_QUEUE_FROZEN_MODEL 0
369 #define IPR_QUEUE_NACA_MODEL 1
371 struct ipr_res_addr res_addr;
374 struct ipr_std_inq_data std_inq_data;
375 }__attribute__ ((packed, aligned (4)));
377 struct ipr_config_table_entry64 {
384 #define IPR_QUEUEING_MODEL64(res) ((((res)->res_flags) & 0x7000) >> 12)
391 #define IPR_MAX_RES_PATH_LENGTH 24
393 struct ipr_std_inq_data std_inq_data;
395 __be64 reserved3[2]; // description text
397 }__attribute__ ((packed, aligned (8)));
399 struct ipr_config_table_hdr {
402 #define IPR_UCODE_DOWNLOAD_REQ 0x10
404 }__attribute__((packed, aligned (4)));
406 struct ipr_config_table_hdr64 {
411 }__attribute__((packed, aligned (4)));
413 struct ipr_config_table {
414 struct ipr_config_table_hdr hdr;
415 struct ipr_config_table_entry dev[0];
416 }__attribute__((packed, aligned (4)));
418 struct ipr_config_table64 {
419 struct ipr_config_table_hdr64 hdr64;
420 struct ipr_config_table_entry64 dev[0];
421 }__attribute__((packed, aligned (8)));
423 struct ipr_config_table_entry_wrapper {
425 struct ipr_config_table_entry *cfgte;
426 struct ipr_config_table_entry64 *cfgte64;
430 struct ipr_hostrcb_cfg_ch_not {
432 struct ipr_config_table_entry cfgte;
433 struct ipr_config_table_entry64 cfgte64;
436 }__attribute__((packed, aligned (4)));
438 struct ipr_supported_device {
442 struct ipr_std_inq_vpids vpids;
444 }__attribute__((packed, aligned (4)));
446 /* Command packet structure */
448 __be16 reserved; /* Reserved by IOA */
450 #define IPR_RQTYPE_SCSICDB 0x00
451 #define IPR_RQTYPE_IOACMD 0x01
452 #define IPR_RQTYPE_HCAM 0x02
453 #define IPR_RQTYPE_ATA_PASSTHRU 0x04
458 #define IPR_FLAGS_HI_WRITE_NOT_READ 0x80
459 #define IPR_FLAGS_HI_NO_ULEN_CHK 0x20
460 #define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10
461 #define IPR_FLAGS_HI_SYNC_COMPLETE 0x08
462 #define IPR_FLAGS_HI_NO_LINK_DESC 0x04
465 #define IPR_FLAGS_LO_ALIGNED_BFR 0x20
466 #define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10
467 #define IPR_FLAGS_LO_UNTAGGED_TASK 0x00
468 #define IPR_FLAGS_LO_SIMPLE_TASK 0x02
469 #define IPR_FLAGS_LO_ORDERED_TASK 0x04
470 #define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06
471 #define IPR_FLAGS_LO_ACA_TASK 0x08
475 }__attribute__ ((packed, aligned(4)));
477 struct ipr_ioarcb_ata_regs { /* 22 bytes */
479 #define IPR_ATA_FLAG_PACKET_CMD 0x80
480 #define IPR_ATA_FLAG_XFER_TYPE_DMA 0x40
481 #define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION 0x20
499 }__attribute__ ((packed, aligned(4)));
501 struct ipr_ioadl_desc {
502 __be32 flags_and_data_len;
503 #define IPR_IOADL_FLAGS_MASK 0xff000000
504 #define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK)
505 #define IPR_IOADL_DATA_LEN_MASK 0x00ffffff
506 #define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK)
507 #define IPR_IOADL_FLAGS_READ 0x48000000
508 #define IPR_IOADL_FLAGS_READ_LAST 0x49000000
509 #define IPR_IOADL_FLAGS_WRITE 0x68000000
510 #define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000
511 #define IPR_IOADL_FLAGS_LAST 0x01000000
514 }__attribute__((packed, aligned (8)));
516 struct ipr_ioadl64_desc {
520 }__attribute__((packed, aligned (16)));
522 struct ipr_ata64_ioadl {
523 struct ipr_ioarcb_ata_regs regs;
525 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
526 }__attribute__((packed, aligned (16)));
528 struct ipr_ioarcb_add_data {
530 struct ipr_ioarcb_ata_regs regs;
531 struct ipr_ioadl_desc ioadl[5];
532 __be32 add_cmd_parms[10];
534 }__attribute__ ((packed, aligned (4)));
536 struct ipr_ioarcb_sis64_add_addr_ecb {
537 __be64 ioasa_host_pci_addr;
538 __be64 data_ioadl_addr;
540 __be32 ext_control_buf[4];
541 }__attribute__((packed, aligned (8)));
543 /* IOA Request Control Block 128 bytes */
546 __be32 ioarcb_host_pci_addr;
547 __be64 ioarcb_host_pci_addr64;
550 __be32 host_response_handle;
555 __be32 data_transfer_length;
556 __be32 read_data_transfer_length;
557 __be32 write_ioadl_addr;
559 __be32 read_ioadl_addr;
560 __be32 read_ioadl_len;
562 __be32 ioasa_host_pci_addr;
566 struct ipr_cmd_pkt cmd_pkt;
568 __be16 add_cmd_parms_offset;
569 __be16 add_cmd_parms_len;
572 struct ipr_ioarcb_add_data add_data;
573 struct ipr_ioarcb_sis64_add_addr_ecb sis64_addr_data;
576 }__attribute__((packed, aligned (4)));
578 struct ipr_ioasa_vset {
579 __be32 failing_lba_hi;
580 __be32 failing_lba_lo;
582 }__attribute__((packed, aligned (4)));
584 struct ipr_ioasa_af_dasd {
587 }__attribute__((packed, aligned (4)));
589 struct ipr_ioasa_gpdd {
594 }__attribute__((packed, aligned (4)));
596 struct ipr_ioasa_gata {
598 u8 nsect; /* Interrupt reason */
604 u8 alt_status; /* ATA CTL */
609 }__attribute__((packed, aligned (4)));
611 struct ipr_auto_sense {
612 __be16 auto_sense_len;
614 __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)];
619 #define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
620 #define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
621 #define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
622 #define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
624 __be16 ret_stat_len; /* Length of the returned IOASA */
626 __be16 avail_stat_len; /* Total Length of status available. */
628 __be32 residual_data_len; /* number of bytes in the host data */
629 /* buffers that were not used by the IOARCB command. */
632 #define IPR_NO_ILID 0
633 #define IPR_DRIVER_ILID 0xffffffff
637 __be32 fd_phys_locator;
639 __be32 fd_res_handle;
641 __be32 ioasc_specific; /* status code specific field */
642 #define IPR_ADDITIONAL_STATUS_FMT 0x80000000
643 #define IPR_AUTOSENSE_VALID 0x40000000
644 #define IPR_ATA_DEVICE_WAS_RESET 0x20000000
645 #define IPR_IOASC_SPECIFIC_MASK 0x00ffffff
646 #define IPR_FIELD_POINTER_VALID (0x80000000 >> 8)
647 #define IPR_FIELD_POINTER_MASK 0x0000ffff
650 struct ipr_ioasa_vset vset;
651 struct ipr_ioasa_af_dasd dasd;
652 struct ipr_ioasa_gpdd gpdd;
653 struct ipr_ioasa_gata gata;
656 struct ipr_auto_sense auto_sense;
657 }__attribute__((packed, aligned (4)));
659 struct ipr_mode_parm_hdr {
662 u8 device_spec_parms;
664 }__attribute__((packed));
666 struct ipr_mode_pages {
667 struct ipr_mode_parm_hdr hdr;
668 u8 data[255 - sizeof(struct ipr_mode_parm_hdr)];
669 }__attribute__((packed));
671 struct ipr_mode_page_hdr {
673 #define IPR_MODE_PAGE_PS 0x80
674 #define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F)
676 }__attribute__ ((packed));
678 struct ipr_dev_bus_entry {
679 struct ipr_res_addr res_addr;
681 #define IPR_SCSI_ATTR_ENABLE_QAS 0x80
682 #define IPR_SCSI_ATTR_DISABLE_QAS 0x40
683 #define IPR_SCSI_ATTR_QAS_MASK 0xC0
684 #define IPR_SCSI_ATTR_ENABLE_TM 0x20
685 #define IPR_SCSI_ATTR_NO_TERM_PWR 0x10
686 #define IPR_SCSI_ATTR_TM_SUPPORTED 0x08
687 #define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04
691 u8 extended_reset_delay;
692 #define IPR_EXTENDED_RESET_DELAY 7
694 __be32 max_xfer_rate;
699 }__attribute__((packed, aligned (4)));
701 struct ipr_mode_page28 {
702 struct ipr_mode_page_hdr hdr;
705 struct ipr_dev_bus_entry bus[0];
706 }__attribute__((packed));
708 struct ipr_mode_page24 {
709 struct ipr_mode_page_hdr hdr;
711 #define IPR_ENABLE_DUAL_IOA_AF 0x80
712 }__attribute__((packed));
715 struct ipr_std_inq_data std_inq_data;
716 u8 ascii_part_num[12];
718 u8 ascii_plant_code[4];
719 }__attribute__((packed));
721 struct ipr_inquiry_page3 {
722 u8 peri_qual_dev_type;
734 }__attribute__((packed));
736 struct ipr_inquiry_cap {
737 u8 peri_qual_dev_type;
745 #define IPR_CAP_DUAL_IOA_RAID 0x80
747 }__attribute__((packed));
749 #define IPR_INQUIRY_PAGE0_ENTRIES 20
750 struct ipr_inquiry_page0 {
751 u8 peri_qual_dev_type;
755 u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
756 }__attribute__((packed));
758 struct ipr_hostrcb_device_data_entry {
760 struct ipr_res_addr dev_res_addr;
761 struct ipr_vpd new_vpd;
762 struct ipr_vpd ioa_last_with_dev_vpd;
763 struct ipr_vpd cfc_last_with_dev_vpd;
765 }__attribute__((packed, aligned (4)));
767 struct ipr_hostrcb_device_data_entry_enhanced {
768 struct ipr_ext_vpd vpd;
770 struct ipr_res_addr dev_res_addr;
771 struct ipr_ext_vpd new_vpd;
773 struct ipr_ext_vpd ioa_last_with_dev_vpd;
774 struct ipr_ext_vpd cfc_last_with_dev_vpd;
775 }__attribute__((packed, aligned (4)));
777 struct ipr_hostrcb64_device_data_entry_enhanced {
778 struct ipr_ext_vpd vpd;
781 struct ipr_ext_vpd new_vpd;
783 struct ipr_ext_vpd ioa_last_with_dev_vpd;
784 struct ipr_ext_vpd cfc_last_with_dev_vpd;
785 }__attribute__((packed, aligned (4)));
787 struct ipr_hostrcb_array_data_entry {
789 struct ipr_res_addr expected_dev_res_addr;
790 struct ipr_res_addr dev_res_addr;
791 }__attribute__((packed, aligned (4)));
793 struct ipr_hostrcb64_array_data_entry {
794 struct ipr_ext_vpd vpd;
796 u8 expected_res_path[8];
798 }__attribute__((packed, aligned (4)));
800 struct ipr_hostrcb_array_data_entry_enhanced {
801 struct ipr_ext_vpd vpd;
803 struct ipr_res_addr expected_dev_res_addr;
804 struct ipr_res_addr dev_res_addr;
805 }__attribute__((packed, aligned (4)));
807 struct ipr_hostrcb_type_ff_error {
808 __be32 ioa_data[758];
809 }__attribute__((packed, aligned (4)));
811 struct ipr_hostrcb_type_01_error {
815 __be32 ioa_data[236];
816 }__attribute__((packed, aligned (4)));
818 struct ipr_hostrcb_type_02_error {
819 struct ipr_vpd ioa_vpd;
820 struct ipr_vpd cfc_vpd;
821 struct ipr_vpd ioa_last_attached_to_cfc_vpd;
822 struct ipr_vpd cfc_last_attached_to_ioa_vpd;
824 }__attribute__((packed, aligned (4)));
826 struct ipr_hostrcb_type_12_error {
827 struct ipr_ext_vpd ioa_vpd;
828 struct ipr_ext_vpd cfc_vpd;
829 struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd;
830 struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd;
832 }__attribute__((packed, aligned (4)));
834 struct ipr_hostrcb_type_03_error {
835 struct ipr_vpd ioa_vpd;
836 struct ipr_vpd cfc_vpd;
837 __be32 errors_detected;
838 __be32 errors_logged;
840 struct ipr_hostrcb_device_data_entry dev[3];
841 }__attribute__((packed, aligned (4)));
843 struct ipr_hostrcb_type_13_error {
844 struct ipr_ext_vpd ioa_vpd;
845 struct ipr_ext_vpd cfc_vpd;
846 __be32 errors_detected;
847 __be32 errors_logged;
848 struct ipr_hostrcb_device_data_entry_enhanced dev[3];
849 }__attribute__((packed, aligned (4)));
851 struct ipr_hostrcb_type_23_error {
852 struct ipr_ext_vpd ioa_vpd;
853 struct ipr_ext_vpd cfc_vpd;
854 __be32 errors_detected;
855 __be32 errors_logged;
856 struct ipr_hostrcb64_device_data_entry_enhanced dev[3];
857 }__attribute__((packed, aligned (4)));
859 struct ipr_hostrcb_type_04_error {
860 struct ipr_vpd ioa_vpd;
861 struct ipr_vpd cfc_vpd;
863 struct ipr_hostrcb_array_data_entry array_member[10];
864 __be32 exposed_mode_adn;
866 struct ipr_vpd incomp_dev_vpd;
868 struct ipr_hostrcb_array_data_entry array_member2[8];
869 struct ipr_res_addr last_func_vset_res_addr;
870 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
871 u8 protection_level[8];
872 }__attribute__((packed, aligned (4)));
874 struct ipr_hostrcb_type_14_error {
875 struct ipr_ext_vpd ioa_vpd;
876 struct ipr_ext_vpd cfc_vpd;
877 __be32 exposed_mode_adn;
879 struct ipr_res_addr last_func_vset_res_addr;
880 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
881 u8 protection_level[8];
883 struct ipr_hostrcb_array_data_entry_enhanced array_member[18];
884 }__attribute__((packed, aligned (4)));
886 struct ipr_hostrcb_type_24_error {
887 struct ipr_ext_vpd ioa_vpd;
888 struct ipr_ext_vpd cfc_vpd;
891 #define IPR_INVALID_ARRAY_DEV_NUM 0xff
894 u8 protection_level[8];
895 struct ipr_ext_vpd array_vpd;
899 struct ipr_hostrcb64_array_data_entry array_member[32];
900 }__attribute__((packed, aligned (4)));
902 struct ipr_hostrcb_type_07_error {
903 u8 failure_reason[64];
906 }__attribute__((packed, aligned (4)));
908 struct ipr_hostrcb_type_17_error {
909 u8 failure_reason[64];
910 struct ipr_ext_vpd vpd;
912 }__attribute__((packed, aligned (4)));
914 struct ipr_hostrcb_config_element {
916 #define IPR_PATH_CFG_TYPE_MASK 0xF0
917 #define IPR_PATH_CFG_NOT_EXIST 0x00
918 #define IPR_PATH_CFG_IOA_PORT 0x10
919 #define IPR_PATH_CFG_EXP_PORT 0x20
920 #define IPR_PATH_CFG_DEVICE_PORT 0x30
921 #define IPR_PATH_CFG_DEVICE_LUN 0x40
923 #define IPR_PATH_CFG_STATUS_MASK 0x0F
924 #define IPR_PATH_CFG_NO_PROB 0x00
925 #define IPR_PATH_CFG_DEGRADED 0x01
926 #define IPR_PATH_CFG_FAILED 0x02
927 #define IPR_PATH_CFG_SUSPECT 0x03
928 #define IPR_PATH_NOT_DETECTED 0x04
929 #define IPR_PATH_INCORRECT_CONN 0x05
931 u8 cascaded_expander;
934 #define IPR_PHY_LINK_RATE_MASK 0x0F
937 }__attribute__((packed, aligned (4)));
939 struct ipr_hostrcb64_config_element {
942 #define IPR_DESCRIPTOR_MASK 0xC0
943 #define IPR_DESCRIPTOR_SIS64 0x00
953 }__attribute__((packed, aligned (8)));
955 struct ipr_hostrcb_fabric_desc {
958 u8 cascaded_expander;
961 #define IPR_PATH_ACTIVE_MASK 0xC0
962 #define IPR_PATH_NO_INFO 0x00
963 #define IPR_PATH_ACTIVE 0x40
964 #define IPR_PATH_NOT_ACTIVE 0x80
966 #define IPR_PATH_STATE_MASK 0x0F
967 #define IPR_PATH_STATE_NO_INFO 0x00
968 #define IPR_PATH_HEALTHY 0x01
969 #define IPR_PATH_DEGRADED 0x02
970 #define IPR_PATH_FAILED 0x03
973 struct ipr_hostrcb_config_element elem[1];
974 }__attribute__((packed, aligned (4)));
976 struct ipr_hostrcb64_fabric_desc {
987 struct ipr_hostrcb64_config_element elem[1];
988 }__attribute__((packed, aligned (8)));
990 #define for_each_fabric_cfg(fabric, cfg) \
991 for (cfg = (fabric)->elem; \
992 cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \
995 struct ipr_hostrcb_type_20_error {
996 u8 failure_reason[64];
999 struct ipr_hostrcb_fabric_desc desc[1];
1000 }__attribute__((packed, aligned (4)));
1002 struct ipr_hostrcb_type_30_error {
1003 u8 failure_reason[64];
1006 struct ipr_hostrcb64_fabric_desc desc[1];
1007 }__attribute__((packed, aligned (4)));
1009 struct ipr_hostrcb_error {
1011 struct ipr_res_addr fd_res_addr;
1012 __be32 fd_res_handle;
1015 struct ipr_hostrcb_type_ff_error type_ff_error;
1016 struct ipr_hostrcb_type_01_error type_01_error;
1017 struct ipr_hostrcb_type_02_error type_02_error;
1018 struct ipr_hostrcb_type_03_error type_03_error;
1019 struct ipr_hostrcb_type_04_error type_04_error;
1020 struct ipr_hostrcb_type_07_error type_07_error;
1021 struct ipr_hostrcb_type_12_error type_12_error;
1022 struct ipr_hostrcb_type_13_error type_13_error;
1023 struct ipr_hostrcb_type_14_error type_14_error;
1024 struct ipr_hostrcb_type_17_error type_17_error;
1025 struct ipr_hostrcb_type_20_error type_20_error;
1027 }__attribute__((packed, aligned (4)));
1029 struct ipr_hostrcb64_error {
1031 __be32 ioa_fw_level;
1032 __be32 fd_res_handle;
1040 struct ipr_hostrcb_type_ff_error type_ff_error;
1041 struct ipr_hostrcb_type_12_error type_12_error;
1042 struct ipr_hostrcb_type_17_error type_17_error;
1043 struct ipr_hostrcb_type_23_error type_23_error;
1044 struct ipr_hostrcb_type_24_error type_24_error;
1045 struct ipr_hostrcb_type_30_error type_30_error;
1047 }__attribute__((packed, aligned (8)));
1049 struct ipr_hostrcb_raw {
1050 __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
1051 }__attribute__((packed, aligned (4)));
1055 #define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1
1056 #define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2
1059 #define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00
1060 #define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01
1061 #define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02
1062 #define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10
1063 #define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11
1065 u8 notifications_lost;
1066 #define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0
1067 #define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80
1070 #define IPR_HOSTRCB_INTERNAL_OPER 0x80
1071 #define IPR_HOSTRCB_ERR_RESP_SENT 0x40
1074 #define IPR_HOST_RCB_OVERLAY_ID_1 0x01
1075 #define IPR_HOST_RCB_OVERLAY_ID_2 0x02
1076 #define IPR_HOST_RCB_OVERLAY_ID_3 0x03
1077 #define IPR_HOST_RCB_OVERLAY_ID_4 0x04
1078 #define IPR_HOST_RCB_OVERLAY_ID_6 0x06
1079 #define IPR_HOST_RCB_OVERLAY_ID_7 0x07
1080 #define IPR_HOST_RCB_OVERLAY_ID_12 0x12
1081 #define IPR_HOST_RCB_OVERLAY_ID_13 0x13
1082 #define IPR_HOST_RCB_OVERLAY_ID_14 0x14
1083 #define IPR_HOST_RCB_OVERLAY_ID_16 0x16
1084 #define IPR_HOST_RCB_OVERLAY_ID_17 0x17
1085 #define IPR_HOST_RCB_OVERLAY_ID_20 0x20
1086 #define IPR_HOST_RCB_OVERLAY_ID_23 0x23
1087 #define IPR_HOST_RCB_OVERLAY_ID_24 0x24
1088 #define IPR_HOST_RCB_OVERLAY_ID_26 0x26
1089 #define IPR_HOST_RCB_OVERLAY_ID_30 0x30
1090 #define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF
1094 __be32 time_since_last_ioa_reset;
1099 struct ipr_hostrcb_error error;
1100 struct ipr_hostrcb64_error error64;
1101 struct ipr_hostrcb_cfg_ch_not ccn;
1102 struct ipr_hostrcb_raw raw;
1104 }__attribute__((packed, aligned (4)));
1106 struct ipr_hostrcb {
1107 struct ipr_hcam hcam;
1108 dma_addr_t hostrcb_dma;
1109 struct list_head queue;
1110 struct ipr_ioa_cfg *ioa_cfg;
1111 char rp_buffer[IPR_MAX_RES_PATH_LENGTH];
1114 /* IPR smart dump table structures */
1115 struct ipr_sdt_entry {
1121 #define IPR_SDT_ENDIAN 0x80
1122 #define IPR_SDT_VALID_ENTRY 0x20
1126 }__attribute__((packed, aligned (4)));
1128 struct ipr_sdt_header {
1131 __be32 num_entries_used;
1133 }__attribute__((packed, aligned (4)));
1136 struct ipr_sdt_header hdr;
1137 struct ipr_sdt_entry entry[IPR_NUM_SDT_ENTRIES];
1138 }__attribute__((packed, aligned (4)));
1141 struct ipr_sdt_header hdr;
1142 struct ipr_sdt_entry entry[1];
1143 }__attribute__((packed, aligned (4)));
1148 struct ipr_bus_attributes {
1156 struct ipr_sata_port {
1157 struct ipr_ioa_cfg *ioa_cfg;
1158 struct ata_port *ap;
1159 struct ipr_resource_entry *res;
1160 struct ipr_ioasa_gata ioasa;
1163 struct ipr_resource_entry {
1164 u8 needs_sync_complete:1;
1168 u8 resetting_device:1;
1170 u32 bus; /* AKA channel */
1171 u32 target; /* AKA id */
1173 #define IPR_ARRAY_VIRTUAL_BUS 0x1
1174 #define IPR_VSET_VIRTUAL_BUS 0x2
1175 #define IPR_IOAFP_VIRTUAL_BUS 0x3
1177 #define IPR_GET_RES_PHYS_LOC(res) \
1178 (((res)->bus << 24) | ((res)->target << 8) | (res)->lun)
1188 struct ipr_std_inq_data std_inq_data;
1192 struct scsi_lun dev_lun;
1195 struct ipr_ioa_cfg *ioa_cfg;
1196 struct scsi_device *sdev;
1197 struct ipr_sata_port *sata_port;
1198 struct list_head queue;
1199 }; /* struct ipr_resource_entry */
1201 struct ipr_resource_hdr {
1206 struct ipr_misc_cbs {
1207 struct ipr_ioa_vpd ioa_vpd;
1208 struct ipr_inquiry_page0 page0_data;
1209 struct ipr_inquiry_page3 page3_data;
1210 struct ipr_inquiry_cap cap;
1211 struct ipr_mode_pages mode_pages;
1212 struct ipr_supported_device supp_dev;
1215 struct ipr_interrupt_offsets {
1216 unsigned long set_interrupt_mask_reg;
1217 unsigned long clr_interrupt_mask_reg;
1218 unsigned long clr_interrupt_mask_reg32;
1219 unsigned long sense_interrupt_mask_reg;
1220 unsigned long sense_interrupt_mask_reg32;
1221 unsigned long clr_interrupt_reg;
1222 unsigned long clr_interrupt_reg32;
1224 unsigned long sense_interrupt_reg;
1225 unsigned long sense_interrupt_reg32;
1226 unsigned long ioarrin_reg;
1227 unsigned long sense_uproc_interrupt_reg;
1228 unsigned long sense_uproc_interrupt_reg32;
1229 unsigned long set_uproc_interrupt_reg;
1230 unsigned long set_uproc_interrupt_reg32;
1231 unsigned long clr_uproc_interrupt_reg;
1232 unsigned long clr_uproc_interrupt_reg32;
1234 unsigned long init_feedback_reg;
1236 unsigned long dump_addr_reg;
1237 unsigned long dump_data_reg;
1240 struct ipr_interrupts {
1241 void __iomem *set_interrupt_mask_reg;
1242 void __iomem *clr_interrupt_mask_reg;
1243 void __iomem *clr_interrupt_mask_reg32;
1244 void __iomem *sense_interrupt_mask_reg;
1245 void __iomem *sense_interrupt_mask_reg32;
1246 void __iomem *clr_interrupt_reg;
1247 void __iomem *clr_interrupt_reg32;
1249 void __iomem *sense_interrupt_reg;
1250 void __iomem *sense_interrupt_reg32;
1251 void __iomem *ioarrin_reg;
1252 void __iomem *sense_uproc_interrupt_reg;
1253 void __iomem *sense_uproc_interrupt_reg32;
1254 void __iomem *set_uproc_interrupt_reg;
1255 void __iomem *set_uproc_interrupt_reg32;
1256 void __iomem *clr_uproc_interrupt_reg;
1257 void __iomem *clr_uproc_interrupt_reg32;
1259 void __iomem *init_feedback_reg;
1261 void __iomem *dump_addr_reg;
1262 void __iomem *dump_data_reg;
1265 struct ipr_chip_cfg_t {
1268 struct ipr_interrupt_offsets regs;
1275 #define IPR_USE_LSI 0x00
1276 #define IPR_USE_MSI 0x01
1278 #define IPR_SIS32 0x00
1279 #define IPR_SIS64 0x01
1280 const struct ipr_chip_cfg_t *cfg;
1283 enum ipr_shutdown_type {
1284 IPR_SHUTDOWN_NORMAL = 0x00,
1285 IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40,
1286 IPR_SHUTDOWN_ABBREV = 0x80,
1287 IPR_SHUTDOWN_NONE = 0x100
1290 struct ipr_trace_entry {
1296 #define IPR_TRACE_START 0x00
1297 #define IPR_TRACE_FINISH 0xff
1313 struct scatterlist scatterlist[1];
1316 enum ipr_sdt_state {
1324 /* Per-controller data */
1325 struct ipr_ioa_cfg {
1326 char eye_catcher[8];
1327 #define IPR_EYECATCHER "iprcfg"
1329 struct list_head queue;
1331 u8 allow_interrupts:1;
1332 u8 in_reset_reload:1;
1333 u8 in_ioa_bringdown:1;
1334 u8 ioa_unit_checked:1;
1338 u8 allow_ml_add_del:1;
1339 u8 needs_hard_reset:1;
1341 u8 needs_warm_reset:1;
1348 * Bitmaps for SIS64 generated target values
1350 unsigned long *target_ids;
1351 unsigned long *array_ids;
1352 unsigned long *vset_ids;
1354 u16 type; /* CCIN of the card */
1357 #define IPR_MAX_LOG_LEVEL 4
1358 #define IPR_DEFAULT_LOG_LEVEL 2
1360 #define IPR_NUM_TRACE_INDEX_BITS 8
1361 #define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS)
1362 #define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES)
1363 char trace_start[8];
1364 #define IPR_TRACE_START_LABEL "trace"
1365 struct ipr_trace_entry *trace;
1366 u32 trace_index:IPR_NUM_TRACE_INDEX_BITS;
1369 * Queue for free command blocks
1371 char ipr_free_label[8];
1372 #define IPR_FREEQ_LABEL "free-q"
1373 struct list_head free_q;
1376 * Queue for command blocks outstanding to the adapter
1378 char ipr_pending_label[8];
1379 #define IPR_PENDQ_LABEL "pend-q"
1380 struct list_head pending_q;
1382 char cfg_table_start[8];
1383 #define IPR_CFG_TBL_START "cfg"
1385 struct ipr_config_table *cfg_table;
1386 struct ipr_config_table64 *cfg_table64;
1388 dma_addr_t cfg_table_dma;
1390 u32 max_devs_supported;
1392 char resource_table_label[8];
1393 #define IPR_RES_TABLE_LABEL "res_tbl"
1394 struct ipr_resource_entry *res_entries;
1395 struct list_head free_res_q;
1396 struct list_head used_res_q;
1398 char ipr_hcam_label[8];
1399 #define IPR_HCAM_LABEL "hcams"
1400 struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS];
1401 dma_addr_t hostrcb_dma[IPR_NUM_HCAMS];
1402 struct list_head hostrcb_free_q;
1403 struct list_head hostrcb_pending_q;
1406 dma_addr_t host_rrq_dma;
1407 #define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc
1408 #define IPR_HRRQ_RESP_BIT_SET 0x00000002
1409 #define IPR_HRRQ_TOGGLE_BIT 0x00000001
1410 #define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2
1411 volatile __be32 *hrrq_start;
1412 volatile __be32 *hrrq_end;
1413 volatile __be32 *hrrq_curr;
1414 volatile u32 toggle_bit;
1416 struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES];
1418 unsigned int transop_timeout;
1419 const struct ipr_chip_cfg_t *chip_cfg;
1420 const struct ipr_chip_t *ipr_chip;
1422 void __iomem *hdw_dma_regs; /* iomapped PCI memory space */
1423 unsigned long hdw_dma_regs_pci; /* raw PCI memory space */
1424 void __iomem *ioa_mailbox;
1425 struct ipr_interrupts regs;
1427 u16 saved_pcix_cmd_reg;
1433 struct Scsi_Host *host;
1434 struct pci_dev *pdev;
1435 struct ipr_sglist *ucode_sglist;
1436 u8 saved_mode_page_len;
1438 struct work_struct work_q;
1440 wait_queue_head_t reset_wait_q;
1441 wait_queue_head_t msi_wait_q;
1443 struct ipr_dump *dump;
1444 enum ipr_sdt_state sdt_state;
1446 struct ipr_misc_cbs *vpd_cbs;
1447 dma_addr_t vpd_cbs_dma;
1449 struct pci_pool *ipr_cmd_pool;
1451 struct ipr_cmnd *reset_cmd;
1452 int (*reset) (struct ipr_cmnd *);
1454 struct ata_host ata_host;
1455 char ipr_cmd_label[8];
1456 #define IPR_CMD_LABEL "ipr_cmd"
1457 struct ipr_cmnd *ipr_cmnd_list[IPR_NUM_CMD_BLKS];
1458 dma_addr_t ipr_cmnd_list_dma[IPR_NUM_CMD_BLKS];
1459 }; /* struct ipr_ioa_cfg */
1462 struct ipr_ioarcb ioarcb;
1464 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
1465 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
1466 struct ipr_ata64_ioadl ata_ioadl;
1468 struct ipr_ioasa ioasa;
1469 struct list_head queue;
1470 struct scsi_cmnd *scsi_cmd;
1471 struct ata_queued_cmd *qc;
1472 struct completion completion;
1473 struct timer_list timer;
1474 void (*done) (struct ipr_cmnd *);
1475 int (*job_step) (struct ipr_cmnd *);
1476 int (*job_step_failed) (struct ipr_cmnd *);
1478 u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
1479 dma_addr_t sense_buffer_dma;
1480 unsigned short dma_use_sg;
1481 dma_addr_t dma_addr;
1482 struct ipr_cmnd *sibling;
1484 enum ipr_shutdown_type shutdown_type;
1485 struct ipr_hostrcb *hostrcb;
1486 unsigned long time_left;
1487 unsigned long scratch;
1488 struct ipr_resource_entry *res;
1489 struct scsi_device *sdev;
1492 struct ipr_ioa_cfg *ioa_cfg;
1495 struct ipr_ses_table_entry {
1496 char product_id[17];
1497 char compare_product_id_byte[17];
1498 u32 max_bus_speed_limit; /* MB/sec limit for this backplane */
1501 struct ipr_dump_header {
1503 #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1506 u32 first_entry_offset;
1508 #define IPR_DUMP_STATUS_SUCCESS 0
1509 #define IPR_DUMP_STATUS_QUAL_SUCCESS 2
1510 #define IPR_DUMP_STATUS_FAILED 0xffffffff
1512 #define IPR_DUMP_OS_LINUX 0x4C4E5558
1514 #define IPR_DUMP_DRIVER_NAME 0x49505232
1515 }__attribute__((packed, aligned (4)));
1517 struct ipr_dump_entry_header {
1519 #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1524 #define IPR_DUMP_DATA_TYPE_ASCII 0x41534349
1525 #define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41
1527 #define IPR_DUMP_IOA_DUMP_ID 0x494F4131
1528 #define IPR_DUMP_LOCATION_ID 0x4C4F4341
1529 #define IPR_DUMP_TRACE_ID 0x54524143
1530 #define IPR_DUMP_DRIVER_VERSION_ID 0x44525652
1531 #define IPR_DUMP_DRIVER_TYPE_ID 0x54595045
1532 #define IPR_DUMP_IOA_CTRL_BLK 0x494F4342
1533 #define IPR_DUMP_PEND_OPS 0x414F5053
1535 }__attribute__((packed, aligned (4)));
1537 struct ipr_dump_location_entry {
1538 struct ipr_dump_entry_header hdr;
1540 }__attribute__((packed));
1542 struct ipr_dump_trace_entry {
1543 struct ipr_dump_entry_header hdr;
1544 u32 trace[IPR_TRACE_SIZE / sizeof(u32)];
1545 }__attribute__((packed, aligned (4)));
1547 struct ipr_dump_version_entry {
1548 struct ipr_dump_entry_header hdr;
1549 u8 version[sizeof(IPR_DRIVER_VERSION)];
1552 struct ipr_dump_ioa_type_entry {
1553 struct ipr_dump_entry_header hdr;
1558 struct ipr_driver_dump {
1559 struct ipr_dump_header hdr;
1560 struct ipr_dump_version_entry version_entry;
1561 struct ipr_dump_location_entry location_entry;
1562 struct ipr_dump_ioa_type_entry ioa_type_entry;
1563 struct ipr_dump_trace_entry trace_entry;
1564 }__attribute__((packed));
1566 struct ipr_ioa_dump {
1567 struct ipr_dump_entry_header hdr;
1569 __be32 *ioa_data[IPR_MAX_NUM_DUMP_PAGES];
1571 u32 next_page_index;
1574 }__attribute__((packed, aligned (4)));
1578 struct ipr_ioa_cfg *ioa_cfg;
1579 struct ipr_driver_dump driver_dump;
1580 struct ipr_ioa_dump ioa_dump;
1583 struct ipr_error_table_t {
1590 struct ipr_software_inq_lid_info {
1592 __be32 timestamp[3];
1593 }__attribute__((packed, aligned (4)));
1595 struct ipr_ucode_image_header {
1596 __be32 header_length;
1597 __be32 lid_table_offset;
1600 u8 minor_release[2];
1602 char eyecatcher[16];
1604 struct ipr_software_inq_lid_info lid[1];
1605 }__attribute__((packed, aligned (4)));
1610 #define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; }
1612 #ifdef CONFIG_SCSI_IPR_TRACE
1613 #define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1614 #define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1616 #define ipr_create_trace_file(kobj, attr) 0
1617 #define ipr_remove_trace_file(kobj, attr) do { } while(0)
1620 #ifdef CONFIG_SCSI_IPR_DUMP
1621 #define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1622 #define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1624 #define ipr_create_dump_file(kobj, attr) 0
1625 #define ipr_remove_dump_file(kobj, attr) do { } while(0)
1629 * Error logging macros
1631 #define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__)
1632 #define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
1633 #define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
1635 #define ipr_res_printk(level, ioa_cfg, bus, target, lun, fmt, ...) \
1636 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1637 bus, target, lun, ##__VA_ARGS__)
1639 #define ipr_res_err(ioa_cfg, res, fmt, ...) \
1640 ipr_res_printk(KERN_ERR, ioa_cfg, (res)->bus, (res)->target, (res)->lun, fmt, ##__VA_ARGS__)
1642 #define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \
1643 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1644 (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__)
1646 #define ipr_ra_err(ioa_cfg, ra, fmt, ...) \
1647 ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__)
1649 #define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \
1651 if ((res).bus >= IPR_MAX_NUM_BUSES) { \
1652 ipr_err(fmt": unknown\n", ##__VA_ARGS__); \
1654 ipr_err(fmt": %d:%d:%d:%d\n", \
1655 ##__VA_ARGS__, (ioa_cfg)->host->host_no, \
1656 (res).bus, (res).target, (res).lun); \
1660 #define ipr_hcam_err(hostrcb, fmt, ...) \
1662 if (ipr_is_device(hostrcb)) { \
1663 if ((hostrcb)->ioa_cfg->sis64) { \
1664 printk(KERN_ERR IPR_NAME ": %s: " fmt, \
1665 ipr_format_resource_path(&hostrcb->hcam.u.error64.fd_res_path[0], \
1666 &hostrcb->rp_buffer[0]), \
1669 ipr_ra_err((hostrcb)->ioa_cfg, \
1670 (hostrcb)->hcam.u.error.fd_res_addr, \
1671 fmt, __VA_ARGS__); \
1674 dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, __VA_ARGS__); \
1678 #define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
1679 __FILE__, __func__, __LINE__)
1681 #define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __func__))
1682 #define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __func__))
1684 #define ipr_err_separator \
1685 ipr_err("----------------------------------------------------------\n")
1693 * ipr_is_ioa_resource - Determine if a resource is the IOA
1694 * @res: resource entry struct
1697 * 1 if IOA / 0 if not IOA
1699 static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
1701 return res->type == IPR_RES_TYPE_IOAFP;
1705 * ipr_is_af_dasd_device - Determine if a resource is an AF DASD
1706 * @res: resource entry struct
1709 * 1 if AF DASD / 0 if not AF DASD
1711 static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
1713 return res->type == IPR_RES_TYPE_AF_DASD ||
1714 res->type == IPR_RES_TYPE_REMOTE_AF_DASD;
1718 * ipr_is_vset_device - Determine if a resource is a VSET
1719 * @res: resource entry struct
1722 * 1 if VSET / 0 if not VSET
1724 static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
1726 return res->type == IPR_RES_TYPE_VOLUME_SET;
1730 * ipr_is_gscsi - Determine if a resource is a generic scsi resource
1731 * @res: resource entry struct
1734 * 1 if GSCSI / 0 if not GSCSI
1736 static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
1738 return res->type == IPR_RES_TYPE_GENERIC_SCSI;
1742 * ipr_is_scsi_disk - Determine if a resource is a SCSI disk
1743 * @res: resource entry struct
1746 * 1 if SCSI disk / 0 if not SCSI disk
1748 static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res)
1750 if (ipr_is_af_dasd_device(res) ||
1751 (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->std_inq_data)))
1758 * ipr_is_gata - Determine if a resource is a generic ATA resource
1759 * @res: resource entry struct
1762 * 1 if GATA / 0 if not GATA
1764 static inline int ipr_is_gata(struct ipr_resource_entry *res)
1766 return res->type == IPR_RES_TYPE_GENERIC_ATA;
1770 * ipr_is_naca_model - Determine if a resource is using NACA queueing model
1771 * @res: resource entry struct
1774 * 1 if NACA queueing model / 0 if not NACA queueing model
1776 static inline int ipr_is_naca_model(struct ipr_resource_entry *res)
1778 if (ipr_is_gscsi(res) && res->qmodel == IPR_QUEUE_NACA_MODEL)
1784 * ipr_is_device - Determine if the hostrcb structure is related to a device
1785 * @hostrcb: host resource control blocks struct
1788 * 1 if AF / 0 if not AF
1790 static inline int ipr_is_device(struct ipr_hostrcb *hostrcb)
1792 struct ipr_res_addr *res_addr;
1795 if (hostrcb->ioa_cfg->sis64) {
1796 res_path = &hostrcb->hcam.u.error64.fd_res_path[0];
1797 if ((res_path[0] == 0x00 || res_path[0] == 0x80 ||
1798 res_path[0] == 0x81) && res_path[2] != 0xFF)
1801 res_addr = &hostrcb->hcam.u.error.fd_res_addr;
1803 if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
1804 (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1)))
1811 * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2
1812 * @sdt_word: SDT address
1815 * 1 if format 2 / 0 if not
1817 static inline int ipr_sdt_is_fmt2(u32 sdt_word)
1819 u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word);
1822 case IPR_SDT_FMT2_BAR0_SEL:
1823 case IPR_SDT_FMT2_BAR1_SEL:
1824 case IPR_SDT_FMT2_BAR2_SEL:
1825 case IPR_SDT_FMT2_BAR3_SEL:
1826 case IPR_SDT_FMT2_BAR4_SEL:
1827 case IPR_SDT_FMT2_BAR5_SEL:
1828 case IPR_SDT_FMT2_EXP_ROM_SEL: