2 * ipr.h -- driver for IBM Power Linux RAID adapters
4 * Written By: Brian King <brking@us.ibm.com>, IBM Corporation
6 * Copyright (C) 2003, 2004 IBM Corporation
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 * Alan Cox <alan@lxorguk.ukuu.org.uk> - Removed several careless u32/dma_addr_t errors
23 * that broke 64bit platforms.
29 #include <asm/unaligned.h>
30 #include <linux/types.h>
31 #include <linux/completion.h>
32 #include <linux/libata.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <scsi/scsi.h>
36 #include <scsi/scsi_cmnd.h>
41 #define IPR_DRIVER_VERSION "2.5.1"
42 #define IPR_DRIVER_DATE "(August 10, 2010)"
45 * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
46 * ops per device for devices not running tagged command queuing.
47 * This can be adjusted at runtime through sysfs device attributes.
49 #define IPR_MAX_CMD_PER_LUN 6
50 #define IPR_MAX_CMD_PER_ATA_LUN 1
53 * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of
54 * ops the mid-layer can send to the adapter.
56 #define IPR_NUM_BASE_CMD_BLKS 100
58 #define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339
60 #define PCI_DEVICE_ID_IBM_CROC_FPGA_E2 0x033D
61 #define PCI_DEVICE_ID_IBM_CROC_ASIC_E2 0x034A
63 #define IPR_SUBS_DEV_ID_2780 0x0264
64 #define IPR_SUBS_DEV_ID_5702 0x0266
65 #define IPR_SUBS_DEV_ID_5703 0x0278
66 #define IPR_SUBS_DEV_ID_572E 0x028D
67 #define IPR_SUBS_DEV_ID_573E 0x02D3
68 #define IPR_SUBS_DEV_ID_573D 0x02D4
69 #define IPR_SUBS_DEV_ID_571A 0x02C0
70 #define IPR_SUBS_DEV_ID_571B 0x02BE
71 #define IPR_SUBS_DEV_ID_571E 0x02BF
72 #define IPR_SUBS_DEV_ID_571F 0x02D5
73 #define IPR_SUBS_DEV_ID_572A 0x02C1
74 #define IPR_SUBS_DEV_ID_572B 0x02C2
75 #define IPR_SUBS_DEV_ID_572F 0x02C3
76 #define IPR_SUBS_DEV_ID_574E 0x030A
77 #define IPR_SUBS_DEV_ID_575B 0x030D
78 #define IPR_SUBS_DEV_ID_575C 0x0338
79 #define IPR_SUBS_DEV_ID_57B3 0x033A
80 #define IPR_SUBS_DEV_ID_57B7 0x0360
81 #define IPR_SUBS_DEV_ID_57B8 0x02C2
83 #define IPR_SUBS_DEV_ID_57B4 0x033B
84 #define IPR_SUBS_DEV_ID_57B2 0x035F
85 #define IPR_SUBS_DEV_ID_57C6 0x0357
86 #define IPR_SUBS_DEV_ID_57CC 0x035C
88 #define IPR_SUBS_DEV_ID_57B5 0x033C
89 #define IPR_SUBS_DEV_ID_57CE 0x035E
90 #define IPR_SUBS_DEV_ID_57B1 0x0355
92 #define IPR_SUBS_DEV_ID_574D 0x0356
93 #define IPR_SUBS_DEV_ID_575D 0x035D
95 #define IPR_NAME "ipr"
100 #define IPR_RC_JOB_CONTINUE 1
101 #define IPR_RC_JOB_RETURN 2
106 #define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200
107 #define IPR_IOASC_NR_IOA_RESET_REQUIRED 0x02048000
108 #define IPR_IOASC_SYNC_REQUIRED 0x023f0000
109 #define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00
110 #define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000
111 #define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500
112 #define IPR_IOASC_IOASC_MASK 0xFFFFFF00
113 #define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF
114 #define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT 0x05240000
115 #define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000
116 #define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100
117 #define IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000
118 #define IPR_IOASC_BUS_WAS_RESET 0x06290000
119 #define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000
120 #define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000
122 #define IPR_FIRST_DRIVER_IOASC 0x10000000
123 #define IPR_IOASC_IOA_WAS_RESET 0x10000001
124 #define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002
126 /* Driver data flags */
127 #define IPR_USE_LONG_TRANSOP_TIMEOUT 0x00000001
128 #define IPR_USE_PCI_WARM_RESET 0x00000002
130 #define IPR_DEFAULT_MAX_ERROR_DUMP 984
131 #define IPR_NUM_LOG_HCAMS 2
132 #define IPR_NUM_CFG_CHG_HCAMS 2
133 #define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
135 #define IPR_MAX_SIS64_TARGETS_PER_BUS 1024
136 #define IPR_MAX_SIS64_LUNS_PER_TARGET 0xffffffff
138 #define IPR_MAX_NUM_TARGETS_PER_BUS 256
139 #define IPR_MAX_NUM_LUNS_PER_TARGET 256
140 #define IPR_MAX_NUM_VSET_LUNS_PER_TARGET 8
141 #define IPR_VSET_BUS 0xff
142 #define IPR_IOA_BUS 0xff
143 #define IPR_IOA_TARGET 0xff
144 #define IPR_IOA_LUN 0xff
145 #define IPR_MAX_NUM_BUSES 16
146 #define IPR_MAX_BUS_TO_SCAN IPR_MAX_NUM_BUSES
148 #define IPR_NUM_RESET_RELOAD_RETRIES 3
150 /* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */
151 #define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \
152 ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 4)
154 #define IPR_MAX_COMMANDS IPR_NUM_BASE_CMD_BLKS
155 #define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \
156 IPR_NUM_INTERNAL_CMD_BLKS)
158 #define IPR_MAX_PHYSICAL_DEVS 192
159 #define IPR_DEFAULT_SIS64_DEVS 1024
160 #define IPR_MAX_SIS64_DEVS 4096
162 #define IPR_MAX_SGLIST 64
163 #define IPR_IOA_MAX_SECTORS 32767
164 #define IPR_VSET_MAX_SECTORS 512
165 #define IPR_MAX_CDB_LEN 16
166 #define IPR_MAX_HRRQ_RETRIES 3
168 #define IPR_DEFAULT_BUS_WIDTH 16
169 #define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
170 #define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
171 #define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
172 #define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8))
174 #define IPR_IOA_RES_HANDLE 0xffffffff
175 #define IPR_INVALID_RES_HANDLE 0
176 #define IPR_IOA_RES_ADDR 0x00ffffff
181 #define IPR_QUERY_RSRC_STATE 0xC2
182 #define IPR_RESET_DEVICE 0xC3
183 #define IPR_RESET_TYPE_SELECT 0x80
184 #define IPR_LUN_RESET 0x40
185 #define IPR_TARGET_RESET 0x20
186 #define IPR_BUS_RESET 0x10
187 #define IPR_ATA_PHY_RESET 0x80
188 #define IPR_ID_HOST_RR_Q 0xC4
189 #define IPR_QUERY_IOA_CONFIG 0xC5
190 #define IPR_CANCEL_ALL_REQUESTS 0xCE
191 #define IPR_HOST_CONTROLLED_ASYNC 0xCF
192 #define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01
193 #define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02
194 #define IPR_SET_SUPPORTED_DEVICES 0xFB
195 #define IPR_SET_ALL_SUPPORTED_DEVICES 0x80
196 #define IPR_IOA_SHUTDOWN 0xF7
197 #define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05
202 #define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ)
203 #define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ)
204 #define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ)
205 #define IPR_DUAL_IOA_ABBR_SHUTDOWN_TO (2 * 60 * HZ)
206 #define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
207 #define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
208 #define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
209 #define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
210 #define IPR_WRITE_BUFFER_TIMEOUT (10 * 60 * HZ)
211 #define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ)
212 #define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ)
213 #define IPR_OPERATIONAL_TIMEOUT (5 * 60)
214 #define IPR_LONG_OPERATIONAL_TIMEOUT (12 * 60)
215 #define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ)
216 #define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10)
217 #define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ)
218 #define IPR_PCI_RESET_TIMEOUT (HZ / 2)
219 #define IPR_DUMP_TIMEOUT (15 * HZ)
224 #define IPR_VENDOR_ID_LEN 8
225 #define IPR_PROD_ID_LEN 16
226 #define IPR_SERIAL_NUM_LEN 8
231 #define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff
232 #define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000
233 #define IPR_FMT2_MKR_BAR_SEL_SHIFT 28
234 #define IPR_GET_FMT2_BAR_SEL(mbx) \
235 (((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT)
236 #define IPR_SDT_FMT2_BAR0_SEL 0x0
237 #define IPR_SDT_FMT2_BAR1_SEL 0x1
238 #define IPR_SDT_FMT2_BAR2_SEL 0x2
239 #define IPR_SDT_FMT2_BAR3_SEL 0x3
240 #define IPR_SDT_FMT2_BAR4_SEL 0x4
241 #define IPR_SDT_FMT2_BAR5_SEL 0x5
242 #define IPR_SDT_FMT2_EXP_ROM_SEL 0x8
243 #define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2
244 #define IPR_FMT3_SDT_READY_TO_USE 0xC4D4E3F3
245 #define IPR_DOORBELL 0x82800000
246 #define IPR_RUNTIME_RESET 0x40000000
248 #define IPR_IPL_INIT_MIN_STAGE_TIME 5
249 #define IPR_IPL_INIT_DEFAULT_STAGE_TIME 15
250 #define IPR_IPL_INIT_STAGE_UNKNOWN 0x0
251 #define IPR_IPL_INIT_STAGE_TRANSOP 0xB0000000
252 #define IPR_IPL_INIT_STAGE_MASK 0xff000000
253 #define IPR_IPL_INIT_STAGE_TIME_MASK 0x0000ffff
254 #define IPR_PCII_IPL_STAGE_CHANGE (0x80000000 >> 0)
256 #define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0)
257 #define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3)
258 #define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4)
259 #define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5)
260 #define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6)
261 #define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7)
262 #define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27)
263 #define IPR_PCII_MMIO_ERROR (0x80000000 >> 28)
264 #define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29)
265 #define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30)
266 #define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31)
268 #define IPR_PCII_ERROR_INTERRUPTS \
269 (IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \
270 IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR)
272 #define IPR_PCII_OPER_INTERRUPTS \
273 (IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER)
275 #define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7)
276 #define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9)
277 #define IPR_UPROCI_SIS64_START_BIST (0x80000000 >> 23)
279 #define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */
280 #define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */
285 #define IPR_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024)
286 #define IPR_NUM_SDT_ENTRIES 511
287 #define IPR_MAX_NUM_DUMP_PAGES ((IPR_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
292 #define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST
295 * Adapter interface types
298 struct ipr_res_addr {
303 #define IPR_GET_PHYS_LOC(res_addr) \
304 (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun)
305 }__attribute__((packed, aligned (4)));
307 struct ipr_std_inq_vpids {
308 u8 vendor_id[IPR_VENDOR_ID_LEN];
309 u8 product_id[IPR_PROD_ID_LEN];
310 }__attribute__((packed));
313 struct ipr_std_inq_vpids vpids;
314 u8 sn[IPR_SERIAL_NUM_LEN];
315 }__attribute__((packed));
320 }__attribute__((packed));
322 struct ipr_std_inq_data {
323 u8 peri_qual_dev_type;
324 #define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5)
325 #define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F)
327 u8 removeable_medium_rsvd;
328 #define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80
330 #define IPR_IS_DASD_DEVICE(std_inq) \
331 ((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \
332 !(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM))
334 #define IPR_IS_SES_DEVICE(std_inq) \
335 (IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE)
344 struct ipr_std_inq_vpids vpids;
346 u8 ros_rsvd_ram_rsvd[4];
348 u8 serial_num[IPR_SERIAL_NUM_LEN];
349 }__attribute__ ((packed));
351 #define IPR_RES_TYPE_AF_DASD 0x00
352 #define IPR_RES_TYPE_GENERIC_SCSI 0x01
353 #define IPR_RES_TYPE_VOLUME_SET 0x02
354 #define IPR_RES_TYPE_REMOTE_AF_DASD 0x03
355 #define IPR_RES_TYPE_GENERIC_ATA 0x04
356 #define IPR_RES_TYPE_ARRAY 0x05
357 #define IPR_RES_TYPE_IOAFP 0xff
359 struct ipr_config_table_entry {
361 #define IPR_PROTO_SATA 0x02
362 #define IPR_PROTO_SATA_ATAPI 0x03
363 #define IPR_PROTO_SAS_STP 0x06
364 #define IPR_PROTO_SAS_STP_ATAPI 0x07
367 #define IPR_IS_IOA_RESOURCE 0x80
370 #define IPR_QUEUEING_MODEL(res) ((((res)->flags) & 0x70) >> 4)
371 #define IPR_QUEUE_FROZEN_MODEL 0
372 #define IPR_QUEUE_NACA_MODEL 1
374 struct ipr_res_addr res_addr;
377 struct ipr_std_inq_data std_inq_data;
378 }__attribute__ ((packed, aligned (4)));
380 struct ipr_config_table_entry64 {
387 #define IPR_QUEUEING_MODEL64(res) ((((res)->res_flags) & 0x7000) >> 12)
394 #define IPR_MAX_RES_PATH_LENGTH 24
396 struct ipr_std_inq_data std_inq_data;
398 __be64 reserved3[2]; // description text
400 }__attribute__ ((packed, aligned (8)));
402 struct ipr_config_table_hdr {
405 #define IPR_UCODE_DOWNLOAD_REQ 0x10
407 }__attribute__((packed, aligned (4)));
409 struct ipr_config_table_hdr64 {
414 }__attribute__((packed, aligned (4)));
416 struct ipr_config_table {
417 struct ipr_config_table_hdr hdr;
418 struct ipr_config_table_entry dev[0];
419 }__attribute__((packed, aligned (4)));
421 struct ipr_config_table64 {
422 struct ipr_config_table_hdr64 hdr64;
423 struct ipr_config_table_entry64 dev[0];
424 }__attribute__((packed, aligned (8)));
426 struct ipr_config_table_entry_wrapper {
428 struct ipr_config_table_entry *cfgte;
429 struct ipr_config_table_entry64 *cfgte64;
433 struct ipr_hostrcb_cfg_ch_not {
435 struct ipr_config_table_entry cfgte;
436 struct ipr_config_table_entry64 cfgte64;
439 }__attribute__((packed, aligned (4)));
441 struct ipr_supported_device {
445 struct ipr_std_inq_vpids vpids;
447 }__attribute__((packed, aligned (4)));
449 /* Command packet structure */
451 __be16 reserved; /* Reserved by IOA */
453 #define IPR_RQTYPE_SCSICDB 0x00
454 #define IPR_RQTYPE_IOACMD 0x01
455 #define IPR_RQTYPE_HCAM 0x02
456 #define IPR_RQTYPE_ATA_PASSTHRU 0x04
461 #define IPR_FLAGS_HI_WRITE_NOT_READ 0x80
462 #define IPR_FLAGS_HI_NO_ULEN_CHK 0x20
463 #define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10
464 #define IPR_FLAGS_HI_SYNC_COMPLETE 0x08
465 #define IPR_FLAGS_HI_NO_LINK_DESC 0x04
468 #define IPR_FLAGS_LO_ALIGNED_BFR 0x20
469 #define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10
470 #define IPR_FLAGS_LO_UNTAGGED_TASK 0x00
471 #define IPR_FLAGS_LO_SIMPLE_TASK 0x02
472 #define IPR_FLAGS_LO_ORDERED_TASK 0x04
473 #define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06
474 #define IPR_FLAGS_LO_ACA_TASK 0x08
478 }__attribute__ ((packed, aligned(4)));
480 struct ipr_ioarcb_ata_regs { /* 22 bytes */
482 #define IPR_ATA_FLAG_PACKET_CMD 0x80
483 #define IPR_ATA_FLAG_XFER_TYPE_DMA 0x40
484 #define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION 0x20
502 }__attribute__ ((packed, aligned(4)));
504 struct ipr_ioadl_desc {
505 __be32 flags_and_data_len;
506 #define IPR_IOADL_FLAGS_MASK 0xff000000
507 #define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK)
508 #define IPR_IOADL_DATA_LEN_MASK 0x00ffffff
509 #define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK)
510 #define IPR_IOADL_FLAGS_READ 0x48000000
511 #define IPR_IOADL_FLAGS_READ_LAST 0x49000000
512 #define IPR_IOADL_FLAGS_WRITE 0x68000000
513 #define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000
514 #define IPR_IOADL_FLAGS_LAST 0x01000000
517 }__attribute__((packed, aligned (8)));
519 struct ipr_ioadl64_desc {
523 }__attribute__((packed, aligned (16)));
525 struct ipr_ata64_ioadl {
526 struct ipr_ioarcb_ata_regs regs;
528 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
529 }__attribute__((packed, aligned (16)));
531 struct ipr_ioarcb_add_data {
533 struct ipr_ioarcb_ata_regs regs;
534 struct ipr_ioadl_desc ioadl[5];
535 __be32 add_cmd_parms[10];
537 }__attribute__ ((packed, aligned (4)));
539 struct ipr_ioarcb_sis64_add_addr_ecb {
540 __be64 ioasa_host_pci_addr;
541 __be64 data_ioadl_addr;
543 __be32 ext_control_buf[4];
544 }__attribute__((packed, aligned (8)));
546 /* IOA Request Control Block 128 bytes */
549 __be32 ioarcb_host_pci_addr;
550 __be64 ioarcb_host_pci_addr64;
553 __be32 host_response_handle;
558 __be32 data_transfer_length;
559 __be32 read_data_transfer_length;
560 __be32 write_ioadl_addr;
562 __be32 read_ioadl_addr;
563 __be32 read_ioadl_len;
565 __be32 ioasa_host_pci_addr;
569 struct ipr_cmd_pkt cmd_pkt;
571 __be16 add_cmd_parms_offset;
572 __be16 add_cmd_parms_len;
575 struct ipr_ioarcb_add_data add_data;
576 struct ipr_ioarcb_sis64_add_addr_ecb sis64_addr_data;
579 }__attribute__((packed, aligned (4)));
581 struct ipr_ioasa_vset {
582 __be32 failing_lba_hi;
583 __be32 failing_lba_lo;
585 }__attribute__((packed, aligned (4)));
587 struct ipr_ioasa_af_dasd {
590 }__attribute__((packed, aligned (4)));
592 struct ipr_ioasa_gpdd {
597 }__attribute__((packed, aligned (4)));
599 struct ipr_ioasa_gata {
601 u8 nsect; /* Interrupt reason */
607 u8 alt_status; /* ATA CTL */
612 }__attribute__((packed, aligned (4)));
614 struct ipr_auto_sense {
615 __be16 auto_sense_len;
617 __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)];
620 struct ipr_ioasa_hdr {
622 #define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
623 #define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
624 #define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
625 #define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
627 __be16 ret_stat_len; /* Length of the returned IOASA */
629 __be16 avail_stat_len; /* Total Length of status available. */
631 __be32 residual_data_len; /* number of bytes in the host data */
632 /* buffers that were not used by the IOARCB command. */
635 #define IPR_NO_ILID 0
636 #define IPR_DRIVER_ILID 0xffffffff
640 __be32 fd_phys_locator;
642 __be32 fd_res_handle;
644 __be32 ioasc_specific; /* status code specific field */
645 #define IPR_ADDITIONAL_STATUS_FMT 0x80000000
646 #define IPR_AUTOSENSE_VALID 0x40000000
647 #define IPR_ATA_DEVICE_WAS_RESET 0x20000000
648 #define IPR_IOASC_SPECIFIC_MASK 0x00ffffff
649 #define IPR_FIELD_POINTER_VALID (0x80000000 >> 8)
650 #define IPR_FIELD_POINTER_MASK 0x0000ffff
652 }__attribute__((packed, aligned (4)));
655 struct ipr_ioasa_hdr hdr;
658 struct ipr_ioasa_vset vset;
659 struct ipr_ioasa_af_dasd dasd;
660 struct ipr_ioasa_gpdd gpdd;
661 struct ipr_ioasa_gata gata;
664 struct ipr_auto_sense auto_sense;
665 }__attribute__((packed, aligned (4)));
668 struct ipr_ioasa_hdr hdr;
672 struct ipr_ioasa_vset vset;
673 struct ipr_ioasa_af_dasd dasd;
674 struct ipr_ioasa_gpdd gpdd;
675 struct ipr_ioasa_gata gata;
678 struct ipr_auto_sense auto_sense;
679 }__attribute__((packed, aligned (4)));
681 struct ipr_mode_parm_hdr {
684 u8 device_spec_parms;
686 }__attribute__((packed));
688 struct ipr_mode_pages {
689 struct ipr_mode_parm_hdr hdr;
690 u8 data[255 - sizeof(struct ipr_mode_parm_hdr)];
691 }__attribute__((packed));
693 struct ipr_mode_page_hdr {
695 #define IPR_MODE_PAGE_PS 0x80
696 #define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F)
698 }__attribute__ ((packed));
700 struct ipr_dev_bus_entry {
701 struct ipr_res_addr res_addr;
703 #define IPR_SCSI_ATTR_ENABLE_QAS 0x80
704 #define IPR_SCSI_ATTR_DISABLE_QAS 0x40
705 #define IPR_SCSI_ATTR_QAS_MASK 0xC0
706 #define IPR_SCSI_ATTR_ENABLE_TM 0x20
707 #define IPR_SCSI_ATTR_NO_TERM_PWR 0x10
708 #define IPR_SCSI_ATTR_TM_SUPPORTED 0x08
709 #define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04
713 u8 extended_reset_delay;
714 #define IPR_EXTENDED_RESET_DELAY 7
716 __be32 max_xfer_rate;
721 }__attribute__((packed, aligned (4)));
723 struct ipr_mode_page28 {
724 struct ipr_mode_page_hdr hdr;
727 struct ipr_dev_bus_entry bus[0];
728 }__attribute__((packed));
730 struct ipr_mode_page24 {
731 struct ipr_mode_page_hdr hdr;
733 #define IPR_ENABLE_DUAL_IOA_AF 0x80
734 }__attribute__((packed));
737 struct ipr_std_inq_data std_inq_data;
738 u8 ascii_part_num[12];
740 u8 ascii_plant_code[4];
741 }__attribute__((packed));
743 struct ipr_inquiry_page3 {
744 u8 peri_qual_dev_type;
756 }__attribute__((packed));
758 struct ipr_inquiry_cap {
759 u8 peri_qual_dev_type;
767 #define IPR_CAP_DUAL_IOA_RAID 0x80
769 }__attribute__((packed));
771 #define IPR_INQUIRY_PAGE0_ENTRIES 20
772 struct ipr_inquiry_page0 {
773 u8 peri_qual_dev_type;
777 u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
778 }__attribute__((packed));
780 struct ipr_hostrcb_device_data_entry {
782 struct ipr_res_addr dev_res_addr;
783 struct ipr_vpd new_vpd;
784 struct ipr_vpd ioa_last_with_dev_vpd;
785 struct ipr_vpd cfc_last_with_dev_vpd;
787 }__attribute__((packed, aligned (4)));
789 struct ipr_hostrcb_device_data_entry_enhanced {
790 struct ipr_ext_vpd vpd;
792 struct ipr_res_addr dev_res_addr;
793 struct ipr_ext_vpd new_vpd;
795 struct ipr_ext_vpd ioa_last_with_dev_vpd;
796 struct ipr_ext_vpd cfc_last_with_dev_vpd;
797 }__attribute__((packed, aligned (4)));
799 struct ipr_hostrcb64_device_data_entry_enhanced {
800 struct ipr_ext_vpd vpd;
803 struct ipr_ext_vpd new_vpd;
805 struct ipr_ext_vpd ioa_last_with_dev_vpd;
806 struct ipr_ext_vpd cfc_last_with_dev_vpd;
807 }__attribute__((packed, aligned (4)));
809 struct ipr_hostrcb_array_data_entry {
811 struct ipr_res_addr expected_dev_res_addr;
812 struct ipr_res_addr dev_res_addr;
813 }__attribute__((packed, aligned (4)));
815 struct ipr_hostrcb64_array_data_entry {
816 struct ipr_ext_vpd vpd;
818 u8 expected_res_path[8];
820 }__attribute__((packed, aligned (4)));
822 struct ipr_hostrcb_array_data_entry_enhanced {
823 struct ipr_ext_vpd vpd;
825 struct ipr_res_addr expected_dev_res_addr;
826 struct ipr_res_addr dev_res_addr;
827 }__attribute__((packed, aligned (4)));
829 struct ipr_hostrcb_type_ff_error {
830 __be32 ioa_data[758];
831 }__attribute__((packed, aligned (4)));
833 struct ipr_hostrcb_type_01_error {
837 __be32 ioa_data[236];
838 }__attribute__((packed, aligned (4)));
840 struct ipr_hostrcb_type_02_error {
841 struct ipr_vpd ioa_vpd;
842 struct ipr_vpd cfc_vpd;
843 struct ipr_vpd ioa_last_attached_to_cfc_vpd;
844 struct ipr_vpd cfc_last_attached_to_ioa_vpd;
846 }__attribute__((packed, aligned (4)));
848 struct ipr_hostrcb_type_12_error {
849 struct ipr_ext_vpd ioa_vpd;
850 struct ipr_ext_vpd cfc_vpd;
851 struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd;
852 struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd;
854 }__attribute__((packed, aligned (4)));
856 struct ipr_hostrcb_type_03_error {
857 struct ipr_vpd ioa_vpd;
858 struct ipr_vpd cfc_vpd;
859 __be32 errors_detected;
860 __be32 errors_logged;
862 struct ipr_hostrcb_device_data_entry dev[3];
863 }__attribute__((packed, aligned (4)));
865 struct ipr_hostrcb_type_13_error {
866 struct ipr_ext_vpd ioa_vpd;
867 struct ipr_ext_vpd cfc_vpd;
868 __be32 errors_detected;
869 __be32 errors_logged;
870 struct ipr_hostrcb_device_data_entry_enhanced dev[3];
871 }__attribute__((packed, aligned (4)));
873 struct ipr_hostrcb_type_23_error {
874 struct ipr_ext_vpd ioa_vpd;
875 struct ipr_ext_vpd cfc_vpd;
876 __be32 errors_detected;
877 __be32 errors_logged;
878 struct ipr_hostrcb64_device_data_entry_enhanced dev[3];
879 }__attribute__((packed, aligned (4)));
881 struct ipr_hostrcb_type_04_error {
882 struct ipr_vpd ioa_vpd;
883 struct ipr_vpd cfc_vpd;
885 struct ipr_hostrcb_array_data_entry array_member[10];
886 __be32 exposed_mode_adn;
888 struct ipr_vpd incomp_dev_vpd;
890 struct ipr_hostrcb_array_data_entry array_member2[8];
891 struct ipr_res_addr last_func_vset_res_addr;
892 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
893 u8 protection_level[8];
894 }__attribute__((packed, aligned (4)));
896 struct ipr_hostrcb_type_14_error {
897 struct ipr_ext_vpd ioa_vpd;
898 struct ipr_ext_vpd cfc_vpd;
899 __be32 exposed_mode_adn;
901 struct ipr_res_addr last_func_vset_res_addr;
902 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
903 u8 protection_level[8];
905 struct ipr_hostrcb_array_data_entry_enhanced array_member[18];
906 }__attribute__((packed, aligned (4)));
908 struct ipr_hostrcb_type_24_error {
909 struct ipr_ext_vpd ioa_vpd;
910 struct ipr_ext_vpd cfc_vpd;
913 #define IPR_INVALID_ARRAY_DEV_NUM 0xff
916 u8 protection_level[8];
917 struct ipr_ext_vpd array_vpd;
921 struct ipr_hostrcb64_array_data_entry array_member[32];
922 }__attribute__((packed, aligned (4)));
924 struct ipr_hostrcb_type_07_error {
925 u8 failure_reason[64];
928 }__attribute__((packed, aligned (4)));
930 struct ipr_hostrcb_type_17_error {
931 u8 failure_reason[64];
932 struct ipr_ext_vpd vpd;
934 }__attribute__((packed, aligned (4)));
936 struct ipr_hostrcb_config_element {
938 #define IPR_PATH_CFG_TYPE_MASK 0xF0
939 #define IPR_PATH_CFG_NOT_EXIST 0x00
940 #define IPR_PATH_CFG_IOA_PORT 0x10
941 #define IPR_PATH_CFG_EXP_PORT 0x20
942 #define IPR_PATH_CFG_DEVICE_PORT 0x30
943 #define IPR_PATH_CFG_DEVICE_LUN 0x40
945 #define IPR_PATH_CFG_STATUS_MASK 0x0F
946 #define IPR_PATH_CFG_NO_PROB 0x00
947 #define IPR_PATH_CFG_DEGRADED 0x01
948 #define IPR_PATH_CFG_FAILED 0x02
949 #define IPR_PATH_CFG_SUSPECT 0x03
950 #define IPR_PATH_NOT_DETECTED 0x04
951 #define IPR_PATH_INCORRECT_CONN 0x05
953 u8 cascaded_expander;
956 #define IPR_PHY_LINK_RATE_MASK 0x0F
959 }__attribute__((packed, aligned (4)));
961 struct ipr_hostrcb64_config_element {
964 #define IPR_DESCRIPTOR_MASK 0xC0
965 #define IPR_DESCRIPTOR_SIS64 0x00
975 }__attribute__((packed, aligned (8)));
977 struct ipr_hostrcb_fabric_desc {
980 u8 cascaded_expander;
983 #define IPR_PATH_ACTIVE_MASK 0xC0
984 #define IPR_PATH_NO_INFO 0x00
985 #define IPR_PATH_ACTIVE 0x40
986 #define IPR_PATH_NOT_ACTIVE 0x80
988 #define IPR_PATH_STATE_MASK 0x0F
989 #define IPR_PATH_STATE_NO_INFO 0x00
990 #define IPR_PATH_HEALTHY 0x01
991 #define IPR_PATH_DEGRADED 0x02
992 #define IPR_PATH_FAILED 0x03
995 struct ipr_hostrcb_config_element elem[1];
996 }__attribute__((packed, aligned (4)));
998 struct ipr_hostrcb64_fabric_desc {
1009 struct ipr_hostrcb64_config_element elem[1];
1010 }__attribute__((packed, aligned (8)));
1012 #define for_each_fabric_cfg(fabric, cfg) \
1013 for (cfg = (fabric)->elem; \
1014 cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \
1017 struct ipr_hostrcb_type_20_error {
1018 u8 failure_reason[64];
1021 struct ipr_hostrcb_fabric_desc desc[1];
1022 }__attribute__((packed, aligned (4)));
1024 struct ipr_hostrcb_type_30_error {
1025 u8 failure_reason[64];
1028 struct ipr_hostrcb64_fabric_desc desc[1];
1029 }__attribute__((packed, aligned (4)));
1031 struct ipr_hostrcb_error {
1033 struct ipr_res_addr fd_res_addr;
1034 __be32 fd_res_handle;
1037 struct ipr_hostrcb_type_ff_error type_ff_error;
1038 struct ipr_hostrcb_type_01_error type_01_error;
1039 struct ipr_hostrcb_type_02_error type_02_error;
1040 struct ipr_hostrcb_type_03_error type_03_error;
1041 struct ipr_hostrcb_type_04_error type_04_error;
1042 struct ipr_hostrcb_type_07_error type_07_error;
1043 struct ipr_hostrcb_type_12_error type_12_error;
1044 struct ipr_hostrcb_type_13_error type_13_error;
1045 struct ipr_hostrcb_type_14_error type_14_error;
1046 struct ipr_hostrcb_type_17_error type_17_error;
1047 struct ipr_hostrcb_type_20_error type_20_error;
1049 }__attribute__((packed, aligned (4)));
1051 struct ipr_hostrcb64_error {
1053 __be32 ioa_fw_level;
1054 __be32 fd_res_handle;
1062 struct ipr_hostrcb_type_ff_error type_ff_error;
1063 struct ipr_hostrcb_type_12_error type_12_error;
1064 struct ipr_hostrcb_type_17_error type_17_error;
1065 struct ipr_hostrcb_type_23_error type_23_error;
1066 struct ipr_hostrcb_type_24_error type_24_error;
1067 struct ipr_hostrcb_type_30_error type_30_error;
1069 }__attribute__((packed, aligned (8)));
1071 struct ipr_hostrcb_raw {
1072 __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
1073 }__attribute__((packed, aligned (4)));
1077 #define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1
1078 #define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2
1081 #define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00
1082 #define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01
1083 #define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02
1084 #define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10
1085 #define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11
1087 u8 notifications_lost;
1088 #define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0
1089 #define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80
1092 #define IPR_HOSTRCB_INTERNAL_OPER 0x80
1093 #define IPR_HOSTRCB_ERR_RESP_SENT 0x40
1096 #define IPR_HOST_RCB_OVERLAY_ID_1 0x01
1097 #define IPR_HOST_RCB_OVERLAY_ID_2 0x02
1098 #define IPR_HOST_RCB_OVERLAY_ID_3 0x03
1099 #define IPR_HOST_RCB_OVERLAY_ID_4 0x04
1100 #define IPR_HOST_RCB_OVERLAY_ID_6 0x06
1101 #define IPR_HOST_RCB_OVERLAY_ID_7 0x07
1102 #define IPR_HOST_RCB_OVERLAY_ID_12 0x12
1103 #define IPR_HOST_RCB_OVERLAY_ID_13 0x13
1104 #define IPR_HOST_RCB_OVERLAY_ID_14 0x14
1105 #define IPR_HOST_RCB_OVERLAY_ID_16 0x16
1106 #define IPR_HOST_RCB_OVERLAY_ID_17 0x17
1107 #define IPR_HOST_RCB_OVERLAY_ID_20 0x20
1108 #define IPR_HOST_RCB_OVERLAY_ID_23 0x23
1109 #define IPR_HOST_RCB_OVERLAY_ID_24 0x24
1110 #define IPR_HOST_RCB_OVERLAY_ID_26 0x26
1111 #define IPR_HOST_RCB_OVERLAY_ID_30 0x30
1112 #define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF
1116 __be32 time_since_last_ioa_reset;
1121 struct ipr_hostrcb_error error;
1122 struct ipr_hostrcb64_error error64;
1123 struct ipr_hostrcb_cfg_ch_not ccn;
1124 struct ipr_hostrcb_raw raw;
1126 }__attribute__((packed, aligned (4)));
1128 struct ipr_hostrcb {
1129 struct ipr_hcam hcam;
1130 dma_addr_t hostrcb_dma;
1131 struct list_head queue;
1132 struct ipr_ioa_cfg *ioa_cfg;
1133 char rp_buffer[IPR_MAX_RES_PATH_LENGTH];
1136 /* IPR smart dump table structures */
1137 struct ipr_sdt_entry {
1143 #define IPR_SDT_ENDIAN 0x80
1144 #define IPR_SDT_VALID_ENTRY 0x20
1148 }__attribute__((packed, aligned (4)));
1150 struct ipr_sdt_header {
1153 __be32 num_entries_used;
1155 }__attribute__((packed, aligned (4)));
1158 struct ipr_sdt_header hdr;
1159 struct ipr_sdt_entry entry[IPR_NUM_SDT_ENTRIES];
1160 }__attribute__((packed, aligned (4)));
1163 struct ipr_sdt_header hdr;
1164 struct ipr_sdt_entry entry[1];
1165 }__attribute__((packed, aligned (4)));
1170 struct ipr_bus_attributes {
1178 struct ipr_sata_port {
1179 struct ipr_ioa_cfg *ioa_cfg;
1180 struct ata_port *ap;
1181 struct ipr_resource_entry *res;
1182 struct ipr_ioasa_gata ioasa;
1185 struct ipr_resource_entry {
1186 u8 needs_sync_complete:1;
1190 u8 resetting_device:1;
1192 u32 bus; /* AKA channel */
1193 u32 target; /* AKA id */
1195 #define IPR_ARRAY_VIRTUAL_BUS 0x1
1196 #define IPR_VSET_VIRTUAL_BUS 0x2
1197 #define IPR_IOAFP_VIRTUAL_BUS 0x3
1199 #define IPR_GET_RES_PHYS_LOC(res) \
1200 (((res)->bus << 24) | ((res)->target << 8) | (res)->lun)
1210 struct ipr_std_inq_data std_inq_data;
1215 struct scsi_lun dev_lun;
1218 struct ipr_ioa_cfg *ioa_cfg;
1219 struct scsi_device *sdev;
1220 struct ipr_sata_port *sata_port;
1221 struct list_head queue;
1222 }; /* struct ipr_resource_entry */
1224 struct ipr_resource_hdr {
1229 struct ipr_misc_cbs {
1230 struct ipr_ioa_vpd ioa_vpd;
1231 struct ipr_inquiry_page0 page0_data;
1232 struct ipr_inquiry_page3 page3_data;
1233 struct ipr_inquiry_cap cap;
1234 struct ipr_mode_pages mode_pages;
1235 struct ipr_supported_device supp_dev;
1238 struct ipr_interrupt_offsets {
1239 unsigned long set_interrupt_mask_reg;
1240 unsigned long clr_interrupt_mask_reg;
1241 unsigned long clr_interrupt_mask_reg32;
1242 unsigned long sense_interrupt_mask_reg;
1243 unsigned long sense_interrupt_mask_reg32;
1244 unsigned long clr_interrupt_reg;
1245 unsigned long clr_interrupt_reg32;
1247 unsigned long sense_interrupt_reg;
1248 unsigned long sense_interrupt_reg32;
1249 unsigned long ioarrin_reg;
1250 unsigned long sense_uproc_interrupt_reg;
1251 unsigned long sense_uproc_interrupt_reg32;
1252 unsigned long set_uproc_interrupt_reg;
1253 unsigned long set_uproc_interrupt_reg32;
1254 unsigned long clr_uproc_interrupt_reg;
1255 unsigned long clr_uproc_interrupt_reg32;
1257 unsigned long init_feedback_reg;
1259 unsigned long dump_addr_reg;
1260 unsigned long dump_data_reg;
1262 #define IPR_ENDIAN_SWAP_KEY 0x00080800
1263 unsigned long endian_swap_reg;
1266 struct ipr_interrupts {
1267 void __iomem *set_interrupt_mask_reg;
1268 void __iomem *clr_interrupt_mask_reg;
1269 void __iomem *clr_interrupt_mask_reg32;
1270 void __iomem *sense_interrupt_mask_reg;
1271 void __iomem *sense_interrupt_mask_reg32;
1272 void __iomem *clr_interrupt_reg;
1273 void __iomem *clr_interrupt_reg32;
1275 void __iomem *sense_interrupt_reg;
1276 void __iomem *sense_interrupt_reg32;
1277 void __iomem *ioarrin_reg;
1278 void __iomem *sense_uproc_interrupt_reg;
1279 void __iomem *sense_uproc_interrupt_reg32;
1280 void __iomem *set_uproc_interrupt_reg;
1281 void __iomem *set_uproc_interrupt_reg32;
1282 void __iomem *clr_uproc_interrupt_reg;
1283 void __iomem *clr_uproc_interrupt_reg32;
1285 void __iomem *init_feedback_reg;
1287 void __iomem *dump_addr_reg;
1288 void __iomem *dump_data_reg;
1290 void __iomem *endian_swap_reg;
1293 struct ipr_chip_cfg_t {
1296 struct ipr_interrupt_offsets regs;
1303 #define IPR_USE_LSI 0x00
1304 #define IPR_USE_MSI 0x01
1306 #define IPR_SIS32 0x00
1307 #define IPR_SIS64 0x01
1309 #define IPR_PCI_CFG 0x00
1310 #define IPR_MMIO 0x01
1311 const struct ipr_chip_cfg_t *cfg;
1314 enum ipr_shutdown_type {
1315 IPR_SHUTDOWN_NORMAL = 0x00,
1316 IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40,
1317 IPR_SHUTDOWN_ABBREV = 0x80,
1318 IPR_SHUTDOWN_NONE = 0x100
1321 struct ipr_trace_entry {
1327 #define IPR_TRACE_START 0x00
1328 #define IPR_TRACE_FINISH 0xff
1344 struct scatterlist scatterlist[1];
1347 enum ipr_sdt_state {
1355 /* Per-controller data */
1356 struct ipr_ioa_cfg {
1357 char eye_catcher[8];
1358 #define IPR_EYECATCHER "iprcfg"
1360 struct list_head queue;
1362 u8 allow_interrupts:1;
1363 u8 in_reset_reload:1;
1364 u8 in_ioa_bringdown:1;
1365 u8 ioa_unit_checked:1;
1369 u8 allow_ml_add_del:1;
1370 u8 needs_hard_reset:1;
1372 u8 needs_warm_reset:1;
1379 * Bitmaps for SIS64 generated target values
1381 unsigned long *target_ids;
1382 unsigned long *array_ids;
1383 unsigned long *vset_ids;
1385 u16 type; /* CCIN of the card */
1388 #define IPR_MAX_LOG_LEVEL 4
1389 #define IPR_DEFAULT_LOG_LEVEL 2
1391 #define IPR_NUM_TRACE_INDEX_BITS 8
1392 #define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS)
1393 #define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES)
1394 char trace_start[8];
1395 #define IPR_TRACE_START_LABEL "trace"
1396 struct ipr_trace_entry *trace;
1397 u32 trace_index:IPR_NUM_TRACE_INDEX_BITS;
1400 * Queue for free command blocks
1402 char ipr_free_label[8];
1403 #define IPR_FREEQ_LABEL "free-q"
1404 struct list_head free_q;
1407 * Queue for command blocks outstanding to the adapter
1409 char ipr_pending_label[8];
1410 #define IPR_PENDQ_LABEL "pend-q"
1411 struct list_head pending_q;
1413 char cfg_table_start[8];
1414 #define IPR_CFG_TBL_START "cfg"
1416 struct ipr_config_table *cfg_table;
1417 struct ipr_config_table64 *cfg_table64;
1419 dma_addr_t cfg_table_dma;
1421 u32 max_devs_supported;
1423 char resource_table_label[8];
1424 #define IPR_RES_TABLE_LABEL "res_tbl"
1425 struct ipr_resource_entry *res_entries;
1426 struct list_head free_res_q;
1427 struct list_head used_res_q;
1429 char ipr_hcam_label[8];
1430 #define IPR_HCAM_LABEL "hcams"
1431 struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS];
1432 dma_addr_t hostrcb_dma[IPR_NUM_HCAMS];
1433 struct list_head hostrcb_free_q;
1434 struct list_head hostrcb_pending_q;
1437 dma_addr_t host_rrq_dma;
1438 #define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc
1439 #define IPR_HRRQ_RESP_BIT_SET 0x00000002
1440 #define IPR_HRRQ_TOGGLE_BIT 0x00000001
1441 #define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2
1442 volatile __be32 *hrrq_start;
1443 volatile __be32 *hrrq_end;
1444 volatile __be32 *hrrq_curr;
1445 volatile u32 toggle_bit;
1447 struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES];
1449 unsigned int transop_timeout;
1450 const struct ipr_chip_cfg_t *chip_cfg;
1451 const struct ipr_chip_t *ipr_chip;
1453 void __iomem *hdw_dma_regs; /* iomapped PCI memory space */
1454 unsigned long hdw_dma_regs_pci; /* raw PCI memory space */
1455 void __iomem *ioa_mailbox;
1456 struct ipr_interrupts regs;
1458 u16 saved_pcix_cmd_reg;
1464 struct Scsi_Host *host;
1465 struct pci_dev *pdev;
1466 struct ipr_sglist *ucode_sglist;
1467 u8 saved_mode_page_len;
1469 struct work_struct work_q;
1471 wait_queue_head_t reset_wait_q;
1472 wait_queue_head_t msi_wait_q;
1474 struct ipr_dump *dump;
1475 enum ipr_sdt_state sdt_state;
1477 struct ipr_misc_cbs *vpd_cbs;
1478 dma_addr_t vpd_cbs_dma;
1480 struct pci_pool *ipr_cmd_pool;
1482 struct ipr_cmnd *reset_cmd;
1483 int (*reset) (struct ipr_cmnd *);
1485 struct ata_host ata_host;
1486 char ipr_cmd_label[8];
1487 #define IPR_CMD_LABEL "ipr_cmd"
1488 struct ipr_cmnd *ipr_cmnd_list[IPR_NUM_CMD_BLKS];
1489 dma_addr_t ipr_cmnd_list_dma[IPR_NUM_CMD_BLKS];
1490 }; /* struct ipr_ioa_cfg */
1493 struct ipr_ioarcb ioarcb;
1495 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
1496 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
1497 struct ipr_ata64_ioadl ata_ioadl;
1500 struct ipr_ioasa ioasa;
1501 struct ipr_ioasa64 ioasa64;
1503 struct list_head queue;
1504 struct scsi_cmnd *scsi_cmd;
1505 struct ata_queued_cmd *qc;
1506 struct completion completion;
1507 struct timer_list timer;
1508 void (*done) (struct ipr_cmnd *);
1509 int (*job_step) (struct ipr_cmnd *);
1510 int (*job_step_failed) (struct ipr_cmnd *);
1512 u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
1513 dma_addr_t sense_buffer_dma;
1514 unsigned short dma_use_sg;
1515 dma_addr_t dma_addr;
1516 struct ipr_cmnd *sibling;
1518 enum ipr_shutdown_type shutdown_type;
1519 struct ipr_hostrcb *hostrcb;
1520 unsigned long time_left;
1521 unsigned long scratch;
1522 struct ipr_resource_entry *res;
1523 struct scsi_device *sdev;
1526 struct ipr_ioa_cfg *ioa_cfg;
1529 struct ipr_ses_table_entry {
1530 char product_id[17];
1531 char compare_product_id_byte[17];
1532 u32 max_bus_speed_limit; /* MB/sec limit for this backplane */
1535 struct ipr_dump_header {
1537 #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1540 u32 first_entry_offset;
1542 #define IPR_DUMP_STATUS_SUCCESS 0
1543 #define IPR_DUMP_STATUS_QUAL_SUCCESS 2
1544 #define IPR_DUMP_STATUS_FAILED 0xffffffff
1546 #define IPR_DUMP_OS_LINUX 0x4C4E5558
1548 #define IPR_DUMP_DRIVER_NAME 0x49505232
1549 }__attribute__((packed, aligned (4)));
1551 struct ipr_dump_entry_header {
1553 #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1558 #define IPR_DUMP_DATA_TYPE_ASCII 0x41534349
1559 #define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41
1561 #define IPR_DUMP_IOA_DUMP_ID 0x494F4131
1562 #define IPR_DUMP_LOCATION_ID 0x4C4F4341
1563 #define IPR_DUMP_TRACE_ID 0x54524143
1564 #define IPR_DUMP_DRIVER_VERSION_ID 0x44525652
1565 #define IPR_DUMP_DRIVER_TYPE_ID 0x54595045
1566 #define IPR_DUMP_IOA_CTRL_BLK 0x494F4342
1567 #define IPR_DUMP_PEND_OPS 0x414F5053
1569 }__attribute__((packed, aligned (4)));
1571 struct ipr_dump_location_entry {
1572 struct ipr_dump_entry_header hdr;
1574 }__attribute__((packed));
1576 struct ipr_dump_trace_entry {
1577 struct ipr_dump_entry_header hdr;
1578 u32 trace[IPR_TRACE_SIZE / sizeof(u32)];
1579 }__attribute__((packed, aligned (4)));
1581 struct ipr_dump_version_entry {
1582 struct ipr_dump_entry_header hdr;
1583 u8 version[sizeof(IPR_DRIVER_VERSION)];
1586 struct ipr_dump_ioa_type_entry {
1587 struct ipr_dump_entry_header hdr;
1592 struct ipr_driver_dump {
1593 struct ipr_dump_header hdr;
1594 struct ipr_dump_version_entry version_entry;
1595 struct ipr_dump_location_entry location_entry;
1596 struct ipr_dump_ioa_type_entry ioa_type_entry;
1597 struct ipr_dump_trace_entry trace_entry;
1598 }__attribute__((packed));
1600 struct ipr_ioa_dump {
1601 struct ipr_dump_entry_header hdr;
1603 __be32 *ioa_data[IPR_MAX_NUM_DUMP_PAGES];
1605 u32 next_page_index;
1608 }__attribute__((packed, aligned (4)));
1612 struct ipr_ioa_cfg *ioa_cfg;
1613 struct ipr_driver_dump driver_dump;
1614 struct ipr_ioa_dump ioa_dump;
1617 struct ipr_error_table_t {
1624 struct ipr_software_inq_lid_info {
1626 __be32 timestamp[3];
1627 }__attribute__((packed, aligned (4)));
1629 struct ipr_ucode_image_header {
1630 __be32 header_length;
1631 __be32 lid_table_offset;
1634 u8 minor_release[2];
1636 char eyecatcher[16];
1638 struct ipr_software_inq_lid_info lid[1];
1639 }__attribute__((packed, aligned (4)));
1644 #define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; }
1646 #ifdef CONFIG_SCSI_IPR_TRACE
1647 #define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1648 #define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1650 #define ipr_create_trace_file(kobj, attr) 0
1651 #define ipr_remove_trace_file(kobj, attr) do { } while(0)
1654 #ifdef CONFIG_SCSI_IPR_DUMP
1655 #define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1656 #define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1658 #define ipr_create_dump_file(kobj, attr) 0
1659 #define ipr_remove_dump_file(kobj, attr) do { } while(0)
1663 * Error logging macros
1665 #define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__)
1666 #define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
1667 #define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
1669 #define ipr_res_printk(level, ioa_cfg, bus, target, lun, fmt, ...) \
1670 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1671 bus, target, lun, ##__VA_ARGS__)
1673 #define ipr_res_err(ioa_cfg, res, fmt, ...) \
1674 ipr_res_printk(KERN_ERR, ioa_cfg, (res)->bus, (res)->target, (res)->lun, fmt, ##__VA_ARGS__)
1676 #define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \
1677 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1678 (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__)
1680 #define ipr_ra_err(ioa_cfg, ra, fmt, ...) \
1681 ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__)
1683 #define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \
1685 if ((res).bus >= IPR_MAX_NUM_BUSES) { \
1686 ipr_err(fmt": unknown\n", ##__VA_ARGS__); \
1688 ipr_err(fmt": %d:%d:%d:%d\n", \
1689 ##__VA_ARGS__, (ioa_cfg)->host->host_no, \
1690 (res).bus, (res).target, (res).lun); \
1694 #define ipr_hcam_err(hostrcb, fmt, ...) \
1696 if (ipr_is_device(hostrcb)) { \
1697 if ((hostrcb)->ioa_cfg->sis64) { \
1698 printk(KERN_ERR IPR_NAME ": %s: " fmt, \
1699 ipr_format_res_path(hostrcb->hcam.u.error64.fd_res_path, \
1700 hostrcb->rp_buffer, \
1701 sizeof(hostrcb->rp_buffer)), \
1704 ipr_ra_err((hostrcb)->ioa_cfg, \
1705 (hostrcb)->hcam.u.error.fd_res_addr, \
1706 fmt, __VA_ARGS__); \
1709 dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, __VA_ARGS__); \
1713 #define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
1714 __FILE__, __func__, __LINE__)
1716 #define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __func__))
1717 #define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __func__))
1719 #define ipr_err_separator \
1720 ipr_err("----------------------------------------------------------\n")
1728 * ipr_is_ioa_resource - Determine if a resource is the IOA
1729 * @res: resource entry struct
1732 * 1 if IOA / 0 if not IOA
1734 static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
1736 return res->type == IPR_RES_TYPE_IOAFP;
1740 * ipr_is_af_dasd_device - Determine if a resource is an AF DASD
1741 * @res: resource entry struct
1744 * 1 if AF DASD / 0 if not AF DASD
1746 static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
1748 return res->type == IPR_RES_TYPE_AF_DASD ||
1749 res->type == IPR_RES_TYPE_REMOTE_AF_DASD;
1753 * ipr_is_vset_device - Determine if a resource is a VSET
1754 * @res: resource entry struct
1757 * 1 if VSET / 0 if not VSET
1759 static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
1761 return res->type == IPR_RES_TYPE_VOLUME_SET;
1765 * ipr_is_gscsi - Determine if a resource is a generic scsi resource
1766 * @res: resource entry struct
1769 * 1 if GSCSI / 0 if not GSCSI
1771 static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
1773 return res->type == IPR_RES_TYPE_GENERIC_SCSI;
1777 * ipr_is_scsi_disk - Determine if a resource is a SCSI disk
1778 * @res: resource entry struct
1781 * 1 if SCSI disk / 0 if not SCSI disk
1783 static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res)
1785 if (ipr_is_af_dasd_device(res) ||
1786 (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->std_inq_data)))
1793 * ipr_is_gata - Determine if a resource is a generic ATA resource
1794 * @res: resource entry struct
1797 * 1 if GATA / 0 if not GATA
1799 static inline int ipr_is_gata(struct ipr_resource_entry *res)
1801 return res->type == IPR_RES_TYPE_GENERIC_ATA;
1805 * ipr_is_naca_model - Determine if a resource is using NACA queueing model
1806 * @res: resource entry struct
1809 * 1 if NACA queueing model / 0 if not NACA queueing model
1811 static inline int ipr_is_naca_model(struct ipr_resource_entry *res)
1813 if (ipr_is_gscsi(res) && res->qmodel == IPR_QUEUE_NACA_MODEL)
1819 * ipr_is_device - Determine if the hostrcb structure is related to a device
1820 * @hostrcb: host resource control blocks struct
1823 * 1 if AF / 0 if not AF
1825 static inline int ipr_is_device(struct ipr_hostrcb *hostrcb)
1827 struct ipr_res_addr *res_addr;
1830 if (hostrcb->ioa_cfg->sis64) {
1831 res_path = &hostrcb->hcam.u.error64.fd_res_path[0];
1832 if ((res_path[0] == 0x00 || res_path[0] == 0x80 ||
1833 res_path[0] == 0x81) && res_path[2] != 0xFF)
1836 res_addr = &hostrcb->hcam.u.error.fd_res_addr;
1838 if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
1839 (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1)))
1846 * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2
1847 * @sdt_word: SDT address
1850 * 1 if format 2 / 0 if not
1852 static inline int ipr_sdt_is_fmt2(u32 sdt_word)
1854 u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word);
1857 case IPR_SDT_FMT2_BAR0_SEL:
1858 case IPR_SDT_FMT2_BAR1_SEL:
1859 case IPR_SDT_FMT2_BAR2_SEL:
1860 case IPR_SDT_FMT2_BAR3_SEL:
1861 case IPR_SDT_FMT2_BAR4_SEL:
1862 case IPR_SDT_FMT2_BAR5_SEL:
1863 case IPR_SDT_FMT2_EXP_ROM_SEL:
1871 static inline void writeq(u64 val, void __iomem *addr)
1873 writel(((u32) (val >> 32)), addr);
1874 writel(((u32) (val)), (addr + 4));