2 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
6 * Linux driver for Brocade Fibre Channel Host Bus Adapter.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License (GPL) Version 2 as
10 * published by the Free Software Foundation
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
19 #include "bfa_modules.h"
22 BFA_TRC_FILE(HAL, CORE);
25 * BFA module list terminated by NULL
27 static struct bfa_module_s *hal_mods[] = {
41 * Message handlers for various modules.
43 static bfa_isr_func_t bfa_isrs[BFI_MC_MAX] = {
44 bfa_isr_unhandled, /* NONE */
45 bfa_isr_unhandled, /* BFI_MC_IOC */
46 bfa_fcdiag_intr, /* BFI_MC_DIAG */
47 bfa_isr_unhandled, /* BFI_MC_FLASH */
48 bfa_isr_unhandled, /* BFI_MC_CEE */
49 bfa_fcport_isr, /* BFI_MC_FCPORT */
50 bfa_isr_unhandled, /* BFI_MC_IOCFC */
51 bfa_isr_unhandled, /* BFI_MC_LL */
52 bfa_uf_isr, /* BFI_MC_UF */
53 bfa_fcxp_isr, /* BFI_MC_FCXP */
54 bfa_lps_isr, /* BFI_MC_LPS */
55 bfa_rport_isr, /* BFI_MC_RPORT */
56 bfa_itn_isr, /* BFI_MC_ITN */
57 bfa_isr_unhandled, /* BFI_MC_IOIM_READ */
58 bfa_isr_unhandled, /* BFI_MC_IOIM_WRITE */
59 bfa_isr_unhandled, /* BFI_MC_IOIM_IO */
60 bfa_ioim_isr, /* BFI_MC_IOIM */
61 bfa_ioim_good_comp_isr, /* BFI_MC_IOIM_IOCOM */
62 bfa_tskim_isr, /* BFI_MC_TSKIM */
63 bfa_isr_unhandled, /* BFI_MC_SBOOT */
64 bfa_isr_unhandled, /* BFI_MC_IPFC */
65 bfa_isr_unhandled, /* BFI_MC_PORT */
66 bfa_isr_unhandled, /* --------- */
67 bfa_isr_unhandled, /* --------- */
68 bfa_isr_unhandled, /* --------- */
69 bfa_isr_unhandled, /* --------- */
70 bfa_isr_unhandled, /* --------- */
71 bfa_isr_unhandled, /* --------- */
72 bfa_isr_unhandled, /* --------- */
73 bfa_isr_unhandled, /* --------- */
74 bfa_isr_unhandled, /* --------- */
75 bfa_isr_unhandled, /* --------- */
78 * Message handlers for mailbox command classes
80 static bfa_ioc_mbox_mcfunc_t bfa_mbox_isrs[BFI_MC_MAX] = {
82 NULL, /* BFI_MC_IOC */
83 NULL, /* BFI_MC_DIAG */
84 NULL, /* BFI_MC_FLASH */
85 NULL, /* BFI_MC_CEE */
86 NULL, /* BFI_MC_PORT */
87 bfa_iocfc_isr, /* BFI_MC_IOCFC */
94 bfa_com_port_attach(struct bfa_s *bfa)
96 struct bfa_port_s *port = &bfa->modules.port;
97 struct bfa_mem_dma_s *port_dma = BFA_MEM_PORT_DMA(bfa);
99 bfa_port_attach(port, &bfa->ioc, bfa, bfa->trcmod);
100 bfa_port_mem_claim(port, port_dma->kva_curp, port_dma->dma_curp);
107 bfa_com_ablk_attach(struct bfa_s *bfa)
109 struct bfa_ablk_s *ablk = &bfa->modules.ablk;
110 struct bfa_mem_dma_s *ablk_dma = BFA_MEM_ABLK_DMA(bfa);
112 bfa_ablk_attach(ablk, &bfa->ioc);
113 bfa_ablk_memclaim(ablk, ablk_dma->kva_curp, ablk_dma->dma_curp);
117 bfa_com_cee_attach(struct bfa_s *bfa)
119 struct bfa_cee_s *cee = &bfa->modules.cee;
120 struct bfa_mem_dma_s *cee_dma = BFA_MEM_CEE_DMA(bfa);
122 cee->trcmod = bfa->trcmod;
123 bfa_cee_attach(cee, &bfa->ioc, bfa);
124 bfa_cee_mem_claim(cee, cee_dma->kva_curp, cee_dma->dma_curp);
128 bfa_com_sfp_attach(struct bfa_s *bfa)
130 struct bfa_sfp_s *sfp = BFA_SFP_MOD(bfa);
131 struct bfa_mem_dma_s *sfp_dma = BFA_MEM_SFP_DMA(bfa);
133 bfa_sfp_attach(sfp, &bfa->ioc, bfa, bfa->trcmod);
134 bfa_sfp_memclaim(sfp, sfp_dma->kva_curp, sfp_dma->dma_curp);
138 bfa_com_flash_attach(struct bfa_s *bfa, bfa_boolean_t mincfg)
140 struct bfa_flash_s *flash = BFA_FLASH(bfa);
141 struct bfa_mem_dma_s *flash_dma = BFA_MEM_FLASH_DMA(bfa);
143 bfa_flash_attach(flash, &bfa->ioc, bfa, bfa->trcmod, mincfg);
144 bfa_flash_memclaim(flash, flash_dma->kva_curp,
145 flash_dma->dma_curp, mincfg);
149 bfa_com_diag_attach(struct bfa_s *bfa)
151 struct bfa_diag_s *diag = BFA_DIAG_MOD(bfa);
152 struct bfa_mem_dma_s *diag_dma = BFA_MEM_DIAG_DMA(bfa);
154 bfa_diag_attach(diag, &bfa->ioc, bfa, bfa_fcport_beacon, bfa->trcmod);
155 bfa_diag_memclaim(diag, diag_dma->kva_curp, diag_dma->dma_curp);
159 bfa_com_phy_attach(struct bfa_s *bfa, bfa_boolean_t mincfg)
161 struct bfa_phy_s *phy = BFA_PHY(bfa);
162 struct bfa_mem_dma_s *phy_dma = BFA_MEM_PHY_DMA(bfa);
164 bfa_phy_attach(phy, &bfa->ioc, bfa, bfa->trcmod, mincfg);
165 bfa_phy_memclaim(phy, phy_dma->kva_curp, phy_dma->dma_curp, mincfg);
169 * BFA IOC FC related definitions
173 * IOC local definitions
175 #define BFA_IOCFC_TOV 5000 /* msecs */
178 BFA_IOCFC_ACT_NONE = 0,
179 BFA_IOCFC_ACT_INIT = 1,
180 BFA_IOCFC_ACT_STOP = 2,
181 BFA_IOCFC_ACT_DISABLE = 3,
182 BFA_IOCFC_ACT_ENABLE = 4,
185 #define DEF_CFG_NUM_FABRICS 1
186 #define DEF_CFG_NUM_LPORTS 256
187 #define DEF_CFG_NUM_CQS 4
188 #define DEF_CFG_NUM_IOIM_REQS (BFA_IOIM_MAX)
189 #define DEF_CFG_NUM_TSKIM_REQS 128
190 #define DEF_CFG_NUM_FCXP_REQS 64
191 #define DEF_CFG_NUM_UF_BUFS 64
192 #define DEF_CFG_NUM_RPORTS 1024
193 #define DEF_CFG_NUM_ITNIMS (DEF_CFG_NUM_RPORTS)
194 #define DEF_CFG_NUM_TINS 256
196 #define DEF_CFG_NUM_SGPGS 2048
197 #define DEF_CFG_NUM_REQQ_ELEMS 256
198 #define DEF_CFG_NUM_RSPQ_ELEMS 64
199 #define DEF_CFG_NUM_SBOOT_TGTS 16
200 #define DEF_CFG_NUM_SBOOT_LUNS 16
203 * IOCFC state machine definitions/declarations
205 bfa_fsm_state_decl(bfa_iocfc, stopped, struct bfa_iocfc_s, enum iocfc_event);
206 bfa_fsm_state_decl(bfa_iocfc, initing, struct bfa_iocfc_s, enum iocfc_event);
207 bfa_fsm_state_decl(bfa_iocfc, dconf_read, struct bfa_iocfc_s, enum iocfc_event);
208 bfa_fsm_state_decl(bfa_iocfc, init_cfg_wait,
209 struct bfa_iocfc_s, enum iocfc_event);
210 bfa_fsm_state_decl(bfa_iocfc, init_cfg_done,
211 struct bfa_iocfc_s, enum iocfc_event);
212 bfa_fsm_state_decl(bfa_iocfc, operational,
213 struct bfa_iocfc_s, enum iocfc_event);
214 bfa_fsm_state_decl(bfa_iocfc, dconf_write,
215 struct bfa_iocfc_s, enum iocfc_event);
216 bfa_fsm_state_decl(bfa_iocfc, stopping, struct bfa_iocfc_s, enum iocfc_event);
217 bfa_fsm_state_decl(bfa_iocfc, enabling, struct bfa_iocfc_s, enum iocfc_event);
218 bfa_fsm_state_decl(bfa_iocfc, cfg_wait, struct bfa_iocfc_s, enum iocfc_event);
219 bfa_fsm_state_decl(bfa_iocfc, disabling, struct bfa_iocfc_s, enum iocfc_event);
220 bfa_fsm_state_decl(bfa_iocfc, disabled, struct bfa_iocfc_s, enum iocfc_event);
221 bfa_fsm_state_decl(bfa_iocfc, failed, struct bfa_iocfc_s, enum iocfc_event);
222 bfa_fsm_state_decl(bfa_iocfc, init_failed,
223 struct bfa_iocfc_s, enum iocfc_event);
226 * forward declaration for IOC FC functions
228 static void bfa_iocfc_start_submod(struct bfa_s *bfa);
229 static void bfa_iocfc_disable_submod(struct bfa_s *bfa);
230 static void bfa_iocfc_send_cfg(void *bfa_arg);
231 static void bfa_iocfc_enable_cbfn(void *bfa_arg, enum bfa_status status);
232 static void bfa_iocfc_disable_cbfn(void *bfa_arg);
233 static void bfa_iocfc_hbfail_cbfn(void *bfa_arg);
234 static void bfa_iocfc_reset_cbfn(void *bfa_arg);
235 static struct bfa_ioc_cbfn_s bfa_iocfc_cbfn;
236 static void bfa_iocfc_init_cb(void *bfa_arg, bfa_boolean_t complete);
237 static void bfa_iocfc_stop_cb(void *bfa_arg, bfa_boolean_t compl);
238 static void bfa_iocfc_enable_cb(void *bfa_arg, bfa_boolean_t compl);
239 static void bfa_iocfc_disable_cb(void *bfa_arg, bfa_boolean_t compl);
242 bfa_iocfc_sm_stopped_entry(struct bfa_iocfc_s *iocfc)
247 bfa_iocfc_sm_stopped(struct bfa_iocfc_s *iocfc, enum iocfc_event event)
249 bfa_trc(iocfc->bfa, event);
254 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_initing);
257 bfa_sm_fault(iocfc->bfa, event);
263 bfa_iocfc_sm_initing_entry(struct bfa_iocfc_s *iocfc)
265 bfa_ioc_enable(&iocfc->bfa->ioc);
269 bfa_iocfc_sm_initing(struct bfa_iocfc_s *iocfc, enum iocfc_event event)
271 bfa_trc(iocfc->bfa, event);
274 case IOCFC_E_IOC_ENABLED:
275 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_dconf_read);
277 case IOCFC_E_IOC_FAILED:
278 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_init_failed);
281 bfa_sm_fault(iocfc->bfa, event);
287 bfa_iocfc_sm_dconf_read_entry(struct bfa_iocfc_s *iocfc)
289 bfa_dconf_modinit(iocfc->bfa);
293 bfa_iocfc_sm_dconf_read(struct bfa_iocfc_s *iocfc, enum iocfc_event event)
295 bfa_trc(iocfc->bfa, event);
298 case IOCFC_E_DCONF_DONE:
299 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_init_cfg_wait);
301 case IOCFC_E_IOC_FAILED:
302 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_init_failed);
305 bfa_sm_fault(iocfc->bfa, event);
311 bfa_iocfc_sm_init_cfg_wait_entry(struct bfa_iocfc_s *iocfc)
313 bfa_iocfc_send_cfg(iocfc->bfa);
317 bfa_iocfc_sm_init_cfg_wait(struct bfa_iocfc_s *iocfc, enum iocfc_event event)
319 bfa_trc(iocfc->bfa, event);
322 case IOCFC_E_CFG_DONE:
323 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_init_cfg_done);
325 case IOCFC_E_IOC_FAILED:
326 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_init_failed);
329 bfa_sm_fault(iocfc->bfa, event);
335 bfa_iocfc_sm_init_cfg_done_entry(struct bfa_iocfc_s *iocfc)
337 iocfc->bfa->iocfc.op_status = BFA_STATUS_OK;
338 bfa_cb_queue(iocfc->bfa, &iocfc->bfa->iocfc.init_hcb_qe,
339 bfa_iocfc_init_cb, iocfc->bfa);
343 bfa_iocfc_sm_init_cfg_done(struct bfa_iocfc_s *iocfc, enum iocfc_event event)
345 bfa_trc(iocfc->bfa, event);
349 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_operational);
352 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_stopping);
354 case IOCFC_E_DISABLE:
355 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_disabling);
357 case IOCFC_E_IOC_FAILED:
358 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_failed);
361 bfa_sm_fault(iocfc->bfa, event);
367 bfa_iocfc_sm_operational_entry(struct bfa_iocfc_s *iocfc)
369 bfa_fcport_init(iocfc->bfa);
370 bfa_iocfc_start_submod(iocfc->bfa);
374 bfa_iocfc_sm_operational(struct bfa_iocfc_s *iocfc, enum iocfc_event event)
376 bfa_trc(iocfc->bfa, event);
380 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_dconf_write);
382 case IOCFC_E_DISABLE:
383 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_disabling);
385 case IOCFC_E_IOC_FAILED:
386 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_failed);
389 bfa_sm_fault(iocfc->bfa, event);
395 bfa_iocfc_sm_dconf_write_entry(struct bfa_iocfc_s *iocfc)
397 bfa_dconf_modexit(iocfc->bfa);
401 bfa_iocfc_sm_dconf_write(struct bfa_iocfc_s *iocfc, enum iocfc_event event)
403 bfa_trc(iocfc->bfa, event);
406 case IOCFC_E_DCONF_DONE:
407 case IOCFC_E_IOC_FAILED:
408 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_stopping);
411 bfa_sm_fault(iocfc->bfa, event);
417 bfa_iocfc_sm_stopping_entry(struct bfa_iocfc_s *iocfc)
419 bfa_ioc_disable(&iocfc->bfa->ioc);
423 bfa_iocfc_sm_stopping(struct bfa_iocfc_s *iocfc, enum iocfc_event event)
425 bfa_trc(iocfc->bfa, event);
428 case IOCFC_E_IOC_DISABLED:
429 bfa_isr_disable(iocfc->bfa);
430 bfa_iocfc_disable_submod(iocfc->bfa);
431 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_stopped);
432 iocfc->bfa->iocfc.op_status = BFA_STATUS_OK;
433 bfa_cb_queue(iocfc->bfa, &iocfc->bfa->iocfc.stop_hcb_qe,
434 bfa_iocfc_stop_cb, iocfc->bfa);
437 bfa_sm_fault(iocfc->bfa, event);
443 bfa_iocfc_sm_enabling_entry(struct bfa_iocfc_s *iocfc)
445 bfa_ioc_enable(&iocfc->bfa->ioc);
449 bfa_iocfc_sm_enabling(struct bfa_iocfc_s *iocfc, enum iocfc_event event)
451 bfa_trc(iocfc->bfa, event);
454 case IOCFC_E_IOC_ENABLED:
455 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_cfg_wait);
457 case IOCFC_E_IOC_FAILED:
458 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_failed);
460 if (iocfc->bfa->iocfc.cb_reqd == BFA_FALSE)
463 iocfc->bfa->iocfc.op_status = BFA_STATUS_FAILED;
464 bfa_cb_queue(iocfc->bfa, &iocfc->bfa->iocfc.en_hcb_qe,
465 bfa_iocfc_enable_cb, iocfc->bfa);
466 iocfc->bfa->iocfc.cb_reqd = BFA_FALSE;
469 bfa_sm_fault(iocfc->bfa, event);
475 bfa_iocfc_sm_cfg_wait_entry(struct bfa_iocfc_s *iocfc)
477 bfa_iocfc_send_cfg(iocfc->bfa);
481 bfa_iocfc_sm_cfg_wait(struct bfa_iocfc_s *iocfc, enum iocfc_event event)
483 bfa_trc(iocfc->bfa, event);
486 case IOCFC_E_CFG_DONE:
487 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_operational);
488 if (iocfc->bfa->iocfc.cb_reqd == BFA_FALSE)
491 iocfc->bfa->iocfc.op_status = BFA_STATUS_OK;
492 bfa_cb_queue(iocfc->bfa, &iocfc->bfa->iocfc.en_hcb_qe,
493 bfa_iocfc_enable_cb, iocfc->bfa);
494 iocfc->bfa->iocfc.cb_reqd = BFA_FALSE;
496 case IOCFC_E_IOC_FAILED:
497 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_failed);
498 if (iocfc->bfa->iocfc.cb_reqd == BFA_FALSE)
501 iocfc->bfa->iocfc.op_status = BFA_STATUS_FAILED;
502 bfa_cb_queue(iocfc->bfa, &iocfc->bfa->iocfc.en_hcb_qe,
503 bfa_iocfc_enable_cb, iocfc->bfa);
504 iocfc->bfa->iocfc.cb_reqd = BFA_FALSE;
507 bfa_sm_fault(iocfc->bfa, event);
513 bfa_iocfc_sm_disabling_entry(struct bfa_iocfc_s *iocfc)
515 bfa_ioc_disable(&iocfc->bfa->ioc);
519 bfa_iocfc_sm_disabling(struct bfa_iocfc_s *iocfc, enum iocfc_event event)
521 bfa_trc(iocfc->bfa, event);
524 case IOCFC_E_IOC_DISABLED:
525 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_disabled);
528 bfa_sm_fault(iocfc->bfa, event);
534 bfa_iocfc_sm_disabled_entry(struct bfa_iocfc_s *iocfc)
536 bfa_isr_disable(iocfc->bfa);
537 bfa_iocfc_disable_submod(iocfc->bfa);
538 iocfc->bfa->iocfc.op_status = BFA_STATUS_OK;
539 bfa_cb_queue(iocfc->bfa, &iocfc->bfa->iocfc.dis_hcb_qe,
540 bfa_iocfc_disable_cb, iocfc->bfa);
544 bfa_iocfc_sm_disabled(struct bfa_iocfc_s *iocfc, enum iocfc_event event)
546 bfa_trc(iocfc->bfa, event);
550 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_dconf_write);
553 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_enabling);
556 bfa_sm_fault(iocfc->bfa, event);
562 bfa_iocfc_sm_failed_entry(struct bfa_iocfc_s *iocfc)
564 bfa_isr_disable(iocfc->bfa);
565 bfa_iocfc_disable_submod(iocfc->bfa);
569 bfa_iocfc_sm_failed(struct bfa_iocfc_s *iocfc, enum iocfc_event event)
571 bfa_trc(iocfc->bfa, event);
575 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_dconf_write);
577 case IOCFC_E_DISABLE:
578 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_disabling);
580 case IOCFC_E_IOC_ENABLED:
581 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_cfg_wait);
583 case IOCFC_E_IOC_FAILED:
586 bfa_sm_fault(iocfc->bfa, event);
592 bfa_iocfc_sm_init_failed_entry(struct bfa_iocfc_s *iocfc)
594 bfa_isr_disable(iocfc->bfa);
595 iocfc->bfa->iocfc.op_status = BFA_STATUS_FAILED;
596 bfa_cb_queue(iocfc->bfa, &iocfc->bfa->iocfc.init_hcb_qe,
597 bfa_iocfc_init_cb, iocfc->bfa);
601 bfa_iocfc_sm_init_failed(struct bfa_iocfc_s *iocfc, enum iocfc_event event)
603 bfa_trc(iocfc->bfa, event);
607 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_stopping);
609 case IOCFC_E_DISABLE:
610 bfa_ioc_disable(&iocfc->bfa->ioc);
612 case IOCFC_E_IOC_ENABLED:
613 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_dconf_read);
615 case IOCFC_E_IOC_DISABLED:
616 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_stopped);
617 iocfc->bfa->iocfc.op_status = BFA_STATUS_OK;
618 bfa_cb_queue(iocfc->bfa, &iocfc->bfa->iocfc.dis_hcb_qe,
619 bfa_iocfc_disable_cb, iocfc->bfa);
621 case IOCFC_E_IOC_FAILED:
624 bfa_sm_fault(iocfc->bfa, event);
630 * BFA Interrupt handling functions
633 bfa_reqq_resume(struct bfa_s *bfa, int qid)
635 struct list_head *waitq, *qe, *qen;
636 struct bfa_reqq_wait_s *wqe;
638 waitq = bfa_reqq(bfa, qid);
639 list_for_each_safe(qe, qen, waitq) {
641 * Callback only as long as there is room in request queue
643 if (bfa_reqq_full(bfa, qid))
647 wqe = (struct bfa_reqq_wait_s *) qe;
648 wqe->qresume(wqe->cbarg);
653 bfa_isr_rspq(struct bfa_s *bfa, int qid)
657 struct list_head *waitq;
660 ci = bfa_rspq_ci(bfa, qid);
661 pi = bfa_rspq_pi(bfa, qid);
666 m = bfa_rspq_elem(bfa, qid, ci);
667 WARN_ON(m->mhdr.msg_class >= BFI_MC_MAX);
669 bfa_isrs[m->mhdr.msg_class] (bfa, m);
670 CQ_INCR(ci, bfa->iocfc.cfg.drvcfg.num_rspq_elems);
674 * acknowledge RME completions and update CI
676 bfa_isr_rspq_ack(bfa, qid, ci);
679 * Resume any pending requests in the corresponding reqq.
681 waitq = bfa_reqq(bfa, qid);
682 if (!list_empty(waitq))
683 bfa_reqq_resume(bfa, qid);
689 bfa_isr_reqq(struct bfa_s *bfa, int qid)
691 struct list_head *waitq;
693 bfa_isr_reqq_ack(bfa, qid);
696 * Resume any pending requests in the corresponding reqq.
698 waitq = bfa_reqq(bfa, qid);
699 if (!list_empty(waitq))
700 bfa_reqq_resume(bfa, qid);
704 bfa_msix_all(struct bfa_s *bfa, int vec)
709 intr = readl(bfa->iocfc.bfa_regs.intr_status);
714 * RME completion queue interrupt
716 qintr = intr & __HFN_INT_RME_MASK;
717 if (qintr && bfa->queue_process) {
718 for (queue = 0; queue < BFI_IOC_MAX_CQS; queue++)
719 bfa_isr_rspq(bfa, queue);
727 * CPE completion queue interrupt
729 qintr = intr & __HFN_INT_CPE_MASK;
730 if (qintr && bfa->queue_process) {
731 for (queue = 0; queue < BFI_IOC_MAX_CQS; queue++)
732 bfa_isr_reqq(bfa, queue);
738 bfa_msix_lpu_err(bfa, intr);
742 bfa_intx(struct bfa_s *bfa)
746 bfa_boolean_t rspq_comp = BFA_FALSE;
748 intr = readl(bfa->iocfc.bfa_regs.intr_status);
750 qintr = intr & (__HFN_INT_RME_MASK | __HFN_INT_CPE_MASK);
752 writel(qintr, bfa->iocfc.bfa_regs.intr_status);
755 * Unconditional RME completion queue interrupt
757 if (bfa->queue_process) {
758 for (queue = 0; queue < BFI_IOC_MAX_CQS; queue++)
759 if (bfa_isr_rspq(bfa, queue))
760 rspq_comp = BFA_TRUE;
764 return (qintr | rspq_comp) ? BFA_TRUE : BFA_FALSE;
767 * CPE completion queue interrupt
769 qintr = intr & __HFN_INT_CPE_MASK;
770 if (qintr && bfa->queue_process) {
771 for (queue = 0; queue < BFI_IOC_MAX_CQS; queue++)
772 bfa_isr_reqq(bfa, queue);
778 if (bfa->intr_enabled)
779 bfa_msix_lpu_err(bfa, intr);
785 bfa_isr_enable(struct bfa_s *bfa)
788 int pci_func = bfa_ioc_pcifn(&bfa->ioc);
790 bfa_trc(bfa, pci_func);
792 bfa_msix_ctrl_install(bfa);
794 if (bfa_asic_id_ct2(bfa->ioc.pcidev.device_id)) {
795 umsk = __HFN_INT_ERR_MASK_CT2;
796 umsk |= pci_func == 0 ?
797 __HFN_INT_FN0_MASK_CT2 : __HFN_INT_FN1_MASK_CT2;
799 umsk = __HFN_INT_ERR_MASK;
800 umsk |= pci_func == 0 ? __HFN_INT_FN0_MASK : __HFN_INT_FN1_MASK;
803 writel(umsk, bfa->iocfc.bfa_regs.intr_status);
804 writel(~umsk, bfa->iocfc.bfa_regs.intr_mask);
805 bfa->iocfc.intr_mask = ~umsk;
806 bfa_isr_mode_set(bfa, bfa->msix.nvecs != 0);
809 * Set the flag indicating successful enabling of interrupts
811 bfa->intr_enabled = BFA_TRUE;
815 bfa_isr_disable(struct bfa_s *bfa)
817 bfa->intr_enabled = BFA_FALSE;
818 bfa_isr_mode_set(bfa, BFA_FALSE);
819 writel(-1L, bfa->iocfc.bfa_regs.intr_mask);
820 bfa_msix_uninstall(bfa);
824 bfa_msix_reqq(struct bfa_s *bfa, int vec)
826 bfa_isr_reqq(bfa, vec - bfa->iocfc.hwif.cpe_vec_q0);
830 bfa_isr_unhandled(struct bfa_s *bfa, struct bfi_msg_s *m)
832 bfa_trc(bfa, m->mhdr.msg_class);
833 bfa_trc(bfa, m->mhdr.msg_id);
834 bfa_trc(bfa, m->mhdr.mtag.i2htok);
836 bfa_trc_stop(bfa->trcmod);
840 bfa_msix_rspq(struct bfa_s *bfa, int vec)
842 bfa_isr_rspq(bfa, vec - bfa->iocfc.hwif.rme_vec_q0);
846 bfa_msix_lpu_err(struct bfa_s *bfa, int vec)
848 u32 intr, curr_value;
849 bfa_boolean_t lpu_isr, halt_isr, pss_isr;
851 intr = readl(bfa->iocfc.bfa_regs.intr_status);
853 if (bfa_asic_id_ct2(bfa->ioc.pcidev.device_id)) {
854 halt_isr = intr & __HFN_INT_CPQ_HALT_CT2;
855 pss_isr = intr & __HFN_INT_ERR_PSS_CT2;
856 lpu_isr = intr & (__HFN_INT_MBOX_LPU0_CT2 |
857 __HFN_INT_MBOX_LPU1_CT2);
858 intr &= __HFN_INT_ERR_MASK_CT2;
860 halt_isr = bfa_asic_id_ct(bfa->ioc.pcidev.device_id) ?
861 (intr & __HFN_INT_LL_HALT) : 0;
862 pss_isr = intr & __HFN_INT_ERR_PSS;
863 lpu_isr = intr & (__HFN_INT_MBOX_LPU0 | __HFN_INT_MBOX_LPU1);
864 intr &= __HFN_INT_ERR_MASK;
868 bfa_ioc_mbox_isr(&bfa->ioc);
873 * If LL_HALT bit is set then FW Init Halt LL Port
874 * Register needs to be cleared as well so Interrupt
875 * Status Register will be cleared.
877 curr_value = readl(bfa->ioc.ioc_regs.ll_halt);
878 curr_value &= ~__FW_INIT_HALT_P;
879 writel(curr_value, bfa->ioc.ioc_regs.ll_halt);
884 * ERR_PSS bit needs to be cleared as well in case
885 * interrups are shared so driver's interrupt handler is
886 * still called even though it is already masked out.
889 bfa->ioc.ioc_regs.pss_err_status_reg);
891 bfa->ioc.ioc_regs.pss_err_status_reg);
894 writel(intr, bfa->iocfc.bfa_regs.intr_status);
895 bfa_ioc_error_isr(&bfa->ioc);
900 * BFA IOC FC related functions
904 * BFA IOC private functions
908 * Use the Mailbox interface to send BFI_IOCFC_H2I_CFG_REQ
911 bfa_iocfc_send_cfg(void *bfa_arg)
913 struct bfa_s *bfa = bfa_arg;
914 struct bfa_iocfc_s *iocfc = &bfa->iocfc;
915 struct bfi_iocfc_cfg_req_s cfg_req;
916 struct bfi_iocfc_cfg_s *cfg_info = iocfc->cfginfo;
917 struct bfa_iocfc_cfg_s *cfg = &iocfc->cfg;
920 WARN_ON(cfg->fwcfg.num_cqs > BFI_IOC_MAX_CQS);
921 bfa_trc(bfa, cfg->fwcfg.num_cqs);
923 bfa_iocfc_reset_queues(bfa);
926 * initialize IOC configuration info
928 cfg_info->single_msix_vec = 0;
929 if (bfa->msix.nvecs == 1)
930 cfg_info->single_msix_vec = 1;
931 cfg_info->endian_sig = BFI_IOC_ENDIAN_SIG;
932 cfg_info->num_cqs = cfg->fwcfg.num_cqs;
933 cfg_info->num_ioim_reqs = cpu_to_be16(cfg->fwcfg.num_ioim_reqs);
934 cfg_info->num_fwtio_reqs = cpu_to_be16(cfg->fwcfg.num_fwtio_reqs);
936 bfa_dma_be_addr_set(cfg_info->cfgrsp_addr, iocfc->cfgrsp_dma.pa);
938 * dma map REQ and RSP circular queues and shadow pointers
940 for (i = 0; i < cfg->fwcfg.num_cqs; i++) {
941 bfa_dma_be_addr_set(cfg_info->req_cq_ba[i],
942 iocfc->req_cq_ba[i].pa);
943 bfa_dma_be_addr_set(cfg_info->req_shadow_ci[i],
944 iocfc->req_cq_shadow_ci[i].pa);
945 cfg_info->req_cq_elems[i] =
946 cpu_to_be16(cfg->drvcfg.num_reqq_elems);
948 bfa_dma_be_addr_set(cfg_info->rsp_cq_ba[i],
949 iocfc->rsp_cq_ba[i].pa);
950 bfa_dma_be_addr_set(cfg_info->rsp_shadow_pi[i],
951 iocfc->rsp_cq_shadow_pi[i].pa);
952 cfg_info->rsp_cq_elems[i] =
953 cpu_to_be16(cfg->drvcfg.num_rspq_elems);
957 * Enable interrupt coalescing if it is driver init path
958 * and not ioc disable/enable path.
960 if (bfa_fsm_cmp_state(iocfc, bfa_iocfc_sm_init_cfg_wait))
961 cfg_info->intr_attr.coalesce = BFA_TRUE;
964 * dma map IOC configuration itself
966 bfi_h2i_set(cfg_req.mh, BFI_MC_IOCFC, BFI_IOCFC_H2I_CFG_REQ,
968 bfa_dma_be_addr_set(cfg_req.ioc_cfg_dma_addr, iocfc->cfg_info.pa);
970 bfa_ioc_mbox_send(&bfa->ioc, &cfg_req,
971 sizeof(struct bfi_iocfc_cfg_req_s));
975 bfa_iocfc_init_mem(struct bfa_s *bfa, void *bfad, struct bfa_iocfc_cfg_s *cfg,
976 struct bfa_pcidev_s *pcidev)
978 struct bfa_iocfc_s *iocfc = &bfa->iocfc;
985 * Initialize chip specific handlers.
987 if (bfa_asic_id_ctc(bfa_ioc_devid(&bfa->ioc))) {
988 iocfc->hwif.hw_reginit = bfa_hwct_reginit;
989 iocfc->hwif.hw_reqq_ack = bfa_hwct_reqq_ack;
990 iocfc->hwif.hw_rspq_ack = bfa_hwct_rspq_ack;
991 iocfc->hwif.hw_msix_init = bfa_hwct_msix_init;
992 iocfc->hwif.hw_msix_ctrl_install = bfa_hwct_msix_ctrl_install;
993 iocfc->hwif.hw_msix_queue_install = bfa_hwct_msix_queue_install;
994 iocfc->hwif.hw_msix_uninstall = bfa_hwct_msix_uninstall;
995 iocfc->hwif.hw_isr_mode_set = bfa_hwct_isr_mode_set;
996 iocfc->hwif.hw_msix_getvecs = bfa_hwct_msix_getvecs;
997 iocfc->hwif.hw_msix_get_rme_range = bfa_hwct_msix_get_rme_range;
998 iocfc->hwif.rme_vec_q0 = BFI_MSIX_RME_QMIN_CT;
999 iocfc->hwif.cpe_vec_q0 = BFI_MSIX_CPE_QMIN_CT;
1001 iocfc->hwif.hw_reginit = bfa_hwcb_reginit;
1002 iocfc->hwif.hw_reqq_ack = NULL;
1003 iocfc->hwif.hw_rspq_ack = bfa_hwcb_rspq_ack;
1004 iocfc->hwif.hw_msix_init = bfa_hwcb_msix_init;
1005 iocfc->hwif.hw_msix_ctrl_install = bfa_hwcb_msix_ctrl_install;
1006 iocfc->hwif.hw_msix_queue_install = bfa_hwcb_msix_queue_install;
1007 iocfc->hwif.hw_msix_uninstall = bfa_hwcb_msix_uninstall;
1008 iocfc->hwif.hw_isr_mode_set = bfa_hwcb_isr_mode_set;
1009 iocfc->hwif.hw_msix_getvecs = bfa_hwcb_msix_getvecs;
1010 iocfc->hwif.hw_msix_get_rme_range = bfa_hwcb_msix_get_rme_range;
1011 iocfc->hwif.rme_vec_q0 = BFI_MSIX_RME_QMIN_CB +
1012 bfa_ioc_pcifn(&bfa->ioc) * BFI_IOC_MAX_CQS;
1013 iocfc->hwif.cpe_vec_q0 = BFI_MSIX_CPE_QMIN_CB +
1014 bfa_ioc_pcifn(&bfa->ioc) * BFI_IOC_MAX_CQS;
1017 if (bfa_asic_id_ct2(bfa_ioc_devid(&bfa->ioc))) {
1018 iocfc->hwif.hw_reginit = bfa_hwct2_reginit;
1019 iocfc->hwif.hw_isr_mode_set = NULL;
1020 iocfc->hwif.hw_rspq_ack = bfa_hwct2_rspq_ack;
1023 iocfc->hwif.hw_reginit(bfa);
1024 bfa->msix.nvecs = 0;
1028 bfa_iocfc_mem_claim(struct bfa_s *bfa, struct bfa_iocfc_cfg_s *cfg)
1032 int i, per_reqq_sz, per_rspq_sz;
1033 struct bfa_iocfc_s *iocfc = &bfa->iocfc;
1034 struct bfa_mem_dma_s *ioc_dma = BFA_MEM_IOC_DMA(bfa);
1035 struct bfa_mem_dma_s *iocfc_dma = BFA_MEM_IOCFC_DMA(bfa);
1036 struct bfa_mem_dma_s *reqq_dma, *rspq_dma;
1038 /* First allocate dma memory for IOC */
1039 bfa_ioc_mem_claim(&bfa->ioc, bfa_mem_dma_virt(ioc_dma),
1040 bfa_mem_dma_phys(ioc_dma));
1042 /* Claim DMA-able memory for the request/response queues */
1043 per_reqq_sz = BFA_ROUNDUP((cfg->drvcfg.num_reqq_elems * BFI_LMSG_SZ),
1045 per_rspq_sz = BFA_ROUNDUP((cfg->drvcfg.num_rspq_elems * BFI_LMSG_SZ),
1048 for (i = 0; i < cfg->fwcfg.num_cqs; i++) {
1049 reqq_dma = BFA_MEM_REQQ_DMA(bfa, i);
1050 iocfc->req_cq_ba[i].kva = bfa_mem_dma_virt(reqq_dma);
1051 iocfc->req_cq_ba[i].pa = bfa_mem_dma_phys(reqq_dma);
1052 memset(iocfc->req_cq_ba[i].kva, 0, per_reqq_sz);
1054 rspq_dma = BFA_MEM_RSPQ_DMA(bfa, i);
1055 iocfc->rsp_cq_ba[i].kva = bfa_mem_dma_virt(rspq_dma);
1056 iocfc->rsp_cq_ba[i].pa = bfa_mem_dma_phys(rspq_dma);
1057 memset(iocfc->rsp_cq_ba[i].kva, 0, per_rspq_sz);
1060 /* Claim IOCFC dma memory - for shadow CI/PI */
1061 dm_kva = bfa_mem_dma_virt(iocfc_dma);
1062 dm_pa = bfa_mem_dma_phys(iocfc_dma);
1064 for (i = 0; i < cfg->fwcfg.num_cqs; i++) {
1065 iocfc->req_cq_shadow_ci[i].kva = dm_kva;
1066 iocfc->req_cq_shadow_ci[i].pa = dm_pa;
1067 dm_kva += BFA_CACHELINE_SZ;
1068 dm_pa += BFA_CACHELINE_SZ;
1070 iocfc->rsp_cq_shadow_pi[i].kva = dm_kva;
1071 iocfc->rsp_cq_shadow_pi[i].pa = dm_pa;
1072 dm_kva += BFA_CACHELINE_SZ;
1073 dm_pa += BFA_CACHELINE_SZ;
1076 /* Claim IOCFC dma memory - for the config info page */
1077 bfa->iocfc.cfg_info.kva = dm_kva;
1078 bfa->iocfc.cfg_info.pa = dm_pa;
1079 bfa->iocfc.cfginfo = (struct bfi_iocfc_cfg_s *) dm_kva;
1080 dm_kva += BFA_ROUNDUP(sizeof(struct bfi_iocfc_cfg_s), BFA_CACHELINE_SZ);
1081 dm_pa += BFA_ROUNDUP(sizeof(struct bfi_iocfc_cfg_s), BFA_CACHELINE_SZ);
1083 /* Claim IOCFC dma memory - for the config response */
1084 bfa->iocfc.cfgrsp_dma.kva = dm_kva;
1085 bfa->iocfc.cfgrsp_dma.pa = dm_pa;
1086 bfa->iocfc.cfgrsp = (struct bfi_iocfc_cfgrsp_s *) dm_kva;
1087 dm_kva += BFA_ROUNDUP(sizeof(struct bfi_iocfc_cfgrsp_s),
1089 dm_pa += BFA_ROUNDUP(sizeof(struct bfi_iocfc_cfgrsp_s),
1092 /* Claim IOCFC kva memory */
1093 bfa_ioc_debug_memclaim(&bfa->ioc, bfa_mem_kva_curp(iocfc));
1094 bfa_mem_kva_curp(iocfc) += BFA_DBG_FWTRC_LEN;
1098 * Start BFA submodules.
1101 bfa_iocfc_start_submod(struct bfa_s *bfa)
1105 bfa->queue_process = BFA_TRUE;
1106 for (i = 0; i < BFI_IOC_MAX_CQS; i++)
1107 bfa_isr_rspq_ack(bfa, i, bfa_rspq_ci(bfa, i));
1109 for (i = 0; hal_mods[i]; i++)
1110 hal_mods[i]->start(bfa);
1112 bfa->iocfc.submod_enabled = BFA_TRUE;
1116 * Disable BFA submodules.
1119 bfa_iocfc_disable_submod(struct bfa_s *bfa)
1123 if (bfa->iocfc.submod_enabled == BFA_FALSE)
1126 for (i = 0; hal_mods[i]; i++)
1127 hal_mods[i]->iocdisable(bfa);
1129 bfa->iocfc.submod_enabled = BFA_FALSE;
1133 bfa_iocfc_init_cb(void *bfa_arg, bfa_boolean_t complete)
1135 struct bfa_s *bfa = bfa_arg;
1138 bfa_cb_init(bfa->bfad, bfa->iocfc.op_status);
1142 bfa_iocfc_stop_cb(void *bfa_arg, bfa_boolean_t compl)
1144 struct bfa_s *bfa = bfa_arg;
1145 struct bfad_s *bfad = bfa->bfad;
1148 complete(&bfad->comp);
1152 bfa_iocfc_enable_cb(void *bfa_arg, bfa_boolean_t compl)
1154 struct bfa_s *bfa = bfa_arg;
1155 struct bfad_s *bfad = bfa->bfad;
1158 complete(&bfad->enable_comp);
1162 bfa_iocfc_disable_cb(void *bfa_arg, bfa_boolean_t compl)
1164 struct bfa_s *bfa = bfa_arg;
1165 struct bfad_s *bfad = bfa->bfad;
1168 complete(&bfad->disable_comp);
1172 * configure queue registers from firmware response
1175 bfa_iocfc_qreg(struct bfa_s *bfa, struct bfi_iocfc_qreg_s *qreg)
1178 struct bfa_iocfc_regs_s *r = &bfa->iocfc.bfa_regs;
1179 void __iomem *kva = bfa_ioc_bar0(&bfa->ioc);
1181 for (i = 0; i < BFI_IOC_MAX_CQS; i++) {
1182 bfa->iocfc.hw_qid[i] = qreg->hw_qid[i];
1183 r->cpe_q_ci[i] = kva + be32_to_cpu(qreg->cpe_q_ci_off[i]);
1184 r->cpe_q_pi[i] = kva + be32_to_cpu(qreg->cpe_q_pi_off[i]);
1185 r->cpe_q_ctrl[i] = kva + be32_to_cpu(qreg->cpe_qctl_off[i]);
1186 r->rme_q_ci[i] = kva + be32_to_cpu(qreg->rme_q_ci_off[i]);
1187 r->rme_q_pi[i] = kva + be32_to_cpu(qreg->rme_q_pi_off[i]);
1188 r->rme_q_ctrl[i] = kva + be32_to_cpu(qreg->rme_qctl_off[i]);
1193 bfa_iocfc_res_recfg(struct bfa_s *bfa, struct bfa_iocfc_fwcfg_s *fwcfg)
1195 bfa_fcxp_res_recfg(bfa, fwcfg->num_fcxp_reqs);
1196 bfa_uf_res_recfg(bfa, fwcfg->num_uf_bufs);
1197 bfa_rport_res_recfg(bfa, fwcfg->num_rports);
1198 bfa_fcp_res_recfg(bfa, fwcfg->num_ioim_reqs);
1199 bfa_tskim_res_recfg(bfa, fwcfg->num_tskim_reqs);
1203 * Update BFA configuration from firmware configuration.
1206 bfa_iocfc_cfgrsp(struct bfa_s *bfa)
1208 struct bfa_iocfc_s *iocfc = &bfa->iocfc;
1209 struct bfi_iocfc_cfgrsp_s *cfgrsp = iocfc->cfgrsp;
1210 struct bfa_iocfc_fwcfg_s *fwcfg = &cfgrsp->fwcfg;
1212 fwcfg->num_cqs = fwcfg->num_cqs;
1213 fwcfg->num_ioim_reqs = be16_to_cpu(fwcfg->num_ioim_reqs);
1214 fwcfg->num_fwtio_reqs = be16_to_cpu(fwcfg->num_fwtio_reqs);
1215 fwcfg->num_tskim_reqs = be16_to_cpu(fwcfg->num_tskim_reqs);
1216 fwcfg->num_fcxp_reqs = be16_to_cpu(fwcfg->num_fcxp_reqs);
1217 fwcfg->num_uf_bufs = be16_to_cpu(fwcfg->num_uf_bufs);
1218 fwcfg->num_rports = be16_to_cpu(fwcfg->num_rports);
1221 * configure queue register offsets as learnt from firmware
1223 bfa_iocfc_qreg(bfa, &cfgrsp->qreg);
1226 * Re-configure resources as learnt from Firmware
1228 bfa_iocfc_res_recfg(bfa, fwcfg);
1231 * Install MSIX queue handlers
1233 bfa_msix_queue_install(bfa);
1235 if (bfa->iocfc.cfgrsp->pbc_cfg.pbc_pwwn != 0) {
1236 bfa->ioc.attr->pwwn = bfa->iocfc.cfgrsp->pbc_cfg.pbc_pwwn;
1237 bfa->ioc.attr->nwwn = bfa->iocfc.cfgrsp->pbc_cfg.pbc_nwwn;
1238 bfa_fsm_send_event(iocfc, IOCFC_E_CFG_DONE);
1243 bfa_iocfc_reset_queues(struct bfa_s *bfa)
1247 for (q = 0; q < BFI_IOC_MAX_CQS; q++) {
1248 bfa_reqq_ci(bfa, q) = 0;
1249 bfa_reqq_pi(bfa, q) = 0;
1250 bfa_rspq_ci(bfa, q) = 0;
1251 bfa_rspq_pi(bfa, q) = 0;
1256 * Process FAA pwwn msg from fw.
1259 bfa_iocfc_process_faa_addr(struct bfa_s *bfa, struct bfi_faa_addr_msg_s *msg)
1261 struct bfa_iocfc_s *iocfc = &bfa->iocfc;
1262 struct bfi_iocfc_cfgrsp_s *cfgrsp = iocfc->cfgrsp;
1264 cfgrsp->pbc_cfg.pbc_pwwn = msg->pwwn;
1265 cfgrsp->pbc_cfg.pbc_nwwn = msg->nwwn;
1267 bfa->ioc.attr->pwwn = msg->pwwn;
1268 bfa->ioc.attr->nwwn = msg->nwwn;
1269 bfa_fsm_send_event(iocfc, IOCFC_E_CFG_DONE);
1272 /* Fabric Assigned Address specific functions */
1275 * Check whether IOC is ready before sending command down
1278 bfa_faa_validate_request(struct bfa_s *bfa)
1280 enum bfa_ioc_type_e ioc_type = bfa_get_type(bfa);
1281 u32 card_type = bfa->ioc.attr->card_type;
1283 if (bfa_ioc_is_operational(&bfa->ioc)) {
1284 if ((ioc_type != BFA_IOC_TYPE_FC) || bfa_mfg_is_mezz(card_type))
1285 return BFA_STATUS_FEATURE_NOT_SUPPORTED;
1287 return BFA_STATUS_IOC_NON_OP;
1290 return BFA_STATUS_OK;
1294 bfa_faa_query(struct bfa_s *bfa, struct bfa_faa_attr_s *attr,
1295 bfa_cb_iocfc_t cbfn, void *cbarg)
1297 struct bfi_faa_query_s faa_attr_req;
1298 struct bfa_iocfc_s *iocfc = &bfa->iocfc;
1299 bfa_status_t status;
1301 iocfc->faa_args.faa_attr = attr;
1302 iocfc->faa_args.faa_cb.faa_cbfn = cbfn;
1303 iocfc->faa_args.faa_cb.faa_cbarg = cbarg;
1305 status = bfa_faa_validate_request(bfa);
1306 if (status != BFA_STATUS_OK)
1309 if (iocfc->faa_args.busy == BFA_TRUE)
1310 return BFA_STATUS_DEVBUSY;
1312 iocfc->faa_args.busy = BFA_TRUE;
1313 memset(&faa_attr_req, 0, sizeof(struct bfi_faa_query_s));
1314 bfi_h2i_set(faa_attr_req.mh, BFI_MC_IOCFC,
1315 BFI_IOCFC_H2I_FAA_QUERY_REQ, bfa_fn_lpu(bfa));
1317 bfa_ioc_mbox_send(&bfa->ioc, &faa_attr_req,
1318 sizeof(struct bfi_faa_query_s));
1320 return BFA_STATUS_OK;
1324 * FAA query response
1327 bfa_faa_query_reply(struct bfa_iocfc_s *iocfc,
1328 bfi_faa_query_rsp_t *rsp)
1330 void *cbarg = iocfc->faa_args.faa_cb.faa_cbarg;
1332 if (iocfc->faa_args.faa_attr) {
1333 iocfc->faa_args.faa_attr->faa = rsp->faa;
1334 iocfc->faa_args.faa_attr->faa_state = rsp->faa_status;
1335 iocfc->faa_args.faa_attr->pwwn_source = rsp->addr_source;
1338 WARN_ON(!iocfc->faa_args.faa_cb.faa_cbfn);
1340 iocfc->faa_args.faa_cb.faa_cbfn(cbarg, BFA_STATUS_OK);
1341 iocfc->faa_args.busy = BFA_FALSE;
1345 * IOC enable request is complete
1348 bfa_iocfc_enable_cbfn(void *bfa_arg, enum bfa_status status)
1350 struct bfa_s *bfa = bfa_arg;
1352 if (status == BFA_STATUS_OK)
1353 bfa_fsm_send_event(&bfa->iocfc, IOCFC_E_IOC_ENABLED);
1355 bfa_fsm_send_event(&bfa->iocfc, IOCFC_E_IOC_FAILED);
1359 * IOC disable request is complete
1362 bfa_iocfc_disable_cbfn(void *bfa_arg)
1364 struct bfa_s *bfa = bfa_arg;
1366 bfa_fsm_send_event(&bfa->iocfc, IOCFC_E_IOC_DISABLED);
1370 * Notify sub-modules of hardware failure.
1373 bfa_iocfc_hbfail_cbfn(void *bfa_arg)
1375 struct bfa_s *bfa = bfa_arg;
1377 bfa->queue_process = BFA_FALSE;
1378 bfa_fsm_send_event(&bfa->iocfc, IOCFC_E_IOC_FAILED);
1382 * Actions on chip-reset completion.
1385 bfa_iocfc_reset_cbfn(void *bfa_arg)
1387 struct bfa_s *bfa = bfa_arg;
1389 bfa_iocfc_reset_queues(bfa);
1390 bfa_isr_enable(bfa);
1394 * Query IOC memory requirement information.
1397 bfa_iocfc_meminfo(struct bfa_iocfc_cfg_s *cfg, struct bfa_meminfo_s *meminfo,
1400 int q, per_reqq_sz, per_rspq_sz;
1401 struct bfa_mem_dma_s *ioc_dma = BFA_MEM_IOC_DMA(bfa);
1402 struct bfa_mem_dma_s *iocfc_dma = BFA_MEM_IOCFC_DMA(bfa);
1403 struct bfa_mem_kva_s *iocfc_kva = BFA_MEM_IOCFC_KVA(bfa);
1406 /* dma memory setup for IOC */
1407 bfa_mem_dma_setup(meminfo, ioc_dma,
1408 BFA_ROUNDUP(sizeof(struct bfi_ioc_attr_s), BFA_DMA_ALIGN_SZ));
1410 /* dma memory setup for REQ/RSP queues */
1411 per_reqq_sz = BFA_ROUNDUP((cfg->drvcfg.num_reqq_elems * BFI_LMSG_SZ),
1413 per_rspq_sz = BFA_ROUNDUP((cfg->drvcfg.num_rspq_elems * BFI_LMSG_SZ),
1416 for (q = 0; q < cfg->fwcfg.num_cqs; q++) {
1417 bfa_mem_dma_setup(meminfo, BFA_MEM_REQQ_DMA(bfa, q),
1419 bfa_mem_dma_setup(meminfo, BFA_MEM_RSPQ_DMA(bfa, q),
1423 /* IOCFC dma memory - calculate Shadow CI/PI size */
1424 for (q = 0; q < cfg->fwcfg.num_cqs; q++)
1425 dm_len += (2 * BFA_CACHELINE_SZ);
1427 /* IOCFC dma memory - calculate config info / rsp size */
1428 dm_len += BFA_ROUNDUP(sizeof(struct bfi_iocfc_cfg_s), BFA_CACHELINE_SZ);
1429 dm_len += BFA_ROUNDUP(sizeof(struct bfi_iocfc_cfgrsp_s),
1432 /* dma memory setup for IOCFC */
1433 bfa_mem_dma_setup(meminfo, iocfc_dma, dm_len);
1435 /* kva memory setup for IOCFC */
1436 bfa_mem_kva_setup(meminfo, iocfc_kva, BFA_DBG_FWTRC_LEN);
1440 * Query IOC memory requirement information.
1443 bfa_iocfc_attach(struct bfa_s *bfa, void *bfad, struct bfa_iocfc_cfg_s *cfg,
1444 struct bfa_pcidev_s *pcidev)
1447 struct bfa_ioc_s *ioc = &bfa->ioc;
1449 bfa_iocfc_cbfn.enable_cbfn = bfa_iocfc_enable_cbfn;
1450 bfa_iocfc_cbfn.disable_cbfn = bfa_iocfc_disable_cbfn;
1451 bfa_iocfc_cbfn.hbfail_cbfn = bfa_iocfc_hbfail_cbfn;
1452 bfa_iocfc_cbfn.reset_cbfn = bfa_iocfc_reset_cbfn;
1454 ioc->trcmod = bfa->trcmod;
1455 bfa_ioc_attach(&bfa->ioc, bfa, &bfa_iocfc_cbfn, &bfa->timer_mod);
1457 bfa_ioc_pci_init(&bfa->ioc, pcidev, BFI_PCIFN_CLASS_FC);
1458 bfa_ioc_mbox_register(&bfa->ioc, bfa_mbox_isrs);
1460 bfa_iocfc_init_mem(bfa, bfad, cfg, pcidev);
1461 bfa_iocfc_mem_claim(bfa, cfg);
1462 INIT_LIST_HEAD(&bfa->timer_mod.timer_q);
1464 INIT_LIST_HEAD(&bfa->comp_q);
1465 for (i = 0; i < BFI_IOC_MAX_CQS; i++)
1466 INIT_LIST_HEAD(&bfa->reqq_waitq[i]);
1468 bfa->iocfc.cb_reqd = BFA_FALSE;
1469 bfa->iocfc.op_status = BFA_STATUS_OK;
1470 bfa->iocfc.submod_enabled = BFA_FALSE;
1472 bfa_fsm_set_state(&bfa->iocfc, bfa_iocfc_sm_stopped);
1476 * Query IOC memory requirement information.
1479 bfa_iocfc_init(struct bfa_s *bfa)
1481 bfa_fsm_send_event(&bfa->iocfc, IOCFC_E_INIT);
1485 * IOC start called from bfa_start(). Called to start IOC operations
1486 * at driver instantiation for this instance.
1489 bfa_iocfc_start(struct bfa_s *bfa)
1491 bfa_fsm_send_event(&bfa->iocfc, IOCFC_E_START);
1495 * IOC stop called from bfa_stop(). Called only when driver is unloaded
1496 * for this instance.
1499 bfa_iocfc_stop(struct bfa_s *bfa)
1501 bfa->queue_process = BFA_FALSE;
1502 bfa_fsm_send_event(&bfa->iocfc, IOCFC_E_STOP);
1506 bfa_iocfc_isr(void *bfaarg, struct bfi_mbmsg_s *m)
1508 struct bfa_s *bfa = bfaarg;
1509 struct bfa_iocfc_s *iocfc = &bfa->iocfc;
1510 union bfi_iocfc_i2h_msg_u *msg;
1512 msg = (union bfi_iocfc_i2h_msg_u *) m;
1513 bfa_trc(bfa, msg->mh.msg_id);
1515 switch (msg->mh.msg_id) {
1516 case BFI_IOCFC_I2H_CFG_REPLY:
1517 bfa_iocfc_cfgrsp(bfa);
1519 case BFI_IOCFC_I2H_UPDATEQ_RSP:
1520 iocfc->updateq_cbfn(iocfc->updateq_cbarg, BFA_STATUS_OK);
1522 case BFI_IOCFC_I2H_ADDR_MSG:
1523 bfa_iocfc_process_faa_addr(bfa,
1524 (struct bfi_faa_addr_msg_s *)msg);
1526 case BFI_IOCFC_I2H_FAA_QUERY_RSP:
1527 bfa_faa_query_reply(iocfc, (bfi_faa_query_rsp_t *)msg);
1535 bfa_iocfc_get_attr(struct bfa_s *bfa, struct bfa_iocfc_attr_s *attr)
1537 struct bfa_iocfc_s *iocfc = &bfa->iocfc;
1539 attr->intr_attr.coalesce = iocfc->cfginfo->intr_attr.coalesce;
1541 attr->intr_attr.delay = iocfc->cfginfo->intr_attr.delay ?
1542 be16_to_cpu(iocfc->cfginfo->intr_attr.delay) :
1543 be16_to_cpu(iocfc->cfgrsp->intr_attr.delay);
1545 attr->intr_attr.latency = iocfc->cfginfo->intr_attr.latency ?
1546 be16_to_cpu(iocfc->cfginfo->intr_attr.latency) :
1547 be16_to_cpu(iocfc->cfgrsp->intr_attr.latency);
1549 attr->config = iocfc->cfg;
1553 bfa_iocfc_israttr_set(struct bfa_s *bfa, struct bfa_iocfc_intr_attr_s *attr)
1555 struct bfa_iocfc_s *iocfc = &bfa->iocfc;
1556 struct bfi_iocfc_set_intr_req_s *m;
1558 iocfc->cfginfo->intr_attr.coalesce = attr->coalesce;
1559 iocfc->cfginfo->intr_attr.delay = cpu_to_be16(attr->delay);
1560 iocfc->cfginfo->intr_attr.latency = cpu_to_be16(attr->latency);
1562 if (!bfa_iocfc_is_operational(bfa))
1563 return BFA_STATUS_OK;
1565 m = bfa_reqq_next(bfa, BFA_REQQ_IOC);
1567 return BFA_STATUS_DEVBUSY;
1569 bfi_h2i_set(m->mh, BFI_MC_IOCFC, BFI_IOCFC_H2I_SET_INTR_REQ,
1571 m->coalesce = iocfc->cfginfo->intr_attr.coalesce;
1572 m->delay = iocfc->cfginfo->intr_attr.delay;
1573 m->latency = iocfc->cfginfo->intr_attr.latency;
1575 bfa_trc(bfa, attr->delay);
1576 bfa_trc(bfa, attr->latency);
1578 bfa_reqq_produce(bfa, BFA_REQQ_IOC, m->mh);
1579 return BFA_STATUS_OK;
1583 bfa_iocfc_set_snsbase(struct bfa_s *bfa, int seg_no, u64 snsbase_pa)
1585 struct bfa_iocfc_s *iocfc = &bfa->iocfc;
1587 iocfc->cfginfo->sense_buf_len = (BFI_IOIM_SNSLEN - 1);
1588 bfa_dma_be_addr_set(iocfc->cfginfo->ioim_snsbase[seg_no], snsbase_pa);
1591 * Enable IOC after it is disabled.
1594 bfa_iocfc_enable(struct bfa_s *bfa)
1596 bfa_plog_str(bfa->plog, BFA_PL_MID_HAL, BFA_PL_EID_MISC, 0,
1598 bfa->iocfc.cb_reqd = BFA_TRUE;
1599 bfa_fsm_send_event(&bfa->iocfc, IOCFC_E_ENABLE);
1603 bfa_iocfc_disable(struct bfa_s *bfa)
1605 bfa_plog_str(bfa->plog, BFA_PL_MID_HAL, BFA_PL_EID_MISC, 0,
1608 bfa->queue_process = BFA_FALSE;
1609 bfa_fsm_send_event(&bfa->iocfc, IOCFC_E_DISABLE);
1613 bfa_iocfc_is_operational(struct bfa_s *bfa)
1615 return bfa_ioc_is_operational(&bfa->ioc) &&
1616 bfa_fsm_cmp_state(&bfa->iocfc, bfa_iocfc_sm_operational);
1620 * Return boot target port wwns -- read from boot information in flash.
1623 bfa_iocfc_get_bootwwns(struct bfa_s *bfa, u8 *nwwns, wwn_t *wwns)
1625 struct bfa_iocfc_s *iocfc = &bfa->iocfc;
1626 struct bfi_iocfc_cfgrsp_s *cfgrsp = iocfc->cfgrsp;
1629 if (cfgrsp->pbc_cfg.boot_enabled && cfgrsp->pbc_cfg.nbluns) {
1630 bfa_trc(bfa, cfgrsp->pbc_cfg.nbluns);
1631 *nwwns = cfgrsp->pbc_cfg.nbluns;
1632 for (i = 0; i < cfgrsp->pbc_cfg.nbluns; i++)
1633 wwns[i] = cfgrsp->pbc_cfg.blun[i].tgt_pwwn;
1638 *nwwns = cfgrsp->bootwwns.nwwns;
1639 memcpy(wwns, cfgrsp->bootwwns.wwn, sizeof(cfgrsp->bootwwns.wwn));
1643 bfa_iocfc_get_pbc_vports(struct bfa_s *bfa, struct bfi_pbc_vport_s *pbc_vport)
1645 struct bfa_iocfc_s *iocfc = &bfa->iocfc;
1646 struct bfi_iocfc_cfgrsp_s *cfgrsp = iocfc->cfgrsp;
1648 memcpy(pbc_vport, cfgrsp->pbc_cfg.vport, sizeof(cfgrsp->pbc_cfg.vport));
1649 return cfgrsp->pbc_cfg.nvports;
1654 * Use this function query the memory requirement of the BFA library.
1655 * This function needs to be called before bfa_attach() to get the
1656 * memory required of the BFA layer for a given driver configuration.
1658 * This call will fail, if the cap is out of range compared to pre-defined
1659 * values within the BFA library
1661 * @param[in] cfg - pointer to bfa_ioc_cfg_t. Driver layer should indicate
1662 * its configuration in this structure.
1663 * The default values for struct bfa_iocfc_cfg_s can be
1664 * fetched using bfa_cfg_get_default() API.
1666 * If cap's boundary check fails, the library will use
1667 * the default bfa_cap_t values (and log a warning msg).
1669 * @param[out] meminfo - pointer to bfa_meminfo_t. This content
1670 * indicates the memory type (see bfa_mem_type_t) and
1671 * amount of memory required.
1673 * Driver should allocate the memory, populate the
1674 * starting address for each block and provide the same
1675 * structure as input parameter to bfa_attach() call.
1677 * @param[in] bfa - pointer to the bfa structure, used while fetching the
1678 * dma, kva memory information of the bfa sub-modules.
1682 * Special Considerations: @note
1685 bfa_cfg_get_meminfo(struct bfa_iocfc_cfg_s *cfg, struct bfa_meminfo_s *meminfo,
1689 struct bfa_mem_dma_s *port_dma = BFA_MEM_PORT_DMA(bfa);
1690 struct bfa_mem_dma_s *ablk_dma = BFA_MEM_ABLK_DMA(bfa);
1691 struct bfa_mem_dma_s *cee_dma = BFA_MEM_CEE_DMA(bfa);
1692 struct bfa_mem_dma_s *sfp_dma = BFA_MEM_SFP_DMA(bfa);
1693 struct bfa_mem_dma_s *flash_dma = BFA_MEM_FLASH_DMA(bfa);
1694 struct bfa_mem_dma_s *diag_dma = BFA_MEM_DIAG_DMA(bfa);
1695 struct bfa_mem_dma_s *phy_dma = BFA_MEM_PHY_DMA(bfa);
1697 WARN_ON((cfg == NULL) || (meminfo == NULL));
1699 memset((void *)meminfo, 0, sizeof(struct bfa_meminfo_s));
1701 /* Initialize the DMA & KVA meminfo queues */
1702 INIT_LIST_HEAD(&meminfo->dma_info.qe);
1703 INIT_LIST_HEAD(&meminfo->kva_info.qe);
1705 bfa_iocfc_meminfo(cfg, meminfo, bfa);
1707 for (i = 0; hal_mods[i]; i++)
1708 hal_mods[i]->meminfo(cfg, meminfo, bfa);
1710 /* dma info setup */
1711 bfa_mem_dma_setup(meminfo, port_dma, bfa_port_meminfo());
1712 bfa_mem_dma_setup(meminfo, ablk_dma, bfa_ablk_meminfo());
1713 bfa_mem_dma_setup(meminfo, cee_dma, bfa_cee_meminfo());
1714 bfa_mem_dma_setup(meminfo, sfp_dma, bfa_sfp_meminfo());
1715 bfa_mem_dma_setup(meminfo, flash_dma,
1716 bfa_flash_meminfo(cfg->drvcfg.min_cfg));
1717 bfa_mem_dma_setup(meminfo, diag_dma, bfa_diag_meminfo());
1718 bfa_mem_dma_setup(meminfo, phy_dma,
1719 bfa_phy_meminfo(cfg->drvcfg.min_cfg));
1723 * Use this function to do attach the driver instance with the BFA
1724 * library. This function will not trigger any HW initialization
1725 * process (which will be done in bfa_init() call)
1727 * This call will fail, if the cap is out of range compared to
1728 * pre-defined values within the BFA library
1730 * @param[out] bfa Pointer to bfa_t.
1731 * @param[in] bfad Opaque handle back to the driver's IOC structure
1732 * @param[in] cfg Pointer to bfa_ioc_cfg_t. Should be same structure
1733 * that was used in bfa_cfg_get_meminfo().
1734 * @param[in] meminfo Pointer to bfa_meminfo_t. The driver should
1735 * use the bfa_cfg_get_meminfo() call to
1736 * find the memory blocks required, allocate the
1737 * required memory and provide the starting addresses.
1738 * @param[in] pcidev pointer to struct bfa_pcidev_s
1743 * Special Considerations:
1749 bfa_attach(struct bfa_s *bfa, void *bfad, struct bfa_iocfc_cfg_s *cfg,
1750 struct bfa_meminfo_s *meminfo, struct bfa_pcidev_s *pcidev)
1753 struct bfa_mem_dma_s *dma_info, *dma_elem;
1754 struct bfa_mem_kva_s *kva_info, *kva_elem;
1755 struct list_head *dm_qe, *km_qe;
1757 bfa->fcs = BFA_FALSE;
1759 WARN_ON((cfg == NULL) || (meminfo == NULL));
1761 /* Initialize memory pointers for iterative allocation */
1762 dma_info = &meminfo->dma_info;
1763 dma_info->kva_curp = dma_info->kva;
1764 dma_info->dma_curp = dma_info->dma;
1766 kva_info = &meminfo->kva_info;
1767 kva_info->kva_curp = kva_info->kva;
1769 list_for_each(dm_qe, &dma_info->qe) {
1770 dma_elem = (struct bfa_mem_dma_s *) dm_qe;
1771 dma_elem->kva_curp = dma_elem->kva;
1772 dma_elem->dma_curp = dma_elem->dma;
1775 list_for_each(km_qe, &kva_info->qe) {
1776 kva_elem = (struct bfa_mem_kva_s *) km_qe;
1777 kva_elem->kva_curp = kva_elem->kva;
1780 bfa_iocfc_attach(bfa, bfad, cfg, pcidev);
1782 for (i = 0; hal_mods[i]; i++)
1783 hal_mods[i]->attach(bfa, bfad, cfg, pcidev);
1785 bfa_com_port_attach(bfa);
1786 bfa_com_ablk_attach(bfa);
1787 bfa_com_cee_attach(bfa);
1788 bfa_com_sfp_attach(bfa);
1789 bfa_com_flash_attach(bfa, cfg->drvcfg.min_cfg);
1790 bfa_com_diag_attach(bfa);
1791 bfa_com_phy_attach(bfa, cfg->drvcfg.min_cfg);
1795 * Use this function to delete a BFA IOC. IOC should be stopped (by
1796 * calling bfa_stop()) before this function call.
1798 * @param[in] bfa - pointer to bfa_t.
1803 * Special Considerations:
1808 bfa_detach(struct bfa_s *bfa)
1812 for (i = 0; hal_mods[i]; i++)
1813 hal_mods[i]->detach(bfa);
1814 bfa_ioc_detach(&bfa->ioc);
1818 bfa_comp_deq(struct bfa_s *bfa, struct list_head *comp_q)
1820 INIT_LIST_HEAD(comp_q);
1821 list_splice_tail_init(&bfa->comp_q, comp_q);
1825 bfa_comp_process(struct bfa_s *bfa, struct list_head *comp_q)
1827 struct list_head *qe;
1828 struct list_head *qen;
1829 struct bfa_cb_qe_s *hcb_qe;
1830 bfa_cb_cbfn_status_t cbfn;
1832 list_for_each_safe(qe, qen, comp_q) {
1833 hcb_qe = (struct bfa_cb_qe_s *) qe;
1834 if (hcb_qe->pre_rmv) {
1835 /* qe is invalid after return, dequeue before cbfn() */
1837 cbfn = (bfa_cb_cbfn_status_t)(hcb_qe->cbfn);
1838 cbfn(hcb_qe->cbarg, hcb_qe->fw_status);
1840 hcb_qe->cbfn(hcb_qe->cbarg, BFA_TRUE);
1845 bfa_comp_free(struct bfa_s *bfa, struct list_head *comp_q)
1847 struct list_head *qe;
1848 struct bfa_cb_qe_s *hcb_qe;
1850 while (!list_empty(comp_q)) {
1851 bfa_q_deq(comp_q, &qe);
1852 hcb_qe = (struct bfa_cb_qe_s *) qe;
1853 WARN_ON(hcb_qe->pre_rmv);
1854 hcb_qe->cbfn(hcb_qe->cbarg, BFA_FALSE);
1859 * Return the list of PCI vendor/device id lists supported by this
1863 bfa_get_pciids(struct bfa_pciid_s **pciids, int *npciids)
1865 static struct bfa_pciid_s __pciids[] = {
1866 {BFA_PCI_VENDOR_ID_BROCADE, BFA_PCI_DEVICE_ID_FC_8G2P},
1867 {BFA_PCI_VENDOR_ID_BROCADE, BFA_PCI_DEVICE_ID_FC_8G1P},
1868 {BFA_PCI_VENDOR_ID_BROCADE, BFA_PCI_DEVICE_ID_CT},
1869 {BFA_PCI_VENDOR_ID_BROCADE, BFA_PCI_DEVICE_ID_CT_FC},
1872 *npciids = sizeof(__pciids) / sizeof(__pciids[0]);
1877 * Use this function query the default struct bfa_iocfc_cfg_s value (compiled
1878 * into BFA layer). The OS driver can then turn back and overwrite entries that
1879 * have been configured by the user.
1881 * @param[in] cfg - pointer to bfa_ioc_cfg_t
1886 * Special Considerations:
1890 bfa_cfg_get_default(struct bfa_iocfc_cfg_s *cfg)
1892 cfg->fwcfg.num_fabrics = DEF_CFG_NUM_FABRICS;
1893 cfg->fwcfg.num_lports = DEF_CFG_NUM_LPORTS;
1894 cfg->fwcfg.num_rports = DEF_CFG_NUM_RPORTS;
1895 cfg->fwcfg.num_ioim_reqs = DEF_CFG_NUM_IOIM_REQS;
1896 cfg->fwcfg.num_tskim_reqs = DEF_CFG_NUM_TSKIM_REQS;
1897 cfg->fwcfg.num_fcxp_reqs = DEF_CFG_NUM_FCXP_REQS;
1898 cfg->fwcfg.num_uf_bufs = DEF_CFG_NUM_UF_BUFS;
1899 cfg->fwcfg.num_cqs = DEF_CFG_NUM_CQS;
1900 cfg->fwcfg.num_fwtio_reqs = 0;
1902 cfg->drvcfg.num_reqq_elems = DEF_CFG_NUM_REQQ_ELEMS;
1903 cfg->drvcfg.num_rspq_elems = DEF_CFG_NUM_RSPQ_ELEMS;
1904 cfg->drvcfg.num_sgpgs = DEF_CFG_NUM_SGPGS;
1905 cfg->drvcfg.num_sboot_tgts = DEF_CFG_NUM_SBOOT_TGTS;
1906 cfg->drvcfg.num_sboot_luns = DEF_CFG_NUM_SBOOT_LUNS;
1907 cfg->drvcfg.path_tov = BFA_FCPIM_PATHTOV_DEF;
1908 cfg->drvcfg.ioc_recover = BFA_FALSE;
1909 cfg->drvcfg.delay_comp = BFA_FALSE;
1914 bfa_cfg_get_min(struct bfa_iocfc_cfg_s *cfg)
1916 bfa_cfg_get_default(cfg);
1917 cfg->fwcfg.num_ioim_reqs = BFA_IOIM_MIN;
1918 cfg->fwcfg.num_tskim_reqs = BFA_TSKIM_MIN;
1919 cfg->fwcfg.num_fcxp_reqs = BFA_FCXP_MIN;
1920 cfg->fwcfg.num_uf_bufs = BFA_UF_MIN;
1921 cfg->fwcfg.num_rports = BFA_RPORT_MIN;
1922 cfg->fwcfg.num_fwtio_reqs = 0;
1924 cfg->drvcfg.num_sgpgs = BFA_SGPG_MIN;
1925 cfg->drvcfg.num_reqq_elems = BFA_REQQ_NELEMS_MIN;
1926 cfg->drvcfg.num_rspq_elems = BFA_RSPQ_NELEMS_MIN;
1927 cfg->drvcfg.min_cfg = BFA_TRUE;