2 * Copyright (C) 2005 - 2013 Emulex
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Written by: Jayamohan Kallickal (jayamohan.kallickal@emulex.com)
12 * Contact Information:
13 * linux-drivers@emulex.com
17 * Costa Mesa, CA 92626
20 #ifndef _BEISCSI_MAIN_
21 #define _BEISCSI_MAIN_
23 #include <linux/kernel.h>
24 #include <linux/pci.h>
25 #include <linux/if_ether.h>
27 #include <linux/ctype.h>
28 #include <linux/module.h>
29 #include <scsi/scsi.h>
30 #include <scsi/scsi_cmnd.h>
31 #include <scsi/scsi_device.h>
32 #include <scsi/scsi_host.h>
33 #include <scsi/iscsi_proto.h>
34 #include <scsi/libiscsi.h>
35 #include <scsi/scsi_transport_iscsi.h>
38 #define DRV_NAME "be2iscsi"
39 #define BUILD_STR "10.0.467.0"
40 #define BE_NAME "Emulex OneConnect" \
41 "Open-iSCSI Driver version" BUILD_STR
42 #define DRV_DESC BE_NAME " " "Driver"
44 #define BE_VENDOR_ID 0x19A2
45 #define ELX_VENDOR_ID 0x10DF
46 /* DEVICE ID's for BE2 */
47 #define BE_DEVICE_ID1 0x212
48 #define OC_DEVICE_ID1 0x702
49 #define OC_DEVICE_ID2 0x703
51 /* DEVICE ID's for BE3 */
52 #define BE_DEVICE_ID2 0x222
53 #define OC_DEVICE_ID3 0x712
55 /* DEVICE ID for SKH */
56 #define OC_SKH_ID1 0x722
58 #define BE2_IO_DEPTH 1024
59 #define BE2_MAX_SESSIONS 256
60 #define BE2_CMDS_PER_CXN 128
62 #define BE2_NOPOUT_REQ 16
64 #define BE2_DEFPDU_HDR_SZ 64
65 #define BE2_DEFPDU_DATA_SZ 8192
68 #define BEISCSI_MAX_NUM_CPUS 7
69 #define OC_SKH_MAX_NUM_CPUS 31
71 #define BEISCSI_VER_STRLEN 32
73 #define BEISCSI_SGLIST_ELEMENTS 30
75 #define BEISCSI_CMD_PER_LUN 128 /* scsi_host->cmd_per_lun */
76 #define BEISCSI_MAX_SECTORS 2048 /* scsi_host->max_sectors */
77 #define BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE 128 /* Template size per cxn */
79 #define BEISCSI_MAX_CMD_LEN 16 /* scsi_host->max_cmd_len */
80 #define BEISCSI_NUM_MAX_LUN 256 /* scsi_host->max_lun */
81 #define BEISCSI_NUM_DEVICES_SUPPORTED 0x01
82 #define BEISCSI_MAX_FRAGS_INIT 192
83 #define BE_NUM_MSIX_ENTRIES 1
85 #define MPU_EP_CONTROL 0
86 #define MPU_EP_SEMAPHORE 0xac
87 #define BE2_SOFT_RESET 0x5c
88 #define BE2_PCI_ONLINE0 0xb0
89 #define BE2_PCI_ONLINE1 0xb4
90 #define BE2_SET_RESET 0x80
91 #define BE2_MPU_IRAM_ONLINE 0x00000080
93 #define BE_SENSE_INFO_SIZE 258
94 #define BE_ISCSI_PDU_HEADER_SIZE 64
95 #define BE_MIN_MEM_SIZE 16384
96 #define MAX_CMD_SZ 65536
97 #define IIOC_SCSI_DATA 0x05 /* Write Operation */
99 #define INVALID_SESS_HANDLE 0xFFFFFFFF
101 #define BE_ADAPTER_UP 0x00000000
102 #define BE_ADAPTER_LINK_DOWN 0x00000001
104 * hardware needs the async PDU buffers to be posted in multiples of 8
105 * So have atleast 8 of them by default
108 #define HWI_GET_ASYNC_PDU_CTX(phwi, ulp_num) \
109 (phwi->phwi_ctxt->pasync_ctx[ulp_num])
111 /********* Memory BAR register ************/
112 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
114 * Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
115 * Disable" may still globally block interrupts in addition to individual
116 * interrupt masks; a mechanism for the device driver to block all interrupts
117 * atomically without having to arbitrate for the PCI Interrupt Disable bit
120 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */
122 /********* ISR0 Register offset **********/
123 #define CEV_ISR0_OFFSET 0xC18
124 #define CEV_ISR_SIZE 4
127 * Macros for reading/writing a protection domain or CSR registers
131 #define DB_TXULP0_OFFSET 0x40
132 #define DB_RXULP0_OFFSET 0xA0
133 /********* Event Q door bell *************/
134 #define DB_EQ_OFFSET DB_CQ_OFFSET
135 #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
136 /* Clear the interrupt for this eq */
137 #define DB_EQ_CLR_SHIFT (9) /* bit 9 */
139 #define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
140 /* Number of event entries processed */
141 #define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
143 #define DB_EQ_REARM_SHIFT (29) /* bit 29 */
145 /********* Compl Q door bell *************/
146 #define DB_CQ_OFFSET 0x120
147 #define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
148 /* Number of event entries processed */
149 #define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
151 #define DB_CQ_REARM_SHIFT (29) /* bit 29 */
153 #define GET_HWI_CONTROLLER_WS(pc) (pc->phwi_ctrlr)
154 #define HWI_GET_DEF_BUFQ_ID(pc, ulp_num) (((struct hwi_controller *)\
155 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data[ulp_num].id)
156 #define HWI_GET_DEF_HDRQ_ID(pc, ulp_num) (((struct hwi_controller *)\
157 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr[ulp_num].id)
159 #define PAGES_REQUIRED(x) \
160 ((x < PAGE_SIZE) ? 1 : ((x + PAGE_SIZE - 1) / PAGE_SIZE))
162 #define BEISCSI_MSI_NAME 20 /* size of msi_name string */
164 #define MEM_DESCR_OFFSET 7
165 #define BEISCSI_DEFQ_HDR 1
166 #define BEISCSI_DEFQ_DATA 0
168 HWI_MEM_ADDN_CONTEXT,
173 HWI_MEM_TEMPLATE_HDR,
174 HWI_MEM_ASYNC_HEADER_BUF_ULP0,
175 HWI_MEM_ASYNC_DATA_BUF_ULP0,
176 HWI_MEM_ASYNC_HEADER_RING_ULP0,
177 HWI_MEM_ASYNC_DATA_RING_ULP0,
178 HWI_MEM_ASYNC_HEADER_HANDLE_ULP0,
179 HWI_MEM_ASYNC_DATA_HANDLE_ULP0,
180 HWI_MEM_ASYNC_PDU_CONTEXT_ULP0,
181 HWI_MEM_ASYNC_HEADER_BUF_ULP1,
182 HWI_MEM_ASYNC_DATA_BUF_ULP1,
183 HWI_MEM_ASYNC_HEADER_RING_ULP1,
184 HWI_MEM_ASYNC_DATA_RING_ULP1,
185 HWI_MEM_ASYNC_HEADER_HANDLE_ULP1,
186 HWI_MEM_ASYNC_DATA_HANDLE_ULP1,
187 HWI_MEM_ASYNC_PDU_CONTEXT_ULP1,
188 ISCSI_MEM_GLOBAL_HEADER,
192 struct be_bus_address32 {
193 unsigned int address_lo;
194 unsigned int address_hi;
197 struct be_bus_address64 {
198 unsigned long long address;
201 struct be_bus_address {
203 struct be_bus_address32 a32;
204 struct be_bus_address64 a64;
209 struct be_bus_address bus_address; /* Bus address of location */
210 void *virtual_address; /* virtual address to the location */
211 unsigned int size; /* Size required by memory block */
214 struct be_mem_descriptor {
215 unsigned int index; /* Index of this memory parameter */
216 unsigned int category; /* type indicates cached/non-cached */
217 unsigned int num_elements; /* number of elements in this
220 unsigned int alignment_mask; /* Alignment mask for this block */
221 unsigned int size_in_bytes; /* Size required by memory block */
222 struct mem_array *mem_array;
226 unsigned int sgl_index;
229 struct iscsi_task *task;
230 struct iscsi_sge *pfrag;
233 struct hba_parameters {
234 unsigned int ios_per_ctrl;
235 unsigned int cxns_per_ctrl;
236 unsigned int asyncpdus_per_ctrl;
237 unsigned int icds_per_ctrl;
238 unsigned int num_sge_per_io;
239 unsigned int defpdu_hdr_sz;
240 unsigned int defpdu_data_sz;
241 unsigned int num_cq_entries;
242 unsigned int num_eq_entries;
243 unsigned int wrbs_per_cxn;
244 unsigned int crashmode;
245 unsigned int hba_num;
247 unsigned int mgmt_ws_sz;
248 unsigned int hwi_ws_sz;
253 unsigned int dbg_flags;
254 unsigned int num_cxn;
256 unsigned int eq_timer;
258 * These are calculated from other params. They're here
261 unsigned int num_mcc_pages;
262 unsigned int num_mcc_cq_pages;
263 unsigned int num_cq_pages;
264 unsigned int num_eq_pages;
266 unsigned int num_async_pdu_buf_pages;
267 unsigned int num_async_pdu_buf_sgl_pages;
268 unsigned int num_async_pdu_buf_cq_pages;
270 unsigned int num_async_pdu_hdr_pages;
271 unsigned int num_async_pdu_hdr_sgl_pages;
272 unsigned int num_async_pdu_hdr_cq_pages;
274 unsigned int num_sge;
277 struct invalidate_command_table {
282 #define chip_be2(phba) (phba->generation == BE_GEN2)
283 #define chip_be3_r(phba) (phba->generation == BE_GEN3)
284 #define is_chip_be2_be3r(phba) (chip_be3_r(phba) || (chip_be2(phba)))
286 #define BEISCSI_ULP0 0
287 #define BEISCSI_ULP1 1
288 #define BEISCSI_ULP_COUNT 2
289 #define BEISCSI_ULP0_LOADED 0x01
290 #define BEISCSI_ULP1_LOADED 0x02
292 struct hba_parameters params;
293 struct hwi_controller *phwi_ctrlr;
294 unsigned int mem_req[SE_MEM_MAX];
295 /* PCI BAR mapped addresses */
296 u8 __iomem *csr_va; /* CSR */
297 u8 __iomem *db_va; /* Door Bell */
298 u8 __iomem *pci_va; /* PCI Config */
299 struct be_bus_address csr_pa; /* CSR */
300 struct be_bus_address db_pa; /* CSR */
301 struct be_bus_address pci_pa; /* CSR */
302 /* PCI representation of our HBA */
303 struct pci_dev *pcidev;
304 unsigned short asic_revision;
305 unsigned int num_cpus;
306 unsigned int nxt_cqid;
307 struct msix_entry msix_entries[MAX_CPUS];
308 char *msi_name[MAX_CPUS];
310 struct be_mem_descriptor *init_mem;
312 unsigned short io_sgl_alloc_index;
313 unsigned short io_sgl_free_index;
314 unsigned short io_sgl_hndl_avbl;
315 struct sgl_handle **io_sgl_hndl_base;
316 struct sgl_handle **sgl_hndl_array;
318 unsigned short eh_sgl_alloc_index;
319 unsigned short eh_sgl_free_index;
320 unsigned short eh_sgl_hndl_avbl;
321 struct sgl_handle **eh_sgl_hndl_base;
322 spinlock_t io_sgl_lock;
323 spinlock_t mgmt_sgl_lock;
325 spinlock_t async_pdu_lock;
327 unsigned short avlbl_cids;
328 unsigned short cid_alloc;
329 unsigned short cid_free;
330 struct list_head hba_queue;
331 #define BE_MAX_SESSION 2048
332 #define BE_SET_CID_TO_CRI(cri_index, cid) \
333 (phba->cid_to_cri_map[cid] = cri_index)
334 #define BE_GET_CRI_FROM_CID(cid) (phba->cid_to_cri_map[cid])
335 unsigned short cid_to_cri_map[BE_MAX_SESSION];
336 unsigned short *cid_array;
337 struct iscsi_endpoint **ep_array;
338 struct beiscsi_conn **conn_table;
339 struct iscsi_boot_kset *boot_kset;
340 struct Scsi_Host *shost;
341 struct iscsi_iface *ipv4_iface;
342 struct iscsi_iface *ipv6_iface;
345 * group together since they are used most frequently
346 * for cid to cri conversion
348 unsigned int phys_port;
349 unsigned int iscsi_cid_start[BEISCSI_ULP_COUNT];
350 #define BEISCSI_GET_CID_COUNT(phba, ulp_num) \
351 (phba->fw_config.iscsi_cid_count[ulp_num])
352 unsigned int iscsi_cid_count[BEISCSI_ULP_COUNT];
353 unsigned int iscsi_icd_count[BEISCSI_ULP_COUNT];
354 unsigned int iscsi_icd_start[BEISCSI_ULP_COUNT];
355 unsigned int iscsi_chain_start[BEISCSI_ULP_COUNT];
356 unsigned int iscsi_chain_count[BEISCSI_ULP_COUNT];
358 unsigned short iscsi_features;
359 uint16_t dual_ulp_aware;
360 unsigned long ulp_supported;
366 struct delayed_work beiscsi_hw_check_task;
369 u8 mac_address[ETH_ALEN];
370 char fw_ver_str[BEISCSI_VER_STRLEN];
372 struct workqueue_struct *wq; /* The actuak work queue */
373 struct be_ctrl_info ctrl;
374 unsigned int generation;
375 unsigned int interface_handle;
376 struct mgmt_session_info boot_sess;
377 struct invalidate_command_table inv_tbl[128];
379 unsigned int attr_log_enable;
380 int (*iotask_fn)(struct iscsi_task *,
381 struct scatterlist *sg,
382 uint32_t num_sg, uint32_t xferlen,
386 struct beiscsi_session {
387 struct pci_pool *bhs_pool;
391 * struct beiscsi_conn - iscsi connection structure
393 struct beiscsi_conn {
394 struct iscsi_conn *conn;
395 struct beiscsi_hba *phba;
397 u32 beiscsi_conn_cid;
398 struct beiscsi_endpoint *ep;
399 unsigned short login_in_progress;
400 struct wrb_handle *plogin_wrb_handle;
401 struct sgl_handle *plogin_sgl_handle;
402 struct beiscsi_session *beiscsi_sess;
403 struct iscsi_task *task;
406 /* This structure is used by the chip */
407 struct pdu_data_out {
411 * Pseudo amap definition in which each bit of the actual structure is defined
412 * as a byte: used to calculate offset/shift/mask of each field
414 struct amap_pdu_data_out {
415 u8 opcode[6]; /* opcode */
416 u8 rsvd0[2]; /* should be 0 */
418 u8 final_bit; /* F bit */
420 u8 ahs_length[8]; /* no AHS */
422 u8 data_len_lo[16]; /* DataSegmentLength */
424 u8 itt[32]; /* ITT; initiator task tag */
425 u8 ttt[32]; /* TTT; valid for R2T or 0xffffffff */
430 u8 buffer_offset[32];
435 struct iscsi_scsi_req iscsi_hdr;
436 unsigned char pad1[16];
437 struct pdu_data_out iscsi_data_pdu;
438 unsigned char pad2[BE_SENSE_INFO_SIZE -
439 sizeof(struct pdu_data_out)];
442 struct beiscsi_io_task {
443 struct wrb_handle *pwrb_handle;
444 struct sgl_handle *psgl_handle;
445 struct beiscsi_conn *conn;
446 struct scsi_cmnd *scsi_cmnd;
450 unsigned short header_len;
452 struct be_cmd_bhs *cmd_bhs;
453 struct be_bus_address bhs_pa;
454 unsigned short bhs_len;
455 dma_addr_t mtask_addr;
456 uint32_t mtask_data_count;
460 struct be_nonio_bhs {
461 struct iscsi_hdr iscsi_hdr;
462 unsigned char pad1[16];
463 struct pdu_data_out iscsi_data_pdu;
464 unsigned char pad2[BE_SENSE_INFO_SIZE -
465 sizeof(struct pdu_data_out)];
468 struct be_status_bhs {
469 struct iscsi_scsi_req iscsi_hdr;
470 unsigned char pad1[16];
472 * The plus 2 below is to hold the sense info length that gets
475 unsigned char sense_info[BE_SENSE_INFO_SIZE];
483 * Pseudo amap definition in which each bit of the actual structure is defined
484 * as a byte: used to calculate offset/shift/mask of each field
486 struct amap_iscsi_sge {
489 u8 sge_offset[22]; /* DWORD 2 */
490 u8 rsvd0[9]; /* DWORD 2 */
491 u8 last_sge; /* DWORD 2 */
492 u8 len[17]; /* DWORD 3 */
493 u8 rsvd1[15]; /* DWORD 3 */
496 struct beiscsi_offload_params {
500 #define OFFLD_PARAMS_ERL 0x00000003
501 #define OFFLD_PARAMS_DDE 0x00000004
502 #define OFFLD_PARAMS_HDE 0x00000008
503 #define OFFLD_PARAMS_IR2T 0x00000010
504 #define OFFLD_PARAMS_IMD 0x00000020
505 #define OFFLD_PARAMS_DATA_SEQ_INORDER 0x00000040
506 #define OFFLD_PARAMS_PDU_SEQ_INORDER 0x00000080
507 #define OFFLD_PARAMS_MAX_R2T 0x00FFFF00
510 * Pseudo amap definition in which each bit of the actual structure is defined
511 * as a byte: used to calculate offset/shift/mask of each field
513 struct amap_beiscsi_offload_params {
514 u8 max_burst_length[32];
515 u8 max_send_data_segment_length[32];
516 u8 first_burst_length[32];
522 u8 data_seq_inorder[1];
523 u8 pdu_seq_inorder[1];
527 u8 max_recv_data_segment_length[32];
530 /* void hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
531 struct beiscsi_hba *phba, struct sol_cqe *psol);*/
533 struct async_pdu_handle {
534 struct list_head link;
535 struct be_bus_address pa;
537 unsigned int consumed;
539 unsigned char is_header;
541 unsigned long buffer_len;
544 struct hwi_async_entry {
546 unsigned char hdr_received;
547 unsigned char hdr_len;
548 unsigned short bytes_received;
549 unsigned int bytes_needed;
550 struct list_head list;
553 struct list_head header_busy_list;
554 struct list_head data_busy_list;
557 struct hwi_async_pdu_context {
559 struct be_bus_address pa_base;
562 struct async_pdu_handle *handle_base;
564 unsigned int host_write_ptr;
565 unsigned int ep_read_ptr;
566 unsigned int writables;
568 unsigned int free_entries;
569 unsigned int busy_entries;
571 struct list_head free_list;
575 struct be_bus_address pa_base;
578 struct async_pdu_handle *handle_base;
580 unsigned int host_write_ptr;
581 unsigned int ep_read_ptr;
582 unsigned int writables;
584 unsigned int free_entries;
585 unsigned int busy_entries;
586 struct list_head free_list;
589 unsigned int buffer_size;
590 unsigned int num_entries;
591 #define BE_GET_ASYNC_CRI_FROM_CID(cid) (pasync_ctx->cid_to_async_cri_map[cid])
592 unsigned short cid_to_async_cri_map[BE_MAX_SESSION];
594 * This is a varying size list! Do not add anything
597 struct hwi_async_entry *async_entry;
600 #define PDUCQE_CODE_MASK 0x0000003F
601 #define PDUCQE_DPL_MASK 0xFFFF0000
602 #define PDUCQE_INDEX_MASK 0x0000FFFF
604 struct i_t_dpdu_cqe {
609 * Pseudo amap definition in which each bit of the actual structure is defined
610 * as a byte: used to calculate offset/shift/mask of each field
612 struct amap_i_t_dpdu_cqe {
625 struct amap_i_t_dpdu_cqe_v2 {
626 u8 db_addr_hi[32]; /* DWORD 0 */
627 u8 db_addr_lo[32]; /* DWORD 1 */
628 u8 code[6]; /* DWORD 2 */
629 u8 num_cons; /* DWORD 2*/
630 u8 rsvd0[8]; /* DWORD 2 */
631 u8 dpl[17]; /* DWORD 2 */
632 u8 index[16]; /* DWORD 3 */
633 u8 cid[13]; /* DWORD 3 */
634 u8 rsvd1; /* DWORD 3 */
635 u8 final; /* DWORD 3 */
636 u8 valid; /* DWORD 3 */
639 #define CQE_VALID_MASK 0x80000000
640 #define CQE_CODE_MASK 0x0000003F
641 #define CQE_CID_MASK 0x0000FFC0
643 #define EQE_VALID_MASK 0x00000001
644 #define EQE_MAJORCODE_MASK 0x0000000E
645 #define EQE_RESID_MASK 0xFFFF0000
652 * Pseudo amap definition in which each bit of the actual structure is defined
653 * as a byte: used to calculate offset/shift/mask of each field
655 struct amap_eq_entry {
656 u8 valid; /* DWORD 0 */
657 u8 major_code[3]; /* DWORD 0 */
658 u8 minor_code[12]; /* DWORD 0 */
659 u8 resource_id[16]; /* DWORD 0 */
668 * Pseudo amap definition in which each bit of the actual structure is defined
669 * as a byte: used to calculate offset/shift/mask of each field
680 void beiscsi_process_eq(struct beiscsi_hba *phba);
686 #define WRB_TYPE_MASK 0xF0000000
687 #define SKH_WRB_TYPE_OFFSET 27
688 #define BE_WRB_TYPE_OFFSET 28
690 #define ADAPTER_SET_WRB_TYPE(pwrb, wrb_type, type_offset) \
691 (pwrb->dw[0] |= (wrb_type << type_offset))
694 * Pseudo amap definition in which each bit of the actual structure is defined
695 * as a byte: used to calculate offset/shift/mask of each field
697 struct amap_iscsi_wrb {
698 u8 lun[14]; /* DWORD 0 */
700 u8 invld; /* DWORD 0 */
701 u8 wrb_idx[8]; /* DWORD 0 */
702 u8 dsp; /* DWORD 0 */
703 u8 dmsg; /* DWORD 0 */
704 u8 undr_run; /* DWORD 0 */
705 u8 over_run; /* DWORD 0 */
706 u8 type[4]; /* DWORD 0 */
707 u8 ptr2nextwrb[8]; /* DWORD 1 */
708 u8 r2t_exp_dtl[24]; /* DWORD 1 */
709 u8 sgl_icd_idx[12]; /* DWORD 2 */
710 u8 rsvd0[20]; /* DWORD 2 */
711 u8 exp_data_sn[32]; /* DWORD 3 */
712 u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */
713 u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */
714 u8 cmdsn_itt[32]; /* DWORD 6 */
715 u8 dif_ref_tag[32]; /* DWORD 7 */
716 u8 sge0_addr_hi[32]; /* DWORD 8 */
717 u8 sge0_addr_lo[32]; /* DWORD 9 */
718 u8 sge0_offset[22]; /* DWORD 10 */
719 u8 pbs; /* DWORD 10 */
720 u8 dif_mode[2]; /* DWORD 10 */
721 u8 rsvd1[6]; /* DWORD 10 */
722 u8 sge0_last; /* DWORD 10 */
723 u8 sge0_len[17]; /* DWORD 11 */
724 u8 dif_meta_tag[14]; /* DWORD 11 */
725 u8 sge0_in_ddr; /* DWORD 11 */
726 u8 sge1_addr_hi[32]; /* DWORD 12 */
727 u8 sge1_addr_lo[32]; /* DWORD 13 */
728 u8 sge1_r2t_offset[22]; /* DWORD 14 */
729 u8 rsvd2[9]; /* DWORD 14 */
730 u8 sge1_last; /* DWORD 14 */
731 u8 sge1_len[17]; /* DWORD 15 */
732 u8 ref_sgl_icd_idx[12]; /* DWORD 15 */
733 u8 rsvd3[2]; /* DWORD 15 */
734 u8 sge1_in_ddr; /* DWORD 15 */
738 struct amap_iscsi_wrb_v2 {
739 u8 r2t_exp_dtl[25]; /* DWORD 0 */
740 u8 rsvd0[2]; /* DWORD 0*/
741 u8 type[5]; /* DWORD 0 */
742 u8 ptr2nextwrb[8]; /* DWORD 1 */
743 u8 wrb_idx[8]; /* DWORD 1 */
744 u8 lun[16]; /* DWORD 1 */
745 u8 sgl_idx[16]; /* DWORD 2 */
746 u8 ref_sgl_icd_idx[16]; /* DWORD 2 */
747 u8 exp_data_sn[32]; /* DWORD 3 */
748 u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */
749 u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */
750 u8 cq_id[16]; /* DWORD 6 */
751 u8 rsvd1[16]; /* DWORD 6 */
752 u8 cmdsn_itt[32]; /* DWORD 7 */
753 u8 sge0_addr_hi[32]; /* DWORD 8 */
754 u8 sge0_addr_lo[32]; /* DWORD 9 */
755 u8 sge0_offset[24]; /* DWORD 10 */
756 u8 rsvd2[7]; /* DWORD 10 */
757 u8 sge0_last; /* DWORD 10 */
758 u8 sge0_len[17]; /* DWORD 11 */
759 u8 rsvd3[7]; /* DWORD 11 */
760 u8 diff_enbl; /* DWORD 11 */
761 u8 u_run; /* DWORD 11 */
762 u8 o_run; /* DWORD 11 */
763 u8 invalid; /* DWORD 11 */
764 u8 dsp; /* DWORD 11 */
765 u8 dmsg; /* DWORD 11 */
766 u8 rsvd4; /* DWORD 11 */
767 u8 lt; /* DWORD 11 */
768 u8 sge1_addr_hi[32]; /* DWORD 12 */
769 u8 sge1_addr_lo[32]; /* DWORD 13 */
770 u8 sge1_r2t_offset[24]; /* DWORD 14 */
771 u8 rsvd5[7]; /* DWORD 14 */
772 u8 sge1_last; /* DWORD 14 */
773 u8 sge1_len[17]; /* DWORD 15 */
774 u8 rsvd6[15]; /* DWORD 15 */
778 struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid);
780 free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle);
782 void beiscsi_process_all_cqs(struct work_struct *work);
783 void beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn,
784 struct iscsi_task *task);
786 static inline bool beiscsi_error(struct beiscsi_hba *phba)
788 return phba->ue_detected || phba->fw_timeout;
796 * Pseudo amap definition in which each bit of the actual structure is defined
797 * as a byte: used to calculate offset/shift/mask of each field
799 struct amap_pdu_nop_out {
800 u8 opcode[6]; /* opcode 0x00 */
801 u8 i_bit; /* I Bit */
802 u8 x_bit; /* reserved; should be 0 */
803 u8 fp_bit_filler1[7];
804 u8 f_bit; /* always 1 */
806 u8 ahs_length[8]; /* no AHS */
808 u8 data_len_lo[16]; /* DataSegmentLength */
810 u8 itt[32]; /* initiator id for ping or 0xffffffff */
811 u8 ttt[32]; /* target id for ping or 0xffffffff */
817 #define PDUBASE_OPCODE_MASK 0x0000003F
818 #define PDUBASE_DATALENHI_MASK 0x0000FF00
819 #define PDUBASE_DATALENLO_MASK 0xFFFF0000
826 * Pseudo amap definition in which each bit of the actual structure is defined
827 * as a byte: used to calculate offset/shift/mask of each field
829 struct amap_pdu_base {
831 u8 i_bit; /* immediate bit */
832 u8 x_bit; /* reserved, always 0 */
833 u8 reserved1[24]; /* opcode-specific fields */
834 u8 ahs_length[8]; /* length units is 4 byte words */
836 u8 data_len_lo[16]; /* DatasegmentLength */
837 u8 lun[64]; /* lun or opcode-specific fields */
838 u8 itt[32]; /* initiator task tag */
842 struct iscsi_target_context_update_wrb {
847 * Pseudo amap definition in which each bit of the actual structure is defined
848 * as a byte: used to calculate offset/shift/mask of each field
850 #define BE_TGT_CTX_UPDT_CMD 0x07
851 struct amap_iscsi_target_context_update_wrb {
852 u8 lun[14]; /* DWORD 0 */
854 u8 invld; /* DWORD 0 */
855 u8 wrb_idx[8]; /* DWORD 0 */
856 u8 dsp; /* DWORD 0 */
857 u8 dmsg; /* DWORD 0 */
858 u8 undr_run; /* DWORD 0 */
859 u8 over_run; /* DWORD 0 */
860 u8 type[4]; /* DWORD 0 */
861 u8 ptr2nextwrb[8]; /* DWORD 1 */
862 u8 max_burst_length[19]; /* DWORD 1 */
863 u8 rsvd0[5]; /* DWORD 1 */
864 u8 rsvd1[15]; /* DWORD 2 */
865 u8 max_send_data_segment_length[17]; /* DWORD 2 */
866 u8 first_burst_length[14]; /* DWORD 3 */
867 u8 rsvd2[2]; /* DWORD 3 */
868 u8 tx_wrbindex_drv_msg[8]; /* DWORD 3 */
869 u8 rsvd3[5]; /* DWORD 3 */
870 u8 session_state[3]; /* DWORD 3 */
871 u8 rsvd4[16]; /* DWORD 4 */
872 u8 tx_jumbo; /* DWORD 4 */
873 u8 hde; /* DWORD 4 */
874 u8 dde; /* DWORD 4 */
875 u8 erl[2]; /* DWORD 4 */
876 u8 domain_id[5]; /* DWORD 4 */
877 u8 mode; /* DWORD 4 */
878 u8 imd; /* DWORD 4 */
879 u8 ir2t; /* DWORD 4 */
880 u8 notpredblq[2]; /* DWORD 4 */
881 u8 compltonack; /* DWORD 4 */
882 u8 stat_sn[32]; /* DWORD 5 */
883 u8 pad_buffer_addr_hi[32]; /* DWORD 6 */
884 u8 pad_buffer_addr_lo[32]; /* DWORD 7 */
885 u8 pad_addr_hi[32]; /* DWORD 8 */
886 u8 pad_addr_lo[32]; /* DWORD 9 */
887 u8 rsvd5[32]; /* DWORD 10 */
888 u8 rsvd6[32]; /* DWORD 11 */
889 u8 rsvd7[32]; /* DWORD 12 */
890 u8 rsvd8[32]; /* DWORD 13 */
891 u8 rsvd9[32]; /* DWORD 14 */
892 u8 rsvd10[32]; /* DWORD 15 */
896 #define BEISCSI_MAX_RECV_DATASEG_LEN (64 * 1024)
897 #define BEISCSI_MAX_CXNS 1
898 struct amap_iscsi_target_context_update_wrb_v2 {
899 u8 max_burst_length[24]; /* DWORD 0 */
900 u8 rsvd0[3]; /* DWORD 0 */
901 u8 type[5]; /* DWORD 0 */
902 u8 ptr2nextwrb[8]; /* DWORD 1 */
903 u8 wrb_idx[8]; /* DWORD 1 */
904 u8 rsvd1[16]; /* DWORD 1 */
905 u8 max_send_data_segment_length[24]; /* DWORD 2 */
906 u8 rsvd2[8]; /* DWORD 2 */
907 u8 first_burst_length[24]; /* DWORD 3 */
908 u8 rsvd3[8]; /* DOWRD 3 */
909 u8 max_r2t[16]; /* DWORD 4 */
910 u8 rsvd4; /* DWORD 4 */
911 u8 hde; /* DWORD 4 */
912 u8 dde; /* DWORD 4 */
913 u8 erl[2]; /* DWORD 4 */
914 u8 rsvd5[6]; /* DWORD 4 */
915 u8 imd; /* DWORD 4 */
916 u8 ir2t; /* DWORD 4 */
917 u8 rsvd6[3]; /* DWORD 4 */
918 u8 stat_sn[32]; /* DWORD 5 */
919 u8 rsvd7[32]; /* DWORD 6 */
920 u8 rsvd8[32]; /* DWORD 7 */
921 u8 max_recv_dataseg_len[24]; /* DWORD 8 */
922 u8 rsvd9[8]; /* DWORD 8 */
923 u8 rsvd10[32]; /* DWORD 9 */
924 u8 rsvd11[32]; /* DWORD 10 */
925 u8 max_cxns[16]; /* DWORD 11 */
926 u8 rsvd12[11]; /* DWORD 11*/
927 u8 invld; /* DWORD 11 */
928 u8 rsvd13;/* DWORD 11*/
929 u8 dmsg; /* DWORD 11 */
930 u8 data_seq_inorder; /* DWORD 11 */
931 u8 pdu_seq_inorder; /* DWORD 11 */
932 u8 rsvd14[32]; /*DWORD 12 */
933 u8 rsvd15[32]; /* DWORD 13 */
934 u8 rsvd16[32]; /* DWORD 14 */
935 u8 rsvd17[32]; /* DWORD 15 */
940 u32 pages; /* queue size in pages */
941 u32 id; /* queue id assigned by beklib */
942 u32 num; /* number of elements in queue */
943 u32 cidx; /* consumer index */
944 u32 pidx; /* producer index -- not used by most rings */
945 u32 item_size; /* size in bytes of one object */
946 u8 ulp_num; /* ULP to which CID binded */
951 void *va; /* The virtual address of the ring. This
952 * should be last to allow 32 & 64 bit debugger
953 * extensions to work.
957 #define BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, cri) \
958 (phwi_ctrlr->wrb_context[cri].ulp_num)
959 struct hwi_wrb_context {
960 struct list_head wrb_handle_list;
961 struct list_head wrb_handle_drvr_list;
962 struct wrb_handle **pwrb_handle_base;
963 struct wrb_handle **pwrb_handle_basestd;
964 struct iscsi_wrb *plast_wrb;
965 unsigned short alloc_index;
966 unsigned short free_index;
967 unsigned short wrb_handles_available;
969 uint8_t ulp_num; /* ULP to which CID binded */
972 struct hwi_controller {
973 struct list_head io_sgl_list;
974 struct list_head eh_sgl_list;
975 struct sgl_handle *psgl_handle_base;
976 unsigned int wrb_mem_index;
978 struct hwi_wrb_context *wrb_context;
979 struct mcc_wrb *pmcc_wrb_base;
980 struct be_ring default_pdu_hdr[BEISCSI_ULP_COUNT];
981 struct be_ring default_pdu_data[BEISCSI_ULP_COUNT];
982 struct hwi_context_memory *phwi_ctxt;
992 HWH_TYPE_INVALID = 0xFFFFFFFF
996 enum hwh_type_enum type;
997 unsigned short wrb_index;
998 unsigned short nxt_wrb_index;
1000 struct iscsi_task *pio_handle;
1001 struct iscsi_wrb *pwrb;
1004 struct hwi_context_memory {
1005 /* Adaptive interrupt coalescing (AIC) info */
1006 u16 min_eqd; /* in usecs */
1007 u16 max_eqd; /* in usecs */
1008 u16 cur_eqd; /* in usecs */
1009 struct be_eq_obj be_eq[MAX_CPUS];
1010 struct be_queue_info be_cq[MAX_CPUS - 1];
1012 struct be_queue_info *be_wrbq;
1013 struct be_queue_info be_def_hdrq[BEISCSI_ULP_COUNT];
1014 struct be_queue_info be_def_dataq[BEISCSI_ULP_COUNT];
1015 struct hwi_async_pdu_context *pasync_ctx[BEISCSI_ULP_COUNT];
1018 /* Logging related definitions */
1019 #define BEISCSI_LOG_INIT 0x0001 /* Initialization events */
1020 #define BEISCSI_LOG_MBOX 0x0002 /* Mailbox Events */
1021 #define BEISCSI_LOG_MISC 0x0004 /* Miscllaneous Events */
1022 #define BEISCSI_LOG_EH 0x0008 /* Error Handler */
1023 #define BEISCSI_LOG_IO 0x0010 /* IO Code Path */
1024 #define BEISCSI_LOG_CONFIG 0x0020 /* CONFIG Code Path */
1026 #define beiscsi_log(phba, level, mask, fmt, arg...) \
1028 uint32_t log_value = phba->attr_log_enable; \
1029 if (((mask) & log_value) || (level[1] <= '3')) \
1030 shost_printk(level, phba->shost, \
1031 fmt, __LINE__, ##arg); \