2 * Copyright (C) 2005 - 2013 Emulex
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Written by: Jayamohan Kallickal (jayamohan.kallickal@emulex.com)
12 * Contact Information:
13 * linux-drivers@emulex.com
17 * Costa Mesa, CA 92626
20 #ifndef _BEISCSI_MAIN_
21 #define _BEISCSI_MAIN_
23 #include <linux/kernel.h>
24 #include <linux/pci.h>
25 #include <linux/if_ether.h>
27 #include <linux/ctype.h>
28 #include <linux/module.h>
29 #include <scsi/scsi.h>
30 #include <scsi/scsi_cmnd.h>
31 #include <scsi/scsi_device.h>
32 #include <scsi/scsi_host.h>
33 #include <scsi/iscsi_proto.h>
34 #include <scsi/libiscsi.h>
35 #include <scsi/scsi_transport_iscsi.h>
37 #define DRV_NAME "be2iscsi"
38 #define BUILD_STR "10.0.467.0"
39 #define BE_NAME "Emulex OneConnect" \
40 "Open-iSCSI Driver version" BUILD_STR
41 #define DRV_DESC BE_NAME " " "Driver"
43 #define BE_VENDOR_ID 0x19A2
44 #define ELX_VENDOR_ID 0x10DF
45 /* DEVICE ID's for BE2 */
46 #define BE_DEVICE_ID1 0x212
47 #define OC_DEVICE_ID1 0x702
48 #define OC_DEVICE_ID2 0x703
50 /* DEVICE ID's for BE3 */
51 #define BE_DEVICE_ID2 0x222
52 #define OC_DEVICE_ID3 0x712
54 /* DEVICE ID for SKH */
55 #define OC_SKH_ID1 0x722
57 #define BE2_IO_DEPTH 1024
58 #define BE2_MAX_SESSIONS 256
59 #define BE2_CMDS_PER_CXN 128
61 #define BE2_NOPOUT_REQ 16
63 #define BE2_DEFPDU_HDR_SZ 64
64 #define BE2_DEFPDU_DATA_SZ 8192
67 #define BEISCSI_MAX_NUM_CPUS 7
68 #define OC_SKH_MAX_NUM_CPUS 31
70 #define BEISCSI_VER_STRLEN 32
72 #define BEISCSI_SGLIST_ELEMENTS 30
74 #define BEISCSI_CMD_PER_LUN 128 /* scsi_host->cmd_per_lun */
75 #define BEISCSI_MAX_SECTORS 2048 /* scsi_host->max_sectors */
76 #define BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE 128 /* Template size per cxn */
78 #define BEISCSI_MAX_CMD_LEN 16 /* scsi_host->max_cmd_len */
79 #define BEISCSI_NUM_MAX_LUN 256 /* scsi_host->max_lun */
80 #define BEISCSI_NUM_DEVICES_SUPPORTED 0x01
81 #define BEISCSI_MAX_FRAGS_INIT 192
82 #define BE_NUM_MSIX_ENTRIES 1
84 #define MPU_EP_CONTROL 0
85 #define MPU_EP_SEMAPHORE 0xac
86 #define BE2_SOFT_RESET 0x5c
87 #define BE2_PCI_ONLINE0 0xb0
88 #define BE2_PCI_ONLINE1 0xb4
89 #define BE2_SET_RESET 0x80
90 #define BE2_MPU_IRAM_ONLINE 0x00000080
92 #define BE_SENSE_INFO_SIZE 258
93 #define BE_ISCSI_PDU_HEADER_SIZE 64
94 #define BE_MIN_MEM_SIZE 16384
95 #define MAX_CMD_SZ 65536
96 #define IIOC_SCSI_DATA 0x05 /* Write Operation */
98 #define INVALID_SESS_HANDLE 0xFFFFFFFF
100 #define BE_ADAPTER_UP 0x00000000
101 #define BE_ADAPTER_LINK_DOWN 0x00000001
103 * hardware needs the async PDU buffers to be posted in multiples of 8
104 * So have atleast 8 of them by default
107 #define HWI_GET_ASYNC_PDU_CTX(phwi, ulp_num) \
108 (phwi->phwi_ctxt->pasync_ctx[ulp_num])
110 /********* Memory BAR register ************/
111 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
113 * Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
114 * Disable" may still globally block interrupts in addition to individual
115 * interrupt masks; a mechanism for the device driver to block all interrupts
116 * atomically without having to arbitrate for the PCI Interrupt Disable bit
119 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */
121 /********* ISR0 Register offset **********/
122 #define CEV_ISR0_OFFSET 0xC18
123 #define CEV_ISR_SIZE 4
126 * Macros for reading/writing a protection domain or CSR registers
130 #define DB_TXULP0_OFFSET 0x40
131 #define DB_RXULP0_OFFSET 0xA0
132 /********* Event Q door bell *************/
133 #define DB_EQ_OFFSET DB_CQ_OFFSET
134 #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
135 /* Clear the interrupt for this eq */
136 #define DB_EQ_CLR_SHIFT (9) /* bit 9 */
138 #define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
139 /* Number of event entries processed */
140 #define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
142 #define DB_EQ_REARM_SHIFT (29) /* bit 29 */
144 /********* Compl Q door bell *************/
145 #define DB_CQ_OFFSET 0x120
146 #define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
147 /* Number of event entries processed */
148 #define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
150 #define DB_CQ_REARM_SHIFT (29) /* bit 29 */
152 #define GET_HWI_CONTROLLER_WS(pc) (pc->phwi_ctrlr)
153 #define HWI_GET_DEF_BUFQ_ID(pc, ulp_num) (((struct hwi_controller *)\
154 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data[ulp_num].id)
155 #define HWI_GET_DEF_HDRQ_ID(pc, ulp_num) (((struct hwi_controller *)\
156 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr[ulp_num].id)
158 #define PAGES_REQUIRED(x) \
159 ((x < PAGE_SIZE) ? 1 : ((x + PAGE_SIZE - 1) / PAGE_SIZE))
161 #define BEISCSI_MSI_NAME 20 /* size of msi_name string */
163 #define MEM_DESCR_OFFSET 8
164 #define BEISCSI_DEFQ_HDR 1
165 #define BEISCSI_DEFQ_DATA 0
167 HWI_MEM_ADDN_CONTEXT,
172 HWI_MEM_TEMPLATE_HDR_ULP0,
173 HWI_MEM_ASYNC_HEADER_BUF_ULP0, /* 6 */
174 HWI_MEM_ASYNC_DATA_BUF_ULP0,
175 HWI_MEM_ASYNC_HEADER_RING_ULP0,
176 HWI_MEM_ASYNC_DATA_RING_ULP0,
177 HWI_MEM_ASYNC_HEADER_HANDLE_ULP0,
178 HWI_MEM_ASYNC_DATA_HANDLE_ULP0, /* 11 */
179 HWI_MEM_ASYNC_PDU_CONTEXT_ULP0,
180 HWI_MEM_TEMPLATE_HDR_ULP1,
181 HWI_MEM_ASYNC_HEADER_BUF_ULP1, /* 14 */
182 HWI_MEM_ASYNC_DATA_BUF_ULP1,
183 HWI_MEM_ASYNC_HEADER_RING_ULP1,
184 HWI_MEM_ASYNC_DATA_RING_ULP1,
185 HWI_MEM_ASYNC_HEADER_HANDLE_ULP1,
186 HWI_MEM_ASYNC_DATA_HANDLE_ULP1, /* 19 */
187 HWI_MEM_ASYNC_PDU_CONTEXT_ULP1,
188 ISCSI_MEM_GLOBAL_HEADER,
192 struct be_bus_address32 {
193 unsigned int address_lo;
194 unsigned int address_hi;
197 struct be_bus_address64 {
198 unsigned long long address;
201 struct be_bus_address {
203 struct be_bus_address32 a32;
204 struct be_bus_address64 a64;
209 struct be_bus_address bus_address; /* Bus address of location */
210 void *virtual_address; /* virtual address to the location */
211 unsigned int size; /* Size required by memory block */
214 struct be_mem_descriptor {
215 unsigned int index; /* Index of this memory parameter */
216 unsigned int category; /* type indicates cached/non-cached */
217 unsigned int num_elements; /* number of elements in this
220 unsigned int alignment_mask; /* Alignment mask for this block */
221 unsigned int size_in_bytes; /* Size required by memory block */
222 struct mem_array *mem_array;
226 unsigned int sgl_index;
229 struct iscsi_task *task;
230 struct iscsi_sge *pfrag;
233 struct hba_parameters {
234 unsigned int ios_per_ctrl;
235 unsigned int cxns_per_ctrl;
236 unsigned int asyncpdus_per_ctrl;
237 unsigned int icds_per_ctrl;
238 unsigned int num_sge_per_io;
239 unsigned int defpdu_hdr_sz;
240 unsigned int defpdu_data_sz;
241 unsigned int num_cq_entries;
242 unsigned int num_eq_entries;
243 unsigned int wrbs_per_cxn;
244 unsigned int crashmode;
245 unsigned int hba_num;
247 unsigned int mgmt_ws_sz;
248 unsigned int hwi_ws_sz;
253 unsigned int dbg_flags;
254 unsigned int num_cxn;
256 unsigned int eq_timer;
258 * These are calculated from other params. They're here
261 unsigned int num_mcc_pages;
262 unsigned int num_mcc_cq_pages;
263 unsigned int num_cq_pages;
264 unsigned int num_eq_pages;
266 unsigned int num_async_pdu_buf_pages;
267 unsigned int num_async_pdu_buf_sgl_pages;
268 unsigned int num_async_pdu_buf_cq_pages;
270 unsigned int num_async_pdu_hdr_pages;
271 unsigned int num_async_pdu_hdr_sgl_pages;
272 unsigned int num_async_pdu_hdr_cq_pages;
274 unsigned int num_sge;
277 struct invalidate_command_table {
282 #define BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, cri) \
283 (phwi_ctrlr->wrb_context[cri].ulp_num)
284 struct hwi_wrb_context {
285 struct list_head wrb_handle_list;
286 struct list_head wrb_handle_drvr_list;
287 struct wrb_handle **pwrb_handle_base;
288 struct wrb_handle **pwrb_handle_basestd;
289 struct iscsi_wrb *plast_wrb;
290 unsigned short alloc_index;
291 unsigned short free_index;
292 unsigned short wrb_handles_available;
294 uint8_t ulp_num; /* ULP to which CID binded */
295 uint16_t register_set;
296 uint16_t doorbell_format;
297 uint32_t doorbell_offset;
301 #define chip_be2(phba) (phba->generation == BE_GEN2)
302 #define chip_be3_r(phba) (phba->generation == BE_GEN3)
303 #define is_chip_be2_be3r(phba) (chip_be3_r(phba) || (chip_be2(phba)))
305 #define BEISCSI_ULP0 0
306 #define BEISCSI_ULP1 1
307 #define BEISCSI_ULP_COUNT 2
308 #define BEISCSI_ULP0_LOADED 0x01
309 #define BEISCSI_ULP1_LOADED 0x02
311 struct hba_parameters params;
312 struct hwi_controller *phwi_ctrlr;
313 unsigned int mem_req[SE_MEM_MAX];
314 /* PCI BAR mapped addresses */
315 u8 __iomem *csr_va; /* CSR */
316 u8 __iomem *db_va; /* Door Bell */
317 u8 __iomem *pci_va; /* PCI Config */
318 struct be_bus_address csr_pa; /* CSR */
319 struct be_bus_address db_pa; /* CSR */
320 struct be_bus_address pci_pa; /* CSR */
321 /* PCI representation of our HBA */
322 struct pci_dev *pcidev;
323 unsigned short asic_revision;
324 unsigned int num_cpus;
325 unsigned int nxt_cqid;
326 struct msix_entry msix_entries[MAX_CPUS];
327 char *msi_name[MAX_CPUS];
329 struct be_mem_descriptor *init_mem;
331 unsigned short io_sgl_alloc_index;
332 unsigned short io_sgl_free_index;
333 unsigned short io_sgl_hndl_avbl;
334 struct sgl_handle **io_sgl_hndl_base;
335 struct sgl_handle **sgl_hndl_array;
337 unsigned short eh_sgl_alloc_index;
338 unsigned short eh_sgl_free_index;
339 unsigned short eh_sgl_hndl_avbl;
340 struct sgl_handle **eh_sgl_hndl_base;
341 spinlock_t io_sgl_lock;
342 spinlock_t mgmt_sgl_lock;
344 spinlock_t async_pdu_lock;
346 unsigned short avlbl_cids;
347 unsigned short cid_alloc;
348 unsigned short cid_free;
349 struct list_head hba_queue;
350 #define BE_MAX_SESSION 2048
351 #define BE_SET_CID_TO_CRI(cri_index, cid) \
352 (phba->cid_to_cri_map[cid] = cri_index)
353 #define BE_GET_CRI_FROM_CID(cid) (phba->cid_to_cri_map[cid])
354 unsigned short cid_to_cri_map[BE_MAX_SESSION];
355 unsigned short *cid_array;
356 struct iscsi_endpoint **ep_array;
357 struct beiscsi_conn **conn_table;
358 struct iscsi_boot_kset *boot_kset;
359 struct Scsi_Host *shost;
360 struct iscsi_iface *ipv4_iface;
361 struct iscsi_iface *ipv6_iface;
364 * group together since they are used most frequently
365 * for cid to cri conversion
367 unsigned int phys_port;
368 unsigned int iscsi_cid_start[BEISCSI_ULP_COUNT];
369 #define BEISCSI_GET_CID_COUNT(phba, ulp_num) \
370 (phba->fw_config.iscsi_cid_count[ulp_num])
371 unsigned int iscsi_cid_count[BEISCSI_ULP_COUNT];
372 unsigned int iscsi_icd_count[BEISCSI_ULP_COUNT];
373 unsigned int iscsi_icd_start[BEISCSI_ULP_COUNT];
374 unsigned int iscsi_chain_start[BEISCSI_ULP_COUNT];
375 unsigned int iscsi_chain_count[BEISCSI_ULP_COUNT];
377 unsigned short iscsi_features;
378 uint16_t dual_ulp_aware;
379 unsigned long ulp_supported;
385 struct delayed_work beiscsi_hw_check_task;
388 u8 mac_address[ETH_ALEN];
389 char fw_ver_str[BEISCSI_VER_STRLEN];
391 struct workqueue_struct *wq; /* The actuak work queue */
392 struct be_ctrl_info ctrl;
393 unsigned int generation;
394 unsigned int interface_handle;
395 struct mgmt_session_info boot_sess;
396 struct invalidate_command_table inv_tbl[128];
398 unsigned int attr_log_enable;
399 int (*iotask_fn)(struct iscsi_task *,
400 struct scatterlist *sg,
401 uint32_t num_sg, uint32_t xferlen,
405 struct beiscsi_session {
406 struct pci_pool *bhs_pool;
410 * struct beiscsi_conn - iscsi connection structure
412 struct beiscsi_conn {
413 struct iscsi_conn *conn;
414 struct beiscsi_hba *phba;
416 u32 beiscsi_conn_cid;
417 struct beiscsi_endpoint *ep;
418 unsigned short login_in_progress;
419 struct wrb_handle *plogin_wrb_handle;
420 struct sgl_handle *plogin_sgl_handle;
421 struct beiscsi_session *beiscsi_sess;
422 struct iscsi_task *task;
425 /* This structure is used by the chip */
426 struct pdu_data_out {
430 * Pseudo amap definition in which each bit of the actual structure is defined
431 * as a byte: used to calculate offset/shift/mask of each field
433 struct amap_pdu_data_out {
434 u8 opcode[6]; /* opcode */
435 u8 rsvd0[2]; /* should be 0 */
437 u8 final_bit; /* F bit */
439 u8 ahs_length[8]; /* no AHS */
441 u8 data_len_lo[16]; /* DataSegmentLength */
443 u8 itt[32]; /* ITT; initiator task tag */
444 u8 ttt[32]; /* TTT; valid for R2T or 0xffffffff */
449 u8 buffer_offset[32];
454 struct iscsi_scsi_req iscsi_hdr;
455 unsigned char pad1[16];
456 struct pdu_data_out iscsi_data_pdu;
457 unsigned char pad2[BE_SENSE_INFO_SIZE -
458 sizeof(struct pdu_data_out)];
461 struct beiscsi_io_task {
462 struct wrb_handle *pwrb_handle;
463 struct sgl_handle *psgl_handle;
464 struct beiscsi_conn *conn;
465 struct scsi_cmnd *scsi_cmnd;
469 unsigned short header_len;
471 struct be_cmd_bhs *cmd_bhs;
472 struct be_bus_address bhs_pa;
473 unsigned short bhs_len;
474 dma_addr_t mtask_addr;
475 uint32_t mtask_data_count;
479 struct be_nonio_bhs {
480 struct iscsi_hdr iscsi_hdr;
481 unsigned char pad1[16];
482 struct pdu_data_out iscsi_data_pdu;
483 unsigned char pad2[BE_SENSE_INFO_SIZE -
484 sizeof(struct pdu_data_out)];
487 struct be_status_bhs {
488 struct iscsi_scsi_req iscsi_hdr;
489 unsigned char pad1[16];
491 * The plus 2 below is to hold the sense info length that gets
494 unsigned char sense_info[BE_SENSE_INFO_SIZE];
502 * Pseudo amap definition in which each bit of the actual structure is defined
503 * as a byte: used to calculate offset/shift/mask of each field
505 struct amap_iscsi_sge {
508 u8 sge_offset[22]; /* DWORD 2 */
509 u8 rsvd0[9]; /* DWORD 2 */
510 u8 last_sge; /* DWORD 2 */
511 u8 len[17]; /* DWORD 3 */
512 u8 rsvd1[15]; /* DWORD 3 */
515 struct beiscsi_offload_params {
519 #define OFFLD_PARAMS_ERL 0x00000003
520 #define OFFLD_PARAMS_DDE 0x00000004
521 #define OFFLD_PARAMS_HDE 0x00000008
522 #define OFFLD_PARAMS_IR2T 0x00000010
523 #define OFFLD_PARAMS_IMD 0x00000020
524 #define OFFLD_PARAMS_DATA_SEQ_INORDER 0x00000040
525 #define OFFLD_PARAMS_PDU_SEQ_INORDER 0x00000080
526 #define OFFLD_PARAMS_MAX_R2T 0x00FFFF00
529 * Pseudo amap definition in which each bit of the actual structure is defined
530 * as a byte: used to calculate offset/shift/mask of each field
532 struct amap_beiscsi_offload_params {
533 u8 max_burst_length[32];
534 u8 max_send_data_segment_length[32];
535 u8 first_burst_length[32];
541 u8 data_seq_inorder[1];
542 u8 pdu_seq_inorder[1];
546 u8 max_recv_data_segment_length[32];
549 /* void hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
550 struct beiscsi_hba *phba, struct sol_cqe *psol);*/
552 struct async_pdu_handle {
553 struct list_head link;
554 struct be_bus_address pa;
556 unsigned int consumed;
558 unsigned char is_header;
560 unsigned long buffer_len;
563 struct hwi_async_entry {
565 unsigned char hdr_received;
566 unsigned char hdr_len;
567 unsigned short bytes_received;
568 unsigned int bytes_needed;
569 struct list_head list;
572 struct list_head header_busy_list;
573 struct list_head data_busy_list;
576 struct hwi_async_pdu_context {
578 struct be_bus_address pa_base;
581 struct async_pdu_handle *handle_base;
583 unsigned int host_write_ptr;
584 unsigned int ep_read_ptr;
585 unsigned int writables;
587 unsigned int free_entries;
588 unsigned int busy_entries;
590 struct list_head free_list;
594 struct be_bus_address pa_base;
597 struct async_pdu_handle *handle_base;
599 unsigned int host_write_ptr;
600 unsigned int ep_read_ptr;
601 unsigned int writables;
603 unsigned int free_entries;
604 unsigned int busy_entries;
605 struct list_head free_list;
608 unsigned int buffer_size;
609 unsigned int num_entries;
610 #define BE_GET_ASYNC_CRI_FROM_CID(cid) (pasync_ctx->cid_to_async_cri_map[cid])
611 unsigned short cid_to_async_cri_map[BE_MAX_SESSION];
613 * This is a varying size list! Do not add anything
616 struct hwi_async_entry *async_entry;
619 #define PDUCQE_CODE_MASK 0x0000003F
620 #define PDUCQE_DPL_MASK 0xFFFF0000
621 #define PDUCQE_INDEX_MASK 0x0000FFFF
623 struct i_t_dpdu_cqe {
628 * Pseudo amap definition in which each bit of the actual structure is defined
629 * as a byte: used to calculate offset/shift/mask of each field
631 struct amap_i_t_dpdu_cqe {
644 struct amap_i_t_dpdu_cqe_v2 {
645 u8 db_addr_hi[32]; /* DWORD 0 */
646 u8 db_addr_lo[32]; /* DWORD 1 */
647 u8 code[6]; /* DWORD 2 */
648 u8 num_cons; /* DWORD 2*/
649 u8 rsvd0[8]; /* DWORD 2 */
650 u8 dpl[17]; /* DWORD 2 */
651 u8 index[16]; /* DWORD 3 */
652 u8 cid[13]; /* DWORD 3 */
653 u8 rsvd1; /* DWORD 3 */
654 u8 final; /* DWORD 3 */
655 u8 valid; /* DWORD 3 */
658 #define CQE_VALID_MASK 0x80000000
659 #define CQE_CODE_MASK 0x0000003F
660 #define CQE_CID_MASK 0x0000FFC0
662 #define EQE_VALID_MASK 0x00000001
663 #define EQE_MAJORCODE_MASK 0x0000000E
664 #define EQE_RESID_MASK 0xFFFF0000
671 * Pseudo amap definition in which each bit of the actual structure is defined
672 * as a byte: used to calculate offset/shift/mask of each field
674 struct amap_eq_entry {
675 u8 valid; /* DWORD 0 */
676 u8 major_code[3]; /* DWORD 0 */
677 u8 minor_code[12]; /* DWORD 0 */
678 u8 resource_id[16]; /* DWORD 0 */
687 * Pseudo amap definition in which each bit of the actual structure is defined
688 * as a byte: used to calculate offset/shift/mask of each field
699 void beiscsi_process_eq(struct beiscsi_hba *phba);
705 #define WRB_TYPE_MASK 0xF0000000
706 #define SKH_WRB_TYPE_OFFSET 27
707 #define BE_WRB_TYPE_OFFSET 28
709 #define ADAPTER_SET_WRB_TYPE(pwrb, wrb_type, type_offset) \
710 (pwrb->dw[0] |= (wrb_type << type_offset))
713 * Pseudo amap definition in which each bit of the actual structure is defined
714 * as a byte: used to calculate offset/shift/mask of each field
716 struct amap_iscsi_wrb {
717 u8 lun[14]; /* DWORD 0 */
719 u8 invld; /* DWORD 0 */
720 u8 wrb_idx[8]; /* DWORD 0 */
721 u8 dsp; /* DWORD 0 */
722 u8 dmsg; /* DWORD 0 */
723 u8 undr_run; /* DWORD 0 */
724 u8 over_run; /* DWORD 0 */
725 u8 type[4]; /* DWORD 0 */
726 u8 ptr2nextwrb[8]; /* DWORD 1 */
727 u8 r2t_exp_dtl[24]; /* DWORD 1 */
728 u8 sgl_icd_idx[12]; /* DWORD 2 */
729 u8 rsvd0[20]; /* DWORD 2 */
730 u8 exp_data_sn[32]; /* DWORD 3 */
731 u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */
732 u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */
733 u8 cmdsn_itt[32]; /* DWORD 6 */
734 u8 dif_ref_tag[32]; /* DWORD 7 */
735 u8 sge0_addr_hi[32]; /* DWORD 8 */
736 u8 sge0_addr_lo[32]; /* DWORD 9 */
737 u8 sge0_offset[22]; /* DWORD 10 */
738 u8 pbs; /* DWORD 10 */
739 u8 dif_mode[2]; /* DWORD 10 */
740 u8 rsvd1[6]; /* DWORD 10 */
741 u8 sge0_last; /* DWORD 10 */
742 u8 sge0_len[17]; /* DWORD 11 */
743 u8 dif_meta_tag[14]; /* DWORD 11 */
744 u8 sge0_in_ddr; /* DWORD 11 */
745 u8 sge1_addr_hi[32]; /* DWORD 12 */
746 u8 sge1_addr_lo[32]; /* DWORD 13 */
747 u8 sge1_r2t_offset[22]; /* DWORD 14 */
748 u8 rsvd2[9]; /* DWORD 14 */
749 u8 sge1_last; /* DWORD 14 */
750 u8 sge1_len[17]; /* DWORD 15 */
751 u8 ref_sgl_icd_idx[12]; /* DWORD 15 */
752 u8 rsvd3[2]; /* DWORD 15 */
753 u8 sge1_in_ddr; /* DWORD 15 */
757 struct amap_iscsi_wrb_v2 {
758 u8 r2t_exp_dtl[25]; /* DWORD 0 */
759 u8 rsvd0[2]; /* DWORD 0*/
760 u8 type[5]; /* DWORD 0 */
761 u8 ptr2nextwrb[8]; /* DWORD 1 */
762 u8 wrb_idx[8]; /* DWORD 1 */
763 u8 lun[16]; /* DWORD 1 */
764 u8 sgl_idx[16]; /* DWORD 2 */
765 u8 ref_sgl_icd_idx[16]; /* DWORD 2 */
766 u8 exp_data_sn[32]; /* DWORD 3 */
767 u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */
768 u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */
769 u8 cq_id[16]; /* DWORD 6 */
770 u8 rsvd1[16]; /* DWORD 6 */
771 u8 cmdsn_itt[32]; /* DWORD 7 */
772 u8 sge0_addr_hi[32]; /* DWORD 8 */
773 u8 sge0_addr_lo[32]; /* DWORD 9 */
774 u8 sge0_offset[24]; /* DWORD 10 */
775 u8 rsvd2[7]; /* DWORD 10 */
776 u8 sge0_last; /* DWORD 10 */
777 u8 sge0_len[17]; /* DWORD 11 */
778 u8 rsvd3[7]; /* DWORD 11 */
779 u8 diff_enbl; /* DWORD 11 */
780 u8 u_run; /* DWORD 11 */
781 u8 o_run; /* DWORD 11 */
782 u8 invalid; /* DWORD 11 */
783 u8 dsp; /* DWORD 11 */
784 u8 dmsg; /* DWORD 11 */
785 u8 rsvd4; /* DWORD 11 */
786 u8 lt; /* DWORD 11 */
787 u8 sge1_addr_hi[32]; /* DWORD 12 */
788 u8 sge1_addr_lo[32]; /* DWORD 13 */
789 u8 sge1_r2t_offset[24]; /* DWORD 14 */
790 u8 rsvd5[7]; /* DWORD 14 */
791 u8 sge1_last; /* DWORD 14 */
792 u8 sge1_len[17]; /* DWORD 15 */
793 u8 rsvd6[15]; /* DWORD 15 */
797 struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid);
799 free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle);
801 void beiscsi_process_all_cqs(struct work_struct *work);
802 void beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn,
803 struct iscsi_task *task);
805 static inline bool beiscsi_error(struct beiscsi_hba *phba)
807 return phba->ue_detected || phba->fw_timeout;
815 * Pseudo amap definition in which each bit of the actual structure is defined
816 * as a byte: used to calculate offset/shift/mask of each field
818 struct amap_pdu_nop_out {
819 u8 opcode[6]; /* opcode 0x00 */
820 u8 i_bit; /* I Bit */
821 u8 x_bit; /* reserved; should be 0 */
822 u8 fp_bit_filler1[7];
823 u8 f_bit; /* always 1 */
825 u8 ahs_length[8]; /* no AHS */
827 u8 data_len_lo[16]; /* DataSegmentLength */
829 u8 itt[32]; /* initiator id for ping or 0xffffffff */
830 u8 ttt[32]; /* target id for ping or 0xffffffff */
836 #define PDUBASE_OPCODE_MASK 0x0000003F
837 #define PDUBASE_DATALENHI_MASK 0x0000FF00
838 #define PDUBASE_DATALENLO_MASK 0xFFFF0000
845 * Pseudo amap definition in which each bit of the actual structure is defined
846 * as a byte: used to calculate offset/shift/mask of each field
848 struct amap_pdu_base {
850 u8 i_bit; /* immediate bit */
851 u8 x_bit; /* reserved, always 0 */
852 u8 reserved1[24]; /* opcode-specific fields */
853 u8 ahs_length[8]; /* length units is 4 byte words */
855 u8 data_len_lo[16]; /* DatasegmentLength */
856 u8 lun[64]; /* lun or opcode-specific fields */
857 u8 itt[32]; /* initiator task tag */
861 struct iscsi_target_context_update_wrb {
866 * Pseudo amap definition in which each bit of the actual structure is defined
867 * as a byte: used to calculate offset/shift/mask of each field
869 #define BE_TGT_CTX_UPDT_CMD 0x07
870 struct amap_iscsi_target_context_update_wrb {
871 u8 lun[14]; /* DWORD 0 */
873 u8 invld; /* DWORD 0 */
874 u8 wrb_idx[8]; /* DWORD 0 */
875 u8 dsp; /* DWORD 0 */
876 u8 dmsg; /* DWORD 0 */
877 u8 undr_run; /* DWORD 0 */
878 u8 over_run; /* DWORD 0 */
879 u8 type[4]; /* DWORD 0 */
880 u8 ptr2nextwrb[8]; /* DWORD 1 */
881 u8 max_burst_length[19]; /* DWORD 1 */
882 u8 rsvd0[5]; /* DWORD 1 */
883 u8 rsvd1[15]; /* DWORD 2 */
884 u8 max_send_data_segment_length[17]; /* DWORD 2 */
885 u8 first_burst_length[14]; /* DWORD 3 */
886 u8 rsvd2[2]; /* DWORD 3 */
887 u8 tx_wrbindex_drv_msg[8]; /* DWORD 3 */
888 u8 rsvd3[5]; /* DWORD 3 */
889 u8 session_state[3]; /* DWORD 3 */
890 u8 rsvd4[16]; /* DWORD 4 */
891 u8 tx_jumbo; /* DWORD 4 */
892 u8 hde; /* DWORD 4 */
893 u8 dde; /* DWORD 4 */
894 u8 erl[2]; /* DWORD 4 */
895 u8 domain_id[5]; /* DWORD 4 */
896 u8 mode; /* DWORD 4 */
897 u8 imd; /* DWORD 4 */
898 u8 ir2t; /* DWORD 4 */
899 u8 notpredblq[2]; /* DWORD 4 */
900 u8 compltonack; /* DWORD 4 */
901 u8 stat_sn[32]; /* DWORD 5 */
902 u8 pad_buffer_addr_hi[32]; /* DWORD 6 */
903 u8 pad_buffer_addr_lo[32]; /* DWORD 7 */
904 u8 pad_addr_hi[32]; /* DWORD 8 */
905 u8 pad_addr_lo[32]; /* DWORD 9 */
906 u8 rsvd5[32]; /* DWORD 10 */
907 u8 rsvd6[32]; /* DWORD 11 */
908 u8 rsvd7[32]; /* DWORD 12 */
909 u8 rsvd8[32]; /* DWORD 13 */
910 u8 rsvd9[32]; /* DWORD 14 */
911 u8 rsvd10[32]; /* DWORD 15 */
915 #define BEISCSI_MAX_RECV_DATASEG_LEN (64 * 1024)
916 #define BEISCSI_MAX_CXNS 1
917 struct amap_iscsi_target_context_update_wrb_v2 {
918 u8 max_burst_length[24]; /* DWORD 0 */
919 u8 rsvd0[3]; /* DWORD 0 */
920 u8 type[5]; /* DWORD 0 */
921 u8 ptr2nextwrb[8]; /* DWORD 1 */
922 u8 wrb_idx[8]; /* DWORD 1 */
923 u8 rsvd1[16]; /* DWORD 1 */
924 u8 max_send_data_segment_length[24]; /* DWORD 2 */
925 u8 rsvd2[8]; /* DWORD 2 */
926 u8 first_burst_length[24]; /* DWORD 3 */
927 u8 rsvd3[8]; /* DOWRD 3 */
928 u8 max_r2t[16]; /* DWORD 4 */
929 u8 rsvd4; /* DWORD 4 */
930 u8 hde; /* DWORD 4 */
931 u8 dde; /* DWORD 4 */
932 u8 erl[2]; /* DWORD 4 */
933 u8 rsvd5[6]; /* DWORD 4 */
934 u8 imd; /* DWORD 4 */
935 u8 ir2t; /* DWORD 4 */
936 u8 rsvd6[3]; /* DWORD 4 */
937 u8 stat_sn[32]; /* DWORD 5 */
938 u8 rsvd7[32]; /* DWORD 6 */
939 u8 rsvd8[32]; /* DWORD 7 */
940 u8 max_recv_dataseg_len[24]; /* DWORD 8 */
941 u8 rsvd9[8]; /* DWORD 8 */
942 u8 rsvd10[32]; /* DWORD 9 */
943 u8 rsvd11[32]; /* DWORD 10 */
944 u8 max_cxns[16]; /* DWORD 11 */
945 u8 rsvd12[11]; /* DWORD 11*/
946 u8 invld; /* DWORD 11 */
947 u8 rsvd13;/* DWORD 11*/
948 u8 dmsg; /* DWORD 11 */
949 u8 data_seq_inorder; /* DWORD 11 */
950 u8 pdu_seq_inorder; /* DWORD 11 */
951 u8 rsvd14[32]; /*DWORD 12 */
952 u8 rsvd15[32]; /* DWORD 13 */
953 u8 rsvd16[32]; /* DWORD 14 */
954 u8 rsvd17[32]; /* DWORD 15 */
959 u32 pages; /* queue size in pages */
960 u32 id; /* queue id assigned by beklib */
961 u32 num; /* number of elements in queue */
962 u32 cidx; /* consumer index */
963 u32 pidx; /* producer index -- not used by most rings */
964 u32 item_size; /* size in bytes of one object */
965 u8 ulp_num; /* ULP to which CID binded */
970 void *va; /* The virtual address of the ring. This
971 * should be last to allow 32 & 64 bit debugger
972 * extensions to work.
976 struct hwi_controller {
977 struct list_head io_sgl_list;
978 struct list_head eh_sgl_list;
979 struct sgl_handle *psgl_handle_base;
980 unsigned int wrb_mem_index;
982 struct hwi_wrb_context *wrb_context;
983 struct mcc_wrb *pmcc_wrb_base;
984 struct be_ring default_pdu_hdr[BEISCSI_ULP_COUNT];
985 struct be_ring default_pdu_data[BEISCSI_ULP_COUNT];
986 struct hwi_context_memory *phwi_ctxt;
996 HWH_TYPE_INVALID = 0xFFFFFFFF
1000 enum hwh_type_enum type;
1001 unsigned short wrb_index;
1002 unsigned short nxt_wrb_index;
1004 struct iscsi_task *pio_handle;
1005 struct iscsi_wrb *pwrb;
1008 struct hwi_context_memory {
1009 /* Adaptive interrupt coalescing (AIC) info */
1010 u16 min_eqd; /* in usecs */
1011 u16 max_eqd; /* in usecs */
1012 u16 cur_eqd; /* in usecs */
1013 struct be_eq_obj be_eq[MAX_CPUS];
1014 struct be_queue_info be_cq[MAX_CPUS - 1];
1016 struct be_queue_info *be_wrbq;
1017 struct be_queue_info be_def_hdrq[BEISCSI_ULP_COUNT];
1018 struct be_queue_info be_def_dataq[BEISCSI_ULP_COUNT];
1019 struct hwi_async_pdu_context *pasync_ctx[BEISCSI_ULP_COUNT];
1022 /* Logging related definitions */
1023 #define BEISCSI_LOG_INIT 0x0001 /* Initialization events */
1024 #define BEISCSI_LOG_MBOX 0x0002 /* Mailbox Events */
1025 #define BEISCSI_LOG_MISC 0x0004 /* Miscllaneous Events */
1026 #define BEISCSI_LOG_EH 0x0008 /* Error Handler */
1027 #define BEISCSI_LOG_IO 0x0010 /* IO Code Path */
1028 #define BEISCSI_LOG_CONFIG 0x0020 /* CONFIG Code Path */
1030 #define beiscsi_log(phba, level, mask, fmt, arg...) \
1032 uint32_t log_value = phba->attr_log_enable; \
1033 if (((mask) & log_value) || (level[1] <= '3')) \
1034 shost_printk(level, phba->shost, \
1035 fmt, __LINE__, ##arg); \