1 #define DRV_NAME "advansys"
2 #define ASC_VERSION "3.4" /* AdvanSys Driver Version */
5 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
7 * Copyright (c) 1995-2000 Advanced System Products, Inc.
8 * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
9 * Copyright (c) 2007 Matthew Wilcox <matthew@wil.cx>
10 * All Rights Reserved.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
19 * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
20 * changed its name to ConnectCom Solutions, Inc.
21 * On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets
24 #include <linux/module.h>
25 #include <linux/string.h>
26 #include <linux/kernel.h>
27 #include <linux/types.h>
28 #include <linux/ioport.h>
29 #include <linux/interrupt.h>
30 #include <linux/delay.h>
31 #include <linux/slab.h>
33 #include <linux/proc_fs.h>
34 #include <linux/init.h>
35 #include <linux/blkdev.h>
36 #include <linux/isa.h>
37 #include <linux/eisa.h>
38 #include <linux/pci.h>
39 #include <linux/spinlock.h>
40 #include <linux/dma-mapping.h>
43 #include <asm/system.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <scsi/scsi_device.h>
48 #include <scsi/scsi_tcq.h>
49 #include <scsi/scsi.h>
50 #include <scsi/scsi_host.h>
54 * 1. Although all of the necessary command mapping places have the
55 * appropriate dma_map.. APIs, the driver still processes its internal
56 * queue using bus_to_virt() and virt_to_bus() which are illegal under
57 * the API. The entire queue processing structure will need to be
58 * altered to fix this.
59 * 2. Need to add memory mapping workaround. Test the memory mapping.
60 * If it doesn't work revert to I/O port access. Can a test be done
62 * 3. Handle an interrupt not working. Keep an interrupt counter in
63 * the interrupt handler. In the timeout function if the interrupt
64 * has not occurred then print a message and run in polled mode.
65 * 4. Need to add support for target mode commands, cf. CAM XPT.
66 * 5. check DMA mapping functions for failure
67 * 6. Use scsi_transport_spi
68 * 7. advansys_info is not safe against multiple simultaneous callers
70 * 9. Add module_param to override ISA/VLB ioport array
72 #warning this driver is still not properly converted to the DMA API
74 /* Enable driver /proc statistics. */
75 #define ADVANSYS_STATS
77 /* Enable driver tracing. */
78 /* #define ADVANSYS_DEBUG */
83 * Any instance where a 32-bit long or pointer type is assumed
84 * for precision or HW defined structures, the following define
85 * types must be used. In Linux the char, short, and int types
86 * are all consistent at 8, 16, and 32 bits respectively. Pointers
87 * and long types are 64 bits on Alpha and UltraSPARC.
89 #define ASC_PADDR __u32 /* Physical/Bus address data type. */
90 #define ASC_VADDR __u32 /* Virtual address data type. */
91 #define ASC_DCNT __u32 /* Unsigned Data count type. */
92 #define ASC_SDCNT __s32 /* Signed Data count type. */
95 * These macros are used to convert a virtual address to a
96 * 32-bit value. This currently can be used on Linux Alpha
97 * which uses 64-bit virtual address but a 32-bit bus address.
98 * This is likely to break in the future, but doing this now
99 * will give us time to change the HW and FW to handle 64-bit
102 #define ASC_VADDR_TO_U32 virt_to_bus
103 #define ASC_U32_TO_VADDR bus_to_virt
105 typedef unsigned char uchar;
115 #define UW_ERR (uint)(0xFFFF)
116 #define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0)
118 #define PCI_VENDOR_ID_ASP 0x10cd
119 #define PCI_DEVICE_ID_ASP_1200A 0x1100
120 #define PCI_DEVICE_ID_ASP_ABP940 0x1200
121 #define PCI_DEVICE_ID_ASP_ABP940U 0x1300
122 #define PCI_DEVICE_ID_ASP_ABP940UW 0x2300
123 #define PCI_DEVICE_ID_38C0800_REV1 0x2500
124 #define PCI_DEVICE_ID_38C1600_REV1 0x2700
127 * Enable CC_VERY_LONG_SG_LIST to support up to 64K element SG lists.
128 * The SRB structure will have to be changed and the ASC_SRB2SCSIQ()
129 * macro re-defined to be able to obtain a ASC_SCSI_Q pointer from the
132 #define CC_VERY_LONG_SG_LIST 0
133 #define ASC_SRB2SCSIQ(srb_ptr) (srb_ptr)
135 #define PortAddr unsigned short /* port address size */
136 #define inp(port) inb(port)
137 #define outp(port, byte) outb((byte), (port))
139 #define inpw(port) inw(port)
140 #define outpw(port, word) outw((word), (port))
142 #define ASC_MAX_SG_QUEUE 7
143 #define ASC_MAX_SG_LIST 255
145 #define ASC_CS_TYPE unsigned short
147 #define ASC_IS_ISA (0x0001)
148 #define ASC_IS_ISAPNP (0x0081)
149 #define ASC_IS_EISA (0x0002)
150 #define ASC_IS_PCI (0x0004)
151 #define ASC_IS_PCI_ULTRA (0x0104)
152 #define ASC_IS_PCMCIA (0x0008)
153 #define ASC_IS_MCA (0x0020)
154 #define ASC_IS_VL (0x0040)
155 #define ASC_IS_WIDESCSI_16 (0x0100)
156 #define ASC_IS_WIDESCSI_32 (0x0200)
157 #define ASC_IS_BIG_ENDIAN (0x8000)
159 #define ASC_CHIP_MIN_VER_VL (0x01)
160 #define ASC_CHIP_MAX_VER_VL (0x07)
161 #define ASC_CHIP_MIN_VER_PCI (0x09)
162 #define ASC_CHIP_MAX_VER_PCI (0x0F)
163 #define ASC_CHIP_VER_PCI_BIT (0x08)
164 #define ASC_CHIP_MIN_VER_ISA (0x11)
165 #define ASC_CHIP_MIN_VER_ISA_PNP (0x21)
166 #define ASC_CHIP_MAX_VER_ISA (0x27)
167 #define ASC_CHIP_VER_ISA_BIT (0x30)
168 #define ASC_CHIP_VER_ISAPNP_BIT (0x20)
169 #define ASC_CHIP_VER_ASYN_BUG (0x21)
170 #define ASC_CHIP_VER_PCI 0x08
171 #define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02)
172 #define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03)
173 #define ASC_CHIP_MIN_VER_EISA (0x41)
174 #define ASC_CHIP_MAX_VER_EISA (0x47)
175 #define ASC_CHIP_VER_EISA_BIT (0x40)
176 #define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
177 #define ASC_MAX_VL_DMA_COUNT (0x07FFFFFFL)
178 #define ASC_MAX_PCI_DMA_COUNT (0xFFFFFFFFL)
179 #define ASC_MAX_ISA_DMA_COUNT (0x00FFFFFFL)
181 #define ASC_SCSI_ID_BITS 3
182 #define ASC_SCSI_TIX_TYPE uchar
183 #define ASC_ALL_DEVICE_BIT_SET 0xFF
184 #define ASC_SCSI_BIT_ID_TYPE uchar
185 #define ASC_MAX_TID 7
186 #define ASC_MAX_LUN 7
187 #define ASC_SCSI_WIDTH_BIT_SET 0xFF
188 #define ASC_MAX_SENSE_LEN 32
189 #define ASC_MIN_SENSE_LEN 14
190 #define ASC_SCSI_RESET_HOLD_TIME_US 60
193 * Narrow boards only support 12-byte commands, while wide boards
194 * extend to 16-byte commands.
196 #define ASC_MAX_CDB_LEN 12
197 #define ADV_MAX_CDB_LEN 16
199 #define MS_SDTR_LEN 0x03
200 #define MS_WDTR_LEN 0x02
202 #define ASC_SG_LIST_PER_Q 7
204 #define QS_READY 0x01
205 #define QS_DISC1 0x02
206 #define QS_DISC2 0x04
208 #define QS_ABORTED 0x40
210 #define QC_NO_CALLBACK 0x01
211 #define QC_SG_SWAP_QUEUE 0x02
212 #define QC_SG_HEAD 0x04
213 #define QC_DATA_IN 0x08
214 #define QC_DATA_OUT 0x10
215 #define QC_URGENT 0x20
216 #define QC_MSG_OUT 0x40
217 #define QC_REQ_SENSE 0x80
218 #define QCSG_SG_XFER_LIST 0x02
219 #define QCSG_SG_XFER_MORE 0x04
220 #define QCSG_SG_XFER_END 0x08
221 #define QD_IN_PROGRESS 0x00
222 #define QD_NO_ERROR 0x01
223 #define QD_ABORTED_BY_HOST 0x02
224 #define QD_WITH_ERROR 0x04
225 #define QD_INVALID_REQUEST 0x80
226 #define QD_INVALID_HOST_NUM 0x81
227 #define QD_INVALID_DEVICE 0x82
228 #define QD_ERR_INTERNAL 0xFF
229 #define QHSTA_NO_ERROR 0x00
230 #define QHSTA_M_SEL_TIMEOUT 0x11
231 #define QHSTA_M_DATA_OVER_RUN 0x12
232 #define QHSTA_M_DATA_UNDER_RUN 0x12
233 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
234 #define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14
235 #define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
236 #define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22
237 #define QHSTA_D_HOST_ABORT_FAILED 0x23
238 #define QHSTA_D_EXE_SCSI_Q_FAILED 0x24
239 #define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
240 #define QHSTA_D_ASPI_NO_BUF_POOL 0x26
241 #define QHSTA_M_WTM_TIMEOUT 0x41
242 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
243 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
244 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
245 #define QHSTA_M_TARGET_STATUS_BUSY 0x45
246 #define QHSTA_M_BAD_TAG_CODE 0x46
247 #define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47
248 #define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
249 #define QHSTA_D_LRAM_CMP_ERROR 0x81
250 #define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
251 #define ASC_FLAG_SCSIQ_REQ 0x01
252 #define ASC_FLAG_BIOS_SCSIQ_REQ 0x02
253 #define ASC_FLAG_BIOS_ASYNC_IO 0x04
254 #define ASC_FLAG_SRB_LINEAR_ADDR 0x08
255 #define ASC_FLAG_WIN16 0x10
256 #define ASC_FLAG_WIN32 0x20
257 #define ASC_FLAG_ISA_OVER_16MB 0x40
258 #define ASC_FLAG_DOS_VM_CALLBACK 0x80
259 #define ASC_TAG_FLAG_EXTRA_BYTES 0x10
260 #define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04
261 #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08
262 #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
263 #define ASC_SCSIQ_CPY_BEG 4
264 #define ASC_SCSIQ_SGHD_CPY_BEG 2
265 #define ASC_SCSIQ_B_FWD 0
266 #define ASC_SCSIQ_B_BWD 1
267 #define ASC_SCSIQ_B_STATUS 2
268 #define ASC_SCSIQ_B_QNO 3
269 #define ASC_SCSIQ_B_CNTL 4
270 #define ASC_SCSIQ_B_SG_QUEUE_CNT 5
271 #define ASC_SCSIQ_D_DATA_ADDR 8
272 #define ASC_SCSIQ_D_DATA_CNT 12
273 #define ASC_SCSIQ_B_SENSE_LEN 20
274 #define ASC_SCSIQ_DONE_INFO_BEG 22
275 #define ASC_SCSIQ_D_SRBPTR 22
276 #define ASC_SCSIQ_B_TARGET_IX 26
277 #define ASC_SCSIQ_B_CDB_LEN 28
278 #define ASC_SCSIQ_B_TAG_CODE 29
279 #define ASC_SCSIQ_W_VM_ID 30
280 #define ASC_SCSIQ_DONE_STATUS 32
281 #define ASC_SCSIQ_HOST_STATUS 33
282 #define ASC_SCSIQ_SCSI_STATUS 34
283 #define ASC_SCSIQ_CDB_BEG 36
284 #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
285 #define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60
286 #define ASC_SCSIQ_B_FIRST_SG_WK_QP 48
287 #define ASC_SCSIQ_B_SG_WK_QP 49
288 #define ASC_SCSIQ_B_SG_WK_IX 50
289 #define ASC_SCSIQ_W_ALT_DC1 52
290 #define ASC_SCSIQ_B_LIST_CNT 6
291 #define ASC_SCSIQ_B_CUR_LIST_CNT 7
292 #define ASC_SGQ_B_SG_CNTL 4
293 #define ASC_SGQ_B_SG_HEAD_QP 5
294 #define ASC_SGQ_B_SG_LIST_CNT 6
295 #define ASC_SGQ_B_SG_CUR_LIST_CNT 7
296 #define ASC_SGQ_LIST_BEG 8
297 #define ASC_DEF_SCSI1_QNG 4
298 #define ASC_MAX_SCSI1_QNG 4
299 #define ASC_DEF_SCSI2_QNG 16
300 #define ASC_MAX_SCSI2_QNG 32
301 #define ASC_TAG_CODE_MASK 0x23
302 #define ASC_STOP_REQ_RISC_STOP 0x01
303 #define ASC_STOP_ACK_RISC_STOP 0x03
304 #define ASC_STOP_CLEAN_UP_BUSY_Q 0x10
305 #define ASC_STOP_CLEAN_UP_DISC_Q 0x20
306 #define ASC_STOP_HOST_REQ_RISC_HALT 0x40
307 #define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
308 #define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
309 #define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID))
310 #define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID)
311 #define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID)
312 #define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
313 #define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6))
315 typedef struct asc_scsiq_1 {
324 ASC_PADDR sense_addr;
329 typedef struct asc_scsiq_2 {
338 typedef struct asc_scsiq_3 {
345 typedef struct asc_scsiq_4 {
346 uchar cdb[ASC_MAX_CDB_LEN];
347 uchar y_first_sg_list_qp;
348 uchar y_working_sg_qp;
349 uchar y_working_sg_ix;
352 ushort x_reconnect_rtn;
353 ASC_PADDR x_saved_data_addr;
354 ASC_DCNT x_saved_data_cnt;
357 typedef struct asc_q_done_info {
366 ASC_DCNT remain_bytes;
369 typedef struct asc_sg_list {
374 typedef struct asc_sg_head {
377 ushort entry_to_copy;
379 ASC_SG_LIST sg_list[0];
382 typedef struct asc_scsi_q {
386 ASC_SG_HEAD *sg_head;
387 ushort remain_sg_entry_cnt;
388 ushort next_sg_index;
391 typedef struct asc_scsi_req_q {
395 ASC_SG_HEAD *sg_head;
398 uchar cdb[ASC_MAX_CDB_LEN];
399 uchar sense[ASC_MIN_SENSE_LEN];
402 typedef struct asc_scsi_bios_req_q {
406 ASC_SG_HEAD *sg_head;
409 uchar cdb[ASC_MAX_CDB_LEN];
410 uchar sense[ASC_MIN_SENSE_LEN];
411 } ASC_SCSI_BIOS_REQ_Q;
413 typedef struct asc_risc_q {
422 typedef struct asc_sg_list_q {
428 uchar sg_cur_list_cnt;
431 typedef struct asc_risc_sg_list_q {
435 ASC_SG_LIST sg_list[7];
436 } ASC_RISC_SG_LIST_Q;
438 #define ASCQ_ERR_Q_STATUS 0x0D
439 #define ASCQ_ERR_CUR_QNG 0x17
440 #define ASCQ_ERR_SG_Q_LINKS 0x18
441 #define ASCQ_ERR_ISR_RE_ENTRY 0x1A
442 #define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B
443 #define ASCQ_ERR_ISR_ON_CRITICAL 0x1C
446 * Warning code values are set in ASC_DVC_VAR 'warn_code'.
448 #define ASC_WARN_NO_ERROR 0x0000
449 #define ASC_WARN_IO_PORT_ROTATE 0x0001
450 #define ASC_WARN_EEPROM_CHKSUM 0x0002
451 #define ASC_WARN_IRQ_MODIFIED 0x0004
452 #define ASC_WARN_AUTO_CONFIG 0x0008
453 #define ASC_WARN_CMD_QNG_CONFLICT 0x0010
454 #define ASC_WARN_EEPROM_RECOVER 0x0020
455 #define ASC_WARN_CFG_MSW_RECOVER 0x0040
458 * Error code values are set in {ASC/ADV}_DVC_VAR 'err_code'.
460 #define ASC_IERR_NO_CARRIER 0x0001 /* No more carrier memory */
461 #define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */
462 #define ASC_IERR_SET_PC_ADDR 0x0004
463 #define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */
464 #define ASC_IERR_ILLEGAL_CONNECTION 0x0010 /* Illegal cable connection */
465 #define ASC_IERR_SINGLE_END_DEVICE 0x0020 /* SE device on DIFF bus */
466 #define ASC_IERR_REVERSED_CABLE 0x0040 /* Narrow flat cable reversed */
467 #define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */
468 #define ASC_IERR_HVD_DEVICE 0x0100 /* HVD device on LVD port */
469 #define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */
470 #define ASC_IERR_NO_BUS_TYPE 0x0400
471 #define ASC_IERR_BIST_PRE_TEST 0x0800 /* BIST pre-test error */
472 #define ASC_IERR_BIST_RAM_TEST 0x1000 /* BIST RAM test error */
473 #define ASC_IERR_BAD_CHIPTYPE 0x2000 /* Invalid chip_type setting */
475 #define ASC_DEF_MAX_TOTAL_QNG (0xF0)
476 #define ASC_MIN_TAG_Q_PER_DVC (0x04)
477 #define ASC_MIN_FREE_Q (0x02)
478 #define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
479 #define ASC_MAX_TOTAL_QNG 240
480 #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
481 #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8
482 #define ASC_MAX_PCI_INRAM_TOTAL_QNG 20
483 #define ASC_MAX_INRAM_TAG_QNG 16
484 #define ASC_IOADR_GAP 0x10
485 #define ASC_MAX_SYN_XFER_NO 16
486 #define ASC_SYN_MAX_OFFSET 0x0F
487 #define ASC_DEF_SDTR_OFFSET 0x0F
488 #define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02
489 #define SYN_XFER_NS_0 25
490 #define SYN_XFER_NS_1 30
491 #define SYN_XFER_NS_2 35
492 #define SYN_XFER_NS_3 40
493 #define SYN_XFER_NS_4 50
494 #define SYN_XFER_NS_5 60
495 #define SYN_XFER_NS_6 70
496 #define SYN_XFER_NS_7 85
497 #define SYN_ULTRA_XFER_NS_0 12
498 #define SYN_ULTRA_XFER_NS_1 19
499 #define SYN_ULTRA_XFER_NS_2 25
500 #define SYN_ULTRA_XFER_NS_3 32
501 #define SYN_ULTRA_XFER_NS_4 38
502 #define SYN_ULTRA_XFER_NS_5 44
503 #define SYN_ULTRA_XFER_NS_6 50
504 #define SYN_ULTRA_XFER_NS_7 57
505 #define SYN_ULTRA_XFER_NS_8 63
506 #define SYN_ULTRA_XFER_NS_9 69
507 #define SYN_ULTRA_XFER_NS_10 75
508 #define SYN_ULTRA_XFER_NS_11 82
509 #define SYN_ULTRA_XFER_NS_12 88
510 #define SYN_ULTRA_XFER_NS_13 94
511 #define SYN_ULTRA_XFER_NS_14 100
512 #define SYN_ULTRA_XFER_NS_15 107
514 typedef struct ext_msg {
520 uchar sdtr_xfer_period;
521 uchar sdtr_req_ack_offset;
536 #define xfer_period u_ext_msg.sdtr.sdtr_xfer_period
537 #define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset
538 #define wdtr_width u_ext_msg.wdtr.wdtr_width
539 #define mdp_b3 u_ext_msg.mdp_b3
540 #define mdp_b2 u_ext_msg.mdp_b2
541 #define mdp_b1 u_ext_msg.mdp_b1
542 #define mdp_b0 u_ext_msg.mdp_b0
544 typedef struct asc_dvc_cfg {
545 ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
546 ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
547 ASC_SCSI_BIT_ID_TYPE disc_enable;
548 ASC_SCSI_BIT_ID_TYPE sdtr_enable;
551 uchar isa_dma_channel;
554 ushort mcode_version;
555 uchar max_tag_qng[ASC_MAX_TID + 1];
557 uchar sdtr_period_offset[ASC_MAX_TID + 1];
558 uchar adapter_info[6];
561 #define ASC_DEF_DVC_CNTL 0xFFFF
562 #define ASC_DEF_CHIP_SCSI_ID 7
563 #define ASC_DEF_ISA_DMA_SPEED 4
564 #define ASC_INIT_STATE_BEG_GET_CFG 0x0001
565 #define ASC_INIT_STATE_END_GET_CFG 0x0002
566 #define ASC_INIT_STATE_BEG_SET_CFG 0x0004
567 #define ASC_INIT_STATE_END_SET_CFG 0x0008
568 #define ASC_INIT_STATE_BEG_LOAD_MC 0x0010
569 #define ASC_INIT_STATE_END_LOAD_MC 0x0020
570 #define ASC_INIT_STATE_BEG_INQUIRY 0x0040
571 #define ASC_INIT_STATE_END_INQUIRY 0x0080
572 #define ASC_INIT_RESET_SCSI_DONE 0x0100
573 #define ASC_INIT_STATE_WITHOUT_EEP 0x8000
574 #define ASC_BUG_FIX_IF_NOT_DWB 0x0001
575 #define ASC_BUG_FIX_ASYN_USE_SYN 0x0002
576 #define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
577 #define ASC_MIN_TAGGED_CMD 7
578 #define ASC_MAX_SCSI_RESET_WAIT 30
580 struct asc_dvc_var; /* Forward Declaration. */
582 typedef struct asc_dvc_var {
588 ASC_SCSI_BIT_ID_TYPE init_sdtr;
589 ASC_SCSI_BIT_ID_TYPE sdtr_done;
590 ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
591 ASC_SCSI_BIT_ID_TYPE unit_not_ready;
592 ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
593 ASC_SCSI_BIT_ID_TYPE start_motor;
594 uchar scsi_reset_wait;
599 uchar in_critical_cnt;
600 uchar last_q_shortage;
602 uchar cur_dvc_qng[ASC_MAX_TID + 1];
603 uchar max_dvc_qng[ASC_MAX_TID + 1];
604 ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
605 ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
606 uchar sdtr_period_tbl[ASC_MAX_SYN_XFER_NO];
608 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
611 uchar dos_int13_table[ASC_MAX_TID + 1];
612 ASC_DCNT max_dma_count;
613 ASC_SCSI_BIT_ID_TYPE no_scam;
614 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
615 uchar max_sdtr_index;
616 uchar host_init_sdtr_index;
617 struct asc_board *drv_ptr;
621 typedef struct asc_dvc_inq_info {
622 uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
625 typedef struct asc_cap_info {
630 typedef struct asc_cap_info_array {
631 ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
632 } ASC_CAP_INFO_ARRAY;
634 #define ASC_MCNTL_NO_SEL_TIMEOUT (ushort)0x0001
635 #define ASC_MCNTL_NULL_TARGET (ushort)0x0002
636 #define ASC_CNTL_INITIATOR (ushort)0x0001
637 #define ASC_CNTL_BIOS_GT_1GB (ushort)0x0002
638 #define ASC_CNTL_BIOS_GT_2_DISK (ushort)0x0004
639 #define ASC_CNTL_BIOS_REMOVABLE (ushort)0x0008
640 #define ASC_CNTL_NO_SCAM (ushort)0x0010
641 #define ASC_CNTL_INT_MULTI_Q (ushort)0x0080
642 #define ASC_CNTL_NO_LUN_SUPPORT (ushort)0x0040
643 #define ASC_CNTL_NO_VERIFY_COPY (ushort)0x0100
644 #define ASC_CNTL_RESET_SCSI (ushort)0x0200
645 #define ASC_CNTL_INIT_INQUIRY (ushort)0x0400
646 #define ASC_CNTL_INIT_VERBOSE (ushort)0x0800
647 #define ASC_CNTL_SCSI_PARITY (ushort)0x1000
648 #define ASC_CNTL_BURST_MODE (ushort)0x2000
649 #define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
650 #define ASC_EEP_DVC_CFG_BEG_VL 2
651 #define ASC_EEP_MAX_DVC_ADDR_VL 15
652 #define ASC_EEP_DVC_CFG_BEG 32
653 #define ASC_EEP_MAX_DVC_ADDR 45
654 #define ASC_EEP_MAX_RETRY 20
657 * These macros keep the chip SCSI id and ISA DMA speed
658 * bitfields in board order. C bitfields aren't portable
659 * between big and little-endian platforms so they are
663 #define ASC_EEP_GET_CHIP_ID(cfg) ((cfg)->id_speed & 0x0f)
664 #define ASC_EEP_GET_DMA_SPD(cfg) (((cfg)->id_speed & 0xf0) >> 4)
665 #define ASC_EEP_SET_CHIP_ID(cfg, sid) \
666 ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
667 #define ASC_EEP_SET_DMA_SPD(cfg, spd) \
668 ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
670 typedef struct asceep_config {
682 uchar id_speed; /* low order 4 bits is chip scsi id */
683 /* high order 4 bits is isa dma speed */
684 uchar dos_int13_table[ASC_MAX_TID + 1];
685 uchar adapter_info[6];
690 #define ASC_EEP_CMD_READ 0x80
691 #define ASC_EEP_CMD_WRITE 0x40
692 #define ASC_EEP_CMD_WRITE_ABLE 0x30
693 #define ASC_EEP_CMD_WRITE_DISABLE 0x00
694 #define ASC_OVERRUN_BSIZE 0x00000048UL
695 #define ASCV_MSGOUT_BEG 0x0000
696 #define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
697 #define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
698 #define ASCV_BREAK_SAVED_CODE (ushort)0x0006
699 #define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8)
700 #define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3)
701 #define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4)
702 #define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8)
703 #define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8)
704 #define ASCV_MAX_DVC_QNG_BEG (ushort)0x0020
705 #define ASCV_BREAK_ADDR (ushort)0x0028
706 #define ASCV_BREAK_NOTIFY_COUNT (ushort)0x002A
707 #define ASCV_BREAK_CONTROL (ushort)0x002C
708 #define ASCV_BREAK_HIT_COUNT (ushort)0x002E
710 #define ASCV_ASCDVC_ERR_CODE_W (ushort)0x0030
711 #define ASCV_MCODE_CHKSUM_W (ushort)0x0032
712 #define ASCV_MCODE_SIZE_W (ushort)0x0034
713 #define ASCV_STOP_CODE_B (ushort)0x0036
714 #define ASCV_DVC_ERR_CODE_B (ushort)0x0037
715 #define ASCV_OVERRUN_PADDR_D (ushort)0x0038
716 #define ASCV_OVERRUN_BSIZE_D (ushort)0x003C
717 #define ASCV_HALTCODE_W (ushort)0x0040
718 #define ASCV_CHKSUM_W (ushort)0x0042
719 #define ASCV_MC_DATE_W (ushort)0x0044
720 #define ASCV_MC_VER_W (ushort)0x0046
721 #define ASCV_NEXTRDY_B (ushort)0x0048
722 #define ASCV_DONENEXT_B (ushort)0x0049
723 #define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
724 #define ASCV_SCSIBUSY_B (ushort)0x004B
725 #define ASCV_Q_DONE_IN_PROGRESS_B (ushort)0x004C
726 #define ASCV_CURCDB_B (ushort)0x004D
727 #define ASCV_RCLUN_B (ushort)0x004E
728 #define ASCV_BUSY_QHEAD_B (ushort)0x004F
729 #define ASCV_DISC1_QHEAD_B (ushort)0x0050
730 #define ASCV_DISC_ENABLE_B (ushort)0x0052
731 #define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
732 #define ASCV_HOSTSCSI_ID_B (ushort)0x0055
733 #define ASCV_MCODE_CNTL_B (ushort)0x0056
734 #define ASCV_NULL_TARGET_B (ushort)0x0057
735 #define ASCV_FREE_Q_HEAD_W (ushort)0x0058
736 #define ASCV_DONE_Q_TAIL_W (ushort)0x005A
737 #define ASCV_FREE_Q_HEAD_B (ushort)(ASCV_FREE_Q_HEAD_W+1)
738 #define ASCV_DONE_Q_TAIL_B (ushort)(ASCV_DONE_Q_TAIL_W+1)
739 #define ASCV_HOST_FLAG_B (ushort)0x005D
740 #define ASCV_TOTAL_READY_Q_B (ushort)0x0064
741 #define ASCV_VER_SERIAL_B (ushort)0x0065
742 #define ASCV_HALTCODE_SAVED_W (ushort)0x0066
743 #define ASCV_WTM_FLAG_B (ushort)0x0068
744 #define ASCV_RISC_FLAG_B (ushort)0x006A
745 #define ASCV_REQ_SG_LIST_QP (ushort)0x006B
746 #define ASC_HOST_FLAG_IN_ISR 0x01
747 #define ASC_HOST_FLAG_ACK_INT 0x02
748 #define ASC_RISC_FLAG_GEN_INT 0x01
749 #define ASC_RISC_FLAG_REQ_SG_LIST 0x02
750 #define IOP_CTRL (0x0F)
751 #define IOP_STATUS (0x0E)
752 #define IOP_INT_ACK IOP_STATUS
753 #define IOP_REG_IFC (0x0D)
754 #define IOP_SYN_OFFSET (0x0B)
755 #define IOP_EXTRA_CONTROL (0x0D)
756 #define IOP_REG_PC (0x0C)
757 #define IOP_RAM_ADDR (0x0A)
758 #define IOP_RAM_DATA (0x08)
759 #define IOP_EEP_DATA (0x06)
760 #define IOP_EEP_CMD (0x07)
761 #define IOP_VERSION (0x03)
762 #define IOP_CONFIG_HIGH (0x04)
763 #define IOP_CONFIG_LOW (0x02)
764 #define IOP_SIG_BYTE (0x01)
765 #define IOP_SIG_WORD (0x00)
766 #define IOP_REG_DC1 (0x0E)
767 #define IOP_REG_DC0 (0x0C)
768 #define IOP_REG_SB (0x0B)
769 #define IOP_REG_DA1 (0x0A)
770 #define IOP_REG_DA0 (0x08)
771 #define IOP_REG_SC (0x09)
772 #define IOP_DMA_SPEED (0x07)
773 #define IOP_REG_FLAG (0x07)
774 #define IOP_FIFO_H (0x06)
775 #define IOP_FIFO_L (0x04)
776 #define IOP_REG_ID (0x05)
777 #define IOP_REG_QP (0x03)
778 #define IOP_REG_IH (0x02)
779 #define IOP_REG_IX (0x01)
780 #define IOP_REG_AX (0x00)
781 #define IFC_REG_LOCK (0x00)
782 #define IFC_REG_UNLOCK (0x09)
783 #define IFC_WR_EN_FILTER (0x10)
784 #define IFC_RD_NO_EEPROM (0x10)
785 #define IFC_SLEW_RATE (0x20)
786 #define IFC_ACT_NEG (0x40)
787 #define IFC_INP_FILTER (0x80)
788 #define IFC_INIT_DEFAULT (IFC_ACT_NEG | IFC_REG_UNLOCK)
789 #define SC_SEL (uchar)(0x80)
790 #define SC_BSY (uchar)(0x40)
791 #define SC_ACK (uchar)(0x20)
792 #define SC_REQ (uchar)(0x10)
793 #define SC_ATN (uchar)(0x08)
794 #define SC_IO (uchar)(0x04)
795 #define SC_CD (uchar)(0x02)
796 #define SC_MSG (uchar)(0x01)
797 #define SEC_SCSI_CTL (uchar)(0x80)
798 #define SEC_ACTIVE_NEGATE (uchar)(0x40)
799 #define SEC_SLEW_RATE (uchar)(0x20)
800 #define SEC_ENABLE_FILTER (uchar)(0x10)
801 #define ASC_HALT_EXTMSG_IN (ushort)0x8000
802 #define ASC_HALT_CHK_CONDITION (ushort)0x8100
803 #define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
804 #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX (ushort)0x8300
805 #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX (ushort)0x8400
806 #define ASC_HALT_SDTR_REJECTED (ushort)0x4000
807 #define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
808 #define ASC_MAX_QNO 0xF8
809 #define ASC_DATA_SEC_BEG (ushort)0x0080
810 #define ASC_DATA_SEC_END (ushort)0x0080
811 #define ASC_CODE_SEC_BEG (ushort)0x0080
812 #define ASC_CODE_SEC_END (ushort)0x0080
813 #define ASC_QADR_BEG (0x4000)
814 #define ASC_QADR_USED (ushort)(ASC_MAX_QNO * 64)
815 #define ASC_QADR_END (ushort)0x7FFF
816 #define ASC_QLAST_ADR (ushort)0x7FC0
817 #define ASC_QBLK_SIZE 0x40
818 #define ASC_BIOS_DATA_QBEG 0xF8
819 #define ASC_MIN_ACTIVE_QNO 0x01
820 #define ASC_QLINK_END 0xFF
821 #define ASC_EEPROM_WORDS 0x10
822 #define ASC_MAX_MGS_LEN 0x10
823 #define ASC_BIOS_ADDR_DEF 0xDC00
824 #define ASC_BIOS_SIZE 0x3800
825 #define ASC_BIOS_RAM_OFF 0x3800
826 #define ASC_BIOS_RAM_SIZE 0x800
827 #define ASC_BIOS_MIN_ADDR 0xC000
828 #define ASC_BIOS_MAX_ADDR 0xEC00
829 #define ASC_BIOS_BANK_SIZE 0x0400
830 #define ASC_MCODE_START_ADDR 0x0080
831 #define ASC_CFG0_HOST_INT_ON 0x0020
832 #define ASC_CFG0_BIOS_ON 0x0040
833 #define ASC_CFG0_VERA_BURST_ON 0x0080
834 #define ASC_CFG0_SCSI_PARITY_ON 0x0800
835 #define ASC_CFG1_SCSI_TARGET_ON 0x0080
836 #define ASC_CFG1_LRAM_8BITS_ON 0x0800
837 #define ASC_CFG_MSW_CLR_MASK 0x3080
838 #define CSW_TEST1 (ASC_CS_TYPE)0x8000
839 #define CSW_AUTO_CONFIG (ASC_CS_TYPE)0x4000
840 #define CSW_RESERVED1 (ASC_CS_TYPE)0x2000
841 #define CSW_IRQ_WRITTEN (ASC_CS_TYPE)0x1000
842 #define CSW_33MHZ_SELECTED (ASC_CS_TYPE)0x0800
843 #define CSW_TEST2 (ASC_CS_TYPE)0x0400
844 #define CSW_TEST3 (ASC_CS_TYPE)0x0200
845 #define CSW_RESERVED2 (ASC_CS_TYPE)0x0100
846 #define CSW_DMA_DONE (ASC_CS_TYPE)0x0080
847 #define CSW_FIFO_RDY (ASC_CS_TYPE)0x0040
848 #define CSW_EEP_READ_DONE (ASC_CS_TYPE)0x0020
849 #define CSW_HALTED (ASC_CS_TYPE)0x0010
850 #define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
851 #define CSW_PARITY_ERR (ASC_CS_TYPE)0x0004
852 #define CSW_SCSI_RESET_LATCH (ASC_CS_TYPE)0x0002
853 #define CSW_INT_PENDING (ASC_CS_TYPE)0x0001
854 #define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
855 #define CIW_INT_ACK (ASC_CS_TYPE)0x0100
856 #define CIW_TEST1 (ASC_CS_TYPE)0x0200
857 #define CIW_TEST2 (ASC_CS_TYPE)0x0400
858 #define CIW_SEL_33MHZ (ASC_CS_TYPE)0x0800
859 #define CIW_IRQ_ACT (ASC_CS_TYPE)0x1000
860 #define CC_CHIP_RESET (uchar)0x80
861 #define CC_SCSI_RESET (uchar)0x40
862 #define CC_HALT (uchar)0x20
863 #define CC_SINGLE_STEP (uchar)0x10
864 #define CC_DMA_ABLE (uchar)0x08
865 #define CC_TEST (uchar)0x04
866 #define CC_BANK_ONE (uchar)0x02
867 #define CC_DIAG (uchar)0x01
868 #define ASC_1000_ID0W 0x04C1
869 #define ASC_1000_ID0W_FIX 0x00C1
870 #define ASC_1000_ID1B 0x25
871 #define ASC_EISA_REV_IOP_MASK (0x0C83)
872 #define ASC_EISA_CFG_IOP_MASK (0x0C86)
873 #define ASC_GET_EISA_SLOT(iop) (PortAddr)((iop) & 0xF000)
874 #define INS_HALTINT (ushort)0x6281
875 #define INS_HALT (ushort)0x6280
876 #define INS_SINT (ushort)0x6200
877 #define INS_RFLAG_WTM (ushort)0x7380
878 #define ASC_MC_SAVE_CODE_WSIZE 0x500
879 #define ASC_MC_SAVE_DATA_WSIZE 0x40
881 typedef struct asc_mc_saved {
882 ushort data[ASC_MC_SAVE_DATA_WSIZE];
883 ushort code[ASC_MC_SAVE_CODE_WSIZE];
886 #define AscGetQDoneInProgress(port) AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
887 #define AscPutQDoneInProgress(port, val) AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
888 #define AscGetVarFreeQHead(port) AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
889 #define AscGetVarDoneQTail(port) AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
890 #define AscPutVarFreeQHead(port, val) AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
891 #define AscPutVarDoneQTail(port, val) AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
892 #define AscGetRiscVarFreeQHead(port) AscReadLramByte((port), ASCV_NEXTRDY_B)
893 #define AscGetRiscVarDoneQTail(port) AscReadLramByte((port), ASCV_DONENEXT_B)
894 #define AscPutRiscVarFreeQHead(port, val) AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
895 #define AscPutRiscVarDoneQTail(port, val) AscWriteLramByte((port), ASCV_DONENEXT_B, val)
896 #define AscPutMCodeSDTRDoneAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data))
897 #define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id))
898 #define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data)
899 #define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id))
900 #define AscSynIndexToPeriod(index) (uchar)(asc_dvc->sdtr_period_tbl[ (index) ])
901 #define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE)
902 #define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD)
903 #define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION)
904 #define AscGetChipCfgLsw(port) (ushort)inpw((port)+IOP_CONFIG_LOW)
905 #define AscGetChipCfgMsw(port) (ushort)inpw((port)+IOP_CONFIG_HIGH)
906 #define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data)
907 #define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data)
908 #define AscGetChipEEPCmd(port) (uchar)inp((port)+IOP_EEP_CMD)
909 #define AscSetChipEEPCmd(port, data) outp((port)+IOP_EEP_CMD, data)
910 #define AscGetChipEEPData(port) (ushort)inpw((port)+IOP_EEP_DATA)
911 #define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data)
912 #define AscGetChipLramAddr(port) (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
913 #define AscSetChipLramAddr(port, addr) outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
914 #define AscGetChipLramData(port) (ushort)inpw((port)+IOP_RAM_DATA)
915 #define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data)
916 #define AscGetChipIFC(port) (uchar)inp((port)+IOP_REG_IFC)
917 #define AscSetChipIFC(port, data) outp((port)+IOP_REG_IFC, data)
918 #define AscGetChipStatus(port) (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
919 #define AscSetChipStatus(port, cs_val) outpw((port)+IOP_STATUS, cs_val)
920 #define AscGetChipControl(port) (uchar)inp((port)+IOP_CTRL)
921 #define AscSetChipControl(port, cc_val) outp((port)+IOP_CTRL, cc_val)
922 #define AscGetChipSyn(port) (uchar)inp((port)+IOP_SYN_OFFSET)
923 #define AscSetChipSyn(port, data) outp((port)+IOP_SYN_OFFSET, data)
924 #define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data)
925 #define AscGetPCAddr(port) (ushort)inpw((port)+IOP_REG_PC)
926 #define AscIsIntPending(port) (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
927 #define AscGetChipScsiID(port) ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
928 #define AscGetExtraControl(port) (uchar)inp((port)+IOP_EXTRA_CONTROL)
929 #define AscSetExtraControl(port, data) outp((port)+IOP_EXTRA_CONTROL, data)
930 #define AscReadChipAX(port) (ushort)inpw((port)+IOP_REG_AX)
931 #define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data)
932 #define AscReadChipIX(port) (uchar)inp((port)+IOP_REG_IX)
933 #define AscWriteChipIX(port, data) outp((port)+IOP_REG_IX, data)
934 #define AscReadChipIH(port) (ushort)inpw((port)+IOP_REG_IH)
935 #define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data)
936 #define AscReadChipQP(port) (uchar)inp((port)+IOP_REG_QP)
937 #define AscWriteChipQP(port, data) outp((port)+IOP_REG_QP, data)
938 #define AscReadChipFIFO_L(port) (ushort)inpw((port)+IOP_REG_FIFO_L)
939 #define AscWriteChipFIFO_L(port, data) outpw((port)+IOP_REG_FIFO_L, data)
940 #define AscReadChipFIFO_H(port) (ushort)inpw((port)+IOP_REG_FIFO_H)
941 #define AscWriteChipFIFO_H(port, data) outpw((port)+IOP_REG_FIFO_H, data)
942 #define AscReadChipDmaSpeed(port) (uchar)inp((port)+IOP_DMA_SPEED)
943 #define AscWriteChipDmaSpeed(port, data) outp((port)+IOP_DMA_SPEED, data)
944 #define AscReadChipDA0(port) (ushort)inpw((port)+IOP_REG_DA0)
945 #define AscWriteChipDA0(port) outpw((port)+IOP_REG_DA0, data)
946 #define AscReadChipDA1(port) (ushort)inpw((port)+IOP_REG_DA1)
947 #define AscWriteChipDA1(port) outpw((port)+IOP_REG_DA1, data)
948 #define AscReadChipDC0(port) (ushort)inpw((port)+IOP_REG_DC0)
949 #define AscWriteChipDC0(port) outpw((port)+IOP_REG_DC0, data)
950 #define AscReadChipDC1(port) (ushort)inpw((port)+IOP_REG_DC1)
951 #define AscWriteChipDC1(port) outpw((port)+IOP_REG_DC1, data)
952 #define AscReadChipDvcID(port) (uchar)inp((port)+IOP_REG_ID)
953 #define AscWriteChipDvcID(port, data) outp((port)+IOP_REG_ID, data)
956 * Portable Data Types
958 * Any instance where a 32-bit long or pointer type is assumed
959 * for precision or HW defined structures, the following define
960 * types must be used. In Linux the char, short, and int types
961 * are all consistent at 8, 16, and 32 bits respectively. Pointers
962 * and long types are 64 bits on Alpha and UltraSPARC.
964 #define ADV_PADDR __u32 /* Physical address data type. */
965 #define ADV_VADDR __u32 /* Virtual address data type. */
966 #define ADV_DCNT __u32 /* Unsigned Data count type. */
967 #define ADV_SDCNT __s32 /* Signed Data count type. */
970 * These macros are used to convert a virtual address to a
971 * 32-bit value. This currently can be used on Linux Alpha
972 * which uses 64-bit virtual address but a 32-bit bus address.
973 * This is likely to break in the future, but doing this now
974 * will give us time to change the HW and FW to handle 64-bit
977 #define ADV_VADDR_TO_U32 virt_to_bus
978 #define ADV_U32_TO_VADDR bus_to_virt
980 #define AdvPortAddr void __iomem * /* Virtual memory address size */
983 * Define Adv Library required memory access macros.
985 #define ADV_MEM_READB(addr) readb(addr)
986 #define ADV_MEM_READW(addr) readw(addr)
987 #define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
988 #define ADV_MEM_WRITEW(addr, word) writew(word, addr)
989 #define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
991 #define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 15)
994 * Define total number of simultaneous maximum element scatter-gather
995 * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
996 * maximum number of outstanding commands per wide host adapter. Each
997 * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
998 * elements. Allow each command to have at least one ADV_SG_BLOCK structure.
999 * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
1000 * structures or 255 scatter-gather elements.
1003 #define ADV_TOT_SG_BLOCK ASC_DEF_MAX_HOST_QNG
1006 * Define Adv Library required maximum number of scatter-gather
1007 * elements per request.
1009 #define ADV_MAX_SG_LIST 255
1011 /* Number of SG blocks needed. */
1012 #define ADV_NUM_SG_BLOCK \
1013 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK)
1015 /* Total contiguous memory needed for SG blocks. */
1016 #define ADV_SG_TOTAL_MEM_SIZE \
1017 (sizeof(ADV_SG_BLOCK) * ADV_NUM_SG_BLOCK)
1019 #define ADV_PAGE_SIZE PAGE_SIZE
1021 #define ADV_NUM_PAGE_CROSSING \
1022 ((ADV_SG_TOTAL_MEM_SIZE + (ADV_PAGE_SIZE - 1))/ADV_PAGE_SIZE)
1024 #define ADV_EEP_DVC_CFG_BEGIN (0x00)
1025 #define ADV_EEP_DVC_CFG_END (0x15)
1026 #define ADV_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */
1027 #define ADV_EEP_MAX_WORD_ADDR (0x1E)
1029 #define ADV_EEP_DELAY_MS 100
1031 #define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */
1032 #define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */
1034 * For the ASC3550 Bit 13 is Termination Polarity control bit.
1035 * For later ICs Bit 13 controls whether the CIS (Card Information
1036 * Service Section) is loaded from EEPROM.
1038 #define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */
1039 #define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */
1043 * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
1044 * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
1045 * Function 0 will specify INT B.
1047 * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
1048 * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
1049 * Function 1 will specify INT A.
1051 #define ADV_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */
1053 typedef struct adveep_3550_config {
1054 /* Word Offset, Description */
1056 ushort cfg_lsw; /* 00 power up initialization */
1057 /* bit 13 set - Term Polarity Control */
1058 /* bit 14 set - BIOS Enable */
1059 /* bit 15 set - Big Endian Mode */
1060 ushort cfg_msw; /* 01 unused */
1061 ushort disc_enable; /* 02 disconnect enable */
1062 ushort wdtr_able; /* 03 Wide DTR able */
1063 ushort sdtr_able; /* 04 Synchronous DTR able */
1064 ushort start_motor; /* 05 send start up motor */
1065 ushort tagqng_able; /* 06 tag queuing able */
1066 ushort bios_scan; /* 07 BIOS device control */
1067 ushort scam_tolerant; /* 08 no scam */
1069 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1070 uchar bios_boot_delay; /* power up wait */
1072 uchar scsi_reset_delay; /* 10 reset delay */
1073 uchar bios_id_lun; /* first boot device scsi id & lun */
1074 /* high nibble is lun */
1075 /* low nibble is scsi id */
1077 uchar termination; /* 11 0 - automatic */
1078 /* 1 - low off / high off */
1079 /* 2 - low off / high on */
1080 /* 3 - low on / high on */
1081 /* There is no low on / high off */
1083 uchar reserved1; /* reserved byte (not used) */
1085 ushort bios_ctrl; /* 12 BIOS control bits */
1086 /* bit 0 BIOS don't act as initiator. */
1087 /* bit 1 BIOS > 1 GB support */
1088 /* bit 2 BIOS > 2 Disk Support */
1089 /* bit 3 BIOS don't support removables */
1090 /* bit 4 BIOS support bootable CD */
1091 /* bit 5 BIOS scan enabled */
1092 /* bit 6 BIOS support multiple LUNs */
1093 /* bit 7 BIOS display of message */
1094 /* bit 8 SCAM disabled */
1095 /* bit 9 Reset SCSI bus during init. */
1097 /* bit 11 No verbose initialization. */
1098 /* bit 12 SCSI parity enabled */
1102 ushort ultra_able; /* 13 ULTRA speed able */
1103 ushort reserved2; /* 14 reserved */
1104 uchar max_host_qng; /* 15 maximum host queuing */
1105 uchar max_dvc_qng; /* maximum per device queuing */
1106 ushort dvc_cntl; /* 16 control bit for driver */
1107 ushort bug_fix; /* 17 control bit for bug fix */
1108 ushort serial_number_word1; /* 18 Board serial number word 1 */
1109 ushort serial_number_word2; /* 19 Board serial number word 2 */
1110 ushort serial_number_word3; /* 20 Board serial number word 3 */
1111 ushort check_sum; /* 21 EEP check sum */
1112 uchar oem_name[16]; /* 22 OEM name */
1113 ushort dvc_err_code; /* 30 last device driver error code */
1114 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1115 ushort adv_err_addr; /* 32 last uc error address */
1116 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1117 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1118 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1119 ushort num_of_err; /* 36 number of error */
1120 } ADVEEP_3550_CONFIG;
1122 typedef struct adveep_38C0800_config {
1123 /* Word Offset, Description */
1125 ushort cfg_lsw; /* 00 power up initialization */
1126 /* bit 13 set - Load CIS */
1127 /* bit 14 set - BIOS Enable */
1128 /* bit 15 set - Big Endian Mode */
1129 ushort cfg_msw; /* 01 unused */
1130 ushort disc_enable; /* 02 disconnect enable */
1131 ushort wdtr_able; /* 03 Wide DTR able */
1132 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1133 ushort start_motor; /* 05 send start up motor */
1134 ushort tagqng_able; /* 06 tag queuing able */
1135 ushort bios_scan; /* 07 BIOS device control */
1136 ushort scam_tolerant; /* 08 no scam */
1138 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1139 uchar bios_boot_delay; /* power up wait */
1141 uchar scsi_reset_delay; /* 10 reset delay */
1142 uchar bios_id_lun; /* first boot device scsi id & lun */
1143 /* high nibble is lun */
1144 /* low nibble is scsi id */
1146 uchar termination_se; /* 11 0 - automatic */
1147 /* 1 - low off / high off */
1148 /* 2 - low off / high on */
1149 /* 3 - low on / high on */
1150 /* There is no low on / high off */
1152 uchar termination_lvd; /* 11 0 - automatic */
1153 /* 1 - low off / high off */
1154 /* 2 - low off / high on */
1155 /* 3 - low on / high on */
1156 /* There is no low on / high off */
1158 ushort bios_ctrl; /* 12 BIOS control bits */
1159 /* bit 0 BIOS don't act as initiator. */
1160 /* bit 1 BIOS > 1 GB support */
1161 /* bit 2 BIOS > 2 Disk Support */
1162 /* bit 3 BIOS don't support removables */
1163 /* bit 4 BIOS support bootable CD */
1164 /* bit 5 BIOS scan enabled */
1165 /* bit 6 BIOS support multiple LUNs */
1166 /* bit 7 BIOS display of message */
1167 /* bit 8 SCAM disabled */
1168 /* bit 9 Reset SCSI bus during init. */
1170 /* bit 11 No verbose initialization. */
1171 /* bit 12 SCSI parity enabled */
1175 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1176 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1177 uchar max_host_qng; /* 15 maximum host queueing */
1178 uchar max_dvc_qng; /* maximum per device queuing */
1179 ushort dvc_cntl; /* 16 control bit for driver */
1180 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1181 ushort serial_number_word1; /* 18 Board serial number word 1 */
1182 ushort serial_number_word2; /* 19 Board serial number word 2 */
1183 ushort serial_number_word3; /* 20 Board serial number word 3 */
1184 ushort check_sum; /* 21 EEP check sum */
1185 uchar oem_name[16]; /* 22 OEM name */
1186 ushort dvc_err_code; /* 30 last device driver error code */
1187 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1188 ushort adv_err_addr; /* 32 last uc error address */
1189 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1190 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1191 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1192 ushort reserved36; /* 36 reserved */
1193 ushort reserved37; /* 37 reserved */
1194 ushort reserved38; /* 38 reserved */
1195 ushort reserved39; /* 39 reserved */
1196 ushort reserved40; /* 40 reserved */
1197 ushort reserved41; /* 41 reserved */
1198 ushort reserved42; /* 42 reserved */
1199 ushort reserved43; /* 43 reserved */
1200 ushort reserved44; /* 44 reserved */
1201 ushort reserved45; /* 45 reserved */
1202 ushort reserved46; /* 46 reserved */
1203 ushort reserved47; /* 47 reserved */
1204 ushort reserved48; /* 48 reserved */
1205 ushort reserved49; /* 49 reserved */
1206 ushort reserved50; /* 50 reserved */
1207 ushort reserved51; /* 51 reserved */
1208 ushort reserved52; /* 52 reserved */
1209 ushort reserved53; /* 53 reserved */
1210 ushort reserved54; /* 54 reserved */
1211 ushort reserved55; /* 55 reserved */
1212 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1213 ushort cisprt_msw; /* 57 CIS PTR MSW */
1214 ushort subsysvid; /* 58 SubSystem Vendor ID */
1215 ushort subsysid; /* 59 SubSystem ID */
1216 ushort reserved60; /* 60 reserved */
1217 ushort reserved61; /* 61 reserved */
1218 ushort reserved62; /* 62 reserved */
1219 ushort reserved63; /* 63 reserved */
1220 } ADVEEP_38C0800_CONFIG;
1222 typedef struct adveep_38C1600_config {
1223 /* Word Offset, Description */
1225 ushort cfg_lsw; /* 00 power up initialization */
1226 /* bit 11 set - Func. 0 INTB, Func. 1 INTA */
1227 /* clear - Func. 0 INTA, Func. 1 INTB */
1228 /* bit 13 set - Load CIS */
1229 /* bit 14 set - BIOS Enable */
1230 /* bit 15 set - Big Endian Mode */
1231 ushort cfg_msw; /* 01 unused */
1232 ushort disc_enable; /* 02 disconnect enable */
1233 ushort wdtr_able; /* 03 Wide DTR able */
1234 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1235 ushort start_motor; /* 05 send start up motor */
1236 ushort tagqng_able; /* 06 tag queuing able */
1237 ushort bios_scan; /* 07 BIOS device control */
1238 ushort scam_tolerant; /* 08 no scam */
1240 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1241 uchar bios_boot_delay; /* power up wait */
1243 uchar scsi_reset_delay; /* 10 reset delay */
1244 uchar bios_id_lun; /* first boot device scsi id & lun */
1245 /* high nibble is lun */
1246 /* low nibble is scsi id */
1248 uchar termination_se; /* 11 0 - automatic */
1249 /* 1 - low off / high off */
1250 /* 2 - low off / high on */
1251 /* 3 - low on / high on */
1252 /* There is no low on / high off */
1254 uchar termination_lvd; /* 11 0 - automatic */
1255 /* 1 - low off / high off */
1256 /* 2 - low off / high on */
1257 /* 3 - low on / high on */
1258 /* There is no low on / high off */
1260 ushort bios_ctrl; /* 12 BIOS control bits */
1261 /* bit 0 BIOS don't act as initiator. */
1262 /* bit 1 BIOS > 1 GB support */
1263 /* bit 2 BIOS > 2 Disk Support */
1264 /* bit 3 BIOS don't support removables */
1265 /* bit 4 BIOS support bootable CD */
1266 /* bit 5 BIOS scan enabled */
1267 /* bit 6 BIOS support multiple LUNs */
1268 /* bit 7 BIOS display of message */
1269 /* bit 8 SCAM disabled */
1270 /* bit 9 Reset SCSI bus during init. */
1271 /* bit 10 Basic Integrity Checking disabled */
1272 /* bit 11 No verbose initialization. */
1273 /* bit 12 SCSI parity enabled */
1274 /* bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
1277 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1278 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1279 uchar max_host_qng; /* 15 maximum host queueing */
1280 uchar max_dvc_qng; /* maximum per device queuing */
1281 ushort dvc_cntl; /* 16 control bit for driver */
1282 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1283 ushort serial_number_word1; /* 18 Board serial number word 1 */
1284 ushort serial_number_word2; /* 19 Board serial number word 2 */
1285 ushort serial_number_word3; /* 20 Board serial number word 3 */
1286 ushort check_sum; /* 21 EEP check sum */
1287 uchar oem_name[16]; /* 22 OEM name */
1288 ushort dvc_err_code; /* 30 last device driver error code */
1289 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1290 ushort adv_err_addr; /* 32 last uc error address */
1291 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1292 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1293 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1294 ushort reserved36; /* 36 reserved */
1295 ushort reserved37; /* 37 reserved */
1296 ushort reserved38; /* 38 reserved */
1297 ushort reserved39; /* 39 reserved */
1298 ushort reserved40; /* 40 reserved */
1299 ushort reserved41; /* 41 reserved */
1300 ushort reserved42; /* 42 reserved */
1301 ushort reserved43; /* 43 reserved */
1302 ushort reserved44; /* 44 reserved */
1303 ushort reserved45; /* 45 reserved */
1304 ushort reserved46; /* 46 reserved */
1305 ushort reserved47; /* 47 reserved */
1306 ushort reserved48; /* 48 reserved */
1307 ushort reserved49; /* 49 reserved */
1308 ushort reserved50; /* 50 reserved */
1309 ushort reserved51; /* 51 reserved */
1310 ushort reserved52; /* 52 reserved */
1311 ushort reserved53; /* 53 reserved */
1312 ushort reserved54; /* 54 reserved */
1313 ushort reserved55; /* 55 reserved */
1314 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1315 ushort cisprt_msw; /* 57 CIS PTR MSW */
1316 ushort subsysvid; /* 58 SubSystem Vendor ID */
1317 ushort subsysid; /* 59 SubSystem ID */
1318 ushort reserved60; /* 60 reserved */
1319 ushort reserved61; /* 61 reserved */
1320 ushort reserved62; /* 62 reserved */
1321 ushort reserved63; /* 63 reserved */
1322 } ADVEEP_38C1600_CONFIG;
1327 #define ASC_EEP_CMD_DONE 0x0200
1330 #define BIOS_CTRL_BIOS 0x0001
1331 #define BIOS_CTRL_EXTENDED_XLAT 0x0002
1332 #define BIOS_CTRL_GT_2_DISK 0x0004
1333 #define BIOS_CTRL_BIOS_REMOVABLE 0x0008
1334 #define BIOS_CTRL_BOOTABLE_CD 0x0010
1335 #define BIOS_CTRL_MULTIPLE_LUN 0x0040
1336 #define BIOS_CTRL_DISPLAY_MSG 0x0080
1337 #define BIOS_CTRL_NO_SCAM 0x0100
1338 #define BIOS_CTRL_RESET_SCSI_BUS 0x0200
1339 #define BIOS_CTRL_INIT_VERBOSE 0x0800
1340 #define BIOS_CTRL_SCSI_PARITY 0x1000
1341 #define BIOS_CTRL_AIPP_DIS 0x2000
1343 #define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */
1345 #define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1348 * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
1349 * a special 16K Adv Library and Microcode version. After the issue is
1350 * resolved, should restore 32K support.
1352 * #define ADV_38C1600_MEMSIZE 0x8000L * 32 KB Internal Memory *
1354 #define ADV_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1357 * Byte I/O register address from base of 'iop_base'.
1359 #define IOPB_INTR_STATUS_REG 0x00
1360 #define IOPB_CHIP_ID_1 0x01
1361 #define IOPB_INTR_ENABLES 0x02
1362 #define IOPB_CHIP_TYPE_REV 0x03
1363 #define IOPB_RES_ADDR_4 0x04
1364 #define IOPB_RES_ADDR_5 0x05
1365 #define IOPB_RAM_DATA 0x06
1366 #define IOPB_RES_ADDR_7 0x07
1367 #define IOPB_FLAG_REG 0x08
1368 #define IOPB_RES_ADDR_9 0x09
1369 #define IOPB_RISC_CSR 0x0A
1370 #define IOPB_RES_ADDR_B 0x0B
1371 #define IOPB_RES_ADDR_C 0x0C
1372 #define IOPB_RES_ADDR_D 0x0D
1373 #define IOPB_SOFT_OVER_WR 0x0E
1374 #define IOPB_RES_ADDR_F 0x0F
1375 #define IOPB_MEM_CFG 0x10
1376 #define IOPB_RES_ADDR_11 0x11
1377 #define IOPB_GPIO_DATA 0x12
1378 #define IOPB_RES_ADDR_13 0x13
1379 #define IOPB_FLASH_PAGE 0x14
1380 #define IOPB_RES_ADDR_15 0x15
1381 #define IOPB_GPIO_CNTL 0x16
1382 #define IOPB_RES_ADDR_17 0x17
1383 #define IOPB_FLASH_DATA 0x18
1384 #define IOPB_RES_ADDR_19 0x19
1385 #define IOPB_RES_ADDR_1A 0x1A
1386 #define IOPB_RES_ADDR_1B 0x1B
1387 #define IOPB_RES_ADDR_1C 0x1C
1388 #define IOPB_RES_ADDR_1D 0x1D
1389 #define IOPB_RES_ADDR_1E 0x1E
1390 #define IOPB_RES_ADDR_1F 0x1F
1391 #define IOPB_DMA_CFG0 0x20
1392 #define IOPB_DMA_CFG1 0x21
1393 #define IOPB_TICKLE 0x22
1394 #define IOPB_DMA_REG_WR 0x23
1395 #define IOPB_SDMA_STATUS 0x24
1396 #define IOPB_SCSI_BYTE_CNT 0x25
1397 #define IOPB_HOST_BYTE_CNT 0x26
1398 #define IOPB_BYTE_LEFT_TO_XFER 0x27
1399 #define IOPB_BYTE_TO_XFER_0 0x28
1400 #define IOPB_BYTE_TO_XFER_1 0x29
1401 #define IOPB_BYTE_TO_XFER_2 0x2A
1402 #define IOPB_BYTE_TO_XFER_3 0x2B
1403 #define IOPB_ACC_GRP 0x2C
1404 #define IOPB_RES_ADDR_2D 0x2D
1405 #define IOPB_DEV_ID 0x2E
1406 #define IOPB_RES_ADDR_2F 0x2F
1407 #define IOPB_SCSI_DATA 0x30
1408 #define IOPB_RES_ADDR_31 0x31
1409 #define IOPB_RES_ADDR_32 0x32
1410 #define IOPB_SCSI_DATA_HSHK 0x33
1411 #define IOPB_SCSI_CTRL 0x34
1412 #define IOPB_RES_ADDR_35 0x35
1413 #define IOPB_RES_ADDR_36 0x36
1414 #define IOPB_RES_ADDR_37 0x37
1415 #define IOPB_RAM_BIST 0x38
1416 #define IOPB_PLL_TEST 0x39
1417 #define IOPB_PCI_INT_CFG 0x3A
1418 #define IOPB_RES_ADDR_3B 0x3B
1419 #define IOPB_RFIFO_CNT 0x3C
1420 #define IOPB_RES_ADDR_3D 0x3D
1421 #define IOPB_RES_ADDR_3E 0x3E
1422 #define IOPB_RES_ADDR_3F 0x3F
1425 * Word I/O register address from base of 'iop_base'.
1427 #define IOPW_CHIP_ID_0 0x00 /* CID0 */
1428 #define IOPW_CTRL_REG 0x02 /* CC */
1429 #define IOPW_RAM_ADDR 0x04 /* LA */
1430 #define IOPW_RAM_DATA 0x06 /* LD */
1431 #define IOPW_RES_ADDR_08 0x08
1432 #define IOPW_RISC_CSR 0x0A /* CSR */
1433 #define IOPW_SCSI_CFG0 0x0C /* CFG0 */
1434 #define IOPW_SCSI_CFG1 0x0E /* CFG1 */
1435 #define IOPW_RES_ADDR_10 0x10
1436 #define IOPW_SEL_MASK 0x12 /* SM */
1437 #define IOPW_RES_ADDR_14 0x14
1438 #define IOPW_FLASH_ADDR 0x16 /* FA */
1439 #define IOPW_RES_ADDR_18 0x18
1440 #define IOPW_EE_CMD 0x1A /* EC */
1441 #define IOPW_EE_DATA 0x1C /* ED */
1442 #define IOPW_SFIFO_CNT 0x1E /* SFC */
1443 #define IOPW_RES_ADDR_20 0x20
1444 #define IOPW_Q_BASE 0x22 /* QB */
1445 #define IOPW_QP 0x24 /* QP */
1446 #define IOPW_IX 0x26 /* IX */
1447 #define IOPW_SP 0x28 /* SP */
1448 #define IOPW_PC 0x2A /* PC */
1449 #define IOPW_RES_ADDR_2C 0x2C
1450 #define IOPW_RES_ADDR_2E 0x2E
1451 #define IOPW_SCSI_DATA 0x30 /* SD */
1452 #define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */
1453 #define IOPW_SCSI_CTRL 0x34 /* SC */
1454 #define IOPW_HSHK_CFG 0x36 /* HCFG */
1455 #define IOPW_SXFR_STATUS 0x36 /* SXS */
1456 #define IOPW_SXFR_CNTL 0x38 /* SXL */
1457 #define IOPW_SXFR_CNTH 0x3A /* SXH */
1458 #define IOPW_RES_ADDR_3C 0x3C
1459 #define IOPW_RFIFO_DATA 0x3E /* RFD */
1462 * Doubleword I/O register address from base of 'iop_base'.
1464 #define IOPDW_RES_ADDR_0 0x00
1465 #define IOPDW_RAM_DATA 0x04
1466 #define IOPDW_RES_ADDR_8 0x08
1467 #define IOPDW_RES_ADDR_C 0x0C
1468 #define IOPDW_RES_ADDR_10 0x10
1469 #define IOPDW_COMMA 0x14
1470 #define IOPDW_COMMB 0x18
1471 #define IOPDW_RES_ADDR_1C 0x1C
1472 #define IOPDW_SDMA_ADDR0 0x20
1473 #define IOPDW_SDMA_ADDR1 0x24
1474 #define IOPDW_SDMA_COUNT 0x28
1475 #define IOPDW_SDMA_ERROR 0x2C
1476 #define IOPDW_RDMA_ADDR0 0x30
1477 #define IOPDW_RDMA_ADDR1 0x34
1478 #define IOPDW_RDMA_COUNT 0x38
1479 #define IOPDW_RDMA_ERROR 0x3C
1481 #define ADV_CHIP_ID_BYTE 0x25
1482 #define ADV_CHIP_ID_WORD 0x04C1
1484 #define ADV_INTR_ENABLE_HOST_INTR 0x01
1485 #define ADV_INTR_ENABLE_SEL_INTR 0x02
1486 #define ADV_INTR_ENABLE_DPR_INTR 0x04
1487 #define ADV_INTR_ENABLE_RTA_INTR 0x08
1488 #define ADV_INTR_ENABLE_RMA_INTR 0x10
1489 #define ADV_INTR_ENABLE_RST_INTR 0x20
1490 #define ADV_INTR_ENABLE_DPE_INTR 0x40
1491 #define ADV_INTR_ENABLE_GLOBAL_INTR 0x80
1493 #define ADV_INTR_STATUS_INTRA 0x01
1494 #define ADV_INTR_STATUS_INTRB 0x02
1495 #define ADV_INTR_STATUS_INTRC 0x04
1497 #define ADV_RISC_CSR_STOP (0x0000)
1498 #define ADV_RISC_TEST_COND (0x2000)
1499 #define ADV_RISC_CSR_RUN (0x4000)
1500 #define ADV_RISC_CSR_SINGLE_STEP (0x8000)
1502 #define ADV_CTRL_REG_HOST_INTR 0x0100
1503 #define ADV_CTRL_REG_SEL_INTR 0x0200
1504 #define ADV_CTRL_REG_DPR_INTR 0x0400
1505 #define ADV_CTRL_REG_RTA_INTR 0x0800
1506 #define ADV_CTRL_REG_RMA_INTR 0x1000
1507 #define ADV_CTRL_REG_RES_BIT14 0x2000
1508 #define ADV_CTRL_REG_DPE_INTR 0x4000
1509 #define ADV_CTRL_REG_POWER_DONE 0x8000
1510 #define ADV_CTRL_REG_ANY_INTR 0xFF00
1512 #define ADV_CTRL_REG_CMD_RESET 0x00C6
1513 #define ADV_CTRL_REG_CMD_WR_IO_REG 0x00C5
1514 #define ADV_CTRL_REG_CMD_RD_IO_REG 0x00C4
1515 #define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3
1516 #define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2
1518 #define ADV_TICKLE_NOP 0x00
1519 #define ADV_TICKLE_A 0x01
1520 #define ADV_TICKLE_B 0x02
1521 #define ADV_TICKLE_C 0x03
1523 #define AdvIsIntPending(port) \
1524 (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
1527 * SCSI_CFG0 Register bit definitions
1529 #define TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */
1530 #define PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */
1531 #define EVEN_PARITY 0x1000 /* Select Even Parity */
1532 #define WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */
1533 #define QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */
1534 #define PRIM_MODE 0x0100 /* Primitive SCSI mode */
1535 #define SCAM_EN 0x0080 /* Enable SCAM selection */
1536 #define SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
1537 #define CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
1538 #define OUR_ID_EN 0x0010 /* Enable OUR_ID bits */
1539 #define OUR_ID 0x000F /* SCSI ID */
1542 * SCSI_CFG1 Register bit definitions
1544 #define BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */
1545 #define TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
1546 #define SLEW_RATE 0x1000 /* SCSI output buffer slew rate */
1547 #define FILTER_SEL 0x0C00 /* Filter Period Selection */
1548 #define FLTR_DISABLE 0x0000 /* Input Filtering Disabled */
1549 #define FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
1550 #define FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
1551 #define ACTIVE_DBL 0x0200 /* Disable Active Negation */
1552 #define DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */
1553 #define DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */
1554 #define TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */
1555 #define TERM_CTL 0x0030 /* External SCSI Termination Bits */
1556 #define TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */
1557 #define TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */
1558 #define CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */
1561 * Addendum for ASC-38C0800 Chip
1563 * The ASC-38C1600 Chip uses the same definitions except that the
1564 * bus mode override bits [12:10] have been moved to byte register
1565 * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
1566 * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
1567 * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
1568 * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
1569 * and [1:0]. Bits [14], [7:6], [3:2] are unused.
1571 #define DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */
1572 #define HVD_LVD_SE 0x1C00 /* Device Detect Bits */
1573 #define HVD 0x1000 /* HVD Device Detect */
1574 #define LVD 0x0800 /* LVD Device Detect */
1575 #define SE 0x0400 /* SE Device Detect */
1576 #define TERM_LVD 0x00C0 /* LVD Termination Bits */
1577 #define TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */
1578 #define TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */
1579 #define TERM_SE 0x0030 /* SE Termination Bits */
1580 #define TERM_SE_HI 0x0020 /* Enable SE Upper Termination */
1581 #define TERM_SE_LO 0x0010 /* Enable SE Lower Termination */
1582 #define C_DET_LVD 0x000C /* LVD Cable Detect Bits */
1583 #define C_DET3 0x0008 /* Cable Detect for LVD External Wide */
1584 #define C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */
1585 #define C_DET_SE 0x0003 /* SE Cable Detect Bits */
1586 #define C_DET1 0x0002 /* Cable Detect for SE Internal Wide */
1587 #define C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */
1589 #define CABLE_ILLEGAL_A 0x7
1590 /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */
1592 #define CABLE_ILLEGAL_B 0xB
1593 /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */
1596 * MEM_CFG Register bit definitions
1598 #define BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */
1599 #define FAST_EE_CLK 0x20 /* Diagnostic Bit */
1600 #define RAM_SZ 0x1C /* Specify size of RAM to RISC */
1601 #define RAM_SZ_2KB 0x00 /* 2 KB */
1602 #define RAM_SZ_4KB 0x04 /* 4 KB */
1603 #define RAM_SZ_8KB 0x08 /* 8 KB */
1604 #define RAM_SZ_16KB 0x0C /* 16 KB */
1605 #define RAM_SZ_32KB 0x10 /* 32 KB */
1606 #define RAM_SZ_64KB 0x14 /* 64 KB */
1609 * DMA_CFG0 Register bit definitions
1611 * This register is only accessible to the host.
1613 #define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */
1614 #define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */
1615 #define FIFO_THRESH_16B 0x00 /* 16 bytes */
1616 #define FIFO_THRESH_32B 0x20 /* 32 bytes */
1617 #define FIFO_THRESH_48B 0x30 /* 48 bytes */
1618 #define FIFO_THRESH_64B 0x40 /* 64 bytes */
1619 #define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */
1620 #define FIFO_THRESH_96B 0x60 /* 96 bytes */
1621 #define FIFO_THRESH_112B 0x70 /* 112 bytes */
1622 #define START_CTL 0x0C /* DMA start conditions */
1623 #define START_CTL_TH 0x00 /* Wait threshold level (default) */
1624 #define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */
1625 #define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */
1626 #define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */
1627 #define READ_CMD 0x03 /* Memory Read Method */
1628 #define READ_CMD_MR 0x00 /* Memory Read */
1629 #define READ_CMD_MRL 0x02 /* Memory Read Long */
1630 #define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */
1633 * ASC-38C0800 RAM BIST Register bit definitions
1635 #define RAM_TEST_MODE 0x80
1636 #define PRE_TEST_MODE 0x40
1637 #define NORMAL_MODE 0x00
1638 #define RAM_TEST_DONE 0x10
1639 #define RAM_TEST_STATUS 0x0F
1640 #define RAM_TEST_HOST_ERROR 0x08
1641 #define RAM_TEST_INTRAM_ERROR 0x04
1642 #define RAM_TEST_RISC_ERROR 0x02
1643 #define RAM_TEST_SCSI_ERROR 0x01
1644 #define RAM_TEST_SUCCESS 0x00
1645 #define PRE_TEST_VALUE 0x05
1646 #define NORMAL_VALUE 0x00
1649 * ASC38C1600 Definitions
1651 * IOPB_PCI_INT_CFG Bit Field Definitions
1654 #define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */
1657 * Bit 1 can be set to change the interrupt for the Function to operate in
1658 * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
1659 * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
1660 * mode, otherwise the operating mode is undefined.
1662 #define TOTEMPOLE 0x02
1665 * Bit 0 can be used to change the Int Pin for the Function. The value is
1666 * 0 by default for both Functions with Function 0 using INT A and Function
1667 * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
1670 * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
1671 * value specified in the PCI Configuration Space.
1676 * Adv Library Status Definitions
1680 #define ADV_SUCCESS 1
1682 #define ADV_ERROR (-1)
1685 * ADV_DVC_VAR 'warn_code' values
1687 #define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */
1688 #define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */
1689 #define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */
1690 #define ASC_WARN_ERROR 0xFFFF /* ADV_ERROR return */
1692 #define ADV_MAX_TID 15 /* max. target identifier */
1693 #define ADV_MAX_LUN 7 /* max. logical unit number */
1696 * Fixed locations of microcode operating variables.
1698 #define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */
1699 #define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */
1700 #define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */
1701 #define ASC_MC_VERSION_DATE 0x0038 /* microcode version */
1702 #define ASC_MC_VERSION_NUM 0x003A /* microcode number */
1703 #define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
1704 #define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
1705 #define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */
1706 #define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */
1707 #define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */
1708 #define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */
1709 #define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */
1710 #define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */
1711 #define ASC_MC_CHIP_TYPE 0x009A
1712 #define ASC_MC_INTRB_CODE 0x009B
1713 #define ASC_MC_WDTR_ABLE 0x009C
1714 #define ASC_MC_SDTR_ABLE 0x009E
1715 #define ASC_MC_TAGQNG_ABLE 0x00A0
1716 #define ASC_MC_DISC_ENABLE 0x00A2
1717 #define ASC_MC_IDLE_CMD_STATUS 0x00A4
1718 #define ASC_MC_IDLE_CMD 0x00A6
1719 #define ASC_MC_IDLE_CMD_PARAMETER 0x00A8
1720 #define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC
1721 #define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE
1722 #define ASC_MC_DEFAULT_MEM_CFG 0x00B0
1723 #define ASC_MC_DEFAULT_SEL_MASK 0x00B2
1724 #define ASC_MC_SDTR_DONE 0x00B6
1725 #define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0
1726 #define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0
1727 #define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100
1728 #define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */
1729 #define ASC_MC_WDTR_DONE 0x0124
1730 #define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */
1731 #define ASC_MC_ICQ 0x0160
1732 #define ASC_MC_IRQ 0x0164
1733 #define ASC_MC_PPR_ABLE 0x017A
1736 * BIOS LRAM variable absolute offsets.
1738 #define BIOS_CODESEG 0x54
1739 #define BIOS_CODELEN 0x56
1740 #define BIOS_SIGNATURE 0x58
1741 #define BIOS_VERSION 0x5A
1744 * Microcode Control Flags
1746 * Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
1747 * and handled by the microcode.
1749 #define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */
1750 #define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */
1753 * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
1755 #define HSHK_CFG_WIDE_XFR 0x8000
1756 #define HSHK_CFG_RATE 0x0F00
1757 #define HSHK_CFG_OFFSET 0x001F
1759 #define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */
1760 #define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */
1761 #define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */
1762 #define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */
1764 #define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */
1765 #define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */
1766 #define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
1767 #define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */
1768 #define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */
1770 #define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */
1771 #define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */
1772 #define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */
1773 #define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */
1774 #define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */
1776 * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
1777 * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
1779 #define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */
1780 #define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */
1783 * All fields here are accessed by the board microcode and need to be
1786 typedef struct adv_carr_t {
1787 ADV_VADDR carr_va; /* Carrier Virtual Address */
1788 ADV_PADDR carr_pa; /* Carrier Physical Address */
1789 ADV_VADDR areq_vpa; /* ASC_SCSI_REQ_Q Virtual or Physical Address */
1791 * next_vpa [31:4] Carrier Virtual or Physical Next Pointer
1793 * next_vpa [3:1] Reserved Bits
1794 * next_vpa [0] Done Flag set in Response Queue.
1800 * Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
1802 #define ASC_NEXT_VPA_MASK 0xFFFFFFF0
1804 #define ASC_RQ_DONE 0x00000001
1805 #define ASC_RQ_GOOD 0x00000002
1806 #define ASC_CQ_STOPPER 0x00000000
1808 #define ASC_GET_CARRP(carrp) ((carrp) & ASC_NEXT_VPA_MASK)
1810 #define ADV_CARRIER_NUM_PAGE_CROSSING \
1811 (((ADV_CARRIER_COUNT * sizeof(ADV_CARR_T)) + \
1812 (ADV_PAGE_SIZE - 1))/ADV_PAGE_SIZE)
1814 #define ADV_CARRIER_BUFSIZE \
1815 ((ADV_CARRIER_COUNT + ADV_CARRIER_NUM_PAGE_CROSSING) * sizeof(ADV_CARR_T))
1818 * ASC_SCSI_REQ_Q 'a_flag' definitions
1820 * The Adv Library should limit use to the lower nibble (4 bits) of
1821 * a_flag. Drivers are free to use the upper nibble (4 bits) of a_flag.
1823 #define ADV_POLL_REQUEST 0x01 /* poll for request completion */
1824 #define ADV_SCSIQ_DONE 0x02 /* request done */
1825 #define ADV_DONT_RETRY 0x08 /* don't do retry */
1827 #define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */
1828 #define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */
1829 #define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */
1832 * Adapter temporary configuration structure
1834 * This structure can be discarded after initialization. Don't add
1835 * fields here needed after initialization.
1837 * Field naming convention:
1839 * *_enable indicates the field enables or disables a feature. The
1840 * value of the field is never reset.
1842 typedef struct adv_dvc_cfg {
1843 ushort disc_enable; /* enable disconnection */
1844 uchar chip_version; /* chip version */
1845 uchar termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
1846 ushort control_flag; /* Microcode Control Flag */
1847 ushort mcode_date; /* Microcode date */
1848 ushort mcode_version; /* Microcode version */
1849 ushort serial1; /* EEPROM serial number word 1 */
1850 ushort serial2; /* EEPROM serial number word 2 */
1851 ushort serial3; /* EEPROM serial number word 3 */
1855 struct adv_scsi_req_q;
1858 * Adapter operation variable structure.
1860 * One structure is required per host adapter.
1862 * Field naming convention:
1864 * *_able indicates both whether a feature should be enabled or disabled
1865 * and whether a device isi capable of the feature. At initialization
1866 * this field may be set, but later if a device is found to be incapable
1867 * of the feature, the field is cleared.
1869 typedef struct adv_dvc_var {
1870 AdvPortAddr iop_base; /* I/O port address */
1871 ushort err_code; /* fatal error code */
1872 ushort bios_ctrl; /* BIOS control word, EEPROM word 12 */
1873 ushort wdtr_able; /* try WDTR for a device */
1874 ushort sdtr_able; /* try SDTR for a device */
1875 ushort ultra_able; /* try SDTR Ultra speed for a device */
1876 ushort sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */
1877 ushort sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */
1878 ushort sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */
1879 ushort sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */
1880 ushort tagqng_able; /* try tagged queuing with a device */
1881 ushort ppr_able; /* PPR message capable per TID bitmask. */
1882 uchar max_dvc_qng; /* maximum number of tagged commands per device */
1883 ushort start_motor; /* start motor command allowed */
1884 uchar scsi_reset_wait; /* delay in seconds after scsi bus reset */
1885 uchar chip_no; /* should be assigned by caller */
1886 uchar max_host_qng; /* maximum number of Q'ed command allowed */
1887 ushort no_scam; /* scam_tolerant of EEPROM */
1888 struct asc_board *drv_ptr; /* driver pointer to private structure */
1889 uchar chip_scsi_id; /* chip SCSI target ID */
1891 uchar bist_err_code;
1892 ADV_CARR_T *carrier_buf;
1893 ADV_CARR_T *carr_freelist; /* Carrier free list. */
1894 ADV_CARR_T *icq_sp; /* Initiator command queue stopper pointer. */
1895 ADV_CARR_T *irq_sp; /* Initiator response queue stopper pointer. */
1896 ushort carr_pending_cnt; /* Count of pending carriers. */
1898 * Note: The following fields will not be used after initialization. The
1899 * driver may discard the buffer after initialization is done.
1901 ADV_DVC_CFG *cfg; /* temporary configuration structure */
1904 #define NO_OF_SG_PER_BLOCK 15
1906 typedef struct asc_sg_block {
1910 uchar sg_cnt; /* Valid entries in block. */
1911 ADV_PADDR sg_ptr; /* Pointer to next sg block. */
1913 ADV_PADDR sg_addr; /* SG element address. */
1914 ADV_DCNT sg_count; /* SG element count. */
1915 } sg_list[NO_OF_SG_PER_BLOCK];
1919 * ADV_SCSI_REQ_Q - microcode request structure
1921 * All fields in this structure up to byte 60 are used by the microcode.
1922 * The microcode makes assumptions about the size and ordering of fields
1923 * in this structure. Do not change the structure definition here without
1924 * coordinating the change with the microcode.
1926 * All fields accessed by microcode must be maintained in little_endian
1929 typedef struct adv_scsi_req_q {
1930 uchar cntl; /* Ucode flags and state (ASC_MC_QC_*). */
1932 uchar target_id; /* Device target identifier. */
1933 uchar target_lun; /* Device target logical unit number. */
1934 ADV_PADDR data_addr; /* Data buffer physical address. */
1935 ADV_DCNT data_cnt; /* Data count. Ucode sets to residual. */
1936 ADV_PADDR sense_addr;
1940 uchar cdb_len; /* SCSI CDB length. Must <= 16 bytes. */
1942 uchar done_status; /* Completion status. */
1943 uchar scsi_status; /* SCSI status byte. */
1944 uchar host_status; /* Ucode host status. */
1945 uchar sg_working_ix;
1946 uchar cdb[12]; /* SCSI CDB bytes 0-11. */
1947 ADV_PADDR sg_real_addr; /* SG list physical address. */
1948 ADV_PADDR scsiq_rptr;
1949 uchar cdb16[4]; /* SCSI CDB bytes 12-15. */
1950 ADV_VADDR scsiq_ptr;
1953 * End of microcode structure - 60 bytes. The rest of the structure
1954 * is used by the Adv Library and ignored by the microcode.
1957 ADV_SG_BLOCK *sg_list_ptr; /* SG list virtual address. */
1958 char *vdata_addr; /* Data buffer virtual address. */
1960 uchar pad[2]; /* Pad out to a word boundary. */
1964 * Microcode idle loop commands
1966 #define IDLE_CMD_COMPLETED 0
1967 #define IDLE_CMD_STOP_CHIP 0x0001
1968 #define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002
1969 #define IDLE_CMD_SEND_INT 0x0004
1970 #define IDLE_CMD_ABORT 0x0008
1971 #define IDLE_CMD_DEVICE_RESET 0x0010
1972 #define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */
1973 #define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */
1974 #define IDLE_CMD_SCSIREQ 0x0080
1976 #define IDLE_CMD_STATUS_SUCCESS 0x0001
1977 #define IDLE_CMD_STATUS_FAILURE 0x0002
1980 * AdvSendIdleCmd() flag definitions.
1982 #define ADV_NOWAIT 0x01
1985 * Wait loop time out values.
1987 #define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */
1988 #define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */
1989 #define SCSI_MAX_RETRY 10 /* retry count */
1991 #define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */
1992 #define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */
1993 #define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */
1994 #define ADV_RDMA_IN_CARR_AND_Q_INVALID 0x04 /* RDMAed-in data invalid. */
1996 #define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */
1998 /* Read byte from a register. */
1999 #define AdvReadByteRegister(iop_base, reg_off) \
2000 (ADV_MEM_READB((iop_base) + (reg_off)))
2002 /* Write byte to a register. */
2003 #define AdvWriteByteRegister(iop_base, reg_off, byte) \
2004 (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
2006 /* Read word (2 bytes) from a register. */
2007 #define AdvReadWordRegister(iop_base, reg_off) \
2008 (ADV_MEM_READW((iop_base) + (reg_off)))
2010 /* Write word (2 bytes) to a register. */
2011 #define AdvWriteWordRegister(iop_base, reg_off, word) \
2012 (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
2014 /* Write dword (4 bytes) to a register. */
2015 #define AdvWriteDWordRegister(iop_base, reg_off, dword) \
2016 (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
2018 /* Read byte from LRAM. */
2019 #define AdvReadByteLram(iop_base, addr, byte) \
2021 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
2022 (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
2025 /* Write byte to LRAM. */
2026 #define AdvWriteByteLram(iop_base, addr, byte) \
2027 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2028 ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
2030 /* Read word (2 bytes) from LRAM. */
2031 #define AdvReadWordLram(iop_base, addr, word) \
2033 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
2034 (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
2037 /* Write word (2 bytes) to LRAM. */
2038 #define AdvWriteWordLram(iop_base, addr, word) \
2039 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2040 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2042 /* Write little-endian double word (4 bytes) to LRAM */
2043 /* Because of unspecified C language ordering don't use auto-increment. */
2044 #define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
2045 ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2046 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2047 cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
2048 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
2049 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2050 cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
2052 /* Read word (2 bytes) from LRAM assuming that the address is already set. */
2053 #define AdvReadWordAutoIncLram(iop_base) \
2054 (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
2056 /* Write word (2 bytes) to LRAM assuming that the address is already set. */
2057 #define AdvWriteWordAutoIncLram(iop_base, word) \
2058 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2061 * Define macro to check for Condor signature.
2063 * Evaluate to ADV_TRUE if a Condor chip is found the specified port
2064 * address 'iop_base'. Otherwise evalue to ADV_FALSE.
2066 #define AdvFindSignature(iop_base) \
2067 (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
2068 ADV_CHIP_ID_BYTE) && \
2069 (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
2070 ADV_CHIP_ID_WORD)) ? ADV_TRUE : ADV_FALSE)
2073 * Define macro to Return the version number of the chip at 'iop_base'.
2075 * The second parameter 'bus_type' is currently unused.
2077 #define AdvGetChipVersion(iop_base, bus_type) \
2078 AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
2081 * Abort an SRB in the chip's RISC Memory. The 'srb_ptr' argument must
2082 * match the ASC_SCSI_REQ_Q 'srb_ptr' field.
2084 * If the request has not yet been sent to the device it will simply be
2085 * aborted from RISC memory. If the request is disconnected it will be
2086 * aborted on reselection by sending an Abort Message to the target ID.
2089 * ADV_TRUE(1) - Queue was successfully aborted.
2090 * ADV_FALSE(0) - Queue was not found on the active queue list.
2092 #define AdvAbortQueue(asc_dvc, scsiq) \
2093 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
2097 * Send a Bus Device Reset Message to the specified target ID.
2099 * All outstanding commands will be purged if sending the
2100 * Bus Device Reset Message is successful.
2103 * ADV_TRUE(1) - All requests on the target are purged.
2104 * ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
2107 #define AdvResetDevice(asc_dvc, target_id) \
2108 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
2109 (ADV_DCNT) (target_id))
2112 * SCSI Wide Type definition.
2114 #define ADV_SCSI_BIT_ID_TYPE ushort
2117 * AdvInitScsiTarget() 'cntl_flag' options.
2119 #define ADV_SCAN_LUN 0x01
2120 #define ADV_CAPINFO_NOLUN 0x02
2123 * Convert target id to target id bit mask.
2125 #define ADV_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADV_MAX_TID))
2128 * ASC_SCSI_REQ_Q 'done_status' and 'host_status' return values.
2131 #define QD_NO_STATUS 0x00 /* Request not completed yet. */
2132 #define QD_NO_ERROR 0x01
2133 #define QD_ABORTED_BY_HOST 0x02
2134 #define QD_WITH_ERROR 0x04
2136 #define QHSTA_NO_ERROR 0x00
2137 #define QHSTA_M_SEL_TIMEOUT 0x11
2138 #define QHSTA_M_DATA_OVER_RUN 0x12
2139 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
2140 #define QHSTA_M_QUEUE_ABORTED 0x15
2141 #define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */
2142 #define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */
2143 #define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */
2144 #define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */
2145 #define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */
2146 #define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */
2147 #define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */
2148 /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
2149 #define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */
2150 #define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */
2151 #define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */
2152 #define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */
2153 #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */
2154 #define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */
2155 #define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */
2156 #define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */
2157 #define QHSTA_M_WTM_TIMEOUT 0x41
2158 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
2159 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
2160 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
2161 #define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */
2162 #define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */
2163 #define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */
2166 * DvcGetPhyAddr() flag arguments
2168 #define ADV_IS_SCSIQ_FLAG 0x01 /* 'addr' is ASC_SCSI_REQ_Q pointer */
2169 #define ADV_ASCGETSGLIST_VADDR 0x02 /* 'addr' is AscGetSGList() virtual addr */
2170 #define ADV_IS_SENSE_FLAG 0x04 /* 'addr' is sense virtual pointer */
2171 #define ADV_IS_DATA_FLAG 0x08 /* 'addr' is data virtual pointer */
2172 #define ADV_IS_SGLIST_FLAG 0x10 /* 'addr' is sglist virtual pointer */
2173 #define ADV_IS_CARRIER_FLAG 0x20 /* 'addr' is ADV_CARR_T pointer */
2175 /* Return the address that is aligned at the next doubleword >= to 'addr'. */
2176 #define ADV_8BALIGN(addr) (((ulong) (addr) + 0x7) & ~0x7)
2177 #define ADV_16BALIGN(addr) (((ulong) (addr) + 0xF) & ~0xF)
2178 #define ADV_32BALIGN(addr) (((ulong) (addr) + 0x1F) & ~0x1F)
2181 * Total contiguous memory needed for driver SG blocks.
2183 * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum
2184 * number of scatter-gather elements the driver supports in a
2188 #define ADV_SG_LIST_MAX_BYTE_SIZE \
2189 (sizeof(ADV_SG_BLOCK) * \
2190 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
2192 /* struct asc_board flags */
2193 #define ASC_IS_WIDE_BOARD 0x04 /* AdvanSys Wide Board */
2195 #define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0)
2197 #define NO_ISA_DMA 0xff /* No ISA DMA Channel Used */
2199 #define ASC_INFO_SIZE 128 /* advansys_info() line size */
2201 #ifdef CONFIG_PROC_FS
2202 /* /proc/scsi/advansys/[0...] related definitions */
2203 #define ASC_PRTBUF_SIZE 2048
2204 #define ASC_PRTLINE_SIZE 160
2206 #define ASC_PRT_NEXT() \
2210 if (leftlen == 0) { \
2215 #endif /* CONFIG_PROC_FS */
2217 /* Asc Library return codes */
2220 #define ASC_NOERROR 1
2222 #define ASC_ERROR (-1)
2224 /* struct scsi_cmnd function return codes */
2225 #define STATUS_BYTE(byte) (byte)
2226 #define MSG_BYTE(byte) ((byte) << 8)
2227 #define HOST_BYTE(byte) ((byte) << 16)
2228 #define DRIVER_BYTE(byte) ((byte) << 24)
2230 #define ASC_STATS(shost, counter) ASC_STATS_ADD(shost, counter, 1)
2231 #ifndef ADVANSYS_STATS
2232 #define ASC_STATS_ADD(shost, counter, count)
2233 #else /* ADVANSYS_STATS */
2234 #define ASC_STATS_ADD(shost, counter, count) \
2235 (((struct asc_board *) shost_priv(shost))->asc_stats.counter += (count))
2236 #endif /* ADVANSYS_STATS */
2238 #define ASC_CEILING(val, unit) (((val) + ((unit) - 1))/(unit))
2240 /* If the result wraps when calculating tenths, return 0. */
2241 #define ASC_TENTHS(num, den) \
2242 (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
2243 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
2246 * Display a message to the console.
2248 #define ASC_PRINT(s) \
2250 printk("advansys: "); \
2254 #define ASC_PRINT1(s, a1) \
2256 printk("advansys: "); \
2257 printk((s), (a1)); \
2260 #define ASC_PRINT2(s, a1, a2) \
2262 printk("advansys: "); \
2263 printk((s), (a1), (a2)); \
2266 #define ASC_PRINT3(s, a1, a2, a3) \
2268 printk("advansys: "); \
2269 printk((s), (a1), (a2), (a3)); \
2272 #define ASC_PRINT4(s, a1, a2, a3, a4) \
2274 printk("advansys: "); \
2275 printk((s), (a1), (a2), (a3), (a4)); \
2278 #ifndef ADVANSYS_DEBUG
2280 #define ASC_DBG(lvl, s)
2281 #define ASC_DBG1(lvl, s, a1)
2282 #define ASC_DBG2(lvl, s, a1, a2)
2283 #define ASC_DBG3(lvl, s, a1, a2, a3)
2284 #define ASC_DBG4(lvl, s, a1, a2, a3, a4)
2285 #define ASC_DBG_PRT_SCSI_HOST(lvl, s)
2286 #define ASC_DBG_PRT_SCSI_CMND(lvl, s)
2287 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp)
2288 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2289 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone)
2290 #define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2291 #define ASC_DBG_PRT_HEX(lvl, name, start, length)
2292 #define ASC_DBG_PRT_CDB(lvl, cdb, len)
2293 #define ASC_DBG_PRT_SENSE(lvl, sense, len)
2294 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len)
2296 #else /* ADVANSYS_DEBUG */
2299 * Debugging Message Levels:
2301 * 1: High-Level Tracing
2302 * 2-N: Verbose Tracing
2305 #define ASC_DBG(lvl, s) \
2307 if (asc_dbglvl >= (lvl)) { \
2312 #define ASC_DBG1(lvl, s, a1) \
2314 if (asc_dbglvl >= (lvl)) { \
2315 printk((s), (a1)); \
2319 #define ASC_DBG2(lvl, s, a1, a2) \
2321 if (asc_dbglvl >= (lvl)) { \
2322 printk((s), (a1), (a2)); \
2326 #define ASC_DBG3(lvl, s, a1, a2, a3) \
2328 if (asc_dbglvl >= (lvl)) { \
2329 printk((s), (a1), (a2), (a3)); \
2333 #define ASC_DBG4(lvl, s, a1, a2, a3, a4) \
2335 if (asc_dbglvl >= (lvl)) { \
2336 printk((s), (a1), (a2), (a3), (a4)); \
2340 #define ASC_DBG_PRT_SCSI_HOST(lvl, s) \
2342 if (asc_dbglvl >= (lvl)) { \
2343 asc_prt_scsi_host(s); \
2347 #define ASC_DBG_PRT_SCSI_CMND(lvl, s) \
2349 if (asc_dbglvl >= (lvl)) { \
2350 asc_prt_scsi_cmnd(s); \
2354 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \
2356 if (asc_dbglvl >= (lvl)) { \
2357 asc_prt_asc_scsi_q(scsiqp); \
2361 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \
2363 if (asc_dbglvl >= (lvl)) { \
2364 asc_prt_asc_qdone_info(qdone); \
2368 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \
2370 if (asc_dbglvl >= (lvl)) { \
2371 asc_prt_adv_scsi_req_q(scsiqp); \
2375 #define ASC_DBG_PRT_HEX(lvl, name, start, length) \
2377 if (asc_dbglvl >= (lvl)) { \
2378 asc_prt_hex((name), (start), (length)); \
2382 #define ASC_DBG_PRT_CDB(lvl, cdb, len) \
2383 ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len));
2385 #define ASC_DBG_PRT_SENSE(lvl, sense, len) \
2386 ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len));
2388 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \
2389 ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len));
2390 #endif /* ADVANSYS_DEBUG */
2392 #ifdef ADVANSYS_STATS
2394 /* Per board statistics structure */
2396 /* Driver Entrypoint Statistics */
2397 ADV_DCNT queuecommand; /* # calls to advansys_queuecommand() */
2398 ADV_DCNT reset; /* # calls to advansys_eh_bus_reset() */
2399 ADV_DCNT biosparam; /* # calls to advansys_biosparam() */
2400 ADV_DCNT interrupt; /* # advansys_interrupt() calls */
2401 ADV_DCNT callback; /* # calls to asc/adv_isr_callback() */
2402 ADV_DCNT done; /* # calls to request's scsi_done function */
2403 ADV_DCNT build_error; /* # asc/adv_build_req() ASC_ERROR returns. */
2404 ADV_DCNT adv_build_noreq; /* # adv_build_req() adv_req_t alloc. fail. */
2405 ADV_DCNT adv_build_nosg; /* # adv_build_req() adv_sgblk_t alloc. fail. */
2406 /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
2407 ADV_DCNT exe_noerror; /* # ASC_NOERROR returns. */
2408 ADV_DCNT exe_busy; /* # ASC_BUSY returns. */
2409 ADV_DCNT exe_error; /* # ASC_ERROR returns. */
2410 ADV_DCNT exe_unknown; /* # unknown returns. */
2411 /* Data Transfer Statistics */
2412 ADV_DCNT cont_cnt; /* # non-scatter-gather I/O requests received */
2413 ADV_DCNT cont_xfer; /* # contiguous transfer 512-bytes */
2414 ADV_DCNT sg_cnt; /* # scatter-gather I/O requests received */
2415 ADV_DCNT sg_elem; /* # scatter-gather elements */
2416 ADV_DCNT sg_xfer; /* # scatter-gather transfer 512-bytes */
2418 #endif /* ADVANSYS_STATS */
2421 * Adv Library Request Structures
2423 * The following two structures are used to process Wide Board requests.
2425 * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
2426 * and microcode with the ADV_SCSI_REQ_Q field 'srb_ptr' pointing to the
2427 * adv_req_t. The adv_req_t structure 'cmndp' field in turn points to the
2428 * Mid-Level SCSI request structure.
2430 * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
2431 * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
2432 * up to 255 scatter-gather elements may be used per request or
2435 * Both structures must be 32 byte aligned.
2437 typedef struct adv_sgblk {
2438 ADV_SG_BLOCK sg_block; /* Sgblock structure. */
2439 uchar align[32]; /* Sgblock structure padding. */
2440 struct adv_sgblk *next_sgblkp; /* Next scatter-gather structure. */
2443 typedef struct adv_req {
2444 ADV_SCSI_REQ_Q scsi_req_q; /* Adv Library request structure. */
2445 uchar align[32]; /* Request structure padding. */
2446 struct scsi_cmnd *cmndp; /* Mid-Level SCSI command pointer. */
2447 adv_sgblk_t *sgblkp; /* Adv Library scatter-gather pointer. */
2448 struct adv_req *next_reqp; /* Next Request Structure. */
2452 * Structure allocated for each board.
2454 * This structure is allocated by scsi_host_alloc() at the end
2455 * of the 'Scsi_Host' structure starting at the 'hostdata'
2456 * field. It is guaranteed to be allocated from DMA-able memory.
2460 int id; /* Board Id */
2461 uint flags; /* Board flags */
2464 ASC_DVC_VAR asc_dvc_var; /* Narrow board */
2465 ADV_DVC_VAR adv_dvc_var; /* Wide board */
2468 ASC_DVC_CFG asc_dvc_cfg; /* Narrow board */
2469 ADV_DVC_CFG adv_dvc_cfg; /* Wide board */
2471 ushort asc_n_io_port; /* Number I/O ports. */
2472 ADV_SCSI_BIT_ID_TYPE init_tidmask; /* Target init./valid mask */
2473 ushort reqcnt[ADV_MAX_TID + 1]; /* Starvation request count */
2474 ADV_SCSI_BIT_ID_TYPE queue_full; /* Queue full mask */
2475 ushort queue_full_cnt[ADV_MAX_TID + 1]; /* Queue full count */
2477 ASCEEP_CONFIG asc_eep; /* Narrow EEPROM config. */
2478 ADVEEP_3550_CONFIG adv_3550_eep; /* 3550 EEPROM config. */
2479 ADVEEP_38C0800_CONFIG adv_38C0800_eep; /* 38C0800 EEPROM config. */
2480 ADVEEP_38C1600_CONFIG adv_38C1600_eep; /* 38C1600 EEPROM config. */
2482 ulong last_reset; /* Saved last reset time */
2483 spinlock_t lock; /* Board spinlock */
2484 /* /proc/scsi/advansys/[0...] */
2485 char *prtbuf; /* /proc print buffer */
2486 #ifdef ADVANSYS_STATS
2487 struct asc_stats asc_stats; /* Board statistics */
2488 #endif /* ADVANSYS_STATS */
2490 * The following fields are used only for Narrow Boards.
2492 uchar sdtr_data[ASC_MAX_TID + 1]; /* SDTR information */
2494 * The following fields are used only for Wide Boards.
2496 void __iomem *ioremap_addr; /* I/O Memory remap address. */
2497 ushort ioport; /* I/O Port address. */
2498 ADV_CARR_T *carrp; /* ADV_CARR_T memory block. */
2499 adv_req_t *orig_reqp; /* adv_req_t memory block. */
2500 adv_req_t *adv_reqp; /* Request structures. */
2501 adv_sgblk_t *adv_sgblkp; /* Scatter-gather structures. */
2502 ushort bios_signature; /* BIOS Signature. */
2503 ushort bios_version; /* BIOS Version. */
2504 ushort bios_codeseg; /* BIOS Code Segment. */
2505 ushort bios_codelen; /* BIOS Code Segment Length. */
2508 #define adv_dvc_to_board(adv_dvc) container_of(adv_dvc, struct asc_board, \
2509 dvc_var.adv_dvc_var)
2510 #define adv_dvc_to_pdev(adv_dvc) to_pci_dev(adv_dvc_to_board(adv_dvc)->dev)
2512 /* Number of boards detected in system. */
2513 static int asc_board_count;
2515 /* Overrun buffer used by all narrow boards. */
2516 static uchar overrun_buf[ASC_OVERRUN_BSIZE] = { 0 };
2518 #ifdef ADVANSYS_DEBUG
2519 static int asc_dbglvl = 3;
2522 * asc_prt_scsi_host()
2524 static void asc_prt_scsi_host(struct Scsi_Host *s)
2526 struct asc_board *boardp = shost_priv(s);
2528 printk("Scsi_Host at addr 0x%lx\n", (ulong)s);
2529 printk(" host_busy %u, host_no %d, last_reset %d,\n",
2530 s->host_busy, s->host_no, (unsigned)s->last_reset);
2532 printk(" base 0x%lx, io_port 0x%lx, irq 0x%x,\n",
2533 (ulong)s->base, (ulong)s->io_port, boardp->irq);
2535 printk(" dma_channel %d, this_id %d, can_queue %d,\n",
2536 s->dma_channel, s->this_id, s->can_queue);
2538 printk(" cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n",
2539 s->cmd_per_lun, s->sg_tablesize, s->unchecked_isa_dma);
2541 if (ASC_NARROW_BOARD(boardp)) {
2542 asc_prt_asc_dvc_var(boardp->dvc_var.asc_dvc_var);
2543 asc_prt_asc_dvc_cfg(boardp->dvc_cfg.asc_dvc_cfg);
2545 asc_prt_adv_dvc_var(boardp->dvc_var.adv_dvc_var);
2546 asc_prt_adv_dvc_cfg(boardp->dvc_cfg.adv_dvc_cfg);
2551 * asc_prt_scsi_cmnd()
2553 static void asc_prt_scsi_cmnd(struct scsi_cmnd *s)
2555 printk("struct scsi_cmnd at addr 0x%lx\n", (ulong)s);
2557 printk(" host 0x%lx, device 0x%lx, target %u, lun %u, channel %u,\n",
2558 (ulong)s->device->host, (ulong)s->device, s->device->id,
2559 s->device->lun, s->device->channel);
2561 asc_prt_hex(" CDB", s->cmnd, s->cmd_len);
2563 printk("sc_data_direction %u, resid %d\n",
2564 s->sc_data_direction, s->resid);
2566 printk(" use_sg %u, sglist_len %u\n", s->use_sg, s->sglist_len);
2568 printk(" serial_number 0x%x, retries %d, allowed %d\n",
2569 (unsigned)s->serial_number, s->retries, s->allowed);
2571 printk(" timeout_per_command %d\n", s->timeout_per_command);
2573 printk(" scsi_done 0x%p, done 0x%p, host_scribble 0x%p, result 0x%x\n",
2574 s->scsi_done, s->done, s->host_scribble, s->result);
2576 printk(" tag %u, pid %u\n", (unsigned)s->tag, (unsigned)s->pid);
2580 * asc_prt_asc_dvc_var()
2582 static void asc_prt_asc_dvc_var(ASC_DVC_VAR *h)
2584 printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong)h);
2586 printk(" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl "
2587 "%d,\n", h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl);
2589 printk(" bus_type %d, init_sdtr 0x%x,\n", h->bus_type,
2590 (unsigned)h->init_sdtr);
2592 printk(" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, "
2593 "chip_no 0x%x,\n", (unsigned)h->sdtr_done,
2594 (unsigned)h->use_tagged_qng, (unsigned)h->unit_not_ready,
2595 (unsigned)h->chip_no);
2597 printk(" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait "
2598 "%u,\n", (unsigned)h->queue_full_or_busy,
2599 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2601 printk(" is_in_int %u, max_total_qng %u, cur_total_qng %u, "
2602 "in_critical_cnt %u,\n", (unsigned)h->is_in_int,
2603 (unsigned)h->max_total_qng, (unsigned)h->cur_total_qng,
2604 (unsigned)h->in_critical_cnt);
2606 printk(" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, "
2607 "pci_fix_asyn_xfer 0x%x,\n", (unsigned)h->last_q_shortage,
2608 (unsigned)h->init_state, (unsigned)h->no_scam,
2609 (unsigned)h->pci_fix_asyn_xfer);
2611 printk(" cfg 0x%lx\n", (ulong)h->cfg);
2615 * asc_prt_asc_dvc_cfg()
2617 static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h)
2619 printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong)h);
2621 printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n",
2622 h->can_tagged_qng, h->cmd_qng_enabled);
2623 printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n",
2624 h->disc_enable, h->sdtr_enable);
2626 printk(" chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, "
2627 "chip_version %d,\n", h->chip_scsi_id, h->isa_dma_speed,
2628 h->isa_dma_channel, h->chip_version);
2630 printk(" pci_device_id %d, mcode_date 0x%x, mcode_version %d, "
2631 "overrun_buf 0x%p\n", to_pci_dev(h->dev)->device,
2632 h->mcode_date, h->mcode_version, h->overrun_buf);
2636 * asc_prt_asc_scsi_q()
2638 static void asc_prt_asc_scsi_q(ASC_SCSI_Q *q)
2643 printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong)q);
2646 (" target_ix 0x%x, target_lun %u, srb_ptr 0x%lx, tag_code 0x%x,\n",
2647 q->q2.target_ix, q->q1.target_lun, (ulong)q->q2.srb_ptr,
2651 (" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2652 (ulong)le32_to_cpu(q->q1.data_addr),
2653 (ulong)le32_to_cpu(q->q1.data_cnt),
2654 (ulong)le32_to_cpu(q->q1.sense_addr), q->q1.sense_len);
2656 printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n",
2657 (ulong)q->cdbptr, q->q2.cdb_len,
2658 (ulong)q->sg_head, q->q1.sg_queue_cnt);
2662 printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong)sgp);
2663 printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt,
2665 for (i = 0; i < sgp->entry_cnt; i++) {
2666 printk(" [%u]: addr 0x%lx, bytes %lu\n",
2667 i, (ulong)le32_to_cpu(sgp->sg_list[i].addr),
2668 (ulong)le32_to_cpu(sgp->sg_list[i].bytes));
2675 * asc_prt_asc_qdone_info()
2677 static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *q)
2679 printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong)q);
2680 printk(" srb_ptr 0x%lx, target_ix %u, cdb_len %u, tag_code %u,\n",
2681 (ulong)q->d2.srb_ptr, q->d2.target_ix, q->d2.cdb_len,
2684 (" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n",
2685 q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg);
2689 * asc_prt_adv_dvc_var()
2691 * Display an ADV_DVC_VAR structure.
2693 static void asc_prt_adv_dvc_var(ADV_DVC_VAR *h)
2695 printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong)h);
2697 printk(" iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n",
2698 (ulong)h->iop_base, h->err_code, (unsigned)h->ultra_able);
2700 printk(" isr_callback 0x%lx, sdtr_able 0x%x, wdtr_able 0x%x\n",
2701 (ulong)h->isr_callback, (unsigned)h->sdtr_able,
2702 (unsigned)h->wdtr_able);
2704 printk(" start_motor 0x%x, scsi_reset_wait 0x%x\n",
2705 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2707 printk(" max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%lxn\n",
2708 (unsigned)h->max_host_qng, (unsigned)h->max_dvc_qng,
2709 (ulong)h->carr_freelist);
2711 printk(" icq_sp 0x%lx, irq_sp 0x%lx\n",
2712 (ulong)h->icq_sp, (ulong)h->irq_sp);
2714 printk(" no_scam 0x%x, tagqng_able 0x%x\n",
2715 (unsigned)h->no_scam, (unsigned)h->tagqng_able);
2717 printk(" chip_scsi_id 0x%x, cfg 0x%lx\n",
2718 (unsigned)h->chip_scsi_id, (ulong)h->cfg);
2722 * asc_prt_adv_dvc_cfg()
2724 * Display an ADV_DVC_CFG structure.
2726 static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h)
2728 printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong)h);
2730 printk(" disc_enable 0x%x, termination 0x%x\n",
2731 h->disc_enable, h->termination);
2733 printk(" chip_version 0x%x, mcode_date 0x%x\n",
2734 h->chip_version, h->mcode_date);
2736 printk(" mcode_version 0x%x, pci_device_id 0x%x\n",
2737 h->mcode_version, to_pci_dev(h->dev)->device);
2739 printk(" control_flag 0x%x\n", h->control_flag);
2743 * asc_prt_adv_scsi_req_q()
2745 * Display an ADV_SCSI_REQ_Q structure.
2747 static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q)
2750 struct asc_sg_block *sg_ptr;
2752 printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong)q);
2754 printk(" target_id %u, target_lun %u, srb_ptr 0x%lx, a_flag 0x%x\n",
2755 q->target_id, q->target_lun, (ulong)q->srb_ptr, q->a_flag);
2757 printk(" cntl 0x%x, data_addr 0x%lx, vdata_addr 0x%lx\n",
2758 q->cntl, (ulong)le32_to_cpu(q->data_addr), (ulong)q->vdata_addr);
2760 printk(" data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2761 (ulong)le32_to_cpu(q->data_cnt),
2762 (ulong)le32_to_cpu(q->sense_addr), q->sense_len);
2765 (" cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
2766 q->cdb_len, q->done_status, q->host_status, q->scsi_status);
2768 printk(" sg_working_ix 0x%x, target_cmd %u\n",
2769 q->sg_working_ix, q->target_cmd);
2771 printk(" scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n",
2772 (ulong)le32_to_cpu(q->scsiq_rptr),
2773 (ulong)le32_to_cpu(q->sg_real_addr), (ulong)q->sg_list_ptr);
2775 /* Display the request's ADV_SG_BLOCK structures. */
2776 if (q->sg_list_ptr != NULL) {
2780 * 'sg_ptr' is a physical address. Convert it to a virtual
2781 * address by indexing 'sg_blk_cnt' into the virtual address
2782 * array 'sg_list_ptr'.
2784 * XXX - Assumes all SG physical blocks are virtually contiguous.
2787 &(((ADV_SG_BLOCK *)(q->sg_list_ptr))[sg_blk_cnt]);
2788 asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr);
2789 if (sg_ptr->sg_ptr == 0) {
2798 * asc_prt_adv_sgblock()
2800 * Display an ADV_SG_BLOCK structure.
2802 static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b)
2806 printk(" ASC_SG_BLOCK at addr 0x%lx (sgblockno %d)\n",
2807 (ulong)b, sgblockno);
2808 printk(" sg_cnt %u, sg_ptr 0x%lx\n",
2809 b->sg_cnt, (ulong)le32_to_cpu(b->sg_ptr));
2810 BUG_ON(b->sg_cnt > NO_OF_SG_PER_BLOCK);
2812 BUG_ON(b->sg_cnt != NO_OF_SG_PER_BLOCK);
2813 for (i = 0; i < b->sg_cnt; i++) {
2814 printk(" [%u]: sg_addr 0x%lx, sg_count 0x%lx\n",
2815 i, (ulong)b->sg_list[i].sg_addr,
2816 (ulong)b->sg_list[i].sg_count);
2823 * Print hexadecimal output in 4 byte groupings 32 bytes
2824 * or 8 double-words per line.
2826 static void asc_prt_hex(char *f, uchar *s, int l)
2833 printk("%s: (%d bytes)\n", f, l);
2835 for (i = 0; i < l; i += 32) {
2837 /* Display a maximum of 8 double-words per line. */
2838 if ((k = (l - i) / 4) >= 8) {
2845 for (j = 0; j < k; j++) {
2846 printk(" %2.2X%2.2X%2.2X%2.2X",
2847 (unsigned)s[i + (j * 4)],
2848 (unsigned)s[i + (j * 4) + 1],
2849 (unsigned)s[i + (j * 4) + 2],
2850 (unsigned)s[i + (j * 4) + 3]);
2858 printk(" %2.2X", (unsigned)s[i + (j * 4)]);
2861 printk(" %2.2X%2.2X",
2862 (unsigned)s[i + (j * 4)],
2863 (unsigned)s[i + (j * 4) + 1]);
2866 printk(" %2.2X%2.2X%2.2X",
2867 (unsigned)s[i + (j * 4) + 1],
2868 (unsigned)s[i + (j * 4) + 2],
2869 (unsigned)s[i + (j * 4) + 3]);
2876 #endif /* ADVANSYS_DEBUG */
2881 * Return suitable for printing on the console with the argument
2882 * adapter's configuration information.
2884 * Note: The information line should not exceed ASC_INFO_SIZE bytes,
2885 * otherwise the static 'info' array will be overrun.
2887 static const char *advansys_info(struct Scsi_Host *shost)
2889 static char info[ASC_INFO_SIZE];
2890 struct asc_board *boardp = shost_priv(shost);
2891 ASC_DVC_VAR *asc_dvc_varp;
2892 ADV_DVC_VAR *adv_dvc_varp;
2894 char *widename = NULL;
2896 if (ASC_NARROW_BOARD(boardp)) {
2897 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
2898 ASC_DBG(1, "advansys_info: begin\n");
2899 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
2900 if ((asc_dvc_varp->bus_type & ASC_IS_ISAPNP) ==
2902 busname = "ISA PnP";
2907 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X",
2908 ASC_VERSION, busname,
2909 (ulong)shost->io_port,
2910 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2911 boardp->irq, shost->dma_channel);
2913 if (asc_dvc_varp->bus_type & ASC_IS_VL) {
2915 } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) {
2917 } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) {
2918 if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA)
2919 == ASC_IS_PCI_ULTRA) {
2920 busname = "PCI Ultra";
2926 ASC_PRINT2("advansys_info: board %d: unknown "
2927 "bus type %d\n", boardp->id,
2928 asc_dvc_varp->bus_type);
2931 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X",
2932 ASC_VERSION, busname, (ulong)shost->io_port,
2933 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2938 * Wide Adapter Information
2940 * Memory-mapped I/O is used instead of I/O space to access
2941 * the adapter, but display the I/O Port range. The Memory
2942 * I/O address is displayed through the driver /proc file.
2944 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
2945 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2946 widename = "Ultra-Wide";
2947 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
2948 widename = "Ultra2-Wide";
2950 widename = "Ultra3-Wide";
2953 "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X",
2954 ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base,
2955 (ulong)adv_dvc_varp->iop_base + boardp->asc_n_io_port - 1, boardp->irq);
2957 BUG_ON(strlen(info) >= ASC_INFO_SIZE);
2958 ASC_DBG(1, "advansys_info: end\n");
2962 #ifdef CONFIG_PROC_FS
2966 * If 'cp' is NULL print to the console, otherwise print to a buffer.
2968 * Return 0 if printing to the console, otherwise return the number of
2969 * bytes written to the buffer.
2971 * Note: If any single line is greater than ASC_PRTLINE_SIZE bytes the stack
2972 * will be corrupted. 's[]' is defined to be ASC_PRTLINE_SIZE bytes.
2974 static int asc_prt_line(char *buf, int buflen, char *fmt, ...)
2978 char s[ASC_PRTLINE_SIZE];
2980 va_start(args, fmt);
2981 ret = vsprintf(s, fmt, args);
2982 BUG_ON(ret >= ASC_PRTLINE_SIZE);
2987 ret = min(buflen, ret);
2988 memcpy(buf, s, ret);
2995 * asc_prt_board_devices()
2997 * Print driver information for devices attached to the board.
2999 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3000 * cf. asc_prt_line().
3002 * Return the number of characters copied into 'cp'. No more than
3003 * 'cplen' characters will be copied to 'cp'.
3005 static int asc_prt_board_devices(struct Scsi_Host *shost, char *cp, int cplen)
3007 struct asc_board *boardp = shost_priv(shost);
3017 len = asc_prt_line(cp, leftlen,
3018 "\nDevice Information for AdvanSys SCSI Host %d:\n",
3022 if (ASC_NARROW_BOARD(boardp)) {
3023 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
3025 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
3028 len = asc_prt_line(cp, leftlen, "Target IDs Detected:");
3030 for (i = 0; i <= ADV_MAX_TID; i++) {
3031 if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) {
3032 len = asc_prt_line(cp, leftlen, " %X,", i);
3036 len = asc_prt_line(cp, leftlen, " (%X=Host Adapter)\n", chip_scsi_id);
3043 * Display Wide Board BIOS Information.
3045 static int asc_prt_adv_bios(struct Scsi_Host *shost, char *cp, int cplen)
3047 struct asc_board *boardp = shost_priv(shost);
3051 ushort major, minor, letter;
3056 len = asc_prt_line(cp, leftlen, "\nROM BIOS Version: ");
3060 * If the BIOS saved a valid signature, then fill in
3061 * the BIOS code segment base address.
3063 if (boardp->bios_signature != 0x55AA) {
3064 len = asc_prt_line(cp, leftlen, "Disabled or Pre-3.1\n");
3066 len = asc_prt_line(cp, leftlen,
3067 "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n");
3069 len = asc_prt_line(cp, leftlen,
3070 "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n");
3073 major = (boardp->bios_version >> 12) & 0xF;
3074 minor = (boardp->bios_version >> 8) & 0xF;
3075 letter = (boardp->bios_version & 0xFF);
3077 len = asc_prt_line(cp, leftlen, "%d.%d%c\n",
3079 letter >= 26 ? '?' : letter + 'A');
3083 * Current available ROM BIOS release is 3.1I for UW
3084 * and 3.2I for U2W. This code doesn't differentiate
3085 * UW and U2W boards.
3087 if (major < 3 || (major <= 3 && minor < 1) ||
3088 (major <= 3 && minor <= 1 && letter < ('I' - 'A'))) {
3089 len = asc_prt_line(cp, leftlen,
3090 "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n");
3092 len = asc_prt_line(cp, leftlen,
3093 "ftp://ftp.connectcom.net/pub\n");
3102 * Add serial number to information bar if signature AAh
3103 * is found in at bit 15-9 (7 bits) of word 1.
3105 * Serial Number consists fo 12 alpha-numeric digits.
3107 * 1 - Product type (A,B,C,D..) Word0: 15-13 (3 bits)
3108 * 2 - MFG Location (A,B,C,D..) Word0: 12-10 (3 bits)
3109 * 3-4 - Product ID (0-99) Word0: 9-0 (10 bits)
3110 * 5 - Product revision (A-J) Word0: " "
3112 * Signature Word1: 15-9 (7 bits)
3113 * 6 - Year (0-9) Word1: 8-6 (3 bits) & Word2: 15 (1 bit)
3114 * 7-8 - Week of the year (1-52) Word1: 5-0 (6 bits)
3116 * 9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits)
3118 * Note 1: Only production cards will have a serial number.
3120 * Note 2: Signature is most significant 7 bits (0xFE).
3122 * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE.
3124 static int asc_get_eeprom_string(ushort *serialnum, uchar *cp)
3128 if ((serialnum[1] & 0xFE00) != ((ushort)0xAA << 8)) {
3132 * First word - 6 digits.
3136 /* Product type - 1st digit. */
3137 if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') {
3138 /* Product type is P=Prototype */
3143 /* Manufacturing location - 2nd digit. */
3144 *cp++ = 'A' + ((w & 0x1C00) >> 10);
3146 /* Product ID - 3rd, 4th digits. */
3148 *cp++ = '0' + (num / 100);
3150 *cp++ = '0' + (num / 10);
3152 /* Product revision - 5th digit. */
3153 *cp++ = 'A' + (num % 10);
3163 * If bit 15 of third word is set, then the
3164 * last digit of the year is greater than 7.
3166 if (serialnum[2] & 0x8000) {
3167 *cp++ = '8' + ((w & 0x1C0) >> 6);
3169 *cp++ = '0' + ((w & 0x1C0) >> 6);
3172 /* Week of year - 7th, 8th digits. */
3174 *cp++ = '0' + num / 10;
3181 w = serialnum[2] & 0x7FFF;
3183 /* Serial number - 9th digit. */
3184 *cp++ = 'A' + (w / 1000);
3186 /* 10th, 11th, 12th digits. */
3188 *cp++ = '0' + num / 100;
3190 *cp++ = '0' + num / 10;
3194 *cp = '\0'; /* Null Terminate the string. */
3200 * asc_prt_asc_board_eeprom()
3202 * Print board EEPROM configuration.
3204 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3205 * cf. asc_prt_line().
3207 * Return the number of characters copied into 'cp'. No more than
3208 * 'cplen' characters will be copied to 'cp'.
3210 static int asc_prt_asc_board_eeprom(struct Scsi_Host *shost, char *cp, int cplen)
3212 struct asc_board *boardp = shost_priv(shost);
3213 ASC_DVC_VAR *asc_dvc_varp;
3220 int isa_dma_speed[] = { 10, 8, 7, 6, 5, 4, 3, 2 };
3221 #endif /* CONFIG_ISA */
3222 uchar serialstr[13];
3224 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
3225 ep = &boardp->eep_config.asc_eep;
3230 len = asc_prt_line(cp, leftlen,
3231 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3235 if (asc_get_eeprom_string((ushort *)&ep->adapter_info[0], serialstr)
3238 asc_prt_line(cp, leftlen, " Serial Number: %s\n",
3242 if (ep->adapter_info[5] == 0xBB) {
3243 len = asc_prt_line(cp, leftlen,
3244 " Default Settings Used for EEPROM-less Adapter.\n");
3247 len = asc_prt_line(cp, leftlen,
3248 " Serial Number Signature Not Present.\n");
3253 len = asc_prt_line(cp, leftlen,
3254 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3255 ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng,
3259 len = asc_prt_line(cp, leftlen,
3260 " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam);
3263 len = asc_prt_line(cp, leftlen, " Target ID: ");
3265 for (i = 0; i <= ASC_MAX_TID; i++) {
3266 len = asc_prt_line(cp, leftlen, " %d", i);
3269 len = asc_prt_line(cp, leftlen, "\n");
3272 len = asc_prt_line(cp, leftlen, " Disconnects: ");
3274 for (i = 0; i <= ASC_MAX_TID; i++) {
3275 len = asc_prt_line(cp, leftlen, " %c",
3277 disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3281 len = asc_prt_line(cp, leftlen, "\n");
3284 len = asc_prt_line(cp, leftlen, " Command Queuing: ");
3286 for (i = 0; i <= ASC_MAX_TID; i++) {
3287 len = asc_prt_line(cp, leftlen, " %c",
3289 use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3293 len = asc_prt_line(cp, leftlen, "\n");
3296 len = asc_prt_line(cp, leftlen, " Start Motor: ");
3298 for (i = 0; i <= ASC_MAX_TID; i++) {
3299 len = asc_prt_line(cp, leftlen, " %c",
3301 start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3305 len = asc_prt_line(cp, leftlen, "\n");
3308 len = asc_prt_line(cp, leftlen, " Synchronous Transfer:");
3310 for (i = 0; i <= ASC_MAX_TID; i++) {
3311 len = asc_prt_line(cp, leftlen, " %c",
3313 init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3317 len = asc_prt_line(cp, leftlen, "\n");
3321 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
3322 len = asc_prt_line(cp, leftlen,
3323 " Host ISA DMA speed: %d MB/S\n",
3324 isa_dma_speed[ASC_EEP_GET_DMA_SPD(ep)]);
3327 #endif /* CONFIG_ISA */
3333 * asc_prt_adv_board_eeprom()
3335 * Print board EEPROM configuration.
3337 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3338 * cf. asc_prt_line().
3340 * Return the number of characters copied into 'cp'. No more than
3341 * 'cplen' characters will be copied to 'cp'.
3343 static int asc_prt_adv_board_eeprom(struct Scsi_Host *shost, char *cp, int cplen)
3345 struct asc_board *boardp = shost_priv(shost);
3346 ADV_DVC_VAR *adv_dvc_varp;
3352 uchar serialstr[13];
3353 ADVEEP_3550_CONFIG *ep_3550 = NULL;
3354 ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL;
3355 ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL;
3358 ushort sdtr_speed = 0;
3360 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
3361 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3362 ep_3550 = &boardp->eep_config.adv_3550_eep;
3363 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3364 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
3366 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
3372 len = asc_prt_line(cp, leftlen,
3373 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3377 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3378 wordp = &ep_3550->serial_number_word1;
3379 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3380 wordp = &ep_38C0800->serial_number_word1;
3382 wordp = &ep_38C1600->serial_number_word1;
3385 if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE) {
3387 asc_prt_line(cp, leftlen, " Serial Number: %s\n",
3391 len = asc_prt_line(cp, leftlen,
3392 " Serial Number Signature Not Present.\n");
3396 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3397 len = asc_prt_line(cp, leftlen,
3398 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3399 ep_3550->adapter_scsi_id,
3400 ep_3550->max_host_qng, ep_3550->max_dvc_qng);
3402 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3403 len = asc_prt_line(cp, leftlen,
3404 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3405 ep_38C0800->adapter_scsi_id,
3406 ep_38C0800->max_host_qng,
3407 ep_38C0800->max_dvc_qng);
3410 len = asc_prt_line(cp, leftlen,
3411 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3412 ep_38C1600->adapter_scsi_id,
3413 ep_38C1600->max_host_qng,
3414 ep_38C1600->max_dvc_qng);
3417 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3418 word = ep_3550->termination;
3419 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3420 word = ep_38C0800->termination_lvd;
3422 word = ep_38C1600->termination_lvd;
3426 termstr = "Low Off/High Off";
3429 termstr = "Low Off/High On";
3432 termstr = "Low On/High On";
3436 termstr = "Automatic";
3440 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3441 len = asc_prt_line(cp, leftlen,
3442 " termination: %u (%s), bios_ctrl: 0x%x\n",
3443 ep_3550->termination, termstr,
3444 ep_3550->bios_ctrl);
3446 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3447 len = asc_prt_line(cp, leftlen,
3448 " termination: %u (%s), bios_ctrl: 0x%x\n",
3449 ep_38C0800->termination_lvd, termstr,
3450 ep_38C0800->bios_ctrl);
3453 len = asc_prt_line(cp, leftlen,
3454 " termination: %u (%s), bios_ctrl: 0x%x\n",
3455 ep_38C1600->termination_lvd, termstr,
3456 ep_38C1600->bios_ctrl);
3460 len = asc_prt_line(cp, leftlen, " Target ID: ");
3462 for (i = 0; i <= ADV_MAX_TID; i++) {
3463 len = asc_prt_line(cp, leftlen, " %X", i);
3466 len = asc_prt_line(cp, leftlen, "\n");
3469 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3470 word = ep_3550->disc_enable;
3471 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3472 word = ep_38C0800->disc_enable;
3474 word = ep_38C1600->disc_enable;
3476 len = asc_prt_line(cp, leftlen, " Disconnects: ");
3478 for (i = 0; i <= ADV_MAX_TID; i++) {
3479 len = asc_prt_line(cp, leftlen, " %c",
3480 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3483 len = asc_prt_line(cp, leftlen, "\n");
3486 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3487 word = ep_3550->tagqng_able;
3488 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3489 word = ep_38C0800->tagqng_able;
3491 word = ep_38C1600->tagqng_able;
3493 len = asc_prt_line(cp, leftlen, " Command Queuing: ");
3495 for (i = 0; i <= ADV_MAX_TID; i++) {
3496 len = asc_prt_line(cp, leftlen, " %c",
3497 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3500 len = asc_prt_line(cp, leftlen, "\n");
3503 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3504 word = ep_3550->start_motor;
3505 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3506 word = ep_38C0800->start_motor;
3508 word = ep_38C1600->start_motor;
3510 len = asc_prt_line(cp, leftlen, " Start Motor: ");
3512 for (i = 0; i <= ADV_MAX_TID; i++) {
3513 len = asc_prt_line(cp, leftlen, " %c",
3514 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3517 len = asc_prt_line(cp, leftlen, "\n");
3520 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3521 len = asc_prt_line(cp, leftlen, " Synchronous Transfer:");
3523 for (i = 0; i <= ADV_MAX_TID; i++) {
3524 len = asc_prt_line(cp, leftlen, " %c",
3526 sdtr_able & ADV_TID_TO_TIDMASK(i)) ?
3530 len = asc_prt_line(cp, leftlen, "\n");
3534 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3535 len = asc_prt_line(cp, leftlen, " Ultra Transfer: ");
3537 for (i = 0; i <= ADV_MAX_TID; i++) {
3538 len = asc_prt_line(cp, leftlen, " %c",
3540 ultra_able & ADV_TID_TO_TIDMASK(i))
3544 len = asc_prt_line(cp, leftlen, "\n");
3548 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3549 word = ep_3550->wdtr_able;
3550 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3551 word = ep_38C0800->wdtr_able;
3553 word = ep_38C1600->wdtr_able;
3555 len = asc_prt_line(cp, leftlen, " Wide Transfer: ");
3557 for (i = 0; i <= ADV_MAX_TID; i++) {
3558 len = asc_prt_line(cp, leftlen, " %c",
3559 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3562 len = asc_prt_line(cp, leftlen, "\n");
3565 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 ||
3566 adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600) {
3567 len = asc_prt_line(cp, leftlen,
3568 " Synchronous Transfer Speed (Mhz):\n ");
3570 for (i = 0; i <= ADV_MAX_TID; i++) {
3574 sdtr_speed = adv_dvc_varp->sdtr_speed1;
3575 } else if (i == 4) {
3576 sdtr_speed = adv_dvc_varp->sdtr_speed2;
3577 } else if (i == 8) {
3578 sdtr_speed = adv_dvc_varp->sdtr_speed3;
3579 } else if (i == 12) {
3580 sdtr_speed = adv_dvc_varp->sdtr_speed4;
3582 switch (sdtr_speed & ADV_MAX_TID) {
3605 len = asc_prt_line(cp, leftlen, "%X:%s ", i, speed_str);
3608 len = asc_prt_line(cp, leftlen, "\n ");
3613 len = asc_prt_line(cp, leftlen, "\n");
3621 * asc_prt_driver_conf()
3623 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3624 * cf. asc_prt_line().
3626 * Return the number of characters copied into 'cp'. No more than
3627 * 'cplen' characters will be copied to 'cp'.
3629 static int asc_prt_driver_conf(struct Scsi_Host *shost, char *cp, int cplen)
3631 struct asc_board *boardp = shost_priv(shost);
3640 len = asc_prt_line(cp, leftlen,
3641 "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n",
3645 len = asc_prt_line(cp, leftlen,
3646 " host_busy %u, last_reset %u, max_id %u, max_lun %u, max_channel %u\n",
3647 shost->host_busy, shost->last_reset, shost->max_id,
3648 shost->max_lun, shost->max_channel);
3651 len = asc_prt_line(cp, leftlen,
3652 " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n",
3653 shost->unique_id, shost->can_queue, shost->this_id,
3654 shost->sg_tablesize, shost->cmd_per_lun);
3657 len = asc_prt_line(cp, leftlen,
3658 " unchecked_isa_dma %d, use_clustering %d\n",
3659 shost->unchecked_isa_dma, shost->use_clustering);
3662 len = asc_prt_line(cp, leftlen,
3663 " flags 0x%x, last_reset 0x%x, jiffies 0x%x, asc_n_io_port 0x%x\n",
3664 boardp->flags, boardp->last_reset, jiffies,
3665 boardp->asc_n_io_port);
3668 len = asc_prt_line(cp, leftlen, " io_port 0x%x\n", shost->io_port);
3671 if (ASC_NARROW_BOARD(boardp)) {
3672 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
3674 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
3681 * asc_prt_asc_board_info()
3683 * Print dynamic board configuration information.
3685 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3686 * cf. asc_prt_line().
3688 * Return the number of characters copied into 'cp'. No more than
3689 * 'cplen' characters will be copied to 'cp'.
3691 static int asc_prt_asc_board_info(struct Scsi_Host *shost, char *cp, int cplen)
3693 struct asc_board *boardp = shost_priv(shost);
3701 int renegotiate = 0;
3703 v = &boardp->dvc_var.asc_dvc_var;
3704 c = &boardp->dvc_cfg.asc_dvc_cfg;
3705 chip_scsi_id = c->chip_scsi_id;
3710 len = asc_prt_line(cp, leftlen,
3711 "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3715 len = asc_prt_line(cp, leftlen, " chip_version %u, mcode_date 0x%x, "
3716 "mcode_version 0x%x, err_code %u\n",
3717 c->chip_version, c->mcode_date, c->mcode_version,
3721 /* Current number of commands waiting for the host. */
3722 len = asc_prt_line(cp, leftlen,
3723 " Total Command Pending: %d\n", v->cur_total_qng);
3726 len = asc_prt_line(cp, leftlen, " Command Queuing:");
3728 for (i = 0; i <= ASC_MAX_TID; i++) {
3729 if ((chip_scsi_id == i) ||
3730 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3733 len = asc_prt_line(cp, leftlen, " %X:%c",
3736 use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ?
3740 len = asc_prt_line(cp, leftlen, "\n");
3743 /* Current number of commands waiting for a device. */
3744 len = asc_prt_line(cp, leftlen, " Command Queue Pending:");
3746 for (i = 0; i <= ASC_MAX_TID; i++) {
3747 if ((chip_scsi_id == i) ||
3748 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3751 len = asc_prt_line(cp, leftlen, " %X:%u", i, v->cur_dvc_qng[i]);
3754 len = asc_prt_line(cp, leftlen, "\n");
3757 /* Current limit on number of commands that can be sent to a device. */
3758 len = asc_prt_line(cp, leftlen, " Command Queue Limit:");
3760 for (i = 0; i <= ASC_MAX_TID; i++) {
3761 if ((chip_scsi_id == i) ||
3762 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3765 len = asc_prt_line(cp, leftlen, " %X:%u", i, v->max_dvc_qng[i]);
3768 len = asc_prt_line(cp, leftlen, "\n");
3771 /* Indicate whether the device has returned queue full status. */
3772 len = asc_prt_line(cp, leftlen, " Command Queue Full:");
3774 for (i = 0; i <= ASC_MAX_TID; i++) {
3775 if ((chip_scsi_id == i) ||
3776 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3779 if (boardp->queue_full & ADV_TID_TO_TIDMASK(i)) {
3780 len = asc_prt_line(cp, leftlen, " %X:Y-%d",
3781 i, boardp->queue_full_cnt[i]);
3783 len = asc_prt_line(cp, leftlen, " %X:N", i);
3787 len = asc_prt_line(cp, leftlen, "\n");
3790 len = asc_prt_line(cp, leftlen, " Synchronous Transfer:");
3792 for (i = 0; i <= ASC_MAX_TID; i++) {
3793 if ((chip_scsi_id == i) ||
3794 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3797 len = asc_prt_line(cp, leftlen, " %X:%c",
3800 sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3804 len = asc_prt_line(cp, leftlen, "\n");
3807 for (i = 0; i <= ASC_MAX_TID; i++) {
3808 uchar syn_period_ix;
3810 if ((chip_scsi_id == i) ||
3811 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3812 ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) {
3816 len = asc_prt_line(cp, leftlen, " %X:", i);
3819 if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0) {
3820 len = asc_prt_line(cp, leftlen, " Asynchronous");
3824 (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index -
3827 len = asc_prt_line(cp, leftlen,
3828 " Transfer Period Factor: %d (%d.%d Mhz),",
3829 v->sdtr_period_tbl[syn_period_ix],
3831 v->sdtr_period_tbl[syn_period_ix],
3838 len = asc_prt_line(cp, leftlen, " REQ/ACK Offset: %d",
3840 sdtr_data[i] & ASC_SYN_MAX_OFFSET);
3844 if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3845 len = asc_prt_line(cp, leftlen, "*\n");
3848 len = asc_prt_line(cp, leftlen, "\n");
3854 len = asc_prt_line(cp, leftlen,
3855 " * = Re-negotiation pending before next command.\n");
3863 * asc_prt_adv_board_info()
3865 * Print dynamic board configuration information.
3867 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3868 * cf. asc_prt_line().
3870 * Return the number of characters copied into 'cp'. No more than
3871 * 'cplen' characters will be copied to 'cp'.
3873 static int asc_prt_adv_board_info(struct Scsi_Host *shost, char *cp, int cplen)
3875 struct asc_board *boardp = shost_priv(shost);
3882 AdvPortAddr iop_base;
3883 ushort chip_scsi_id;
3887 ushort sdtr_able, wdtr_able;
3888 ushort wdtr_done, sdtr_done;
3890 int renegotiate = 0;
3892 v = &boardp->dvc_var.adv_dvc_var;
3893 c = &boardp->dvc_cfg.adv_dvc_cfg;
3894 iop_base = v->iop_base;
3895 chip_scsi_id = v->chip_scsi_id;
3900 len = asc_prt_line(cp, leftlen,
3901 "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3905 len = asc_prt_line(cp, leftlen,
3906 " iop_base 0x%lx, cable_detect: %X, err_code %u\n",
3908 AdvReadWordRegister(iop_base,
3909 IOPW_SCSI_CFG1) & CABLE_DETECT,
3913 len = asc_prt_line(cp, leftlen, " chip_version %u, mcode_date 0x%x, "
3914 "mcode_version 0x%x\n", c->chip_version,
3915 c->mcode_date, c->mcode_version);
3918 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
3919 len = asc_prt_line(cp, leftlen, " Queuing Enabled:");
3921 for (i = 0; i <= ADV_MAX_TID; i++) {
3922 if ((chip_scsi_id == i) ||
3923 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3927 len = asc_prt_line(cp, leftlen, " %X:%c",
3929 (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3933 len = asc_prt_line(cp, leftlen, "\n");
3936 len = asc_prt_line(cp, leftlen, " Queue Limit:");
3938 for (i = 0; i <= ADV_MAX_TID; i++) {
3939 if ((chip_scsi_id == i) ||
3940 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3944 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i,
3947 len = asc_prt_line(cp, leftlen, " %X:%d", i, lrambyte);
3950 len = asc_prt_line(cp, leftlen, "\n");
3953 len = asc_prt_line(cp, leftlen, " Command Pending:");
3955 for (i = 0; i <= ADV_MAX_TID; i++) {
3956 if ((chip_scsi_id == i) ||
3957 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3961 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i,
3964 len = asc_prt_line(cp, leftlen, " %X:%d", i, lrambyte);
3967 len = asc_prt_line(cp, leftlen, "\n");
3970 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
3971 len = asc_prt_line(cp, leftlen, " Wide Enabled:");
3973 for (i = 0; i <= ADV_MAX_TID; i++) {
3974 if ((chip_scsi_id == i) ||
3975 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3979 len = asc_prt_line(cp, leftlen, " %X:%c",
3981 (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3985 len = asc_prt_line(cp, leftlen, "\n");
3988 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done);
3989 len = asc_prt_line(cp, leftlen, " Transfer Bit Width:");
3991 for (i = 0; i <= ADV_MAX_TID; i++) {
3992 if ((chip_scsi_id == i) ||
3993 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3997 AdvReadWordLram(iop_base,
3998 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
4001 len = asc_prt_line(cp, leftlen, " %X:%d",
4002 i, (lramword & 0x8000) ? 16 : 8);
4005 if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) &&
4006 (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
4007 len = asc_prt_line(cp, leftlen, "*");
4012 len = asc_prt_line(cp, leftlen, "\n");
4015 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4016 len = asc_prt_line(cp, leftlen, " Synchronous Enabled:");
4018 for (i = 0; i <= ADV_MAX_TID; i++) {
4019 if ((chip_scsi_id == i) ||
4020 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
4024 len = asc_prt_line(cp, leftlen, " %X:%c",
4026 (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
4030 len = asc_prt_line(cp, leftlen, "\n");
4033 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done);
4034 for (i = 0; i <= ADV_MAX_TID; i++) {
4036 AdvReadWordLram(iop_base,
4037 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
4039 lramword &= ~0x8000;
4041 if ((chip_scsi_id == i) ||
4042 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
4043 ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) {
4047 len = asc_prt_line(cp, leftlen, " %X:", i);
4050 if ((lramword & 0x1F) == 0) { /* Check for REQ/ACK Offset 0. */
4051 len = asc_prt_line(cp, leftlen, " Asynchronous");
4055 asc_prt_line(cp, leftlen,
4056 " Transfer Period Factor: ");
4059 if ((lramword & 0x1F00) == 0x1100) { /* 80 Mhz */
4061 asc_prt_line(cp, leftlen, "9 (80.0 Mhz),");
4063 } else if ((lramword & 0x1F00) == 0x1000) { /* 40 Mhz */
4065 asc_prt_line(cp, leftlen, "10 (40.0 Mhz),");
4067 } else { /* 20 Mhz or below. */
4069 period = (((lramword >> 8) * 25) + 50) / 4;
4071 if (period == 0) { /* Should never happen. */
4073 asc_prt_line(cp, leftlen,
4077 len = asc_prt_line(cp, leftlen,
4079 period, 250 / period,
4086 len = asc_prt_line(cp, leftlen, " REQ/ACK Offset: %d",
4091 if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
4092 len = asc_prt_line(cp, leftlen, "*\n");
4095 len = asc_prt_line(cp, leftlen, "\n");
4101 len = asc_prt_line(cp, leftlen,
4102 " * = Re-negotiation pending before next command.\n");
4112 * Copy proc information to a read buffer taking into account the current
4113 * read offset in the file and the remaining space in the read buffer.
4116 asc_proc_copy(off_t advoffset, off_t offset, char *curbuf, int leftlen,
4117 char *cp, int cplen)
4121 ASC_DBG3(2, "asc_proc_copy: offset %d, advoffset %d, cplen %d\n",
4122 (unsigned)offset, (unsigned)advoffset, cplen);
4123 if (offset <= advoffset) {
4124 /* Read offset below current offset, copy everything. */
4125 cnt = min(cplen, leftlen);
4126 ASC_DBG3(2, "asc_proc_copy: curbuf 0x%lx, cp 0x%lx, cnt %d\n",
4127 (ulong)curbuf, (ulong)cp, cnt);
4128 memcpy(curbuf, cp, cnt);
4129 } else if (offset < advoffset + cplen) {
4130 /* Read offset within current range, partial copy. */
4131 cnt = (advoffset + cplen) - offset;
4132 cp = (cp + cplen) - cnt;
4133 cnt = min(cnt, leftlen);
4134 ASC_DBG3(2, "asc_proc_copy: curbuf 0x%lx, cp 0x%lx, cnt %d\n",
4135 (ulong)curbuf, (ulong)cp, cnt);
4136 memcpy(curbuf, cp, cnt);
4141 #ifdef ADVANSYS_STATS
4143 * asc_prt_board_stats()
4145 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
4146 * cf. asc_prt_line().
4148 * Return the number of characters copied into 'cp'. No more than
4149 * 'cplen' characters will be copied to 'cp'.
4151 static int asc_prt_board_stats(struct Scsi_Host *shost, char *cp, int cplen)
4153 struct asc_board *boardp = shost_priv(shost);
4154 struct asc_stats *s = &boardp->asc_stats;
4156 int leftlen = cplen;
4157 int len, totlen = 0;
4159 len = asc_prt_line(cp, leftlen,
4160 "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n",
4164 len = asc_prt_line(cp, leftlen,
4165 " queuecommand %lu, reset %lu, biosparam %lu, interrupt %lu\n",
4166 s->queuecommand, s->reset, s->biosparam,
4170 len = asc_prt_line(cp, leftlen,
4171 " callback %lu, done %lu, build_error %lu, build_noreq %lu, build_nosg %lu\n",
4172 s->callback, s->done, s->build_error,
4173 s->adv_build_noreq, s->adv_build_nosg);
4176 len = asc_prt_line(cp, leftlen,
4177 " exe_noerror %lu, exe_busy %lu, exe_error %lu, exe_unknown %lu\n",
4178 s->exe_noerror, s->exe_busy, s->exe_error,
4183 * Display data transfer statistics.
4185 if (s->cont_cnt > 0) {
4186 len = asc_prt_line(cp, leftlen, " cont_cnt %lu, ", s->cont_cnt);
4189 len = asc_prt_line(cp, leftlen, "cont_xfer %lu.%01lu kb ",
4191 ASC_TENTHS(s->cont_xfer, 2));
4194 /* Contiguous transfer average size */
4195 len = asc_prt_line(cp, leftlen, "avg_xfer %lu.%01lu kb\n",
4196 (s->cont_xfer / 2) / s->cont_cnt,
4197 ASC_TENTHS((s->cont_xfer / 2), s->cont_cnt));
4201 if (s->sg_cnt > 0) {
4203 len = asc_prt_line(cp, leftlen, " sg_cnt %lu, sg_elem %lu, ",
4204 s->sg_cnt, s->sg_elem);
4207 len = asc_prt_line(cp, leftlen, "sg_xfer %lu.%01lu kb\n",
4208 s->sg_xfer / 2, ASC_TENTHS(s->sg_xfer, 2));
4211 /* Scatter gather transfer statistics */
4212 len = asc_prt_line(cp, leftlen, " avg_num_elem %lu.%01lu, ",
4213 s->sg_elem / s->sg_cnt,
4214 ASC_TENTHS(s->sg_elem, s->sg_cnt));
4217 len = asc_prt_line(cp, leftlen, "avg_elem_size %lu.%01lu kb, ",
4218 (s->sg_xfer / 2) / s->sg_elem,
4219 ASC_TENTHS((s->sg_xfer / 2), s->sg_elem));
4222 len = asc_prt_line(cp, leftlen, "avg_xfer_size %lu.%01lu kb\n",
4223 (s->sg_xfer / 2) / s->sg_cnt,
4224 ASC_TENTHS((s->sg_xfer / 2), s->sg_cnt));
4229 * Display request queuing statistics.
4231 len = asc_prt_line(cp, leftlen,
4232 " Active and Waiting Request Queues (Time Unit: %d HZ):\n",
4238 #endif /* ADVANSYS_STATS */
4241 * advansys_proc_info() - /proc/scsi/advansys/{0,1,2,3,...}
4243 * *buffer: I/O buffer
4244 * **start: if inout == FALSE pointer into buffer where user read should start
4245 * offset: current offset into a /proc/scsi/advansys/[0...] file
4246 * length: length of buffer
4247 * hostno: Scsi_Host host_no
4248 * inout: TRUE - user is writing; FALSE - user is reading
4250 * Return the number of bytes read from or written to a
4251 * /proc/scsi/advansys/[0...] file.
4253 * Note: This function uses the per board buffer 'prtbuf' which is
4254 * allocated when the board is initialized in advansys_detect(). The
4255 * buffer is ASC_PRTBUF_SIZE bytes. The function asc_proc_copy() is
4256 * used to write to the buffer. The way asc_proc_copy() is written
4257 * if 'prtbuf' is too small it will not be overwritten. Instead the
4258 * user just won't get all the available statistics.
4261 advansys_proc_info(struct Scsi_Host *shost, char *buffer, char **start,
4262 off_t offset, int length, int inout)
4264 struct asc_board *boardp = shost_priv(shost);
4273 ASC_DBG(1, "advansys_proc_info: begin\n");
4276 * User write not supported.
4282 * User read of /proc/scsi/advansys/[0...] file.
4285 /* Copy read data starting at the beginning of the buffer. */
4293 * Get board configuration information.
4295 * advansys_info() returns the board string from its own static buffer.
4297 cp = (char *)advansys_info(shost);
4300 /* Copy board information. */
4301 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4305 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4312 * Display Wide Board BIOS Information.
4314 if (!ASC_NARROW_BOARD(boardp)) {
4315 cp = boardp->prtbuf;
4316 cplen = asc_prt_adv_bios(shost, cp, ASC_PRTBUF_SIZE);
4317 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4318 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp,
4323 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4331 * Display driver information for each device attached to the board.
4333 cp = boardp->prtbuf;
4334 cplen = asc_prt_board_devices(shost, cp, ASC_PRTBUF_SIZE);
4335 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4336 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4340 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4347 * Display EEPROM configuration for the board.
4349 cp = boardp->prtbuf;
4350 if (ASC_NARROW_BOARD(boardp)) {
4351 cplen = asc_prt_asc_board_eeprom(shost, cp, ASC_PRTBUF_SIZE);
4353 cplen = asc_prt_adv_board_eeprom(shost, cp, ASC_PRTBUF_SIZE);
4355 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4356 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4360 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4367 * Display driver configuration and information for the board.
4369 cp = boardp->prtbuf;
4370 cplen = asc_prt_driver_conf(shost, cp, ASC_PRTBUF_SIZE);
4371 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4372 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4376 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4382 #ifdef ADVANSYS_STATS
4384 * Display driver statistics for the board.
4386 cp = boardp->prtbuf;
4387 cplen = asc_prt_board_stats(shost, cp, ASC_PRTBUF_SIZE);
4388 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4389 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4393 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4398 #endif /* ADVANSYS_STATS */
4401 * Display Asc Library dynamic configuration information
4404 cp = boardp->prtbuf;
4405 if (ASC_NARROW_BOARD(boardp)) {
4406 cplen = asc_prt_asc_board_info(shost, cp, ASC_PRTBUF_SIZE);
4408 cplen = asc_prt_adv_board_info(shost, cp, ASC_PRTBUF_SIZE);
4410 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4411 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4415 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4421 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4425 #endif /* CONFIG_PROC_FS */
4427 static void asc_scsi_done(struct scsi_cmnd *scp)
4429 struct asc_board *boardp = shost_priv(scp->device->host);
4432 dma_unmap_sg(boardp->dev,
4433 (struct scatterlist *)scp->request_buffer,
4434 scp->use_sg, scp->sc_data_direction);
4435 else if (scp->request_bufflen)
4436 dma_unmap_single(boardp->dev, scp->SCp.dma_handle,
4437 scp->request_bufflen, scp->sc_data_direction);
4439 ASC_STATS(scp->device->host, done);
4441 scp->scsi_done(scp);
4444 static void AscSetBank(PortAddr iop_base, uchar bank)
4448 val = AscGetChipControl(iop_base) &
4450 (CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET |
4454 } else if (bank == 2) {
4455 val |= CC_DIAG | CC_BANK_ONE;
4457 val &= ~CC_BANK_ONE;
4459 AscSetChipControl(iop_base, val);
4463 static void AscSetChipIH(PortAddr iop_base, ushort ins_code)
4465 AscSetBank(iop_base, 1);
4466 AscWriteChipIH(iop_base, ins_code);
4467 AscSetBank(iop_base, 0);
4471 static int AscStartChip(PortAddr iop_base)
4473 AscSetChipControl(iop_base, 0);
4474 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
4480 static int AscStopChip(PortAddr iop_base)
4485 AscGetChipControl(iop_base) &
4486 (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG));
4487 AscSetChipControl(iop_base, (uchar)(cc_val | CC_HALT));
4488 AscSetChipIH(iop_base, INS_HALT);
4489 AscSetChipIH(iop_base, INS_RFLAG_WTM);
4490 if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) {
4496 static int AscIsChipHalted(PortAddr iop_base)
4498 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
4499 if ((AscGetChipControl(iop_base) & CC_HALT) != 0) {
4506 static int AscResetChipAndScsiBus(ASC_DVC_VAR *asc_dvc)
4511 iop_base = asc_dvc->iop_base;
4512 while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE)
4516 AscStopChip(iop_base);
4517 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT);
4519 AscSetChipIH(iop_base, INS_RFLAG_WTM);
4520 AscSetChipIH(iop_base, INS_HALT);
4521 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT);
4522 AscSetChipControl(iop_base, CC_HALT);
4524 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
4525 AscSetChipStatus(iop_base, 0);
4526 return (AscIsChipHalted(iop_base));
4529 static int AscFindSignature(PortAddr iop_base)
4533 ASC_DBG2(1, "AscFindSignature: AscGetChipSignatureByte(0x%x) 0x%x\n",
4534 iop_base, AscGetChipSignatureByte(iop_base));
4535 if (AscGetChipSignatureByte(iop_base) == (uchar)ASC_1000_ID1B) {
4537 "AscFindSignature: AscGetChipSignatureWord(0x%x) 0x%x\n",
4538 iop_base, AscGetChipSignatureWord(iop_base));
4539 sig_word = AscGetChipSignatureWord(iop_base);
4540 if ((sig_word == (ushort)ASC_1000_ID0W) ||
4541 (sig_word == (ushort)ASC_1000_ID0W_FIX)) {
4548 static void AscEnableInterrupt(PortAddr iop_base)
4552 cfg = AscGetChipCfgLsw(iop_base);
4553 AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON);
4557 static void AscDisableInterrupt(PortAddr iop_base)
4561 cfg = AscGetChipCfgLsw(iop_base);
4562 AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON));
4566 static uchar AscReadLramByte(PortAddr iop_base, ushort addr)
4568 unsigned char byte_data;
4569 unsigned short word_data;
4571 if (isodd_word(addr)) {
4572 AscSetChipLramAddr(iop_base, addr - 1);
4573 word_data = AscGetChipLramData(iop_base);
4574 byte_data = (word_data >> 8) & 0xFF;
4576 AscSetChipLramAddr(iop_base, addr);
4577 word_data = AscGetChipLramData(iop_base);
4578 byte_data = word_data & 0xFF;
4583 static ushort AscReadLramWord(PortAddr iop_base, ushort addr)
4587 AscSetChipLramAddr(iop_base, addr);
4588 word_data = AscGetChipLramData(iop_base);
4592 #if CC_VERY_LONG_SG_LIST
4593 static ASC_DCNT AscReadLramDWord(PortAddr iop_base, ushort addr)
4595 ushort val_low, val_high;
4596 ASC_DCNT dword_data;
4598 AscSetChipLramAddr(iop_base, addr);
4599 val_low = AscGetChipLramData(iop_base);
4600 val_high = AscGetChipLramData(iop_base);
4601 dword_data = ((ASC_DCNT) val_high << 16) | (ASC_DCNT) val_low;
4602 return (dword_data);
4604 #endif /* CC_VERY_LONG_SG_LIST */
4607 AscMemWordSetLram(PortAddr iop_base, ushort s_addr, ushort set_wval, int words)
4611 AscSetChipLramAddr(iop_base, s_addr);
4612 for (i = 0; i < words; i++) {
4613 AscSetChipLramData(iop_base, set_wval);
4617 static void AscWriteLramWord(PortAddr iop_base, ushort addr, ushort word_val)
4619 AscSetChipLramAddr(iop_base, addr);
4620 AscSetChipLramData(iop_base, word_val);
4624 static void AscWriteLramByte(PortAddr iop_base, ushort addr, uchar byte_val)
4628 if (isodd_word(addr)) {
4630 word_data = AscReadLramWord(iop_base, addr);
4631 word_data &= 0x00FF;
4632 word_data |= (((ushort)byte_val << 8) & 0xFF00);
4634 word_data = AscReadLramWord(iop_base, addr);
4635 word_data &= 0xFF00;
4636 word_data |= ((ushort)byte_val & 0x00FF);
4638 AscWriteLramWord(iop_base, addr, word_data);
4643 * Copy 2 bytes to LRAM.
4645 * The source data is assumed to be in little-endian order in memory
4646 * and is maintained in little-endian order when written to LRAM.
4649 AscMemWordCopyPtrToLram(PortAddr iop_base,
4650 ushort s_addr, uchar *s_buffer, int words)
4654 AscSetChipLramAddr(iop_base, s_addr);
4655 for (i = 0; i < 2 * words; i += 2) {
4657 * On a little-endian system the second argument below
4658 * produces a little-endian ushort which is written to
4659 * LRAM in little-endian order. On a big-endian system
4660 * the second argument produces a big-endian ushort which
4661 * is "transparently" byte-swapped by outpw() and written
4662 * in little-endian order to LRAM.
4664 outpw(iop_base + IOP_RAM_DATA,
4665 ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);
4671 * Copy 4 bytes to LRAM.
4673 * The source data is assumed to be in little-endian order in memory
4674 * and is maintained in little-endian order when writen to LRAM.
4677 AscMemDWordCopyPtrToLram(PortAddr iop_base,
4678 ushort s_addr, uchar *s_buffer, int dwords)
4682 AscSetChipLramAddr(iop_base, s_addr);
4683 for (i = 0; i < 4 * dwords; i += 4) {
4684 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]); /* LSW */
4685 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 3] << 8) | s_buffer[i + 2]); /* MSW */
4691 * Copy 2 bytes from LRAM.
4693 * The source data is assumed to be in little-endian order in LRAM
4694 * and is maintained in little-endian order when written to memory.
4697 AscMemWordCopyPtrFromLram(PortAddr iop_base,
4698 ushort s_addr, uchar *d_buffer, int words)
4703 AscSetChipLramAddr(iop_base, s_addr);
4704 for (i = 0; i < 2 * words; i += 2) {
4705 word = inpw(iop_base + IOP_RAM_DATA);
4706 d_buffer[i] = word & 0xff;
4707 d_buffer[i + 1] = (word >> 8) & 0xff;
4712 static ASC_DCNT AscMemSumLramWord(PortAddr iop_base, ushort s_addr, int words)
4718 for (i = 0; i < words; i++, s_addr += 2) {
4719 sum += AscReadLramWord(iop_base, s_addr);
4724 static ushort AscInitLram(ASC_DVC_VAR *asc_dvc)
4731 iop_base = asc_dvc->iop_base;
4733 AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0,
4734 (ushort)(((int)(asc_dvc->max_total_qng + 2 + 1) *
4736 i = ASC_MIN_ACTIVE_QNO;
4737 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
4738 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4740 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4741 (uchar)(asc_dvc->max_total_qng));
4742 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4745 s_addr += ASC_QBLK_SIZE;
4746 for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
4747 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4749 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4751 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4754 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4755 (uchar)ASC_QLINK_END);
4756 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4757 (uchar)(asc_dvc->max_total_qng - 1));
4758 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4759 (uchar)asc_dvc->max_total_qng);
4761 s_addr += ASC_QBLK_SIZE;
4762 for (; i <= (uchar)(asc_dvc->max_total_qng + 3);
4763 i++, s_addr += ASC_QBLK_SIZE) {
4764 AscWriteLramByte(iop_base,
4765 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_FWD), i);
4766 AscWriteLramByte(iop_base,
4767 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_BWD), i);
4768 AscWriteLramByte(iop_base,
4769 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_QNO), i);
4775 AscLoadMicroCode(PortAddr iop_base,
4776 ushort s_addr, uchar *mcode_buf, ushort mcode_size)
4779 ushort mcode_word_size;
4780 ushort mcode_chksum;
4782 /* Write the microcode buffer starting at LRAM address 0. */
4783 mcode_word_size = (ushort)(mcode_size >> 1);
4784 AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size);
4785 AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size);
4787 chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size);
4788 ASC_DBG1(1, "AscLoadMicroCode: chksum 0x%lx\n", (ulong)chksum);
4789 mcode_chksum = (ushort)AscMemSumLramWord(iop_base,
4790 (ushort)ASC_CODE_SEC_BEG,
4791 (ushort)((mcode_size -
4795 ASC_DBG1(1, "AscLoadMicroCode: mcode_chksum 0x%lx\n",
4796 (ulong)mcode_chksum);
4797 AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum);
4798 AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size);
4802 /* Microcode buffer is kept after initialization for error recovery. */
4803 static uchar _asc_mcode_buf[] = {
4804 0x01, 0x03, 0x01, 0x19, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4805 0x00, 0x00, 0x00, 0x00, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F,
4806 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4807 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4808 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4809 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC3, 0x12, 0x0D, 0x05,
4810 0x01, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4811 0xFF, 0x80, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4812 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0xFF,
4813 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00,
4814 0x00, 0x00, 0xE4, 0x88, 0x00, 0x00, 0x00, 0x00, 0x80, 0x73, 0x48, 0x04,
4815 0x36, 0x00, 0x00, 0xA2, 0xC2, 0x00, 0x80, 0x73, 0x03, 0x23, 0x36, 0x40,
4816 0xB6, 0x00, 0x36, 0x00, 0x05, 0xD6, 0x0C, 0xD2, 0x12, 0xDA, 0x00, 0xA2,
4817 0xC2, 0x00, 0x92, 0x80, 0x1E, 0x98, 0x50, 0x00, 0xF5, 0x00, 0x48, 0x98,
4818 0xDF, 0x23, 0x36, 0x60, 0xB6, 0x00, 0x92, 0x80, 0x4F, 0x00, 0xF5, 0x00,
4819 0x48, 0x98, 0xEF, 0x23, 0x36, 0x60, 0xB6, 0x00, 0x92, 0x80, 0x80, 0x62,
4820 0x92, 0x80, 0x00, 0x46, 0x15, 0xEE, 0x13, 0xEA, 0x02, 0x01, 0x09, 0xD8,
4821 0xCD, 0x04, 0x4D, 0x00, 0x00, 0xA3, 0xD6, 0x00, 0xA6, 0x97, 0x7F, 0x23,
4822 0x04, 0x61, 0x84, 0x01, 0xE6, 0x84, 0xD2, 0xC1, 0x80, 0x73, 0xCD, 0x04,
4823 0x4D, 0x00, 0x00, 0xA3, 0xDA, 0x01, 0xA6, 0x97, 0xC6, 0x81, 0xC2, 0x88,
4824 0x80, 0x73, 0x80, 0x77, 0x00, 0x01, 0x01, 0xA1, 0xFE, 0x00, 0x4F, 0x00,
4825 0x84, 0x97, 0x07, 0xA6, 0x08, 0x01, 0x00, 0x33, 0x03, 0x00, 0xC2, 0x88,
4826 0x03, 0x03, 0x01, 0xDE, 0xC2, 0x88, 0xCE, 0x00, 0x69, 0x60, 0xCE, 0x00,
4827 0x02, 0x03, 0x4A, 0x60, 0x00, 0xA2, 0x78, 0x01, 0x80, 0x63, 0x07, 0xA6,
4828 0x24, 0x01, 0x78, 0x81, 0x03, 0x03, 0x80, 0x63, 0xE2, 0x00, 0x07, 0xA6,
4829 0x34, 0x01, 0x00, 0x33, 0x04, 0x00, 0xC2, 0x88, 0x03, 0x07, 0x02, 0x01,
4830 0x04, 0xCA, 0x0D, 0x23, 0x68, 0x98, 0x4D, 0x04, 0x04, 0x85, 0x05, 0xD8,
4831 0x0D, 0x23, 0x68, 0x98, 0xCD, 0x04, 0x15, 0x23, 0xF8, 0x88, 0xFB, 0x23,
4832 0x02, 0x61, 0x82, 0x01, 0x80, 0x63, 0x02, 0x03, 0x06, 0xA3, 0x62, 0x01,
4833 0x00, 0x33, 0x0A, 0x00, 0xC2, 0x88, 0x4E, 0x00, 0x07, 0xA3, 0x6E, 0x01,
4834 0x00, 0x33, 0x0B, 0x00, 0xC2, 0x88, 0xCD, 0x04, 0x36, 0x2D, 0x00, 0x33,
4835 0x1A, 0x00, 0xC2, 0x88, 0x50, 0x04, 0x88, 0x81, 0x06, 0xAB, 0x82, 0x01,
4836 0x88, 0x81, 0x4E, 0x00, 0x07, 0xA3, 0x92, 0x01, 0x50, 0x00, 0x00, 0xA3,
4837 0x3C, 0x01, 0x00, 0x05, 0x7C, 0x81, 0x46, 0x97, 0x02, 0x01, 0x05, 0xC6,
4838 0x04, 0x23, 0xA0, 0x01, 0x15, 0x23, 0xA1, 0x01, 0xBE, 0x81, 0xFD, 0x23,
4839 0x02, 0x61, 0x82, 0x01, 0x0A, 0xDA, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA0,
4840 0xB4, 0x01, 0x80, 0x63, 0xCD, 0x04, 0x36, 0x2D, 0x00, 0x33, 0x1B, 0x00,
4841 0xC2, 0x88, 0x06, 0x23, 0x68, 0x98, 0xCD, 0x04, 0xE6, 0x84, 0x06, 0x01,
4842 0x00, 0xA2, 0xD4, 0x01, 0x57, 0x60, 0x00, 0xA0, 0xDA, 0x01, 0xE6, 0x84,
4843 0x80, 0x23, 0xA0, 0x01, 0xE6, 0x84, 0x80, 0x73, 0x4B, 0x00, 0x06, 0x61,
4844 0x00, 0xA2, 0x00, 0x02, 0x04, 0x01, 0x0C, 0xDE, 0x02, 0x01, 0x03, 0xCC,
4845 0x4F, 0x00, 0x84, 0x97, 0xFC, 0x81, 0x08, 0x23, 0x02, 0x41, 0x82, 0x01,
4846 0x4F, 0x00, 0x62, 0x97, 0x48, 0x04, 0x84, 0x80, 0xF0, 0x97, 0x00, 0x46,
4847 0x56, 0x00, 0x03, 0xC0, 0x01, 0x23, 0xE8, 0x00, 0x81, 0x73, 0x06, 0x29,
4848 0x03, 0x42, 0x06, 0xE2, 0x03, 0xEE, 0x6B, 0xEB, 0x11, 0x23, 0xF8, 0x88,
4849 0x04, 0x98, 0xF0, 0x80, 0x80, 0x73, 0x80, 0x77, 0x07, 0xA4, 0x2A, 0x02,
4850 0x7C, 0x95, 0x06, 0xA6, 0x34, 0x02, 0x03, 0xA6, 0x4C, 0x04, 0x46, 0x82,
4851 0x04, 0x01, 0x03, 0xD8, 0xB4, 0x98, 0x6A, 0x96, 0x46, 0x82, 0xFE, 0x95,
4852 0x80, 0x67, 0x83, 0x03, 0x80, 0x63, 0xB6, 0x2D, 0x02, 0xA6, 0x6C, 0x02,
4853 0x07, 0xA6, 0x5A, 0x02, 0x06, 0xA6, 0x5E, 0x02, 0x03, 0xA6, 0x62, 0x02,
4854 0xC2, 0x88, 0x7C, 0x95, 0x48, 0x82, 0x60, 0x96, 0x48, 0x82, 0x04, 0x23,
4855 0xA0, 0x01, 0x14, 0x23, 0xA1, 0x01, 0x3C, 0x84, 0x04, 0x01, 0x0C, 0xDC,
4856 0xE0, 0x23, 0x25, 0x61, 0xEF, 0x00, 0x14, 0x01, 0x4F, 0x04, 0xA8, 0x01,
4857 0x6F, 0x00, 0xA5, 0x01, 0x03, 0x23, 0xA4, 0x01, 0x06, 0x23, 0x9C, 0x01,
4858 0x24, 0x2B, 0x1C, 0x01, 0x02, 0xA6, 0xAA, 0x02, 0x07, 0xA6, 0x5A, 0x02,
4859 0x06, 0xA6, 0x5E, 0x02, 0x03, 0xA6, 0x20, 0x04, 0x01, 0xA6, 0xB4, 0x02,
4860 0x00, 0xA6, 0xB4, 0x02, 0x00, 0x33, 0x12, 0x00, 0xC2, 0x88, 0x00, 0x0E,
4861 0x80, 0x63, 0x00, 0x43, 0x00, 0xA0, 0x8C, 0x02, 0x4D, 0x04, 0x04, 0x01,
4862 0x0B, 0xDC, 0xE7, 0x23, 0x04, 0x61, 0x84, 0x01, 0x10, 0x31, 0x12, 0x35,
4863 0x14, 0x01, 0xEC, 0x00, 0x6C, 0x38, 0x00, 0x3F, 0x00, 0x00, 0xEA, 0x82,
4864 0x18, 0x23, 0x04, 0x61, 0x18, 0xA0, 0xE2, 0x02, 0x04, 0x01, 0xA2, 0xC8,
4865 0x00, 0x33, 0x1F, 0x00, 0xC2, 0x88, 0x08, 0x31, 0x0A, 0x35, 0x0C, 0x39,
4866 0x0E, 0x3D, 0x7E, 0x98, 0xB6, 0x2D, 0x01, 0xA6, 0x14, 0x03, 0x00, 0xA6,
4867 0x14, 0x03, 0x07, 0xA6, 0x0C, 0x03, 0x06, 0xA6, 0x10, 0x03, 0x03, 0xA6,
4868 0x20, 0x04, 0x02, 0xA6, 0x6C, 0x02, 0x00, 0x33, 0x33, 0x00, 0xC2, 0x88,
4869 0x7C, 0x95, 0xEE, 0x82, 0x60, 0x96, 0xEE, 0x82, 0x82, 0x98, 0x80, 0x42,
4870 0x7E, 0x98, 0x64, 0xE4, 0x04, 0x01, 0x2D, 0xC8, 0x31, 0x05, 0x07, 0x01,
4871 0x00, 0xA2, 0x54, 0x03, 0x00, 0x43, 0x87, 0x01, 0x05, 0x05, 0x86, 0x98,
4872 0x7E, 0x98, 0x00, 0xA6, 0x16, 0x03, 0x07, 0xA6, 0x4C, 0x03, 0x03, 0xA6,
4873 0x3C, 0x04, 0x06, 0xA6, 0x50, 0x03, 0x01, 0xA6, 0x16, 0x03, 0x00, 0x33,
4874 0x25, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0x32, 0x83, 0x60, 0x96, 0x32, 0x83,
4875 0x04, 0x01, 0x10, 0xCE, 0x07, 0xC8, 0x05, 0x05, 0xEB, 0x04, 0x00, 0x33,
4876 0x00, 0x20, 0xC0, 0x20, 0x81, 0x62, 0x72, 0x83, 0x00, 0x01, 0x05, 0x05,
4877 0xFF, 0xA2, 0x7A, 0x03, 0xB1, 0x01, 0x08, 0x23, 0xB2, 0x01, 0x2E, 0x83,
4878 0x05, 0x05, 0x15, 0x01, 0x00, 0xA2, 0x9A, 0x03, 0xEC, 0x00, 0x6E, 0x00,
4879 0x95, 0x01, 0x6C, 0x38, 0x00, 0x3F, 0x00, 0x00, 0x01, 0xA6, 0x96, 0x03,
4880 0x00, 0xA6, 0x96, 0x03, 0x10, 0x84, 0x80, 0x42, 0x7E, 0x98, 0x01, 0xA6,
4881 0xA4, 0x03, 0x00, 0xA6, 0xBC, 0x03, 0x10, 0x84, 0xA8, 0x98, 0x80, 0x42,
4882 0x01, 0xA6, 0xA4, 0x03, 0x07, 0xA6, 0xB2, 0x03, 0xD4, 0x83, 0x7C, 0x95,
4883 0xA8, 0x83, 0x00, 0x33, 0x2F, 0x00, 0xC2, 0x88, 0xA8, 0x98, 0x80, 0x42,
4884 0x00, 0xA6, 0xBC, 0x03, 0x07, 0xA6, 0xCA, 0x03, 0xD4, 0x83, 0x7C, 0x95,
4885 0xC0, 0x83, 0x00, 0x33, 0x26, 0x00, 0xC2, 0x88, 0x38, 0x2B, 0x80, 0x32,
4886 0x80, 0x36, 0x04, 0x23, 0xA0, 0x01, 0x12, 0x23, 0xA1, 0x01, 0x10, 0x84,
4887 0x07, 0xF0, 0x06, 0xA4, 0xF4, 0x03, 0x80, 0x6B, 0x80, 0x67, 0x05, 0x23,
4888 0x83, 0x03, 0x80, 0x63, 0x03, 0xA6, 0x0E, 0x04, 0x07, 0xA6, 0x06, 0x04,
4889 0x06, 0xA6, 0x0A, 0x04, 0x00, 0x33, 0x17, 0x00, 0xC2, 0x88, 0x7C, 0x95,
4890 0xF4, 0x83, 0x60, 0x96, 0xF4, 0x83, 0x20, 0x84, 0x07, 0xF0, 0x06, 0xA4,
4891 0x20, 0x04, 0x80, 0x6B, 0x80, 0x67, 0x05, 0x23, 0x83, 0x03, 0x80, 0x63,
4892 0xB6, 0x2D, 0x03, 0xA6, 0x3C, 0x04, 0x07, 0xA6, 0x34, 0x04, 0x06, 0xA6,
4893 0x38, 0x04, 0x00, 0x33, 0x30, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0x20, 0x84,
4894 0x60, 0x96, 0x20, 0x84, 0x1D, 0x01, 0x06, 0xCC, 0x00, 0x33, 0x00, 0x84,
4895 0xC0, 0x20, 0x00, 0x23, 0xEA, 0x00, 0x81, 0x62, 0xA2, 0x0D, 0x80, 0x63,
4896 0x07, 0xA6, 0x5A, 0x04, 0x00, 0x33, 0x18, 0x00, 0xC2, 0x88, 0x03, 0x03,
4897 0x80, 0x63, 0xA3, 0x01, 0x07, 0xA4, 0x64, 0x04, 0x23, 0x01, 0x00, 0xA2,
4898 0x86, 0x04, 0x0A, 0xA0, 0x76, 0x04, 0xE0, 0x00, 0x00, 0x33, 0x1D, 0x00,
4899 0xC2, 0x88, 0x0B, 0xA0, 0x82, 0x04, 0xE0, 0x00, 0x00, 0x33, 0x1E, 0x00,
4900 0xC2, 0x88, 0x42, 0x23, 0xF8, 0x88, 0x00, 0x23, 0x22, 0xA3, 0xE6, 0x04,
4901 0x08, 0x23, 0x22, 0xA3, 0xA2, 0x04, 0x28, 0x23, 0x22, 0xA3, 0xAE, 0x04,
4902 0x02, 0x23, 0x22, 0xA3, 0xC4, 0x04, 0x42, 0x23, 0xF8, 0x88, 0x4A, 0x00,
4903 0x06, 0x61, 0x00, 0xA0, 0xAE, 0x04, 0x45, 0x23, 0xF8, 0x88, 0x04, 0x98,
4904 0x00, 0xA2, 0xC0, 0x04, 0xB4, 0x98, 0x00, 0x33, 0x00, 0x82, 0xC0, 0x20,
4905 0x81, 0x62, 0xE8, 0x81, 0x47, 0x23, 0xF8, 0x88, 0x04, 0x01, 0x0B, 0xDE,
4906 0x04, 0x98, 0xB4, 0x98, 0x00, 0x33, 0x00, 0x81, 0xC0, 0x20, 0x81, 0x62,
4907 0x14, 0x01, 0x00, 0xA0, 0x00, 0x02, 0x43, 0x23, 0xF8, 0x88, 0x04, 0x23,
4908 0xA0, 0x01, 0x44, 0x23, 0xA1, 0x01, 0x80, 0x73, 0x4D, 0x00, 0x03, 0xA3,
4909 0xF4, 0x04, 0x00, 0x33, 0x27, 0x00, 0xC2, 0x88, 0x04, 0x01, 0x04, 0xDC,
4910 0x02, 0x23, 0xA2, 0x01, 0x04, 0x23, 0xA0, 0x01, 0x04, 0x98, 0x26, 0x95,
4911 0x4B, 0x00, 0xF6, 0x00, 0x4F, 0x04, 0x4F, 0x00, 0x00, 0xA3, 0x22, 0x05,
4912 0x00, 0x05, 0x76, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x1C, 0x05, 0x0A, 0x85,
4913 0x46, 0x97, 0xCD, 0x04, 0x24, 0x85, 0x48, 0x04, 0x84, 0x80, 0x02, 0x01,
4914 0x03, 0xDA, 0x80, 0x23, 0x82, 0x01, 0x34, 0x85, 0x02, 0x23, 0xA0, 0x01,
4915 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x40, 0x05, 0x1D, 0x01, 0x04, 0xD6,
4916 0xFF, 0x23, 0x86, 0x41, 0x4B, 0x60, 0xCB, 0x00, 0xFF, 0x23, 0x80, 0x01,
4917 0x49, 0x00, 0x81, 0x01, 0x04, 0x01, 0x02, 0xC8, 0x30, 0x01, 0x80, 0x01,
4918 0xF7, 0x04, 0x03, 0x01, 0x49, 0x04, 0x80, 0x01, 0xC9, 0x00, 0x00, 0x05,
4919 0x00, 0x01, 0xFF, 0xA0, 0x60, 0x05, 0x77, 0x04, 0x01, 0x23, 0xEA, 0x00,
4920 0x5D, 0x00, 0xFE, 0xC7, 0x00, 0x62, 0x00, 0x23, 0xEA, 0x00, 0x00, 0x63,
4921 0x07, 0xA4, 0xF8, 0x05, 0x03, 0x03, 0x02, 0xA0, 0x8E, 0x05, 0xF4, 0x85,
4922 0x00, 0x33, 0x2D, 0x00, 0xC2, 0x88, 0x04, 0xA0, 0xB8, 0x05, 0x80, 0x63,
4923 0x00, 0x23, 0xDF, 0x00, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA2, 0xA4, 0x05,
4924 0x1D, 0x01, 0x06, 0xD6, 0x02, 0x23, 0x02, 0x41, 0x82, 0x01, 0x50, 0x00,
4925 0x62, 0x97, 0x04, 0x85, 0x04, 0x23, 0x02, 0x41, 0x82, 0x01, 0x04, 0x85,
4926 0x08, 0xA0, 0xBE, 0x05, 0xF4, 0x85, 0x03, 0xA0, 0xC4, 0x05, 0xF4, 0x85,
4927 0x01, 0xA0, 0xCE, 0x05, 0x88, 0x00, 0x80, 0x63, 0xCC, 0x86, 0x07, 0xA0,
4928 0xEE, 0x05, 0x5F, 0x00, 0x00, 0x2B, 0xDF, 0x08, 0x00, 0xA2, 0xE6, 0x05,
4929 0x80, 0x67, 0x80, 0x63, 0x01, 0xA2, 0x7A, 0x06, 0x7C, 0x85, 0x06, 0x23,
4930 0x68, 0x98, 0x48, 0x23, 0xF8, 0x88, 0x07, 0x23, 0x80, 0x00, 0x06, 0x87,
4931 0x80, 0x63, 0x7C, 0x85, 0x00, 0x23, 0xDF, 0x00, 0x00, 0x63, 0x4A, 0x00,
4932 0x06, 0x61, 0x00, 0xA2, 0x36, 0x06, 0x1D, 0x01, 0x16, 0xD4, 0xC0, 0x23,
4933 0x07, 0x41, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6, 0x1C, 0x06, 0x00, 0x33,
4934 0x37, 0x00, 0xC2, 0x88, 0x1D, 0x01, 0x01, 0xD6, 0x20, 0x23, 0x63, 0x60,
4935 0x83, 0x03, 0x80, 0x63, 0x02, 0x23, 0xDF, 0x00, 0x07, 0xA6, 0x7C, 0x05,
4936 0xEF, 0x04, 0x6F, 0x00, 0x00, 0x63, 0x4B, 0x00, 0x06, 0x41, 0xCB, 0x00,
4937 0x52, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x4E, 0x06, 0x1D, 0x01, 0x03, 0xCA,
4938 0xC0, 0x23, 0x07, 0x41, 0x00, 0x63, 0x1D, 0x01, 0x04, 0xCC, 0x00, 0x33,
4939 0x00, 0x83, 0xC0, 0x20, 0x81, 0x62, 0x80, 0x23, 0x07, 0x41, 0x00, 0x63,
4940 0x80, 0x67, 0x08, 0x23, 0x83, 0x03, 0x80, 0x63, 0x00, 0x63, 0x01, 0x23,
4941 0xDF, 0x00, 0x06, 0xA6, 0x84, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x80, 0x67,
4942 0x80, 0x63, 0x00, 0x33, 0x00, 0x40, 0xC0, 0x20, 0x81, 0x62, 0x00, 0x63,
4943 0x00, 0x00, 0xFE, 0x95, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6, 0x94, 0x06,
4944 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x00, 0x01, 0xA0, 0x14, 0x07, 0x00, 0x2B,
4945 0x40, 0x0E, 0x80, 0x63, 0x01, 0x00, 0x06, 0xA6, 0xAA, 0x06, 0x07, 0xA6,
4946 0x7C, 0x05, 0x40, 0x0E, 0x80, 0x63, 0x00, 0x43, 0x00, 0xA0, 0xA2, 0x06,
4947 0x06, 0xA6, 0xBC, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x80, 0x67, 0x40, 0x0E,
4948 0x80, 0x63, 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x23, 0xDF, 0x00, 0x00, 0x63,
4949 0x07, 0xA6, 0xD6, 0x06, 0x00, 0x33, 0x2A, 0x00, 0xC2, 0x88, 0x03, 0x03,
4950 0x80, 0x63, 0x89, 0x00, 0x0A, 0x2B, 0x07, 0xA6, 0xE8, 0x06, 0x00, 0x33,
4951 0x29, 0x00, 0xC2, 0x88, 0x00, 0x43, 0x00, 0xA2, 0xF4, 0x06, 0xC0, 0x0E,
4952 0x80, 0x63, 0xDE, 0x86, 0xC0, 0x0E, 0x00, 0x33, 0x00, 0x80, 0xC0, 0x20,
4953 0x81, 0x62, 0x04, 0x01, 0x02, 0xDA, 0x80, 0x63, 0x7C, 0x85, 0x80, 0x7B,
4954 0x80, 0x63, 0x06, 0xA6, 0x8C, 0x06, 0x00, 0x33, 0x2C, 0x00, 0xC2, 0x88,
4955 0x0C, 0xA2, 0x2E, 0x07, 0xFE, 0x95, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6,
4956 0x2C, 0x07, 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x33, 0x3D, 0x00, 0xC2, 0x88,
4957 0x00, 0x00, 0x80, 0x67, 0x83, 0x03, 0x80, 0x63, 0x0C, 0xA0, 0x44, 0x07,
4958 0x07, 0xA6, 0x7C, 0x05, 0xBF, 0x23, 0x04, 0x61, 0x84, 0x01, 0xE6, 0x84,
4959 0x00, 0x63, 0xF0, 0x04, 0x01, 0x01, 0xF1, 0x00, 0x00, 0x01, 0xF2, 0x00,
4960 0x01, 0x05, 0x80, 0x01, 0x72, 0x04, 0x71, 0x00, 0x81, 0x01, 0x70, 0x04,
4961 0x80, 0x05, 0x81, 0x05, 0x00, 0x63, 0xF0, 0x04, 0xF2, 0x00, 0x72, 0x04,
4962 0x01, 0x01, 0xF1, 0x00, 0x70, 0x00, 0x81, 0x01, 0x70, 0x04, 0x71, 0x00,
4963 0x81, 0x01, 0x72, 0x00, 0x80, 0x01, 0x71, 0x04, 0x70, 0x00, 0x80, 0x01,
4964 0x70, 0x04, 0x00, 0x63, 0xF0, 0x04, 0xF2, 0x00, 0x72, 0x04, 0x00, 0x01,
4965 0xF1, 0x00, 0x70, 0x00, 0x80, 0x01, 0x70, 0x04, 0x71, 0x00, 0x80, 0x01,
4966 0x72, 0x00, 0x81, 0x01, 0x71, 0x04, 0x70, 0x00, 0x81, 0x01, 0x70, 0x04,
4967 0x00, 0x63, 0x00, 0x23, 0xB3, 0x01, 0x83, 0x05, 0xA3, 0x01, 0xA2, 0x01,
4968 0xA1, 0x01, 0x01, 0x23, 0xA0, 0x01, 0x00, 0x01, 0xC8, 0x00, 0x03, 0xA1,
4969 0xC4, 0x07, 0x00, 0x33, 0x07, 0x00, 0xC2, 0x88, 0x80, 0x05, 0x81, 0x05,
4970 0x04, 0x01, 0x11, 0xC8, 0x48, 0x00, 0xB0, 0x01, 0xB1, 0x01, 0x08, 0x23,
4971 0xB2, 0x01, 0x05, 0x01, 0x48, 0x04, 0x00, 0x43, 0x00, 0xA2, 0xE4, 0x07,
4972 0x00, 0x05, 0xDA, 0x87, 0x00, 0x01, 0xC8, 0x00, 0xFF, 0x23, 0x80, 0x01,
4973 0x05, 0x05, 0x00, 0x63, 0xF7, 0x04, 0x1A, 0x09, 0xF6, 0x08, 0x6E, 0x04,
4974 0x00, 0x02, 0x80, 0x43, 0x76, 0x08, 0x80, 0x02, 0x77, 0x04, 0x00, 0x63,
4975 0xF7, 0x04, 0x1A, 0x09, 0xF6, 0x08, 0x6E, 0x04, 0x00, 0x02, 0x00, 0xA0,
4976 0x14, 0x08, 0x16, 0x88, 0x00, 0x43, 0x76, 0x08, 0x80, 0x02, 0x77, 0x04,
4977 0x00, 0x63, 0xF3, 0x04, 0x00, 0x23, 0xF4, 0x00, 0x74, 0x00, 0x80, 0x43,
4978 0xF4, 0x00, 0xCF, 0x40, 0x00, 0xA2, 0x44, 0x08, 0x74, 0x04, 0x02, 0x01,
4979 0xF7, 0xC9, 0xF6, 0xD9, 0x00, 0x01, 0x01, 0xA1, 0x24, 0x08, 0x04, 0x98,
4980 0x26, 0x95, 0x24, 0x88, 0x73, 0x04, 0x00, 0x63, 0xF3, 0x04, 0x75, 0x04,
4981 0x5A, 0x88, 0x02, 0x01, 0x04, 0xD8, 0x46, 0x97, 0x04, 0x98, 0x26, 0x95,
4982 0x4A, 0x88, 0x75, 0x00, 0x00, 0xA3, 0x64, 0x08, 0x00, 0x05, 0x4E, 0x88,
4983 0x73, 0x04, 0x00, 0x63, 0x80, 0x7B, 0x80, 0x63, 0x06, 0xA6, 0x76, 0x08,
4984 0x00, 0x33, 0x3E, 0x00, 0xC2, 0x88, 0x80, 0x67, 0x83, 0x03, 0x80, 0x63,
4985 0x00, 0x63, 0x38, 0x2B, 0x9C, 0x88, 0x38, 0x2B, 0x92, 0x88, 0x32, 0x09,
4986 0x31, 0x05, 0x92, 0x98, 0x05, 0x05, 0xB2, 0x09, 0x00, 0x63, 0x00, 0x32,
4987 0x00, 0x36, 0x00, 0x3A, 0x00, 0x3E, 0x00, 0x63, 0x80, 0x32, 0x80, 0x36,
4988 0x80, 0x3A, 0x80, 0x3E, 0xB4, 0x3D, 0x00, 0x63, 0x38, 0x2B, 0x40, 0x32,
4989 0x40, 0x36, 0x40, 0x3A, 0x40, 0x3E, 0x00, 0x63, 0x5A, 0x20, 0xC9, 0x40,
4990 0x00, 0xA0, 0xB4, 0x08, 0x5D, 0x00, 0xFE, 0xC3, 0x00, 0x63, 0x80, 0x73,
4991 0xE6, 0x20, 0x02, 0x23, 0xE8, 0x00, 0x82, 0x73, 0xFF, 0xFD, 0x80, 0x73,
4992 0x13, 0x23, 0xF8, 0x88, 0x66, 0x20, 0xC0, 0x20, 0x04, 0x23, 0xA0, 0x01,
4993 0xA1, 0x23, 0xA1, 0x01, 0x81, 0x62, 0xE2, 0x88, 0x80, 0x73, 0x80, 0x77,
4994 0x68, 0x00, 0x00, 0xA2, 0x80, 0x00, 0x03, 0xC2, 0xF1, 0xC7, 0x41, 0x23,
4995 0xF8, 0x88, 0x11, 0x23, 0xA1, 0x01, 0x04, 0x23, 0xA0, 0x01, 0xE6, 0x84,
4998 static unsigned short _asc_mcode_size = sizeof(_asc_mcode_buf);
4999 static ADV_DCNT _asc_mcode_chksum = 0x012C453FUL;
5001 /* Microcode buffer is kept after initialization for error recovery. */
5002 static unsigned char _adv_asc3550_buf[] = {
5003 0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0x16, 0x18, 0xe4, 0x00, 0xfc,
5004 0x01, 0x00, 0x48, 0xe4, 0xbe, 0x18, 0x18, 0x80, 0x03, 0xf6, 0x02, 0x00,
5005 0x00, 0xfa, 0xff, 0xff, 0x28, 0x0e, 0x9e, 0xe7, 0xff, 0x00, 0x82, 0xe7,
5006 0x00, 0xea, 0x00, 0xf6, 0x01, 0xe6, 0x09, 0xe7, 0x55, 0xf0, 0x01, 0xf6,
5007 0x01, 0xfa, 0x08, 0x00, 0x03, 0x00, 0x04, 0x00, 0x18, 0xf4, 0x10, 0x00,
5008 0x00, 0xec, 0x85, 0xf0, 0xbc, 0x00, 0xd5, 0xf0, 0x8e, 0x0c, 0x38, 0x54,
5009 0x00, 0xe6, 0x1e, 0xf0, 0x86, 0xf0, 0xb4, 0x00, 0x98, 0x57, 0xd0, 0x01,
5010 0x0c, 0x1c, 0x3e, 0x1c, 0x0c, 0x00, 0xbb, 0x00, 0xaa, 0x18, 0x02, 0x80,
5011 0x32, 0xf0, 0x01, 0xfc, 0x88, 0x0c, 0xc6, 0x12, 0x02, 0x13, 0x18, 0x40,
5012 0x00, 0x57, 0x01, 0xea, 0x3c, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x04, 0x12,
5013 0x3e, 0x57, 0x00, 0x80, 0x03, 0xe6, 0xb6, 0x00, 0xc0, 0x00, 0x01, 0x01,
5014 0x3e, 0x01, 0xda, 0x0f, 0x22, 0x10, 0x08, 0x12, 0x02, 0x4a, 0xb9, 0x54,
5015 0x03, 0x58, 0x1b, 0x80, 0x30, 0xe4, 0x4b, 0xe4, 0x20, 0x00, 0x32, 0x00,
5016 0x3e, 0x00, 0x80, 0x00, 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01,
5017 0x70, 0x01, 0x72, 0x01, 0x74, 0x01, 0x76, 0x01, 0x78, 0x01, 0x62, 0x0a,
5018 0x92, 0x0c, 0x2c, 0x10, 0x2e, 0x10, 0x06, 0x13, 0x4c, 0x1c, 0xbb, 0x55,
5019 0x3c, 0x56, 0x04, 0x80, 0x4a, 0xe4, 0x02, 0xee, 0x5b, 0xf0, 0xb1, 0xf0,
5020 0x03, 0xf7, 0x06, 0xf7, 0x03, 0xfc, 0x0f, 0x00, 0x40, 0x00, 0xbe, 0x00,
5021 0x00, 0x01, 0xb0, 0x08, 0x30, 0x13, 0x64, 0x15, 0x32, 0x1c, 0x38, 0x1c,
5022 0x4e, 0x1c, 0x10, 0x44, 0x02, 0x48, 0x00, 0x4c, 0x04, 0xea, 0x5d, 0xf0,
5023 0x04, 0xf6, 0x02, 0xfc, 0x05, 0x00, 0x34, 0x00, 0x36, 0x00, 0x98, 0x00,
5024 0xcc, 0x00, 0x20, 0x01, 0x4e, 0x01, 0x4e, 0x0b, 0x1e, 0x0e, 0x0c, 0x10,
5025 0x0a, 0x12, 0x04, 0x13, 0x40, 0x13, 0x30, 0x1c, 0x00, 0x4e, 0xbd, 0x56,
5026 0x06, 0x83, 0x00, 0xdc, 0x05, 0xf0, 0x09, 0xf0, 0x59, 0xf0, 0xa7, 0xf0,
5027 0xb8, 0xf0, 0x0e, 0xf7, 0x06, 0x00, 0x19, 0x00, 0x33, 0x00, 0x9b, 0x00,
5028 0xa4, 0x00, 0xb5, 0x00, 0xba, 0x00, 0xd0, 0x00, 0xe1, 0x00, 0xe7, 0x00,
5029 0xde, 0x03, 0x56, 0x0a, 0x14, 0x0e, 0x02, 0x10, 0x04, 0x10, 0x0a, 0x10,
5030 0x36, 0x10, 0x0a, 0x13, 0x12, 0x13, 0x52, 0x13, 0x10, 0x15, 0x14, 0x15,
5031 0xac, 0x16, 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c, 0x08, 0x44, 0x38, 0x44,
5032 0x91, 0x44, 0x0a, 0x45, 0x48, 0x46, 0x01, 0x48, 0x68, 0x54, 0x83, 0x55,
5033 0xb0, 0x57, 0x01, 0x58, 0x83, 0x59, 0x05, 0xe6, 0x0b, 0xf0, 0x0c, 0xf0,
5034 0x5c, 0xf0, 0x4b, 0xf4, 0x04, 0xf8, 0x05, 0xf8, 0x02, 0xfa, 0x03, 0xfa,
5035 0x04, 0xfc, 0x05, 0xfc, 0x07, 0x00, 0x0a, 0x00, 0x0d, 0x00, 0x1c, 0x00,
5036 0x9e, 0x00, 0xa8, 0x00, 0xaa, 0x00, 0xb9, 0x00, 0xe0, 0x00, 0x22, 0x01,
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5332 0x03, 0x0a, 0x50, 0x01, 0x82, 0x0a, 0x3f, 0x01, 0x82, 0x03, 0xfc, 0x1c,
5333 0x10, 0xff, 0x03, 0x00, 0x54, 0xfe, 0x00, 0xf4, 0x19, 0x48, 0xfe, 0x00,
5334 0x7d, 0xfe, 0x01, 0x7d, 0xfe, 0x02, 0x7d, 0xfe, 0x03, 0x7c, 0x63, 0x27,
5335 0x0c, 0x52, 0x18, 0x53, 0xbe, 0x56, 0xbf, 0x57, 0x03, 0xfe, 0x62, 0x08,
5336 0xfe, 0x82, 0x4a, 0xfe, 0xe1, 0x1a, 0xfe, 0x83, 0x5a, 0x74, 0x03, 0x01,
5337 0xfe, 0x14, 0x18, 0xfe, 0x42, 0x48, 0x5f, 0x60, 0x89, 0x01, 0x08, 0x1f,
5338 0xfe, 0xa2, 0x14, 0x30, 0x2e, 0xd8, 0x01, 0x08, 0x1f, 0xfe, 0xa2, 0x14,
5339 0x30, 0x2e, 0xfe, 0xe8, 0x0a, 0xfe, 0xc1, 0x59, 0x05, 0xc6, 0x28, 0xfe,
5340 0xcc, 0x12, 0x49, 0x04, 0x1b, 0xfe, 0xc4, 0x13, 0x23, 0x62, 0x1b, 0xe2,
5341 0x4b, 0xc3, 0x64, 0xfe, 0xe8, 0x13, 0x3b, 0x13, 0x06, 0x17, 0xc3, 0x78,
5342 0xdb, 0xfe, 0x78, 0x10, 0xff, 0x02, 0x83, 0x55, 0xa1, 0xff, 0x02, 0x83,
5343 0x55, 0x62, 0x1a, 0xa4, 0xbb, 0xfe, 0x30, 0x00, 0x8e, 0xe4, 0x17, 0x2c,
5344 0x13, 0x06, 0xfe, 0x56, 0x10, 0x62, 0x0b, 0xe1, 0xbb, 0xfe, 0x64, 0x00,
5345 0x8e, 0xe4, 0x0a, 0xfe, 0x64, 0x00, 0x17, 0x93, 0x13, 0x06, 0xfe, 0x28,
5346 0x10, 0x62, 0x06, 0xfe, 0x60, 0x13, 0xbb, 0xfe, 0xc8, 0x00, 0x8e, 0xe4,
5347 0x0a, 0xfe, 0xc8, 0x00, 0x17, 0x4d, 0x13, 0x06, 0x83, 0xbb, 0xfe, 0x90,
5348 0x01, 0xba, 0xfe, 0x4e, 0x14, 0x89, 0xfe, 0x12, 0x10, 0xfe, 0x43, 0xf4,
5349 0x94, 0xfe, 0x56, 0xf0, 0xfe, 0x60, 0x14, 0xfe, 0x04, 0xf4, 0x6c, 0xfe,
5350 0x43, 0xf4, 0x93, 0xfe, 0xf3, 0x10, 0xf9, 0x01, 0xfe, 0x22, 0x13, 0x1c,
5351 0x3d, 0xfe, 0x10, 0x13, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4, 0x69, 0xba,
5352 0xfe, 0x9c, 0x14, 0xb7, 0x69, 0xfe, 0x1c, 0x10, 0xfe, 0x00, 0x17, 0xfe,
5353 0x4d, 0xe4, 0x19, 0xba, 0xfe, 0x9c, 0x14, 0xb7, 0x19, 0x83, 0x60, 0x23,
5354 0xfe, 0x4d, 0xf4, 0x00, 0xdf, 0x89, 0x13, 0x06, 0xfe, 0xb4, 0x56, 0xfe,
5355 0xc3, 0x58, 0x03, 0x60, 0x13, 0x0b, 0x03, 0x15, 0x06, 0x01, 0x08, 0x26,
5356 0xe5, 0x15, 0x0b, 0x01, 0x08, 0x26, 0xe5, 0x15, 0x1a, 0x01, 0x08, 0x26,
5357 0xe5, 0x72, 0xfe, 0x89, 0x49, 0x01, 0x08, 0x03, 0x15, 0x06, 0x01, 0x08,
5358 0x26, 0xa6, 0x15, 0x1a, 0x01, 0x08, 0x26, 0xa6, 0x15, 0x06, 0x01, 0x08,
5359 0x26, 0xa6, 0xfe, 0x89, 0x49, 0x01, 0x08, 0x26, 0xa6, 0x72, 0xfe, 0x89,
5360 0x4a, 0x01, 0x08, 0x03, 0x60, 0x03, 0x1e, 0xcc, 0x07, 0x06, 0xfe, 0x44,
5361 0x13, 0xad, 0x12, 0xcc, 0xfe, 0x49, 0xf4, 0x00, 0x3b, 0x72, 0x9f, 0x5e,
5362 0xfe, 0x01, 0xec, 0xfe, 0x27, 0x01, 0xf1, 0x01, 0x08, 0x2f, 0x07, 0xfe,
5363 0xe3, 0x00, 0xfe, 0x20, 0x13, 0x1f, 0xfe, 0x5a, 0x15, 0x23, 0x12, 0xcd,
5364 0x01, 0x43, 0x1e, 0xcd, 0x07, 0x06, 0x45, 0x09, 0x4a, 0x06, 0x35, 0x03,
5365 0x0a, 0x42, 0x01, 0x0e, 0xed, 0x88, 0x07, 0x10, 0xa4, 0x0a, 0x80, 0x01,
5366 0x0e, 0x88, 0x0a, 0x51, 0x01, 0x9e, 0x03, 0x0a, 0x80, 0x01, 0x0e, 0x88,
5367 0xfe, 0x80, 0xe7, 0x10, 0x07, 0x10, 0x84, 0xfe, 0x45, 0x58, 0x01, 0xe3,
5368 0x88, 0x03, 0x0a, 0x42, 0x01, 0x0e, 0x88, 0x0a, 0x51, 0x01, 0x9e, 0x03,
5369 0x0a, 0x42, 0x01, 0x0e, 0xfe, 0x80, 0x80, 0xf2, 0xfe, 0x49, 0xe4, 0x10,
5370 0xa4, 0x0a, 0x80, 0x01, 0x0e, 0xf2, 0x0a, 0x51, 0x01, 0x82, 0x03, 0x17,
5371 0x10, 0x71, 0x66, 0xfe, 0x60, 0x01, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde,
5372 0xfe, 0x24, 0x1c, 0xfe, 0x1d, 0xf7, 0x1d, 0x90, 0xfe, 0xf6, 0x15, 0x01,
5373 0xfe, 0xfc, 0x16, 0xe0, 0x91, 0x1d, 0x66, 0xfe, 0x2c, 0x01, 0xfe, 0x2f,
5374 0x19, 0x03, 0xae, 0x21, 0xfe, 0xe6, 0x15, 0xfe, 0xda, 0x10, 0x17, 0x10,
5375 0x71, 0x05, 0xfe, 0x64, 0x01, 0xfe, 0x00, 0xf4, 0x19, 0xfe, 0x18, 0x58,
5376 0x05, 0xfe, 0x66, 0x01, 0xfe, 0x19, 0x58, 0x91, 0x19, 0xfe, 0x3c, 0x90,
5377 0xfe, 0x30, 0xf4, 0x06, 0xfe, 0x3c, 0x50, 0x66, 0xfe, 0x38, 0x00, 0xfe,
5378 0x0f, 0x79, 0xfe, 0x1c, 0xf7, 0x19, 0x90, 0xfe, 0x40, 0x16, 0xfe, 0xb6,
5379 0x14, 0x34, 0x03, 0xae, 0x21, 0xfe, 0x18, 0x16, 0xfe, 0x9c, 0x10, 0x17,
5380 0x10, 0x71, 0xfe, 0x83, 0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe,
5381 0x1d, 0xf7, 0x38, 0x90, 0xfe, 0x62, 0x16, 0xfe, 0x94, 0x14, 0xfe, 0x10,
5382 0x13, 0x91, 0x38, 0x66, 0x1b, 0xfe, 0xaf, 0x19, 0xfe, 0x98, 0xe7, 0x00,
5383 0x03, 0xae, 0x21, 0xfe, 0x56, 0x16, 0xfe, 0x6c, 0x10, 0x17, 0x10, 0x71,
5384 0xfe, 0x30, 0xbc, 0xfe, 0xb2, 0xbc, 0x91, 0xc5, 0x66, 0x1b, 0xfe, 0x0f,
5385 0x79, 0xfe, 0x1c, 0xf7, 0xc5, 0x90, 0xfe, 0x9a, 0x16, 0xfe, 0x5c, 0x14,
5386 0x34, 0x03, 0xae, 0x21, 0xfe, 0x86, 0x16, 0xfe, 0x42, 0x10, 0xfe, 0x02,
5387 0xf6, 0x10, 0x71, 0xfe, 0x18, 0xfe, 0x54, 0xfe, 0x19, 0xfe, 0x55, 0xfc,
5388 0xfe, 0x1d, 0xf7, 0x4f, 0x90, 0xfe, 0xc0, 0x16, 0xfe, 0x36, 0x14, 0xfe,
5389 0x1c, 0x13, 0x91, 0x4f, 0x47, 0xfe, 0x83, 0x58, 0xfe, 0xaf, 0x19, 0xfe,
5390 0x80, 0xe7, 0x10, 0xfe, 0x81, 0xe7, 0x10, 0x11, 0xfe, 0xdd, 0x00, 0x63,
5391 0x27, 0x03, 0x63, 0x27, 0xfe, 0x12, 0x45, 0x21, 0xfe, 0xb0, 0x16, 0x14,
5392 0x06, 0x37, 0x95, 0xa9, 0x02, 0x29, 0xfe, 0x39, 0xf0, 0xfe, 0x04, 0x17,
5393 0x23, 0x03, 0xfe, 0x7e, 0x18, 0x1c, 0x1a, 0x5d, 0x13, 0x0d, 0x03, 0x71,
5394 0x05, 0xcb, 0x1c, 0x06, 0xfe, 0xef, 0x12, 0xfe, 0xe1, 0x10, 0x78, 0x2c,
5395 0x46, 0x2f, 0x07, 0x2d, 0xfe, 0x3c, 0x13, 0xfe, 0x82, 0x14, 0xfe, 0x42,
5396 0x13, 0x3c, 0x8a, 0x0a, 0x42, 0x01, 0x0e, 0xb0, 0xfe, 0x3e, 0x12, 0xf0,
5397 0xfe, 0x45, 0x48, 0x01, 0xe3, 0xfe, 0x00, 0xcc, 0xb0, 0xfe, 0xf3, 0x13,
5398 0x3d, 0x75, 0x07, 0x10, 0xa3, 0x0a, 0x80, 0x01, 0x0e, 0xf2, 0x01, 0x6f,
5399 0xfe, 0x16, 0x10, 0x07, 0x7e, 0x85, 0xfe, 0x40, 0x14, 0xfe, 0x24, 0x12,
5400 0xf6, 0xfe, 0xd6, 0xf0, 0xfe, 0x24, 0x17, 0x17, 0x0b, 0x03, 0xfe, 0x9c,
5401 0xe7, 0x0b, 0x0f, 0xfe, 0x15, 0x00, 0x59, 0x76, 0x27, 0x01, 0xda, 0x17,
5402 0x06, 0x03, 0x3c, 0x8a, 0x09, 0x4a, 0x1d, 0x35, 0x11, 0x2d, 0x01, 0x6f,
5403 0x17, 0x06, 0x03, 0xfe, 0x38, 0x90, 0xfe, 0xba, 0x90, 0x79, 0xc7, 0x68,
5404 0xc8, 0xfe, 0x48, 0x55, 0x34, 0xfe, 0xc9, 0x55, 0x03, 0x1e, 0x98, 0x73,
5405 0x12, 0x98, 0x03, 0x0a, 0x99, 0x01, 0x0e, 0xf0, 0x0a, 0x40, 0x01, 0x0e,
5406 0xfe, 0x49, 0x44, 0x16, 0xfe, 0xf0, 0x17, 0x73, 0x75, 0x03, 0x0a, 0x42,
5407 0x01, 0x0e, 0x07, 0x10, 0x45, 0x0a, 0x51, 0x01, 0x9e, 0x0a, 0x40, 0x01,
5408 0x0e, 0x73, 0x75, 0x03, 0xfe, 0x4e, 0xe4, 0x1a, 0x64, 0xfe, 0x24, 0x18,
5409 0x05, 0xfe, 0x90, 0x00, 0xfe, 0x3a, 0x45, 0x5b, 0xfe, 0x4e, 0xe4, 0xc2,
5410 0x64, 0xfe, 0x36, 0x18, 0x05, 0xfe, 0x92, 0x00, 0xfe, 0x02, 0xe6, 0x1b,
5411 0xdc, 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x64, 0xfe, 0x48, 0x18, 0x05,
5412 0xfe, 0x94, 0x00, 0xfe, 0x02, 0xe6, 0x19, 0xfe, 0x08, 0x10, 0x05, 0xfe,
5413 0x96, 0x00, 0xfe, 0x02, 0xe6, 0x2c, 0xfe, 0x4e, 0x45, 0xfe, 0x0c, 0x12,
5414 0xaf, 0xff, 0x04, 0x68, 0x54, 0xde, 0x1c, 0x69, 0x03, 0x07, 0x7a, 0xfe,
5415 0x5a, 0xf0, 0xfe, 0x74, 0x18, 0x24, 0xfe, 0x09, 0x00, 0xfe, 0x34, 0x10,
5416 0x07, 0x1b, 0xfe, 0x5a, 0xf0, 0xfe, 0x82, 0x18, 0x24, 0xc3, 0xfe, 0x26,
5417 0x10, 0x07, 0x1a, 0x5d, 0x24, 0x2c, 0xdc, 0x07, 0x0b, 0x5d, 0x24, 0x93,
5418 0xfe, 0x0e, 0x10, 0x07, 0x06, 0x5d, 0x24, 0x4d, 0x9f, 0xad, 0x03, 0x14,
5419 0xfe, 0x09, 0x00, 0x01, 0x33, 0xfe, 0x04, 0xfe, 0x7d, 0x05, 0x7f, 0xf9,
5420 0x03, 0x25, 0xfe, 0xca, 0x18, 0xfe, 0x14, 0xf0, 0x08, 0x65, 0xfe, 0xc6,
5421 0x18, 0x03, 0xff, 0x1a, 0x00, 0x00,
5424 static unsigned short _adv_asc3550_size = sizeof(_adv_asc3550_buf); /* 0x13AD */
5425 static ADV_DCNT _adv_asc3550_chksum = 0x04D52DDDUL; /* Expanded little-endian checksum. */
5427 /* Microcode buffer is kept after initialization for error recovery. */
5428 static unsigned char _adv_asc38C0800_buf[] = {
5429 0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0xfc, 0x00, 0x16, 0x18, 0xe4,
5430 0x01, 0x00, 0x48, 0xe4, 0x18, 0x80, 0x03, 0xf6, 0x02, 0x00, 0xce, 0x19,
5431 0x00, 0xfa, 0xff, 0xff, 0x1c, 0x0f, 0x00, 0xf6, 0x9e, 0xe7, 0xff, 0x00,
5432 0x82, 0xe7, 0x00, 0xea, 0x01, 0xfa, 0x01, 0xe6, 0x09, 0xe7, 0x55, 0xf0,
5433 0x01, 0xf6, 0x03, 0x00, 0x04, 0x00, 0x10, 0x00, 0x1e, 0xf0, 0x85, 0xf0,
5434 0x18, 0xf4, 0x08, 0x00, 0xbc, 0x00, 0x38, 0x54, 0x00, 0xec, 0xd5, 0xf0,
5435 0x82, 0x0d, 0x00, 0xe6, 0x86, 0xf0, 0xb1, 0xf0, 0x98, 0x57, 0x01, 0xfc,
5436 0xb4, 0x00, 0xd4, 0x01, 0x0c, 0x1c, 0x3e, 0x1c, 0x3c, 0x00, 0xbb, 0x00,
5437 0x00, 0x10, 0xba, 0x19, 0x02, 0x80, 0x32, 0xf0, 0x7c, 0x0d, 0x02, 0x13,
5438 0xba, 0x13, 0x18, 0x40, 0x00, 0x57, 0x01, 0xea, 0x02, 0xfc, 0x03, 0xfc,
5439 0x3e, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x74, 0x01, 0x76, 0x01, 0xb9, 0x54,
5440 0x3e, 0x57, 0x00, 0x80, 0x03, 0xe6, 0xb6, 0x00, 0xc0, 0x00, 0x01, 0x01,
5441 0x3e, 0x01, 0x7a, 0x01, 0xca, 0x08, 0xce, 0x10, 0x16, 0x11, 0x04, 0x12,
5442 0x08, 0x12, 0x02, 0x4a, 0xbb, 0x55, 0x3c, 0x56, 0x03, 0x58, 0x1b, 0x80,
5443 0x30, 0xe4, 0x4b, 0xe4, 0x5d, 0xf0, 0x02, 0xfa, 0x20, 0x00, 0x32, 0x00,
5444 0x40, 0x00, 0x80, 0x00, 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01,
5445 0x70, 0x01, 0x72, 0x01, 0x78, 0x01, 0x7c, 0x01, 0x62, 0x0a, 0x86, 0x0d,
5446 0x06, 0x13, 0x4c, 0x1c, 0x04, 0x80, 0x4a, 0xe4, 0x02, 0xee, 0x5b, 0xf0,
5447 0x03, 0xf7, 0x0c, 0x00, 0x0f, 0x00, 0x47, 0x00, 0xbe, 0x00, 0x00, 0x01,
5448 0x20, 0x11, 0x5c, 0x16, 0x32, 0x1c, 0x38, 0x1c, 0x4e, 0x1c, 0x10, 0x44,
5449 0x00, 0x4c, 0x04, 0xea, 0x5c, 0xf0, 0xa7, 0xf0, 0x04, 0xf6, 0x03, 0xfa,
5450 0x05, 0x00, 0x34, 0x00, 0x36, 0x00, 0x98, 0x00, 0xcc, 0x00, 0x20, 0x01,
5451 0x4e, 0x01, 0x4a, 0x0b, 0x42, 0x0c, 0x12, 0x0f, 0x0c, 0x10, 0x22, 0x11,
5452 0x0a, 0x12, 0x04, 0x13, 0x30, 0x1c, 0x02, 0x48, 0x00, 0x4e, 0x42, 0x54,
5453 0x44, 0x55, 0xbd, 0x56, 0x06, 0x83, 0x00, 0xdc, 0x05, 0xf0, 0x09, 0xf0,
5454 0x59, 0xf0, 0xb8, 0xf0, 0x4b, 0xf4, 0x06, 0xf7, 0x0e, 0xf7, 0x04, 0xfc,
5455 0x05, 0xfc, 0x06, 0x00, 0x19, 0x00, 0x33, 0x00, 0x9b, 0x00, 0xa4, 0x00,
5456 0xb5, 0x00, 0xba, 0x00, 0xd0, 0x00, 0xe1, 0x00, 0xe7, 0x00, 0xe2, 0x03,
5457 0x08, 0x0f, 0x02, 0x10, 0x04, 0x10, 0x0a, 0x10, 0x0a, 0x13, 0x0c, 0x13,
5458 0x12, 0x13, 0x24, 0x14, 0x34, 0x14, 0x04, 0x16, 0x08, 0x16, 0xa4, 0x17,
5459 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c, 0x08, 0x44, 0x38, 0x44, 0x91, 0x44,
5460 0x0a, 0x45, 0x48, 0x46, 0x01, 0x48, 0x68, 0x54, 0x3a, 0x55, 0x83, 0x55,
5461 0xe5, 0x55, 0xb0, 0x57, 0x01, 0x58, 0x83, 0x59, 0x05, 0xe6, 0x0b, 0xf0,
5462 0x0c, 0xf0, 0x04, 0xf8, 0x05, 0xf8, 0x07, 0x00, 0x0a, 0x00, 0x1c, 0x00,
5463 0x1e, 0x00, 0x9e, 0x00, 0xa8, 0x00, 0xaa, 0x00, 0xb9, 0x00, 0xe0, 0x00,
5464 0x22, 0x01, 0x26, 0x01, 0x79, 0x01, 0x7e, 0x01, 0xc4, 0x01, 0xc6, 0x01,
5465 0x80, 0x02, 0x5e, 0x03, 0xee, 0x04, 0x9a, 0x06, 0xf8, 0x07, 0x62, 0x08,
5466 0x68, 0x08, 0x69, 0x08, 0xd6, 0x08, 0xe9, 0x09, 0xfa, 0x0b, 0x2e, 0x0f,
5467 0x12, 0x10, 0x1a, 0x10, 0xed, 0x10, 0xf1, 0x10, 0x2a, 0x11, 0x06, 0x12,
5468 0x0c, 0x12, 0x3e, 0x12, 0x10, 0x13, 0x16, 0x13, 0x1e, 0x13, 0x46, 0x14,
5469 0x76, 0x14, 0x82, 0x14, 0x36, 0x15, 0xca, 0x15, 0x6b, 0x18, 0xbe, 0x18,
5470 0xca, 0x18, 0xe6, 0x19, 0x12, 0x1c, 0x46, 0x1c, 0x9c, 0x32, 0x00, 0x40,
5471 0x0e, 0x47, 0xfe, 0x9c, 0xf0, 0x2b, 0x02, 0xfe, 0xac, 0x0d, 0xff, 0x10,
5472 0x00, 0x00, 0xd7, 0xfe, 0xe8, 0x19, 0x00, 0xd6, 0xfe, 0x84, 0x01, 0xff,
5473 0x03, 0x00, 0x00, 0xfe, 0x93, 0x15, 0xfe, 0x0f, 0x05, 0xff, 0x38, 0x00,
5474 0x00, 0xfe, 0x57, 0x24, 0x00, 0xfe, 0x4c, 0x00, 0x5b, 0xff, 0x04, 0x00,
5475 0x00, 0x11, 0xff, 0x09, 0x00, 0x00, 0xff, 0x08, 0x01, 0x01, 0xff, 0x08,
5476 0xff, 0xff, 0xff, 0x27, 0x00, 0x00, 0xff, 0x10, 0xff, 0xff, 0xff, 0x11,
5477 0x00, 0x00, 0xfe, 0x78, 0x56, 0xfe, 0x34, 0x12, 0xff, 0x21, 0x00, 0x00,
5478 0xfe, 0x04, 0xf7, 0xd6, 0x2c, 0x99, 0x0a, 0x01, 0xfe, 0xc2, 0x0f, 0xfe,
5479 0x04, 0xf7, 0xd6, 0x99, 0x0a, 0x42, 0x2c, 0xfe, 0x3d, 0xf0, 0xfe, 0x06,
5480 0x02, 0xfe, 0x20, 0xf0, 0xa7, 0xfe, 0x91, 0xf0, 0xfe, 0xf4, 0x01, 0xfe,
5481 0x90, 0xf0, 0xfe, 0xf4, 0x01, 0xfe, 0x8f, 0xf0, 0xa7, 0x03, 0x5d, 0x4d,
5482 0x02, 0xfe, 0xc8, 0x0d, 0x01, 0xfe, 0x38, 0x0e, 0xfe, 0xdd, 0x12, 0xfe,
5483 0xfc, 0x10, 0xfe, 0x28, 0x1c, 0x03, 0xfe, 0xa6, 0x00, 0xfe, 0xd3, 0x12,
5484 0x41, 0x14, 0xfe, 0xa6, 0x00, 0xc2, 0xfe, 0x48, 0xf0, 0xfe, 0x8a, 0x02,
5485 0xfe, 0x49, 0xf0, 0xfe, 0xa4, 0x02, 0xfe, 0x4a, 0xf0, 0xfe, 0xc2, 0x02,
5486 0xfe, 0x46, 0xf0, 0xfe, 0x54, 0x02, 0xfe, 0x47, 0xf0, 0xfe, 0x5a, 0x02,
5487 0xfe, 0x43, 0xf0, 0xfe, 0x48, 0x02, 0xfe, 0x44, 0xf0, 0xfe, 0x4c, 0x02,
5488 0xfe, 0x45, 0xf0, 0xfe, 0x50, 0x02, 0x18, 0x0a, 0xaa, 0x18, 0x06, 0x14,
5489 0xa1, 0x02, 0x2b, 0xfe, 0x00, 0x1c, 0xe7, 0xfe, 0x02, 0x1c, 0xe6, 0xfe,
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5785 0xfe, 0x0c, 0x19, 0xfe, 0x42, 0x48, 0x50, 0x51, 0x91, 0x01, 0x0b, 0x1d,
5786 0xfe, 0x96, 0x15, 0x33, 0x31, 0xe1, 0x01, 0x0b, 0x1d, 0xfe, 0x96, 0x15,
5787 0x33, 0x31, 0xfe, 0xe8, 0x0a, 0xfe, 0xc1, 0x59, 0x03, 0xcd, 0x28, 0xfe,
5788 0xcc, 0x12, 0x53, 0x05, 0x1a, 0xfe, 0xc4, 0x13, 0x21, 0x69, 0x1a, 0xee,
5789 0x55, 0xca, 0x6b, 0xfe, 0xdc, 0x14, 0x4d, 0x0f, 0x06, 0x18, 0xca, 0x7c,
5790 0x30, 0xfe, 0x78, 0x10, 0xff, 0x02, 0x83, 0x55, 0xab, 0xff, 0x02, 0x83,
5791 0x55, 0x69, 0x19, 0xae, 0x98, 0xfe, 0x30, 0x00, 0x96, 0xf2, 0x18, 0x6d,
5792 0x0f, 0x06, 0xfe, 0x56, 0x10, 0x69, 0x0a, 0xed, 0x98, 0xfe, 0x64, 0x00,
5793 0x96, 0xf2, 0x09, 0xfe, 0x64, 0x00, 0x18, 0x9e, 0x0f, 0x06, 0xfe, 0x28,
5794 0x10, 0x69, 0x06, 0xfe, 0x60, 0x13, 0x98, 0xfe, 0xc8, 0x00, 0x96, 0xf2,
5795 0x09, 0xfe, 0xc8, 0x00, 0x18, 0x59, 0x0f, 0x06, 0x88, 0x98, 0xfe, 0x90,
5796 0x01, 0x7a, 0xfe, 0x42, 0x15, 0x91, 0xe4, 0xfe, 0x43, 0xf4, 0x9f, 0xfe,
5797 0x56, 0xf0, 0xfe, 0x54, 0x15, 0xfe, 0x04, 0xf4, 0x71, 0xfe, 0x43, 0xf4,
5798 0x9e, 0xfe, 0xf3, 0x10, 0xfe, 0x40, 0x5c, 0x01, 0xfe, 0x16, 0x14, 0x1e,
5799 0x43, 0xec, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4, 0x6e, 0x7a, 0xfe, 0x90,
5800 0x15, 0xc4, 0x6e, 0xfe, 0x1c, 0x10, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4,
5801 0xcc, 0x7a, 0xfe, 0x90, 0x15, 0xc4, 0xcc, 0x88, 0x51, 0x21, 0xfe, 0x4d,
5802 0xf4, 0x00, 0xe9, 0x91, 0x0f, 0x06, 0xfe, 0xb4, 0x56, 0xfe, 0xc3, 0x58,
5803 0x04, 0x51, 0x0f, 0x0a, 0x04, 0x16, 0x06, 0x01, 0x0b, 0x26, 0xf3, 0x16,
5804 0x0a, 0x01, 0x0b, 0x26, 0xf3, 0x16, 0x19, 0x01, 0x0b, 0x26, 0xf3, 0x76,
5805 0xfe, 0x89, 0x49, 0x01, 0x0b, 0x04, 0x16, 0x06, 0x01, 0x0b, 0x26, 0xb1,
5806 0x16, 0x19, 0x01, 0x0b, 0x26, 0xb1, 0x16, 0x06, 0x01, 0x0b, 0x26, 0xb1,
5807 0xfe, 0x89, 0x49, 0x01, 0x0b, 0x26, 0xb1, 0x76, 0xfe, 0x89, 0x4a, 0x01,
5808 0x0b, 0x04, 0x51, 0x04, 0x22, 0xd3, 0x07, 0x06, 0xfe, 0x48, 0x13, 0xb8,
5809 0x13, 0xd3, 0xfe, 0x49, 0xf4, 0x00, 0x4d, 0x76, 0xa9, 0x67, 0xfe, 0x01,
5810 0xec, 0xfe, 0x27, 0x01, 0xfe, 0x89, 0x48, 0xff, 0x02, 0x00, 0x10, 0x27,
5811 0xfe, 0x2e, 0x16, 0x32, 0x07, 0xfe, 0xe3, 0x00, 0xfe, 0x20, 0x13, 0x1d,
5812 0xfe, 0x52, 0x16, 0x21, 0x13, 0xd4, 0x01, 0x4b, 0x22, 0xd4, 0x07, 0x06,
5813 0x4e, 0x08, 0x54, 0x06, 0x37, 0x04, 0x09, 0x48, 0x01, 0x0e, 0xfb, 0x8e,
5814 0x07, 0x11, 0xae, 0x09, 0x84, 0x01, 0x0e, 0x8e, 0x09, 0x5d, 0x01, 0xa8,
5815 0x04, 0x09, 0x84, 0x01, 0x0e, 0x8e, 0xfe, 0x80, 0xe7, 0x11, 0x07, 0x11,
5816 0x8a, 0xfe, 0x45, 0x58, 0x01, 0xf0, 0x8e, 0x04, 0x09, 0x48, 0x01, 0x0e,
5817 0x8e, 0x09, 0x5d, 0x01, 0xa8, 0x04, 0x09, 0x48, 0x01, 0x0e, 0xfe, 0x80,
5818 0x80, 0xfe, 0x80, 0x4c, 0xfe, 0x49, 0xe4, 0x11, 0xae, 0x09, 0x84, 0x01,
5819 0x0e, 0xfe, 0x80, 0x4c, 0x09, 0x5d, 0x01, 0x87, 0x04, 0x18, 0x11, 0x75,
5820 0x6c, 0xfe, 0x60, 0x01, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x24,
5821 0x1c, 0xfe, 0x1d, 0xf7, 0x1b, 0x97, 0xfe, 0xee, 0x16, 0x01, 0xfe, 0xf4,
5822 0x17, 0xad, 0x9a, 0x1b, 0x6c, 0xfe, 0x2c, 0x01, 0xfe, 0x2f, 0x19, 0x04,
5823 0xb9, 0x23, 0xfe, 0xde, 0x16, 0xfe, 0xda, 0x10, 0x18, 0x11, 0x75, 0x03,
5824 0xfe, 0x64, 0x01, 0xfe, 0x00, 0xf4, 0x1f, 0xfe, 0x18, 0x58, 0x03, 0xfe,
5825 0x66, 0x01, 0xfe, 0x19, 0x58, 0x9a, 0x1f, 0xfe, 0x3c, 0x90, 0xfe, 0x30,
5826 0xf4, 0x06, 0xfe, 0x3c, 0x50, 0x6c, 0xfe, 0x38, 0x00, 0xfe, 0x0f, 0x79,
5827 0xfe, 0x1c, 0xf7, 0x1f, 0x97, 0xfe, 0x38, 0x17, 0xfe, 0xb6, 0x14, 0x35,
5828 0x04, 0xb9, 0x23, 0xfe, 0x10, 0x17, 0xfe, 0x9c, 0x10, 0x18, 0x11, 0x75,
5829 0xfe, 0x83, 0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x1d, 0xf7,
5830 0x2e, 0x97, 0xfe, 0x5a, 0x17, 0xfe, 0x94, 0x14, 0xec, 0x9a, 0x2e, 0x6c,
5831 0x1a, 0xfe, 0xaf, 0x19, 0xfe, 0x98, 0xe7, 0x00, 0x04, 0xb9, 0x23, 0xfe,
5832 0x4e, 0x17, 0xfe, 0x6c, 0x10, 0x18, 0x11, 0x75, 0xfe, 0x30, 0xbc, 0xfe,
5833 0xb2, 0xbc, 0x9a, 0xcb, 0x6c, 0x1a, 0xfe, 0x0f, 0x79, 0xfe, 0x1c, 0xf7,
5834 0xcb, 0x97, 0xfe, 0x92, 0x17, 0xfe, 0x5c, 0x14, 0x35, 0x04, 0xb9, 0x23,
5835 0xfe, 0x7e, 0x17, 0xfe, 0x42, 0x10, 0xfe, 0x02, 0xf6, 0x11, 0x75, 0xfe,
5836 0x18, 0xfe, 0x60, 0xfe, 0x19, 0xfe, 0x61, 0xfe, 0x03, 0xa1, 0xfe, 0x1d,
5837 0xf7, 0x5b, 0x97, 0xfe, 0xb8, 0x17, 0xfe, 0x36, 0x14, 0xfe, 0x1c, 0x13,
5838 0x9a, 0x5b, 0x41, 0xfe, 0x83, 0x58, 0xfe, 0xaf, 0x19, 0xfe, 0x80, 0xe7,
5839 0x11, 0xfe, 0x81, 0xe7, 0x11, 0x12, 0xfe, 0xdd, 0x00, 0x6a, 0x2a, 0x04,
5840 0x6a, 0x2a, 0xfe, 0x12, 0x45, 0x23, 0xfe, 0xa8, 0x17, 0x15, 0x06, 0x39,
5841 0xa0, 0xb4, 0x02, 0x2b, 0xfe, 0x39, 0xf0, 0xfe, 0xfc, 0x17, 0x21, 0x04,
5842 0xfe, 0x7e, 0x18, 0x1e, 0x19, 0x66, 0x0f, 0x0d, 0x04, 0x75, 0x03, 0xd2,
5843 0x1e, 0x06, 0xfe, 0xef, 0x12, 0xfe, 0xe1, 0x10, 0x7c, 0x6f, 0x4f, 0x32,
5844 0x07, 0x2f, 0xfe, 0x3c, 0x13, 0xf1, 0xfe, 0x42, 0x13, 0x42, 0x92, 0x09,
5845 0x48, 0x01, 0x0e, 0xbb, 0xeb, 0xfe, 0x41, 0x48, 0xfe, 0x45, 0x48, 0x01,
5846 0xf0, 0xfe, 0x00, 0xcc, 0xbb, 0xfe, 0xf3, 0x13, 0x43, 0x78, 0x07, 0x11,
5847 0xac, 0x09, 0x84, 0x01, 0x0e, 0xfe, 0x80, 0x4c, 0x01, 0x73, 0xfe, 0x16,
5848 0x10, 0x07, 0x82, 0x8b, 0xfe, 0x40, 0x14, 0xfe, 0x24, 0x12, 0xfe, 0x14,
5849 0x56, 0xfe, 0xd6, 0xf0, 0xfe, 0x1c, 0x18, 0x18, 0x0a, 0x04, 0xfe, 0x9c,
5850 0xe7, 0x0a, 0x10, 0xfe, 0x15, 0x00, 0x64, 0x79, 0x2a, 0x01, 0xe3, 0x18,
5851 0x06, 0x04, 0x42, 0x92, 0x08, 0x54, 0x1b, 0x37, 0x12, 0x2f, 0x01, 0x73,
5852 0x18, 0x06, 0x04, 0xfe, 0x38, 0x90, 0xfe, 0xba, 0x90, 0x3a, 0xce, 0x3b,
5853 0xcf, 0xfe, 0x48, 0x55, 0x35, 0xfe, 0xc9, 0x55, 0x04, 0x22, 0xa3, 0x77,
5854 0x13, 0xa3, 0x04, 0x09, 0xa4, 0x01, 0x0e, 0xfe, 0x41, 0x48, 0x09, 0x46,
5855 0x01, 0x0e, 0xfe, 0x49, 0x44, 0x17, 0xfe, 0xe8, 0x18, 0x77, 0x78, 0x04,
5856 0x09, 0x48, 0x01, 0x0e, 0x07, 0x11, 0x4e, 0x09, 0x5d, 0x01, 0xa8, 0x09,
5857 0x46, 0x01, 0x0e, 0x77, 0x78, 0x04, 0xfe, 0x4e, 0xe4, 0x19, 0x6b, 0xfe,
5858 0x1c, 0x19, 0x03, 0xfe, 0x90, 0x00, 0xfe, 0x3a, 0x45, 0xfe, 0x2c, 0x10,
5859 0xfe, 0x4e, 0xe4, 0xc9, 0x6b, 0xfe, 0x2e, 0x19, 0x03, 0xfe, 0x92, 0x00,
5860 0xfe, 0x02, 0xe6, 0x1a, 0xe5, 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x6b,
5861 0xfe, 0x40, 0x19, 0x03, 0xfe, 0x94, 0x00, 0xfe, 0x02, 0xe6, 0x1f, 0xfe,
5862 0x08, 0x10, 0x03, 0xfe, 0x96, 0x00, 0xfe, 0x02, 0xe6, 0x6d, 0xfe, 0x4e,
5863 0x45, 0xea, 0xba, 0xff, 0x04, 0x68, 0x54, 0xe7, 0x1e, 0x6e, 0xfe, 0x08,
5864 0x1c, 0xfe, 0x67, 0x19, 0xfe, 0x0a, 0x1c, 0xfe, 0x1a, 0xf4, 0xfe, 0x00,
5865 0x04, 0xea, 0xfe, 0x48, 0xf4, 0x19, 0x7a, 0xfe, 0x74, 0x19, 0x0f, 0x19,
5866 0x04, 0x07, 0x7e, 0xfe, 0x5a, 0xf0, 0xfe, 0x84, 0x19, 0x25, 0xfe, 0x09,
5867 0x00, 0xfe, 0x34, 0x10, 0x07, 0x1a, 0xfe, 0x5a, 0xf0, 0xfe, 0x92, 0x19,
5868 0x25, 0xca, 0xfe, 0x26, 0x10, 0x07, 0x19, 0x66, 0x25, 0x6d, 0xe5, 0x07,
5869 0x0a, 0x66, 0x25, 0x9e, 0xfe, 0x0e, 0x10, 0x07, 0x06, 0x66, 0x25, 0x59,
5870 0xa9, 0xb8, 0x04, 0x15, 0xfe, 0x09, 0x00, 0x01, 0x36, 0xfe, 0x04, 0xfe,
5871 0x81, 0x03, 0x83, 0xfe, 0x40, 0x5c, 0x04, 0x1c, 0xf7, 0xfe, 0x14, 0xf0,
5872 0x0b, 0x27, 0xfe, 0xd6, 0x19, 0x1c, 0xf7, 0x7b, 0xf7, 0xfe, 0x82, 0xf0,
5873 0xfe, 0xda, 0x19, 0x04, 0xff, 0xcc, 0x00, 0x00,
5876 static unsigned short _adv_asc38C0800_size = sizeof(_adv_asc38C0800_buf); /* 0x14E1 */
5877 static ADV_DCNT _adv_asc38C0800_chksum = 0x050D3FD8UL; /* Expanded little-endian checksum. */
5879 /* Microcode buffer is kept after initialization for error recovery. */
5880 static unsigned char _adv_asc38C1600_buf[] = {
5881 0x00, 0x00, 0x00, 0xf2, 0x00, 0x16, 0x00, 0xfc, 0x00, 0x10, 0x00, 0xf0,
5882 0x18, 0xe4, 0x01, 0x00, 0x04, 0x1e, 0x48, 0xe4, 0x03, 0xf6, 0xf7, 0x13,
5883 0x2e, 0x1e, 0x02, 0x00, 0x07, 0x17, 0xc0, 0x5f, 0x00, 0xfa, 0xff, 0xff,
5884 0x04, 0x00, 0x00, 0xf6, 0x09, 0xe7, 0x82, 0xe7, 0x85, 0xf0, 0x86, 0xf0,
5885 0x4e, 0x10, 0x9e, 0xe7, 0xff, 0x00, 0x55, 0xf0, 0x01, 0xf6, 0x03, 0x00,
5886 0x98, 0x57, 0x01, 0xe6, 0x00, 0xea, 0x00, 0xec, 0x01, 0xfa, 0x18, 0xf4,
5887 0x08, 0x00, 0xf0, 0x1d, 0x38, 0x54, 0x32, 0xf0, 0x10, 0x00, 0xc2, 0x0e,
5888 0x1e, 0xf0, 0xd5, 0xf0, 0xbc, 0x00, 0x4b, 0xe4, 0x00, 0xe6, 0xb1, 0xf0,
5889 0xb4, 0x00, 0x02, 0x13, 0x3e, 0x1c, 0xc8, 0x47, 0x3e, 0x00, 0xd8, 0x01,
5890 0x06, 0x13, 0x0c, 0x1c, 0x5e, 0x1e, 0x00, 0x57, 0xc8, 0x57, 0x01, 0xfc,
5891 0xbc, 0x0e, 0xa2, 0x12, 0xb9, 0x54, 0x00, 0x80, 0x62, 0x0a, 0x5a, 0x12,
5892 0xc8, 0x15, 0x3e, 0x1e, 0x18, 0x40, 0xbd, 0x56, 0x03, 0xe6, 0x01, 0xea,
5893 0x5c, 0xf0, 0x0f, 0x00, 0x20, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x04, 0x12,
5894 0x04, 0x13, 0xbb, 0x55, 0x3c, 0x56, 0x3e, 0x57, 0x03, 0x58, 0x4a, 0xe4,
5895 0x40, 0x00, 0xb6, 0x00, 0xbb, 0x00, 0xc0, 0x00, 0x00, 0x01, 0x01, 0x01,
5896 0x3e, 0x01, 0x58, 0x0a, 0x44, 0x10, 0x0a, 0x12, 0x4c, 0x1c, 0x4e, 0x1c,
5897 0x02, 0x4a, 0x30, 0xe4, 0x05, 0xe6, 0x0c, 0x00, 0x3c, 0x00, 0x80, 0x00,
5898 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01, 0x70, 0x01, 0x72, 0x01,
5899 0x74, 0x01, 0x76, 0x01, 0x78, 0x01, 0x7c, 0x01, 0xc6, 0x0e, 0x0c, 0x10,
5900 0xac, 0x12, 0xae, 0x12, 0x16, 0x1a, 0x32, 0x1c, 0x6e, 0x1e, 0x02, 0x48,
5901 0x3a, 0x55, 0xc9, 0x57, 0x02, 0xee, 0x5b, 0xf0, 0x03, 0xf7, 0x06, 0xf7,
5902 0x03, 0xfc, 0x06, 0x00, 0x1e, 0x00, 0xbe, 0x00, 0xe1, 0x00, 0x0c, 0x12,
5903 0x18, 0x1a, 0x70, 0x1a, 0x30, 0x1c, 0x38, 0x1c, 0x10, 0x44, 0x00, 0x4c,
5904 0xb0, 0x57, 0x40, 0x5c, 0x4d, 0xe4, 0x04, 0xea, 0x5d, 0xf0, 0xa7, 0xf0,
5905 0x04, 0xf6, 0x02, 0xfc, 0x05, 0x00, 0x09, 0x00, 0x19, 0x00, 0x32, 0x00,
5906 0x33, 0x00, 0x34, 0x00, 0x36, 0x00, 0x98, 0x00, 0x9e, 0x00, 0xcc, 0x00,
5907 0x20, 0x01, 0x4e, 0x01, 0x79, 0x01, 0x3c, 0x09, 0x68, 0x0d, 0x02, 0x10,
5908 0x04, 0x10, 0x3a, 0x10, 0x08, 0x12, 0x0a, 0x13, 0x40, 0x16, 0x50, 0x16,
5909 0x00, 0x17, 0x4a, 0x19, 0x00, 0x4e, 0x00, 0x54, 0x01, 0x58, 0x00, 0xdc,
5910 0x05, 0xf0, 0x09, 0xf0, 0x59, 0xf0, 0xb8, 0xf0, 0x48, 0xf4, 0x0e, 0xf7,
5911 0x0a, 0x00, 0x9b, 0x00, 0x9c, 0x00, 0xa4, 0x00, 0xb5, 0x00, 0xba, 0x00,
5912 0xd0, 0x00, 0xe7, 0x00, 0xf0, 0x03, 0x69, 0x08, 0xe9, 0x09, 0x5c, 0x0c,
5913 0xb6, 0x12, 0xbc, 0x19, 0xd8, 0x1b, 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c,
5914 0x42, 0x1d, 0x08, 0x44, 0x38, 0x44, 0x91, 0x44, 0x0a, 0x45, 0x48, 0x46,
5915 0x89, 0x48, 0x68, 0x54, 0x83, 0x55, 0x83, 0x59, 0x31, 0xe4, 0x02, 0xe6,
5916 0x07, 0xf0, 0x08, 0xf0, 0x0b, 0xf0, 0x0c, 0xf0, 0x4b, 0xf4, 0x04, 0xf8,
5917 0x05, 0xf8, 0x02, 0xfa, 0x03, 0xfa, 0x04, 0xfc, 0x05, 0xfc, 0x07, 0x00,
5918 0xa8, 0x00, 0xaa, 0x00, 0xb9, 0x00, 0xe0, 0x00, 0xe5, 0x00, 0x22, 0x01,
5919 0x26, 0x01, 0x60, 0x01, 0x7a, 0x01, 0x82, 0x01, 0xc8, 0x01, 0xca, 0x01,
5920 0x86, 0x02, 0x6a, 0x03, 0x18, 0x05, 0xb2, 0x07, 0x68, 0x08, 0x10, 0x0d,
5921 0x06, 0x10, 0x0a, 0x10, 0x0e, 0x10, 0x12, 0x10, 0x60, 0x10, 0xed, 0x10,
5922 0xf3, 0x10, 0x06, 0x12, 0x10, 0x12, 0x1e, 0x12, 0x0c, 0x13, 0x0e, 0x13,
5923 0x10, 0x13, 0xfe, 0x9c, 0xf0, 0x35, 0x05, 0xfe, 0xec, 0x0e, 0xff, 0x10,
5924 0x00, 0x00, 0xe9, 0xfe, 0x34, 0x1f, 0x00, 0xe8, 0xfe, 0x88, 0x01, 0xff,
5925 0x03, 0x00, 0x00, 0xfe, 0x93, 0x15, 0xfe, 0x0f, 0x05, 0xff, 0x38, 0x00,
5926 0x00, 0xfe, 0x57, 0x24, 0x00, 0xfe, 0x4c, 0x00, 0x65, 0xff, 0x04, 0x00,
5927 0x00, 0x1a, 0xff, 0x09, 0x00, 0x00, 0xff, 0x08, 0x01, 0x01, 0xff, 0x08,
5928 0xff, 0xff, 0xff, 0x27, 0x00, 0x00, 0xff, 0x10, 0xff, 0xff, 0xff, 0x13,
5929 0x00, 0x00, 0xfe, 0x78, 0x56, 0xfe, 0x34, 0x12, 0xff, 0x21, 0x00, 0x00,
5930 0xfe, 0x04, 0xf7, 0xe8, 0x37, 0x7d, 0x0d, 0x01, 0xfe, 0x4a, 0x11, 0xfe,
5931 0x04, 0xf7, 0xe8, 0x7d, 0x0d, 0x51, 0x37, 0xfe, 0x3d, 0xf0, 0xfe, 0x0c,
5932 0x02, 0xfe, 0x20, 0xf0, 0xbc, 0xfe, 0x91, 0xf0, 0xfe, 0xf8, 0x01, 0xfe,
5933 0x90, 0xf0, 0xfe, 0xf8, 0x01, 0xfe, 0x8f, 0xf0, 0xbc, 0x03, 0x67, 0x4d,
5934 0x05, 0xfe, 0x08, 0x0f, 0x01, 0xfe, 0x78, 0x0f, 0xfe, 0xdd, 0x12, 0x05,
5935 0xfe, 0x0e, 0x03, 0xfe, 0x28, 0x1c, 0x03, 0xfe, 0xa6, 0x00, 0xfe, 0xd1,
5936 0x12, 0x3e, 0x22, 0xfe, 0xa6, 0x00, 0xac, 0xfe, 0x48, 0xf0, 0xfe, 0x90,
5937 0x02, 0xfe, 0x49, 0xf0, 0xfe, 0xaa, 0x02, 0xfe, 0x4a, 0xf0, 0xfe, 0xc8,
5938 0x02, 0xfe, 0x46, 0xf0, 0xfe, 0x5a, 0x02, 0xfe, 0x47, 0xf0, 0xfe, 0x60,
5939 0x02, 0xfe, 0x43, 0xf0, 0xfe, 0x4e, 0x02, 0xfe, 0x44, 0xf0, 0xfe, 0x52,
5940 0x02, 0xfe, 0x45, 0xf0, 0xfe, 0x56, 0x02, 0x1c, 0x0d, 0xa2, 0x1c, 0x07,
5941 0x22, 0xb7, 0x05, 0x35, 0xfe, 0x00, 0x1c, 0xfe, 0xf1, 0x10, 0xfe, 0x02,
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6385 0x1d, 0x2e, 0xb4, 0xfe, 0x26, 0x10, 0x09, 0x1d, 0x36, 0x2e, 0x63, 0xfe,
6386 0x1a, 0x10, 0x09, 0x0d, 0x36, 0x2e, 0x94, 0xf2, 0x09, 0x07, 0x36, 0x2e,
6387 0x95, 0xa1, 0xc8, 0x02, 0x1f, 0x93, 0x01, 0x42, 0xfe, 0x04, 0xfe, 0x99,
6388 0x03, 0x9c, 0x8b, 0x02, 0x2a, 0xfe, 0x1c, 0x1e, 0xfe, 0x14, 0xf0, 0x08,
6389 0x2f, 0xfe, 0x0c, 0x1e, 0x2a, 0xfe, 0x1c, 0x1e, 0x8f, 0xfe, 0x1c, 0x1e,
6390 0xfe, 0x82, 0xf0, 0xfe, 0x10, 0x1e, 0x02, 0x0f, 0x3f, 0x04, 0xfe, 0x80,
6391 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x18, 0x80, 0x04, 0xfe, 0x98,
6392 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x02, 0x80, 0x04, 0xfe, 0x82,
6393 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x06, 0x80, 0x04, 0xfe, 0x86,
6394 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x1b, 0x80, 0x04, 0xfe, 0x9b,
6395 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x04, 0x80, 0x04, 0xfe, 0x84,
6396 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x80, 0x80, 0x04, 0xfe, 0x80,
6397 0x83, 0xfe, 0xc9, 0x47, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x19, 0x81, 0x04,
6398 0xfe, 0x99, 0x83, 0xfe, 0xca, 0x47, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x06,
6399 0x83, 0x04, 0xfe, 0x86, 0x83, 0xfe, 0xce, 0x47, 0x0b, 0x0e, 0x02, 0x0f,
6400 0xfe, 0x2c, 0x90, 0x04, 0xfe, 0xac, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f,
6401 0xfe, 0xae, 0x90, 0x04, 0xfe, 0xae, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f,
6402 0xfe, 0x08, 0x90, 0x04, 0xfe, 0x88, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f,
6403 0xfe, 0x8a, 0x90, 0x04, 0xfe, 0x8a, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f,
6404 0xfe, 0x0c, 0x90, 0x04, 0xfe, 0x8c, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f,
6405 0xfe, 0x8e, 0x90, 0x04, 0xfe, 0x8e, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f,
6406 0xfe, 0x3c, 0x90, 0x04, 0xfe, 0xbc, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x8b,
6407 0x0f, 0xfe, 0x03, 0x80, 0x04, 0xfe, 0x83, 0x83, 0x33, 0x0b, 0x77, 0x0e,
6408 0xa8, 0x02, 0xff, 0x66, 0x00, 0x00,
6411 static unsigned short _adv_asc38C1600_size = sizeof(_adv_asc38C1600_buf); /* 0x1673 */
6412 static ADV_DCNT _adv_asc38C1600_chksum = 0x0604EF77UL; /* Expanded little-endian checksum. */
6414 static void AscInitQLinkVar(ASC_DVC_VAR *asc_dvc)
6420 iop_base = asc_dvc->iop_base;
6421 AscPutRiscVarFreeQHead(iop_base, 1);
6422 AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng);
6423 AscPutVarFreeQHead(iop_base, 1);
6424 AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng);
6425 AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B,
6426 (uchar)((int)asc_dvc->max_total_qng + 1));
6427 AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B,
6428 (uchar)((int)asc_dvc->max_total_qng + 2));
6429 AscWriteLramByte(iop_base, (ushort)ASCV_TOTAL_READY_Q_B,
6430 asc_dvc->max_total_qng);
6431 AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0);
6432 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6433 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0);
6434 AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0);
6435 AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0);
6436 AscPutQDoneInProgress(iop_base, 0);
6437 lram_addr = ASC_QADR_BEG;
6438 for (i = 0; i < 32; i++, lram_addr += 2) {
6439 AscWriteLramWord(iop_base, lram_addr, 0);
6443 static ushort AscInitMicroCodeVar(ASC_DVC_VAR *asc_dvc)
6451 iop_base = asc_dvc->iop_base;
6453 for (i = 0; i <= ASC_MAX_TID; i++) {
6454 AscPutMCodeInitSDTRAtID(iop_base, i,
6455 asc_dvc->cfg->sdtr_period_offset[i]);
6458 AscInitQLinkVar(asc_dvc);
6459 AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B,
6460 asc_dvc->cfg->disc_enable);
6461 AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B,
6462 ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id));
6464 /* Align overrun buffer on an 8 byte boundary. */
6465 phy_addr = virt_to_bus(asc_dvc->cfg->overrun_buf);
6466 phy_addr = cpu_to_le32((phy_addr + 7) & ~0x7);
6467 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D,
6468 (uchar *)&phy_addr, 1);
6469 phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE - 8);
6470 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D,
6471 (uchar *)&phy_size, 1);
6473 asc_dvc->cfg->mcode_date =
6474 AscReadLramWord(iop_base, (ushort)ASCV_MC_DATE_W);
6475 asc_dvc->cfg->mcode_version =
6476 AscReadLramWord(iop_base, (ushort)ASCV_MC_VER_W);
6478 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
6479 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
6480 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
6483 if (AscStartChip(iop_base) != 1) {
6484 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
6491 static ushort AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc)
6496 iop_base = asc_dvc->iop_base;
6498 if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) &&
6499 !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) {
6500 AscResetChipAndScsiBus(asc_dvc);
6501 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
6503 asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC;
6504 if (asc_dvc->err_code != 0)
6506 if (!AscFindSignature(asc_dvc->iop_base)) {
6507 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
6510 AscDisableInterrupt(iop_base);
6511 warn_code |= AscInitLram(asc_dvc);
6512 if (asc_dvc->err_code != 0)
6514 ASC_DBG1(1, "AscInitAsc1000Driver: _asc_mcode_chksum 0x%lx\n",
6515 (ulong)_asc_mcode_chksum);
6516 if (AscLoadMicroCode(iop_base, 0, _asc_mcode_buf,
6517 _asc_mcode_size) != _asc_mcode_chksum) {
6518 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
6521 warn_code |= AscInitMicroCodeVar(asc_dvc);
6522 asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC;
6523 AscEnableInterrupt(iop_base);
6528 * Load the Microcode
6530 * Write the microcode image to RISC memory starting at address 0.
6532 * The microcode is stored compressed in the following format:
6534 * 254 word (508 byte) table indexed by byte code followed
6535 * by the following byte codes:
6538 * 00: Emit word 0 in table.
6539 * 01: Emit word 1 in table.
6541 * FD: Emit word 253 in table.
6544 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
6545 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
6547 * Returns 0 or an error if the checksum doesn't match
6549 static int AdvLoadMicrocode(AdvPortAddr iop_base, unsigned char *buf, int size,
6550 int memsize, int chksum)
6552 int i, j, end, len = 0;
6555 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
6557 for (i = 253 * 2; i < size; i++) {
6558 if (buf[i] == 0xff) {
6559 unsigned short word = (buf[i + 3] << 8) | buf[i + 2];
6560 for (j = 0; j < buf[i + 1]; j++) {
6561 AdvWriteWordAutoIncLram(iop_base, word);
6565 } else if (buf[i] == 0xfe) {
6566 unsigned short word = (buf[i + 2] << 8) | buf[i + 1];
6567 AdvWriteWordAutoIncLram(iop_base, word);
6571 unsigned char off = buf[i] * 2;
6572 unsigned short word = (buf[off + 1] << 8) | buf[off];
6573 AdvWriteWordAutoIncLram(iop_base, word);
6580 while (len < memsize) {
6581 AdvWriteWordAutoIncLram(iop_base, 0);
6585 /* Verify the microcode checksum. */
6587 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
6589 for (len = 0; len < end; len += 2) {
6590 sum += AdvReadWordAutoIncLram(iop_base);
6594 return ASC_IERR_MCODE_CHKSUM;
6602 * Return the physical address of 'vaddr' and set '*lenp' to the
6603 * number of physically contiguous bytes that follow 'vaddr'.
6604 * 'flag' indicates the type of structure whose physical address
6605 * is being translated.
6607 * Note: Because Linux currently doesn't page the kernel and all
6608 * kernel buffers are physically contiguous, leave '*lenp' unchanged.
6611 DvcGetPhyAddr(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq,
6612 uchar *vaddr, ADV_SDCNT *lenp, int flag)
6614 ADV_PADDR paddr = virt_to_bus(vaddr);
6616 ASC_DBG4(4, "DvcGetPhyAddr: vaddr 0x%p, lenp 0x%p *lenp %lu, paddr 0x%lx\n",
6617 vaddr, lenp, (ulong)*((ulong *)lenp), (ulong)paddr);
6622 static void AdvBuildCarrierFreelist(struct adv_dvc_var *asc_dvc)
6626 ADV_PADDR carr_paddr;
6628 BUG_ON(!asc_dvc->carrier_buf);
6630 carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
6631 asc_dvc->carr_freelist = NULL;
6632 if (carrp == asc_dvc->carrier_buf) {
6633 buf_size = ADV_CARRIER_BUFSIZE;
6635 buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T);
6639 /* Get physical address of the carrier 'carrp'. */
6640 ADV_DCNT contig_len = sizeof(ADV_CARR_T);
6641 carr_paddr = cpu_to_le32(DvcGetPhyAddr(asc_dvc, NULL,
6643 (ADV_SDCNT *)&contig_len,
6644 ADV_IS_CARRIER_FLAG));
6646 buf_size -= sizeof(ADV_CARR_T);
6649 * If the current carrier is not physically contiguous, then
6650 * maybe there was a page crossing. Try the next carrier
6651 * aligned start address.
6653 if (contig_len < sizeof(ADV_CARR_T)) {
6658 carrp->carr_pa = carr_paddr;
6659 carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp));
6662 * Insert the carrier at the beginning of the freelist.
6665 cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
6666 asc_dvc->carr_freelist = carrp;
6669 } while (buf_size > 0);
6673 * Send an idle command to the chip and wait for completion.
6675 * Command completion is polled for once per microsecond.
6677 * The function can be called from anywhere including an interrupt handler.
6678 * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical()
6679 * functions to prevent reentrancy.
6682 * ADV_TRUE - command completed successfully
6683 * ADV_FALSE - command failed
6684 * ADV_ERROR - command timed out
6687 AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc,
6688 ushort idle_cmd, ADV_DCNT idle_cmd_parameter)
6692 AdvPortAddr iop_base;
6694 iop_base = asc_dvc->iop_base;
6697 * Clear the idle command status which is set by the microcode
6698 * to a non-zero value to indicate when the command is completed.
6699 * The non-zero result is one of the IDLE_CMD_STATUS_* values
6701 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort)0);
6704 * Write the idle command value after the idle command parameter
6705 * has been written to avoid a race condition. If the order is not
6706 * followed, the microcode may process the idle command before the
6707 * parameters have been written to LRAM.
6709 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER,
6710 cpu_to_le32(idle_cmd_parameter));
6711 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd);
6714 * Tickle the RISC to tell it to process the idle command.
6716 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B);
6717 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
6719 * Clear the tickle value. In the ASC-3550 the RISC flag
6720 * command 'clr_tickle_b' does not work unless the host
6723 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
6726 /* Wait for up to 100 millisecond for the idle command to timeout. */
6727 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) {
6728 /* Poll once each microsecond for command completion. */
6729 for (j = 0; j < SCSI_US_PER_MSEC; j++) {
6730 AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS,
6738 BUG(); /* The idle command should never timeout. */
6743 * Reset SCSI Bus and purge all outstanding requests.
6746 * ADV_TRUE(1) - All requests are purged and SCSI Bus is reset.
6747 * ADV_FALSE(0) - Microcode command failed.
6748 * ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC
6749 * may be hung which requires driver recovery.
6751 static int AdvResetSB(ADV_DVC_VAR *asc_dvc)
6756 * Send the SCSI Bus Reset idle start idle command which asserts
6757 * the SCSI Bus Reset signal.
6759 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_START, 0L);
6760 if (status != ADV_TRUE) {
6765 * Delay for the specified SCSI Bus Reset hold time.
6767 * The hold time delay is done on the host because the RISC has no
6768 * microsecond accurate timer.
6770 udelay(ASC_SCSI_RESET_HOLD_TIME_US);
6773 * Send the SCSI Bus Reset end idle command which de-asserts
6774 * the SCSI Bus Reset signal and purges any pending requests.
6776 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_END, 0L);
6777 if (status != ADV_TRUE) {
6781 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
6787 * Initialize the ASC-3550.
6789 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
6791 * For a non-fatal error return a warning code. If there are no warnings
6792 * then 0 is returned.
6794 * Needed after initialization for error recovery.
6796 static int AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc)
6798 AdvPortAddr iop_base;
6807 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
6808 ushort wdtr_able = 0, sdtr_able, tagqng_able;
6809 uchar max_cmd[ADV_MAX_TID + 1];
6811 /* If there is already an error, don't continue. */
6812 if (asc_dvc->err_code != 0)
6816 * The caller must set 'chip_type' to ADV_CHIP_ASC3550.
6818 if (asc_dvc->chip_type != ADV_CHIP_ASC3550) {
6819 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
6824 iop_base = asc_dvc->iop_base;
6827 * Save the RISC memory BIOS region before writing the microcode.
6828 * The BIOS may already be loaded and using its RISC LRAM region
6829 * so its region must be saved and restored.
6831 * Note: This code makes the assumption, which is currently true,
6832 * that a chip reset does not clear RISC LRAM.
6834 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
6835 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
6840 * Save current per TID negotiated values.
6842 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 0x55AA) {
6843 ushort bios_version, major, minor;
6846 bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM) / 2];
6847 major = (bios_version >> 12) & 0xF;
6848 minor = (bios_version >> 8) & 0xF;
6849 if (major < 3 || (major == 3 && minor == 1)) {
6850 /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */
6851 AdvReadWordLram(iop_base, 0x120, wdtr_able);
6853 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
6856 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
6857 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
6858 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
6859 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
6863 asc_dvc->err_code = AdvLoadMicrocode(iop_base, _adv_asc3550_buf,
6864 _adv_asc3550_size, ADV_3550_MEMSIZE,
6865 _adv_asc3550_chksum);
6866 if (asc_dvc->err_code)
6870 * Restore the RISC memory BIOS region.
6872 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
6873 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
6878 * Calculate and write the microcode code checksum to the microcode
6879 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
6881 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
6882 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
6884 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
6885 for (word = begin_addr; word < end_addr; word += 2) {
6886 code_sum += AdvReadWordAutoIncLram(iop_base);
6888 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
6891 * Read and save microcode version and date.
6893 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
6894 asc_dvc->cfg->mcode_date);
6895 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
6896 asc_dvc->cfg->mcode_version);
6899 * Set the chip type to indicate the ASC3550.
6901 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550);
6904 * If the PCI Configuration Command Register "Parity Error Response
6905 * Control" Bit was clear (0), then set the microcode variable
6906 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
6907 * to ignore DMA parity errors.
6909 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
6910 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
6911 word |= CONTROL_FLAG_IGNORE_PERR;
6912 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
6916 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO
6917 * threshold of 128 bytes. This register is only accessible to the host.
6919 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
6920 START_CTL_EMFU | READ_CMD_MRM);
6923 * Microcode operating variables for WDTR, SDTR, and command tag
6924 * queuing will be set in slave_configure() based on what a
6925 * device reports it is capable of in Inquiry byte 7.
6927 * If SCSI Bus Resets have been disabled, then directly set
6928 * SDTR and WDTR from the EEPROM configuration. This will allow
6929 * the BIOS and warm boot to work without a SCSI bus hang on
6930 * the Inquiry caused by host and target mismatched DTR values.
6931 * Without the SCSI Bus Reset, before an Inquiry a device can't
6932 * be assumed to be in Asynchronous, Narrow mode.
6934 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
6935 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
6936 asc_dvc->wdtr_able);
6937 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
6938 asc_dvc->sdtr_able);
6942 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
6943 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
6944 * bitmask. These values determine the maximum SDTR speed negotiated
6947 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
6948 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
6949 * without determining here whether the device supports SDTR.
6951 * 4-bit speed SDTR speed name
6952 * =========== ===============
6953 * 0000b (0x0) SDTR disabled
6955 * 0010b (0x2) 10 Mhz
6956 * 0011b (0x3) 20 Mhz (Ultra)
6957 * 0100b (0x4) 40 Mhz (LVD/Ultra2)
6958 * 0101b (0x5) 80 Mhz (LVD2/Ultra3)
6959 * 0110b (0x6) Undefined
6961 * 1111b (0xF) Undefined
6964 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
6965 if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able) {
6966 /* Set Ultra speed for TID 'tid'. */
6967 word |= (0x3 << (4 * (tid % 4)));
6969 /* Set Fast speed for TID 'tid'. */
6970 word |= (0x2 << (4 * (tid % 4)));
6972 if (tid == 3) { /* Check if done with sdtr_speed1. */
6973 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word);
6975 } else if (tid == 7) { /* Check if done with sdtr_speed2. */
6976 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word);
6978 } else if (tid == 11) { /* Check if done with sdtr_speed3. */
6979 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word);
6981 } else if (tid == 15) { /* Check if done with sdtr_speed4. */
6982 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word);
6988 * Set microcode operating variable for the disconnect per TID bitmask.
6990 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
6991 asc_dvc->cfg->disc_enable);
6994 * Set SCSI_CFG0 Microcode Default Value.
6996 * The microcode will set the SCSI_CFG0 register using this value
6997 * after it is started below.
6999 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
7000 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
7001 asc_dvc->chip_scsi_id);
7004 * Determine SCSI_CFG1 Microcode Default Value.
7006 * The microcode will set the SCSI_CFG1 register using this value
7007 * after it is started below.
7010 /* Read current SCSI_CFG1 Register value. */
7011 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
7014 * If all three connectors are in use, return an error.
7016 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
7017 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) {
7018 asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION;
7023 * If the internal narrow cable is reversed all of the SCSI_CTRL
7024 * register signals will be set. Check for and return an error if
7025 * this condition is found.
7027 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
7028 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
7033 * If this is a differential board and a single-ended device
7034 * is attached to one of the connectors, return an error.
7036 if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0) {
7037 asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE;
7042 * If automatic termination control is enabled, then set the
7043 * termination value based on a table listed in a_condor.h.
7045 * If manual termination was specified with an EEPROM setting
7046 * then 'termination' was set-up in AdvInitFrom3550EEPROM() and
7047 * is ready to be 'ored' into SCSI_CFG1.
7049 if (asc_dvc->cfg->termination == 0) {
7051 * The software always controls termination by setting TERM_CTL_SEL.
7052 * If TERM_CTL_SEL were set to 0, the hardware would set termination.
7054 asc_dvc->cfg->termination |= TERM_CTL_SEL;
7056 switch (scsi_cfg1 & CABLE_DETECT) {
7057 /* TERM_CTL_H: on, TERM_CTL_L: on */
7064 asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L);
7067 /* TERM_CTL_H: on, TERM_CTL_L: off */
7073 asc_dvc->cfg->termination |= TERM_CTL_H;
7076 /* TERM_CTL_H: off, TERM_CTL_L: off */
7084 * Clear any set TERM_CTL_H and TERM_CTL_L bits.
7086 scsi_cfg1 &= ~TERM_CTL;
7089 * Invert the TERM_CTL_H and TERM_CTL_L bits and then
7090 * set 'scsi_cfg1'. The TERM_POL bit does not need to be
7091 * referenced, because the hardware internally inverts
7092 * the Termination High and Low bits if TERM_POL is set.
7094 scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL));
7097 * Set SCSI_CFG1 Microcode Default Value
7099 * Set filter value and possibly modified termination control
7100 * bits in the Microcode SCSI_CFG1 Register Value.
7102 * The microcode will set the SCSI_CFG1 register using this value
7103 * after it is started below.
7105 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1,
7106 FLTR_DISABLE | scsi_cfg1);
7109 * Set MEM_CFG Microcode Default Value
7111 * The microcode will set the MEM_CFG register using this value
7112 * after it is started below.
7114 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
7117 * ASC-3550 has 8KB internal memory.
7119 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
7120 BIOS_EN | RAM_SZ_8KB);
7123 * Set SEL_MASK Microcode Default Value
7125 * The microcode will set the SEL_MASK register using this value
7126 * after it is started below.
7128 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
7129 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
7131 AdvBuildCarrierFreelist(asc_dvc);
7134 * Set-up the Host->RISC Initiator Command Queue (ICQ).
7137 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
7138 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
7141 asc_dvc->carr_freelist = (ADV_CARR_T *)
7142 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
7145 * The first command issued will be placed in the stopper carrier.
7147 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
7150 * Set RISC ICQ physical address start value.
7152 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
7155 * Set-up the RISC->Host Initiator Response Queue (IRQ).
7157 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
7158 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
7161 asc_dvc->carr_freelist = (ADV_CARR_T *)
7162 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
7165 * The first command completed by the RISC will be placed in
7168 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
7169 * completed the RISC will set the ASC_RQ_STOPPER bit.
7171 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
7174 * Set RISC IRQ physical address start value.
7176 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
7177 asc_dvc->carr_pending_cnt = 0;
7179 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
7180 (ADV_INTR_ENABLE_HOST_INTR |
7181 ADV_INTR_ENABLE_GLOBAL_INTR));
7183 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
7184 AdvWriteWordRegister(iop_base, IOPW_PC, word);
7186 /* finally, finally, gentlemen, start your engine */
7187 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
7190 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
7191 * Resets should be performed. The RISC has to be running
7192 * to issue a SCSI Bus Reset.
7194 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
7196 * If the BIOS Signature is present in memory, restore the
7197 * BIOS Handshake Configuration Table and do not perform
7200 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
7203 * Restore per TID negotiated values.
7205 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
7206 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
7207 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
7209 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
7210 AdvWriteByteLram(iop_base,
7211 ASC_MC_NUMBER_OF_MAX_CMD + tid,
7215 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
7216 warn_code = ASC_WARN_BUSRESET_ERROR;
7225 * Initialize the ASC-38C0800.
7227 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
7229 * For a non-fatal error return a warning code. If there are no warnings
7230 * then 0 is returned.
7232 * Needed after initialization for error recovery.
7234 static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc)
7236 AdvPortAddr iop_base;
7246 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
7247 ushort wdtr_able, sdtr_able, tagqng_able;
7248 uchar max_cmd[ADV_MAX_TID + 1];
7250 /* If there is already an error, don't continue. */
7251 if (asc_dvc->err_code != 0)
7255 * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800.
7257 if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800) {
7258 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
7263 iop_base = asc_dvc->iop_base;
7266 * Save the RISC memory BIOS region before writing the microcode.
7267 * The BIOS may already be loaded and using its RISC LRAM region
7268 * so its region must be saved and restored.
7270 * Note: This code makes the assumption, which is currently true,
7271 * that a chip reset does not clear RISC LRAM.
7273 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
7274 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
7279 * Save current per TID negotiated values.
7281 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
7282 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
7283 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
7284 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
7285 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
7290 * RAM BIST (RAM Built-In Self Test)
7292 * Address : I/O base + offset 0x38h register (byte).
7293 * Function: Bit 7-6(RW) : RAM mode
7294 * Normal Mode : 0x00
7295 * Pre-test Mode : 0x40
7296 * RAM Test Mode : 0x80
7298 * Bit 4(RO) : Done bit
7299 * Bit 3-0(RO) : Status
7301 * Int_RAM Error : 0x04
7306 * Note: RAM BIST code should be put right here, before loading the
7307 * microcode and after saving the RISC memory BIOS region.
7313 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
7314 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
7315 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
7316 * to NORMAL_MODE, return an error too.
7318 for (i = 0; i < 2; i++) {
7319 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
7320 mdelay(10); /* Wait for 10ms before reading back. */
7321 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
7322 if ((byte & RAM_TEST_DONE) == 0
7323 || (byte & 0x0F) != PRE_TEST_VALUE) {
7324 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
7328 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
7329 mdelay(10); /* Wait for 10ms before reading back. */
7330 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
7332 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
7338 * LRAM Test - It takes about 1.5 ms to run through the test.
7340 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
7341 * If Done bit not set or Status not 0, save register byte, set the
7342 * err_code, and return an error.
7344 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
7345 mdelay(10); /* Wait for 10ms before checking status. */
7347 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
7348 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
7349 /* Get here if Done bit not set or Status not 0. */
7350 asc_dvc->bist_err_code = byte; /* for BIOS display message */
7351 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
7355 /* We need to reset back to normal mode after LRAM test passes. */
7356 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
7358 asc_dvc->err_code = AdvLoadMicrocode(iop_base, _adv_asc38C0800_buf,
7359 _adv_asc38C0800_size, ADV_38C0800_MEMSIZE,
7360 _adv_asc38C0800_chksum);
7361 if (asc_dvc->err_code)
7365 * Restore the RISC memory BIOS region.
7367 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
7368 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
7373 * Calculate and write the microcode code checksum to the microcode
7374 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
7376 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
7377 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
7379 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
7380 for (word = begin_addr; word < end_addr; word += 2) {
7381 code_sum += AdvReadWordAutoIncLram(iop_base);
7383 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
7386 * Read microcode version and date.
7388 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
7389 asc_dvc->cfg->mcode_date);
7390 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
7391 asc_dvc->cfg->mcode_version);
7394 * Set the chip type to indicate the ASC38C0800.
7396 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800);
7399 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
7400 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
7401 * cable detection and then we are able to read C_DET[3:0].
7403 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
7404 * Microcode Default Value' section below.
7406 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
7407 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
7408 scsi_cfg1 | DIS_TERM_DRV);
7411 * If the PCI Configuration Command Register "Parity Error Response
7412 * Control" Bit was clear (0), then set the microcode variable
7413 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
7414 * to ignore DMA parity errors.
7416 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
7417 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7418 word |= CONTROL_FLAG_IGNORE_PERR;
7419 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7423 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2]
7424 * bits for the default FIFO threshold.
7426 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
7428 * For DMA Errata #4 set the BC_THRESH_ENB bit.
7430 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
7431 BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH |
7435 * Microcode operating variables for WDTR, SDTR, and command tag
7436 * queuing will be set in slave_configure() based on what a
7437 * device reports it is capable of in Inquiry byte 7.
7439 * If SCSI Bus Resets have been disabled, then directly set
7440 * SDTR and WDTR from the EEPROM configuration. This will allow
7441 * the BIOS and warm boot to work without a SCSI bus hang on
7442 * the Inquiry caused by host and target mismatched DTR values.
7443 * Without the SCSI Bus Reset, before an Inquiry a device can't
7444 * be assumed to be in Asynchronous, Narrow mode.
7446 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
7447 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
7448 asc_dvc->wdtr_able);
7449 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
7450 asc_dvc->sdtr_able);
7454 * Set microcode operating variables for DISC and SDTR_SPEED1,
7455 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
7456 * configuration values.
7458 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
7459 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
7460 * without determining here whether the device supports SDTR.
7462 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
7463 asc_dvc->cfg->disc_enable);
7464 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
7465 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
7466 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
7467 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
7470 * Set SCSI_CFG0 Microcode Default Value.
7472 * The microcode will set the SCSI_CFG0 register using this value
7473 * after it is started below.
7475 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
7476 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
7477 asc_dvc->chip_scsi_id);
7480 * Determine SCSI_CFG1 Microcode Default Value.
7482 * The microcode will set the SCSI_CFG1 register using this value
7483 * after it is started below.
7486 /* Read current SCSI_CFG1 Register value. */
7487 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
7490 * If the internal narrow cable is reversed all of the SCSI_CTRL
7491 * register signals will be set. Check for and return an error if
7492 * this condition is found.
7494 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
7495 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
7500 * All kind of combinations of devices attached to one of four
7501 * connectors are acceptable except HVD device attached. For example,
7502 * LVD device can be attached to SE connector while SE device attached
7503 * to LVD connector. If LVD device attached to SE connector, it only
7504 * runs up to Ultra speed.
7506 * If an HVD device is attached to one of LVD connectors, return an
7507 * error. However, there is no way to detect HVD device attached to
7510 if (scsi_cfg1 & HVD) {
7511 asc_dvc->err_code = ASC_IERR_HVD_DEVICE;
7516 * If either SE or LVD automatic termination control is enabled, then
7517 * set the termination value based on a table listed in a_condor.h.
7519 * If manual termination was specified with an EEPROM setting then
7520 * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready
7521 * to be 'ored' into SCSI_CFG1.
7523 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
7524 /* SE automatic termination control is enabled. */
7525 switch (scsi_cfg1 & C_DET_SE) {
7526 /* TERM_SE_HI: on, TERM_SE_LO: on */
7530 asc_dvc->cfg->termination |= TERM_SE;
7533 /* TERM_SE_HI: on, TERM_SE_LO: off */
7535 asc_dvc->cfg->termination |= TERM_SE_HI;
7540 if ((asc_dvc->cfg->termination & TERM_LVD) == 0) {
7541 /* LVD automatic termination control is enabled. */
7542 switch (scsi_cfg1 & C_DET_LVD) {
7543 /* TERM_LVD_HI: on, TERM_LVD_LO: on */
7547 asc_dvc->cfg->termination |= TERM_LVD;
7550 /* TERM_LVD_HI: off, TERM_LVD_LO: off */
7557 * Clear any set TERM_SE and TERM_LVD bits.
7559 scsi_cfg1 &= (~TERM_SE & ~TERM_LVD);
7562 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
7564 scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0);
7567 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE
7568 * bits and set possibly modified termination control bits in the
7569 * Microcode SCSI_CFG1 Register Value.
7571 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE);
7574 * Set SCSI_CFG1 Microcode Default Value
7576 * Set possibly modified termination control and reset DIS_TERM_DRV
7577 * bits in the Microcode SCSI_CFG1 Register Value.
7579 * The microcode will set the SCSI_CFG1 register using this value
7580 * after it is started below.
7582 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
7585 * Set MEM_CFG Microcode Default Value
7587 * The microcode will set the MEM_CFG register using this value
7588 * after it is started below.
7590 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
7593 * ASC-38C0800 has 16KB internal memory.
7595 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
7596 BIOS_EN | RAM_SZ_16KB);
7599 * Set SEL_MASK Microcode Default Value
7601 * The microcode will set the SEL_MASK register using this value
7602 * after it is started below.
7604 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
7605 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
7607 AdvBuildCarrierFreelist(asc_dvc);
7610 * Set-up the Host->RISC Initiator Command Queue (ICQ).
7613 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
7614 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
7617 asc_dvc->carr_freelist = (ADV_CARR_T *)
7618 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
7621 * The first command issued will be placed in the stopper carrier.
7623 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
7626 * Set RISC ICQ physical address start value.
7627 * carr_pa is LE, must be native before write
7629 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
7632 * Set-up the RISC->Host Initiator Response Queue (IRQ).
7634 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
7635 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
7638 asc_dvc->carr_freelist = (ADV_CARR_T *)
7639 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
7642 * The first command completed by the RISC will be placed in
7645 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
7646 * completed the RISC will set the ASC_RQ_STOPPER bit.
7648 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
7651 * Set RISC IRQ physical address start value.
7653 * carr_pa is LE, must be native before write *
7655 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
7656 asc_dvc->carr_pending_cnt = 0;
7658 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
7659 (ADV_INTR_ENABLE_HOST_INTR |
7660 ADV_INTR_ENABLE_GLOBAL_INTR));
7662 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
7663 AdvWriteWordRegister(iop_base, IOPW_PC, word);
7665 /* finally, finally, gentlemen, start your engine */
7666 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
7669 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
7670 * Resets should be performed. The RISC has to be running
7671 * to issue a SCSI Bus Reset.
7673 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
7675 * If the BIOS Signature is present in memory, restore the
7676 * BIOS Handshake Configuration Table and do not perform
7679 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
7682 * Restore per TID negotiated values.
7684 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
7685 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
7686 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
7688 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
7689 AdvWriteByteLram(iop_base,
7690 ASC_MC_NUMBER_OF_MAX_CMD + tid,
7694 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
7695 warn_code = ASC_WARN_BUSRESET_ERROR;
7704 * Initialize the ASC-38C1600.
7706 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
7708 * For a non-fatal error return a warning code. If there are no warnings
7709 * then 0 is returned.
7711 * Needed after initialization for error recovery.
7713 static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc)
7715 AdvPortAddr iop_base;
7725 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
7726 ushort wdtr_able, sdtr_able, ppr_able, tagqng_able;
7727 uchar max_cmd[ASC_MAX_TID + 1];
7729 /* If there is already an error, don't continue. */
7730 if (asc_dvc->err_code != 0) {
7735 * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600.
7737 if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
7738 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
7743 iop_base = asc_dvc->iop_base;
7746 * Save the RISC memory BIOS region before writing the microcode.
7747 * The BIOS may already be loaded and using its RISC LRAM region
7748 * so its region must be saved and restored.
7750 * Note: This code makes the assumption, which is currently true,
7751 * that a chip reset does not clear RISC LRAM.
7753 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
7754 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
7759 * Save current per TID negotiated values.
7761 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
7762 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
7763 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
7764 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
7765 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
7766 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
7771 * RAM BIST (Built-In Self Test)
7773 * Address : I/O base + offset 0x38h register (byte).
7774 * Function: Bit 7-6(RW) : RAM mode
7775 * Normal Mode : 0x00
7776 * Pre-test Mode : 0x40
7777 * RAM Test Mode : 0x80
7779 * Bit 4(RO) : Done bit
7780 * Bit 3-0(RO) : Status
7782 * Int_RAM Error : 0x04
7787 * Note: RAM BIST code should be put right here, before loading the
7788 * microcode and after saving the RISC memory BIOS region.
7794 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
7795 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
7796 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
7797 * to NORMAL_MODE, return an error too.
7799 for (i = 0; i < 2; i++) {
7800 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
7801 mdelay(10); /* Wait for 10ms before reading back. */
7802 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
7803 if ((byte & RAM_TEST_DONE) == 0
7804 || (byte & 0x0F) != PRE_TEST_VALUE) {
7805 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
7809 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
7810 mdelay(10); /* Wait for 10ms before reading back. */
7811 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
7813 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
7819 * LRAM Test - It takes about 1.5 ms to run through the test.
7821 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
7822 * If Done bit not set or Status not 0, save register byte, set the
7823 * err_code, and return an error.
7825 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
7826 mdelay(10); /* Wait for 10ms before checking status. */
7828 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
7829 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
7830 /* Get here if Done bit not set or Status not 0. */
7831 asc_dvc->bist_err_code = byte; /* for BIOS display message */
7832 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
7836 /* We need to reset back to normal mode after LRAM test passes. */
7837 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
7839 asc_dvc->err_code = AdvLoadMicrocode(iop_base, _adv_asc38C1600_buf,
7840 _adv_asc38C1600_size, ADV_38C1600_MEMSIZE,
7841 _adv_asc38C1600_chksum);
7842 if (asc_dvc->err_code)
7846 * Restore the RISC memory BIOS region.
7848 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
7849 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
7854 * Calculate and write the microcode code checksum to the microcode
7855 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
7857 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
7858 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
7860 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
7861 for (word = begin_addr; word < end_addr; word += 2) {
7862 code_sum += AdvReadWordAutoIncLram(iop_base);
7864 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
7867 * Read microcode version and date.
7869 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
7870 asc_dvc->cfg->mcode_date);
7871 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
7872 asc_dvc->cfg->mcode_version);
7875 * Set the chip type to indicate the ASC38C1600.
7877 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600);
7880 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
7881 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
7882 * cable detection and then we are able to read C_DET[3:0].
7884 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
7885 * Microcode Default Value' section below.
7887 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
7888 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
7889 scsi_cfg1 | DIS_TERM_DRV);
7892 * If the PCI Configuration Command Register "Parity Error Response
7893 * Control" Bit was clear (0), then set the microcode variable
7894 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
7895 * to ignore DMA parity errors.
7897 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
7898 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7899 word |= CONTROL_FLAG_IGNORE_PERR;
7900 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7904 * If the BIOS control flag AIPP (Asynchronous Information
7905 * Phase Protection) disable bit is not set, then set the firmware
7906 * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable
7907 * AIPP checking and encoding.
7909 if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) {
7910 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7911 word |= CONTROL_FLAG_ENABLE_AIPP;
7912 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7916 * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4],
7917 * and START_CTL_TH [3:2].
7919 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
7920 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
7923 * Microcode operating variables for WDTR, SDTR, and command tag
7924 * queuing will be set in slave_configure() based on what a
7925 * device reports it is capable of in Inquiry byte 7.
7927 * If SCSI Bus Resets have been disabled, then directly set
7928 * SDTR and WDTR from the EEPROM configuration. This will allow
7929 * the BIOS and warm boot to work without a SCSI bus hang on
7930 * the Inquiry caused by host and target mismatched DTR values.
7931 * Without the SCSI Bus Reset, before an Inquiry a device can't
7932 * be assumed to be in Asynchronous, Narrow mode.
7934 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
7935 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
7936 asc_dvc->wdtr_able);
7937 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
7938 asc_dvc->sdtr_able);
7942 * Set microcode operating variables for DISC and SDTR_SPEED1,
7943 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
7944 * configuration values.
7946 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
7947 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
7948 * without determining here whether the device supports SDTR.
7950 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
7951 asc_dvc->cfg->disc_enable);
7952 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
7953 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
7954 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
7955 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
7958 * Set SCSI_CFG0 Microcode Default Value.
7960 * The microcode will set the SCSI_CFG0 register using this value
7961 * after it is started below.
7963 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
7964 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
7965 asc_dvc->chip_scsi_id);
7968 * Calculate SCSI_CFG1 Microcode Default Value.
7970 * The microcode will set the SCSI_CFG1 register using this value
7971 * after it is started below.
7973 * Each ASC-38C1600 function has only two cable detect bits.
7974 * The bus mode override bits are in IOPB_SOFT_OVER_WR.
7976 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
7979 * If the cable is reversed all of the SCSI_CTRL register signals
7980 * will be set. Check for and return an error if this condition is
7983 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
7984 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
7989 * Each ASC-38C1600 function has two connectors. Only an HVD device
7990 * can not be connected to either connector. An LVD device or SE device
7991 * may be connected to either connecor. If an SE device is connected,
7992 * then at most Ultra speed (20 Mhz) can be used on both connectors.
7994 * If an HVD device is attached, return an error.
7996 if (scsi_cfg1 & HVD) {
7997 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
8002 * Each function in the ASC-38C1600 uses only the SE cable detect and
8003 * termination because there are two connectors for each function. Each
8004 * function may use either LVD or SE mode. Corresponding the SE automatic
8005 * termination control EEPROM bits are used for each function. Each
8006 * function has its own EEPROM. If SE automatic control is enabled for
8007 * the function, then set the termination value based on a table listed
8010 * If manual termination is specified in the EEPROM for the function,
8011 * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is
8012 * ready to be 'ored' into SCSI_CFG1.
8014 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
8015 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
8016 /* SE automatic termination control is enabled. */
8017 switch (scsi_cfg1 & C_DET_SE) {
8018 /* TERM_SE_HI: on, TERM_SE_LO: on */
8022 asc_dvc->cfg->termination |= TERM_SE;
8026 if (PCI_FUNC(pdev->devfn) == 0) {
8027 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
8029 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
8030 asc_dvc->cfg->termination |= TERM_SE_HI;
8037 * Clear any set TERM_SE bits.
8039 scsi_cfg1 &= ~TERM_SE;
8042 * Invert the TERM_SE bits and then set 'scsi_cfg1'.
8044 scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE);
8047 * Clear Big Endian and Terminator Polarity bits and set possibly
8048 * modified termination control bits in the Microcode SCSI_CFG1
8051 * Big Endian bit is not used even on big endian machines.
8053 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL);
8056 * Set SCSI_CFG1 Microcode Default Value
8058 * Set possibly modified termination control bits in the Microcode
8059 * SCSI_CFG1 Register Value.
8061 * The microcode will set the SCSI_CFG1 register using this value
8062 * after it is started below.
8064 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
8067 * Set MEM_CFG Microcode Default Value
8069 * The microcode will set the MEM_CFG register using this value
8070 * after it is started below.
8072 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
8075 * ASC-38C1600 has 32KB internal memory.
8077 * XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come
8078 * out a special 16K Adv Library and Microcode version. After the issue
8079 * resolved, we should turn back to the 32K support. Both a_condor.h and
8080 * mcode.sas files also need to be updated.
8082 * AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
8083 * BIOS_EN | RAM_SZ_32KB);
8085 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
8086 BIOS_EN | RAM_SZ_16KB);
8089 * Set SEL_MASK Microcode Default Value
8091 * The microcode will set the SEL_MASK register using this value
8092 * after it is started below.
8094 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
8095 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
8097 AdvBuildCarrierFreelist(asc_dvc);
8100 * Set-up the Host->RISC Initiator Command Queue (ICQ).
8102 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
8103 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
8106 asc_dvc->carr_freelist = (ADV_CARR_T *)
8107 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
8110 * The first command issued will be placed in the stopper carrier.
8112 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
8115 * Set RISC ICQ physical address start value. Initialize the
8116 * COMMA register to the same value otherwise the RISC will
8117 * prematurely detect a command is available.
8119 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
8120 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
8121 le32_to_cpu(asc_dvc->icq_sp->carr_pa));
8124 * Set-up the RISC->Host Initiator Response Queue (IRQ).
8126 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
8127 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
8130 asc_dvc->carr_freelist = (ADV_CARR_T *)
8131 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
8134 * The first command completed by the RISC will be placed in
8137 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
8138 * completed the RISC will set the ASC_RQ_STOPPER bit.
8140 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
8143 * Set RISC IRQ physical address start value.
8145 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
8146 asc_dvc->carr_pending_cnt = 0;
8148 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
8149 (ADV_INTR_ENABLE_HOST_INTR |
8150 ADV_INTR_ENABLE_GLOBAL_INTR));
8151 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
8152 AdvWriteWordRegister(iop_base, IOPW_PC, word);
8154 /* finally, finally, gentlemen, start your engine */
8155 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
8158 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
8159 * Resets should be performed. The RISC has to be running
8160 * to issue a SCSI Bus Reset.
8162 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
8164 * If the BIOS Signature is present in memory, restore the
8165 * per TID microcode operating variables.
8167 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
8170 * Restore per TID negotiated values.
8172 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
8173 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
8174 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
8175 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
8177 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
8178 AdvWriteByteLram(iop_base,
8179 ASC_MC_NUMBER_OF_MAX_CMD + tid,
8183 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
8184 warn_code = ASC_WARN_BUSRESET_ERROR;
8193 * Reset chip and SCSI Bus.
8196 * ADV_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful.
8197 * ADV_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure.
8199 static int AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc)
8202 ushort wdtr_able, sdtr_able, tagqng_able;
8203 ushort ppr_able = 0;
8204 uchar tid, max_cmd[ADV_MAX_TID + 1];
8205 AdvPortAddr iop_base;
8208 iop_base = asc_dvc->iop_base;
8211 * Save current per TID negotiated values.
8213 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
8214 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
8215 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
8216 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
8218 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
8219 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
8220 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
8225 * Force the AdvInitAsc3550/38C0800Driver() function to
8226 * perform a SCSI Bus Reset by clearing the BIOS signature word.
8227 * The initialization functions assumes a SCSI Bus Reset is not
8228 * needed if the BIOS signature word is present.
8230 AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
8231 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0);
8234 * Stop chip and reset it.
8236 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP);
8237 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET);
8239 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
8240 ADV_CTRL_REG_CMD_WR_IO_REG);
8243 * Reset Adv Library error code, if any, and try
8244 * re-initializing the chip.
8246 asc_dvc->err_code = 0;
8247 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
8248 status = AdvInitAsc38C1600Driver(asc_dvc);
8249 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
8250 status = AdvInitAsc38C0800Driver(asc_dvc);
8252 status = AdvInitAsc3550Driver(asc_dvc);
8255 /* Translate initialization return value to status value. */
8263 * Restore the BIOS signature word.
8265 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
8268 * Restore per TID negotiated values.
8270 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
8271 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
8272 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
8273 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
8275 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
8276 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
8277 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
8285 * adv_async_callback() - Adv Library asynchronous event callback function.
8287 static void adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code)
8290 case ADV_ASYNC_SCSI_BUS_RESET_DET:
8292 * The firmware detected a SCSI Bus reset.
8295 "adv_async_callback: ADV_ASYNC_SCSI_BUS_RESET_DET\n");
8298 case ADV_ASYNC_RDMA_FAILURE:
8300 * Handle RDMA failure by resetting the SCSI Bus and
8301 * possibly the chip if it is unresponsive. Log the error
8302 * with a unique code.
8304 ASC_DBG(0, "adv_async_callback: ADV_ASYNC_RDMA_FAILURE\n");
8305 AdvResetChipAndSB(adv_dvc_varp);
8308 case ADV_HOST_SCSI_BUS_RESET:
8310 * Host generated SCSI bus reset occurred.
8312 ASC_DBG(0, "adv_async_callback: ADV_HOST_SCSI_BUS_RESET\n");
8316 ASC_DBG1(0, "DvcAsyncCallBack: unknown code 0x%x\n", code);
8322 * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR().
8324 * Callback function for the Wide SCSI Adv Library.
8326 static void adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp)
8328 struct asc_board *boardp;
8330 adv_sgblk_t *sgblkp;
8331 struct scsi_cmnd *scp;
8332 struct Scsi_Host *shost;
8335 ASC_DBG2(1, "adv_isr_callback: adv_dvc_varp 0x%lx, scsiqp 0x%lx\n",
8336 (ulong)adv_dvc_varp, (ulong)scsiqp);
8337 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
8340 * Get the adv_req_t structure for the command that has been
8341 * completed. The adv_req_t structure actually contains the
8342 * completed ADV_SCSI_REQ_Q structure.
8344 reqp = (adv_req_t *)ADV_U32_TO_VADDR(scsiqp->srb_ptr);
8345 ASC_DBG1(1, "adv_isr_callback: reqp 0x%lx\n", (ulong)reqp);
8347 ASC_PRINT("adv_isr_callback: reqp is NULL\n");
8352 * Get the struct scsi_cmnd structure and Scsi_Host structure for the
8353 * command that has been completed.
8355 * Note: The adv_req_t request structure and adv_sgblk_t structure,
8356 * if any, are dropped, because a board structure pointer can not be
8360 ASC_DBG1(1, "adv_isr_callback: scp 0x%lx\n", (ulong)scp);
8363 ("adv_isr_callback: scp is NULL; adv_req_t dropped.\n");
8366 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
8368 shost = scp->device->host;
8369 ASC_STATS(shost, callback);
8370 ASC_DBG1(1, "adv_isr_callback: shost 0x%lx\n", (ulong)shost);
8372 boardp = shost_priv(shost);
8373 BUG_ON(adv_dvc_varp != &boardp->dvc_var.adv_dvc_var);
8376 * 'done_status' contains the command's ending status.
8378 switch (scsiqp->done_status) {
8380 ASC_DBG(2, "adv_isr_callback: QD_NO_ERROR\n");
8384 * Check for an underrun condition.
8386 * If there was no error and an underrun condition, then
8387 * then return the number of underrun bytes.
8389 resid_cnt = le32_to_cpu(scsiqp->data_cnt);
8390 if (scp->request_bufflen != 0 && resid_cnt != 0 &&
8391 resid_cnt <= scp->request_bufflen) {
8393 "adv_isr_callback: underrun condition %lu bytes\n",
8395 scp->resid = resid_cnt;
8400 ASC_DBG(2, "adv_isr_callback: QD_WITH_ERROR\n");
8401 switch (scsiqp->host_status) {
8402 case QHSTA_NO_ERROR:
8403 if (scsiqp->scsi_status == SAM_STAT_CHECK_CONDITION) {
8405 "adv_isr_callback: SAM_STAT_CHECK_CONDITION\n");
8406 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
8407 sizeof(scp->sense_buffer));
8409 * Note: The 'status_byte()' macro used by
8410 * target drivers defined in scsi.h shifts the
8411 * status byte returned by host drivers right
8412 * by 1 bit. This is why target drivers also
8413 * use right shifted status byte definitions.
8414 * For instance target drivers use
8415 * CHECK_CONDITION, defined to 0x1, instead of
8416 * the SCSI defined check condition value of
8417 * 0x2. Host drivers are supposed to return
8418 * the status byte as it is defined by SCSI.
8420 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
8421 STATUS_BYTE(scsiqp->scsi_status);
8423 scp->result = STATUS_BYTE(scsiqp->scsi_status);
8428 /* Some other QHSTA error occurred. */
8429 ASC_DBG1(1, "adv_isr_callback: host_status 0x%x\n",
8430 scsiqp->host_status);
8431 scp->result = HOST_BYTE(DID_BAD_TARGET);
8436 case QD_ABORTED_BY_HOST:
8437 ASC_DBG(1, "adv_isr_callback: QD_ABORTED_BY_HOST\n");
8439 HOST_BYTE(DID_ABORT) | STATUS_BYTE(scsiqp->scsi_status);
8443 ASC_DBG1(1, "adv_isr_callback: done_status 0x%x\n",
8444 scsiqp->done_status);
8446 HOST_BYTE(DID_ERROR) | STATUS_BYTE(scsiqp->scsi_status);
8451 * If the 'init_tidmask' bit isn't already set for the target and the
8452 * current request finished normally, then set the bit for the target
8453 * to indicate that a device is present.
8455 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
8456 scsiqp->done_status == QD_NO_ERROR &&
8457 scsiqp->host_status == QHSTA_NO_ERROR) {
8458 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
8464 * Free all 'adv_sgblk_t' structures allocated for the request.
8466 while ((sgblkp = reqp->sgblkp) != NULL) {
8467 /* Remove 'sgblkp' from the request list. */
8468 reqp->sgblkp = sgblkp->next_sgblkp;
8470 /* Add 'sgblkp' to the board free list. */
8471 sgblkp->next_sgblkp = boardp->adv_sgblkp;
8472 boardp->adv_sgblkp = sgblkp;
8476 * Free the adv_req_t structure used with the command by adding
8477 * it back to the board free list.
8479 reqp->next_reqp = boardp->adv_reqp;
8480 boardp->adv_reqp = reqp;
8482 ASC_DBG(1, "adv_isr_callback: done\n");
8488 * Adv Library Interrupt Service Routine
8490 * This function is called by a driver's interrupt service routine.
8491 * The function disables and re-enables interrupts.
8493 * When a microcode idle command is completed, the ADV_DVC_VAR
8494 * 'idle_cmd_done' field is set to ADV_TRUE.
8496 * Note: AdvISR() can be called when interrupts are disabled or even
8497 * when there is no hardware interrupt condition present. It will
8498 * always check for completed idle commands and microcode requests.
8499 * This is an important feature that shouldn't be changed because it
8500 * allows commands to be completed from polling mode loops.
8503 * ADV_TRUE(1) - interrupt was pending
8504 * ADV_FALSE(0) - no interrupt was pending
8506 static int AdvISR(ADV_DVC_VAR *asc_dvc)
8508 AdvPortAddr iop_base;
8511 ADV_CARR_T *free_carrp;
8512 ADV_VADDR irq_next_vpa;
8513 ADV_SCSI_REQ_Q *scsiq;
8515 iop_base = asc_dvc->iop_base;
8517 /* Reading the register clears the interrupt. */
8518 int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG);
8520 if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB |
8521 ADV_INTR_STATUS_INTRC)) == 0) {
8526 * Notify the driver of an asynchronous microcode condition by
8527 * calling the adv_async_callback function. The function
8528 * is passed the microcode ASC_MC_INTRB_CODE byte value.
8530 if (int_stat & ADV_INTR_STATUS_INTRB) {
8533 AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code);
8535 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
8536 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
8537 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE &&
8538 asc_dvc->carr_pending_cnt != 0) {
8539 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
8541 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
8542 AdvWriteByteRegister(iop_base,
8549 adv_async_callback(asc_dvc, intrb_code);
8553 * Check if the IRQ stopper carrier contains a completed request.
8555 while (((irq_next_vpa =
8556 le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ASC_RQ_DONE) != 0) {
8558 * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure.
8559 * The RISC will have set 'areq_vpa' to a virtual address.
8561 * The firmware will have copied the ASC_SCSI_REQ_Q.scsiq_ptr
8562 * field to the carrier ADV_CARR_T.areq_vpa field. The conversion
8563 * below complements the conversion of ASC_SCSI_REQ_Q.scsiq_ptr'
8564 * in AdvExeScsiQueue().
8566 scsiq = (ADV_SCSI_REQ_Q *)
8567 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->areq_vpa));
8570 * Request finished with good status and the queue was not
8571 * DMAed to host memory by the firmware. Set all status fields
8572 * to indicate good status.
8574 if ((irq_next_vpa & ASC_RQ_GOOD) != 0) {
8575 scsiq->done_status = QD_NO_ERROR;
8576 scsiq->host_status = scsiq->scsi_status = 0;
8577 scsiq->data_cnt = 0L;
8581 * Advance the stopper pointer to the next carrier
8582 * ignoring the lower four bits. Free the previous
8585 free_carrp = asc_dvc->irq_sp;
8586 asc_dvc->irq_sp = (ADV_CARR_T *)
8587 ADV_U32_TO_VADDR(ASC_GET_CARRP(irq_next_vpa));
8589 free_carrp->next_vpa =
8590 cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
8591 asc_dvc->carr_freelist = free_carrp;
8592 asc_dvc->carr_pending_cnt--;
8594 target_bit = ADV_TID_TO_TIDMASK(scsiq->target_id);
8597 * Clear request microcode control flag.
8602 * Notify the driver of the completed request by passing
8603 * the ADV_SCSI_REQ_Q pointer to its callback function.
8605 scsiq->a_flag |= ADV_SCSIQ_DONE;
8606 adv_isr_callback(asc_dvc, scsiq);
8608 * Note: After the driver callback function is called, 'scsiq'
8609 * can no longer be referenced.
8611 * Fall through and continue processing other completed
8618 static int AscSetLibErrorCode(ASC_DVC_VAR *asc_dvc, ushort err_code)
8620 if (asc_dvc->err_code == 0) {
8621 asc_dvc->err_code = err_code;
8622 AscWriteLramWord(asc_dvc->iop_base, ASCV_ASCDVC_ERR_CODE_W,
8628 static void AscAckInterrupt(PortAddr iop_base)
8636 risc_flag = AscReadLramByte(iop_base, ASCV_RISC_FLAG_B);
8637 if (loop++ > 0x7FFF) {
8640 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0);
8642 AscReadLramByte(iop_base,
8643 ASCV_HOST_FLAG_B) & (~ASC_HOST_FLAG_ACK_INT);
8644 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
8645 (uchar)(host_flag | ASC_HOST_FLAG_ACK_INT));
8646 AscSetChipStatus(iop_base, CIW_INT_ACK);
8648 while (AscGetChipStatus(iop_base) & CSW_INT_PENDING) {
8649 AscSetChipStatus(iop_base, CIW_INT_ACK);
8654 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
8658 static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *asc_dvc, uchar syn_time)
8660 uchar *period_table;
8665 period_table = asc_dvc->sdtr_period_tbl;
8666 max_index = (int)asc_dvc->max_sdtr_index;
8667 min_index = (int)asc_dvc->host_init_sdtr_index;
8668 if ((syn_time <= period_table[max_index])) {
8669 for (i = min_index; i < (max_index - 1); i++) {
8670 if (syn_time <= period_table[i]) {
8674 return (uchar)max_index;
8676 return (uchar)(max_index + 1);
8681 AscMsgOutSDTR(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar sdtr_offset)
8684 uchar sdtr_period_index;
8687 iop_base = asc_dvc->iop_base;
8688 sdtr_buf.msg_type = EXTENDED_MESSAGE;
8689 sdtr_buf.msg_len = MS_SDTR_LEN;
8690 sdtr_buf.msg_req = EXTENDED_SDTR;
8691 sdtr_buf.xfer_period = sdtr_period;
8692 sdtr_offset &= ASC_SYN_MAX_OFFSET;
8693 sdtr_buf.req_ack_offset = sdtr_offset;
8694 sdtr_period_index = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
8695 if (sdtr_period_index <= asc_dvc->max_sdtr_index) {
8696 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
8698 sizeof(EXT_MSG) >> 1);
8699 return ((sdtr_period_index << 4) | sdtr_offset);
8701 sdtr_buf.req_ack_offset = 0;
8702 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
8704 sizeof(EXT_MSG) >> 1);
8710 AscCalSDTRData(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar syn_offset)
8713 uchar sdtr_period_ix;
8715 sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
8716 if (sdtr_period_ix > asc_dvc->max_sdtr_index) {
8719 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
8723 static int AscSetChipSynRegAtID(PortAddr iop_base, uchar id, uchar sdtr_data)
8725 ASC_SCSI_BIT_ID_TYPE org_id;
8729 AscSetBank(iop_base, 1);
8730 org_id = AscReadChipDvcID(iop_base);
8731 for (i = 0; i <= ASC_MAX_TID; i++) {
8732 if (org_id == (0x01 << i))
8735 org_id = (ASC_SCSI_BIT_ID_TYPE) i;
8736 AscWriteChipDvcID(iop_base, id);
8737 if (AscReadChipDvcID(iop_base) == (0x01 << id)) {
8738 AscSetBank(iop_base, 0);
8739 AscSetChipSyn(iop_base, sdtr_data);
8740 if (AscGetChipSyn(iop_base) != sdtr_data) {
8746 AscSetBank(iop_base, 1);
8747 AscWriteChipDvcID(iop_base, org_id);
8748 AscSetBank(iop_base, 0);
8752 static void AscSetChipSDTR(PortAddr iop_base, uchar sdtr_data, uchar tid_no)
8754 AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
8755 AscPutMCodeSDTRDoneAtID(iop_base, tid_no, sdtr_data);
8758 static int AscIsrChipHalted(ASC_DVC_VAR *asc_dvc)
8764 ushort int_halt_code;
8765 ASC_SCSI_BIT_ID_TYPE scsi_busy;
8766 ASC_SCSI_BIT_ID_TYPE target_id;
8773 uchar q_cntl, tid_no;
8777 struct asc_board *boardp;
8779 BUG_ON(!asc_dvc->drv_ptr);
8780 boardp = asc_dvc->drv_ptr;
8782 iop_base = asc_dvc->iop_base;
8783 int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W);
8785 halt_qp = AscReadLramByte(iop_base, ASCV_CURCDB_B);
8786 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp);
8787 target_ix = AscReadLramByte(iop_base,
8788 (ushort)(halt_q_addr +
8789 (ushort)ASC_SCSIQ_B_TARGET_IX));
8790 q_cntl = AscReadLramByte(iop_base,
8791 (ushort)(halt_q_addr + (ushort)ASC_SCSIQ_B_CNTL));
8792 tid_no = ASC_TIX_TO_TID(target_ix);
8793 target_id = (uchar)ASC_TID_TO_TARGET_ID(tid_no);
8794 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
8795 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB;
8799 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) {
8800 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
8801 AscSetChipSDTR(iop_base, 0, tid_no);
8802 boardp->sdtr_data[tid_no] = 0;
8804 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8806 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) {
8807 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
8808 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
8809 boardp->sdtr_data[tid_no] = asyn_sdtr;
8811 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8813 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) {
8814 AscMemWordCopyPtrFromLram(iop_base,
8817 sizeof(EXT_MSG) >> 1);
8819 if (ext_msg.msg_type == EXTENDED_MESSAGE &&
8820 ext_msg.msg_req == EXTENDED_SDTR &&
8821 ext_msg.msg_len == MS_SDTR_LEN) {
8823 if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) {
8825 sdtr_accept = FALSE;
8826 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
8828 if ((ext_msg.xfer_period <
8829 asc_dvc->sdtr_period_tbl[asc_dvc->
8830 host_init_sdtr_index])
8831 || (ext_msg.xfer_period >
8832 asc_dvc->sdtr_period_tbl[asc_dvc->
8834 sdtr_accept = FALSE;
8835 ext_msg.xfer_period =
8836 asc_dvc->sdtr_period_tbl[asc_dvc->
8837 host_init_sdtr_index];
8841 AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
8842 ext_msg.req_ack_offset);
8843 if ((sdtr_data == 0xFF)) {
8845 q_cntl |= QC_MSG_OUT;
8846 asc_dvc->init_sdtr &= ~target_id;
8847 asc_dvc->sdtr_done &= ~target_id;
8848 AscSetChipSDTR(iop_base, asyn_sdtr,
8850 boardp->sdtr_data[tid_no] = asyn_sdtr;
8853 if (ext_msg.req_ack_offset == 0) {
8855 q_cntl &= ~QC_MSG_OUT;
8856 asc_dvc->init_sdtr &= ~target_id;
8857 asc_dvc->sdtr_done &= ~target_id;
8858 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
8860 if (sdtr_accept && (q_cntl & QC_MSG_OUT)) {
8862 q_cntl &= ~QC_MSG_OUT;
8863 asc_dvc->sdtr_done |= target_id;
8864 asc_dvc->init_sdtr |= target_id;
8865 asc_dvc->pci_fix_asyn_xfer &=
8868 AscCalSDTRData(asc_dvc,
8869 ext_msg.xfer_period,
8872 AscSetChipSDTR(iop_base, sdtr_data,
8874 boardp->sdtr_data[tid_no] = sdtr_data;
8877 q_cntl |= QC_MSG_OUT;
8878 AscMsgOutSDTR(asc_dvc,
8879 ext_msg.xfer_period,
8880 ext_msg.req_ack_offset);
8881 asc_dvc->pci_fix_asyn_xfer &=
8884 AscCalSDTRData(asc_dvc,
8885 ext_msg.xfer_period,
8888 AscSetChipSDTR(iop_base, sdtr_data,
8890 boardp->sdtr_data[tid_no] = sdtr_data;
8891 asc_dvc->sdtr_done |= target_id;
8892 asc_dvc->init_sdtr |= target_id;
8896 AscWriteLramByte(iop_base,
8897 (ushort)(halt_q_addr +
8898 (ushort)ASC_SCSIQ_B_CNTL),
8900 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8902 } else if (ext_msg.msg_type == EXTENDED_MESSAGE &&
8903 ext_msg.msg_req == EXTENDED_WDTR &&
8904 ext_msg.msg_len == MS_WDTR_LEN) {
8906 ext_msg.wdtr_width = 0;
8907 AscMemWordCopyPtrToLram(iop_base,
8910 sizeof(EXT_MSG) >> 1);
8911 q_cntl |= QC_MSG_OUT;
8912 AscWriteLramByte(iop_base,
8913 (ushort)(halt_q_addr +
8914 (ushort)ASC_SCSIQ_B_CNTL),
8916 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8920 ext_msg.msg_type = MESSAGE_REJECT;
8921 AscMemWordCopyPtrToLram(iop_base,
8924 sizeof(EXT_MSG) >> 1);
8925 q_cntl |= QC_MSG_OUT;
8926 AscWriteLramByte(iop_base,
8927 (ushort)(halt_q_addr +
8928 (ushort)ASC_SCSIQ_B_CNTL),
8930 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8933 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) {
8935 q_cntl |= QC_REQ_SENSE;
8937 if ((asc_dvc->init_sdtr & target_id) != 0) {
8939 asc_dvc->sdtr_done &= ~target_id;
8941 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
8942 q_cntl |= QC_MSG_OUT;
8943 AscMsgOutSDTR(asc_dvc,
8945 sdtr_period_tbl[(sdtr_data >> 4) &
8949 (uchar)(sdtr_data & (uchar)
8950 ASC_SYN_MAX_OFFSET));
8953 AscWriteLramByte(iop_base,
8954 (ushort)(halt_q_addr +
8955 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
8957 tag_code = AscReadLramByte(iop_base,
8958 (ushort)(halt_q_addr + (ushort)
8959 ASC_SCSIQ_B_TAG_CODE));
8961 if ((asc_dvc->pci_fix_asyn_xfer & target_id)
8962 && !(asc_dvc->pci_fix_asyn_xfer_always & target_id)
8965 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT
8966 | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX);
8969 AscWriteLramByte(iop_base,
8970 (ushort)(halt_q_addr +
8971 (ushort)ASC_SCSIQ_B_TAG_CODE),
8974 q_status = AscReadLramByte(iop_base,
8975 (ushort)(halt_q_addr + (ushort)
8976 ASC_SCSIQ_B_STATUS));
8977 q_status |= (QS_READY | QS_BUSY);
8978 AscWriteLramByte(iop_base,
8979 (ushort)(halt_q_addr +
8980 (ushort)ASC_SCSIQ_B_STATUS),
8983 scsi_busy = AscReadLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B);
8984 scsi_busy &= ~target_id;
8985 AscWriteLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B, scsi_busy);
8987 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8989 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) {
8991 AscMemWordCopyPtrFromLram(iop_base,
8994 sizeof(EXT_MSG) >> 1);
8996 if ((out_msg.msg_type == EXTENDED_MESSAGE) &&
8997 (out_msg.msg_len == MS_SDTR_LEN) &&
8998 (out_msg.msg_req == EXTENDED_SDTR)) {
9000 asc_dvc->init_sdtr &= ~target_id;
9001 asc_dvc->sdtr_done &= ~target_id;
9002 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
9003 boardp->sdtr_data[tid_no] = asyn_sdtr;
9005 q_cntl &= ~QC_MSG_OUT;
9006 AscWriteLramByte(iop_base,
9007 (ushort)(halt_q_addr +
9008 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
9009 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
9011 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) {
9013 scsi_status = AscReadLramByte(iop_base,
9014 (ushort)((ushort)halt_q_addr +
9016 ASC_SCSIQ_SCSI_STATUS));
9018 AscReadLramByte(iop_base,
9019 (ushort)((ushort)ASC_QADR_BEG +
9020 (ushort)target_ix));
9021 if ((cur_dvc_qng > 0) && (asc_dvc->cur_dvc_qng[tid_no] > 0)) {
9023 scsi_busy = AscReadLramByte(iop_base,
9024 (ushort)ASCV_SCSIBUSY_B);
9025 scsi_busy |= target_id;
9026 AscWriteLramByte(iop_base,
9027 (ushort)ASCV_SCSIBUSY_B, scsi_busy);
9028 asc_dvc->queue_full_or_busy |= target_id;
9030 if (scsi_status == SAM_STAT_TASK_SET_FULL) {
9031 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) {
9033 asc_dvc->max_dvc_qng[tid_no] =
9036 AscWriteLramByte(iop_base,
9038 ASCV_MAX_DVC_QNG_BEG
9044 * Set the device queue depth to the
9045 * number of active requests when the
9046 * QUEUE FULL condition was encountered.
9048 boardp->queue_full |= target_id;
9049 boardp->queue_full_cnt[tid_no] =
9054 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
9057 #if CC_VERY_LONG_SG_LIST
9058 else if (int_halt_code == ASC_HALT_HOST_COPY_SG_LIST_TO_RISC) {
9062 uchar first_sg_wk_q_no;
9063 ASC_SCSI_Q *scsiq; /* Ptr to driver request. */
9064 ASC_SG_HEAD *sg_head; /* Ptr to driver SG request. */
9065 ASC_SG_LIST_Q scsi_sg_q; /* Structure written to queue. */
9066 ushort sg_list_dwords;
9067 ushort sg_entry_cnt;
9071 q_no = AscReadLramByte(iop_base, (ushort)ASCV_REQ_SG_LIST_QP);
9072 if (q_no == ASC_QLINK_END)
9075 q_addr = ASC_QNO_TO_QADDR(q_no);
9078 * Convert the request's SRB pointer to a host ASC_SCSI_REQ
9079 * structure pointer using a macro provided by the driver.
9080 * The ASC_SCSI_REQ pointer provides a pointer to the
9081 * host ASC_SG_HEAD structure.
9083 /* Read request's SRB pointer. */
9084 scsiq = (ASC_SCSI_Q *)
9085 ASC_SRB2SCSIQ(ASC_U32_TO_VADDR(AscReadLramDWord(iop_base,
9088 ASC_SCSIQ_D_SRBPTR))));
9091 * Get request's first and working SG queue.
9093 sg_wk_q_no = AscReadLramByte(iop_base,
9095 ASC_SCSIQ_B_SG_WK_QP));
9097 first_sg_wk_q_no = AscReadLramByte(iop_base,
9099 ASC_SCSIQ_B_FIRST_SG_WK_QP));
9102 * Reset request's working SG queue back to the
9105 AscWriteLramByte(iop_base,
9107 (ushort)ASC_SCSIQ_B_SG_WK_QP),
9110 sg_head = scsiq->sg_head;
9113 * Set sg_entry_cnt to the number of SG elements
9114 * that will be completed on this interrupt.
9116 * Note: The allocated SG queues contain ASC_MAX_SG_LIST - 1
9117 * SG elements. The data_cnt and data_addr fields which
9118 * add 1 to the SG element capacity are not used when
9119 * restarting SG handling after a halt.
9121 if (scsiq->remain_sg_entry_cnt > (ASC_MAX_SG_LIST - 1)) {
9122 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
9125 * Keep track of remaining number of SG elements that
9126 * will need to be handled on the next interrupt.
9128 scsiq->remain_sg_entry_cnt -= (ASC_MAX_SG_LIST - 1);
9130 sg_entry_cnt = scsiq->remain_sg_entry_cnt;
9131 scsiq->remain_sg_entry_cnt = 0;
9135 * Copy SG elements into the list of allocated SG queues.
9137 * Last index completed is saved in scsiq->next_sg_index.
9139 next_qp = first_sg_wk_q_no;
9140 q_addr = ASC_QNO_TO_QADDR(next_qp);
9141 scsi_sg_q.sg_head_qp = q_no;
9142 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
9143 for (i = 0; i < sg_head->queue_cnt; i++) {
9144 scsi_sg_q.seq_no = i + 1;
9145 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
9146 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
9147 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
9149 * After very first SG queue RISC FW uses next
9150 * SG queue first element then checks sg_list_cnt
9151 * against zero and then decrements, so set
9152 * sg_list_cnt 1 less than number of SG elements
9155 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1;
9156 scsi_sg_q.sg_cur_list_cnt =
9157 ASC_SG_LIST_PER_Q - 1;
9160 * This is the last SG queue in the list of
9161 * allocated SG queues. If there are more
9162 * SG elements than will fit in the allocated
9163 * queues, then set the QCSG_SG_XFER_MORE flag.
9165 if (scsiq->remain_sg_entry_cnt != 0) {
9166 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
9168 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
9170 /* equals sg_entry_cnt * 2 */
9171 sg_list_dwords = sg_entry_cnt << 1;
9172 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1;
9173 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1;
9177 scsi_sg_q.q_no = next_qp;
9178 AscMemWordCopyPtrToLram(iop_base,
9179 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
9180 (uchar *)&scsi_sg_q,
9181 sizeof(ASC_SG_LIST_Q) >> 1);
9183 AscMemDWordCopyPtrToLram(iop_base,
9184 q_addr + ASC_SGQ_LIST_BEG,
9186 sg_list[scsiq->next_sg_index],
9189 scsiq->next_sg_index += ASC_SG_LIST_PER_Q;
9192 * If the just completed SG queue contained the
9193 * last SG element, then no more SG queues need
9196 if (scsi_sg_q.cntl & QCSG_SG_XFER_END) {
9200 next_qp = AscReadLramByte(iop_base,
9203 q_addr = ASC_QNO_TO_QADDR(next_qp);
9207 * Clear the halt condition so the RISC will be restarted
9210 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
9213 #endif /* CC_VERY_LONG_SG_LIST */
9219 * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
9221 * Calling/Exit State:
9225 * Input an ASC_QDONE_INFO structure from the chip
9228 DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
9233 AscSetChipLramAddr(iop_base, s_addr);
9234 for (i = 0; i < 2 * words; i += 2) {
9238 word = inpw(iop_base + IOP_RAM_DATA);
9239 inbuf[i] = word & 0xff;
9240 inbuf[i + 1] = (word >> 8) & 0xff;
9242 ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf, 2 * words);
9246 _AscCopyLramScsiDoneQ(PortAddr iop_base,
9248 ASC_QDONE_INFO *scsiq, ASC_DCNT max_dma_count)
9253 DvcGetQinfo(iop_base,
9254 q_addr + ASC_SCSIQ_DONE_INFO_BEG,
9256 (sizeof(ASC_SCSIQ_2) + sizeof(ASC_SCSIQ_3)) / 2);
9258 _val = AscReadLramWord(iop_base,
9259 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS));
9260 scsiq->q_status = (uchar)_val;
9261 scsiq->q_no = (uchar)(_val >> 8);
9262 _val = AscReadLramWord(iop_base,
9263 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_CNTL));
9264 scsiq->cntl = (uchar)_val;
9265 sg_queue_cnt = (uchar)(_val >> 8);
9266 _val = AscReadLramWord(iop_base,
9268 (ushort)ASC_SCSIQ_B_SENSE_LEN));
9269 scsiq->sense_len = (uchar)_val;
9270 scsiq->extra_bytes = (uchar)(_val >> 8);
9273 * Read high word of remain bytes from alternate location.
9275 scsiq->remain_bytes = (((ADV_DCNT)AscReadLramWord(iop_base,
9278 ASC_SCSIQ_W_ALT_DC1)))
9281 * Read low word of remain bytes from original location.
9283 scsiq->remain_bytes += AscReadLramWord(iop_base,
9284 (ushort)(q_addr + (ushort)
9285 ASC_SCSIQ_DW_REMAIN_XFER_CNT));
9287 scsiq->remain_bytes &= max_dma_count;
9288 return sg_queue_cnt;
9292 * asc_isr_callback() - Second Level Interrupt Handler called by AscISR().
9294 * Interrupt callback function for the Narrow SCSI Asc Library.
9296 static void asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep)
9298 struct asc_board *boardp;
9299 struct scsi_cmnd *scp;
9300 struct Scsi_Host *shost;
9302 ASC_DBG2(1, "asc_isr_callback: asc_dvc_varp 0x%lx, qdonep 0x%lx\n",
9303 (ulong)asc_dvc_varp, (ulong)qdonep);
9304 ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep);
9307 * Get the struct scsi_cmnd structure and Scsi_Host structure for the
9308 * command that has been completed.
9310 scp = (struct scsi_cmnd *)ASC_U32_TO_VADDR(qdonep->d2.srb_ptr);
9311 ASC_DBG1(1, "asc_isr_callback: scp 0x%lx\n", (ulong)scp);
9314 ASC_PRINT("asc_isr_callback: scp is NULL\n");
9317 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
9319 shost = scp->device->host;
9320 ASC_STATS(shost, callback);
9321 ASC_DBG1(1, "asc_isr_callback: shost 0x%lx\n", (ulong)shost);
9323 boardp = shost_priv(shost);
9324 BUG_ON(asc_dvc_varp != &boardp->dvc_var.asc_dvc_var);
9327 * 'qdonep' contains the command's ending status.
9329 switch (qdonep->d3.done_stat) {
9331 ASC_DBG(2, "asc_isr_callback: QD_NO_ERROR\n");
9335 * Check for an underrun condition.
9337 * If there was no error and an underrun condition, then
9338 * return the number of underrun bytes.
9340 if (scp->request_bufflen != 0 && qdonep->remain_bytes != 0 &&
9341 qdonep->remain_bytes <= scp->request_bufflen) {
9343 "asc_isr_callback: underrun condition %u bytes\n",
9344 (unsigned)qdonep->remain_bytes);
9345 scp->resid = qdonep->remain_bytes;
9350 ASC_DBG(2, "asc_isr_callback: QD_WITH_ERROR\n");
9351 switch (qdonep->d3.host_stat) {
9352 case QHSTA_NO_ERROR:
9353 if (qdonep->d3.scsi_stat == SAM_STAT_CHECK_CONDITION) {
9355 "asc_isr_callback: SAM_STAT_CHECK_CONDITION\n");
9356 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
9357 sizeof(scp->sense_buffer));
9359 * Note: The 'status_byte()' macro used by
9360 * target drivers defined in scsi.h shifts the
9361 * status byte returned by host drivers right
9362 * by 1 bit. This is why target drivers also
9363 * use right shifted status byte definitions.
9364 * For instance target drivers use
9365 * CHECK_CONDITION, defined to 0x1, instead of
9366 * the SCSI defined check condition value of
9367 * 0x2. Host drivers are supposed to return
9368 * the status byte as it is defined by SCSI.
9370 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
9371 STATUS_BYTE(qdonep->d3.scsi_stat);
9373 scp->result = STATUS_BYTE(qdonep->d3.scsi_stat);
9378 /* QHSTA error occurred */
9379 ASC_DBG1(1, "asc_isr_callback: host_stat 0x%x\n",
9380 qdonep->d3.host_stat);
9381 scp->result = HOST_BYTE(DID_BAD_TARGET);
9386 case QD_ABORTED_BY_HOST:
9387 ASC_DBG(1, "asc_isr_callback: QD_ABORTED_BY_HOST\n");
9389 HOST_BYTE(DID_ABORT) | MSG_BYTE(qdonep->d3.
9391 STATUS_BYTE(qdonep->d3.scsi_stat);
9395 ASC_DBG1(1, "asc_isr_callback: done_stat 0x%x\n",
9396 qdonep->d3.done_stat);
9398 HOST_BYTE(DID_ERROR) | MSG_BYTE(qdonep->d3.
9400 STATUS_BYTE(qdonep->d3.scsi_stat);
9405 * If the 'init_tidmask' bit isn't already set for the target and the
9406 * current request finished normally, then set the bit for the target
9407 * to indicate that a device is present.
9409 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
9410 qdonep->d3.done_stat == QD_NO_ERROR &&
9411 qdonep->d3.host_stat == QHSTA_NO_ERROR) {
9412 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
9420 static int AscIsrQDone(ASC_DVC_VAR *asc_dvc)
9429 ASC_SCSI_BIT_ID_TYPE scsi_busy;
9430 ASC_SCSI_BIT_ID_TYPE target_id;
9434 uchar cur_target_qng;
9435 ASC_QDONE_INFO scsiq_buf;
9436 ASC_QDONE_INFO *scsiq;
9439 iop_base = asc_dvc->iop_base;
9441 scsiq = (ASC_QDONE_INFO *)&scsiq_buf;
9442 done_q_tail = (uchar)AscGetVarDoneQTail(iop_base);
9443 q_addr = ASC_QNO_TO_QADDR(done_q_tail);
9444 next_qp = AscReadLramByte(iop_base,
9445 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_FWD));
9446 if (next_qp != ASC_QLINK_END) {
9447 AscPutVarDoneQTail(iop_base, next_qp);
9448 q_addr = ASC_QNO_TO_QADDR(next_qp);
9449 sg_queue_cnt = _AscCopyLramScsiDoneQ(iop_base, q_addr, scsiq,
9450 asc_dvc->max_dma_count);
9451 AscWriteLramByte(iop_base,
9453 (ushort)ASC_SCSIQ_B_STATUS),
9455 q_status & (uchar)~(QS_READY |
9457 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix);
9458 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix);
9459 if ((scsiq->cntl & QC_SG_HEAD) != 0) {
9461 sg_list_qp = next_qp;
9462 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) {
9463 sg_list_qp = AscReadLramByte(iop_base,
9467 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp);
9468 if (sg_list_qp == ASC_QLINK_END) {
9469 AscSetLibErrorCode(asc_dvc,
9470 ASCQ_ERR_SG_Q_LINKS);
9471 scsiq->d3.done_stat = QD_WITH_ERROR;
9472 scsiq->d3.host_stat =
9473 QHSTA_D_QDONE_SG_LIST_CORRUPTED;
9474 goto FATAL_ERR_QDONE;
9476 AscWriteLramByte(iop_base,
9477 (ushort)(sg_q_addr + (ushort)
9478 ASC_SCSIQ_B_STATUS),
9481 n_q_used = sg_queue_cnt + 1;
9482 AscPutVarDoneQTail(iop_base, sg_list_qp);
9484 if (asc_dvc->queue_full_or_busy & target_id) {
9485 cur_target_qng = AscReadLramByte(iop_base,
9491 if (cur_target_qng < asc_dvc->max_dvc_qng[tid_no]) {
9492 scsi_busy = AscReadLramByte(iop_base, (ushort)
9494 scsi_busy &= ~target_id;
9495 AscWriteLramByte(iop_base,
9496 (ushort)ASCV_SCSIBUSY_B,
9498 asc_dvc->queue_full_or_busy &= ~target_id;
9501 if (asc_dvc->cur_total_qng >= n_q_used) {
9502 asc_dvc->cur_total_qng -= n_q_used;
9503 if (asc_dvc->cur_dvc_qng[tid_no] != 0) {
9504 asc_dvc->cur_dvc_qng[tid_no]--;
9507 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CUR_QNG);
9508 scsiq->d3.done_stat = QD_WITH_ERROR;
9509 goto FATAL_ERR_QDONE;
9511 if ((scsiq->d2.srb_ptr == 0UL) ||
9512 ((scsiq->q_status & QS_ABORTED) != 0)) {
9514 } else if (scsiq->q_status == QS_DONE) {
9515 false_overrun = FALSE;
9516 if (scsiq->extra_bytes != 0) {
9517 scsiq->remain_bytes +=
9518 (ADV_DCNT)scsiq->extra_bytes;
9520 if (scsiq->d3.done_stat == QD_WITH_ERROR) {
9521 if (scsiq->d3.host_stat ==
9522 QHSTA_M_DATA_OVER_RUN) {
9524 cntl & (QC_DATA_IN | QC_DATA_OUT))
9526 scsiq->d3.done_stat =
9528 scsiq->d3.host_stat =
9530 } else if (false_overrun) {
9531 scsiq->d3.done_stat =
9533 scsiq->d3.host_stat =
9536 } else if (scsiq->d3.host_stat ==
9537 QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) {
9538 AscStopChip(iop_base);
9539 AscSetChipControl(iop_base,
9540 (uchar)(CC_SCSI_RESET
9543 AscSetChipControl(iop_base, CC_HALT);
9544 AscSetChipStatus(iop_base,
9545 CIW_CLR_SCSI_RESET_INT);
9546 AscSetChipStatus(iop_base, 0);
9547 AscSetChipControl(iop_base, 0);
9550 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
9551 asc_isr_callback(asc_dvc, scsiq);
9553 if ((AscReadLramByte(iop_base,
9554 (ushort)(q_addr + (ushort)
9557 asc_dvc->unit_not_ready &= ~target_id;
9558 if (scsiq->d3.done_stat != QD_NO_ERROR) {
9559 asc_dvc->start_motor &=
9566 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_Q_STATUS);
9568 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
9569 asc_isr_callback(asc_dvc, scsiq);
9577 static int AscISR(ASC_DVC_VAR *asc_dvc)
9579 ASC_CS_TYPE chipstat;
9581 ushort saved_ram_addr;
9583 uchar saved_ctrl_reg;
9588 iop_base = asc_dvc->iop_base;
9589 int_pending = FALSE;
9591 if (AscIsIntPending(iop_base) == 0)
9594 if ((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0) {
9597 if (asc_dvc->in_critical_cnt != 0) {
9598 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL);
9601 if (asc_dvc->is_in_int) {
9602 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY);
9605 asc_dvc->is_in_int = TRUE;
9606 ctrl_reg = AscGetChipControl(iop_base);
9607 saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET |
9608 CC_SINGLE_STEP | CC_DIAG | CC_TEST));
9609 chipstat = AscGetChipStatus(iop_base);
9610 if (chipstat & CSW_SCSI_RESET_LATCH) {
9611 if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) {
9614 asc_dvc->sdtr_done = 0;
9615 saved_ctrl_reg &= (uchar)(~CC_HALT);
9616 while ((AscGetChipStatus(iop_base) &
9617 CSW_SCSI_RESET_ACTIVE) && (i-- > 0)) {
9620 AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT));
9621 AscSetChipControl(iop_base, CC_HALT);
9622 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
9623 AscSetChipStatus(iop_base, 0);
9624 chipstat = AscGetChipStatus(iop_base);
9627 saved_ram_addr = AscGetChipLramAddr(iop_base);
9628 host_flag = AscReadLramByte(iop_base,
9630 (uchar)(~ASC_HOST_FLAG_IN_ISR);
9631 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
9632 (uchar)(host_flag | (uchar)ASC_HOST_FLAG_IN_ISR));
9633 if ((chipstat & CSW_INT_PENDING) || (int_pending)) {
9634 AscAckInterrupt(iop_base);
9636 if ((chipstat & CSW_HALTED) && (ctrl_reg & CC_SINGLE_STEP)) {
9637 if (AscIsrChipHalted(asc_dvc) == ERR) {
9638 goto ISR_REPORT_QDONE_FATAL_ERROR;
9640 saved_ctrl_reg &= (uchar)(~CC_HALT);
9643 ISR_REPORT_QDONE_FATAL_ERROR:
9644 if ((asc_dvc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) != 0) {
9646 AscIsrQDone(asc_dvc)) & 0x01) != 0) {
9651 AscIsrQDone(asc_dvc)) == 1) {
9654 } while (status == 0x11);
9656 if ((status & 0x80) != 0)
9660 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
9661 AscSetChipLramAddr(iop_base, saved_ram_addr);
9662 AscSetChipControl(iop_base, saved_ctrl_reg);
9663 asc_dvc->is_in_int = FALSE;
9670 * Reset the bus associated with the command 'scp'.
9672 * This function runs its own thread. Interrupts must be blocked but
9673 * sleeping is allowed and no locking other than for host structures is
9674 * required. Returns SUCCESS or FAILED.
9676 static int advansys_reset(struct scsi_cmnd *scp)
9678 struct Scsi_Host *shost = scp->device->host;
9679 struct asc_board *boardp = shost_priv(shost);
9680 unsigned long flags;
9684 ASC_DBG1(1, "advansys_reset: 0x%p\n", scp);
9686 ASC_STATS(shost, reset);
9688 scmd_printk(KERN_INFO, scp, "SCSI bus reset started...\n");
9690 if (ASC_NARROW_BOARD(boardp)) {
9691 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
9693 /* Reset the chip and SCSI bus. */
9694 ASC_DBG(1, "advansys_reset: before AscInitAsc1000Driver()\n");
9695 status = AscInitAsc1000Driver(asc_dvc);
9697 /* Refer to ASC_IERR_* defintions for meaning of 'err_code'. */
9698 if (asc_dvc->err_code) {
9699 scmd_printk(KERN_INFO, scp, "SCSI bus reset error: "
9700 "0x%x\n", asc_dvc->err_code);
9702 } else if (status) {
9703 scmd_printk(KERN_INFO, scp, "SCSI bus reset warning: "
9706 scmd_printk(KERN_INFO, scp, "SCSI bus reset "
9710 ASC_DBG(1, "advansys_reset: after AscInitAsc1000Driver()\n");
9711 spin_lock_irqsave(&boardp->lock, flags);
9714 * If the suggest reset bus flags are set, then reset the bus.
9715 * Otherwise only reset the device.
9717 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
9720 * Reset the target's SCSI bus.
9722 ASC_DBG(1, "advansys_reset: before AdvResetChipAndSB()\n");
9723 switch (AdvResetChipAndSB(adv_dvc)) {
9725 scmd_printk(KERN_INFO, scp, "SCSI bus reset "
9730 scmd_printk(KERN_INFO, scp, "SCSI bus reset error\n");
9734 spin_lock_irqsave(&boardp->lock, flags);
9738 /* Save the time of the most recently completed reset. */
9739 boardp->last_reset = jiffies;
9740 spin_unlock_irqrestore(&boardp->lock, flags);
9742 ASC_DBG1(1, "advansys_reset: ret %d\n", ret);
9748 * advansys_biosparam()
9750 * Translate disk drive geometry if the "BIOS greater than 1 GB"
9751 * support is enabled for a drive.
9753 * ip (information pointer) is an int array with the following definition:
9759 advansys_biosparam(struct scsi_device *sdev, struct block_device *bdev,
9760 sector_t capacity, int ip[])
9762 struct asc_board *boardp = shost_priv(sdev->host);
9764 ASC_DBG(1, "advansys_biosparam: begin\n");
9765 ASC_STATS(sdev->host, biosparam);
9766 if (ASC_NARROW_BOARD(boardp)) {
9767 if ((boardp->dvc_var.asc_dvc_var.dvc_cntl &
9768 ASC_CNTL_BIOS_GT_1GB) && capacity > 0x200000) {
9776 if ((boardp->dvc_var.adv_dvc_var.bios_ctrl &
9777 BIOS_CTRL_EXTENDED_XLAT) && capacity > 0x200000) {
9785 ip[2] = (unsigned long)capacity / (ip[0] * ip[1]);
9786 ASC_DBG(1, "advansys_biosparam: end\n");
9791 * First-level interrupt handler.
9793 * 'dev_id' is a pointer to the interrupting adapter's Scsi_Host.
9795 static irqreturn_t advansys_interrupt(int irq, void *dev_id)
9797 unsigned long flags;
9798 struct Scsi_Host *shost = dev_id;
9799 struct asc_board *boardp = shost_priv(shost);
9800 irqreturn_t result = IRQ_NONE;
9802 ASC_DBG1(2, "advansys_interrupt: boardp 0x%p\n", boardp);
9803 spin_lock_irqsave(&boardp->lock, flags);
9804 if (ASC_NARROW_BOARD(boardp)) {
9805 if (AscIsIntPending(shost->io_port)) {
9806 result = IRQ_HANDLED;
9807 ASC_STATS(shost, interrupt);
9808 ASC_DBG(1, "advansys_interrupt: before AscISR()\n");
9809 AscISR(&boardp->dvc_var.asc_dvc_var);
9812 ASC_DBG(1, "advansys_interrupt: before AdvISR()\n");
9813 if (AdvISR(&boardp->dvc_var.adv_dvc_var)) {
9814 result = IRQ_HANDLED;
9815 ASC_STATS(shost, interrupt);
9818 spin_unlock_irqrestore(&boardp->lock, flags);
9820 ASC_DBG(1, "advansys_interrupt: end\n");
9824 static int AscHostReqRiscHalt(PortAddr iop_base)
9828 uchar saved_stop_code;
9830 if (AscIsChipHalted(iop_base))
9832 saved_stop_code = AscReadLramByte(iop_base, ASCV_STOP_CODE_B);
9833 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
9834 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP);
9836 if (AscIsChipHalted(iop_base)) {
9841 } while (count++ < 20);
9842 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, saved_stop_code);
9847 AscSetRunChipSynRegAtID(PortAddr iop_base, uchar tid_no, uchar sdtr_data)
9851 if (AscHostReqRiscHalt(iop_base)) {
9852 sta = AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
9853 AscStartChip(iop_base);
9858 static void AscAsyncFix(ASC_DVC_VAR *asc_dvc, struct scsi_device *sdev)
9860 char type = sdev->type;
9861 ASC_SCSI_BIT_ID_TYPE tid_bits = 1 << sdev->id;
9863 if (!(asc_dvc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN))
9865 if (asc_dvc->init_sdtr & tid_bits)
9868 if ((type == TYPE_ROM) && (strncmp(sdev->vendor, "HP ", 3) == 0))
9869 asc_dvc->pci_fix_asyn_xfer_always |= tid_bits;
9871 asc_dvc->pci_fix_asyn_xfer |= tid_bits;
9872 if ((type == TYPE_PROCESSOR) || (type == TYPE_SCANNER) ||
9873 (type == TYPE_ROM) || (type == TYPE_TAPE))
9874 asc_dvc->pci_fix_asyn_xfer &= ~tid_bits;
9876 if (asc_dvc->pci_fix_asyn_xfer & tid_bits)
9877 AscSetRunChipSynRegAtID(asc_dvc->iop_base, sdev->id,
9878 ASYN_SDTR_DATA_FIX_PCI_REV_AB);
9882 advansys_narrow_slave_configure(struct scsi_device *sdev, ASC_DVC_VAR *asc_dvc)
9884 ASC_SCSI_BIT_ID_TYPE tid_bit = 1 << sdev->id;
9885 ASC_SCSI_BIT_ID_TYPE orig_use_tagged_qng = asc_dvc->use_tagged_qng;
9887 if (sdev->lun == 0) {
9888 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr = asc_dvc->init_sdtr;
9889 if ((asc_dvc->cfg->sdtr_enable & tid_bit) && sdev->sdtr) {
9890 asc_dvc->init_sdtr |= tid_bit;
9892 asc_dvc->init_sdtr &= ~tid_bit;
9895 if (orig_init_sdtr != asc_dvc->init_sdtr)
9896 AscAsyncFix(asc_dvc, sdev);
9899 if (sdev->tagged_supported) {
9900 if (asc_dvc->cfg->cmd_qng_enabled & tid_bit) {
9901 if (sdev->lun == 0) {
9902 asc_dvc->cfg->can_tagged_qng |= tid_bit;
9903 asc_dvc->use_tagged_qng |= tid_bit;
9905 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG,
9906 asc_dvc->max_dvc_qng[sdev->id]);
9909 if (sdev->lun == 0) {
9910 asc_dvc->cfg->can_tagged_qng &= ~tid_bit;
9911 asc_dvc->use_tagged_qng &= ~tid_bit;
9913 scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
9916 if ((sdev->lun == 0) &&
9917 (orig_use_tagged_qng != asc_dvc->use_tagged_qng)) {
9918 AscWriteLramByte(asc_dvc->iop_base, ASCV_DISC_ENABLE_B,
9919 asc_dvc->cfg->disc_enable);
9920 AscWriteLramByte(asc_dvc->iop_base, ASCV_USE_TAGGED_QNG_B,
9921 asc_dvc->use_tagged_qng);
9922 AscWriteLramByte(asc_dvc->iop_base, ASCV_CAN_TAGGED_QNG_B,
9923 asc_dvc->cfg->can_tagged_qng);
9925 asc_dvc->max_dvc_qng[sdev->id] =
9926 asc_dvc->cfg->max_tag_qng[sdev->id];
9927 AscWriteLramByte(asc_dvc->iop_base,
9928 (ushort)(ASCV_MAX_DVC_QNG_BEG + sdev->id),
9929 asc_dvc->max_dvc_qng[sdev->id]);
9936 * If the EEPROM enabled WDTR for the device and the device supports wide
9937 * bus (16 bit) transfers, then turn on the device's 'wdtr_able' bit and
9938 * write the new value to the microcode.
9941 advansys_wide_enable_wdtr(AdvPortAddr iop_base, unsigned short tidmask)
9943 unsigned short cfg_word;
9944 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
9945 if ((cfg_word & tidmask) != 0)
9948 cfg_word |= tidmask;
9949 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
9952 * Clear the microcode SDTR and WDTR negotiation done indicators for
9953 * the target to cause it to negotiate with the new setting set above.
9954 * WDTR when accepted causes the target to enter asynchronous mode, so
9955 * SDTR must be negotiated.
9957 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
9958 cfg_word &= ~tidmask;
9959 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
9960 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
9961 cfg_word &= ~tidmask;
9962 AdvWriteWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
9966 * Synchronous Transfers
9968 * If the EEPROM enabled SDTR for the device and the device
9969 * supports synchronous transfers, then turn on the device's
9970 * 'sdtr_able' bit. Write the new value to the microcode.
9973 advansys_wide_enable_sdtr(AdvPortAddr iop_base, unsigned short tidmask)
9975 unsigned short cfg_word;
9976 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
9977 if ((cfg_word & tidmask) != 0)
9980 cfg_word |= tidmask;
9981 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
9984 * Clear the microcode "SDTR negotiation" done indicator for the
9985 * target to cause it to negotiate with the new setting set above.
9987 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
9988 cfg_word &= ~tidmask;
9989 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
9993 * PPR (Parallel Protocol Request) Capable
9995 * If the device supports DT mode, then it must be PPR capable.
9996 * The PPR message will be used in place of the SDTR and WDTR
9997 * messages to negotiate synchronous speed and offset, transfer
9998 * width, and protocol options.
10000 static void advansys_wide_enable_ppr(ADV_DVC_VAR *adv_dvc,
10001 AdvPortAddr iop_base, unsigned short tidmask)
10003 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
10004 adv_dvc->ppr_able |= tidmask;
10005 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
10009 advansys_wide_slave_configure(struct scsi_device *sdev, ADV_DVC_VAR *adv_dvc)
10011 AdvPortAddr iop_base = adv_dvc->iop_base;
10012 unsigned short tidmask = 1 << sdev->id;
10014 if (sdev->lun == 0) {
10016 * Handle WDTR, SDTR, and Tag Queuing. If the feature
10017 * is enabled in the EEPROM and the device supports the
10018 * feature, then enable it in the microcode.
10021 if ((adv_dvc->wdtr_able & tidmask) && sdev->wdtr)
10022 advansys_wide_enable_wdtr(iop_base, tidmask);
10023 if ((adv_dvc->sdtr_able & tidmask) && sdev->sdtr)
10024 advansys_wide_enable_sdtr(iop_base, tidmask);
10025 if (adv_dvc->chip_type == ADV_CHIP_ASC38C1600 && sdev->ppr)
10026 advansys_wide_enable_ppr(adv_dvc, iop_base, tidmask);
10029 * Tag Queuing is disabled for the BIOS which runs in polled
10030 * mode and would see no benefit from Tag Queuing. Also by
10031 * disabling Tag Queuing in the BIOS devices with Tag Queuing
10032 * bugs will at least work with the BIOS.
10034 if ((adv_dvc->tagqng_able & tidmask) &&
10035 sdev->tagged_supported) {
10036 unsigned short cfg_word;
10037 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word);
10038 cfg_word |= tidmask;
10039 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
10041 AdvWriteByteLram(iop_base,
10042 ASC_MC_NUMBER_OF_MAX_CMD + sdev->id,
10043 adv_dvc->max_dvc_qng);
10047 if ((adv_dvc->tagqng_able & tidmask) && sdev->tagged_supported) {
10048 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG,
10049 adv_dvc->max_dvc_qng);
10051 scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
10056 * Set the number of commands to queue per device for the
10057 * specified host adapter.
10059 static int advansys_slave_configure(struct scsi_device *sdev)
10061 struct asc_board *boardp = shost_priv(sdev->host);
10063 if (ASC_NARROW_BOARD(boardp))
10064 advansys_narrow_slave_configure(sdev,
10065 &boardp->dvc_var.asc_dvc_var);
10067 advansys_wide_slave_configure(sdev,
10068 &boardp->dvc_var.adv_dvc_var);
10073 static int asc_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
10074 struct asc_scsi_q *asc_scsi_q)
10076 memset(asc_scsi_q, 0, sizeof(*asc_scsi_q));
10079 * Point the ASC_SCSI_Q to the 'struct scsi_cmnd'.
10081 asc_scsi_q->q2.srb_ptr = ASC_VADDR_TO_U32(scp);
10084 * Build the ASC_SCSI_Q request.
10086 asc_scsi_q->cdbptr = &scp->cmnd[0];
10087 asc_scsi_q->q2.cdb_len = scp->cmd_len;
10088 asc_scsi_q->q1.target_id = ASC_TID_TO_TARGET_ID(scp->device->id);
10089 asc_scsi_q->q1.target_lun = scp->device->lun;
10090 asc_scsi_q->q2.target_ix =
10091 ASC_TIDLUN_TO_IX(scp->device->id, scp->device->lun);
10092 asc_scsi_q->q1.sense_addr =
10093 cpu_to_le32(virt_to_bus(&scp->sense_buffer[0]));
10094 asc_scsi_q->q1.sense_len = sizeof(scp->sense_buffer);
10097 * If there are any outstanding requests for the current target,
10098 * then every 255th request send an ORDERED request. This heuristic
10099 * tries to retain the benefit of request sorting while preventing
10100 * request starvation. 255 is the max number of tags or pending commands
10101 * a device may have outstanding.
10103 * The request count is incremented below for every successfully
10107 if ((boardp->dvc_var.asc_dvc_var.cur_dvc_qng[scp->device->id] > 0) &&
10108 (boardp->reqcnt[scp->device->id] % 255) == 0) {
10109 asc_scsi_q->q2.tag_code = MSG_ORDERED_TAG;
10111 asc_scsi_q->q2.tag_code = MSG_SIMPLE_TAG;
10115 * Build ASC_SCSI_Q for a contiguous buffer or a scatter-gather
10118 if (scp->use_sg == 0) {
10120 * CDB request of single contiguous buffer.
10122 ASC_STATS(scp->device->host, cont_cnt);
10123 scp->SCp.dma_handle = scp->request_bufflen ?
10124 dma_map_single(boardp->dev, scp->request_buffer,
10125 scp->request_bufflen,
10126 scp->sc_data_direction) : 0;
10127 asc_scsi_q->q1.data_addr = cpu_to_le32(scp->SCp.dma_handle);
10128 asc_scsi_q->q1.data_cnt = cpu_to_le32(scp->request_bufflen);
10129 ASC_STATS_ADD(scp->device->host, cont_xfer,
10130 ASC_CEILING(scp->request_bufflen, 512));
10131 asc_scsi_q->q1.sg_queue_cnt = 0;
10132 asc_scsi_q->sg_head = NULL;
10135 * CDB scatter-gather request list.
10139 struct scatterlist *slp;
10140 struct asc_sg_head *asc_sg_head;
10142 slp = (struct scatterlist *)scp->request_buffer;
10143 use_sg = dma_map_sg(boardp->dev, slp, scp->use_sg,
10144 scp->sc_data_direction);
10146 if (use_sg > scp->device->host->sg_tablesize) {
10147 ASC_PRINT3("asc_build_req: board %d: use_sg %d > "
10148 "sg_tablesize %d\n", boardp->id, use_sg,
10149 scp->device->host->sg_tablesize);
10150 dma_unmap_sg(boardp->dev, slp, scp->use_sg,
10151 scp->sc_data_direction);
10152 scp->result = HOST_BYTE(DID_ERROR);
10156 ASC_STATS(scp->device->host, sg_cnt);
10158 asc_sg_head = kzalloc(sizeof(asc_scsi_q->sg_head) +
10159 use_sg * sizeof(struct asc_sg_list), GFP_ATOMIC);
10160 if (!asc_sg_head) {
10161 dma_unmap_sg(boardp->dev, slp, scp->use_sg,
10162 scp->sc_data_direction);
10163 scp->result = HOST_BYTE(DID_SOFT_ERROR);
10167 asc_scsi_q->q1.cntl |= QC_SG_HEAD;
10168 asc_scsi_q->sg_head = asc_sg_head;
10169 asc_scsi_q->q1.data_cnt = 0;
10170 asc_scsi_q->q1.data_addr = 0;
10171 /* This is a byte value, otherwise it would need to be swapped. */
10172 asc_sg_head->entry_cnt = asc_scsi_q->q1.sg_queue_cnt = use_sg;
10173 ASC_STATS_ADD(scp->device->host, sg_elem,
10174 asc_sg_head->entry_cnt);
10177 * Convert scatter-gather list into ASC_SG_HEAD list.
10179 for (sgcnt = 0; sgcnt < use_sg; sgcnt++, slp++) {
10180 asc_sg_head->sg_list[sgcnt].addr =
10181 cpu_to_le32(sg_dma_address(slp));
10182 asc_sg_head->sg_list[sgcnt].bytes =
10183 cpu_to_le32(sg_dma_len(slp));
10184 ASC_STATS_ADD(scp->device->host, sg_xfer,
10185 ASC_CEILING(sg_dma_len(slp), 512));
10189 ASC_DBG_PRT_ASC_SCSI_Q(2, &asc_scsi_q);
10190 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
10192 return ASC_NOERROR;
10196 * Build scatter-gather list for Adv Library (Wide Board).
10198 * Additional ADV_SG_BLOCK structures will need to be allocated
10199 * if the total number of scatter-gather elements exceeds
10200 * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are
10201 * assumed to be physically contiguous.
10204 * ADV_SUCCESS(1) - SG List successfully created
10205 * ADV_ERROR(-1) - SG List creation failed
10208 adv_get_sglist(struct asc_board *boardp, adv_req_t *reqp, struct scsi_cmnd *scp,
10211 adv_sgblk_t *sgblkp;
10212 ADV_SCSI_REQ_Q *scsiqp;
10213 struct scatterlist *slp;
10215 ADV_SG_BLOCK *sg_block, *prev_sg_block;
10216 ADV_PADDR sg_block_paddr;
10219 scsiqp = (ADV_SCSI_REQ_Q *)ADV_32BALIGN(&reqp->scsi_req_q);
10220 slp = (struct scatterlist *)scp->request_buffer;
10221 sg_elem_cnt = use_sg;
10222 prev_sg_block = NULL;
10223 reqp->sgblkp = NULL;
10227 * Allocate a 'adv_sgblk_t' structure from the board free
10228 * list. One 'adv_sgblk_t' structure holds NO_OF_SG_PER_BLOCK
10229 * (15) scatter-gather elements.
10231 if ((sgblkp = boardp->adv_sgblkp) == NULL) {
10232 ASC_DBG(1, "adv_get_sglist: no free adv_sgblk_t\n");
10233 ASC_STATS(scp->device->host, adv_build_nosg);
10236 * Allocation failed. Free 'adv_sgblk_t' structures
10237 * already allocated for the request.
10239 while ((sgblkp = reqp->sgblkp) != NULL) {
10240 /* Remove 'sgblkp' from the request list. */
10241 reqp->sgblkp = sgblkp->next_sgblkp;
10243 /* Add 'sgblkp' to the board free list. */
10244 sgblkp->next_sgblkp = boardp->adv_sgblkp;
10245 boardp->adv_sgblkp = sgblkp;
10250 /* Complete 'adv_sgblk_t' board allocation. */
10251 boardp->adv_sgblkp = sgblkp->next_sgblkp;
10252 sgblkp->next_sgblkp = NULL;
10255 * Get 8 byte aligned virtual and physical addresses
10256 * for the allocated ADV_SG_BLOCK structure.
10258 sg_block = (ADV_SG_BLOCK *)ADV_8BALIGN(&sgblkp->sg_block);
10259 sg_block_paddr = virt_to_bus(sg_block);
10262 * Check if this is the first 'adv_sgblk_t' for the
10265 if (reqp->sgblkp == NULL) {
10266 /* Request's first scatter-gather block. */
10267 reqp->sgblkp = sgblkp;
10270 * Set ADV_SCSI_REQ_T ADV_SG_BLOCK virtual and physical
10271 * address pointers.
10273 scsiqp->sg_list_ptr = sg_block;
10274 scsiqp->sg_real_addr = cpu_to_le32(sg_block_paddr);
10276 /* Request's second or later scatter-gather block. */
10277 sgblkp->next_sgblkp = reqp->sgblkp;
10278 reqp->sgblkp = sgblkp;
10281 * Point the previous ADV_SG_BLOCK structure to
10282 * the newly allocated ADV_SG_BLOCK structure.
10284 prev_sg_block->sg_ptr = cpu_to_le32(sg_block_paddr);
10287 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) {
10288 sg_block->sg_list[i].sg_addr =
10289 cpu_to_le32(sg_dma_address(slp));
10290 sg_block->sg_list[i].sg_count =
10291 cpu_to_le32(sg_dma_len(slp));
10292 ASC_STATS_ADD(scp->device->host, sg_xfer,
10293 ASC_CEILING(sg_dma_len(slp), 512));
10295 if (--sg_elem_cnt == 0) { /* Last ADV_SG_BLOCK and scatter-gather entry. */
10296 sg_block->sg_cnt = i + 1;
10297 sg_block->sg_ptr = 0L; /* Last ADV_SG_BLOCK in list. */
10298 return ADV_SUCCESS;
10302 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK;
10303 prev_sg_block = sg_block;
10308 * Build a request structure for the Adv Library (Wide Board).
10310 * If an adv_req_t can not be allocated to issue the request,
10311 * then return ASC_BUSY. If an error occurs, then return ASC_ERROR.
10313 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the
10314 * microcode for DMA addresses or math operations are byte swapped
10315 * to little-endian order.
10318 adv_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
10319 ADV_SCSI_REQ_Q **adv_scsiqpp)
10322 ADV_SCSI_REQ_Q *scsiqp;
10327 * Allocate an adv_req_t structure from the board to execute
10330 if (boardp->adv_reqp == NULL) {
10331 ASC_DBG(1, "adv_build_req: no free adv_req_t\n");
10332 ASC_STATS(scp->device->host, adv_build_noreq);
10335 reqp = boardp->adv_reqp;
10336 boardp->adv_reqp = reqp->next_reqp;
10337 reqp->next_reqp = NULL;
10341 * Get 32-byte aligned ADV_SCSI_REQ_Q and ADV_SG_BLOCK pointers.
10343 scsiqp = (ADV_SCSI_REQ_Q *)ADV_32BALIGN(&reqp->scsi_req_q);
10346 * Initialize the structure.
10348 scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0;
10351 * Set the ADV_SCSI_REQ_Q 'srb_ptr' to point to the adv_req_t structure.
10353 scsiqp->srb_ptr = ASC_VADDR_TO_U32(reqp);
10356 * Set the adv_req_t 'cmndp' to point to the struct scsi_cmnd structure.
10361 * Build the ADV_SCSI_REQ_Q request.
10364 /* Set CDB length and copy it to the request structure. */
10365 scsiqp->cdb_len = scp->cmd_len;
10366 /* Copy first 12 CDB bytes to cdb[]. */
10367 for (i = 0; i < scp->cmd_len && i < 12; i++) {
10368 scsiqp->cdb[i] = scp->cmnd[i];
10370 /* Copy last 4 CDB bytes, if present, to cdb16[]. */
10371 for (; i < scp->cmd_len; i++) {
10372 scsiqp->cdb16[i - 12] = scp->cmnd[i];
10375 scsiqp->target_id = scp->device->id;
10376 scsiqp->target_lun = scp->device->lun;
10378 scsiqp->sense_addr = cpu_to_le32(virt_to_bus(&scp->sense_buffer[0]));
10379 scsiqp->sense_len = sizeof(scp->sense_buffer);
10382 * Build ADV_SCSI_REQ_Q for a contiguous buffer or a scatter-gather
10386 scsiqp->data_cnt = cpu_to_le32(scp->request_bufflen);
10387 scsiqp->vdata_addr = scp->request_buffer;
10388 scsiqp->data_addr = cpu_to_le32(virt_to_bus(scp->request_buffer));
10390 if (scp->use_sg == 0) {
10392 * CDB request of single contiguous buffer.
10394 reqp->sgblkp = NULL;
10395 scsiqp->data_cnt = cpu_to_le32(scp->request_bufflen);
10396 if (scp->request_bufflen) {
10397 scsiqp->vdata_addr = scp->request_buffer;
10398 scp->SCp.dma_handle =
10399 dma_map_single(boardp->dev, scp->request_buffer,
10400 scp->request_bufflen,
10401 scp->sc_data_direction);
10403 scsiqp->vdata_addr = NULL;
10404 scp->SCp.dma_handle = 0;
10406 scsiqp->data_addr = cpu_to_le32(scp->SCp.dma_handle);
10407 scsiqp->sg_list_ptr = NULL;
10408 scsiqp->sg_real_addr = 0;
10409 ASC_STATS(scp->device->host, cont_cnt);
10410 ASC_STATS_ADD(scp->device->host, cont_xfer,
10411 ASC_CEILING(scp->request_bufflen, 512));
10414 * CDB scatter-gather request list.
10416 struct scatterlist *slp;
10419 slp = (struct scatterlist *)scp->request_buffer;
10420 use_sg = dma_map_sg(boardp->dev, slp, scp->use_sg,
10421 scp->sc_data_direction);
10423 if (use_sg > ADV_MAX_SG_LIST) {
10424 ASC_PRINT3("adv_build_req: board %d: use_sg %d > "
10425 "ADV_MAX_SG_LIST %d\n", boardp->id, use_sg,
10426 scp->device->host->sg_tablesize);
10427 dma_unmap_sg(boardp->dev, slp, scp->use_sg,
10428 scp->sc_data_direction);
10429 scp->result = HOST_BYTE(DID_ERROR);
10432 * Free the 'adv_req_t' structure by adding it back
10433 * to the board free list.
10435 reqp->next_reqp = boardp->adv_reqp;
10436 boardp->adv_reqp = reqp;
10441 ret = adv_get_sglist(boardp, reqp, scp, use_sg);
10442 if (ret != ADV_SUCCESS) {
10444 * Free the adv_req_t structure by adding it back to
10445 * the board free list.
10447 reqp->next_reqp = boardp->adv_reqp;
10448 boardp->adv_reqp = reqp;
10453 ASC_STATS(scp->device->host, sg_cnt);
10454 ASC_STATS_ADD(scp->device->host, sg_elem, use_sg);
10457 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
10458 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
10460 *adv_scsiqpp = scsiqp;
10462 return ASC_NOERROR;
10465 static int AscSgListToQueue(int sg_list)
10469 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q);
10470 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0)
10472 return n_sg_list_qs + 1;
10476 AscGetNumOfFreeQueue(ASC_DVC_VAR *asc_dvc, uchar target_ix, uchar n_qs)
10480 ASC_SCSI_BIT_ID_TYPE target_id;
10483 target_id = ASC_TIX_TO_TARGET_ID(target_ix);
10484 tid_no = ASC_TIX_TO_TID(target_ix);
10485 if ((asc_dvc->unit_not_ready & target_id) ||
10486 (asc_dvc->queue_full_or_busy & target_id)) {
10490 cur_used_qs = (uint) asc_dvc->cur_total_qng +
10491 (uint) asc_dvc->last_q_shortage + (uint) ASC_MIN_FREE_Q;
10493 cur_used_qs = (uint) asc_dvc->cur_total_qng +
10494 (uint) ASC_MIN_FREE_Q;
10496 if ((uint) (cur_used_qs + n_qs) <= (uint) asc_dvc->max_total_qng) {
10497 cur_free_qs = (uint) asc_dvc->max_total_qng - cur_used_qs;
10498 if (asc_dvc->cur_dvc_qng[tid_no] >=
10499 asc_dvc->max_dvc_qng[tid_no]) {
10502 return cur_free_qs;
10505 if ((n_qs > asc_dvc->last_q_shortage)
10506 && (n_qs <= (asc_dvc->max_total_qng - ASC_MIN_FREE_Q))) {
10507 asc_dvc->last_q_shortage = n_qs;
10513 static uchar AscAllocFreeQueue(PortAddr iop_base, uchar free_q_head)
10519 q_addr = ASC_QNO_TO_QADDR(free_q_head);
10520 q_status = (uchar)AscReadLramByte(iop_base,
10522 ASC_SCSIQ_B_STATUS));
10523 next_qp = AscReadLramByte(iop_base, (ushort)(q_addr + ASC_SCSIQ_B_FWD));
10524 if (((q_status & QS_READY) == 0) && (next_qp != ASC_QLINK_END))
10526 return ASC_QLINK_END;
10530 AscAllocMultipleFreeQueue(PortAddr iop_base, uchar free_q_head, uchar n_free_q)
10534 for (i = 0; i < n_free_q; i++) {
10535 free_q_head = AscAllocFreeQueue(iop_base, free_q_head);
10536 if (free_q_head == ASC_QLINK_END)
10539 return free_q_head;
10544 * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
10546 * Calling/Exit State:
10550 * Output an ASC_SCSI_Q structure to the chip
10553 DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
10557 ASC_DBG_PRT_HEX(2, "DvcPutScsiQ", outbuf, 2 * words);
10558 AscSetChipLramAddr(iop_base, s_addr);
10559 for (i = 0; i < 2 * words; i += 2) {
10560 if (i == 4 || i == 20) {
10563 outpw(iop_base + IOP_RAM_DATA,
10564 ((ushort)outbuf[i + 1] << 8) | outbuf[i]);
10568 static int AscPutReadyQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
10573 uchar syn_period_ix;
10577 iop_base = asc_dvc->iop_base;
10578 if (((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) &&
10579 ((asc_dvc->sdtr_done & scsiq->q1.target_id) == 0)) {
10580 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix);
10581 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
10583 (sdtr_data >> 4) & (asc_dvc->max_sdtr_index - 1);
10584 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET;
10585 AscMsgOutSDTR(asc_dvc,
10586 asc_dvc->sdtr_period_tbl[syn_period_ix],
10588 scsiq->q1.cntl |= QC_MSG_OUT;
10590 q_addr = ASC_QNO_TO_QADDR(q_no);
10591 if ((scsiq->q1.target_id & asc_dvc->use_tagged_qng) == 0) {
10592 scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG;
10594 scsiq->q1.status = QS_FREE;
10595 AscMemWordCopyPtrToLram(iop_base,
10596 q_addr + ASC_SCSIQ_CDB_BEG,
10597 (uchar *)scsiq->cdbptr, scsiq->q2.cdb_len >> 1);
10599 DvcPutScsiQ(iop_base,
10600 q_addr + ASC_SCSIQ_CPY_BEG,
10601 (uchar *)&scsiq->q1.cntl,
10602 ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1);
10603 AscWriteLramWord(iop_base,
10604 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS),
10605 (ushort)(((ushort)scsiq->q1.
10606 q_no << 8) | (ushort)QS_READY));
10611 AscPutReadySgListQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
10615 ASC_SG_HEAD *sg_head;
10616 ASC_SG_LIST_Q scsi_sg_q;
10617 ASC_DCNT saved_data_addr;
10618 ASC_DCNT saved_data_cnt;
10620 ushort sg_list_dwords;
10622 ushort sg_entry_cnt;
10626 iop_base = asc_dvc->iop_base;
10627 sg_head = scsiq->sg_head;
10628 saved_data_addr = scsiq->q1.data_addr;
10629 saved_data_cnt = scsiq->q1.data_cnt;
10630 scsiq->q1.data_addr = (ASC_PADDR) sg_head->sg_list[0].addr;
10631 scsiq->q1.data_cnt = (ASC_DCNT) sg_head->sg_list[0].bytes;
10632 #if CC_VERY_LONG_SG_LIST
10634 * If sg_head->entry_cnt is greater than ASC_MAX_SG_LIST
10635 * then not all SG elements will fit in the allocated queues.
10636 * The rest of the SG elements will be copied when the RISC
10637 * completes the SG elements that fit and halts.
10639 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
10641 * Set sg_entry_cnt to be the number of SG elements that
10642 * will fit in the allocated SG queues. It is minus 1, because
10643 * the first SG element is handled above. ASC_MAX_SG_LIST is
10644 * already inflated by 1 to account for this. For example it
10645 * may be 50 which is 1 + 7 queues * 7 SG elements.
10647 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
10650 * Keep track of remaining number of SG elements that will
10651 * need to be handled from a_isr.c.
10653 scsiq->remain_sg_entry_cnt =
10654 sg_head->entry_cnt - ASC_MAX_SG_LIST;
10656 #endif /* CC_VERY_LONG_SG_LIST */
10658 * Set sg_entry_cnt to be the number of SG elements that
10659 * will fit in the allocated SG queues. It is minus 1, because
10660 * the first SG element is handled above.
10662 sg_entry_cnt = sg_head->entry_cnt - 1;
10663 #if CC_VERY_LONG_SG_LIST
10665 #endif /* CC_VERY_LONG_SG_LIST */
10666 if (sg_entry_cnt != 0) {
10667 scsiq->q1.cntl |= QC_SG_HEAD;
10668 q_addr = ASC_QNO_TO_QADDR(q_no);
10670 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt;
10671 scsi_sg_q.sg_head_qp = q_no;
10672 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
10673 for (i = 0; i < sg_head->queue_cnt; i++) {
10674 scsi_sg_q.seq_no = i + 1;
10675 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
10676 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
10677 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
10679 scsi_sg_q.sg_list_cnt =
10681 scsi_sg_q.sg_cur_list_cnt =
10684 scsi_sg_q.sg_list_cnt =
10685 ASC_SG_LIST_PER_Q - 1;
10686 scsi_sg_q.sg_cur_list_cnt =
10687 ASC_SG_LIST_PER_Q - 1;
10690 #if CC_VERY_LONG_SG_LIST
10692 * This is the last SG queue in the list of
10693 * allocated SG queues. If there are more
10694 * SG elements than will fit in the allocated
10695 * queues, then set the QCSG_SG_XFER_MORE flag.
10697 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
10698 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
10700 #endif /* CC_VERY_LONG_SG_LIST */
10701 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
10702 #if CC_VERY_LONG_SG_LIST
10704 #endif /* CC_VERY_LONG_SG_LIST */
10705 sg_list_dwords = sg_entry_cnt << 1;
10707 scsi_sg_q.sg_list_cnt = sg_entry_cnt;
10708 scsi_sg_q.sg_cur_list_cnt =
10711 scsi_sg_q.sg_list_cnt =
10713 scsi_sg_q.sg_cur_list_cnt =
10718 next_qp = AscReadLramByte(iop_base,
10721 scsi_sg_q.q_no = next_qp;
10722 q_addr = ASC_QNO_TO_QADDR(next_qp);
10723 AscMemWordCopyPtrToLram(iop_base,
10724 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
10725 (uchar *)&scsi_sg_q,
10726 sizeof(ASC_SG_LIST_Q) >> 1);
10727 AscMemDWordCopyPtrToLram(iop_base,
10728 q_addr + ASC_SGQ_LIST_BEG,
10729 (uchar *)&sg_head->
10732 sg_index += ASC_SG_LIST_PER_Q;
10733 scsiq->next_sg_index = sg_index;
10736 scsiq->q1.cntl &= ~QC_SG_HEAD;
10738 sta = AscPutReadyQueue(asc_dvc, scsiq, q_no);
10739 scsiq->q1.data_addr = saved_data_addr;
10740 scsiq->q1.data_cnt = saved_data_cnt;
10745 AscSendScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar n_q_required)
10754 iop_base = asc_dvc->iop_base;
10755 target_ix = scsiq->q2.target_ix;
10756 tid_no = ASC_TIX_TO_TID(target_ix);
10758 free_q_head = (uchar)AscGetVarFreeQHead(iop_base);
10759 if (n_q_required > 1) {
10760 next_qp = AscAllocMultipleFreeQueue(iop_base, free_q_head,
10761 (uchar)n_q_required);
10762 if (next_qp != ASC_QLINK_END) {
10763 asc_dvc->last_q_shortage = 0;
10764 scsiq->sg_head->queue_cnt = n_q_required - 1;
10765 scsiq->q1.q_no = free_q_head;
10766 sta = AscPutReadySgListQueue(asc_dvc, scsiq,
10769 } else if (n_q_required == 1) {
10770 next_qp = AscAllocFreeQueue(iop_base, free_q_head);
10771 if (next_qp != ASC_QLINK_END) {
10772 scsiq->q1.q_no = free_q_head;
10773 sta = AscPutReadyQueue(asc_dvc, scsiq, free_q_head);
10777 AscPutVarFreeQHead(iop_base, next_qp);
10778 asc_dvc->cur_total_qng += n_q_required;
10779 asc_dvc->cur_dvc_qng[tid_no]++;
10784 #define ASC_SYN_OFFSET_ONE_DISABLE_LIST 16
10785 static uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] = {
10804 static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq)
10809 int disable_syn_offset_one_fix;
10812 ushort sg_entry_cnt = 0;
10813 ushort sg_entry_cnt_minus_one = 0;
10820 ASC_SG_HEAD *sg_head;
10823 iop_base = asc_dvc->iop_base;
10824 sg_head = scsiq->sg_head;
10825 if (asc_dvc->err_code != 0)
10827 scsiq->q1.q_no = 0;
10828 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) {
10829 scsiq->q1.extra_bytes = 0;
10832 target_ix = scsiq->q2.target_ix;
10833 tid_no = ASC_TIX_TO_TID(target_ix);
10835 if (scsiq->cdbptr[0] == REQUEST_SENSE) {
10836 if ((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) {
10837 asc_dvc->sdtr_done &= ~scsiq->q1.target_id;
10838 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
10839 AscMsgOutSDTR(asc_dvc,
10841 sdtr_period_tbl[(sdtr_data >> 4) &
10845 (uchar)(sdtr_data & (uchar)
10846 ASC_SYN_MAX_OFFSET));
10847 scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT);
10850 if (asc_dvc->in_critical_cnt != 0) {
10851 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CRITICAL_RE_ENTRY);
10854 asc_dvc->in_critical_cnt++;
10855 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
10856 if ((sg_entry_cnt = sg_head->entry_cnt) == 0) {
10857 asc_dvc->in_critical_cnt--;
10860 #if !CC_VERY_LONG_SG_LIST
10861 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
10862 asc_dvc->in_critical_cnt--;
10865 #endif /* !CC_VERY_LONG_SG_LIST */
10866 if (sg_entry_cnt == 1) {
10867 scsiq->q1.data_addr =
10868 (ADV_PADDR)sg_head->sg_list[0].addr;
10869 scsiq->q1.data_cnt =
10870 (ADV_DCNT)sg_head->sg_list[0].bytes;
10871 scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE);
10873 sg_entry_cnt_minus_one = sg_entry_cnt - 1;
10875 scsi_cmd = scsiq->cdbptr[0];
10876 disable_syn_offset_one_fix = FALSE;
10877 if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) &&
10878 !(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) {
10879 if (scsiq->q1.cntl & QC_SG_HEAD) {
10881 for (i = 0; i < sg_entry_cnt; i++) {
10883 (ADV_DCNT)le32_to_cpu(sg_head->sg_list[i].
10887 data_cnt = le32_to_cpu(scsiq->q1.data_cnt);
10889 if (data_cnt != 0UL) {
10890 if (data_cnt < 512UL) {
10891 disable_syn_offset_one_fix = TRUE;
10893 for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST;
10896 _syn_offset_one_disable_cmd[i];
10897 if (disable_cmd == 0xFF) {
10900 if (scsi_cmd == disable_cmd) {
10901 disable_syn_offset_one_fix =
10909 if (disable_syn_offset_one_fix) {
10910 scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG;
10911 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX |
10912 ASC_TAG_FLAG_DISABLE_DISCONNECT);
10914 scsiq->q2.tag_code &= 0x27;
10916 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
10917 if (asc_dvc->bug_fix_cntl) {
10918 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
10919 if ((scsi_cmd == READ_6) ||
10920 (scsi_cmd == READ_10)) {
10922 (ADV_PADDR)le32_to_cpu(sg_head->
10924 [sg_entry_cnt_minus_one].
10926 (ADV_DCNT)le32_to_cpu(sg_head->
10928 [sg_entry_cnt_minus_one].
10931 (uchar)((ushort)addr & 0x0003);
10932 if ((extra_bytes != 0)
10936 ASC_TAG_FLAG_EXTRA_BYTES)
10938 scsiq->q2.tag_code |=
10939 ASC_TAG_FLAG_EXTRA_BYTES;
10940 scsiq->q1.extra_bytes =
10943 le32_to_cpu(sg_head->
10945 [sg_entry_cnt_minus_one].
10948 (ASC_DCNT) extra_bytes;
10951 [sg_entry_cnt_minus_one].
10953 cpu_to_le32(data_cnt);
10958 sg_head->entry_to_copy = sg_head->entry_cnt;
10959 #if CC_VERY_LONG_SG_LIST
10961 * Set the sg_entry_cnt to the maximum possible. The rest of
10962 * the SG elements will be copied when the RISC completes the
10963 * SG elements that fit and halts.
10965 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
10966 sg_entry_cnt = ASC_MAX_SG_LIST;
10968 #endif /* CC_VERY_LONG_SG_LIST */
10969 n_q_required = AscSgListToQueue(sg_entry_cnt);
10970 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, n_q_required) >=
10971 (uint) n_q_required)
10972 || ((scsiq->q1.cntl & QC_URGENT) != 0)) {
10974 AscSendScsiQueue(asc_dvc, scsiq,
10975 n_q_required)) == 1) {
10976 asc_dvc->in_critical_cnt--;
10981 if (asc_dvc->bug_fix_cntl) {
10982 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
10983 if ((scsi_cmd == READ_6) ||
10984 (scsi_cmd == READ_10)) {
10986 le32_to_cpu(scsiq->q1.data_addr) +
10987 le32_to_cpu(scsiq->q1.data_cnt);
10989 (uchar)((ushort)addr & 0x0003);
10990 if ((extra_bytes != 0)
10994 ASC_TAG_FLAG_EXTRA_BYTES)
10997 le32_to_cpu(scsiq->q1.
10999 if (((ushort)data_cnt & 0x01FF)
11001 scsiq->q2.tag_code |=
11002 ASC_TAG_FLAG_EXTRA_BYTES;
11003 data_cnt -= (ASC_DCNT)
11005 scsiq->q1.data_cnt =
11008 scsiq->q1.extra_bytes =
11016 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, 1) >= 1) ||
11017 ((scsiq->q1.cntl & QC_URGENT) != 0)) {
11018 if ((sta = AscSendScsiQueue(asc_dvc, scsiq,
11019 n_q_required)) == 1) {
11020 asc_dvc->in_critical_cnt--;
11025 asc_dvc->in_critical_cnt--;
11030 * AdvExeScsiQueue() - Send a request to the RISC microcode program.
11032 * Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q,
11033 * add the carrier to the ICQ (Initiator Command Queue), and tickle the
11034 * RISC to notify it a new command is ready to be executed.
11036 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be
11037 * set to SCSI_MAX_RETRY.
11039 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the microcode
11040 * for DMA addresses or math operations are byte swapped to little-endian
11044 * ADV_SUCCESS(1) - The request was successfully queued.
11045 * ADV_BUSY(0) - Resource unavailable; Retry again after pending
11046 * request completes.
11047 * ADV_ERROR(-1) - Invalid ADV_SCSI_REQ_Q request structure
11050 static int AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq)
11052 AdvPortAddr iop_base;
11054 ADV_PADDR req_paddr;
11055 ADV_CARR_T *new_carrp;
11058 * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID.
11060 if (scsiq->target_id > ADV_MAX_TID) {
11061 scsiq->host_status = QHSTA_M_INVALID_DEVICE;
11062 scsiq->done_status = QD_WITH_ERROR;
11066 iop_base = asc_dvc->iop_base;
11069 * Allocate a carrier ensuring at least one carrier always
11070 * remains on the freelist and initialize fields.
11072 if ((new_carrp = asc_dvc->carr_freelist) == NULL) {
11075 asc_dvc->carr_freelist = (ADV_CARR_T *)
11076 ADV_U32_TO_VADDR(le32_to_cpu(new_carrp->next_vpa));
11077 asc_dvc->carr_pending_cnt++;
11080 * Set the carrier to be a stopper by setting 'next_vpa'
11081 * to the stopper value. The current stopper will be changed
11082 * below to point to the new stopper.
11084 new_carrp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
11087 * Clear the ADV_SCSI_REQ_Q done flag.
11089 scsiq->a_flag &= ~ADV_SCSIQ_DONE;
11091 req_size = sizeof(ADV_SCSI_REQ_Q);
11092 req_paddr = DvcGetPhyAddr(asc_dvc, scsiq, (uchar *)scsiq,
11093 (ADV_SDCNT *)&req_size, ADV_IS_SCSIQ_FLAG);
11095 BUG_ON(req_paddr & 31);
11096 BUG_ON(req_size < sizeof(ADV_SCSI_REQ_Q));
11098 /* Wait for assertion before making little-endian */
11099 req_paddr = cpu_to_le32(req_paddr);
11101 /* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */
11102 scsiq->scsiq_ptr = cpu_to_le32(ADV_VADDR_TO_U32(scsiq));
11103 scsiq->scsiq_rptr = req_paddr;
11105 scsiq->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->icq_sp));
11107 * Every ADV_CARR_T.carr_pa is byte swapped to little-endian
11108 * order during initialization.
11110 scsiq->carr_pa = asc_dvc->icq_sp->carr_pa;
11113 * Use the current stopper to send the ADV_SCSI_REQ_Q command to
11114 * the microcode. The newly allocated stopper will become the new
11117 asc_dvc->icq_sp->areq_vpa = req_paddr;
11120 * Set the 'next_vpa' pointer for the old stopper to be the
11121 * physical address of the new stopper. The RISC can only
11122 * follow physical addresses.
11124 asc_dvc->icq_sp->next_vpa = new_carrp->carr_pa;
11127 * Set the host adapter stopper pointer to point to the new carrier.
11129 asc_dvc->icq_sp = new_carrp;
11131 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
11132 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
11134 * Tickle the RISC to tell it to read its Command Queue Head pointer.
11136 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A);
11137 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
11139 * Clear the tickle value. In the ASC-3550 the RISC flag
11140 * command 'clr_tickle_a' does not work unless the host
11141 * value is cleared.
11143 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
11146 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
11148 * Notify the RISC a carrier is ready by writing the physical
11149 * address of the new carrier stopper to the COMMA register.
11151 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
11152 le32_to_cpu(new_carrp->carr_pa));
11155 return ADV_SUCCESS;
11159 * Execute a single 'Scsi_Cmnd'.
11161 * The function 'done' is called when the request has been completed.
11165 * host - board controlling device
11166 * device - device to send command
11167 * target - target of device
11168 * lun - lun of device
11169 * cmd_len - length of SCSI CDB
11170 * cmnd - buffer for SCSI 8, 10, or 12 byte CDB
11171 * use_sg - if non-zero indicates scatter-gather request with use_sg elements
11173 * if (use_sg == 0) {
11174 * request_buffer - buffer address for request
11175 * request_bufflen - length of request buffer
11177 * request_buffer - pointer to scatterlist structure
11180 * sense_buffer - sense command buffer
11182 * result (4 bytes of an int):
11184 * 0 SCSI Status Byte Code
11185 * 1 SCSI One Byte Message Code
11186 * 2 Host Error Code
11187 * 3 Mid-Level Error Code
11189 * host driver fields:
11190 * SCp - Scsi_Pointer used for command processing status
11191 * scsi_done - used to save caller's done function
11192 * host_scribble - used for pointer to another struct scsi_cmnd
11194 * If this function returns ASC_NOERROR the request will be completed
11195 * from the interrupt handler.
11197 * If this function returns ASC_ERROR the host error code has been set,
11198 * and the called must call asc_scsi_done.
11200 * If ASC_BUSY is returned the request will be returned to the midlayer
11201 * and re-tried later.
11203 static int asc_execute_scsi_cmnd(struct scsi_cmnd *scp)
11206 struct asc_board *boardp = shost_priv(scp->device->host);
11208 ASC_DBG1(1, "asc_execute_scsi_cmnd: scp 0x%p\n", scp);
11210 if (ASC_NARROW_BOARD(boardp)) {
11211 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
11212 struct asc_scsi_q asc_scsi_q;
11214 /* asc_build_req() can not return ASC_BUSY. */
11215 ret = asc_build_req(boardp, scp, &asc_scsi_q);
11216 if (ret == ASC_ERROR) {
11217 ASC_STATS(scp->device->host, build_error);
11221 ret = AscExeScsiQueue(asc_dvc, &asc_scsi_q);
11222 kfree(asc_scsi_q.sg_head);
11223 err_code = asc_dvc->err_code;
11225 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
11226 ADV_SCSI_REQ_Q *adv_scsiqp;
11228 switch (adv_build_req(boardp, scp, &adv_scsiqp)) {
11230 ASC_DBG(3, "asc_execute_scsi_cmnd: adv_build_req "
11234 ASC_DBG(1, "asc_execute_scsi_cmnd: adv_build_req "
11237 * The asc_stats fields 'adv_build_noreq' and
11238 * 'adv_build_nosg' count wide board busy conditions.
11239 * They are updated in adv_build_req and
11240 * adv_get_sglist, respectively.
11245 ASC_DBG(1, "asc_execute_scsi_cmnd: adv_build_req "
11247 ASC_STATS(scp->device->host, build_error);
11251 ret = AdvExeScsiQueue(adv_dvc, adv_scsiqp);
11252 err_code = adv_dvc->err_code;
11257 ASC_STATS(scp->device->host, exe_noerror);
11259 * Increment monotonically increasing per device
11260 * successful request counter. Wrapping doesn't matter.
11262 boardp->reqcnt[scp->device->id]++;
11263 ASC_DBG(1, "asc_execute_scsi_cmnd: ExeScsiQueue(), "
11267 ASC_STATS(scp->device->host, exe_busy);
11270 ASC_PRINT2("asc_execute_scsi_cmnd: board %d: ExeScsiQueue() "
11271 "ASC_ERROR, err_code 0x%x\n", boardp->id, err_code);
11272 ASC_STATS(scp->device->host, exe_error);
11273 scp->result = HOST_BYTE(DID_ERROR);
11276 ASC_PRINT2("asc_execute_scsi_cmnd: board %d: ExeScsiQueue() "
11277 "unknown, err_code 0x%x\n", boardp->id, err_code);
11278 ASC_STATS(scp->device->host, exe_unknown);
11279 scp->result = HOST_BYTE(DID_ERROR);
11283 ASC_DBG(1, "asc_execute_scsi_cmnd: end\n");
11288 * advansys_queuecommand() - interrupt-driven I/O entrypoint.
11290 * This function always returns 0. Command return status is saved
11291 * in the 'scp' result field.
11294 advansys_queuecommand(struct scsi_cmnd *scp, void (*done)(struct scsi_cmnd *))
11296 struct Scsi_Host *shost = scp->device->host;
11297 struct asc_board *boardp = shost_priv(shost);
11298 unsigned long flags;
11299 int asc_res, result = 0;
11301 ASC_STATS(shost, queuecommand);
11302 scp->scsi_done = done;
11305 * host_lock taken by mid-level prior to call, but need
11306 * to protect against own ISR
11308 spin_lock_irqsave(&boardp->lock, flags);
11309 asc_res = asc_execute_scsi_cmnd(scp);
11310 spin_unlock_irqrestore(&boardp->lock, flags);
11316 result = SCSI_MLQUEUE_HOST_BUSY;
11320 asc_scsi_done(scp);
11327 static ushort __devinit AscGetEisaChipCfg(PortAddr iop_base)
11329 PortAddr eisa_cfg_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
11330 (PortAddr) (ASC_EISA_CFG_IOP_MASK);
11331 return inpw(eisa_cfg_iop);
11335 * Return the BIOS address of the adapter at the specified
11336 * I/O port and with the specified bus type.
11338 static unsigned short __devinit
11339 AscGetChipBiosAddress(PortAddr iop_base, unsigned short bus_type)
11341 unsigned short cfg_lsw;
11342 unsigned short bios_addr;
11345 * The PCI BIOS is re-located by the motherboard BIOS. Because
11346 * of this the driver can not determine where a PCI BIOS is
11347 * loaded and executes.
11349 if (bus_type & ASC_IS_PCI)
11352 if ((bus_type & ASC_IS_EISA) != 0) {
11353 cfg_lsw = AscGetEisaChipCfg(iop_base);
11355 bios_addr = ASC_BIOS_MIN_ADDR + cfg_lsw * ASC_BIOS_BANK_SIZE;
11359 cfg_lsw = AscGetChipCfgLsw(iop_base);
11362 * ISA PnP uses the top bit as the 32K BIOS flag
11364 if (bus_type == ASC_IS_ISAPNP)
11366 bios_addr = ASC_BIOS_MIN_ADDR + (cfg_lsw >> 12) * ASC_BIOS_BANK_SIZE;
11370 static uchar __devinit AscSetChipScsiID(PortAddr iop_base, uchar new_host_id)
11374 if (AscGetChipScsiID(iop_base) == new_host_id) {
11375 return (new_host_id);
11377 cfg_lsw = AscGetChipCfgLsw(iop_base);
11379 cfg_lsw |= (ushort)((new_host_id & ASC_MAX_TID) << 8);
11380 AscSetChipCfgLsw(iop_base, cfg_lsw);
11381 return (AscGetChipScsiID(iop_base));
11384 static unsigned char __devinit AscGetChipScsiCtrl(PortAddr iop_base)
11388 AscSetBank(iop_base, 1);
11389 sc = inp(iop_base + IOP_REG_SC);
11390 AscSetBank(iop_base, 0);
11394 static unsigned char __devinit
11395 AscGetChipVersion(PortAddr iop_base, unsigned short bus_type)
11397 if (bus_type & ASC_IS_EISA) {
11399 unsigned char revision;
11400 eisa_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
11401 (PortAddr) ASC_EISA_REV_IOP_MASK;
11402 revision = inp(eisa_iop);
11403 return ASC_CHIP_MIN_VER_EISA - 1 + revision;
11405 return AscGetChipVerNo(iop_base);
11409 static void __devinit AscEnableIsaDma(uchar dma_channel)
11411 if (dma_channel < 4) {
11412 outp(0x000B, (ushort)(0xC0 | dma_channel));
11413 outp(0x000A, dma_channel);
11414 } else if (dma_channel < 8) {
11415 outp(0x00D6, (ushort)(0xC0 | (dma_channel - 4)));
11416 outp(0x00D4, (ushort)(dma_channel - 4));
11420 #endif /* CONFIG_ISA */
11422 static int AscStopQueueExe(PortAddr iop_base)
11426 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) == 0) {
11427 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
11428 ASC_STOP_REQ_RISC_STOP);
11430 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) &
11431 ASC_STOP_ACK_RISC_STOP) {
11435 } while (count++ < 20);
11440 static ASC_DCNT __devinit AscGetMaxDmaCount(ushort bus_type)
11442 if (bus_type & ASC_IS_ISA)
11443 return ASC_MAX_ISA_DMA_COUNT;
11444 else if (bus_type & (ASC_IS_EISA | ASC_IS_VL))
11445 return ASC_MAX_VL_DMA_COUNT;
11446 return ASC_MAX_PCI_DMA_COUNT;
11450 static ushort __devinit AscGetIsaDmaChannel(PortAddr iop_base)
11454 channel = AscGetChipCfgLsw(iop_base) & 0x0003;
11455 if (channel == 0x03)
11457 else if (channel == 0x00)
11459 return (channel + 4);
11462 static ushort __devinit AscSetIsaDmaChannel(PortAddr iop_base, ushort dma_channel)
11467 if ((dma_channel >= 5) && (dma_channel <= 7)) {
11468 if (dma_channel == 7)
11471 value = dma_channel - 4;
11472 cfg_lsw = AscGetChipCfgLsw(iop_base) & 0xFFFC;
11474 AscSetChipCfgLsw(iop_base, cfg_lsw);
11475 return (AscGetIsaDmaChannel(iop_base));
11480 static uchar __devinit AscGetIsaDmaSpeed(PortAddr iop_base)
11484 AscSetBank(iop_base, 1);
11485 speed_value = AscReadChipDmaSpeed(iop_base);
11486 speed_value &= 0x07;
11487 AscSetBank(iop_base, 0);
11488 return speed_value;
11491 static uchar __devinit AscSetIsaDmaSpeed(PortAddr iop_base, uchar speed_value)
11493 speed_value &= 0x07;
11494 AscSetBank(iop_base, 1);
11495 AscWriteChipDmaSpeed(iop_base, speed_value);
11496 AscSetBank(iop_base, 0);
11497 return AscGetIsaDmaSpeed(iop_base);
11499 #endif /* CONFIG_ISA */
11501 static ushort __devinit AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc)
11506 uchar chip_version;
11508 iop_base = asc_dvc->iop_base;
11510 asc_dvc->err_code = 0;
11511 if ((asc_dvc->bus_type &
11512 (ASC_IS_ISA | ASC_IS_PCI | ASC_IS_EISA | ASC_IS_VL)) == 0) {
11513 asc_dvc->err_code |= ASC_IERR_NO_BUS_TYPE;
11515 AscSetChipControl(iop_base, CC_HALT);
11516 AscSetChipStatus(iop_base, 0);
11517 asc_dvc->bug_fix_cntl = 0;
11518 asc_dvc->pci_fix_asyn_xfer = 0;
11519 asc_dvc->pci_fix_asyn_xfer_always = 0;
11520 /* asc_dvc->init_state initalized in AscInitGetConfig(). */
11521 asc_dvc->sdtr_done = 0;
11522 asc_dvc->cur_total_qng = 0;
11523 asc_dvc->is_in_int = 0;
11524 asc_dvc->in_critical_cnt = 0;
11525 asc_dvc->last_q_shortage = 0;
11526 asc_dvc->use_tagged_qng = 0;
11527 asc_dvc->no_scam = 0;
11528 asc_dvc->unit_not_ready = 0;
11529 asc_dvc->queue_full_or_busy = 0;
11530 asc_dvc->redo_scam = 0;
11532 asc_dvc->host_init_sdtr_index = 0;
11533 asc_dvc->cfg->can_tagged_qng = 0;
11534 asc_dvc->cfg->cmd_qng_enabled = 0;
11535 asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL;
11536 asc_dvc->init_sdtr = 0;
11537 asc_dvc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG;
11538 asc_dvc->scsi_reset_wait = 3;
11539 asc_dvc->start_motor = ASC_SCSI_WIDTH_BIT_SET;
11540 asc_dvc->max_dma_count = AscGetMaxDmaCount(asc_dvc->bus_type);
11541 asc_dvc->cfg->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET;
11542 asc_dvc->cfg->disc_enable = ASC_SCSI_WIDTH_BIT_SET;
11543 asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID;
11544 chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type);
11545 asc_dvc->cfg->chip_version = chip_version;
11546 asc_dvc->sdtr_period_tbl[0] = SYN_XFER_NS_0;
11547 asc_dvc->sdtr_period_tbl[1] = SYN_XFER_NS_1;
11548 asc_dvc->sdtr_period_tbl[2] = SYN_XFER_NS_2;
11549 asc_dvc->sdtr_period_tbl[3] = SYN_XFER_NS_3;
11550 asc_dvc->sdtr_period_tbl[4] = SYN_XFER_NS_4;
11551 asc_dvc->sdtr_period_tbl[5] = SYN_XFER_NS_5;
11552 asc_dvc->sdtr_period_tbl[6] = SYN_XFER_NS_6;
11553 asc_dvc->sdtr_period_tbl[7] = SYN_XFER_NS_7;
11554 asc_dvc->max_sdtr_index = 7;
11555 if ((asc_dvc->bus_type & ASC_IS_PCI) &&
11556 (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) {
11557 asc_dvc->bus_type = ASC_IS_PCI_ULTRA;
11558 asc_dvc->sdtr_period_tbl[0] = SYN_ULTRA_XFER_NS_0;
11559 asc_dvc->sdtr_period_tbl[1] = SYN_ULTRA_XFER_NS_1;
11560 asc_dvc->sdtr_period_tbl[2] = SYN_ULTRA_XFER_NS_2;
11561 asc_dvc->sdtr_period_tbl[3] = SYN_ULTRA_XFER_NS_3;
11562 asc_dvc->sdtr_period_tbl[4] = SYN_ULTRA_XFER_NS_4;
11563 asc_dvc->sdtr_period_tbl[5] = SYN_ULTRA_XFER_NS_5;
11564 asc_dvc->sdtr_period_tbl[6] = SYN_ULTRA_XFER_NS_6;
11565 asc_dvc->sdtr_period_tbl[7] = SYN_ULTRA_XFER_NS_7;
11566 asc_dvc->sdtr_period_tbl[8] = SYN_ULTRA_XFER_NS_8;
11567 asc_dvc->sdtr_period_tbl[9] = SYN_ULTRA_XFER_NS_9;
11568 asc_dvc->sdtr_period_tbl[10] = SYN_ULTRA_XFER_NS_10;
11569 asc_dvc->sdtr_period_tbl[11] = SYN_ULTRA_XFER_NS_11;
11570 asc_dvc->sdtr_period_tbl[12] = SYN_ULTRA_XFER_NS_12;
11571 asc_dvc->sdtr_period_tbl[13] = SYN_ULTRA_XFER_NS_13;
11572 asc_dvc->sdtr_period_tbl[14] = SYN_ULTRA_XFER_NS_14;
11573 asc_dvc->sdtr_period_tbl[15] = SYN_ULTRA_XFER_NS_15;
11574 asc_dvc->max_sdtr_index = 15;
11575 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) {
11576 AscSetExtraControl(iop_base,
11577 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
11578 } else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) {
11579 AscSetExtraControl(iop_base,
11580 (SEC_ACTIVE_NEGATE |
11581 SEC_ENABLE_FILTER));
11584 if (asc_dvc->bus_type == ASC_IS_PCI) {
11585 AscSetExtraControl(iop_base,
11586 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
11589 asc_dvc->cfg->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED;
11591 if ((asc_dvc->bus_type & ASC_IS_ISA) != 0) {
11592 if (chip_version >= ASC_CHIP_MIN_VER_ISA_PNP) {
11593 AscSetChipIFC(iop_base, IFC_INIT_DEFAULT);
11594 asc_dvc->bus_type = ASC_IS_ISAPNP;
11596 asc_dvc->cfg->isa_dma_channel =
11597 (uchar)AscGetIsaDmaChannel(iop_base);
11599 #endif /* CONFIG_ISA */
11600 for (i = 0; i <= ASC_MAX_TID; i++) {
11601 asc_dvc->cur_dvc_qng[i] = 0;
11602 asc_dvc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG;
11603 asc_dvc->scsiq_busy_head[i] = (ASC_SCSI_Q *)0L;
11604 asc_dvc->scsiq_busy_tail[i] = (ASC_SCSI_Q *)0L;
11605 asc_dvc->cfg->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG;
11610 static int __devinit AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg)
11614 for (retry = 0; retry < ASC_EEP_MAX_RETRY; retry++) {
11615 unsigned char read_back;
11616 AscSetChipEEPCmd(iop_base, cmd_reg);
11618 read_back = AscGetChipEEPCmd(iop_base);
11619 if (read_back == cmd_reg)
11625 static void __devinit AscWaitEEPRead(void)
11630 static ushort __devinit AscReadEEPWord(PortAddr iop_base, uchar addr)
11635 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
11637 cmd_reg = addr | ASC_EEP_CMD_READ;
11638 AscWriteEEPCmdReg(iop_base, cmd_reg);
11640 read_wval = AscGetChipEEPData(iop_base);
11645 static ushort __devinit
11646 AscGetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type)
11653 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
11656 wbuf = (ushort *)cfg_buf;
11658 /* Read two config words; Byte-swapping done by AscReadEEPWord(). */
11659 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
11660 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
11663 if (bus_type & ASC_IS_VL) {
11664 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
11665 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
11667 cfg_beg = ASC_EEP_DVC_CFG_BEG;
11668 cfg_end = ASC_EEP_MAX_DVC_ADDR;
11670 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
11671 wval = AscReadEEPWord(iop_base, (uchar)s_addr);
11672 if (s_addr <= uchar_end_in_config) {
11674 * Swap all char fields - must unswap bytes already swapped
11675 * by AscReadEEPWord().
11677 *wbuf = le16_to_cpu(wval);
11679 /* Don't swap word field at the end - cntl field. */
11682 sum += wval; /* Checksum treats all EEPROM data as words. */
11685 * Read the checksum word which will be compared against 'sum'
11686 * by the caller. Word field already swapped.
11688 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
11692 static int __devinit AscTestExternalLram(ASC_DVC_VAR *asc_dvc)
11699 iop_base = asc_dvc->iop_base;
11701 q_addr = ASC_QNO_TO_QADDR(241);
11702 saved_word = AscReadLramWord(iop_base, q_addr);
11703 AscSetChipLramAddr(iop_base, q_addr);
11704 AscSetChipLramData(iop_base, 0x55AA);
11706 AscSetChipLramAddr(iop_base, q_addr);
11707 if (AscGetChipLramData(iop_base) == 0x55AA) {
11709 AscWriteLramWord(iop_base, q_addr, saved_word);
11714 static void __devinit AscWaitEEPWrite(void)
11720 static int __devinit AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg)
11727 AscSetChipEEPData(iop_base, data_reg);
11729 read_back = AscGetChipEEPData(iop_base);
11730 if (read_back == data_reg) {
11733 if (retry++ > ASC_EEP_MAX_RETRY) {
11739 static ushort __devinit
11740 AscWriteEEPWord(PortAddr iop_base, uchar addr, ushort word_val)
11744 read_wval = AscReadEEPWord(iop_base, addr);
11745 if (read_wval != word_val) {
11746 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_ABLE);
11748 AscWriteEEPDataReg(iop_base, word_val);
11750 AscWriteEEPCmdReg(iop_base,
11751 (uchar)((uchar)ASC_EEP_CMD_WRITE | addr));
11753 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
11755 return (AscReadEEPWord(iop_base, addr));
11757 return (read_wval);
11760 static int __devinit
11761 AscSetEEPConfigOnce(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type)
11770 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
11772 wbuf = (ushort *)cfg_buf;
11775 /* Write two config words; AscWriteEEPWord() will swap bytes. */
11776 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
11778 if (*wbuf != AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
11782 if (bus_type & ASC_IS_VL) {
11783 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
11784 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
11786 cfg_beg = ASC_EEP_DVC_CFG_BEG;
11787 cfg_end = ASC_EEP_MAX_DVC_ADDR;
11789 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
11790 if (s_addr <= uchar_end_in_config) {
11792 * This is a char field. Swap char fields before they are
11793 * swapped again by AscWriteEEPWord().
11795 word = cpu_to_le16(*wbuf);
11797 AscWriteEEPWord(iop_base, (uchar)s_addr, word)) {
11801 /* Don't swap word field at the end - cntl field. */
11803 AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
11807 sum += *wbuf; /* Checksum calculated from word values. */
11809 /* Write checksum word. It will be swapped by AscWriteEEPWord(). */
11811 if (sum != AscWriteEEPWord(iop_base, (uchar)s_addr, sum)) {
11815 /* Read EEPROM back again. */
11816 wbuf = (ushort *)cfg_buf;
11818 * Read two config words; Byte-swapping done by AscReadEEPWord().
11820 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
11821 if (*wbuf != AscReadEEPWord(iop_base, (uchar)s_addr)) {
11825 if (bus_type & ASC_IS_VL) {
11826 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
11827 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
11829 cfg_beg = ASC_EEP_DVC_CFG_BEG;
11830 cfg_end = ASC_EEP_MAX_DVC_ADDR;
11832 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
11833 if (s_addr <= uchar_end_in_config) {
11835 * Swap all char fields. Must unswap bytes already swapped
11836 * by AscReadEEPWord().
11839 le16_to_cpu(AscReadEEPWord
11840 (iop_base, (uchar)s_addr));
11842 /* Don't swap word field at the end - cntl field. */
11843 word = AscReadEEPWord(iop_base, (uchar)s_addr);
11845 if (*wbuf != word) {
11849 /* Read checksum; Byte swapping not needed. */
11850 if (AscReadEEPWord(iop_base, (uchar)s_addr) != sum) {
11856 static int __devinit
11857 AscSetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type)
11864 if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf,
11868 if (++retry > ASC_EEP_MAX_RETRY) {
11875 static ushort __devinit AscInitFromEEP(ASC_DVC_VAR *asc_dvc)
11877 ASCEEP_CONFIG eep_config_buf;
11878 ASCEEP_CONFIG *eep_config;
11882 ushort cfg_msw, cfg_lsw;
11886 iop_base = asc_dvc->iop_base;
11888 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE);
11889 AscStopQueueExe(iop_base);
11890 if ((AscStopChip(iop_base) == FALSE) ||
11891 (AscGetChipScsiCtrl(iop_base) != 0)) {
11892 asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE;
11893 AscResetChipAndScsiBus(asc_dvc);
11894 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
11896 if (AscIsChipHalted(iop_base) == FALSE) {
11897 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
11898 return (warn_code);
11900 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
11901 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
11902 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
11903 return (warn_code);
11905 eep_config = (ASCEEP_CONFIG *)&eep_config_buf;
11906 cfg_msw = AscGetChipCfgMsw(iop_base);
11907 cfg_lsw = AscGetChipCfgLsw(iop_base);
11908 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
11909 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
11910 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
11911 AscSetChipCfgMsw(iop_base, cfg_msw);
11913 chksum = AscGetEEPConfig(iop_base, eep_config, asc_dvc->bus_type);
11914 ASC_DBG1(1, "AscInitFromEEP: chksum 0x%x\n", chksum);
11918 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
11919 warn_code |= ASC_WARN_AUTO_CONFIG;
11920 if (asc_dvc->cfg->chip_version == 3) {
11921 if (eep_config->cfg_lsw != cfg_lsw) {
11922 warn_code |= ASC_WARN_EEPROM_RECOVER;
11923 eep_config->cfg_lsw =
11924 AscGetChipCfgLsw(iop_base);
11926 if (eep_config->cfg_msw != cfg_msw) {
11927 warn_code |= ASC_WARN_EEPROM_RECOVER;
11928 eep_config->cfg_msw =
11929 AscGetChipCfgMsw(iop_base);
11933 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
11934 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON;
11935 ASC_DBG1(1, "AscInitFromEEP: eep_config->chksum 0x%x\n",
11936 eep_config->chksum);
11937 if (chksum != eep_config->chksum) {
11938 if (AscGetChipVersion(iop_base, asc_dvc->bus_type) ==
11939 ASC_CHIP_VER_PCI_ULTRA_3050) {
11941 "AscInitFromEEP: chksum error ignored; EEPROM-less board\n");
11942 eep_config->init_sdtr = 0xFF;
11943 eep_config->disc_enable = 0xFF;
11944 eep_config->start_motor = 0xFF;
11945 eep_config->use_cmd_qng = 0;
11946 eep_config->max_total_qng = 0xF0;
11947 eep_config->max_tag_qng = 0x20;
11948 eep_config->cntl = 0xBFFF;
11949 ASC_EEP_SET_CHIP_ID(eep_config, 7);
11950 eep_config->no_scam = 0;
11951 eep_config->adapter_info[0] = 0;
11952 eep_config->adapter_info[1] = 0;
11953 eep_config->adapter_info[2] = 0;
11954 eep_config->adapter_info[3] = 0;
11955 eep_config->adapter_info[4] = 0;
11956 /* Indicate EEPROM-less board. */
11957 eep_config->adapter_info[5] = 0xBB;
11960 ("AscInitFromEEP: EEPROM checksum error; Will try to re-write EEPROM.\n");
11962 warn_code |= ASC_WARN_EEPROM_CHKSUM;
11965 asc_dvc->cfg->sdtr_enable = eep_config->init_sdtr;
11966 asc_dvc->cfg->disc_enable = eep_config->disc_enable;
11967 asc_dvc->cfg->cmd_qng_enabled = eep_config->use_cmd_qng;
11968 asc_dvc->cfg->isa_dma_speed = ASC_EEP_GET_DMA_SPD(eep_config);
11969 asc_dvc->start_motor = eep_config->start_motor;
11970 asc_dvc->dvc_cntl = eep_config->cntl;
11971 asc_dvc->no_scam = eep_config->no_scam;
11972 asc_dvc->cfg->adapter_info[0] = eep_config->adapter_info[0];
11973 asc_dvc->cfg->adapter_info[1] = eep_config->adapter_info[1];
11974 asc_dvc->cfg->adapter_info[2] = eep_config->adapter_info[2];
11975 asc_dvc->cfg->adapter_info[3] = eep_config->adapter_info[3];
11976 asc_dvc->cfg->adapter_info[4] = eep_config->adapter_info[4];
11977 asc_dvc->cfg->adapter_info[5] = eep_config->adapter_info[5];
11978 if (!AscTestExternalLram(asc_dvc)) {
11979 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) ==
11980 ASC_IS_PCI_ULTRA)) {
11981 eep_config->max_total_qng =
11982 ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
11983 eep_config->max_tag_qng =
11984 ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG;
11986 eep_config->cfg_msw |= 0x0800;
11988 AscSetChipCfgMsw(iop_base, cfg_msw);
11989 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG;
11990 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG;
11994 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) {
11995 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG;
11997 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) {
11998 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG;
12000 if (eep_config->max_tag_qng > eep_config->max_total_qng) {
12001 eep_config->max_tag_qng = eep_config->max_total_qng;
12003 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) {
12004 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC;
12006 asc_dvc->max_total_qng = eep_config->max_total_qng;
12007 if ((eep_config->use_cmd_qng & eep_config->disc_enable) !=
12008 eep_config->use_cmd_qng) {
12009 eep_config->disc_enable = eep_config->use_cmd_qng;
12010 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
12012 ASC_EEP_SET_CHIP_ID(eep_config,
12013 ASC_EEP_GET_CHIP_ID(eep_config) & ASC_MAX_TID);
12014 asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config);
12015 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) &&
12016 !(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) {
12017 asc_dvc->host_init_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX;
12020 for (i = 0; i <= ASC_MAX_TID; i++) {
12021 asc_dvc->dos_int13_table[i] = eep_config->dos_int13_table[i];
12022 asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng;
12023 asc_dvc->cfg->sdtr_period_offset[i] =
12024 (uchar)(ASC_DEF_SDTR_OFFSET |
12025 (asc_dvc->host_init_sdtr_index << 4));
12027 eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
12029 if ((i = AscSetEEPConfig(iop_base, eep_config,
12030 asc_dvc->bus_type)) != 0) {
12032 ("AscInitFromEEP: Failed to re-write EEPROM with %d errors.\n",
12036 ("AscInitFromEEP: Successfully re-wrote EEPROM.\n");
12039 return (warn_code);
12042 static int __devinit AscInitGetConfig(struct asc_board *boardp)
12044 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
12045 unsigned short warn_code = 0;
12047 asc_dvc->init_state = ASC_INIT_STATE_BEG_GET_CFG;
12048 if (asc_dvc->err_code != 0)
12049 return asc_dvc->err_code;
12051 if (AscFindSignature(asc_dvc->iop_base)) {
12052 warn_code |= AscInitAscDvcVar(asc_dvc);
12053 warn_code |= AscInitFromEEP(asc_dvc);
12054 asc_dvc->init_state |= ASC_INIT_STATE_END_GET_CFG;
12055 if (asc_dvc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT)
12056 asc_dvc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
12058 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
12061 switch (warn_code) {
12062 case 0: /* No error */
12064 case ASC_WARN_IO_PORT_ROTATE:
12065 ASC_PRINT1("AscInitGetConfig: board %d: I/O port address "
12066 "modified\n", boardp->id);
12068 case ASC_WARN_AUTO_CONFIG:
12069 ASC_PRINT1("AscInitGetConfig: board %d: I/O port increment "
12070 "switch enabled\n", boardp->id);
12072 case ASC_WARN_EEPROM_CHKSUM:
12073 ASC_PRINT1("AscInitGetConfig: board %d: EEPROM checksum "
12074 "error\n", boardp->id);
12076 case ASC_WARN_IRQ_MODIFIED:
12077 ASC_PRINT1("AscInitGetConfig: board %d: IRQ modified\n",
12080 case ASC_WARN_CMD_QNG_CONFLICT:
12081 ASC_PRINT1("AscInitGetConfig: board %d: tag queuing enabled "
12082 "w/o disconnects\n", boardp->id);
12085 ASC_PRINT2("AscInitGetConfig: board %d: unknown warning: "
12086 "0x%x\n", boardp->id, warn_code);
12090 if (asc_dvc->err_code != 0) {
12091 ASC_PRINT3("AscInitGetConfig: board %d error: init_state 0x%x, "
12092 "err_code 0x%x\n", boardp->id, asc_dvc->init_state,
12093 asc_dvc->err_code);
12096 return asc_dvc->err_code;
12099 static int __devinit AscInitSetConfig(struct pci_dev *pdev, struct asc_board *boardp)
12101 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
12102 PortAddr iop_base = asc_dvc->iop_base;
12103 unsigned short cfg_msw;
12104 unsigned short warn_code = 0;
12106 asc_dvc->init_state |= ASC_INIT_STATE_BEG_SET_CFG;
12107 if (asc_dvc->err_code != 0)
12108 return asc_dvc->err_code;
12109 if (!AscFindSignature(asc_dvc->iop_base)) {
12110 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
12111 return asc_dvc->err_code;
12114 cfg_msw = AscGetChipCfgMsw(iop_base);
12115 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
12116 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
12117 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
12118 AscSetChipCfgMsw(iop_base, cfg_msw);
12120 if ((asc_dvc->cfg->cmd_qng_enabled & asc_dvc->cfg->disc_enable) !=
12121 asc_dvc->cfg->cmd_qng_enabled) {
12122 asc_dvc->cfg->disc_enable = asc_dvc->cfg->cmd_qng_enabled;
12123 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
12125 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
12126 warn_code |= ASC_WARN_AUTO_CONFIG;
12129 if (asc_dvc->bus_type & ASC_IS_PCI) {
12131 AscSetChipCfgMsw(iop_base, cfg_msw);
12132 if ((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) {
12134 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
12135 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
12136 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB;
12137 asc_dvc->bug_fix_cntl |=
12138 ASC_BUG_FIX_ASYN_USE_SYN;
12142 #endif /* CONFIG_PCI */
12143 if (asc_dvc->bus_type == ASC_IS_ISAPNP) {
12144 if (AscGetChipVersion(iop_base, asc_dvc->bus_type)
12145 == ASC_CHIP_VER_ASYN_BUG) {
12146 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
12149 if (AscSetChipScsiID(iop_base, asc_dvc->cfg->chip_scsi_id) !=
12150 asc_dvc->cfg->chip_scsi_id) {
12151 asc_dvc->err_code |= ASC_IERR_SET_SCSI_ID;
12154 if (asc_dvc->bus_type & ASC_IS_ISA) {
12155 AscSetIsaDmaChannel(iop_base, asc_dvc->cfg->isa_dma_channel);
12156 AscSetIsaDmaSpeed(iop_base, asc_dvc->cfg->isa_dma_speed);
12158 #endif /* CONFIG_ISA */
12160 asc_dvc->init_state |= ASC_INIT_STATE_END_SET_CFG;
12162 switch (warn_code) {
12163 case 0: /* No error. */
12165 case ASC_WARN_IO_PORT_ROTATE:
12166 ASC_PRINT1("AscInitSetConfig: board %d: I/O port address "
12167 "modified\n", boardp->id);
12169 case ASC_WARN_AUTO_CONFIG:
12170 ASC_PRINT1("AscInitSetConfig: board %d: I/O port increment "
12171 "switch enabled\n", boardp->id);
12173 case ASC_WARN_EEPROM_CHKSUM:
12174 ASC_PRINT1("AscInitSetConfig: board %d: EEPROM checksum "
12175 "error\n", boardp->id);
12177 case ASC_WARN_IRQ_MODIFIED:
12178 ASC_PRINT1("AscInitSetConfig: board %d: IRQ modified\n",
12181 case ASC_WARN_CMD_QNG_CONFLICT:
12182 ASC_PRINT1("AscInitSetConfig: board %d: tag queuing w/o "
12187 ASC_PRINT2("AscInitSetConfig: board %d: unknown warning: "
12188 "0x%x\n", boardp->id, warn_code);
12192 if (asc_dvc->err_code != 0) {
12193 ASC_PRINT3("AscInitSetConfig: board %d error: init_state 0x%x, "
12194 "err_code 0x%x\n", boardp->id, asc_dvc->init_state,
12195 asc_dvc->err_code);
12198 return asc_dvc->err_code;
12202 * EEPROM Configuration.
12204 * All drivers should use this structure to set the default EEPROM
12205 * configuration. The BIOS now uses this structure when it is built.
12206 * Additional structure information can be found in a_condor.h where
12207 * the structure is defined.
12209 * The *_Field_IsChar structs are needed to correct for endianness.
12210 * These values are read from the board 16 bits at a time directly
12211 * into the structs. Because some fields are char, the values will be
12212 * in the wrong order. The *_Field_IsChar tells when to flip the
12213 * bytes. Data read and written to PCI memory is automatically swapped
12214 * on big-endian platforms so char fields read as words are actually being
12215 * unswapped on big-endian platforms.
12217 static ADVEEP_3550_CONFIG Default_3550_EEPROM_Config __devinitdata = {
12218 ADV_EEPROM_BIOS_ENABLE, /* cfg_lsw */
12219 0x0000, /* cfg_msw */
12220 0xFFFF, /* disc_enable */
12221 0xFFFF, /* wdtr_able */
12222 0xFFFF, /* sdtr_able */
12223 0xFFFF, /* start_motor */
12224 0xFFFF, /* tagqng_able */
12225 0xFFFF, /* bios_scan */
12226 0, /* scam_tolerant */
12227 7, /* adapter_scsi_id */
12228 0, /* bios_boot_delay */
12229 3, /* scsi_reset_delay */
12230 0, /* bios_id_lun */
12231 0, /* termination */
12233 0xFFE7, /* bios_ctrl */
12234 0xFFFF, /* ultra_able */
12236 ASC_DEF_MAX_HOST_QNG, /* max_host_qng */
12237 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
12240 0, /* serial_number_word1 */
12241 0, /* serial_number_word2 */
12242 0, /* serial_number_word3 */
12244 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
12245 , /* oem_name[16] */
12246 0, /* dvc_err_code */
12247 0, /* adv_err_code */
12248 0, /* adv_err_addr */
12249 0, /* saved_dvc_err_code */
12250 0, /* saved_adv_err_code */
12251 0, /* saved_adv_err_addr */
12255 static ADVEEP_3550_CONFIG ADVEEP_3550_Config_Field_IsChar __devinitdata = {
12258 0, /* -disc_enable */
12261 0, /* start_motor */
12262 0, /* tagqng_able */
12264 0, /* scam_tolerant */
12265 1, /* adapter_scsi_id */
12266 1, /* bios_boot_delay */
12267 1, /* scsi_reset_delay */
12268 1, /* bios_id_lun */
12269 1, /* termination */
12272 0, /* ultra_able */
12274 1, /* max_host_qng */
12275 1, /* max_dvc_qng */
12278 0, /* serial_number_word1 */
12279 0, /* serial_number_word2 */
12280 0, /* serial_number_word3 */
12282 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
12283 , /* oem_name[16] */
12284 0, /* dvc_err_code */
12285 0, /* adv_err_code */
12286 0, /* adv_err_addr */
12287 0, /* saved_dvc_err_code */
12288 0, /* saved_adv_err_code */
12289 0, /* saved_adv_err_addr */
12293 static ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config __devinitdata = {
12294 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
12295 0x0000, /* 01 cfg_msw */
12296 0xFFFF, /* 02 disc_enable */
12297 0xFFFF, /* 03 wdtr_able */
12298 0x4444, /* 04 sdtr_speed1 */
12299 0xFFFF, /* 05 start_motor */
12300 0xFFFF, /* 06 tagqng_able */
12301 0xFFFF, /* 07 bios_scan */
12302 0, /* 08 scam_tolerant */
12303 7, /* 09 adapter_scsi_id */
12304 0, /* bios_boot_delay */
12305 3, /* 10 scsi_reset_delay */
12306 0, /* bios_id_lun */
12307 0, /* 11 termination_se */
12308 0, /* termination_lvd */
12309 0xFFE7, /* 12 bios_ctrl */
12310 0x4444, /* 13 sdtr_speed2 */
12311 0x4444, /* 14 sdtr_speed3 */
12312 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
12313 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
12314 0, /* 16 dvc_cntl */
12315 0x4444, /* 17 sdtr_speed4 */
12316 0, /* 18 serial_number_word1 */
12317 0, /* 19 serial_number_word2 */
12318 0, /* 20 serial_number_word3 */
12319 0, /* 21 check_sum */
12320 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
12321 , /* 22-29 oem_name[16] */
12322 0, /* 30 dvc_err_code */
12323 0, /* 31 adv_err_code */
12324 0, /* 32 adv_err_addr */
12325 0, /* 33 saved_dvc_err_code */
12326 0, /* 34 saved_adv_err_code */
12327 0, /* 35 saved_adv_err_addr */
12328 0, /* 36 reserved */
12329 0, /* 37 reserved */
12330 0, /* 38 reserved */
12331 0, /* 39 reserved */
12332 0, /* 40 reserved */
12333 0, /* 41 reserved */
12334 0, /* 42 reserved */
12335 0, /* 43 reserved */
12336 0, /* 44 reserved */
12337 0, /* 45 reserved */
12338 0, /* 46 reserved */
12339 0, /* 47 reserved */
12340 0, /* 48 reserved */
12341 0, /* 49 reserved */
12342 0, /* 50 reserved */
12343 0, /* 51 reserved */
12344 0, /* 52 reserved */
12345 0, /* 53 reserved */
12346 0, /* 54 reserved */
12347 0, /* 55 reserved */
12348 0, /* 56 cisptr_lsw */
12349 0, /* 57 cisprt_msw */
12350 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
12351 PCI_DEVICE_ID_38C0800_REV1, /* 59 subsysid */
12352 0, /* 60 reserved */
12353 0, /* 61 reserved */
12354 0, /* 62 reserved */
12355 0 /* 63 reserved */
12358 static ADVEEP_38C0800_CONFIG ADVEEP_38C0800_Config_Field_IsChar __devinitdata = {
12359 0, /* 00 cfg_lsw */
12360 0, /* 01 cfg_msw */
12361 0, /* 02 disc_enable */
12362 0, /* 03 wdtr_able */
12363 0, /* 04 sdtr_speed1 */
12364 0, /* 05 start_motor */
12365 0, /* 06 tagqng_able */
12366 0, /* 07 bios_scan */
12367 0, /* 08 scam_tolerant */
12368 1, /* 09 adapter_scsi_id */
12369 1, /* bios_boot_delay */
12370 1, /* 10 scsi_reset_delay */
12371 1, /* bios_id_lun */
12372 1, /* 11 termination_se */
12373 1, /* termination_lvd */
12374 0, /* 12 bios_ctrl */
12375 0, /* 13 sdtr_speed2 */
12376 0, /* 14 sdtr_speed3 */
12377 1, /* 15 max_host_qng */
12378 1, /* max_dvc_qng */
12379 0, /* 16 dvc_cntl */
12380 0, /* 17 sdtr_speed4 */
12381 0, /* 18 serial_number_word1 */
12382 0, /* 19 serial_number_word2 */
12383 0, /* 20 serial_number_word3 */
12384 0, /* 21 check_sum */
12385 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
12386 , /* 22-29 oem_name[16] */
12387 0, /* 30 dvc_err_code */
12388 0, /* 31 adv_err_code */
12389 0, /* 32 adv_err_addr */
12390 0, /* 33 saved_dvc_err_code */
12391 0, /* 34 saved_adv_err_code */
12392 0, /* 35 saved_adv_err_addr */
12393 0, /* 36 reserved */
12394 0, /* 37 reserved */
12395 0, /* 38 reserved */
12396 0, /* 39 reserved */
12397 0, /* 40 reserved */
12398 0, /* 41 reserved */
12399 0, /* 42 reserved */
12400 0, /* 43 reserved */
12401 0, /* 44 reserved */
12402 0, /* 45 reserved */
12403 0, /* 46 reserved */
12404 0, /* 47 reserved */
12405 0, /* 48 reserved */
12406 0, /* 49 reserved */
12407 0, /* 50 reserved */
12408 0, /* 51 reserved */
12409 0, /* 52 reserved */
12410 0, /* 53 reserved */
12411 0, /* 54 reserved */
12412 0, /* 55 reserved */
12413 0, /* 56 cisptr_lsw */
12414 0, /* 57 cisprt_msw */
12415 0, /* 58 subsysvid */
12416 0, /* 59 subsysid */
12417 0, /* 60 reserved */
12418 0, /* 61 reserved */
12419 0, /* 62 reserved */
12420 0 /* 63 reserved */
12423 static ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config __devinitdata = {
12424 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
12425 0x0000, /* 01 cfg_msw */
12426 0xFFFF, /* 02 disc_enable */
12427 0xFFFF, /* 03 wdtr_able */
12428 0x5555, /* 04 sdtr_speed1 */
12429 0xFFFF, /* 05 start_motor */
12430 0xFFFF, /* 06 tagqng_able */
12431 0xFFFF, /* 07 bios_scan */
12432 0, /* 08 scam_tolerant */
12433 7, /* 09 adapter_scsi_id */
12434 0, /* bios_boot_delay */
12435 3, /* 10 scsi_reset_delay */
12436 0, /* bios_id_lun */
12437 0, /* 11 termination_se */
12438 0, /* termination_lvd */
12439 0xFFE7, /* 12 bios_ctrl */
12440 0x5555, /* 13 sdtr_speed2 */
12441 0x5555, /* 14 sdtr_speed3 */
12442 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
12443 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
12444 0, /* 16 dvc_cntl */
12445 0x5555, /* 17 sdtr_speed4 */
12446 0, /* 18 serial_number_word1 */
12447 0, /* 19 serial_number_word2 */
12448 0, /* 20 serial_number_word3 */
12449 0, /* 21 check_sum */
12450 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
12451 , /* 22-29 oem_name[16] */
12452 0, /* 30 dvc_err_code */
12453 0, /* 31 adv_err_code */
12454 0, /* 32 adv_err_addr */
12455 0, /* 33 saved_dvc_err_code */
12456 0, /* 34 saved_adv_err_code */
12457 0, /* 35 saved_adv_err_addr */
12458 0, /* 36 reserved */
12459 0, /* 37 reserved */
12460 0, /* 38 reserved */
12461 0, /* 39 reserved */
12462 0, /* 40 reserved */
12463 0, /* 41 reserved */
12464 0, /* 42 reserved */
12465 0, /* 43 reserved */
12466 0, /* 44 reserved */
12467 0, /* 45 reserved */
12468 0, /* 46 reserved */
12469 0, /* 47 reserved */
12470 0, /* 48 reserved */
12471 0, /* 49 reserved */
12472 0, /* 50 reserved */
12473 0, /* 51 reserved */
12474 0, /* 52 reserved */
12475 0, /* 53 reserved */
12476 0, /* 54 reserved */
12477 0, /* 55 reserved */
12478 0, /* 56 cisptr_lsw */
12479 0, /* 57 cisprt_msw */
12480 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
12481 PCI_DEVICE_ID_38C1600_REV1, /* 59 subsysid */
12482 0, /* 60 reserved */
12483 0, /* 61 reserved */
12484 0, /* 62 reserved */
12485 0 /* 63 reserved */
12488 static ADVEEP_38C1600_CONFIG ADVEEP_38C1600_Config_Field_IsChar __devinitdata = {
12489 0, /* 00 cfg_lsw */
12490 0, /* 01 cfg_msw */
12491 0, /* 02 disc_enable */
12492 0, /* 03 wdtr_able */
12493 0, /* 04 sdtr_speed1 */
12494 0, /* 05 start_motor */
12495 0, /* 06 tagqng_able */
12496 0, /* 07 bios_scan */
12497 0, /* 08 scam_tolerant */
12498 1, /* 09 adapter_scsi_id */
12499 1, /* bios_boot_delay */
12500 1, /* 10 scsi_reset_delay */
12501 1, /* bios_id_lun */
12502 1, /* 11 termination_se */
12503 1, /* termination_lvd */
12504 0, /* 12 bios_ctrl */
12505 0, /* 13 sdtr_speed2 */
12506 0, /* 14 sdtr_speed3 */
12507 1, /* 15 max_host_qng */
12508 1, /* max_dvc_qng */
12509 0, /* 16 dvc_cntl */
12510 0, /* 17 sdtr_speed4 */
12511 0, /* 18 serial_number_word1 */
12512 0, /* 19 serial_number_word2 */
12513 0, /* 20 serial_number_word3 */
12514 0, /* 21 check_sum */
12515 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
12516 , /* 22-29 oem_name[16] */
12517 0, /* 30 dvc_err_code */
12518 0, /* 31 adv_err_code */
12519 0, /* 32 adv_err_addr */
12520 0, /* 33 saved_dvc_err_code */
12521 0, /* 34 saved_adv_err_code */
12522 0, /* 35 saved_adv_err_addr */
12523 0, /* 36 reserved */
12524 0, /* 37 reserved */
12525 0, /* 38 reserved */
12526 0, /* 39 reserved */
12527 0, /* 40 reserved */
12528 0, /* 41 reserved */
12529 0, /* 42 reserved */
12530 0, /* 43 reserved */
12531 0, /* 44 reserved */
12532 0, /* 45 reserved */
12533 0, /* 46 reserved */
12534 0, /* 47 reserved */
12535 0, /* 48 reserved */
12536 0, /* 49 reserved */
12537 0, /* 50 reserved */
12538 0, /* 51 reserved */
12539 0, /* 52 reserved */
12540 0, /* 53 reserved */
12541 0, /* 54 reserved */
12542 0, /* 55 reserved */
12543 0, /* 56 cisptr_lsw */
12544 0, /* 57 cisprt_msw */
12545 0, /* 58 subsysvid */
12546 0, /* 59 subsysid */
12547 0, /* 60 reserved */
12548 0, /* 61 reserved */
12549 0, /* 62 reserved */
12550 0 /* 63 reserved */
12555 * Wait for EEPROM command to complete
12557 static void __devinit AdvWaitEEPCmd(AdvPortAddr iop_base)
12561 for (eep_delay_ms = 0; eep_delay_ms < ADV_EEP_DELAY_MS; eep_delay_ms++) {
12562 if (AdvReadWordRegister(iop_base, IOPW_EE_CMD) &
12563 ASC_EEP_CMD_DONE) {
12568 if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) ==
12574 * Read the EEPROM from specified location
12576 static ushort __devinit AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr)
12578 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12579 ASC_EEP_CMD_READ | eep_word_addr);
12580 AdvWaitEEPCmd(iop_base);
12581 return AdvReadWordRegister(iop_base, IOPW_EE_DATA);
12585 * Write the EEPROM from 'cfg_buf'.
12588 AdvSet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf)
12591 ushort addr, chksum;
12592 ushort *charfields;
12594 wbuf = (ushort *)cfg_buf;
12595 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
12598 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
12599 AdvWaitEEPCmd(iop_base);
12602 * Write EEPROM from word 0 to word 20.
12604 for (addr = ADV_EEP_DVC_CFG_BEGIN;
12605 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
12608 if (*charfields++) {
12609 word = cpu_to_le16(*wbuf);
12613 chksum += *wbuf; /* Checksum is calculated from word values. */
12614 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12615 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12616 ASC_EEP_CMD_WRITE | addr);
12617 AdvWaitEEPCmd(iop_base);
12618 mdelay(ADV_EEP_DELAY_MS);
12622 * Write EEPROM checksum at word 21.
12624 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
12625 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
12626 AdvWaitEEPCmd(iop_base);
12631 * Write EEPROM OEM name at words 22 to 29.
12633 for (addr = ADV_EEP_DVC_CTL_BEGIN;
12634 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
12637 if (*charfields++) {
12638 word = cpu_to_le16(*wbuf);
12642 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12643 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12644 ASC_EEP_CMD_WRITE | addr);
12645 AdvWaitEEPCmd(iop_base);
12647 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
12648 AdvWaitEEPCmd(iop_base);
12652 * Write the EEPROM from 'cfg_buf'.
12655 AdvSet38C0800EEPConfig(AdvPortAddr iop_base, ADVEEP_38C0800_CONFIG *cfg_buf)
12658 ushort *charfields;
12659 ushort addr, chksum;
12661 wbuf = (ushort *)cfg_buf;
12662 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
12665 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
12666 AdvWaitEEPCmd(iop_base);
12669 * Write EEPROM from word 0 to word 20.
12671 for (addr = ADV_EEP_DVC_CFG_BEGIN;
12672 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
12675 if (*charfields++) {
12676 word = cpu_to_le16(*wbuf);
12680 chksum += *wbuf; /* Checksum is calculated from word values. */
12681 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12682 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12683 ASC_EEP_CMD_WRITE | addr);
12684 AdvWaitEEPCmd(iop_base);
12685 mdelay(ADV_EEP_DELAY_MS);
12689 * Write EEPROM checksum at word 21.
12691 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
12692 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
12693 AdvWaitEEPCmd(iop_base);
12698 * Write EEPROM OEM name at words 22 to 29.
12700 for (addr = ADV_EEP_DVC_CTL_BEGIN;
12701 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
12704 if (*charfields++) {
12705 word = cpu_to_le16(*wbuf);
12709 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12710 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12711 ASC_EEP_CMD_WRITE | addr);
12712 AdvWaitEEPCmd(iop_base);
12714 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
12715 AdvWaitEEPCmd(iop_base);
12719 * Write the EEPROM from 'cfg_buf'.
12722 AdvSet38C1600EEPConfig(AdvPortAddr iop_base, ADVEEP_38C1600_CONFIG *cfg_buf)
12725 ushort *charfields;
12726 ushort addr, chksum;
12728 wbuf = (ushort *)cfg_buf;
12729 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
12732 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
12733 AdvWaitEEPCmd(iop_base);
12736 * Write EEPROM from word 0 to word 20.
12738 for (addr = ADV_EEP_DVC_CFG_BEGIN;
12739 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
12742 if (*charfields++) {
12743 word = cpu_to_le16(*wbuf);
12747 chksum += *wbuf; /* Checksum is calculated from word values. */
12748 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12749 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12750 ASC_EEP_CMD_WRITE | addr);
12751 AdvWaitEEPCmd(iop_base);
12752 mdelay(ADV_EEP_DELAY_MS);
12756 * Write EEPROM checksum at word 21.
12758 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
12759 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
12760 AdvWaitEEPCmd(iop_base);
12765 * Write EEPROM OEM name at words 22 to 29.
12767 for (addr = ADV_EEP_DVC_CTL_BEGIN;
12768 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
12771 if (*charfields++) {
12772 word = cpu_to_le16(*wbuf);
12776 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12777 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12778 ASC_EEP_CMD_WRITE | addr);
12779 AdvWaitEEPCmd(iop_base);
12781 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
12782 AdvWaitEEPCmd(iop_base);
12786 * Read EEPROM configuration into the specified buffer.
12788 * Return a checksum based on the EEPROM configuration read.
12790 static ushort __devinit
12791 AdvGet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf)
12793 ushort wval, chksum;
12796 ushort *charfields;
12798 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
12799 wbuf = (ushort *)cfg_buf;
12802 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
12803 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
12804 wval = AdvReadEEPWord(iop_base, eep_addr);
12805 chksum += wval; /* Checksum is calculated from word values. */
12806 if (*charfields++) {
12807 *wbuf = le16_to_cpu(wval);
12812 /* Read checksum word. */
12813 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
12817 /* Read rest of EEPROM not covered by the checksum. */
12818 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
12819 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
12820 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
12821 if (*charfields++) {
12822 *wbuf = le16_to_cpu(*wbuf);
12829 * Read EEPROM configuration into the specified buffer.
12831 * Return a checksum based on the EEPROM configuration read.
12833 static ushort __devinit
12834 AdvGet38C0800EEPConfig(AdvPortAddr iop_base, ADVEEP_38C0800_CONFIG *cfg_buf)
12836 ushort wval, chksum;
12839 ushort *charfields;
12841 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
12842 wbuf = (ushort *)cfg_buf;
12845 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
12846 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
12847 wval = AdvReadEEPWord(iop_base, eep_addr);
12848 chksum += wval; /* Checksum is calculated from word values. */
12849 if (*charfields++) {
12850 *wbuf = le16_to_cpu(wval);
12855 /* Read checksum word. */
12856 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
12860 /* Read rest of EEPROM not covered by the checksum. */
12861 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
12862 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
12863 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
12864 if (*charfields++) {
12865 *wbuf = le16_to_cpu(*wbuf);
12872 * Read EEPROM configuration into the specified buffer.
12874 * Return a checksum based on the EEPROM configuration read.
12876 static ushort __devinit
12877 AdvGet38C1600EEPConfig(AdvPortAddr iop_base, ADVEEP_38C1600_CONFIG *cfg_buf)
12879 ushort wval, chksum;
12882 ushort *charfields;
12884 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
12885 wbuf = (ushort *)cfg_buf;
12888 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
12889 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
12890 wval = AdvReadEEPWord(iop_base, eep_addr);
12891 chksum += wval; /* Checksum is calculated from word values. */
12892 if (*charfields++) {
12893 *wbuf = le16_to_cpu(wval);
12898 /* Read checksum word. */
12899 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
12903 /* Read rest of EEPROM not covered by the checksum. */
12904 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
12905 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
12906 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
12907 if (*charfields++) {
12908 *wbuf = le16_to_cpu(*wbuf);
12915 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
12916 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
12917 * all of this is done.
12919 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
12921 * For a non-fatal error return a warning code. If there are no warnings
12922 * then 0 is returned.
12924 * Note: Chip is stopped on entry.
12926 static int __devinit AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc)
12928 AdvPortAddr iop_base;
12930 ADVEEP_3550_CONFIG eep_config;
12932 iop_base = asc_dvc->iop_base;
12937 * Read the board's EEPROM configuration.
12939 * Set default values if a bad checksum is found.
12941 if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum) {
12942 warn_code |= ASC_WARN_EEPROM_CHKSUM;
12945 * Set EEPROM default values.
12947 memcpy(&eep_config, &Default_3550_EEPROM_Config,
12948 sizeof(ADVEEP_3550_CONFIG));
12951 * Assume the 6 byte board serial number that was read from
12952 * EEPROM is correct even if the EEPROM checksum failed.
12954 eep_config.serial_number_word3 =
12955 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
12957 eep_config.serial_number_word2 =
12958 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
12960 eep_config.serial_number_word1 =
12961 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
12963 AdvSet3550EEPConfig(iop_base, &eep_config);
12966 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
12967 * EEPROM configuration that was read.
12969 * This is the mapping of EEPROM fields to Adv Library fields.
12971 asc_dvc->wdtr_able = eep_config.wdtr_able;
12972 asc_dvc->sdtr_able = eep_config.sdtr_able;
12973 asc_dvc->ultra_able = eep_config.ultra_able;
12974 asc_dvc->tagqng_able = eep_config.tagqng_able;
12975 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
12976 asc_dvc->max_host_qng = eep_config.max_host_qng;
12977 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
12978 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
12979 asc_dvc->start_motor = eep_config.start_motor;
12980 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
12981 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
12982 asc_dvc->no_scam = eep_config.scam_tolerant;
12983 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
12984 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
12985 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
12988 * Set the host maximum queuing (max. 253, min. 16) and the per device
12989 * maximum queuing (max. 63, min. 4).
12991 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
12992 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
12993 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
12994 /* If the value is zero, assume it is uninitialized. */
12995 if (eep_config.max_host_qng == 0) {
12996 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
12998 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
13002 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
13003 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
13004 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
13005 /* If the value is zero, assume it is uninitialized. */
13006 if (eep_config.max_dvc_qng == 0) {
13007 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
13009 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
13014 * If 'max_dvc_qng' is greater than 'max_host_qng', then
13015 * set 'max_dvc_qng' to 'max_host_qng'.
13017 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
13018 eep_config.max_dvc_qng = eep_config.max_host_qng;
13022 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
13023 * values based on possibly adjusted EEPROM values.
13025 asc_dvc->max_host_qng = eep_config.max_host_qng;
13026 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
13029 * If the EEPROM 'termination' field is set to automatic (0), then set
13030 * the ADV_DVC_CFG 'termination' field to automatic also.
13032 * If the termination is specified with a non-zero 'termination'
13033 * value check that a legal value is set and set the ADV_DVC_CFG
13034 * 'termination' field appropriately.
13036 if (eep_config.termination == 0) {
13037 asc_dvc->cfg->termination = 0; /* auto termination */
13039 /* Enable manual control with low off / high off. */
13040 if (eep_config.termination == 1) {
13041 asc_dvc->cfg->termination = TERM_CTL_SEL;
13043 /* Enable manual control with low off / high on. */
13044 } else if (eep_config.termination == 2) {
13045 asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H;
13047 /* Enable manual control with low on / high on. */
13048 } else if (eep_config.termination == 3) {
13049 asc_dvc->cfg->termination =
13050 TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L;
13053 * The EEPROM 'termination' field contains a bad value. Use
13054 * automatic termination instead.
13056 asc_dvc->cfg->termination = 0;
13057 warn_code |= ASC_WARN_EEPROM_TERMINATION;
13065 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
13066 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
13067 * all of this is done.
13069 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
13071 * For a non-fatal error return a warning code. If there are no warnings
13072 * then 0 is returned.
13074 * Note: Chip is stopped on entry.
13076 static int __devinit AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc)
13078 AdvPortAddr iop_base;
13080 ADVEEP_38C0800_CONFIG eep_config;
13081 uchar tid, termination;
13082 ushort sdtr_speed = 0;
13084 iop_base = asc_dvc->iop_base;
13089 * Read the board's EEPROM configuration.
13091 * Set default values if a bad checksum is found.
13093 if (AdvGet38C0800EEPConfig(iop_base, &eep_config) !=
13094 eep_config.check_sum) {
13095 warn_code |= ASC_WARN_EEPROM_CHKSUM;
13098 * Set EEPROM default values.
13100 memcpy(&eep_config, &Default_38C0800_EEPROM_Config,
13101 sizeof(ADVEEP_38C0800_CONFIG));
13104 * Assume the 6 byte board serial number that was read from
13105 * EEPROM is correct even if the EEPROM checksum failed.
13107 eep_config.serial_number_word3 =
13108 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
13110 eep_config.serial_number_word2 =
13111 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
13113 eep_config.serial_number_word1 =
13114 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
13116 AdvSet38C0800EEPConfig(iop_base, &eep_config);
13119 * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the
13120 * EEPROM configuration that was read.
13122 * This is the mapping of EEPROM fields to Adv Library fields.
13124 asc_dvc->wdtr_able = eep_config.wdtr_able;
13125 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
13126 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
13127 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
13128 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
13129 asc_dvc->tagqng_able = eep_config.tagqng_able;
13130 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
13131 asc_dvc->max_host_qng = eep_config.max_host_qng;
13132 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
13133 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
13134 asc_dvc->start_motor = eep_config.start_motor;
13135 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
13136 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
13137 asc_dvc->no_scam = eep_config.scam_tolerant;
13138 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
13139 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
13140 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
13143 * For every Target ID if any of its 'sdtr_speed[1234]' bits
13144 * are set, then set an 'sdtr_able' bit for it.
13146 asc_dvc->sdtr_able = 0;
13147 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
13149 sdtr_speed = asc_dvc->sdtr_speed1;
13150 } else if (tid == 4) {
13151 sdtr_speed = asc_dvc->sdtr_speed2;
13152 } else if (tid == 8) {
13153 sdtr_speed = asc_dvc->sdtr_speed3;
13154 } else if (tid == 12) {
13155 sdtr_speed = asc_dvc->sdtr_speed4;
13157 if (sdtr_speed & ADV_MAX_TID) {
13158 asc_dvc->sdtr_able |= (1 << tid);
13164 * Set the host maximum queuing (max. 253, min. 16) and the per device
13165 * maximum queuing (max. 63, min. 4).
13167 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
13168 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
13169 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
13170 /* If the value is zero, assume it is uninitialized. */
13171 if (eep_config.max_host_qng == 0) {
13172 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
13174 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
13178 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
13179 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
13180 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
13181 /* If the value is zero, assume it is uninitialized. */
13182 if (eep_config.max_dvc_qng == 0) {
13183 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
13185 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
13190 * If 'max_dvc_qng' is greater than 'max_host_qng', then
13191 * set 'max_dvc_qng' to 'max_host_qng'.
13193 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
13194 eep_config.max_dvc_qng = eep_config.max_host_qng;
13198 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
13199 * values based on possibly adjusted EEPROM values.
13201 asc_dvc->max_host_qng = eep_config.max_host_qng;
13202 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
13205 * If the EEPROM 'termination' field is set to automatic (0), then set
13206 * the ADV_DVC_CFG 'termination' field to automatic also.
13208 * If the termination is specified with a non-zero 'termination'
13209 * value check that a legal value is set and set the ADV_DVC_CFG
13210 * 'termination' field appropriately.
13212 if (eep_config.termination_se == 0) {
13213 termination = 0; /* auto termination for SE */
13215 /* Enable manual control with low off / high off. */
13216 if (eep_config.termination_se == 1) {
13219 /* Enable manual control with low off / high on. */
13220 } else if (eep_config.termination_se == 2) {
13221 termination = TERM_SE_HI;
13223 /* Enable manual control with low on / high on. */
13224 } else if (eep_config.termination_se == 3) {
13225 termination = TERM_SE;
13228 * The EEPROM 'termination_se' field contains a bad value.
13229 * Use automatic termination instead.
13232 warn_code |= ASC_WARN_EEPROM_TERMINATION;
13236 if (eep_config.termination_lvd == 0) {
13237 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
13239 /* Enable manual control with low off / high off. */
13240 if (eep_config.termination_lvd == 1) {
13241 asc_dvc->cfg->termination = termination;
13243 /* Enable manual control with low off / high on. */
13244 } else if (eep_config.termination_lvd == 2) {
13245 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
13247 /* Enable manual control with low on / high on. */
13248 } else if (eep_config.termination_lvd == 3) {
13249 asc_dvc->cfg->termination = termination | TERM_LVD;
13252 * The EEPROM 'termination_lvd' field contains a bad value.
13253 * Use automatic termination instead.
13255 asc_dvc->cfg->termination = termination;
13256 warn_code |= ASC_WARN_EEPROM_TERMINATION;
13264 * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and
13265 * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while
13266 * all of this is done.
13268 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
13270 * For a non-fatal error return a warning code. If there are no warnings
13271 * then 0 is returned.
13273 * Note: Chip is stopped on entry.
13275 static int __devinit AdvInitFrom38C1600EEP(ADV_DVC_VAR *asc_dvc)
13277 AdvPortAddr iop_base;
13279 ADVEEP_38C1600_CONFIG eep_config;
13280 uchar tid, termination;
13281 ushort sdtr_speed = 0;
13283 iop_base = asc_dvc->iop_base;
13288 * Read the board's EEPROM configuration.
13290 * Set default values if a bad checksum is found.
13292 if (AdvGet38C1600EEPConfig(iop_base, &eep_config) !=
13293 eep_config.check_sum) {
13294 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
13295 warn_code |= ASC_WARN_EEPROM_CHKSUM;
13298 * Set EEPROM default values.
13300 memcpy(&eep_config, &Default_38C1600_EEPROM_Config,
13301 sizeof(ADVEEP_38C1600_CONFIG));
13303 if (PCI_FUNC(pdev->devfn) != 0) {
13306 * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60
13307 * and old Mac system booting problem. The Expansion
13308 * ROM must be disabled in Function 1 for these systems
13310 eep_config.cfg_lsw &= ~ADV_EEPROM_BIOS_ENABLE;
13312 * Clear the INTAB (bit 11) if the GPIO 0 input
13313 * indicates the Function 1 interrupt line is wired
13316 * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input:
13317 * 1 - Function 1 interrupt line wired to INT A.
13318 * 0 - Function 1 interrupt line wired to INT B.
13320 * Note: Function 0 is always wired to INTA.
13321 * Put all 5 GPIO bits in input mode and then read
13322 * their input values.
13324 AdvWriteByteRegister(iop_base, IOPB_GPIO_CNTL, 0);
13325 ints = AdvReadByteRegister(iop_base, IOPB_GPIO_DATA);
13326 if ((ints & 0x01) == 0)
13327 eep_config.cfg_lsw &= ~ADV_EEPROM_INTAB;
13331 * Assume the 6 byte board serial number that was read from
13332 * EEPROM is correct even if the EEPROM checksum failed.
13334 eep_config.serial_number_word3 =
13335 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
13336 eep_config.serial_number_word2 =
13337 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
13338 eep_config.serial_number_word1 =
13339 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
13341 AdvSet38C1600EEPConfig(iop_base, &eep_config);
13345 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
13346 * EEPROM configuration that was read.
13348 * This is the mapping of EEPROM fields to Adv Library fields.
13350 asc_dvc->wdtr_able = eep_config.wdtr_able;
13351 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
13352 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
13353 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
13354 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
13355 asc_dvc->ppr_able = 0;
13356 asc_dvc->tagqng_able = eep_config.tagqng_able;
13357 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
13358 asc_dvc->max_host_qng = eep_config.max_host_qng;
13359 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
13360 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ASC_MAX_TID);
13361 asc_dvc->start_motor = eep_config.start_motor;
13362 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
13363 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
13364 asc_dvc->no_scam = eep_config.scam_tolerant;
13367 * For every Target ID if any of its 'sdtr_speed[1234]' bits
13368 * are set, then set an 'sdtr_able' bit for it.
13370 asc_dvc->sdtr_able = 0;
13371 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
13373 sdtr_speed = asc_dvc->sdtr_speed1;
13374 } else if (tid == 4) {
13375 sdtr_speed = asc_dvc->sdtr_speed2;
13376 } else if (tid == 8) {
13377 sdtr_speed = asc_dvc->sdtr_speed3;
13378 } else if (tid == 12) {
13379 sdtr_speed = asc_dvc->sdtr_speed4;
13381 if (sdtr_speed & ASC_MAX_TID) {
13382 asc_dvc->sdtr_able |= (1 << tid);
13388 * Set the host maximum queuing (max. 253, min. 16) and the per device
13389 * maximum queuing (max. 63, min. 4).
13391 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
13392 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
13393 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
13394 /* If the value is zero, assume it is uninitialized. */
13395 if (eep_config.max_host_qng == 0) {
13396 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
13398 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
13402 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
13403 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
13404 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
13405 /* If the value is zero, assume it is uninitialized. */
13406 if (eep_config.max_dvc_qng == 0) {
13407 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
13409 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
13414 * If 'max_dvc_qng' is greater than 'max_host_qng', then
13415 * set 'max_dvc_qng' to 'max_host_qng'.
13417 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
13418 eep_config.max_dvc_qng = eep_config.max_host_qng;
13422 * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng'
13423 * values based on possibly adjusted EEPROM values.
13425 asc_dvc->max_host_qng = eep_config.max_host_qng;
13426 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
13429 * If the EEPROM 'termination' field is set to automatic (0), then set
13430 * the ASC_DVC_CFG 'termination' field to automatic also.
13432 * If the termination is specified with a non-zero 'termination'
13433 * value check that a legal value is set and set the ASC_DVC_CFG
13434 * 'termination' field appropriately.
13436 if (eep_config.termination_se == 0) {
13437 termination = 0; /* auto termination for SE */
13439 /* Enable manual control with low off / high off. */
13440 if (eep_config.termination_se == 1) {
13443 /* Enable manual control with low off / high on. */
13444 } else if (eep_config.termination_se == 2) {
13445 termination = TERM_SE_HI;
13447 /* Enable manual control with low on / high on. */
13448 } else if (eep_config.termination_se == 3) {
13449 termination = TERM_SE;
13452 * The EEPROM 'termination_se' field contains a bad value.
13453 * Use automatic termination instead.
13456 warn_code |= ASC_WARN_EEPROM_TERMINATION;
13460 if (eep_config.termination_lvd == 0) {
13461 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
13463 /* Enable manual control with low off / high off. */
13464 if (eep_config.termination_lvd == 1) {
13465 asc_dvc->cfg->termination = termination;
13467 /* Enable manual control with low off / high on. */
13468 } else if (eep_config.termination_lvd == 2) {
13469 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
13471 /* Enable manual control with low on / high on. */
13472 } else if (eep_config.termination_lvd == 3) {
13473 asc_dvc->cfg->termination = termination | TERM_LVD;
13476 * The EEPROM 'termination_lvd' field contains a bad value.
13477 * Use automatic termination instead.
13479 asc_dvc->cfg->termination = termination;
13480 warn_code |= ASC_WARN_EEPROM_TERMINATION;
13488 * Initialize the ADV_DVC_VAR structure.
13490 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
13492 * For a non-fatal error return a warning code. If there are no warnings
13493 * then 0 is returned.
13495 static int __devinit
13496 AdvInitGetConfig(struct pci_dev *pdev, struct asc_board *boardp)
13498 ADV_DVC_VAR *asc_dvc = &boardp->dvc_var.adv_dvc_var;
13499 unsigned short warn_code = 0;
13500 AdvPortAddr iop_base = asc_dvc->iop_base;
13504 asc_dvc->err_code = 0;
13507 * Save the state of the PCI Configuration Command Register
13508 * "Parity Error Response Control" Bit. If the bit is clear (0),
13509 * in AdvInitAsc3550/38C0800Driver() tell the microcode to ignore
13510 * DMA parity errors.
13512 asc_dvc->cfg->control_flag = 0;
13513 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
13514 if ((cmd & PCI_COMMAND_PARITY) == 0)
13515 asc_dvc->cfg->control_flag |= CONTROL_FLAG_IGNORE_PERR;
13517 asc_dvc->cfg->chip_version =
13518 AdvGetChipVersion(iop_base, asc_dvc->bus_type);
13520 ASC_DBG2(1, "AdvInitGetConfig: iopb_chip_id_1: 0x%x 0x%x\n",
13521 (ushort)AdvReadByteRegister(iop_base, IOPB_CHIP_ID_1),
13522 (ushort)ADV_CHIP_ID_BYTE);
13524 ASC_DBG2(1, "AdvInitGetConfig: iopw_chip_id_0: 0x%x 0x%x\n",
13525 (ushort)AdvReadWordRegister(iop_base, IOPW_CHIP_ID_0),
13526 (ushort)ADV_CHIP_ID_WORD);
13529 * Reset the chip to start and allow register writes.
13531 if (AdvFindSignature(iop_base) == 0) {
13532 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
13536 * The caller must set 'chip_type' to a valid setting.
13538 if (asc_dvc->chip_type != ADV_CHIP_ASC3550 &&
13539 asc_dvc->chip_type != ADV_CHIP_ASC38C0800 &&
13540 asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
13541 asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE;
13548 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
13549 ADV_CTRL_REG_CMD_RESET);
13551 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
13552 ADV_CTRL_REG_CMD_WR_IO_REG);
13554 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
13555 status = AdvInitFrom38C1600EEP(asc_dvc);
13556 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
13557 status = AdvInitFrom38C0800EEP(asc_dvc);
13559 status = AdvInitFrom3550EEP(asc_dvc);
13561 warn_code |= status;
13564 if (warn_code != 0) {
13565 ASC_PRINT2("AdvInitGetConfig: board %d: warning: 0x%x\n",
13566 boardp->id, warn_code);
13569 if (asc_dvc->err_code) {
13570 ASC_PRINT2("AdvInitGetConfig: board %d error: err_code 0x%x\n",
13571 boardp->id, asc_dvc->err_code);
13574 return asc_dvc->err_code;
13578 static struct scsi_host_template advansys_template = {
13579 .proc_name = DRV_NAME,
13580 #ifdef CONFIG_PROC_FS
13581 .proc_info = advansys_proc_info,
13584 .info = advansys_info,
13585 .queuecommand = advansys_queuecommand,
13586 .eh_bus_reset_handler = advansys_reset,
13587 .bios_param = advansys_biosparam,
13588 .slave_configure = advansys_slave_configure,
13590 * Because the driver may control an ISA adapter 'unchecked_isa_dma'
13591 * must be set. The flag will be cleared in advansys_board_found
13592 * for non-ISA adapters.
13594 .unchecked_isa_dma = 1,
13596 * All adapters controlled by this driver are capable of large
13597 * scatter-gather lists. According to the mid-level SCSI documentation
13598 * this obviates any performance gain provided by setting
13599 * 'use_clustering'. But empirically while CPU utilization is increased
13600 * by enabling clustering, I/O throughput increases as well.
13602 .use_clustering = ENABLE_CLUSTERING,
13605 static int __devinit
13606 advansys_wide_init_chip(struct asc_board *boardp, ADV_DVC_VAR *adv_dvc_varp)
13609 adv_req_t *reqp = NULL;
13612 int warn_code, err_code;
13615 * Allocate buffer carrier structures. The total size
13616 * is about 4 KB, so allocate all at once.
13618 boardp->carrp = kmalloc(ADV_CARRIER_BUFSIZE, GFP_KERNEL);
13619 ASC_DBG1(1, "advansys_wide_init_chip: carrp 0x%p\n", boardp->carrp);
13621 if (!boardp->carrp)
13622 goto kmalloc_failed;
13625 * Allocate up to 'max_host_qng' request structures for the Wide
13626 * board. The total size is about 16 KB, so allocate all at once.
13627 * If the allocation fails decrement and try again.
13629 for (req_cnt = adv_dvc_varp->max_host_qng; req_cnt > 0; req_cnt--) {
13630 reqp = kmalloc(sizeof(adv_req_t) * req_cnt, GFP_KERNEL);
13632 ASC_DBG3(1, "advansys_wide_init_chip: reqp 0x%p, req_cnt %d, "
13633 "bytes %lu\n", reqp, req_cnt,
13634 (ulong)sizeof(adv_req_t) * req_cnt);
13641 goto kmalloc_failed;
13643 boardp->orig_reqp = reqp;
13646 * Allocate up to ADV_TOT_SG_BLOCK request structures for
13647 * the Wide board. Each structure is about 136 bytes.
13649 boardp->adv_sgblkp = NULL;
13650 for (sg_cnt = 0; sg_cnt < ADV_TOT_SG_BLOCK; sg_cnt++) {
13651 sgp = kmalloc(sizeof(adv_sgblk_t), GFP_KERNEL);
13656 sgp->next_sgblkp = boardp->adv_sgblkp;
13657 boardp->adv_sgblkp = sgp;
13661 ASC_DBG3(1, "advansys_wide_init_chip: sg_cnt %d * %u = %u bytes\n",
13662 sg_cnt, sizeof(adv_sgblk_t),
13663 (unsigned)(sizeof(adv_sgblk_t) * sg_cnt));
13665 if (!boardp->adv_sgblkp)
13666 goto kmalloc_failed;
13668 adv_dvc_varp->carrier_buf = boardp->carrp;
13671 * Point 'adv_reqp' to the request structures and
13672 * link them together.
13675 reqp[req_cnt].next_reqp = NULL;
13676 for (; req_cnt > 0; req_cnt--) {
13677 reqp[req_cnt - 1].next_reqp = &reqp[req_cnt];
13679 boardp->adv_reqp = &reqp[0];
13681 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
13682 ASC_DBG(2, "advansys_wide_init_chip: AdvInitAsc3550Driver()\n");
13683 warn_code = AdvInitAsc3550Driver(adv_dvc_varp);
13684 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
13685 ASC_DBG(2, "advansys_wide_init_chip: AdvInitAsc38C0800Driver()"
13687 warn_code = AdvInitAsc38C0800Driver(adv_dvc_varp);
13689 ASC_DBG(2, "advansys_wide_init_chip: AdvInitAsc38C1600Driver()"
13691 warn_code = AdvInitAsc38C1600Driver(adv_dvc_varp);
13693 err_code = adv_dvc_varp->err_code;
13695 if (warn_code || err_code) {
13696 ASC_PRINT3("advansys_wide_init_chip: board %d error: warn 0x%x,"
13697 " error 0x%x\n", boardp->id, warn_code, err_code);
13703 ASC_PRINT1("advansys_wide_init_chip: board %d error: kmalloc() "
13704 "failed\n", boardp->id);
13705 err_code = ADV_ERROR;
13710 static void advansys_wide_free_mem(struct asc_board *boardp)
13712 kfree(boardp->carrp);
13713 boardp->carrp = NULL;
13714 kfree(boardp->orig_reqp);
13715 boardp->orig_reqp = boardp->adv_reqp = NULL;
13716 while (boardp->adv_sgblkp) {
13717 adv_sgblk_t *sgp = boardp->adv_sgblkp;
13718 boardp->adv_sgblkp = sgp->next_sgblkp;
13723 static int __devinit advansys_board_found(struct Scsi_Host *shost,
13724 unsigned int iop, int bus_type)
13726 struct pci_dev *pdev;
13727 struct asc_board *boardp = shost_priv(shost);
13728 ASC_DVC_VAR *asc_dvc_varp = NULL;
13729 ADV_DVC_VAR *adv_dvc_varp = NULL;
13730 int share_irq, warn_code, ret;
13732 boardp->id = asc_board_count++;
13733 spin_lock_init(&boardp->lock);
13734 pdev = (bus_type == ASC_IS_PCI) ? to_pci_dev(boardp->dev) : NULL;
13736 if (ASC_NARROW_BOARD(boardp)) {
13737 ASC_DBG(1, "advansys_board_found: narrow board\n");
13738 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
13739 asc_dvc_varp->bus_type = bus_type;
13740 asc_dvc_varp->drv_ptr = boardp;
13741 asc_dvc_varp->cfg = &boardp->dvc_cfg.asc_dvc_cfg;
13742 asc_dvc_varp->cfg->overrun_buf = &overrun_buf[0];
13743 asc_dvc_varp->iop_base = iop;
13746 ASC_DBG(1, "advansys_board_found: wide board\n");
13747 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
13748 adv_dvc_varp->drv_ptr = boardp;
13749 adv_dvc_varp->cfg = &boardp->dvc_cfg.adv_dvc_cfg;
13750 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW) {
13751 ASC_DBG(1, "advansys_board_found: ASC-3550\n");
13752 adv_dvc_varp->chip_type = ADV_CHIP_ASC3550;
13753 } else if (pdev->device == PCI_DEVICE_ID_38C0800_REV1) {
13754 ASC_DBG(1, "advansys_board_found: ASC-38C0800\n");
13755 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C0800;
13757 ASC_DBG(1, "advansys_board_found: ASC-38C1600\n");
13758 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C1600;
13761 boardp->asc_n_io_port = pci_resource_len(pdev, 1);
13762 boardp->ioremap_addr = ioremap(pci_resource_start(pdev, 1),
13763 boardp->asc_n_io_port);
13764 if (!boardp->ioremap_addr) {
13766 ("advansys_board_found: board %d: ioremap(%x, %d) returned NULL\n",
13767 boardp->id, pci_resource_start(pdev, 1),
13768 boardp->asc_n_io_port);
13772 adv_dvc_varp->iop_base = (AdvPortAddr)boardp->ioremap_addr
13773 ASC_DBG1(1, "advansys_board_found: iop_base: 0x%lx\n",
13774 adv_dvc_varp->iop_base);
13777 * Even though it isn't used to access wide boards, other
13778 * than for the debug line below, save I/O Port address so
13779 * that it can be reported.
13781 boardp->ioport = iop;
13783 ASC_DBG2(1, "advansys_board_found: iopb_chip_id_1 0x%x, "
13784 "iopw_chip_id_0 0x%x\n", (ushort)inp(iop + 1),
13785 (ushort)inpw(iop));
13786 #endif /* CONFIG_PCI */
13789 #ifdef CONFIG_PROC_FS
13791 * Allocate buffer for printing information from
13792 * /proc/scsi/advansys/[0...].
13794 boardp->prtbuf = kmalloc(ASC_PRTBUF_SIZE, GFP_KERNEL);
13795 if (!boardp->prtbuf) {
13796 ASC_PRINT2("advansys_board_found: board %d: kmalloc(%d) "
13797 "returned NULL\n", boardp->id, ASC_PRTBUF_SIZE);
13801 #endif /* CONFIG_PROC_FS */
13803 if (ASC_NARROW_BOARD(boardp)) {
13805 * Set the board bus type and PCI IRQ before
13806 * calling AscInitGetConfig().
13808 switch (asc_dvc_varp->bus_type) {
13811 shost->unchecked_isa_dma = TRUE;
13815 shost->unchecked_isa_dma = FALSE;
13819 shost->unchecked_isa_dma = FALSE;
13820 share_irq = IRQF_SHARED;
13822 #endif /* CONFIG_ISA */
13825 shost->unchecked_isa_dma = FALSE;
13826 share_irq = IRQF_SHARED;
13828 #endif /* CONFIG_PCI */
13831 ("advansys_board_found: board %d: unknown adapter type: %d\n",
13832 boardp->id, asc_dvc_varp->bus_type);
13833 shost->unchecked_isa_dma = TRUE;
13839 * NOTE: AscInitGetConfig() may change the board's
13840 * bus_type value. The bus_type value should no
13841 * longer be used. If the bus_type field must be
13842 * referenced only use the bit-wise AND operator "&".
13844 ASC_DBG(2, "advansys_board_found: AscInitGetConfig()\n");
13845 ret = AscInitGetConfig(boardp) ? -ENODEV : 0;
13849 * For Wide boards set PCI information before calling
13850 * AdvInitGetConfig().
13852 shost->unchecked_isa_dma = FALSE;
13853 share_irq = IRQF_SHARED;
13854 ASC_DBG(2, "advansys_board_found: AdvInitGetConfig()\n");
13856 ret = AdvInitGetConfig(pdev, boardp) ? -ENODEV : 0;
13857 #endif /* CONFIG_PCI */
13861 goto err_free_proc;
13864 * Save the EEPROM configuration so that it can be displayed
13865 * from /proc/scsi/advansys/[0...].
13867 if (ASC_NARROW_BOARD(boardp)) {
13872 * Set the adapter's target id bit in the 'init_tidmask' field.
13874 boardp->init_tidmask |=
13875 ADV_TID_TO_TIDMASK(asc_dvc_varp->cfg->chip_scsi_id);
13878 * Save EEPROM settings for the board.
13880 ep = &boardp->eep_config.asc_eep;
13882 ep->init_sdtr = asc_dvc_varp->cfg->sdtr_enable;
13883 ep->disc_enable = asc_dvc_varp->cfg->disc_enable;
13884 ep->use_cmd_qng = asc_dvc_varp->cfg->cmd_qng_enabled;
13885 ASC_EEP_SET_DMA_SPD(ep, asc_dvc_varp->cfg->isa_dma_speed);
13886 ep->start_motor = asc_dvc_varp->start_motor;
13887 ep->cntl = asc_dvc_varp->dvc_cntl;
13888 ep->no_scam = asc_dvc_varp->no_scam;
13889 ep->max_total_qng = asc_dvc_varp->max_total_qng;
13890 ASC_EEP_SET_CHIP_ID(ep, asc_dvc_varp->cfg->chip_scsi_id);
13891 /* 'max_tag_qng' is set to the same value for every device. */
13892 ep->max_tag_qng = asc_dvc_varp->cfg->max_tag_qng[0];
13893 ep->adapter_info[0] = asc_dvc_varp->cfg->adapter_info[0];
13894 ep->adapter_info[1] = asc_dvc_varp->cfg->adapter_info[1];
13895 ep->adapter_info[2] = asc_dvc_varp->cfg->adapter_info[2];
13896 ep->adapter_info[3] = asc_dvc_varp->cfg->adapter_info[3];
13897 ep->adapter_info[4] = asc_dvc_varp->cfg->adapter_info[4];
13898 ep->adapter_info[5] = asc_dvc_varp->cfg->adapter_info[5];
13901 * Modify board configuration.
13903 ASC_DBG(2, "advansys_board_found: AscInitSetConfig()\n");
13904 ret = AscInitSetConfig(pdev, boardp) ? -ENODEV : 0;
13906 goto err_free_proc;
13908 ADVEEP_3550_CONFIG *ep_3550;
13909 ADVEEP_38C0800_CONFIG *ep_38C0800;
13910 ADVEEP_38C1600_CONFIG *ep_38C1600;
13913 * Save Wide EEP Configuration Information.
13915 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
13916 ep_3550 = &boardp->eep_config.adv_3550_eep;
13918 ep_3550->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
13919 ep_3550->max_host_qng = adv_dvc_varp->max_host_qng;
13920 ep_3550->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
13921 ep_3550->termination = adv_dvc_varp->cfg->termination;
13922 ep_3550->disc_enable = adv_dvc_varp->cfg->disc_enable;
13923 ep_3550->bios_ctrl = adv_dvc_varp->bios_ctrl;
13924 ep_3550->wdtr_able = adv_dvc_varp->wdtr_able;
13925 ep_3550->sdtr_able = adv_dvc_varp->sdtr_able;
13926 ep_3550->ultra_able = adv_dvc_varp->ultra_able;
13927 ep_3550->tagqng_able = adv_dvc_varp->tagqng_able;
13928 ep_3550->start_motor = adv_dvc_varp->start_motor;
13929 ep_3550->scsi_reset_delay =
13930 adv_dvc_varp->scsi_reset_wait;
13931 ep_3550->serial_number_word1 =
13932 adv_dvc_varp->cfg->serial1;
13933 ep_3550->serial_number_word2 =
13934 adv_dvc_varp->cfg->serial2;
13935 ep_3550->serial_number_word3 =
13936 adv_dvc_varp->cfg->serial3;
13937 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
13938 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
13940 ep_38C0800->adapter_scsi_id =
13941 adv_dvc_varp->chip_scsi_id;
13942 ep_38C0800->max_host_qng = adv_dvc_varp->max_host_qng;
13943 ep_38C0800->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
13944 ep_38C0800->termination_lvd =
13945 adv_dvc_varp->cfg->termination;
13946 ep_38C0800->disc_enable =
13947 adv_dvc_varp->cfg->disc_enable;
13948 ep_38C0800->bios_ctrl = adv_dvc_varp->bios_ctrl;
13949 ep_38C0800->wdtr_able = adv_dvc_varp->wdtr_able;
13950 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
13951 ep_38C0800->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
13952 ep_38C0800->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
13953 ep_38C0800->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
13954 ep_38C0800->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
13955 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
13956 ep_38C0800->start_motor = adv_dvc_varp->start_motor;
13957 ep_38C0800->scsi_reset_delay =
13958 adv_dvc_varp->scsi_reset_wait;
13959 ep_38C0800->serial_number_word1 =
13960 adv_dvc_varp->cfg->serial1;
13961 ep_38C0800->serial_number_word2 =
13962 adv_dvc_varp->cfg->serial2;
13963 ep_38C0800->serial_number_word3 =
13964 adv_dvc_varp->cfg->serial3;
13966 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
13968 ep_38C1600->adapter_scsi_id =
13969 adv_dvc_varp->chip_scsi_id;
13970 ep_38C1600->max_host_qng = adv_dvc_varp->max_host_qng;
13971 ep_38C1600->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
13972 ep_38C1600->termination_lvd =
13973 adv_dvc_varp->cfg->termination;
13974 ep_38C1600->disc_enable =
13975 adv_dvc_varp->cfg->disc_enable;
13976 ep_38C1600->bios_ctrl = adv_dvc_varp->bios_ctrl;
13977 ep_38C1600->wdtr_able = adv_dvc_varp->wdtr_able;
13978 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
13979 ep_38C1600->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
13980 ep_38C1600->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
13981 ep_38C1600->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
13982 ep_38C1600->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
13983 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
13984 ep_38C1600->start_motor = adv_dvc_varp->start_motor;
13985 ep_38C1600->scsi_reset_delay =
13986 adv_dvc_varp->scsi_reset_wait;
13987 ep_38C1600->serial_number_word1 =
13988 adv_dvc_varp->cfg->serial1;
13989 ep_38C1600->serial_number_word2 =
13990 adv_dvc_varp->cfg->serial2;
13991 ep_38C1600->serial_number_word3 =
13992 adv_dvc_varp->cfg->serial3;
13996 * Set the adapter's target id bit in the 'init_tidmask' field.
13998 boardp->init_tidmask |=
13999 ADV_TID_TO_TIDMASK(adv_dvc_varp->chip_scsi_id);
14003 * Channels are numbered beginning with 0. For AdvanSys one host
14004 * structure supports one channel. Multi-channel boards have a
14005 * separate host structure for each channel.
14007 shost->max_channel = 0;
14008 if (ASC_NARROW_BOARD(boardp)) {
14009 shost->max_id = ASC_MAX_TID + 1;
14010 shost->max_lun = ASC_MAX_LUN + 1;
14011 shost->max_cmd_len = ASC_MAX_CDB_LEN;
14013 shost->io_port = asc_dvc_varp->iop_base;
14014 boardp->asc_n_io_port = ASC_IOADR_GAP;
14015 shost->this_id = asc_dvc_varp->cfg->chip_scsi_id;
14017 /* Set maximum number of queues the adapter can handle. */
14018 shost->can_queue = asc_dvc_varp->max_total_qng;
14020 shost->max_id = ADV_MAX_TID + 1;
14021 shost->max_lun = ADV_MAX_LUN + 1;
14022 shost->max_cmd_len = ADV_MAX_CDB_LEN;
14025 * Save the I/O Port address and length even though
14026 * I/O ports are not used to access Wide boards.
14027 * Instead the Wide boards are accessed with
14028 * PCI Memory Mapped I/O.
14030 shost->io_port = iop;
14032 shost->this_id = adv_dvc_varp->chip_scsi_id;
14034 /* Set maximum number of queues the adapter can handle. */
14035 shost->can_queue = adv_dvc_varp->max_host_qng;
14039 * Following v1.3.89, 'cmd_per_lun' is no longer needed
14040 * and should be set to zero.
14042 * But because of a bug introduced in v1.3.89 if the driver is
14043 * compiled as a module and 'cmd_per_lun' is zero, the Mid-Level
14044 * SCSI function 'allocate_device' will panic. To allow the driver
14045 * to work as a module in these kernels set 'cmd_per_lun' to 1.
14047 * Note: This is wrong. cmd_per_lun should be set to the depth
14048 * you want on untagged devices always.
14051 shost->cmd_per_lun = 1;
14053 shost->cmd_per_lun = 0;
14057 * Set the maximum number of scatter-gather elements the
14058 * adapter can handle.
14060 if (ASC_NARROW_BOARD(boardp)) {
14062 * Allow two commands with 'sg_tablesize' scatter-gather
14063 * elements to be executed simultaneously. This value is
14064 * the theoretical hardware limit. It may be decreased
14067 shost->sg_tablesize =
14068 (((asc_dvc_varp->max_total_qng - 2) / 2) *
14069 ASC_SG_LIST_PER_Q) + 1;
14071 shost->sg_tablesize = ADV_MAX_SG_LIST;
14075 * The value of 'sg_tablesize' can not exceed the SCSI
14076 * mid-level driver definition of SG_ALL. SG_ALL also
14077 * must not be exceeded, because it is used to define the
14078 * size of the scatter-gather table in 'struct asc_sg_head'.
14080 if (shost->sg_tablesize > SG_ALL) {
14081 shost->sg_tablesize = SG_ALL;
14084 ASC_DBG1(1, "advansys_board_found: sg_tablesize: %d\n", shost->sg_tablesize);
14086 /* BIOS start address. */
14087 if (ASC_NARROW_BOARD(boardp)) {
14088 shost->base = AscGetChipBiosAddress(asc_dvc_varp->iop_base,
14089 asc_dvc_varp->bus_type);
14092 * Fill-in BIOS board variables. The Wide BIOS saves
14093 * information in LRAM that is used by the driver.
14095 AdvReadWordLram(adv_dvc_varp->iop_base,
14096 BIOS_SIGNATURE, boardp->bios_signature);
14097 AdvReadWordLram(adv_dvc_varp->iop_base,
14098 BIOS_VERSION, boardp->bios_version);
14099 AdvReadWordLram(adv_dvc_varp->iop_base,
14100 BIOS_CODESEG, boardp->bios_codeseg);
14101 AdvReadWordLram(adv_dvc_varp->iop_base,
14102 BIOS_CODELEN, boardp->bios_codelen);
14105 "advansys_board_found: bios_signature 0x%x, bios_version 0x%x\n",
14106 boardp->bios_signature, boardp->bios_version);
14109 "advansys_board_found: bios_codeseg 0x%x, bios_codelen 0x%x\n",
14110 boardp->bios_codeseg, boardp->bios_codelen);
14113 * If the BIOS saved a valid signature, then fill in
14114 * the BIOS code segment base address.
14116 if (boardp->bios_signature == 0x55AA) {
14118 * Convert x86 realmode code segment to a linear
14119 * address by shifting left 4.
14121 shost->base = ((ulong)boardp->bios_codeseg << 4);
14128 * Register Board Resources - I/O Port, DMA, IRQ
14131 /* Register DMA Channel for Narrow boards. */
14132 shost->dma_channel = NO_ISA_DMA; /* Default to no ISA DMA. */
14134 if (ASC_NARROW_BOARD(boardp)) {
14135 /* Register DMA channel for ISA bus. */
14136 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
14137 shost->dma_channel = asc_dvc_varp->cfg->isa_dma_channel;
14138 ret = request_dma(shost->dma_channel, DRV_NAME);
14141 ("advansys_board_found: board %d: request_dma() %d failed %d\n",
14142 boardp->id, shost->dma_channel, ret);
14143 goto err_free_proc;
14145 AscEnableIsaDma(shost->dma_channel);
14148 #endif /* CONFIG_ISA */
14150 /* Register IRQ Number. */
14151 ASC_DBG1(2, "advansys_board_found: request_irq() %d\n", boardp->irq);
14153 ret = request_irq(boardp->irq, advansys_interrupt, share_irq,
14157 if (ret == -EBUSY) {
14159 ("advansys_board_found: board %d: request_irq(): IRQ 0x%x already in use.\n",
14160 boardp->id, boardp->irq);
14161 } else if (ret == -EINVAL) {
14163 ("advansys_board_found: board %d: request_irq(): IRQ 0x%x not valid.\n",
14164 boardp->id, boardp->irq);
14167 ("advansys_board_found: board %d: request_irq(): IRQ 0x%x failed with %d\n",
14168 boardp->id, boardp->irq, ret);
14174 * Initialize board RISC chip and enable interrupts.
14176 if (ASC_NARROW_BOARD(boardp)) {
14177 ASC_DBG(2, "advansys_board_found: AscInitAsc1000Driver()\n");
14178 warn_code = AscInitAsc1000Driver(asc_dvc_varp);
14180 if (warn_code || asc_dvc_varp->err_code) {
14181 ASC_PRINT4("advansys_board_found: board %d error: "
14182 "init_state 0x%x, warn 0x%x, error 0x%x\n",
14183 boardp->id, asc_dvc_varp->init_state,
14184 warn_code, asc_dvc_varp->err_code);
14185 if (asc_dvc_varp->err_code)
14189 if (advansys_wide_init_chip(boardp, adv_dvc_varp))
14194 goto err_free_wide_mem;
14196 ASC_DBG_PRT_SCSI_HOST(2, shost);
14198 ret = scsi_add_host(shost, boardp->dev);
14200 goto err_free_wide_mem;
14202 scsi_scan_host(shost);
14206 advansys_wide_free_mem(boardp);
14207 free_irq(boardp->irq, shost);
14209 if (shost->dma_channel != NO_ISA_DMA)
14210 free_dma(shost->dma_channel);
14212 kfree(boardp->prtbuf);
14214 if (boardp->ioremap_addr)
14215 iounmap(boardp->ioremap_addr);
14221 * advansys_release()
14223 * Release resources allocated for a single AdvanSys adapter.
14225 static int advansys_release(struct Scsi_Host *shost)
14227 struct asc_board *boardp = shost_priv(shost);
14228 ASC_DBG(1, "advansys_release: begin\n");
14229 scsi_remove_host(shost);
14230 free_irq(boardp->irq, shost);
14231 if (shost->dma_channel != NO_ISA_DMA) {
14232 ASC_DBG(1, "advansys_release: free_dma()\n");
14233 free_dma(shost->dma_channel);
14235 if (!ASC_NARROW_BOARD(boardp)) {
14236 iounmap(boardp->ioremap_addr);
14237 advansys_wide_free_mem(boardp);
14239 kfree(boardp->prtbuf);
14240 scsi_host_put(shost);
14241 ASC_DBG(1, "advansys_release: end\n");
14245 #define ASC_IOADR_TABLE_MAX_IX 11
14247 static PortAddr _asc_def_iop_base[ASC_IOADR_TABLE_MAX_IX] __devinitdata = {
14248 0x100, 0x0110, 0x120, 0x0130, 0x140, 0x0150, 0x0190,
14249 0x0210, 0x0230, 0x0250, 0x0330
14253 * The ISA IRQ number is found in bits 2 and 3 of the CfgLsw. It decodes as:
14259 static unsigned int __devinit advansys_isa_irq_no(PortAddr iop_base)
14261 unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
14262 unsigned int chip_irq = ((cfg_lsw >> 2) & 0x03) + 10;
14263 if (chip_irq == 13)
14268 static int __devinit advansys_isa_probe(struct device *dev, unsigned int id)
14271 PortAddr iop_base = _asc_def_iop_base[id];
14272 struct Scsi_Host *shost;
14273 struct asc_board *board;
14275 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
14276 ASC_DBG1(1, "advansys_isa_match: I/O port 0x%x busy\n",
14280 ASC_DBG1(1, "advansys_isa_match: probing I/O port 0x%x\n", iop_base);
14281 if (!AscFindSignature(iop_base))
14282 goto release_region;
14283 if (!(AscGetChipVersion(iop_base, ASC_IS_ISA) & ASC_CHIP_VER_ISA_BIT))
14284 goto release_region;
14287 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
14289 goto release_region;
14291 board = shost_priv(shost);
14292 board->irq = advansys_isa_irq_no(iop_base);
14295 err = advansys_board_found(shost, iop_base, ASC_IS_ISA);
14299 dev_set_drvdata(dev, shost);
14303 scsi_host_put(shost);
14305 release_region(iop_base, ASC_IOADR_GAP);
14309 static int __devexit advansys_isa_remove(struct device *dev, unsigned int id)
14311 int ioport = _asc_def_iop_base[id];
14312 advansys_release(dev_get_drvdata(dev));
14313 release_region(ioport, ASC_IOADR_GAP);
14317 static struct isa_driver advansys_isa_driver = {
14318 .probe = advansys_isa_probe,
14319 .remove = __devexit_p(advansys_isa_remove),
14321 .owner = THIS_MODULE,
14327 * The VLB IRQ number is found in bits 2 to 4 of the CfgLsw. It decodes as:
14337 static unsigned int __devinit advansys_vlb_irq_no(PortAddr iop_base)
14339 unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
14340 unsigned int chip_irq = ((cfg_lsw >> 2) & 0x07) + 9;
14341 if ((chip_irq < 10) || (chip_irq == 13) || (chip_irq > 15))
14346 static int __devinit advansys_vlb_probe(struct device *dev, unsigned int id)
14349 PortAddr iop_base = _asc_def_iop_base[id];
14350 struct Scsi_Host *shost;
14351 struct asc_board *board;
14353 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
14354 ASC_DBG1(1, "advansys_vlb_match: I/O port 0x%x busy\n",
14358 ASC_DBG1(1, "advansys_vlb_match: probing I/O port 0x%x\n", iop_base);
14359 if (!AscFindSignature(iop_base))
14360 goto release_region;
14362 * I don't think this condition can actually happen, but the old
14363 * driver did it, and the chances of finding a VLB setup in 2007
14364 * to do testing with is slight to none.
14366 if (AscGetChipVersion(iop_base, ASC_IS_VL) > ASC_CHIP_MAX_VER_VL)
14367 goto release_region;
14370 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
14372 goto release_region;
14374 board = shost_priv(shost);
14375 board->irq = advansys_vlb_irq_no(iop_base);
14378 err = advansys_board_found(shost, iop_base, ASC_IS_VL);
14382 dev_set_drvdata(dev, shost);
14386 scsi_host_put(shost);
14388 release_region(iop_base, ASC_IOADR_GAP);
14392 static struct isa_driver advansys_vlb_driver = {
14393 .probe = advansys_vlb_probe,
14394 .remove = __devexit_p(advansys_isa_remove),
14396 .owner = THIS_MODULE,
14397 .name = "advansys_vlb",
14401 static struct eisa_device_id advansys_eisa_table[] __devinitdata = {
14407 MODULE_DEVICE_TABLE(eisa, advansys_eisa_table);
14410 * EISA is a little more tricky than PCI; each EISA device may have two
14411 * channels, and this driver is written to make each channel its own Scsi_Host
14413 struct eisa_scsi_data {
14414 struct Scsi_Host *host[2];
14418 * The EISA IRQ number is found in bits 8 to 10 of the CfgLsw. It decodes as:
14428 static unsigned int __devinit advansys_eisa_irq_no(struct eisa_device *edev)
14430 unsigned short cfg_lsw = inw(edev->base_addr + 0xc86);
14431 unsigned int chip_irq = ((cfg_lsw >> 8) & 0x07) + 10;
14432 if ((chip_irq == 13) || (chip_irq > 15))
14437 static int __devinit advansys_eisa_probe(struct device *dev)
14439 int i, ioport, irq = 0;
14441 struct eisa_device *edev = to_eisa_device(dev);
14442 struct eisa_scsi_data *data;
14445 data = kzalloc(sizeof(*data), GFP_KERNEL);
14448 ioport = edev->base_addr + 0xc30;
14451 for (i = 0; i < 2; i++, ioport += 0x20) {
14452 struct asc_board *board;
14453 struct Scsi_Host *shost;
14454 if (!request_region(ioport, ASC_IOADR_GAP, DRV_NAME)) {
14455 printk(KERN_WARNING "Region %x-%x busy\n", ioport,
14456 ioport + ASC_IOADR_GAP - 1);
14459 if (!AscFindSignature(ioport)) {
14460 release_region(ioport, ASC_IOADR_GAP);
14465 * I don't know why we need to do this for EISA chips, but
14466 * not for any others. It looks to be equivalent to
14467 * AscGetChipCfgMsw, but I may have overlooked something,
14468 * so I'm not converting it until I get an EISA board to
14474 irq = advansys_eisa_irq_no(edev);
14477 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
14479 goto release_region;
14481 board = shost_priv(shost);
14485 err = advansys_board_found(shost, ioport, ASC_IS_EISA);
14487 data->host[i] = shost;
14491 scsi_host_put(shost);
14493 release_region(ioport, ASC_IOADR_GAP);
14499 dev_set_drvdata(dev, data);
14503 kfree(data->host[0]);
14504 kfree(data->host[1]);
14510 static __devexit int advansys_eisa_remove(struct device *dev)
14513 struct eisa_scsi_data *data = dev_get_drvdata(dev);
14515 for (i = 0; i < 2; i++) {
14517 struct Scsi_Host *shost = data->host[i];
14520 ioport = shost->io_port;
14521 advansys_release(shost);
14522 release_region(ioport, ASC_IOADR_GAP);
14529 static struct eisa_driver advansys_eisa_driver = {
14530 .id_table = advansys_eisa_table,
14533 .probe = advansys_eisa_probe,
14534 .remove = __devexit_p(advansys_eisa_remove),
14538 /* PCI Devices supported by this driver */
14539 static struct pci_device_id advansys_pci_tbl[] __devinitdata = {
14540 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_1200A,
14541 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14542 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940,
14543 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14544 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940U,
14545 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14546 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940UW,
14547 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14548 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C0800_REV1,
14549 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14550 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C1600_REV1,
14551 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14555 MODULE_DEVICE_TABLE(pci, advansys_pci_tbl);
14557 static void __devinit advansys_set_latency(struct pci_dev *pdev)
14559 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
14560 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
14561 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0);
14564 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency);
14565 if (latency < 0x20)
14566 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20);
14570 static int __devinit
14571 advansys_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
14574 struct Scsi_Host *shost;
14575 struct asc_board *board;
14577 err = pci_enable_device(pdev);
14580 err = pci_request_regions(pdev, DRV_NAME);
14582 goto disable_device;
14583 pci_set_master(pdev);
14584 advansys_set_latency(pdev);
14587 if (pci_resource_len(pdev, 0) == 0)
14588 goto release_region;
14590 ioport = pci_resource_start(pdev, 0);
14593 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
14595 goto release_region;
14597 board = shost_priv(shost);
14598 board->irq = pdev->irq;
14599 board->dev = &pdev->dev;
14601 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW ||
14602 pdev->device == PCI_DEVICE_ID_38C0800_REV1 ||
14603 pdev->device == PCI_DEVICE_ID_38C1600_REV1) {
14604 board->flags |= ASC_IS_WIDE_BOARD;
14607 err = advansys_board_found(shost, ioport, ASC_IS_PCI);
14611 pci_set_drvdata(pdev, shost);
14615 scsi_host_put(shost);
14617 pci_release_regions(pdev);
14619 pci_disable_device(pdev);
14624 static void __devexit advansys_pci_remove(struct pci_dev *pdev)
14626 advansys_release(pci_get_drvdata(pdev));
14627 pci_release_regions(pdev);
14628 pci_disable_device(pdev);
14631 static struct pci_driver advansys_pci_driver = {
14633 .id_table = advansys_pci_tbl,
14634 .probe = advansys_pci_probe,
14635 .remove = __devexit_p(advansys_pci_remove),
14638 static int __init advansys_init(void)
14642 error = isa_register_driver(&advansys_isa_driver,
14643 ASC_IOADR_TABLE_MAX_IX);
14647 error = isa_register_driver(&advansys_vlb_driver,
14648 ASC_IOADR_TABLE_MAX_IX);
14650 goto unregister_isa;
14652 error = eisa_driver_register(&advansys_eisa_driver);
14654 goto unregister_vlb;
14656 error = pci_register_driver(&advansys_pci_driver);
14658 goto unregister_eisa;
14663 eisa_driver_unregister(&advansys_eisa_driver);
14665 isa_unregister_driver(&advansys_vlb_driver);
14667 isa_unregister_driver(&advansys_isa_driver);
14672 static void __exit advansys_exit(void)
14674 pci_unregister_driver(&advansys_pci_driver);
14675 eisa_driver_unregister(&advansys_eisa_driver);
14676 isa_unregister_driver(&advansys_vlb_driver);
14677 isa_unregister_driver(&advansys_isa_driver);
14680 module_init(advansys_init);
14681 module_exit(advansys_exit);
14683 MODULE_LICENSE("GPL");