1 #define DRV_NAME "advansys"
2 #define ASC_VERSION "3.4" /* AdvanSys Driver Version */
5 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
7 * Copyright (c) 1995-2000 Advanced System Products, Inc.
8 * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
9 * Copyright (c) 2007 Matthew Wilcox <matthew@wil.cx>
10 * All Rights Reserved.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
19 * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
20 * changed its name to ConnectCom Solutions, Inc.
21 * On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets
24 #include <linux/module.h>
25 #include <linux/string.h>
26 #include <linux/kernel.h>
27 #include <linux/types.h>
28 #include <linux/ioport.h>
29 #include <linux/interrupt.h>
30 #include <linux/delay.h>
31 #include <linux/slab.h>
33 #include <linux/proc_fs.h>
34 #include <linux/init.h>
35 #include <linux/blkdev.h>
36 #include <linux/isa.h>
37 #include <linux/eisa.h>
38 #include <linux/pci.h>
39 #include <linux/spinlock.h>
40 #include <linux/dma-mapping.h>
43 #include <asm/system.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <scsi/scsi_device.h>
48 #include <scsi/scsi_tcq.h>
49 #include <scsi/scsi.h>
50 #include <scsi/scsi_host.h>
54 * 1. Although all of the necessary command mapping places have the
55 * appropriate dma_map.. APIs, the driver still processes its internal
56 * queue using bus_to_virt() and virt_to_bus() which are illegal under
57 * the API. The entire queue processing structure will need to be
58 * altered to fix this.
59 * 2. Need to add memory mapping workaround. Test the memory mapping.
60 * If it doesn't work revert to I/O port access. Can a test be done
62 * 3. Handle an interrupt not working. Keep an interrupt counter in
63 * the interrupt handler. In the timeout function if the interrupt
64 * has not occurred then print a message and run in polled mode.
65 * 4. Need to add support for target mode commands, cf. CAM XPT.
66 * 5. check DMA mapping functions for failure
67 * 6. Use scsi_transport_spi
68 * 7. advansys_info is not safe against multiple simultaneous callers
70 * 9. Add module_param to override ISA/VLB ioport array
72 #warning this driver is still not properly converted to the DMA API
74 /* Enable driver /proc statistics. */
75 #define ADVANSYS_STATS
77 /* Enable driver tracing. */
78 /* #define ADVANSYS_DEBUG */
80 #define ASC_LIB_VERSION_MAJOR 1
81 #define ASC_LIB_VERSION_MINOR 24
82 #define ASC_LIB_SERIAL_NUMBER 123
87 * Any instance where a 32-bit long or pointer type is assumed
88 * for precision or HW defined structures, the following define
89 * types must be used. In Linux the char, short, and int types
90 * are all consistent at 8, 16, and 32 bits respectively. Pointers
91 * and long types are 64 bits on Alpha and UltraSPARC.
93 #define ASC_PADDR __u32 /* Physical/Bus address data type. */
94 #define ASC_VADDR __u32 /* Virtual address data type. */
95 #define ASC_DCNT __u32 /* Unsigned Data count type. */
96 #define ASC_SDCNT __s32 /* Signed Data count type. */
99 * These macros are used to convert a virtual address to a
100 * 32-bit value. This currently can be used on Linux Alpha
101 * which uses 64-bit virtual address but a 32-bit bus address.
102 * This is likely to break in the future, but doing this now
103 * will give us time to change the HW and FW to handle 64-bit
106 #define ASC_VADDR_TO_U32 virt_to_bus
107 #define ASC_U32_TO_VADDR bus_to_virt
109 typedef unsigned char uchar;
119 #define UW_ERR (uint)(0xFFFF)
120 #define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0)
122 #define PCI_VENDOR_ID_ASP 0x10cd
123 #define PCI_DEVICE_ID_ASP_1200A 0x1100
124 #define PCI_DEVICE_ID_ASP_ABP940 0x1200
125 #define PCI_DEVICE_ID_ASP_ABP940U 0x1300
126 #define PCI_DEVICE_ID_ASP_ABP940UW 0x2300
127 #define PCI_DEVICE_ID_38C0800_REV1 0x2500
128 #define PCI_DEVICE_ID_38C1600_REV1 0x2700
131 * Enable CC_VERY_LONG_SG_LIST to support up to 64K element SG lists.
132 * The SRB structure will have to be changed and the ASC_SRB2SCSIQ()
133 * macro re-defined to be able to obtain a ASC_SCSI_Q pointer from the
136 #define CC_VERY_LONG_SG_LIST 0
137 #define ASC_SRB2SCSIQ(srb_ptr) (srb_ptr)
139 #define PortAddr unsigned short /* port address size */
140 #define inp(port) inb(port)
141 #define outp(port, byte) outb((byte), (port))
143 #define inpw(port) inw(port)
144 #define outpw(port, word) outw((word), (port))
146 #define ASC_MAX_SG_QUEUE 7
147 #define ASC_MAX_SG_LIST 255
149 #define ASC_CS_TYPE unsigned short
151 #define ASC_IS_ISA (0x0001)
152 #define ASC_IS_ISAPNP (0x0081)
153 #define ASC_IS_EISA (0x0002)
154 #define ASC_IS_PCI (0x0004)
155 #define ASC_IS_PCI_ULTRA (0x0104)
156 #define ASC_IS_PCMCIA (0x0008)
157 #define ASC_IS_MCA (0x0020)
158 #define ASC_IS_VL (0x0040)
159 #define ASC_IS_WIDESCSI_16 (0x0100)
160 #define ASC_IS_WIDESCSI_32 (0x0200)
161 #define ASC_IS_BIG_ENDIAN (0x8000)
163 #define ASC_CHIP_MIN_VER_VL (0x01)
164 #define ASC_CHIP_MAX_VER_VL (0x07)
165 #define ASC_CHIP_MIN_VER_PCI (0x09)
166 #define ASC_CHIP_MAX_VER_PCI (0x0F)
167 #define ASC_CHIP_VER_PCI_BIT (0x08)
168 #define ASC_CHIP_MIN_VER_ISA (0x11)
169 #define ASC_CHIP_MIN_VER_ISA_PNP (0x21)
170 #define ASC_CHIP_MAX_VER_ISA (0x27)
171 #define ASC_CHIP_VER_ISA_BIT (0x30)
172 #define ASC_CHIP_VER_ISAPNP_BIT (0x20)
173 #define ASC_CHIP_VER_ASYN_BUG (0x21)
174 #define ASC_CHIP_VER_PCI 0x08
175 #define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02)
176 #define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03)
177 #define ASC_CHIP_MIN_VER_EISA (0x41)
178 #define ASC_CHIP_MAX_VER_EISA (0x47)
179 #define ASC_CHIP_VER_EISA_BIT (0x40)
180 #define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
181 #define ASC_MAX_VL_DMA_COUNT (0x07FFFFFFL)
182 #define ASC_MAX_PCI_DMA_COUNT (0xFFFFFFFFL)
183 #define ASC_MAX_ISA_DMA_COUNT (0x00FFFFFFL)
185 #define ASC_SCSI_ID_BITS 3
186 #define ASC_SCSI_TIX_TYPE uchar
187 #define ASC_ALL_DEVICE_BIT_SET 0xFF
188 #define ASC_SCSI_BIT_ID_TYPE uchar
189 #define ASC_MAX_TID 7
190 #define ASC_MAX_LUN 7
191 #define ASC_SCSI_WIDTH_BIT_SET 0xFF
192 #define ASC_MAX_SENSE_LEN 32
193 #define ASC_MIN_SENSE_LEN 14
194 #define ASC_SCSI_RESET_HOLD_TIME_US 60
197 * Narrow boards only support 12-byte commands, while wide boards
198 * extend to 16-byte commands.
200 #define ASC_MAX_CDB_LEN 12
201 #define ADV_MAX_CDB_LEN 16
203 #define MS_SDTR_LEN 0x03
204 #define MS_WDTR_LEN 0x02
206 #define ASC_SG_LIST_PER_Q 7
208 #define QS_READY 0x01
209 #define QS_DISC1 0x02
210 #define QS_DISC2 0x04
212 #define QS_ABORTED 0x40
214 #define QC_NO_CALLBACK 0x01
215 #define QC_SG_SWAP_QUEUE 0x02
216 #define QC_SG_HEAD 0x04
217 #define QC_DATA_IN 0x08
218 #define QC_DATA_OUT 0x10
219 #define QC_URGENT 0x20
220 #define QC_MSG_OUT 0x40
221 #define QC_REQ_SENSE 0x80
222 #define QCSG_SG_XFER_LIST 0x02
223 #define QCSG_SG_XFER_MORE 0x04
224 #define QCSG_SG_XFER_END 0x08
225 #define QD_IN_PROGRESS 0x00
226 #define QD_NO_ERROR 0x01
227 #define QD_ABORTED_BY_HOST 0x02
228 #define QD_WITH_ERROR 0x04
229 #define QD_INVALID_REQUEST 0x80
230 #define QD_INVALID_HOST_NUM 0x81
231 #define QD_INVALID_DEVICE 0x82
232 #define QD_ERR_INTERNAL 0xFF
233 #define QHSTA_NO_ERROR 0x00
234 #define QHSTA_M_SEL_TIMEOUT 0x11
235 #define QHSTA_M_DATA_OVER_RUN 0x12
236 #define QHSTA_M_DATA_UNDER_RUN 0x12
237 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
238 #define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14
239 #define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
240 #define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22
241 #define QHSTA_D_HOST_ABORT_FAILED 0x23
242 #define QHSTA_D_EXE_SCSI_Q_FAILED 0x24
243 #define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
244 #define QHSTA_D_ASPI_NO_BUF_POOL 0x26
245 #define QHSTA_M_WTM_TIMEOUT 0x41
246 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
247 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
248 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
249 #define QHSTA_M_TARGET_STATUS_BUSY 0x45
250 #define QHSTA_M_BAD_TAG_CODE 0x46
251 #define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47
252 #define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
253 #define QHSTA_D_LRAM_CMP_ERROR 0x81
254 #define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
255 #define ASC_FLAG_SCSIQ_REQ 0x01
256 #define ASC_FLAG_BIOS_SCSIQ_REQ 0x02
257 #define ASC_FLAG_BIOS_ASYNC_IO 0x04
258 #define ASC_FLAG_SRB_LINEAR_ADDR 0x08
259 #define ASC_FLAG_WIN16 0x10
260 #define ASC_FLAG_WIN32 0x20
261 #define ASC_FLAG_ISA_OVER_16MB 0x40
262 #define ASC_FLAG_DOS_VM_CALLBACK 0x80
263 #define ASC_TAG_FLAG_EXTRA_BYTES 0x10
264 #define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04
265 #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08
266 #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
267 #define ASC_SCSIQ_CPY_BEG 4
268 #define ASC_SCSIQ_SGHD_CPY_BEG 2
269 #define ASC_SCSIQ_B_FWD 0
270 #define ASC_SCSIQ_B_BWD 1
271 #define ASC_SCSIQ_B_STATUS 2
272 #define ASC_SCSIQ_B_QNO 3
273 #define ASC_SCSIQ_B_CNTL 4
274 #define ASC_SCSIQ_B_SG_QUEUE_CNT 5
275 #define ASC_SCSIQ_D_DATA_ADDR 8
276 #define ASC_SCSIQ_D_DATA_CNT 12
277 #define ASC_SCSIQ_B_SENSE_LEN 20
278 #define ASC_SCSIQ_DONE_INFO_BEG 22
279 #define ASC_SCSIQ_D_SRBPTR 22
280 #define ASC_SCSIQ_B_TARGET_IX 26
281 #define ASC_SCSIQ_B_CDB_LEN 28
282 #define ASC_SCSIQ_B_TAG_CODE 29
283 #define ASC_SCSIQ_W_VM_ID 30
284 #define ASC_SCSIQ_DONE_STATUS 32
285 #define ASC_SCSIQ_HOST_STATUS 33
286 #define ASC_SCSIQ_SCSI_STATUS 34
287 #define ASC_SCSIQ_CDB_BEG 36
288 #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
289 #define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60
290 #define ASC_SCSIQ_B_FIRST_SG_WK_QP 48
291 #define ASC_SCSIQ_B_SG_WK_QP 49
292 #define ASC_SCSIQ_B_SG_WK_IX 50
293 #define ASC_SCSIQ_W_ALT_DC1 52
294 #define ASC_SCSIQ_B_LIST_CNT 6
295 #define ASC_SCSIQ_B_CUR_LIST_CNT 7
296 #define ASC_SGQ_B_SG_CNTL 4
297 #define ASC_SGQ_B_SG_HEAD_QP 5
298 #define ASC_SGQ_B_SG_LIST_CNT 6
299 #define ASC_SGQ_B_SG_CUR_LIST_CNT 7
300 #define ASC_SGQ_LIST_BEG 8
301 #define ASC_DEF_SCSI1_QNG 4
302 #define ASC_MAX_SCSI1_QNG 4
303 #define ASC_DEF_SCSI2_QNG 16
304 #define ASC_MAX_SCSI2_QNG 32
305 #define ASC_TAG_CODE_MASK 0x23
306 #define ASC_STOP_REQ_RISC_STOP 0x01
307 #define ASC_STOP_ACK_RISC_STOP 0x03
308 #define ASC_STOP_CLEAN_UP_BUSY_Q 0x10
309 #define ASC_STOP_CLEAN_UP_DISC_Q 0x20
310 #define ASC_STOP_HOST_REQ_RISC_HALT 0x40
311 #define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
312 #define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
313 #define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID))
314 #define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID)
315 #define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID)
316 #define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
317 #define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6))
319 typedef struct asc_scsiq_1 {
328 ASC_PADDR sense_addr;
333 typedef struct asc_scsiq_2 {
342 typedef struct asc_scsiq_3 {
349 typedef struct asc_scsiq_4 {
350 uchar cdb[ASC_MAX_CDB_LEN];
351 uchar y_first_sg_list_qp;
352 uchar y_working_sg_qp;
353 uchar y_working_sg_ix;
356 ushort x_reconnect_rtn;
357 ASC_PADDR x_saved_data_addr;
358 ASC_DCNT x_saved_data_cnt;
361 typedef struct asc_q_done_info {
370 ASC_DCNT remain_bytes;
373 typedef struct asc_sg_list {
378 typedef struct asc_sg_head {
381 ushort entry_to_copy;
383 ASC_SG_LIST sg_list[0];
386 typedef struct asc_scsi_q {
390 ASC_SG_HEAD *sg_head;
391 ushort remain_sg_entry_cnt;
392 ushort next_sg_index;
395 typedef struct asc_scsi_req_q {
399 ASC_SG_HEAD *sg_head;
402 uchar cdb[ASC_MAX_CDB_LEN];
403 uchar sense[ASC_MIN_SENSE_LEN];
406 typedef struct asc_scsi_bios_req_q {
410 ASC_SG_HEAD *sg_head;
413 uchar cdb[ASC_MAX_CDB_LEN];
414 uchar sense[ASC_MIN_SENSE_LEN];
415 } ASC_SCSI_BIOS_REQ_Q;
417 typedef struct asc_risc_q {
426 typedef struct asc_sg_list_q {
432 uchar sg_cur_list_cnt;
435 typedef struct asc_risc_sg_list_q {
439 ASC_SG_LIST sg_list[7];
440 } ASC_RISC_SG_LIST_Q;
442 #define ASCQ_ERR_Q_STATUS 0x0D
443 #define ASCQ_ERR_CUR_QNG 0x17
444 #define ASCQ_ERR_SG_Q_LINKS 0x18
445 #define ASCQ_ERR_ISR_RE_ENTRY 0x1A
446 #define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B
447 #define ASCQ_ERR_ISR_ON_CRITICAL 0x1C
450 * Warning code values are set in ASC_DVC_VAR 'warn_code'.
452 #define ASC_WARN_NO_ERROR 0x0000
453 #define ASC_WARN_IO_PORT_ROTATE 0x0001
454 #define ASC_WARN_EEPROM_CHKSUM 0x0002
455 #define ASC_WARN_IRQ_MODIFIED 0x0004
456 #define ASC_WARN_AUTO_CONFIG 0x0008
457 #define ASC_WARN_CMD_QNG_CONFLICT 0x0010
458 #define ASC_WARN_EEPROM_RECOVER 0x0020
459 #define ASC_WARN_CFG_MSW_RECOVER 0x0040
462 * Error code values are set in ASC_DVC_VAR 'err_code'.
464 #define ASC_IERR_WRITE_EEPROM 0x0001
465 #define ASC_IERR_MCODE_CHKSUM 0x0002
466 #define ASC_IERR_SET_PC_ADDR 0x0004
467 #define ASC_IERR_START_STOP_CHIP 0x0008
468 #define ASC_IERR_IRQ_NO 0x0010
469 #define ASC_IERR_SET_IRQ_NO 0x0020
470 #define ASC_IERR_CHIP_VERSION 0x0040
471 #define ASC_IERR_SET_SCSI_ID 0x0080
472 #define ASC_IERR_GET_PHY_ADDR 0x0100
473 #define ASC_IERR_BAD_SIGNATURE 0x0200
474 #define ASC_IERR_NO_BUS_TYPE 0x0400
475 #define ASC_IERR_SCAM 0x0800
476 #define ASC_IERR_SET_SDTR 0x1000
477 #define ASC_IERR_RW_LRAM 0x8000
479 #define ASC_MAX_IRQ_NO 15
480 #define ASC_MIN_IRQ_NO 10
481 #define ASC_DEF_MAX_TOTAL_QNG (0xF0)
482 #define ASC_MIN_TAG_Q_PER_DVC (0x04)
483 #define ASC_MIN_FREE_Q (0x02)
484 #define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
485 #define ASC_MAX_TOTAL_QNG 240
486 #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
487 #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8
488 #define ASC_MAX_PCI_INRAM_TOTAL_QNG 20
489 #define ASC_MAX_INRAM_TAG_QNG 16
490 #define ASC_IOADR_GAP 0x10
491 #define ASC_MAX_SYN_XFER_NO 16
492 #define ASC_SYN_MAX_OFFSET 0x0F
493 #define ASC_DEF_SDTR_OFFSET 0x0F
494 #define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02
495 #define SYN_XFER_NS_0 25
496 #define SYN_XFER_NS_1 30
497 #define SYN_XFER_NS_2 35
498 #define SYN_XFER_NS_3 40
499 #define SYN_XFER_NS_4 50
500 #define SYN_XFER_NS_5 60
501 #define SYN_XFER_NS_6 70
502 #define SYN_XFER_NS_7 85
503 #define SYN_ULTRA_XFER_NS_0 12
504 #define SYN_ULTRA_XFER_NS_1 19
505 #define SYN_ULTRA_XFER_NS_2 25
506 #define SYN_ULTRA_XFER_NS_3 32
507 #define SYN_ULTRA_XFER_NS_4 38
508 #define SYN_ULTRA_XFER_NS_5 44
509 #define SYN_ULTRA_XFER_NS_6 50
510 #define SYN_ULTRA_XFER_NS_7 57
511 #define SYN_ULTRA_XFER_NS_8 63
512 #define SYN_ULTRA_XFER_NS_9 69
513 #define SYN_ULTRA_XFER_NS_10 75
514 #define SYN_ULTRA_XFER_NS_11 82
515 #define SYN_ULTRA_XFER_NS_12 88
516 #define SYN_ULTRA_XFER_NS_13 94
517 #define SYN_ULTRA_XFER_NS_14 100
518 #define SYN_ULTRA_XFER_NS_15 107
520 typedef struct ext_msg {
526 uchar sdtr_xfer_period;
527 uchar sdtr_req_ack_offset;
542 #define xfer_period u_ext_msg.sdtr.sdtr_xfer_period
543 #define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset
544 #define wdtr_width u_ext_msg.wdtr.wdtr_width
545 #define mdp_b3 u_ext_msg.mdp_b3
546 #define mdp_b2 u_ext_msg.mdp_b2
547 #define mdp_b1 u_ext_msg.mdp_b1
548 #define mdp_b0 u_ext_msg.mdp_b0
550 typedef struct asc_dvc_cfg {
551 ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
552 ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
553 ASC_SCSI_BIT_ID_TYPE disc_enable;
554 ASC_SCSI_BIT_ID_TYPE sdtr_enable;
557 uchar isa_dma_channel;
559 ushort lib_serial_no;
562 ushort mcode_version;
563 uchar max_tag_qng[ASC_MAX_TID + 1];
565 uchar sdtr_period_offset[ASC_MAX_TID + 1];
566 uchar adapter_info[6];
569 #define ASC_DEF_DVC_CNTL 0xFFFF
570 #define ASC_DEF_CHIP_SCSI_ID 7
571 #define ASC_DEF_ISA_DMA_SPEED 4
572 #define ASC_INIT_STATE_BEG_GET_CFG 0x0001
573 #define ASC_INIT_STATE_END_GET_CFG 0x0002
574 #define ASC_INIT_STATE_BEG_SET_CFG 0x0004
575 #define ASC_INIT_STATE_END_SET_CFG 0x0008
576 #define ASC_INIT_STATE_BEG_LOAD_MC 0x0010
577 #define ASC_INIT_STATE_END_LOAD_MC 0x0020
578 #define ASC_INIT_STATE_BEG_INQUIRY 0x0040
579 #define ASC_INIT_STATE_END_INQUIRY 0x0080
580 #define ASC_INIT_RESET_SCSI_DONE 0x0100
581 #define ASC_INIT_STATE_WITHOUT_EEP 0x8000
582 #define ASC_BUG_FIX_IF_NOT_DWB 0x0001
583 #define ASC_BUG_FIX_ASYN_USE_SYN 0x0002
584 #define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
585 #define ASC_MIN_TAGGED_CMD 7
586 #define ASC_MAX_SCSI_RESET_WAIT 30
588 struct asc_dvc_var; /* Forward Declaration. */
590 typedef struct asc_dvc_var {
596 ASC_SCSI_BIT_ID_TYPE init_sdtr;
597 ASC_SCSI_BIT_ID_TYPE sdtr_done;
598 ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
599 ASC_SCSI_BIT_ID_TYPE unit_not_ready;
600 ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
601 ASC_SCSI_BIT_ID_TYPE start_motor;
602 uchar scsi_reset_wait;
607 uchar in_critical_cnt;
609 uchar last_q_shortage;
611 uchar cur_dvc_qng[ASC_MAX_TID + 1];
612 uchar max_dvc_qng[ASC_MAX_TID + 1];
613 ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
614 ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
615 uchar sdtr_period_tbl[ASC_MAX_SYN_XFER_NO];
617 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
620 uchar dos_int13_table[ASC_MAX_TID + 1];
621 ASC_DCNT max_dma_count;
622 ASC_SCSI_BIT_ID_TYPE no_scam;
623 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
624 uchar max_sdtr_index;
625 uchar host_init_sdtr_index;
626 struct asc_board *drv_ptr;
630 typedef struct asc_dvc_inq_info {
631 uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
634 typedef struct asc_cap_info {
639 typedef struct asc_cap_info_array {
640 ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
641 } ASC_CAP_INFO_ARRAY;
643 #define ASC_MCNTL_NO_SEL_TIMEOUT (ushort)0x0001
644 #define ASC_MCNTL_NULL_TARGET (ushort)0x0002
645 #define ASC_CNTL_INITIATOR (ushort)0x0001
646 #define ASC_CNTL_BIOS_GT_1GB (ushort)0x0002
647 #define ASC_CNTL_BIOS_GT_2_DISK (ushort)0x0004
648 #define ASC_CNTL_BIOS_REMOVABLE (ushort)0x0008
649 #define ASC_CNTL_NO_SCAM (ushort)0x0010
650 #define ASC_CNTL_INT_MULTI_Q (ushort)0x0080
651 #define ASC_CNTL_NO_LUN_SUPPORT (ushort)0x0040
652 #define ASC_CNTL_NO_VERIFY_COPY (ushort)0x0100
653 #define ASC_CNTL_RESET_SCSI (ushort)0x0200
654 #define ASC_CNTL_INIT_INQUIRY (ushort)0x0400
655 #define ASC_CNTL_INIT_VERBOSE (ushort)0x0800
656 #define ASC_CNTL_SCSI_PARITY (ushort)0x1000
657 #define ASC_CNTL_BURST_MODE (ushort)0x2000
658 #define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
659 #define ASC_EEP_DVC_CFG_BEG_VL 2
660 #define ASC_EEP_MAX_DVC_ADDR_VL 15
661 #define ASC_EEP_DVC_CFG_BEG 32
662 #define ASC_EEP_MAX_DVC_ADDR 45
663 #define ASC_EEP_MAX_RETRY 20
666 * These macros keep the chip SCSI id and ISA DMA speed
667 * bitfields in board order. C bitfields aren't portable
668 * between big and little-endian platforms so they are
672 #define ASC_EEP_GET_CHIP_ID(cfg) ((cfg)->id_speed & 0x0f)
673 #define ASC_EEP_GET_DMA_SPD(cfg) (((cfg)->id_speed & 0xf0) >> 4)
674 #define ASC_EEP_SET_CHIP_ID(cfg, sid) \
675 ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
676 #define ASC_EEP_SET_DMA_SPD(cfg, spd) \
677 ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
679 typedef struct asceep_config {
691 uchar id_speed; /* low order 4 bits is chip scsi id */
692 /* high order 4 bits is isa dma speed */
693 uchar dos_int13_table[ASC_MAX_TID + 1];
694 uchar adapter_info[6];
699 #define ASC_EEP_CMD_READ 0x80
700 #define ASC_EEP_CMD_WRITE 0x40
701 #define ASC_EEP_CMD_WRITE_ABLE 0x30
702 #define ASC_EEP_CMD_WRITE_DISABLE 0x00
703 #define ASC_OVERRUN_BSIZE 0x00000048UL
704 #define ASCV_MSGOUT_BEG 0x0000
705 #define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
706 #define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
707 #define ASCV_BREAK_SAVED_CODE (ushort)0x0006
708 #define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8)
709 #define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3)
710 #define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4)
711 #define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8)
712 #define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8)
713 #define ASCV_MAX_DVC_QNG_BEG (ushort)0x0020
714 #define ASCV_BREAK_ADDR (ushort)0x0028
715 #define ASCV_BREAK_NOTIFY_COUNT (ushort)0x002A
716 #define ASCV_BREAK_CONTROL (ushort)0x002C
717 #define ASCV_BREAK_HIT_COUNT (ushort)0x002E
719 #define ASCV_ASCDVC_ERR_CODE_W (ushort)0x0030
720 #define ASCV_MCODE_CHKSUM_W (ushort)0x0032
721 #define ASCV_MCODE_SIZE_W (ushort)0x0034
722 #define ASCV_STOP_CODE_B (ushort)0x0036
723 #define ASCV_DVC_ERR_CODE_B (ushort)0x0037
724 #define ASCV_OVERRUN_PADDR_D (ushort)0x0038
725 #define ASCV_OVERRUN_BSIZE_D (ushort)0x003C
726 #define ASCV_HALTCODE_W (ushort)0x0040
727 #define ASCV_CHKSUM_W (ushort)0x0042
728 #define ASCV_MC_DATE_W (ushort)0x0044
729 #define ASCV_MC_VER_W (ushort)0x0046
730 #define ASCV_NEXTRDY_B (ushort)0x0048
731 #define ASCV_DONENEXT_B (ushort)0x0049
732 #define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
733 #define ASCV_SCSIBUSY_B (ushort)0x004B
734 #define ASCV_Q_DONE_IN_PROGRESS_B (ushort)0x004C
735 #define ASCV_CURCDB_B (ushort)0x004D
736 #define ASCV_RCLUN_B (ushort)0x004E
737 #define ASCV_BUSY_QHEAD_B (ushort)0x004F
738 #define ASCV_DISC1_QHEAD_B (ushort)0x0050
739 #define ASCV_DISC_ENABLE_B (ushort)0x0052
740 #define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
741 #define ASCV_HOSTSCSI_ID_B (ushort)0x0055
742 #define ASCV_MCODE_CNTL_B (ushort)0x0056
743 #define ASCV_NULL_TARGET_B (ushort)0x0057
744 #define ASCV_FREE_Q_HEAD_W (ushort)0x0058
745 #define ASCV_DONE_Q_TAIL_W (ushort)0x005A
746 #define ASCV_FREE_Q_HEAD_B (ushort)(ASCV_FREE_Q_HEAD_W+1)
747 #define ASCV_DONE_Q_TAIL_B (ushort)(ASCV_DONE_Q_TAIL_W+1)
748 #define ASCV_HOST_FLAG_B (ushort)0x005D
749 #define ASCV_TOTAL_READY_Q_B (ushort)0x0064
750 #define ASCV_VER_SERIAL_B (ushort)0x0065
751 #define ASCV_HALTCODE_SAVED_W (ushort)0x0066
752 #define ASCV_WTM_FLAG_B (ushort)0x0068
753 #define ASCV_RISC_FLAG_B (ushort)0x006A
754 #define ASCV_REQ_SG_LIST_QP (ushort)0x006B
755 #define ASC_HOST_FLAG_IN_ISR 0x01
756 #define ASC_HOST_FLAG_ACK_INT 0x02
757 #define ASC_RISC_FLAG_GEN_INT 0x01
758 #define ASC_RISC_FLAG_REQ_SG_LIST 0x02
759 #define IOP_CTRL (0x0F)
760 #define IOP_STATUS (0x0E)
761 #define IOP_INT_ACK IOP_STATUS
762 #define IOP_REG_IFC (0x0D)
763 #define IOP_SYN_OFFSET (0x0B)
764 #define IOP_EXTRA_CONTROL (0x0D)
765 #define IOP_REG_PC (0x0C)
766 #define IOP_RAM_ADDR (0x0A)
767 #define IOP_RAM_DATA (0x08)
768 #define IOP_EEP_DATA (0x06)
769 #define IOP_EEP_CMD (0x07)
770 #define IOP_VERSION (0x03)
771 #define IOP_CONFIG_HIGH (0x04)
772 #define IOP_CONFIG_LOW (0x02)
773 #define IOP_SIG_BYTE (0x01)
774 #define IOP_SIG_WORD (0x00)
775 #define IOP_REG_DC1 (0x0E)
776 #define IOP_REG_DC0 (0x0C)
777 #define IOP_REG_SB (0x0B)
778 #define IOP_REG_DA1 (0x0A)
779 #define IOP_REG_DA0 (0x08)
780 #define IOP_REG_SC (0x09)
781 #define IOP_DMA_SPEED (0x07)
782 #define IOP_REG_FLAG (0x07)
783 #define IOP_FIFO_H (0x06)
784 #define IOP_FIFO_L (0x04)
785 #define IOP_REG_ID (0x05)
786 #define IOP_REG_QP (0x03)
787 #define IOP_REG_IH (0x02)
788 #define IOP_REG_IX (0x01)
789 #define IOP_REG_AX (0x00)
790 #define IFC_REG_LOCK (0x00)
791 #define IFC_REG_UNLOCK (0x09)
792 #define IFC_WR_EN_FILTER (0x10)
793 #define IFC_RD_NO_EEPROM (0x10)
794 #define IFC_SLEW_RATE (0x20)
795 #define IFC_ACT_NEG (0x40)
796 #define IFC_INP_FILTER (0x80)
797 #define IFC_INIT_DEFAULT (IFC_ACT_NEG | IFC_REG_UNLOCK)
798 #define SC_SEL (uchar)(0x80)
799 #define SC_BSY (uchar)(0x40)
800 #define SC_ACK (uchar)(0x20)
801 #define SC_REQ (uchar)(0x10)
802 #define SC_ATN (uchar)(0x08)
803 #define SC_IO (uchar)(0x04)
804 #define SC_CD (uchar)(0x02)
805 #define SC_MSG (uchar)(0x01)
806 #define SEC_SCSI_CTL (uchar)(0x80)
807 #define SEC_ACTIVE_NEGATE (uchar)(0x40)
808 #define SEC_SLEW_RATE (uchar)(0x20)
809 #define SEC_ENABLE_FILTER (uchar)(0x10)
810 #define ASC_HALT_EXTMSG_IN (ushort)0x8000
811 #define ASC_HALT_CHK_CONDITION (ushort)0x8100
812 #define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
813 #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX (ushort)0x8300
814 #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX (ushort)0x8400
815 #define ASC_HALT_SDTR_REJECTED (ushort)0x4000
816 #define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
817 #define ASC_MAX_QNO 0xF8
818 #define ASC_DATA_SEC_BEG (ushort)0x0080
819 #define ASC_DATA_SEC_END (ushort)0x0080
820 #define ASC_CODE_SEC_BEG (ushort)0x0080
821 #define ASC_CODE_SEC_END (ushort)0x0080
822 #define ASC_QADR_BEG (0x4000)
823 #define ASC_QADR_USED (ushort)(ASC_MAX_QNO * 64)
824 #define ASC_QADR_END (ushort)0x7FFF
825 #define ASC_QLAST_ADR (ushort)0x7FC0
826 #define ASC_QBLK_SIZE 0x40
827 #define ASC_BIOS_DATA_QBEG 0xF8
828 #define ASC_MIN_ACTIVE_QNO 0x01
829 #define ASC_QLINK_END 0xFF
830 #define ASC_EEPROM_WORDS 0x10
831 #define ASC_MAX_MGS_LEN 0x10
832 #define ASC_BIOS_ADDR_DEF 0xDC00
833 #define ASC_BIOS_SIZE 0x3800
834 #define ASC_BIOS_RAM_OFF 0x3800
835 #define ASC_BIOS_RAM_SIZE 0x800
836 #define ASC_BIOS_MIN_ADDR 0xC000
837 #define ASC_BIOS_MAX_ADDR 0xEC00
838 #define ASC_BIOS_BANK_SIZE 0x0400
839 #define ASC_MCODE_START_ADDR 0x0080
840 #define ASC_CFG0_HOST_INT_ON 0x0020
841 #define ASC_CFG0_BIOS_ON 0x0040
842 #define ASC_CFG0_VERA_BURST_ON 0x0080
843 #define ASC_CFG0_SCSI_PARITY_ON 0x0800
844 #define ASC_CFG1_SCSI_TARGET_ON 0x0080
845 #define ASC_CFG1_LRAM_8BITS_ON 0x0800
846 #define ASC_CFG_MSW_CLR_MASK 0x3080
847 #define CSW_TEST1 (ASC_CS_TYPE)0x8000
848 #define CSW_AUTO_CONFIG (ASC_CS_TYPE)0x4000
849 #define CSW_RESERVED1 (ASC_CS_TYPE)0x2000
850 #define CSW_IRQ_WRITTEN (ASC_CS_TYPE)0x1000
851 #define CSW_33MHZ_SELECTED (ASC_CS_TYPE)0x0800
852 #define CSW_TEST2 (ASC_CS_TYPE)0x0400
853 #define CSW_TEST3 (ASC_CS_TYPE)0x0200
854 #define CSW_RESERVED2 (ASC_CS_TYPE)0x0100
855 #define CSW_DMA_DONE (ASC_CS_TYPE)0x0080
856 #define CSW_FIFO_RDY (ASC_CS_TYPE)0x0040
857 #define CSW_EEP_READ_DONE (ASC_CS_TYPE)0x0020
858 #define CSW_HALTED (ASC_CS_TYPE)0x0010
859 #define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
860 #define CSW_PARITY_ERR (ASC_CS_TYPE)0x0004
861 #define CSW_SCSI_RESET_LATCH (ASC_CS_TYPE)0x0002
862 #define CSW_INT_PENDING (ASC_CS_TYPE)0x0001
863 #define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
864 #define CIW_INT_ACK (ASC_CS_TYPE)0x0100
865 #define CIW_TEST1 (ASC_CS_TYPE)0x0200
866 #define CIW_TEST2 (ASC_CS_TYPE)0x0400
867 #define CIW_SEL_33MHZ (ASC_CS_TYPE)0x0800
868 #define CIW_IRQ_ACT (ASC_CS_TYPE)0x1000
869 #define CC_CHIP_RESET (uchar)0x80
870 #define CC_SCSI_RESET (uchar)0x40
871 #define CC_HALT (uchar)0x20
872 #define CC_SINGLE_STEP (uchar)0x10
873 #define CC_DMA_ABLE (uchar)0x08
874 #define CC_TEST (uchar)0x04
875 #define CC_BANK_ONE (uchar)0x02
876 #define CC_DIAG (uchar)0x01
877 #define ASC_1000_ID0W 0x04C1
878 #define ASC_1000_ID0W_FIX 0x00C1
879 #define ASC_1000_ID1B 0x25
880 #define ASC_EISA_REV_IOP_MASK (0x0C83)
881 #define ASC_EISA_CFG_IOP_MASK (0x0C86)
882 #define ASC_GET_EISA_SLOT(iop) (PortAddr)((iop) & 0xF000)
883 #define INS_HALTINT (ushort)0x6281
884 #define INS_HALT (ushort)0x6280
885 #define INS_SINT (ushort)0x6200
886 #define INS_RFLAG_WTM (ushort)0x7380
887 #define ASC_MC_SAVE_CODE_WSIZE 0x500
888 #define ASC_MC_SAVE_DATA_WSIZE 0x40
890 typedef struct asc_mc_saved {
891 ushort data[ASC_MC_SAVE_DATA_WSIZE];
892 ushort code[ASC_MC_SAVE_CODE_WSIZE];
895 #define AscGetQDoneInProgress(port) AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
896 #define AscPutQDoneInProgress(port, val) AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
897 #define AscGetVarFreeQHead(port) AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
898 #define AscGetVarDoneQTail(port) AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
899 #define AscPutVarFreeQHead(port, val) AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
900 #define AscPutVarDoneQTail(port, val) AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
901 #define AscGetRiscVarFreeQHead(port) AscReadLramByte((port), ASCV_NEXTRDY_B)
902 #define AscGetRiscVarDoneQTail(port) AscReadLramByte((port), ASCV_DONENEXT_B)
903 #define AscPutRiscVarFreeQHead(port, val) AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
904 #define AscPutRiscVarDoneQTail(port, val) AscWriteLramByte((port), ASCV_DONENEXT_B, val)
905 #define AscPutMCodeSDTRDoneAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data))
906 #define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id))
907 #define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data)
908 #define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id))
909 #define AscSynIndexToPeriod(index) (uchar)(asc_dvc->sdtr_period_tbl[ (index) ])
910 #define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE)
911 #define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD)
912 #define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION)
913 #define AscGetChipCfgLsw(port) (ushort)inpw((port)+IOP_CONFIG_LOW)
914 #define AscGetChipCfgMsw(port) (ushort)inpw((port)+IOP_CONFIG_HIGH)
915 #define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data)
916 #define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data)
917 #define AscGetChipEEPCmd(port) (uchar)inp((port)+IOP_EEP_CMD)
918 #define AscSetChipEEPCmd(port, data) outp((port)+IOP_EEP_CMD, data)
919 #define AscGetChipEEPData(port) (ushort)inpw((port)+IOP_EEP_DATA)
920 #define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data)
921 #define AscGetChipLramAddr(port) (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
922 #define AscSetChipLramAddr(port, addr) outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
923 #define AscGetChipLramData(port) (ushort)inpw((port)+IOP_RAM_DATA)
924 #define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data)
925 #define AscGetChipIFC(port) (uchar)inp((port)+IOP_REG_IFC)
926 #define AscSetChipIFC(port, data) outp((port)+IOP_REG_IFC, data)
927 #define AscGetChipStatus(port) (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
928 #define AscSetChipStatus(port, cs_val) outpw((port)+IOP_STATUS, cs_val)
929 #define AscGetChipControl(port) (uchar)inp((port)+IOP_CTRL)
930 #define AscSetChipControl(port, cc_val) outp((port)+IOP_CTRL, cc_val)
931 #define AscGetChipSyn(port) (uchar)inp((port)+IOP_SYN_OFFSET)
932 #define AscSetChipSyn(port, data) outp((port)+IOP_SYN_OFFSET, data)
933 #define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data)
934 #define AscGetPCAddr(port) (ushort)inpw((port)+IOP_REG_PC)
935 #define AscIsIntPending(port) (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
936 #define AscGetChipScsiID(port) ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
937 #define AscGetExtraControl(port) (uchar)inp((port)+IOP_EXTRA_CONTROL)
938 #define AscSetExtraControl(port, data) outp((port)+IOP_EXTRA_CONTROL, data)
939 #define AscReadChipAX(port) (ushort)inpw((port)+IOP_REG_AX)
940 #define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data)
941 #define AscReadChipIX(port) (uchar)inp((port)+IOP_REG_IX)
942 #define AscWriteChipIX(port, data) outp((port)+IOP_REG_IX, data)
943 #define AscReadChipIH(port) (ushort)inpw((port)+IOP_REG_IH)
944 #define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data)
945 #define AscReadChipQP(port) (uchar)inp((port)+IOP_REG_QP)
946 #define AscWriteChipQP(port, data) outp((port)+IOP_REG_QP, data)
947 #define AscReadChipFIFO_L(port) (ushort)inpw((port)+IOP_REG_FIFO_L)
948 #define AscWriteChipFIFO_L(port, data) outpw((port)+IOP_REG_FIFO_L, data)
949 #define AscReadChipFIFO_H(port) (ushort)inpw((port)+IOP_REG_FIFO_H)
950 #define AscWriteChipFIFO_H(port, data) outpw((port)+IOP_REG_FIFO_H, data)
951 #define AscReadChipDmaSpeed(port) (uchar)inp((port)+IOP_DMA_SPEED)
952 #define AscWriteChipDmaSpeed(port, data) outp((port)+IOP_DMA_SPEED, data)
953 #define AscReadChipDA0(port) (ushort)inpw((port)+IOP_REG_DA0)
954 #define AscWriteChipDA0(port) outpw((port)+IOP_REG_DA0, data)
955 #define AscReadChipDA1(port) (ushort)inpw((port)+IOP_REG_DA1)
956 #define AscWriteChipDA1(port) outpw((port)+IOP_REG_DA1, data)
957 #define AscReadChipDC0(port) (ushort)inpw((port)+IOP_REG_DC0)
958 #define AscWriteChipDC0(port) outpw((port)+IOP_REG_DC0, data)
959 #define AscReadChipDC1(port) (ushort)inpw((port)+IOP_REG_DC1)
960 #define AscWriteChipDC1(port) outpw((port)+IOP_REG_DC1, data)
961 #define AscReadChipDvcID(port) (uchar)inp((port)+IOP_REG_ID)
962 #define AscWriteChipDvcID(port, data) outp((port)+IOP_REG_ID, data)
964 #define ADV_LIB_VERSION_MAJOR 5
965 #define ADV_LIB_VERSION_MINOR 14
968 * Define Adv Library required special types.
972 * Portable Data Types
974 * Any instance where a 32-bit long or pointer type is assumed
975 * for precision or HW defined structures, the following define
976 * types must be used. In Linux the char, short, and int types
977 * are all consistent at 8, 16, and 32 bits respectively. Pointers
978 * and long types are 64 bits on Alpha and UltraSPARC.
980 #define ADV_PADDR __u32 /* Physical address data type. */
981 #define ADV_VADDR __u32 /* Virtual address data type. */
982 #define ADV_DCNT __u32 /* Unsigned Data count type. */
983 #define ADV_SDCNT __s32 /* Signed Data count type. */
986 * These macros are used to convert a virtual address to a
987 * 32-bit value. This currently can be used on Linux Alpha
988 * which uses 64-bit virtual address but a 32-bit bus address.
989 * This is likely to break in the future, but doing this now
990 * will give us time to change the HW and FW to handle 64-bit
993 #define ADV_VADDR_TO_U32 virt_to_bus
994 #define ADV_U32_TO_VADDR bus_to_virt
996 #define AdvPortAddr void __iomem * /* Virtual memory address size */
999 * Define Adv Library required memory access macros.
1001 #define ADV_MEM_READB(addr) readb(addr)
1002 #define ADV_MEM_READW(addr) readw(addr)
1003 #define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
1004 #define ADV_MEM_WRITEW(addr, word) writew(word, addr)
1005 #define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
1007 #define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 15)
1010 * Define total number of simultaneous maximum element scatter-gather
1011 * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
1012 * maximum number of outstanding commands per wide host adapter. Each
1013 * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
1014 * elements. Allow each command to have at least one ADV_SG_BLOCK structure.
1015 * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
1016 * structures or 255 scatter-gather elements.
1019 #define ADV_TOT_SG_BLOCK ASC_DEF_MAX_HOST_QNG
1022 * Define Adv Library required maximum number of scatter-gather
1023 * elements per request.
1025 #define ADV_MAX_SG_LIST 255
1027 /* Number of SG blocks needed. */
1028 #define ADV_NUM_SG_BLOCK \
1029 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK)
1031 /* Total contiguous memory needed for SG blocks. */
1032 #define ADV_SG_TOTAL_MEM_SIZE \
1033 (sizeof(ADV_SG_BLOCK) * ADV_NUM_SG_BLOCK)
1035 #define ADV_PAGE_SIZE PAGE_SIZE
1037 #define ADV_NUM_PAGE_CROSSING \
1038 ((ADV_SG_TOTAL_MEM_SIZE + (ADV_PAGE_SIZE - 1))/ADV_PAGE_SIZE)
1040 #define ADV_EEP_DVC_CFG_BEGIN (0x00)
1041 #define ADV_EEP_DVC_CFG_END (0x15)
1042 #define ADV_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */
1043 #define ADV_EEP_MAX_WORD_ADDR (0x1E)
1045 #define ADV_EEP_DELAY_MS 100
1047 #define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */
1048 #define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */
1050 * For the ASC3550 Bit 13 is Termination Polarity control bit.
1051 * For later ICs Bit 13 controls whether the CIS (Card Information
1052 * Service Section) is loaded from EEPROM.
1054 #define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */
1055 #define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */
1059 * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
1060 * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
1061 * Function 0 will specify INT B.
1063 * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
1064 * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
1065 * Function 1 will specify INT A.
1067 #define ADV_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */
1069 typedef struct adveep_3550_config {
1070 /* Word Offset, Description */
1072 ushort cfg_lsw; /* 00 power up initialization */
1073 /* bit 13 set - Term Polarity Control */
1074 /* bit 14 set - BIOS Enable */
1075 /* bit 15 set - Big Endian Mode */
1076 ushort cfg_msw; /* 01 unused */
1077 ushort disc_enable; /* 02 disconnect enable */
1078 ushort wdtr_able; /* 03 Wide DTR able */
1079 ushort sdtr_able; /* 04 Synchronous DTR able */
1080 ushort start_motor; /* 05 send start up motor */
1081 ushort tagqng_able; /* 06 tag queuing able */
1082 ushort bios_scan; /* 07 BIOS device control */
1083 ushort scam_tolerant; /* 08 no scam */
1085 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1086 uchar bios_boot_delay; /* power up wait */
1088 uchar scsi_reset_delay; /* 10 reset delay */
1089 uchar bios_id_lun; /* first boot device scsi id & lun */
1090 /* high nibble is lun */
1091 /* low nibble is scsi id */
1093 uchar termination; /* 11 0 - automatic */
1094 /* 1 - low off / high off */
1095 /* 2 - low off / high on */
1096 /* 3 - low on / high on */
1097 /* There is no low on / high off */
1099 uchar reserved1; /* reserved byte (not used) */
1101 ushort bios_ctrl; /* 12 BIOS control bits */
1102 /* bit 0 BIOS don't act as initiator. */
1103 /* bit 1 BIOS > 1 GB support */
1104 /* bit 2 BIOS > 2 Disk Support */
1105 /* bit 3 BIOS don't support removables */
1106 /* bit 4 BIOS support bootable CD */
1107 /* bit 5 BIOS scan enabled */
1108 /* bit 6 BIOS support multiple LUNs */
1109 /* bit 7 BIOS display of message */
1110 /* bit 8 SCAM disabled */
1111 /* bit 9 Reset SCSI bus during init. */
1113 /* bit 11 No verbose initialization. */
1114 /* bit 12 SCSI parity enabled */
1118 ushort ultra_able; /* 13 ULTRA speed able */
1119 ushort reserved2; /* 14 reserved */
1120 uchar max_host_qng; /* 15 maximum host queuing */
1121 uchar max_dvc_qng; /* maximum per device queuing */
1122 ushort dvc_cntl; /* 16 control bit for driver */
1123 ushort bug_fix; /* 17 control bit for bug fix */
1124 ushort serial_number_word1; /* 18 Board serial number word 1 */
1125 ushort serial_number_word2; /* 19 Board serial number word 2 */
1126 ushort serial_number_word3; /* 20 Board serial number word 3 */
1127 ushort check_sum; /* 21 EEP check sum */
1128 uchar oem_name[16]; /* 22 OEM name */
1129 ushort dvc_err_code; /* 30 last device driver error code */
1130 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1131 ushort adv_err_addr; /* 32 last uc error address */
1132 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1133 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1134 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1135 ushort num_of_err; /* 36 number of error */
1136 } ADVEEP_3550_CONFIG;
1138 typedef struct adveep_38C0800_config {
1139 /* Word Offset, Description */
1141 ushort cfg_lsw; /* 00 power up initialization */
1142 /* bit 13 set - Load CIS */
1143 /* bit 14 set - BIOS Enable */
1144 /* bit 15 set - Big Endian Mode */
1145 ushort cfg_msw; /* 01 unused */
1146 ushort disc_enable; /* 02 disconnect enable */
1147 ushort wdtr_able; /* 03 Wide DTR able */
1148 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1149 ushort start_motor; /* 05 send start up motor */
1150 ushort tagqng_able; /* 06 tag queuing able */
1151 ushort bios_scan; /* 07 BIOS device control */
1152 ushort scam_tolerant; /* 08 no scam */
1154 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1155 uchar bios_boot_delay; /* power up wait */
1157 uchar scsi_reset_delay; /* 10 reset delay */
1158 uchar bios_id_lun; /* first boot device scsi id & lun */
1159 /* high nibble is lun */
1160 /* low nibble is scsi id */
1162 uchar termination_se; /* 11 0 - automatic */
1163 /* 1 - low off / high off */
1164 /* 2 - low off / high on */
1165 /* 3 - low on / high on */
1166 /* There is no low on / high off */
1168 uchar termination_lvd; /* 11 0 - automatic */
1169 /* 1 - low off / high off */
1170 /* 2 - low off / high on */
1171 /* 3 - low on / high on */
1172 /* There is no low on / high off */
1174 ushort bios_ctrl; /* 12 BIOS control bits */
1175 /* bit 0 BIOS don't act as initiator. */
1176 /* bit 1 BIOS > 1 GB support */
1177 /* bit 2 BIOS > 2 Disk Support */
1178 /* bit 3 BIOS don't support removables */
1179 /* bit 4 BIOS support bootable CD */
1180 /* bit 5 BIOS scan enabled */
1181 /* bit 6 BIOS support multiple LUNs */
1182 /* bit 7 BIOS display of message */
1183 /* bit 8 SCAM disabled */
1184 /* bit 9 Reset SCSI bus during init. */
1186 /* bit 11 No verbose initialization. */
1187 /* bit 12 SCSI parity enabled */
1191 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1192 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1193 uchar max_host_qng; /* 15 maximum host queueing */
1194 uchar max_dvc_qng; /* maximum per device queuing */
1195 ushort dvc_cntl; /* 16 control bit for driver */
1196 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1197 ushort serial_number_word1; /* 18 Board serial number word 1 */
1198 ushort serial_number_word2; /* 19 Board serial number word 2 */
1199 ushort serial_number_word3; /* 20 Board serial number word 3 */
1200 ushort check_sum; /* 21 EEP check sum */
1201 uchar oem_name[16]; /* 22 OEM name */
1202 ushort dvc_err_code; /* 30 last device driver error code */
1203 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1204 ushort adv_err_addr; /* 32 last uc error address */
1205 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1206 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1207 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1208 ushort reserved36; /* 36 reserved */
1209 ushort reserved37; /* 37 reserved */
1210 ushort reserved38; /* 38 reserved */
1211 ushort reserved39; /* 39 reserved */
1212 ushort reserved40; /* 40 reserved */
1213 ushort reserved41; /* 41 reserved */
1214 ushort reserved42; /* 42 reserved */
1215 ushort reserved43; /* 43 reserved */
1216 ushort reserved44; /* 44 reserved */
1217 ushort reserved45; /* 45 reserved */
1218 ushort reserved46; /* 46 reserved */
1219 ushort reserved47; /* 47 reserved */
1220 ushort reserved48; /* 48 reserved */
1221 ushort reserved49; /* 49 reserved */
1222 ushort reserved50; /* 50 reserved */
1223 ushort reserved51; /* 51 reserved */
1224 ushort reserved52; /* 52 reserved */
1225 ushort reserved53; /* 53 reserved */
1226 ushort reserved54; /* 54 reserved */
1227 ushort reserved55; /* 55 reserved */
1228 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1229 ushort cisprt_msw; /* 57 CIS PTR MSW */
1230 ushort subsysvid; /* 58 SubSystem Vendor ID */
1231 ushort subsysid; /* 59 SubSystem ID */
1232 ushort reserved60; /* 60 reserved */
1233 ushort reserved61; /* 61 reserved */
1234 ushort reserved62; /* 62 reserved */
1235 ushort reserved63; /* 63 reserved */
1236 } ADVEEP_38C0800_CONFIG;
1238 typedef struct adveep_38C1600_config {
1239 /* Word Offset, Description */
1241 ushort cfg_lsw; /* 00 power up initialization */
1242 /* bit 11 set - Func. 0 INTB, Func. 1 INTA */
1243 /* clear - Func. 0 INTA, Func. 1 INTB */
1244 /* bit 13 set - Load CIS */
1245 /* bit 14 set - BIOS Enable */
1246 /* bit 15 set - Big Endian Mode */
1247 ushort cfg_msw; /* 01 unused */
1248 ushort disc_enable; /* 02 disconnect enable */
1249 ushort wdtr_able; /* 03 Wide DTR able */
1250 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1251 ushort start_motor; /* 05 send start up motor */
1252 ushort tagqng_able; /* 06 tag queuing able */
1253 ushort bios_scan; /* 07 BIOS device control */
1254 ushort scam_tolerant; /* 08 no scam */
1256 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1257 uchar bios_boot_delay; /* power up wait */
1259 uchar scsi_reset_delay; /* 10 reset delay */
1260 uchar bios_id_lun; /* first boot device scsi id & lun */
1261 /* high nibble is lun */
1262 /* low nibble is scsi id */
1264 uchar termination_se; /* 11 0 - automatic */
1265 /* 1 - low off / high off */
1266 /* 2 - low off / high on */
1267 /* 3 - low on / high on */
1268 /* There is no low on / high off */
1270 uchar termination_lvd; /* 11 0 - automatic */
1271 /* 1 - low off / high off */
1272 /* 2 - low off / high on */
1273 /* 3 - low on / high on */
1274 /* There is no low on / high off */
1276 ushort bios_ctrl; /* 12 BIOS control bits */
1277 /* bit 0 BIOS don't act as initiator. */
1278 /* bit 1 BIOS > 1 GB support */
1279 /* bit 2 BIOS > 2 Disk Support */
1280 /* bit 3 BIOS don't support removables */
1281 /* bit 4 BIOS support bootable CD */
1282 /* bit 5 BIOS scan enabled */
1283 /* bit 6 BIOS support multiple LUNs */
1284 /* bit 7 BIOS display of message */
1285 /* bit 8 SCAM disabled */
1286 /* bit 9 Reset SCSI bus during init. */
1287 /* bit 10 Basic Integrity Checking disabled */
1288 /* bit 11 No verbose initialization. */
1289 /* bit 12 SCSI parity enabled */
1290 /* bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
1293 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1294 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1295 uchar max_host_qng; /* 15 maximum host queueing */
1296 uchar max_dvc_qng; /* maximum per device queuing */
1297 ushort dvc_cntl; /* 16 control bit for driver */
1298 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1299 ushort serial_number_word1; /* 18 Board serial number word 1 */
1300 ushort serial_number_word2; /* 19 Board serial number word 2 */
1301 ushort serial_number_word3; /* 20 Board serial number word 3 */
1302 ushort check_sum; /* 21 EEP check sum */
1303 uchar oem_name[16]; /* 22 OEM name */
1304 ushort dvc_err_code; /* 30 last device driver error code */
1305 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1306 ushort adv_err_addr; /* 32 last uc error address */
1307 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1308 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1309 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1310 ushort reserved36; /* 36 reserved */
1311 ushort reserved37; /* 37 reserved */
1312 ushort reserved38; /* 38 reserved */
1313 ushort reserved39; /* 39 reserved */
1314 ushort reserved40; /* 40 reserved */
1315 ushort reserved41; /* 41 reserved */
1316 ushort reserved42; /* 42 reserved */
1317 ushort reserved43; /* 43 reserved */
1318 ushort reserved44; /* 44 reserved */
1319 ushort reserved45; /* 45 reserved */
1320 ushort reserved46; /* 46 reserved */
1321 ushort reserved47; /* 47 reserved */
1322 ushort reserved48; /* 48 reserved */
1323 ushort reserved49; /* 49 reserved */
1324 ushort reserved50; /* 50 reserved */
1325 ushort reserved51; /* 51 reserved */
1326 ushort reserved52; /* 52 reserved */
1327 ushort reserved53; /* 53 reserved */
1328 ushort reserved54; /* 54 reserved */
1329 ushort reserved55; /* 55 reserved */
1330 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1331 ushort cisprt_msw; /* 57 CIS PTR MSW */
1332 ushort subsysvid; /* 58 SubSystem Vendor ID */
1333 ushort subsysid; /* 59 SubSystem ID */
1334 ushort reserved60; /* 60 reserved */
1335 ushort reserved61; /* 61 reserved */
1336 ushort reserved62; /* 62 reserved */
1337 ushort reserved63; /* 63 reserved */
1338 } ADVEEP_38C1600_CONFIG;
1343 #define ASC_EEP_CMD_DONE 0x0200
1346 #define BIOS_CTRL_BIOS 0x0001
1347 #define BIOS_CTRL_EXTENDED_XLAT 0x0002
1348 #define BIOS_CTRL_GT_2_DISK 0x0004
1349 #define BIOS_CTRL_BIOS_REMOVABLE 0x0008
1350 #define BIOS_CTRL_BOOTABLE_CD 0x0010
1351 #define BIOS_CTRL_MULTIPLE_LUN 0x0040
1352 #define BIOS_CTRL_DISPLAY_MSG 0x0080
1353 #define BIOS_CTRL_NO_SCAM 0x0100
1354 #define BIOS_CTRL_RESET_SCSI_BUS 0x0200
1355 #define BIOS_CTRL_INIT_VERBOSE 0x0800
1356 #define BIOS_CTRL_SCSI_PARITY 0x1000
1357 #define BIOS_CTRL_AIPP_DIS 0x2000
1359 #define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */
1361 #define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1364 * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
1365 * a special 16K Adv Library and Microcode version. After the issue is
1366 * resolved, should restore 32K support.
1368 * #define ADV_38C1600_MEMSIZE 0x8000L * 32 KB Internal Memory *
1370 #define ADV_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1373 * Byte I/O register address from base of 'iop_base'.
1375 #define IOPB_INTR_STATUS_REG 0x00
1376 #define IOPB_CHIP_ID_1 0x01
1377 #define IOPB_INTR_ENABLES 0x02
1378 #define IOPB_CHIP_TYPE_REV 0x03
1379 #define IOPB_RES_ADDR_4 0x04
1380 #define IOPB_RES_ADDR_5 0x05
1381 #define IOPB_RAM_DATA 0x06
1382 #define IOPB_RES_ADDR_7 0x07
1383 #define IOPB_FLAG_REG 0x08
1384 #define IOPB_RES_ADDR_9 0x09
1385 #define IOPB_RISC_CSR 0x0A
1386 #define IOPB_RES_ADDR_B 0x0B
1387 #define IOPB_RES_ADDR_C 0x0C
1388 #define IOPB_RES_ADDR_D 0x0D
1389 #define IOPB_SOFT_OVER_WR 0x0E
1390 #define IOPB_RES_ADDR_F 0x0F
1391 #define IOPB_MEM_CFG 0x10
1392 #define IOPB_RES_ADDR_11 0x11
1393 #define IOPB_GPIO_DATA 0x12
1394 #define IOPB_RES_ADDR_13 0x13
1395 #define IOPB_FLASH_PAGE 0x14
1396 #define IOPB_RES_ADDR_15 0x15
1397 #define IOPB_GPIO_CNTL 0x16
1398 #define IOPB_RES_ADDR_17 0x17
1399 #define IOPB_FLASH_DATA 0x18
1400 #define IOPB_RES_ADDR_19 0x19
1401 #define IOPB_RES_ADDR_1A 0x1A
1402 #define IOPB_RES_ADDR_1B 0x1B
1403 #define IOPB_RES_ADDR_1C 0x1C
1404 #define IOPB_RES_ADDR_1D 0x1D
1405 #define IOPB_RES_ADDR_1E 0x1E
1406 #define IOPB_RES_ADDR_1F 0x1F
1407 #define IOPB_DMA_CFG0 0x20
1408 #define IOPB_DMA_CFG1 0x21
1409 #define IOPB_TICKLE 0x22
1410 #define IOPB_DMA_REG_WR 0x23
1411 #define IOPB_SDMA_STATUS 0x24
1412 #define IOPB_SCSI_BYTE_CNT 0x25
1413 #define IOPB_HOST_BYTE_CNT 0x26
1414 #define IOPB_BYTE_LEFT_TO_XFER 0x27
1415 #define IOPB_BYTE_TO_XFER_0 0x28
1416 #define IOPB_BYTE_TO_XFER_1 0x29
1417 #define IOPB_BYTE_TO_XFER_2 0x2A
1418 #define IOPB_BYTE_TO_XFER_3 0x2B
1419 #define IOPB_ACC_GRP 0x2C
1420 #define IOPB_RES_ADDR_2D 0x2D
1421 #define IOPB_DEV_ID 0x2E
1422 #define IOPB_RES_ADDR_2F 0x2F
1423 #define IOPB_SCSI_DATA 0x30
1424 #define IOPB_RES_ADDR_31 0x31
1425 #define IOPB_RES_ADDR_32 0x32
1426 #define IOPB_SCSI_DATA_HSHK 0x33
1427 #define IOPB_SCSI_CTRL 0x34
1428 #define IOPB_RES_ADDR_35 0x35
1429 #define IOPB_RES_ADDR_36 0x36
1430 #define IOPB_RES_ADDR_37 0x37
1431 #define IOPB_RAM_BIST 0x38
1432 #define IOPB_PLL_TEST 0x39
1433 #define IOPB_PCI_INT_CFG 0x3A
1434 #define IOPB_RES_ADDR_3B 0x3B
1435 #define IOPB_RFIFO_CNT 0x3C
1436 #define IOPB_RES_ADDR_3D 0x3D
1437 #define IOPB_RES_ADDR_3E 0x3E
1438 #define IOPB_RES_ADDR_3F 0x3F
1441 * Word I/O register address from base of 'iop_base'.
1443 #define IOPW_CHIP_ID_0 0x00 /* CID0 */
1444 #define IOPW_CTRL_REG 0x02 /* CC */
1445 #define IOPW_RAM_ADDR 0x04 /* LA */
1446 #define IOPW_RAM_DATA 0x06 /* LD */
1447 #define IOPW_RES_ADDR_08 0x08
1448 #define IOPW_RISC_CSR 0x0A /* CSR */
1449 #define IOPW_SCSI_CFG0 0x0C /* CFG0 */
1450 #define IOPW_SCSI_CFG1 0x0E /* CFG1 */
1451 #define IOPW_RES_ADDR_10 0x10
1452 #define IOPW_SEL_MASK 0x12 /* SM */
1453 #define IOPW_RES_ADDR_14 0x14
1454 #define IOPW_FLASH_ADDR 0x16 /* FA */
1455 #define IOPW_RES_ADDR_18 0x18
1456 #define IOPW_EE_CMD 0x1A /* EC */
1457 #define IOPW_EE_DATA 0x1C /* ED */
1458 #define IOPW_SFIFO_CNT 0x1E /* SFC */
1459 #define IOPW_RES_ADDR_20 0x20
1460 #define IOPW_Q_BASE 0x22 /* QB */
1461 #define IOPW_QP 0x24 /* QP */
1462 #define IOPW_IX 0x26 /* IX */
1463 #define IOPW_SP 0x28 /* SP */
1464 #define IOPW_PC 0x2A /* PC */
1465 #define IOPW_RES_ADDR_2C 0x2C
1466 #define IOPW_RES_ADDR_2E 0x2E
1467 #define IOPW_SCSI_DATA 0x30 /* SD */
1468 #define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */
1469 #define IOPW_SCSI_CTRL 0x34 /* SC */
1470 #define IOPW_HSHK_CFG 0x36 /* HCFG */
1471 #define IOPW_SXFR_STATUS 0x36 /* SXS */
1472 #define IOPW_SXFR_CNTL 0x38 /* SXL */
1473 #define IOPW_SXFR_CNTH 0x3A /* SXH */
1474 #define IOPW_RES_ADDR_3C 0x3C
1475 #define IOPW_RFIFO_DATA 0x3E /* RFD */
1478 * Doubleword I/O register address from base of 'iop_base'.
1480 #define IOPDW_RES_ADDR_0 0x00
1481 #define IOPDW_RAM_DATA 0x04
1482 #define IOPDW_RES_ADDR_8 0x08
1483 #define IOPDW_RES_ADDR_C 0x0C
1484 #define IOPDW_RES_ADDR_10 0x10
1485 #define IOPDW_COMMA 0x14
1486 #define IOPDW_COMMB 0x18
1487 #define IOPDW_RES_ADDR_1C 0x1C
1488 #define IOPDW_SDMA_ADDR0 0x20
1489 #define IOPDW_SDMA_ADDR1 0x24
1490 #define IOPDW_SDMA_COUNT 0x28
1491 #define IOPDW_SDMA_ERROR 0x2C
1492 #define IOPDW_RDMA_ADDR0 0x30
1493 #define IOPDW_RDMA_ADDR1 0x34
1494 #define IOPDW_RDMA_COUNT 0x38
1495 #define IOPDW_RDMA_ERROR 0x3C
1497 #define ADV_CHIP_ID_BYTE 0x25
1498 #define ADV_CHIP_ID_WORD 0x04C1
1500 #define ADV_INTR_ENABLE_HOST_INTR 0x01
1501 #define ADV_INTR_ENABLE_SEL_INTR 0x02
1502 #define ADV_INTR_ENABLE_DPR_INTR 0x04
1503 #define ADV_INTR_ENABLE_RTA_INTR 0x08
1504 #define ADV_INTR_ENABLE_RMA_INTR 0x10
1505 #define ADV_INTR_ENABLE_RST_INTR 0x20
1506 #define ADV_INTR_ENABLE_DPE_INTR 0x40
1507 #define ADV_INTR_ENABLE_GLOBAL_INTR 0x80
1509 #define ADV_INTR_STATUS_INTRA 0x01
1510 #define ADV_INTR_STATUS_INTRB 0x02
1511 #define ADV_INTR_STATUS_INTRC 0x04
1513 #define ADV_RISC_CSR_STOP (0x0000)
1514 #define ADV_RISC_TEST_COND (0x2000)
1515 #define ADV_RISC_CSR_RUN (0x4000)
1516 #define ADV_RISC_CSR_SINGLE_STEP (0x8000)
1518 #define ADV_CTRL_REG_HOST_INTR 0x0100
1519 #define ADV_CTRL_REG_SEL_INTR 0x0200
1520 #define ADV_CTRL_REG_DPR_INTR 0x0400
1521 #define ADV_CTRL_REG_RTA_INTR 0x0800
1522 #define ADV_CTRL_REG_RMA_INTR 0x1000
1523 #define ADV_CTRL_REG_RES_BIT14 0x2000
1524 #define ADV_CTRL_REG_DPE_INTR 0x4000
1525 #define ADV_CTRL_REG_POWER_DONE 0x8000
1526 #define ADV_CTRL_REG_ANY_INTR 0xFF00
1528 #define ADV_CTRL_REG_CMD_RESET 0x00C6
1529 #define ADV_CTRL_REG_CMD_WR_IO_REG 0x00C5
1530 #define ADV_CTRL_REG_CMD_RD_IO_REG 0x00C4
1531 #define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3
1532 #define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2
1534 #define ADV_TICKLE_NOP 0x00
1535 #define ADV_TICKLE_A 0x01
1536 #define ADV_TICKLE_B 0x02
1537 #define ADV_TICKLE_C 0x03
1539 #define AdvIsIntPending(port) \
1540 (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
1543 * SCSI_CFG0 Register bit definitions
1545 #define TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */
1546 #define PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */
1547 #define EVEN_PARITY 0x1000 /* Select Even Parity */
1548 #define WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */
1549 #define QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */
1550 #define PRIM_MODE 0x0100 /* Primitive SCSI mode */
1551 #define SCAM_EN 0x0080 /* Enable SCAM selection */
1552 #define SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
1553 #define CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
1554 #define OUR_ID_EN 0x0010 /* Enable OUR_ID bits */
1555 #define OUR_ID 0x000F /* SCSI ID */
1558 * SCSI_CFG1 Register bit definitions
1560 #define BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */
1561 #define TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
1562 #define SLEW_RATE 0x1000 /* SCSI output buffer slew rate */
1563 #define FILTER_SEL 0x0C00 /* Filter Period Selection */
1564 #define FLTR_DISABLE 0x0000 /* Input Filtering Disabled */
1565 #define FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
1566 #define FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
1567 #define ACTIVE_DBL 0x0200 /* Disable Active Negation */
1568 #define DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */
1569 #define DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */
1570 #define TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */
1571 #define TERM_CTL 0x0030 /* External SCSI Termination Bits */
1572 #define TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */
1573 #define TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */
1574 #define CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */
1577 * Addendum for ASC-38C0800 Chip
1579 * The ASC-38C1600 Chip uses the same definitions except that the
1580 * bus mode override bits [12:10] have been moved to byte register
1581 * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
1582 * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
1583 * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
1584 * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
1585 * and [1:0]. Bits [14], [7:6], [3:2] are unused.
1587 #define DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */
1588 #define HVD_LVD_SE 0x1C00 /* Device Detect Bits */
1589 #define HVD 0x1000 /* HVD Device Detect */
1590 #define LVD 0x0800 /* LVD Device Detect */
1591 #define SE 0x0400 /* SE Device Detect */
1592 #define TERM_LVD 0x00C0 /* LVD Termination Bits */
1593 #define TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */
1594 #define TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */
1595 #define TERM_SE 0x0030 /* SE Termination Bits */
1596 #define TERM_SE_HI 0x0020 /* Enable SE Upper Termination */
1597 #define TERM_SE_LO 0x0010 /* Enable SE Lower Termination */
1598 #define C_DET_LVD 0x000C /* LVD Cable Detect Bits */
1599 #define C_DET3 0x0008 /* Cable Detect for LVD External Wide */
1600 #define C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */
1601 #define C_DET_SE 0x0003 /* SE Cable Detect Bits */
1602 #define C_DET1 0x0002 /* Cable Detect for SE Internal Wide */
1603 #define C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */
1605 #define CABLE_ILLEGAL_A 0x7
1606 /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */
1608 #define CABLE_ILLEGAL_B 0xB
1609 /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */
1612 * MEM_CFG Register bit definitions
1614 #define BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */
1615 #define FAST_EE_CLK 0x20 /* Diagnostic Bit */
1616 #define RAM_SZ 0x1C /* Specify size of RAM to RISC */
1617 #define RAM_SZ_2KB 0x00 /* 2 KB */
1618 #define RAM_SZ_4KB 0x04 /* 4 KB */
1619 #define RAM_SZ_8KB 0x08 /* 8 KB */
1620 #define RAM_SZ_16KB 0x0C /* 16 KB */
1621 #define RAM_SZ_32KB 0x10 /* 32 KB */
1622 #define RAM_SZ_64KB 0x14 /* 64 KB */
1625 * DMA_CFG0 Register bit definitions
1627 * This register is only accessible to the host.
1629 #define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */
1630 #define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */
1631 #define FIFO_THRESH_16B 0x00 /* 16 bytes */
1632 #define FIFO_THRESH_32B 0x20 /* 32 bytes */
1633 #define FIFO_THRESH_48B 0x30 /* 48 bytes */
1634 #define FIFO_THRESH_64B 0x40 /* 64 bytes */
1635 #define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */
1636 #define FIFO_THRESH_96B 0x60 /* 96 bytes */
1637 #define FIFO_THRESH_112B 0x70 /* 112 bytes */
1638 #define START_CTL 0x0C /* DMA start conditions */
1639 #define START_CTL_TH 0x00 /* Wait threshold level (default) */
1640 #define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */
1641 #define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */
1642 #define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */
1643 #define READ_CMD 0x03 /* Memory Read Method */
1644 #define READ_CMD_MR 0x00 /* Memory Read */
1645 #define READ_CMD_MRL 0x02 /* Memory Read Long */
1646 #define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */
1649 * ASC-38C0800 RAM BIST Register bit definitions
1651 #define RAM_TEST_MODE 0x80
1652 #define PRE_TEST_MODE 0x40
1653 #define NORMAL_MODE 0x00
1654 #define RAM_TEST_DONE 0x10
1655 #define RAM_TEST_STATUS 0x0F
1656 #define RAM_TEST_HOST_ERROR 0x08
1657 #define RAM_TEST_INTRAM_ERROR 0x04
1658 #define RAM_TEST_RISC_ERROR 0x02
1659 #define RAM_TEST_SCSI_ERROR 0x01
1660 #define RAM_TEST_SUCCESS 0x00
1661 #define PRE_TEST_VALUE 0x05
1662 #define NORMAL_VALUE 0x00
1665 * ASC38C1600 Definitions
1667 * IOPB_PCI_INT_CFG Bit Field Definitions
1670 #define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */
1673 * Bit 1 can be set to change the interrupt for the Function to operate in
1674 * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
1675 * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
1676 * mode, otherwise the operating mode is undefined.
1678 #define TOTEMPOLE 0x02
1681 * Bit 0 can be used to change the Int Pin for the Function. The value is
1682 * 0 by default for both Functions with Function 0 using INT A and Function
1683 * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
1686 * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
1687 * value specified in the PCI Configuration Space.
1692 * Adv Library Status Definitions
1696 #define ADV_SUCCESS 1
1698 #define ADV_ERROR (-1)
1701 * ADV_DVC_VAR 'warn_code' values
1703 #define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */
1704 #define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */
1705 #define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */
1706 #define ASC_WARN_ERROR 0xFFFF /* ADV_ERROR return */
1708 #define ADV_MAX_TID 15 /* max. target identifier */
1709 #define ADV_MAX_LUN 7 /* max. logical unit number */
1712 * Error code values are set in ADV_DVC_VAR 'err_code'.
1714 #define ASC_IERR_WRITE_EEPROM 0x0001 /* write EEPROM error */
1715 #define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */
1716 #define ASC_IERR_NO_CARRIER 0x0004 /* No more carrier memory. */
1717 #define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */
1718 #define ASC_IERR_CHIP_VERSION 0x0040 /* wrong chip version */
1719 #define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */
1720 #define ASC_IERR_HVD_DEVICE 0x0100 /* HVD attached to LVD connector. */
1721 #define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */
1722 #define ASC_IERR_ILLEGAL_CONNECTION 0x0400 /* Illegal cable connection */
1723 #define ASC_IERR_SINGLE_END_DEVICE 0x0800 /* Single-end used w/differential */
1724 #define ASC_IERR_REVERSED_CABLE 0x1000 /* Narrow flat cable reversed */
1725 #define ASC_IERR_BIST_PRE_TEST 0x2000 /* BIST pre-test error */
1726 #define ASC_IERR_BIST_RAM_TEST 0x4000 /* BIST RAM test error */
1727 #define ASC_IERR_BAD_CHIPTYPE 0x8000 /* Invalid 'chip_type' setting. */
1730 * Fixed locations of microcode operating variables.
1732 #define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */
1733 #define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */
1734 #define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */
1735 #define ASC_MC_VERSION_DATE 0x0038 /* microcode version */
1736 #define ASC_MC_VERSION_NUM 0x003A /* microcode number */
1737 #define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
1738 #define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
1739 #define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */
1740 #define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */
1741 #define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */
1742 #define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */
1743 #define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */
1744 #define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */
1745 #define ASC_MC_CHIP_TYPE 0x009A
1746 #define ASC_MC_INTRB_CODE 0x009B
1747 #define ASC_MC_WDTR_ABLE 0x009C
1748 #define ASC_MC_SDTR_ABLE 0x009E
1749 #define ASC_MC_TAGQNG_ABLE 0x00A0
1750 #define ASC_MC_DISC_ENABLE 0x00A2
1751 #define ASC_MC_IDLE_CMD_STATUS 0x00A4
1752 #define ASC_MC_IDLE_CMD 0x00A6
1753 #define ASC_MC_IDLE_CMD_PARAMETER 0x00A8
1754 #define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC
1755 #define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE
1756 #define ASC_MC_DEFAULT_MEM_CFG 0x00B0
1757 #define ASC_MC_DEFAULT_SEL_MASK 0x00B2
1758 #define ASC_MC_SDTR_DONE 0x00B6
1759 #define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0
1760 #define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0
1761 #define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100
1762 #define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */
1763 #define ASC_MC_WDTR_DONE 0x0124
1764 #define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */
1765 #define ASC_MC_ICQ 0x0160
1766 #define ASC_MC_IRQ 0x0164
1767 #define ASC_MC_PPR_ABLE 0x017A
1770 * BIOS LRAM variable absolute offsets.
1772 #define BIOS_CODESEG 0x54
1773 #define BIOS_CODELEN 0x56
1774 #define BIOS_SIGNATURE 0x58
1775 #define BIOS_VERSION 0x5A
1778 * Microcode Control Flags
1780 * Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
1781 * and handled by the microcode.
1783 #define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */
1784 #define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */
1787 * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
1789 #define HSHK_CFG_WIDE_XFR 0x8000
1790 #define HSHK_CFG_RATE 0x0F00
1791 #define HSHK_CFG_OFFSET 0x001F
1793 #define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */
1794 #define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */
1795 #define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */
1796 #define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */
1798 #define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */
1799 #define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */
1800 #define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
1801 #define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */
1802 #define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */
1804 #define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */
1805 #define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */
1806 #define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */
1807 #define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */
1808 #define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */
1810 * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
1811 * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
1813 #define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */
1814 #define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */
1817 * All fields here are accessed by the board microcode and need to be
1820 typedef struct adv_carr_t {
1821 ADV_VADDR carr_va; /* Carrier Virtual Address */
1822 ADV_PADDR carr_pa; /* Carrier Physical Address */
1823 ADV_VADDR areq_vpa; /* ASC_SCSI_REQ_Q Virtual or Physical Address */
1825 * next_vpa [31:4] Carrier Virtual or Physical Next Pointer
1827 * next_vpa [3:1] Reserved Bits
1828 * next_vpa [0] Done Flag set in Response Queue.
1834 * Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
1836 #define ASC_NEXT_VPA_MASK 0xFFFFFFF0
1838 #define ASC_RQ_DONE 0x00000001
1839 #define ASC_RQ_GOOD 0x00000002
1840 #define ASC_CQ_STOPPER 0x00000000
1842 #define ASC_GET_CARRP(carrp) ((carrp) & ASC_NEXT_VPA_MASK)
1844 #define ADV_CARRIER_NUM_PAGE_CROSSING \
1845 (((ADV_CARRIER_COUNT * sizeof(ADV_CARR_T)) + \
1846 (ADV_PAGE_SIZE - 1))/ADV_PAGE_SIZE)
1848 #define ADV_CARRIER_BUFSIZE \
1849 ((ADV_CARRIER_COUNT + ADV_CARRIER_NUM_PAGE_CROSSING) * sizeof(ADV_CARR_T))
1852 * ASC_SCSI_REQ_Q 'a_flag' definitions
1854 * The Adv Library should limit use to the lower nibble (4 bits) of
1855 * a_flag. Drivers are free to use the upper nibble (4 bits) of a_flag.
1857 #define ADV_POLL_REQUEST 0x01 /* poll for request completion */
1858 #define ADV_SCSIQ_DONE 0x02 /* request done */
1859 #define ADV_DONT_RETRY 0x08 /* don't do retry */
1861 #define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */
1862 #define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */
1863 #define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */
1866 * Adapter temporary configuration structure
1868 * This structure can be discarded after initialization. Don't add
1869 * fields here needed after initialization.
1871 * Field naming convention:
1873 * *_enable indicates the field enables or disables a feature. The
1874 * value of the field is never reset.
1876 typedef struct adv_dvc_cfg {
1877 ushort disc_enable; /* enable disconnection */
1878 uchar chip_version; /* chip version */
1879 uchar termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
1880 ushort lib_version; /* Adv Library version number */
1881 ushort control_flag; /* Microcode Control Flag */
1882 ushort mcode_date; /* Microcode date */
1883 ushort mcode_version; /* Microcode version */
1884 ushort serial1; /* EEPROM serial number word 1 */
1885 ushort serial2; /* EEPROM serial number word 2 */
1886 ushort serial3; /* EEPROM serial number word 3 */
1890 struct adv_scsi_req_q;
1893 * Adapter operation variable structure.
1895 * One structure is required per host adapter.
1897 * Field naming convention:
1899 * *_able indicates both whether a feature should be enabled or disabled
1900 * and whether a device isi capable of the feature. At initialization
1901 * this field may be set, but later if a device is found to be incapable
1902 * of the feature, the field is cleared.
1904 typedef struct adv_dvc_var {
1905 AdvPortAddr iop_base; /* I/O port address */
1906 ushort err_code; /* fatal error code */
1907 ushort bios_ctrl; /* BIOS control word, EEPROM word 12 */
1908 ushort wdtr_able; /* try WDTR for a device */
1909 ushort sdtr_able; /* try SDTR for a device */
1910 ushort ultra_able; /* try SDTR Ultra speed for a device */
1911 ushort sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */
1912 ushort sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */
1913 ushort sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */
1914 ushort sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */
1915 ushort tagqng_able; /* try tagged queuing with a device */
1916 ushort ppr_able; /* PPR message capable per TID bitmask. */
1917 uchar max_dvc_qng; /* maximum number of tagged commands per device */
1918 ushort start_motor; /* start motor command allowed */
1919 uchar scsi_reset_wait; /* delay in seconds after scsi bus reset */
1920 uchar chip_no; /* should be assigned by caller */
1921 uchar max_host_qng; /* maximum number of Q'ed command allowed */
1922 uchar irq_no; /* IRQ number */
1923 ushort no_scam; /* scam_tolerant of EEPROM */
1924 struct asc_board *drv_ptr; /* driver pointer to private structure */
1925 uchar chip_scsi_id; /* chip SCSI target ID */
1927 uchar bist_err_code;
1928 ADV_CARR_T *carrier_buf;
1929 ADV_CARR_T *carr_freelist; /* Carrier free list. */
1930 ADV_CARR_T *icq_sp; /* Initiator command queue stopper pointer. */
1931 ADV_CARR_T *irq_sp; /* Initiator response queue stopper pointer. */
1932 ushort carr_pending_cnt; /* Count of pending carriers. */
1934 * Note: The following fields will not be used after initialization. The
1935 * driver may discard the buffer after initialization is done.
1937 ADV_DVC_CFG *cfg; /* temporary configuration structure */
1940 #define NO_OF_SG_PER_BLOCK 15
1942 typedef struct asc_sg_block {
1946 uchar sg_cnt; /* Valid entries in block. */
1947 ADV_PADDR sg_ptr; /* Pointer to next sg block. */
1949 ADV_PADDR sg_addr; /* SG element address. */
1950 ADV_DCNT sg_count; /* SG element count. */
1951 } sg_list[NO_OF_SG_PER_BLOCK];
1955 * ADV_SCSI_REQ_Q - microcode request structure
1957 * All fields in this structure up to byte 60 are used by the microcode.
1958 * The microcode makes assumptions about the size and ordering of fields
1959 * in this structure. Do not change the structure definition here without
1960 * coordinating the change with the microcode.
1962 * All fields accessed by microcode must be maintained in little_endian
1965 typedef struct adv_scsi_req_q {
1966 uchar cntl; /* Ucode flags and state (ASC_MC_QC_*). */
1968 uchar target_id; /* Device target identifier. */
1969 uchar target_lun; /* Device target logical unit number. */
1970 ADV_PADDR data_addr; /* Data buffer physical address. */
1971 ADV_DCNT data_cnt; /* Data count. Ucode sets to residual. */
1972 ADV_PADDR sense_addr;
1976 uchar cdb_len; /* SCSI CDB length. Must <= 16 bytes. */
1978 uchar done_status; /* Completion status. */
1979 uchar scsi_status; /* SCSI status byte. */
1980 uchar host_status; /* Ucode host status. */
1981 uchar sg_working_ix;
1982 uchar cdb[12]; /* SCSI CDB bytes 0-11. */
1983 ADV_PADDR sg_real_addr; /* SG list physical address. */
1984 ADV_PADDR scsiq_rptr;
1985 uchar cdb16[4]; /* SCSI CDB bytes 12-15. */
1986 ADV_VADDR scsiq_ptr;
1989 * End of microcode structure - 60 bytes. The rest of the structure
1990 * is used by the Adv Library and ignored by the microcode.
1993 ADV_SG_BLOCK *sg_list_ptr; /* SG list virtual address. */
1994 char *vdata_addr; /* Data buffer virtual address. */
1996 uchar pad[2]; /* Pad out to a word boundary. */
2000 * Microcode idle loop commands
2002 #define IDLE_CMD_COMPLETED 0
2003 #define IDLE_CMD_STOP_CHIP 0x0001
2004 #define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002
2005 #define IDLE_CMD_SEND_INT 0x0004
2006 #define IDLE_CMD_ABORT 0x0008
2007 #define IDLE_CMD_DEVICE_RESET 0x0010
2008 #define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */
2009 #define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */
2010 #define IDLE_CMD_SCSIREQ 0x0080
2012 #define IDLE_CMD_STATUS_SUCCESS 0x0001
2013 #define IDLE_CMD_STATUS_FAILURE 0x0002
2016 * AdvSendIdleCmd() flag definitions.
2018 #define ADV_NOWAIT 0x01
2021 * Wait loop time out values.
2023 #define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */
2024 #define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */
2025 #define SCSI_MAX_RETRY 10 /* retry count */
2027 #define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */
2028 #define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */
2029 #define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */
2030 #define ADV_RDMA_IN_CARR_AND_Q_INVALID 0x04 /* RDMAed-in data invalid. */
2032 #define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */
2034 /* Read byte from a register. */
2035 #define AdvReadByteRegister(iop_base, reg_off) \
2036 (ADV_MEM_READB((iop_base) + (reg_off)))
2038 /* Write byte to a register. */
2039 #define AdvWriteByteRegister(iop_base, reg_off, byte) \
2040 (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
2042 /* Read word (2 bytes) from a register. */
2043 #define AdvReadWordRegister(iop_base, reg_off) \
2044 (ADV_MEM_READW((iop_base) + (reg_off)))
2046 /* Write word (2 bytes) to a register. */
2047 #define AdvWriteWordRegister(iop_base, reg_off, word) \
2048 (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
2050 /* Write dword (4 bytes) to a register. */
2051 #define AdvWriteDWordRegister(iop_base, reg_off, dword) \
2052 (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
2054 /* Read byte from LRAM. */
2055 #define AdvReadByteLram(iop_base, addr, byte) \
2057 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
2058 (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
2061 /* Write byte to LRAM. */
2062 #define AdvWriteByteLram(iop_base, addr, byte) \
2063 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2064 ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
2066 /* Read word (2 bytes) from LRAM. */
2067 #define AdvReadWordLram(iop_base, addr, word) \
2069 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
2070 (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
2073 /* Write word (2 bytes) to LRAM. */
2074 #define AdvWriteWordLram(iop_base, addr, word) \
2075 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2076 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2078 /* Write little-endian double word (4 bytes) to LRAM */
2079 /* Because of unspecified C language ordering don't use auto-increment. */
2080 #define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
2081 ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2082 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2083 cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
2084 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
2085 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2086 cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
2088 /* Read word (2 bytes) from LRAM assuming that the address is already set. */
2089 #define AdvReadWordAutoIncLram(iop_base) \
2090 (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
2092 /* Write word (2 bytes) to LRAM assuming that the address is already set. */
2093 #define AdvWriteWordAutoIncLram(iop_base, word) \
2094 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2097 * Define macro to check for Condor signature.
2099 * Evaluate to ADV_TRUE if a Condor chip is found the specified port
2100 * address 'iop_base'. Otherwise evalue to ADV_FALSE.
2102 #define AdvFindSignature(iop_base) \
2103 (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
2104 ADV_CHIP_ID_BYTE) && \
2105 (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
2106 ADV_CHIP_ID_WORD)) ? ADV_TRUE : ADV_FALSE)
2109 * Define macro to Return the version number of the chip at 'iop_base'.
2111 * The second parameter 'bus_type' is currently unused.
2113 #define AdvGetChipVersion(iop_base, bus_type) \
2114 AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
2117 * Abort an SRB in the chip's RISC Memory. The 'srb_ptr' argument must
2118 * match the ASC_SCSI_REQ_Q 'srb_ptr' field.
2120 * If the request has not yet been sent to the device it will simply be
2121 * aborted from RISC memory. If the request is disconnected it will be
2122 * aborted on reselection by sending an Abort Message to the target ID.
2125 * ADV_TRUE(1) - Queue was successfully aborted.
2126 * ADV_FALSE(0) - Queue was not found on the active queue list.
2128 #define AdvAbortQueue(asc_dvc, scsiq) \
2129 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
2133 * Send a Bus Device Reset Message to the specified target ID.
2135 * All outstanding commands will be purged if sending the
2136 * Bus Device Reset Message is successful.
2139 * ADV_TRUE(1) - All requests on the target are purged.
2140 * ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
2143 #define AdvResetDevice(asc_dvc, target_id) \
2144 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
2145 (ADV_DCNT) (target_id))
2148 * SCSI Wide Type definition.
2150 #define ADV_SCSI_BIT_ID_TYPE ushort
2153 * AdvInitScsiTarget() 'cntl_flag' options.
2155 #define ADV_SCAN_LUN 0x01
2156 #define ADV_CAPINFO_NOLUN 0x02
2159 * Convert target id to target id bit mask.
2161 #define ADV_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADV_MAX_TID))
2164 * ASC_SCSI_REQ_Q 'done_status' and 'host_status' return values.
2167 #define QD_NO_STATUS 0x00 /* Request not completed yet. */
2168 #define QD_NO_ERROR 0x01
2169 #define QD_ABORTED_BY_HOST 0x02
2170 #define QD_WITH_ERROR 0x04
2172 #define QHSTA_NO_ERROR 0x00
2173 #define QHSTA_M_SEL_TIMEOUT 0x11
2174 #define QHSTA_M_DATA_OVER_RUN 0x12
2175 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
2176 #define QHSTA_M_QUEUE_ABORTED 0x15
2177 #define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */
2178 #define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */
2179 #define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */
2180 #define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */
2181 #define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */
2182 #define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */
2183 #define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */
2184 /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
2185 #define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */
2186 #define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */
2187 #define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */
2188 #define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */
2189 #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */
2190 #define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */
2191 #define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */
2192 #define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */
2193 #define QHSTA_M_WTM_TIMEOUT 0x41
2194 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
2195 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
2196 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
2197 #define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */
2198 #define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */
2199 #define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */
2202 * DvcGetPhyAddr() flag arguments
2204 #define ADV_IS_SCSIQ_FLAG 0x01 /* 'addr' is ASC_SCSI_REQ_Q pointer */
2205 #define ADV_ASCGETSGLIST_VADDR 0x02 /* 'addr' is AscGetSGList() virtual addr */
2206 #define ADV_IS_SENSE_FLAG 0x04 /* 'addr' is sense virtual pointer */
2207 #define ADV_IS_DATA_FLAG 0x08 /* 'addr' is data virtual pointer */
2208 #define ADV_IS_SGLIST_FLAG 0x10 /* 'addr' is sglist virtual pointer */
2209 #define ADV_IS_CARRIER_FLAG 0x20 /* 'addr' is ADV_CARR_T pointer */
2211 /* Return the address that is aligned at the next doubleword >= to 'addr'. */
2212 #define ADV_8BALIGN(addr) (((ulong) (addr) + 0x7) & ~0x7)
2213 #define ADV_16BALIGN(addr) (((ulong) (addr) + 0xF) & ~0xF)
2214 #define ADV_32BALIGN(addr) (((ulong) (addr) + 0x1F) & ~0x1F)
2217 * Total contiguous memory needed for driver SG blocks.
2219 * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum
2220 * number of scatter-gather elements the driver supports in a
2224 #define ADV_SG_LIST_MAX_BYTE_SIZE \
2225 (sizeof(ADV_SG_BLOCK) * \
2226 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
2228 /* Reference Scsi_Host hostdata */
2229 #define ASC_BOARDP(host) ((asc_board_t *) &((host)->hostdata))
2231 /* asc_board_t flags */
2232 #define ASC_IS_WIDE_BOARD 0x04 /* AdvanSys Wide Board */
2233 #define ASC_SELECT_QUEUE_DEPTHS 0x08
2235 #define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0)
2236 #define ASC_WIDE_BOARD(boardp) ((boardp)->flags & ASC_IS_WIDE_BOARD)
2238 #define NO_ISA_DMA 0xff /* No ISA DMA Channel Used */
2240 #define ASC_INFO_SIZE 128 /* advansys_info() line size */
2242 #ifdef CONFIG_PROC_FS
2243 /* /proc/scsi/advansys/[0...] related definitions */
2244 #define ASC_PRTBUF_SIZE 2048
2245 #define ASC_PRTLINE_SIZE 160
2247 #define ASC_PRT_NEXT() \
2251 if (leftlen == 0) { \
2256 #endif /* CONFIG_PROC_FS */
2258 /* Asc Library return codes */
2261 #define ASC_NOERROR 1
2263 #define ASC_ERROR (-1)
2265 /* struct scsi_cmnd function return codes */
2266 #define STATUS_BYTE(byte) (byte)
2267 #define MSG_BYTE(byte) ((byte) << 8)
2268 #define HOST_BYTE(byte) ((byte) << 16)
2269 #define DRIVER_BYTE(byte) ((byte) << 24)
2271 #ifndef ADVANSYS_STATS
2272 #define ASC_STATS(shost, counter)
2273 #define ASC_STATS_ADD(shost, counter, count)
2274 #else /* ADVANSYS_STATS */
2275 #define ASC_STATS(shost, counter) \
2276 (ASC_BOARDP(shost)->asc_stats.counter++)
2278 #define ASC_STATS_ADD(shost, counter, count) \
2279 (ASC_BOARDP(shost)->asc_stats.counter += (count))
2280 #endif /* ADVANSYS_STATS */
2282 #define ASC_CEILING(val, unit) (((val) + ((unit) - 1))/(unit))
2284 /* If the result wraps when calculating tenths, return 0. */
2285 #define ASC_TENTHS(num, den) \
2286 (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
2287 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
2290 * Display a message to the console.
2292 #define ASC_PRINT(s) \
2294 printk("advansys: "); \
2298 #define ASC_PRINT1(s, a1) \
2300 printk("advansys: "); \
2301 printk((s), (a1)); \
2304 #define ASC_PRINT2(s, a1, a2) \
2306 printk("advansys: "); \
2307 printk((s), (a1), (a2)); \
2310 #define ASC_PRINT3(s, a1, a2, a3) \
2312 printk("advansys: "); \
2313 printk((s), (a1), (a2), (a3)); \
2316 #define ASC_PRINT4(s, a1, a2, a3, a4) \
2318 printk("advansys: "); \
2319 printk((s), (a1), (a2), (a3), (a4)); \
2322 #ifndef ADVANSYS_DEBUG
2324 #define ASC_DBG(lvl, s)
2325 #define ASC_DBG1(lvl, s, a1)
2326 #define ASC_DBG2(lvl, s, a1, a2)
2327 #define ASC_DBG3(lvl, s, a1, a2, a3)
2328 #define ASC_DBG4(lvl, s, a1, a2, a3, a4)
2329 #define ASC_DBG_PRT_SCSI_HOST(lvl, s)
2330 #define ASC_DBG_PRT_SCSI_CMND(lvl, s)
2331 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp)
2332 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2333 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone)
2334 #define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2335 #define ASC_DBG_PRT_HEX(lvl, name, start, length)
2336 #define ASC_DBG_PRT_CDB(lvl, cdb, len)
2337 #define ASC_DBG_PRT_SENSE(lvl, sense, len)
2338 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len)
2340 #else /* ADVANSYS_DEBUG */
2343 * Debugging Message Levels:
2345 * 1: High-Level Tracing
2346 * 2-N: Verbose Tracing
2349 #define ASC_DBG(lvl, s) \
2351 if (asc_dbglvl >= (lvl)) { \
2356 #define ASC_DBG1(lvl, s, a1) \
2358 if (asc_dbglvl >= (lvl)) { \
2359 printk((s), (a1)); \
2363 #define ASC_DBG2(lvl, s, a1, a2) \
2365 if (asc_dbglvl >= (lvl)) { \
2366 printk((s), (a1), (a2)); \
2370 #define ASC_DBG3(lvl, s, a1, a2, a3) \
2372 if (asc_dbglvl >= (lvl)) { \
2373 printk((s), (a1), (a2), (a3)); \
2377 #define ASC_DBG4(lvl, s, a1, a2, a3, a4) \
2379 if (asc_dbglvl >= (lvl)) { \
2380 printk((s), (a1), (a2), (a3), (a4)); \
2384 #define ASC_DBG_PRT_SCSI_HOST(lvl, s) \
2386 if (asc_dbglvl >= (lvl)) { \
2387 asc_prt_scsi_host(s); \
2391 #define ASC_DBG_PRT_SCSI_CMND(lvl, s) \
2393 if (asc_dbglvl >= (lvl)) { \
2394 asc_prt_scsi_cmnd(s); \
2398 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \
2400 if (asc_dbglvl >= (lvl)) { \
2401 asc_prt_asc_scsi_q(scsiqp); \
2405 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \
2407 if (asc_dbglvl >= (lvl)) { \
2408 asc_prt_asc_qdone_info(qdone); \
2412 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \
2414 if (asc_dbglvl >= (lvl)) { \
2415 asc_prt_adv_scsi_req_q(scsiqp); \
2419 #define ASC_DBG_PRT_HEX(lvl, name, start, length) \
2421 if (asc_dbglvl >= (lvl)) { \
2422 asc_prt_hex((name), (start), (length)); \
2426 #define ASC_DBG_PRT_CDB(lvl, cdb, len) \
2427 ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len));
2429 #define ASC_DBG_PRT_SENSE(lvl, sense, len) \
2430 ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len));
2432 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \
2433 ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len));
2434 #endif /* ADVANSYS_DEBUG */
2436 #ifdef ADVANSYS_STATS
2438 /* Per board statistics structure */
2440 /* Driver Entrypoint Statistics */
2441 ADV_DCNT queuecommand; /* # calls to advansys_queuecommand() */
2442 ADV_DCNT reset; /* # calls to advansys_eh_bus_reset() */
2443 ADV_DCNT biosparam; /* # calls to advansys_biosparam() */
2444 ADV_DCNT interrupt; /* # advansys_interrupt() calls */
2445 ADV_DCNT callback; /* # calls to asc/adv_isr_callback() */
2446 ADV_DCNT done; /* # calls to request's scsi_done function */
2447 ADV_DCNT build_error; /* # asc/adv_build_req() ASC_ERROR returns. */
2448 ADV_DCNT adv_build_noreq; /* # adv_build_req() adv_req_t alloc. fail. */
2449 ADV_DCNT adv_build_nosg; /* # adv_build_req() adv_sgblk_t alloc. fail. */
2450 /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
2451 ADV_DCNT exe_noerror; /* # ASC_NOERROR returns. */
2452 ADV_DCNT exe_busy; /* # ASC_BUSY returns. */
2453 ADV_DCNT exe_error; /* # ASC_ERROR returns. */
2454 ADV_DCNT exe_unknown; /* # unknown returns. */
2455 /* Data Transfer Statistics */
2456 ADV_DCNT cont_cnt; /* # non-scatter-gather I/O requests received */
2457 ADV_DCNT cont_xfer; /* # contiguous transfer 512-bytes */
2458 ADV_DCNT sg_cnt; /* # scatter-gather I/O requests received */
2459 ADV_DCNT sg_elem; /* # scatter-gather elements */
2460 ADV_DCNT sg_xfer; /* # scatter-gather transfer 512-bytes */
2462 #endif /* ADVANSYS_STATS */
2465 * Adv Library Request Structures
2467 * The following two structures are used to process Wide Board requests.
2469 * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
2470 * and microcode with the ADV_SCSI_REQ_Q field 'srb_ptr' pointing to the
2471 * adv_req_t. The adv_req_t structure 'cmndp' field in turn points to the
2472 * Mid-Level SCSI request structure.
2474 * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
2475 * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
2476 * up to 255 scatter-gather elements may be used per request or
2479 * Both structures must be 32 byte aligned.
2481 typedef struct adv_sgblk {
2482 ADV_SG_BLOCK sg_block; /* Sgblock structure. */
2483 uchar align[32]; /* Sgblock structure padding. */
2484 struct adv_sgblk *next_sgblkp; /* Next scatter-gather structure. */
2487 typedef struct adv_req {
2488 ADV_SCSI_REQ_Q scsi_req_q; /* Adv Library request structure. */
2489 uchar align[32]; /* Request structure padding. */
2490 struct scsi_cmnd *cmndp; /* Mid-Level SCSI command pointer. */
2491 adv_sgblk_t *sgblkp; /* Adv Library scatter-gather pointer. */
2492 struct adv_req *next_reqp; /* Next Request Structure. */
2496 * Structure allocated for each board.
2498 * This structure is allocated by scsi_host_alloc() at the end
2499 * of the 'Scsi_Host' structure starting at the 'hostdata'
2500 * field. It is guaranteed to be allocated from DMA-able memory.
2502 typedef struct asc_board {
2504 int id; /* Board Id */
2505 uint flags; /* Board flags */
2507 ASC_DVC_VAR asc_dvc_var; /* Narrow board */
2508 ADV_DVC_VAR adv_dvc_var; /* Wide board */
2511 ASC_DVC_CFG asc_dvc_cfg; /* Narrow board */
2512 ADV_DVC_CFG adv_dvc_cfg; /* Wide board */
2514 ushort asc_n_io_port; /* Number I/O ports. */
2515 ADV_SCSI_BIT_ID_TYPE init_tidmask; /* Target init./valid mask */
2516 ushort reqcnt[ADV_MAX_TID + 1]; /* Starvation request count */
2517 ADV_SCSI_BIT_ID_TYPE queue_full; /* Queue full mask */
2518 ushort queue_full_cnt[ADV_MAX_TID + 1]; /* Queue full count */
2520 ASCEEP_CONFIG asc_eep; /* Narrow EEPROM config. */
2521 ADVEEP_3550_CONFIG adv_3550_eep; /* 3550 EEPROM config. */
2522 ADVEEP_38C0800_CONFIG adv_38C0800_eep; /* 38C0800 EEPROM config. */
2523 ADVEEP_38C1600_CONFIG adv_38C1600_eep; /* 38C1600 EEPROM config. */
2525 ulong last_reset; /* Saved last reset time */
2526 spinlock_t lock; /* Board spinlock */
2527 /* /proc/scsi/advansys/[0...] */
2528 char *prtbuf; /* /proc print buffer */
2529 #ifdef ADVANSYS_STATS
2530 struct asc_stats asc_stats; /* Board statistics */
2531 #endif /* ADVANSYS_STATS */
2533 * The following fields are used only for Narrow Boards.
2535 uchar sdtr_data[ASC_MAX_TID + 1]; /* SDTR information */
2537 * The following fields are used only for Wide Boards.
2539 void __iomem *ioremap_addr; /* I/O Memory remap address. */
2540 ushort ioport; /* I/O Port address. */
2541 ADV_CARR_T *carrp; /* ADV_CARR_T memory block. */
2542 adv_req_t *orig_reqp; /* adv_req_t memory block. */
2543 adv_req_t *adv_reqp; /* Request structures. */
2544 adv_sgblk_t *adv_sgblkp; /* Scatter-gather structures. */
2545 ushort bios_signature; /* BIOS Signature. */
2546 ushort bios_version; /* BIOS Version. */
2547 ushort bios_codeseg; /* BIOS Code Segment. */
2548 ushort bios_codelen; /* BIOS Code Segment Length. */
2551 #define adv_dvc_to_board(adv_dvc) container_of(adv_dvc, struct asc_board, \
2552 dvc_var.adv_dvc_var)
2553 #define adv_dvc_to_pdev(adv_dvc) to_pci_dev(adv_dvc_to_board(adv_dvc)->dev)
2555 /* Number of boards detected in system. */
2556 static int asc_board_count;
2558 /* Overrun buffer used by all narrow boards. */
2559 static uchar overrun_buf[ASC_OVERRUN_BSIZE] = { 0 };
2561 #ifdef ADVANSYS_DEBUG
2562 static int asc_dbglvl = 3;
2565 * asc_prt_scsi_host()
2567 static void asc_prt_scsi_host(struct Scsi_Host *s)
2569 asc_board_t *boardp;
2571 boardp = ASC_BOARDP(s);
2573 printk("Scsi_Host at addr 0x%lx\n", (ulong)s);
2574 printk(" host_busy %u, host_no %d, last_reset %d,\n",
2575 s->host_busy, s->host_no, (unsigned)s->last_reset);
2577 printk(" base 0x%lx, io_port 0x%lx, irq 0x%x,\n",
2578 (ulong)s->base, (ulong)s->io_port, s->irq);
2580 printk(" dma_channel %d, this_id %d, can_queue %d,\n",
2581 s->dma_channel, s->this_id, s->can_queue);
2583 printk(" cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n",
2584 s->cmd_per_lun, s->sg_tablesize, s->unchecked_isa_dma);
2586 if (ASC_NARROW_BOARD(boardp)) {
2587 asc_prt_asc_dvc_var(&ASC_BOARDP(s)->dvc_var.asc_dvc_var);
2588 asc_prt_asc_dvc_cfg(&ASC_BOARDP(s)->dvc_cfg.asc_dvc_cfg);
2590 asc_prt_adv_dvc_var(&ASC_BOARDP(s)->dvc_var.adv_dvc_var);
2591 asc_prt_adv_dvc_cfg(&ASC_BOARDP(s)->dvc_cfg.adv_dvc_cfg);
2596 * asc_prt_scsi_cmnd()
2598 static void asc_prt_scsi_cmnd(struct scsi_cmnd *s)
2600 printk("struct scsi_cmnd at addr 0x%lx\n", (ulong)s);
2602 printk(" host 0x%lx, device 0x%lx, target %u, lun %u, channel %u,\n",
2603 (ulong)s->device->host, (ulong)s->device, s->device->id,
2604 s->device->lun, s->device->channel);
2606 asc_prt_hex(" CDB", s->cmnd, s->cmd_len);
2608 printk("sc_data_direction %u, resid %d\n",
2609 s->sc_data_direction, s->resid);
2611 printk(" use_sg %u, sglist_len %u\n", s->use_sg, s->sglist_len);
2613 printk(" serial_number 0x%x, retries %d, allowed %d\n",
2614 (unsigned)s->serial_number, s->retries, s->allowed);
2616 printk(" timeout_per_command %d\n", s->timeout_per_command);
2618 printk(" scsi_done 0x%p, done 0x%p, host_scribble 0x%p, result 0x%x\n",
2619 s->scsi_done, s->done, s->host_scribble, s->result);
2621 printk(" tag %u, pid %u\n", (unsigned)s->tag, (unsigned)s->pid);
2625 * asc_prt_asc_dvc_var()
2627 static void asc_prt_asc_dvc_var(ASC_DVC_VAR *h)
2629 printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong)h);
2631 printk(" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl "
2632 "%d,\n", h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl);
2634 printk(" bus_type %d, init_sdtr 0x%x,\n", h->bus_type,
2635 (unsigned)h->init_sdtr);
2637 printk(" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, "
2638 "chip_no 0x%x,\n", (unsigned)h->sdtr_done,
2639 (unsigned)h->use_tagged_qng, (unsigned)h->unit_not_ready,
2640 (unsigned)h->chip_no);
2642 printk(" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait "
2643 "%u,\n", (unsigned)h->queue_full_or_busy,
2644 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2646 printk(" is_in_int %u, max_total_qng %u, cur_total_qng %u, "
2647 "in_critical_cnt %u,\n", (unsigned)h->is_in_int,
2648 (unsigned)h->max_total_qng, (unsigned)h->cur_total_qng,
2649 (unsigned)h->in_critical_cnt);
2651 printk(" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, "
2652 "pci_fix_asyn_xfer 0x%x,\n", (unsigned)h->last_q_shortage,
2653 (unsigned)h->init_state, (unsigned)h->no_scam,
2654 (unsigned)h->pci_fix_asyn_xfer);
2656 printk(" cfg 0x%lx, irq_no 0x%x\n", (ulong)h->cfg, (unsigned)h->irq_no);
2660 * asc_prt_asc_dvc_cfg()
2662 static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h)
2664 printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong)h);
2666 printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n",
2667 h->can_tagged_qng, h->cmd_qng_enabled);
2668 printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n",
2669 h->disc_enable, h->sdtr_enable);
2672 (" chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, chip_version %d,\n",
2673 h->chip_scsi_id, h->isa_dma_speed, h->isa_dma_channel,
2677 (" pci_device_id %d, lib_serial_no %u, lib_version %u, mcode_date 0x%x,\n",
2678 to_pci_dev(h->dev)->device, h->lib_serial_no, h->lib_version,
2681 printk(" mcode_version %d, overrun_buf 0x%lx\n",
2682 h->mcode_version, (ulong)h->overrun_buf);
2686 * asc_prt_asc_scsi_q()
2688 static void asc_prt_asc_scsi_q(ASC_SCSI_Q *q)
2693 printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong)q);
2696 (" target_ix 0x%x, target_lun %u, srb_ptr 0x%lx, tag_code 0x%x,\n",
2697 q->q2.target_ix, q->q1.target_lun, (ulong)q->q2.srb_ptr,
2701 (" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2702 (ulong)le32_to_cpu(q->q1.data_addr),
2703 (ulong)le32_to_cpu(q->q1.data_cnt),
2704 (ulong)le32_to_cpu(q->q1.sense_addr), q->q1.sense_len);
2706 printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n",
2707 (ulong)q->cdbptr, q->q2.cdb_len,
2708 (ulong)q->sg_head, q->q1.sg_queue_cnt);
2712 printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong)sgp);
2713 printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt,
2715 for (i = 0; i < sgp->entry_cnt; i++) {
2716 printk(" [%u]: addr 0x%lx, bytes %lu\n",
2717 i, (ulong)le32_to_cpu(sgp->sg_list[i].addr),
2718 (ulong)le32_to_cpu(sgp->sg_list[i].bytes));
2725 * asc_prt_asc_qdone_info()
2727 static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *q)
2729 printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong)q);
2730 printk(" srb_ptr 0x%lx, target_ix %u, cdb_len %u, tag_code %u,\n",
2731 (ulong)q->d2.srb_ptr, q->d2.target_ix, q->d2.cdb_len,
2734 (" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n",
2735 q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg);
2739 * asc_prt_adv_dvc_var()
2741 * Display an ADV_DVC_VAR structure.
2743 static void asc_prt_adv_dvc_var(ADV_DVC_VAR *h)
2745 printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong)h);
2747 printk(" iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n",
2748 (ulong)h->iop_base, h->err_code, (unsigned)h->ultra_able);
2750 printk(" isr_callback 0x%lx, sdtr_able 0x%x, wdtr_able 0x%x\n",
2751 (ulong)h->isr_callback, (unsigned)h->sdtr_able,
2752 (unsigned)h->wdtr_able);
2754 printk(" start_motor 0x%x, scsi_reset_wait 0x%x, irq_no 0x%x,\n",
2755 (unsigned)h->start_motor,
2756 (unsigned)h->scsi_reset_wait, (unsigned)h->irq_no);
2758 printk(" max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%lxn\n",
2759 (unsigned)h->max_host_qng, (unsigned)h->max_dvc_qng,
2760 (ulong)h->carr_freelist);
2762 printk(" icq_sp 0x%lx, irq_sp 0x%lx\n",
2763 (ulong)h->icq_sp, (ulong)h->irq_sp);
2765 printk(" no_scam 0x%x, tagqng_able 0x%x\n",
2766 (unsigned)h->no_scam, (unsigned)h->tagqng_able);
2768 printk(" chip_scsi_id 0x%x, cfg 0x%lx\n",
2769 (unsigned)h->chip_scsi_id, (ulong)h->cfg);
2773 * asc_prt_adv_dvc_cfg()
2775 * Display an ADV_DVC_CFG structure.
2777 static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h)
2779 printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong)h);
2781 printk(" disc_enable 0x%x, termination 0x%x\n",
2782 h->disc_enable, h->termination);
2784 printk(" chip_version 0x%x, mcode_date 0x%x\n",
2785 h->chip_version, h->mcode_date);
2787 printk(" mcode_version 0x%x, pci_device_id 0x%x, lib_version %u\n",
2788 h->mcode_version, to_pci_dev(h->dev)->device, h->lib_version);
2790 printk(" control_flag 0x%x\n", h->control_flag);
2794 * asc_prt_adv_scsi_req_q()
2796 * Display an ADV_SCSI_REQ_Q structure.
2798 static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q)
2801 struct asc_sg_block *sg_ptr;
2803 printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong)q);
2805 printk(" target_id %u, target_lun %u, srb_ptr 0x%lx, a_flag 0x%x\n",
2806 q->target_id, q->target_lun, (ulong)q->srb_ptr, q->a_flag);
2808 printk(" cntl 0x%x, data_addr 0x%lx, vdata_addr 0x%lx\n",
2809 q->cntl, (ulong)le32_to_cpu(q->data_addr), (ulong)q->vdata_addr);
2811 printk(" data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2812 (ulong)le32_to_cpu(q->data_cnt),
2813 (ulong)le32_to_cpu(q->sense_addr), q->sense_len);
2816 (" cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
2817 q->cdb_len, q->done_status, q->host_status, q->scsi_status);
2819 printk(" sg_working_ix 0x%x, target_cmd %u\n",
2820 q->sg_working_ix, q->target_cmd);
2822 printk(" scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n",
2823 (ulong)le32_to_cpu(q->scsiq_rptr),
2824 (ulong)le32_to_cpu(q->sg_real_addr), (ulong)q->sg_list_ptr);
2826 /* Display the request's ADV_SG_BLOCK structures. */
2827 if (q->sg_list_ptr != NULL) {
2831 * 'sg_ptr' is a physical address. Convert it to a virtual
2832 * address by indexing 'sg_blk_cnt' into the virtual address
2833 * array 'sg_list_ptr'.
2835 * XXX - Assumes all SG physical blocks are virtually contiguous.
2838 &(((ADV_SG_BLOCK *)(q->sg_list_ptr))[sg_blk_cnt]);
2839 asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr);
2840 if (sg_ptr->sg_ptr == 0) {
2849 * asc_prt_adv_sgblock()
2851 * Display an ADV_SG_BLOCK structure.
2853 static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b)
2857 printk(" ASC_SG_BLOCK at addr 0x%lx (sgblockno %d)\n",
2858 (ulong)b, sgblockno);
2859 printk(" sg_cnt %u, sg_ptr 0x%lx\n",
2860 b->sg_cnt, (ulong)le32_to_cpu(b->sg_ptr));
2861 BUG_ON(b->sg_cnt > NO_OF_SG_PER_BLOCK);
2863 BUG_ON(b->sg_cnt != NO_OF_SG_PER_BLOCK);
2864 for (i = 0; i < b->sg_cnt; i++) {
2865 printk(" [%u]: sg_addr 0x%lx, sg_count 0x%lx\n",
2866 i, (ulong)b->sg_list[i].sg_addr,
2867 (ulong)b->sg_list[i].sg_count);
2874 * Print hexadecimal output in 4 byte groupings 32 bytes
2875 * or 8 double-words per line.
2877 static void asc_prt_hex(char *f, uchar *s, int l)
2884 printk("%s: (%d bytes)\n", f, l);
2886 for (i = 0; i < l; i += 32) {
2888 /* Display a maximum of 8 double-words per line. */
2889 if ((k = (l - i) / 4) >= 8) {
2896 for (j = 0; j < k; j++) {
2897 printk(" %2.2X%2.2X%2.2X%2.2X",
2898 (unsigned)s[i + (j * 4)],
2899 (unsigned)s[i + (j * 4) + 1],
2900 (unsigned)s[i + (j * 4) + 2],
2901 (unsigned)s[i + (j * 4) + 3]);
2909 printk(" %2.2X", (unsigned)s[i + (j * 4)]);
2912 printk(" %2.2X%2.2X",
2913 (unsigned)s[i + (j * 4)],
2914 (unsigned)s[i + (j * 4) + 1]);
2917 printk(" %2.2X%2.2X%2.2X",
2918 (unsigned)s[i + (j * 4) + 1],
2919 (unsigned)s[i + (j * 4) + 2],
2920 (unsigned)s[i + (j * 4) + 3]);
2927 #endif /* ADVANSYS_DEBUG */
2932 * Return suitable for printing on the console with the argument
2933 * adapter's configuration information.
2935 * Note: The information line should not exceed ASC_INFO_SIZE bytes,
2936 * otherwise the static 'info' array will be overrun.
2938 static const char *advansys_info(struct Scsi_Host *shost)
2940 static char info[ASC_INFO_SIZE];
2941 asc_board_t *boardp;
2942 ASC_DVC_VAR *asc_dvc_varp;
2943 ADV_DVC_VAR *adv_dvc_varp;
2945 char *widename = NULL;
2947 boardp = ASC_BOARDP(shost);
2948 if (ASC_NARROW_BOARD(boardp)) {
2949 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
2950 ASC_DBG(1, "advansys_info: begin\n");
2951 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
2952 if ((asc_dvc_varp->bus_type & ASC_IS_ISAPNP) ==
2954 busname = "ISA PnP";
2959 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X",
2960 ASC_VERSION, busname,
2961 (ulong)shost->io_port,
2962 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2963 shost->irq, shost->dma_channel);
2965 if (asc_dvc_varp->bus_type & ASC_IS_VL) {
2967 } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) {
2969 } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) {
2970 if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA)
2971 == ASC_IS_PCI_ULTRA) {
2972 busname = "PCI Ultra";
2978 ASC_PRINT2("advansys_info: board %d: unknown "
2979 "bus type %d\n", boardp->id,
2980 asc_dvc_varp->bus_type);
2983 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X",
2984 ASC_VERSION, busname, (ulong)shost->io_port,
2985 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2990 * Wide Adapter Information
2992 * Memory-mapped I/O is used instead of I/O space to access
2993 * the adapter, but display the I/O Port range. The Memory
2994 * I/O address is displayed through the driver /proc file.
2996 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
2997 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2998 widename = "Ultra-Wide";
2999 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3000 widename = "Ultra2-Wide";
3002 widename = "Ultra3-Wide";
3005 "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X",
3006 ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base,
3007 (ulong)adv_dvc_varp->iop_base + boardp->asc_n_io_port - 1, shost->irq);
3009 BUG_ON(strlen(info) >= ASC_INFO_SIZE);
3010 ASC_DBG(1, "advansys_info: end\n");
3014 #ifdef CONFIG_PROC_FS
3018 * If 'cp' is NULL print to the console, otherwise print to a buffer.
3020 * Return 0 if printing to the console, otherwise return the number of
3021 * bytes written to the buffer.
3023 * Note: If any single line is greater than ASC_PRTLINE_SIZE bytes the stack
3024 * will be corrupted. 's[]' is defined to be ASC_PRTLINE_SIZE bytes.
3026 static int asc_prt_line(char *buf, int buflen, char *fmt, ...)
3030 char s[ASC_PRTLINE_SIZE];
3032 va_start(args, fmt);
3033 ret = vsprintf(s, fmt, args);
3034 BUG_ON(ret >= ASC_PRTLINE_SIZE);
3039 ret = min(buflen, ret);
3040 memcpy(buf, s, ret);
3047 * asc_prt_board_devices()
3049 * Print driver information for devices attached to the board.
3051 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3052 * cf. asc_prt_line().
3054 * Return the number of characters copied into 'cp'. No more than
3055 * 'cplen' characters will be copied to 'cp'.
3057 static int asc_prt_board_devices(struct Scsi_Host *shost, char *cp, int cplen)
3059 asc_board_t *boardp;
3066 boardp = ASC_BOARDP(shost);
3070 len = asc_prt_line(cp, leftlen,
3071 "\nDevice Information for AdvanSys SCSI Host %d:\n",
3075 if (ASC_NARROW_BOARD(boardp)) {
3076 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
3078 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
3081 len = asc_prt_line(cp, leftlen, "Target IDs Detected:");
3083 for (i = 0; i <= ADV_MAX_TID; i++) {
3084 if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) {
3085 len = asc_prt_line(cp, leftlen, " %X,", i);
3089 len = asc_prt_line(cp, leftlen, " (%X=Host Adapter)\n", chip_scsi_id);
3096 * Display Wide Board BIOS Information.
3098 static int asc_prt_adv_bios(struct Scsi_Host *shost, char *cp, int cplen)
3100 asc_board_t *boardp;
3104 ushort major, minor, letter;
3106 boardp = ASC_BOARDP(shost);
3110 len = asc_prt_line(cp, leftlen, "\nROM BIOS Version: ");
3114 * If the BIOS saved a valid signature, then fill in
3115 * the BIOS code segment base address.
3117 if (boardp->bios_signature != 0x55AA) {
3118 len = asc_prt_line(cp, leftlen, "Disabled or Pre-3.1\n");
3120 len = asc_prt_line(cp, leftlen,
3121 "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n");
3123 len = asc_prt_line(cp, leftlen,
3124 "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n");
3127 major = (boardp->bios_version >> 12) & 0xF;
3128 minor = (boardp->bios_version >> 8) & 0xF;
3129 letter = (boardp->bios_version & 0xFF);
3131 len = asc_prt_line(cp, leftlen, "%d.%d%c\n",
3133 letter >= 26 ? '?' : letter + 'A');
3137 * Current available ROM BIOS release is 3.1I for UW
3138 * and 3.2I for U2W. This code doesn't differentiate
3139 * UW and U2W boards.
3141 if (major < 3 || (major <= 3 && minor < 1) ||
3142 (major <= 3 && minor <= 1 && letter < ('I' - 'A'))) {
3143 len = asc_prt_line(cp, leftlen,
3144 "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n");
3146 len = asc_prt_line(cp, leftlen,
3147 "ftp://ftp.connectcom.net/pub\n");
3156 * Add serial number to information bar if signature AAh
3157 * is found in at bit 15-9 (7 bits) of word 1.
3159 * Serial Number consists fo 12 alpha-numeric digits.
3161 * 1 - Product type (A,B,C,D..) Word0: 15-13 (3 bits)
3162 * 2 - MFG Location (A,B,C,D..) Word0: 12-10 (3 bits)
3163 * 3-4 - Product ID (0-99) Word0: 9-0 (10 bits)
3164 * 5 - Product revision (A-J) Word0: " "
3166 * Signature Word1: 15-9 (7 bits)
3167 * 6 - Year (0-9) Word1: 8-6 (3 bits) & Word2: 15 (1 bit)
3168 * 7-8 - Week of the year (1-52) Word1: 5-0 (6 bits)
3170 * 9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits)
3172 * Note 1: Only production cards will have a serial number.
3174 * Note 2: Signature is most significant 7 bits (0xFE).
3176 * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE.
3178 static int asc_get_eeprom_string(ushort *serialnum, uchar *cp)
3182 if ((serialnum[1] & 0xFE00) != ((ushort)0xAA << 8)) {
3186 * First word - 6 digits.
3190 /* Product type - 1st digit. */
3191 if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') {
3192 /* Product type is P=Prototype */
3197 /* Manufacturing location - 2nd digit. */
3198 *cp++ = 'A' + ((w & 0x1C00) >> 10);
3200 /* Product ID - 3rd, 4th digits. */
3202 *cp++ = '0' + (num / 100);
3204 *cp++ = '0' + (num / 10);
3206 /* Product revision - 5th digit. */
3207 *cp++ = 'A' + (num % 10);
3217 * If bit 15 of third word is set, then the
3218 * last digit of the year is greater than 7.
3220 if (serialnum[2] & 0x8000) {
3221 *cp++ = '8' + ((w & 0x1C0) >> 6);
3223 *cp++ = '0' + ((w & 0x1C0) >> 6);
3226 /* Week of year - 7th, 8th digits. */
3228 *cp++ = '0' + num / 10;
3235 w = serialnum[2] & 0x7FFF;
3237 /* Serial number - 9th digit. */
3238 *cp++ = 'A' + (w / 1000);
3240 /* 10th, 11th, 12th digits. */
3242 *cp++ = '0' + num / 100;
3244 *cp++ = '0' + num / 10;
3248 *cp = '\0'; /* Null Terminate the string. */
3254 * asc_prt_asc_board_eeprom()
3256 * Print board EEPROM configuration.
3258 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3259 * cf. asc_prt_line().
3261 * Return the number of characters copied into 'cp'. No more than
3262 * 'cplen' characters will be copied to 'cp'.
3264 static int asc_prt_asc_board_eeprom(struct Scsi_Host *shost, char *cp, int cplen)
3266 asc_board_t *boardp;
3267 ASC_DVC_VAR *asc_dvc_varp;
3274 int isa_dma_speed[] = { 10, 8, 7, 6, 5, 4, 3, 2 };
3275 #endif /* CONFIG_ISA */
3276 uchar serialstr[13];
3278 boardp = ASC_BOARDP(shost);
3279 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
3280 ep = &boardp->eep_config.asc_eep;
3285 len = asc_prt_line(cp, leftlen,
3286 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3290 if (asc_get_eeprom_string((ushort *)&ep->adapter_info[0], serialstr)
3293 asc_prt_line(cp, leftlen, " Serial Number: %s\n",
3297 if (ep->adapter_info[5] == 0xBB) {
3298 len = asc_prt_line(cp, leftlen,
3299 " Default Settings Used for EEPROM-less Adapter.\n");
3302 len = asc_prt_line(cp, leftlen,
3303 " Serial Number Signature Not Present.\n");
3308 len = asc_prt_line(cp, leftlen,
3309 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3310 ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng,
3314 len = asc_prt_line(cp, leftlen,
3315 " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam);
3318 len = asc_prt_line(cp, leftlen, " Target ID: ");
3320 for (i = 0; i <= ASC_MAX_TID; i++) {
3321 len = asc_prt_line(cp, leftlen, " %d", i);
3324 len = asc_prt_line(cp, leftlen, "\n");
3327 len = asc_prt_line(cp, leftlen, " Disconnects: ");
3329 for (i = 0; i <= ASC_MAX_TID; i++) {
3330 len = asc_prt_line(cp, leftlen, " %c",
3332 disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3336 len = asc_prt_line(cp, leftlen, "\n");
3339 len = asc_prt_line(cp, leftlen, " Command Queuing: ");
3341 for (i = 0; i <= ASC_MAX_TID; i++) {
3342 len = asc_prt_line(cp, leftlen, " %c",
3344 use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3348 len = asc_prt_line(cp, leftlen, "\n");
3351 len = asc_prt_line(cp, leftlen, " Start Motor: ");
3353 for (i = 0; i <= ASC_MAX_TID; i++) {
3354 len = asc_prt_line(cp, leftlen, " %c",
3356 start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3360 len = asc_prt_line(cp, leftlen, "\n");
3363 len = asc_prt_line(cp, leftlen, " Synchronous Transfer:");
3365 for (i = 0; i <= ASC_MAX_TID; i++) {
3366 len = asc_prt_line(cp, leftlen, " %c",
3368 init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3372 len = asc_prt_line(cp, leftlen, "\n");
3376 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
3377 len = asc_prt_line(cp, leftlen,
3378 " Host ISA DMA speed: %d MB/S\n",
3379 isa_dma_speed[ASC_EEP_GET_DMA_SPD(ep)]);
3382 #endif /* CONFIG_ISA */
3388 * asc_prt_adv_board_eeprom()
3390 * Print board EEPROM configuration.
3392 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3393 * cf. asc_prt_line().
3395 * Return the number of characters copied into 'cp'. No more than
3396 * 'cplen' characters will be copied to 'cp'.
3398 static int asc_prt_adv_board_eeprom(struct Scsi_Host *shost, char *cp, int cplen)
3400 asc_board_t *boardp;
3401 ADV_DVC_VAR *adv_dvc_varp;
3407 uchar serialstr[13];
3408 ADVEEP_3550_CONFIG *ep_3550 = NULL;
3409 ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL;
3410 ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL;
3413 ushort sdtr_speed = 0;
3415 boardp = ASC_BOARDP(shost);
3416 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
3417 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3418 ep_3550 = &boardp->eep_config.adv_3550_eep;
3419 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3420 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
3422 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
3428 len = asc_prt_line(cp, leftlen,
3429 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3433 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3434 wordp = &ep_3550->serial_number_word1;
3435 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3436 wordp = &ep_38C0800->serial_number_word1;
3438 wordp = &ep_38C1600->serial_number_word1;
3441 if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE) {
3443 asc_prt_line(cp, leftlen, " Serial Number: %s\n",
3447 len = asc_prt_line(cp, leftlen,
3448 " Serial Number Signature Not Present.\n");
3452 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3453 len = asc_prt_line(cp, leftlen,
3454 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3455 ep_3550->adapter_scsi_id,
3456 ep_3550->max_host_qng, ep_3550->max_dvc_qng);
3458 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3459 len = asc_prt_line(cp, leftlen,
3460 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3461 ep_38C0800->adapter_scsi_id,
3462 ep_38C0800->max_host_qng,
3463 ep_38C0800->max_dvc_qng);
3466 len = asc_prt_line(cp, leftlen,
3467 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3468 ep_38C1600->adapter_scsi_id,
3469 ep_38C1600->max_host_qng,
3470 ep_38C1600->max_dvc_qng);
3473 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3474 word = ep_3550->termination;
3475 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3476 word = ep_38C0800->termination_lvd;
3478 word = ep_38C1600->termination_lvd;
3482 termstr = "Low Off/High Off";
3485 termstr = "Low Off/High On";
3488 termstr = "Low On/High On";
3492 termstr = "Automatic";
3496 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3497 len = asc_prt_line(cp, leftlen,
3498 " termination: %u (%s), bios_ctrl: 0x%x\n",
3499 ep_3550->termination, termstr,
3500 ep_3550->bios_ctrl);
3502 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3503 len = asc_prt_line(cp, leftlen,
3504 " termination: %u (%s), bios_ctrl: 0x%x\n",
3505 ep_38C0800->termination_lvd, termstr,
3506 ep_38C0800->bios_ctrl);
3509 len = asc_prt_line(cp, leftlen,
3510 " termination: %u (%s), bios_ctrl: 0x%x\n",
3511 ep_38C1600->termination_lvd, termstr,
3512 ep_38C1600->bios_ctrl);
3516 len = asc_prt_line(cp, leftlen, " Target ID: ");
3518 for (i = 0; i <= ADV_MAX_TID; i++) {
3519 len = asc_prt_line(cp, leftlen, " %X", i);
3522 len = asc_prt_line(cp, leftlen, "\n");
3525 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3526 word = ep_3550->disc_enable;
3527 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3528 word = ep_38C0800->disc_enable;
3530 word = ep_38C1600->disc_enable;
3532 len = asc_prt_line(cp, leftlen, " Disconnects: ");
3534 for (i = 0; i <= ADV_MAX_TID; i++) {
3535 len = asc_prt_line(cp, leftlen, " %c",
3536 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3539 len = asc_prt_line(cp, leftlen, "\n");
3542 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3543 word = ep_3550->tagqng_able;
3544 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3545 word = ep_38C0800->tagqng_able;
3547 word = ep_38C1600->tagqng_able;
3549 len = asc_prt_line(cp, leftlen, " Command Queuing: ");
3551 for (i = 0; i <= ADV_MAX_TID; i++) {
3552 len = asc_prt_line(cp, leftlen, " %c",
3553 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3556 len = asc_prt_line(cp, leftlen, "\n");
3559 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3560 word = ep_3550->start_motor;
3561 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3562 word = ep_38C0800->start_motor;
3564 word = ep_38C1600->start_motor;
3566 len = asc_prt_line(cp, leftlen, " Start Motor: ");
3568 for (i = 0; i <= ADV_MAX_TID; i++) {
3569 len = asc_prt_line(cp, leftlen, " %c",
3570 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3573 len = asc_prt_line(cp, leftlen, "\n");
3576 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3577 len = asc_prt_line(cp, leftlen, " Synchronous Transfer:");
3579 for (i = 0; i <= ADV_MAX_TID; i++) {
3580 len = asc_prt_line(cp, leftlen, " %c",
3582 sdtr_able & ADV_TID_TO_TIDMASK(i)) ?
3586 len = asc_prt_line(cp, leftlen, "\n");
3590 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3591 len = asc_prt_line(cp, leftlen, " Ultra Transfer: ");
3593 for (i = 0; i <= ADV_MAX_TID; i++) {
3594 len = asc_prt_line(cp, leftlen, " %c",
3596 ultra_able & ADV_TID_TO_TIDMASK(i))
3600 len = asc_prt_line(cp, leftlen, "\n");
3604 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3605 word = ep_3550->wdtr_able;
3606 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3607 word = ep_38C0800->wdtr_able;
3609 word = ep_38C1600->wdtr_able;
3611 len = asc_prt_line(cp, leftlen, " Wide Transfer: ");
3613 for (i = 0; i <= ADV_MAX_TID; i++) {
3614 len = asc_prt_line(cp, leftlen, " %c",
3615 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3618 len = asc_prt_line(cp, leftlen, "\n");
3621 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 ||
3622 adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600) {
3623 len = asc_prt_line(cp, leftlen,
3624 " Synchronous Transfer Speed (Mhz):\n ");
3626 for (i = 0; i <= ADV_MAX_TID; i++) {
3630 sdtr_speed = adv_dvc_varp->sdtr_speed1;
3631 } else if (i == 4) {
3632 sdtr_speed = adv_dvc_varp->sdtr_speed2;
3633 } else if (i == 8) {
3634 sdtr_speed = adv_dvc_varp->sdtr_speed3;
3635 } else if (i == 12) {
3636 sdtr_speed = adv_dvc_varp->sdtr_speed4;
3638 switch (sdtr_speed & ADV_MAX_TID) {
3661 len = asc_prt_line(cp, leftlen, "%X:%s ", i, speed_str);
3664 len = asc_prt_line(cp, leftlen, "\n ");
3669 len = asc_prt_line(cp, leftlen, "\n");
3677 * asc_prt_driver_conf()
3679 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3680 * cf. asc_prt_line().
3682 * Return the number of characters copied into 'cp'. No more than
3683 * 'cplen' characters will be copied to 'cp'.
3685 static int asc_prt_driver_conf(struct Scsi_Host *shost, char *cp, int cplen)
3687 asc_board_t *boardp;
3693 boardp = ASC_BOARDP(shost);
3698 len = asc_prt_line(cp, leftlen,
3699 "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n",
3703 len = asc_prt_line(cp, leftlen,
3704 " host_busy %u, last_reset %u, max_id %u, max_lun %u, max_channel %u\n",
3705 shost->host_busy, shost->last_reset, shost->max_id,
3706 shost->max_lun, shost->max_channel);
3709 len = asc_prt_line(cp, leftlen,
3710 " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n",
3711 shost->unique_id, shost->can_queue, shost->this_id,
3712 shost->sg_tablesize, shost->cmd_per_lun);
3715 len = asc_prt_line(cp, leftlen,
3716 " unchecked_isa_dma %d, use_clustering %d\n",
3717 shost->unchecked_isa_dma, shost->use_clustering);
3720 len = asc_prt_line(cp, leftlen,
3721 " flags 0x%x, last_reset 0x%x, jiffies 0x%x, asc_n_io_port 0x%x\n",
3722 boardp->flags, boardp->last_reset, jiffies,
3723 boardp->asc_n_io_port);
3726 len = asc_prt_line(cp, leftlen, " io_port 0x%x\n", shost->io_port);
3729 if (ASC_NARROW_BOARD(boardp)) {
3730 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
3732 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
3739 * asc_prt_asc_board_info()
3741 * Print dynamic board configuration information.
3743 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3744 * cf. asc_prt_line().
3746 * Return the number of characters copied into 'cp'. No more than
3747 * 'cplen' characters will be copied to 'cp'.
3749 static int asc_prt_asc_board_info(struct Scsi_Host *shost, char *cp, int cplen)
3751 asc_board_t *boardp;
3759 int renegotiate = 0;
3761 boardp = ASC_BOARDP(shost);
3762 v = &boardp->dvc_var.asc_dvc_var;
3763 c = &boardp->dvc_cfg.asc_dvc_cfg;
3764 chip_scsi_id = c->chip_scsi_id;
3769 len = asc_prt_line(cp, leftlen,
3770 "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3774 len = asc_prt_line(cp, leftlen,
3775 " chip_version %u, lib_version 0x%x, lib_serial_no %u, mcode_date 0x%x\n",
3776 c->chip_version, c->lib_version, c->lib_serial_no,
3780 len = asc_prt_line(cp, leftlen,
3781 " mcode_version 0x%x, err_code %u\n",
3782 c->mcode_version, v->err_code);
3785 /* Current number of commands waiting for the host. */
3786 len = asc_prt_line(cp, leftlen,
3787 " Total Command Pending: %d\n", v->cur_total_qng);
3790 len = asc_prt_line(cp, leftlen, " Command Queuing:");
3792 for (i = 0; i <= ASC_MAX_TID; i++) {
3793 if ((chip_scsi_id == i) ||
3794 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3797 len = asc_prt_line(cp, leftlen, " %X:%c",
3800 use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ?
3804 len = asc_prt_line(cp, leftlen, "\n");
3807 /* Current number of commands waiting for a device. */
3808 len = asc_prt_line(cp, leftlen, " Command Queue Pending:");
3810 for (i = 0; i <= ASC_MAX_TID; i++) {
3811 if ((chip_scsi_id == i) ||
3812 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3815 len = asc_prt_line(cp, leftlen, " %X:%u", i, v->cur_dvc_qng[i]);
3818 len = asc_prt_line(cp, leftlen, "\n");
3821 /* Current limit on number of commands that can be sent to a device. */
3822 len = asc_prt_line(cp, leftlen, " Command Queue Limit:");
3824 for (i = 0; i <= ASC_MAX_TID; i++) {
3825 if ((chip_scsi_id == i) ||
3826 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3829 len = asc_prt_line(cp, leftlen, " %X:%u", i, v->max_dvc_qng[i]);
3832 len = asc_prt_line(cp, leftlen, "\n");
3835 /* Indicate whether the device has returned queue full status. */
3836 len = asc_prt_line(cp, leftlen, " Command Queue Full:");
3838 for (i = 0; i <= ASC_MAX_TID; i++) {
3839 if ((chip_scsi_id == i) ||
3840 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3843 if (boardp->queue_full & ADV_TID_TO_TIDMASK(i)) {
3844 len = asc_prt_line(cp, leftlen, " %X:Y-%d",
3845 i, boardp->queue_full_cnt[i]);
3847 len = asc_prt_line(cp, leftlen, " %X:N", i);
3851 len = asc_prt_line(cp, leftlen, "\n");
3854 len = asc_prt_line(cp, leftlen, " Synchronous Transfer:");
3856 for (i = 0; i <= ASC_MAX_TID; i++) {
3857 if ((chip_scsi_id == i) ||
3858 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3861 len = asc_prt_line(cp, leftlen, " %X:%c",
3864 sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3868 len = asc_prt_line(cp, leftlen, "\n");
3871 for (i = 0; i <= ASC_MAX_TID; i++) {
3872 uchar syn_period_ix;
3874 if ((chip_scsi_id == i) ||
3875 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3876 ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) {
3880 len = asc_prt_line(cp, leftlen, " %X:", i);
3883 if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0) {
3884 len = asc_prt_line(cp, leftlen, " Asynchronous");
3888 (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index -
3891 len = asc_prt_line(cp, leftlen,
3892 " Transfer Period Factor: %d (%d.%d Mhz),",
3893 v->sdtr_period_tbl[syn_period_ix],
3895 v->sdtr_period_tbl[syn_period_ix],
3902 len = asc_prt_line(cp, leftlen, " REQ/ACK Offset: %d",
3904 sdtr_data[i] & ASC_SYN_MAX_OFFSET);
3908 if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3909 len = asc_prt_line(cp, leftlen, "*\n");
3912 len = asc_prt_line(cp, leftlen, "\n");
3918 len = asc_prt_line(cp, leftlen,
3919 " * = Re-negotiation pending before next command.\n");
3927 * asc_prt_adv_board_info()
3929 * Print dynamic board configuration information.
3931 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3932 * cf. asc_prt_line().
3934 * Return the number of characters copied into 'cp'. No more than
3935 * 'cplen' characters will be copied to 'cp'.
3937 static int asc_prt_adv_board_info(struct Scsi_Host *shost, char *cp, int cplen)
3939 asc_board_t *boardp;
3946 AdvPortAddr iop_base;
3947 ushort chip_scsi_id;
3951 ushort sdtr_able, wdtr_able;
3952 ushort wdtr_done, sdtr_done;
3954 int renegotiate = 0;
3956 boardp = ASC_BOARDP(shost);
3957 v = &boardp->dvc_var.adv_dvc_var;
3958 c = &boardp->dvc_cfg.adv_dvc_cfg;
3959 iop_base = v->iop_base;
3960 chip_scsi_id = v->chip_scsi_id;
3965 len = asc_prt_line(cp, leftlen,
3966 "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3970 len = asc_prt_line(cp, leftlen,
3971 " iop_base 0x%lx, cable_detect: %X, err_code %u\n",
3973 AdvReadWordRegister(iop_base,
3974 IOPW_SCSI_CFG1) & CABLE_DETECT,
3978 len = asc_prt_line(cp, leftlen,
3979 " chip_version %u, lib_version 0x%x, mcode_date 0x%x, mcode_version 0x%x\n",
3980 c->chip_version, c->lib_version, c->mcode_date,
3984 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
3985 len = asc_prt_line(cp, leftlen, " Queuing Enabled:");
3987 for (i = 0; i <= ADV_MAX_TID; i++) {
3988 if ((chip_scsi_id == i) ||
3989 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3993 len = asc_prt_line(cp, leftlen, " %X:%c",
3995 (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3999 len = asc_prt_line(cp, leftlen, "\n");
4002 len = asc_prt_line(cp, leftlen, " Queue Limit:");
4004 for (i = 0; i <= ADV_MAX_TID; i++) {
4005 if ((chip_scsi_id == i) ||
4006 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
4010 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i,
4013 len = asc_prt_line(cp, leftlen, " %X:%d", i, lrambyte);
4016 len = asc_prt_line(cp, leftlen, "\n");
4019 len = asc_prt_line(cp, leftlen, " Command Pending:");
4021 for (i = 0; i <= ADV_MAX_TID; i++) {
4022 if ((chip_scsi_id == i) ||
4023 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
4027 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i,
4030 len = asc_prt_line(cp, leftlen, " %X:%d", i, lrambyte);
4033 len = asc_prt_line(cp, leftlen, "\n");
4036 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4037 len = asc_prt_line(cp, leftlen, " Wide Enabled:");
4039 for (i = 0; i <= ADV_MAX_TID; i++) {
4040 if ((chip_scsi_id == i) ||
4041 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
4045 len = asc_prt_line(cp, leftlen, " %X:%c",
4047 (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
4051 len = asc_prt_line(cp, leftlen, "\n");
4054 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done);
4055 len = asc_prt_line(cp, leftlen, " Transfer Bit Width:");
4057 for (i = 0; i <= ADV_MAX_TID; i++) {
4058 if ((chip_scsi_id == i) ||
4059 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
4063 AdvReadWordLram(iop_base,
4064 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
4067 len = asc_prt_line(cp, leftlen, " %X:%d",
4068 i, (lramword & 0x8000) ? 16 : 8);
4071 if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) &&
4072 (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
4073 len = asc_prt_line(cp, leftlen, "*");
4078 len = asc_prt_line(cp, leftlen, "\n");
4081 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4082 len = asc_prt_line(cp, leftlen, " Synchronous Enabled:");
4084 for (i = 0; i <= ADV_MAX_TID; i++) {
4085 if ((chip_scsi_id == i) ||
4086 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
4090 len = asc_prt_line(cp, leftlen, " %X:%c",
4092 (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
4096 len = asc_prt_line(cp, leftlen, "\n");
4099 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done);
4100 for (i = 0; i <= ADV_MAX_TID; i++) {
4102 AdvReadWordLram(iop_base,
4103 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
4105 lramword &= ~0x8000;
4107 if ((chip_scsi_id == i) ||
4108 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
4109 ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) {
4113 len = asc_prt_line(cp, leftlen, " %X:", i);
4116 if ((lramword & 0x1F) == 0) { /* Check for REQ/ACK Offset 0. */
4117 len = asc_prt_line(cp, leftlen, " Asynchronous");
4121 asc_prt_line(cp, leftlen,
4122 " Transfer Period Factor: ");
4125 if ((lramword & 0x1F00) == 0x1100) { /* 80 Mhz */
4127 asc_prt_line(cp, leftlen, "9 (80.0 Mhz),");
4129 } else if ((lramword & 0x1F00) == 0x1000) { /* 40 Mhz */
4131 asc_prt_line(cp, leftlen, "10 (40.0 Mhz),");
4133 } else { /* 20 Mhz or below. */
4135 period = (((lramword >> 8) * 25) + 50) / 4;
4137 if (period == 0) { /* Should never happen. */
4139 asc_prt_line(cp, leftlen,
4143 len = asc_prt_line(cp, leftlen,
4145 period, 250 / period,
4152 len = asc_prt_line(cp, leftlen, " REQ/ACK Offset: %d",
4157 if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
4158 len = asc_prt_line(cp, leftlen, "*\n");
4161 len = asc_prt_line(cp, leftlen, "\n");
4167 len = asc_prt_line(cp, leftlen,
4168 " * = Re-negotiation pending before next command.\n");
4178 * Copy proc information to a read buffer taking into account the current
4179 * read offset in the file and the remaining space in the read buffer.
4182 asc_proc_copy(off_t advoffset, off_t offset, char *curbuf, int leftlen,
4183 char *cp, int cplen)
4187 ASC_DBG3(2, "asc_proc_copy: offset %d, advoffset %d, cplen %d\n",
4188 (unsigned)offset, (unsigned)advoffset, cplen);
4189 if (offset <= advoffset) {
4190 /* Read offset below current offset, copy everything. */
4191 cnt = min(cplen, leftlen);
4192 ASC_DBG3(2, "asc_proc_copy: curbuf 0x%lx, cp 0x%lx, cnt %d\n",
4193 (ulong)curbuf, (ulong)cp, cnt);
4194 memcpy(curbuf, cp, cnt);
4195 } else if (offset < advoffset + cplen) {
4196 /* Read offset within current range, partial copy. */
4197 cnt = (advoffset + cplen) - offset;
4198 cp = (cp + cplen) - cnt;
4199 cnt = min(cnt, leftlen);
4200 ASC_DBG3(2, "asc_proc_copy: curbuf 0x%lx, cp 0x%lx, cnt %d\n",
4201 (ulong)curbuf, (ulong)cp, cnt);
4202 memcpy(curbuf, cp, cnt);
4207 #ifdef ADVANSYS_STATS
4209 * asc_prt_board_stats()
4211 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
4212 * cf. asc_prt_line().
4214 * Return the number of characters copied into 'cp'. No more than
4215 * 'cplen' characters will be copied to 'cp'.
4217 static int asc_prt_board_stats(struct Scsi_Host *shost, char *cp, int cplen)
4222 struct asc_stats *s;
4223 asc_board_t *boardp;
4228 boardp = ASC_BOARDP(shost);
4229 s = &boardp->asc_stats;
4231 len = asc_prt_line(cp, leftlen,
4232 "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n",
4236 len = asc_prt_line(cp, leftlen,
4237 " queuecommand %lu, reset %lu, biosparam %lu, interrupt %lu\n",
4238 s->queuecommand, s->reset, s->biosparam,
4242 len = asc_prt_line(cp, leftlen,
4243 " callback %lu, done %lu, build_error %lu, build_noreq %lu, build_nosg %lu\n",
4244 s->callback, s->done, s->build_error,
4245 s->adv_build_noreq, s->adv_build_nosg);
4248 len = asc_prt_line(cp, leftlen,
4249 " exe_noerror %lu, exe_busy %lu, exe_error %lu, exe_unknown %lu\n",
4250 s->exe_noerror, s->exe_busy, s->exe_error,
4255 * Display data transfer statistics.
4257 if (s->cont_cnt > 0) {
4258 len = asc_prt_line(cp, leftlen, " cont_cnt %lu, ", s->cont_cnt);
4261 len = asc_prt_line(cp, leftlen, "cont_xfer %lu.%01lu kb ",
4263 ASC_TENTHS(s->cont_xfer, 2));
4266 /* Contiguous transfer average size */
4267 len = asc_prt_line(cp, leftlen, "avg_xfer %lu.%01lu kb\n",
4268 (s->cont_xfer / 2) / s->cont_cnt,
4269 ASC_TENTHS((s->cont_xfer / 2), s->cont_cnt));
4273 if (s->sg_cnt > 0) {
4275 len = asc_prt_line(cp, leftlen, " sg_cnt %lu, sg_elem %lu, ",
4276 s->sg_cnt, s->sg_elem);
4279 len = asc_prt_line(cp, leftlen, "sg_xfer %lu.%01lu kb\n",
4280 s->sg_xfer / 2, ASC_TENTHS(s->sg_xfer, 2));
4283 /* Scatter gather transfer statistics */
4284 len = asc_prt_line(cp, leftlen, " avg_num_elem %lu.%01lu, ",
4285 s->sg_elem / s->sg_cnt,
4286 ASC_TENTHS(s->sg_elem, s->sg_cnt));
4289 len = asc_prt_line(cp, leftlen, "avg_elem_size %lu.%01lu kb, ",
4290 (s->sg_xfer / 2) / s->sg_elem,
4291 ASC_TENTHS((s->sg_xfer / 2), s->sg_elem));
4294 len = asc_prt_line(cp, leftlen, "avg_xfer_size %lu.%01lu kb\n",
4295 (s->sg_xfer / 2) / s->sg_cnt,
4296 ASC_TENTHS((s->sg_xfer / 2), s->sg_cnt));
4301 * Display request queuing statistics.
4303 len = asc_prt_line(cp, leftlen,
4304 " Active and Waiting Request Queues (Time Unit: %d HZ):\n",
4310 #endif /* ADVANSYS_STATS */
4313 * advansys_proc_info() - /proc/scsi/advansys/{0,1,2,3,...}
4315 * *buffer: I/O buffer
4316 * **start: if inout == FALSE pointer into buffer where user read should start
4317 * offset: current offset into a /proc/scsi/advansys/[0...] file
4318 * length: length of buffer
4319 * hostno: Scsi_Host host_no
4320 * inout: TRUE - user is writing; FALSE - user is reading
4322 * Return the number of bytes read from or written to a
4323 * /proc/scsi/advansys/[0...] file.
4325 * Note: This function uses the per board buffer 'prtbuf' which is
4326 * allocated when the board is initialized in advansys_detect(). The
4327 * buffer is ASC_PRTBUF_SIZE bytes. The function asc_proc_copy() is
4328 * used to write to the buffer. The way asc_proc_copy() is written
4329 * if 'prtbuf' is too small it will not be overwritten. Instead the
4330 * user just won't get all the available statistics.
4333 advansys_proc_info(struct Scsi_Host *shost, char *buffer, char **start,
4334 off_t offset, int length, int inout)
4336 asc_board_t *boardp;
4345 ASC_DBG(1, "advansys_proc_info: begin\n");
4348 * User write not supported.
4350 if (inout == TRUE) {
4355 * User read of /proc/scsi/advansys/[0...] file.
4358 boardp = ASC_BOARDP(shost);
4360 /* Copy read data starting at the beginning of the buffer. */
4368 * Get board configuration information.
4370 * advansys_info() returns the board string from its own static buffer.
4372 cp = (char *)advansys_info(shost);
4375 /* Copy board information. */
4376 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4380 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4387 * Display Wide Board BIOS Information.
4389 if (ASC_WIDE_BOARD(boardp)) {
4390 cp = boardp->prtbuf;
4391 cplen = asc_prt_adv_bios(shost, cp, ASC_PRTBUF_SIZE);
4392 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4393 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp,
4398 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4406 * Display driver information for each device attached to the board.
4408 cp = boardp->prtbuf;
4409 cplen = asc_prt_board_devices(shost, cp, ASC_PRTBUF_SIZE);
4410 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4411 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4415 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4422 * Display EEPROM configuration for the board.
4424 cp = boardp->prtbuf;
4425 if (ASC_NARROW_BOARD(boardp)) {
4426 cplen = asc_prt_asc_board_eeprom(shost, cp, ASC_PRTBUF_SIZE);
4428 cplen = asc_prt_adv_board_eeprom(shost, cp, ASC_PRTBUF_SIZE);
4430 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4431 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4435 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4442 * Display driver configuration and information for the board.
4444 cp = boardp->prtbuf;
4445 cplen = asc_prt_driver_conf(shost, cp, ASC_PRTBUF_SIZE);
4446 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4447 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4451 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4457 #ifdef ADVANSYS_STATS
4459 * Display driver statistics for the board.
4461 cp = boardp->prtbuf;
4462 cplen = asc_prt_board_stats(shost, cp, ASC_PRTBUF_SIZE);
4463 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4464 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4468 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4473 #endif /* ADVANSYS_STATS */
4476 * Display Asc Library dynamic configuration information
4479 cp = boardp->prtbuf;
4480 if (ASC_NARROW_BOARD(boardp)) {
4481 cplen = asc_prt_asc_board_info(shost, cp, ASC_PRTBUF_SIZE);
4483 cplen = asc_prt_adv_board_info(shost, cp, ASC_PRTBUF_SIZE);
4485 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4486 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4490 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4496 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4500 #endif /* CONFIG_PROC_FS */
4502 static void asc_scsi_done(struct scsi_cmnd *scp)
4504 struct asc_board *boardp = ASC_BOARDP(scp->device->host);
4507 dma_unmap_sg(boardp->dev,
4508 (struct scatterlist *)scp->request_buffer,
4509 scp->use_sg, scp->sc_data_direction);
4510 else if (scp->request_bufflen)
4511 dma_unmap_single(boardp->dev, scp->SCp.dma_handle,
4512 scp->request_bufflen, scp->sc_data_direction);
4514 ASC_STATS(scp->device->host, done);
4516 scp->scsi_done(scp);
4519 static void AscSetBank(PortAddr iop_base, uchar bank)
4523 val = AscGetChipControl(iop_base) &
4525 (CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET |
4529 } else if (bank == 2) {
4530 val |= CC_DIAG | CC_BANK_ONE;
4532 val &= ~CC_BANK_ONE;
4534 AscSetChipControl(iop_base, val);
4538 static void AscSetChipIH(PortAddr iop_base, ushort ins_code)
4540 AscSetBank(iop_base, 1);
4541 AscWriteChipIH(iop_base, ins_code);
4542 AscSetBank(iop_base, 0);
4546 static int AscStartChip(PortAddr iop_base)
4548 AscSetChipControl(iop_base, 0);
4549 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
4555 static int AscStopChip(PortAddr iop_base)
4560 AscGetChipControl(iop_base) &
4561 (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG));
4562 AscSetChipControl(iop_base, (uchar)(cc_val | CC_HALT));
4563 AscSetChipIH(iop_base, INS_HALT);
4564 AscSetChipIH(iop_base, INS_RFLAG_WTM);
4565 if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) {
4571 static int AscIsChipHalted(PortAddr iop_base)
4573 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
4574 if ((AscGetChipControl(iop_base) & CC_HALT) != 0) {
4581 static int AscResetChipAndScsiBus(ASC_DVC_VAR *asc_dvc)
4586 iop_base = asc_dvc->iop_base;
4587 while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE)
4591 AscStopChip(iop_base);
4592 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT);
4594 AscSetChipIH(iop_base, INS_RFLAG_WTM);
4595 AscSetChipIH(iop_base, INS_HALT);
4596 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT);
4597 AscSetChipControl(iop_base, CC_HALT);
4599 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
4600 AscSetChipStatus(iop_base, 0);
4601 return (AscIsChipHalted(iop_base));
4604 static int AscFindSignature(PortAddr iop_base)
4608 ASC_DBG2(1, "AscFindSignature: AscGetChipSignatureByte(0x%x) 0x%x\n",
4609 iop_base, AscGetChipSignatureByte(iop_base));
4610 if (AscGetChipSignatureByte(iop_base) == (uchar)ASC_1000_ID1B) {
4612 "AscFindSignature: AscGetChipSignatureWord(0x%x) 0x%x\n",
4613 iop_base, AscGetChipSignatureWord(iop_base));
4614 sig_word = AscGetChipSignatureWord(iop_base);
4615 if ((sig_word == (ushort)ASC_1000_ID0W) ||
4616 (sig_word == (ushort)ASC_1000_ID0W_FIX)) {
4623 static void AscEnableInterrupt(PortAddr iop_base)
4627 cfg = AscGetChipCfgLsw(iop_base);
4628 AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON);
4632 static void AscDisableInterrupt(PortAddr iop_base)
4636 cfg = AscGetChipCfgLsw(iop_base);
4637 AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON));
4641 static uchar AscReadLramByte(PortAddr iop_base, ushort addr)
4643 unsigned char byte_data;
4644 unsigned short word_data;
4646 if (isodd_word(addr)) {
4647 AscSetChipLramAddr(iop_base, addr - 1);
4648 word_data = AscGetChipLramData(iop_base);
4649 byte_data = (word_data >> 8) & 0xFF;
4651 AscSetChipLramAddr(iop_base, addr);
4652 word_data = AscGetChipLramData(iop_base);
4653 byte_data = word_data & 0xFF;
4658 static ushort AscReadLramWord(PortAddr iop_base, ushort addr)
4662 AscSetChipLramAddr(iop_base, addr);
4663 word_data = AscGetChipLramData(iop_base);
4667 #if CC_VERY_LONG_SG_LIST
4668 static ASC_DCNT AscReadLramDWord(PortAddr iop_base, ushort addr)
4670 ushort val_low, val_high;
4671 ASC_DCNT dword_data;
4673 AscSetChipLramAddr(iop_base, addr);
4674 val_low = AscGetChipLramData(iop_base);
4675 val_high = AscGetChipLramData(iop_base);
4676 dword_data = ((ASC_DCNT) val_high << 16) | (ASC_DCNT) val_low;
4677 return (dword_data);
4679 #endif /* CC_VERY_LONG_SG_LIST */
4682 AscMemWordSetLram(PortAddr iop_base, ushort s_addr, ushort set_wval, int words)
4686 AscSetChipLramAddr(iop_base, s_addr);
4687 for (i = 0; i < words; i++) {
4688 AscSetChipLramData(iop_base, set_wval);
4692 static void AscWriteLramWord(PortAddr iop_base, ushort addr, ushort word_val)
4694 AscSetChipLramAddr(iop_base, addr);
4695 AscSetChipLramData(iop_base, word_val);
4699 static void AscWriteLramByte(PortAddr iop_base, ushort addr, uchar byte_val)
4703 if (isodd_word(addr)) {
4705 word_data = AscReadLramWord(iop_base, addr);
4706 word_data &= 0x00FF;
4707 word_data |= (((ushort)byte_val << 8) & 0xFF00);
4709 word_data = AscReadLramWord(iop_base, addr);
4710 word_data &= 0xFF00;
4711 word_data |= ((ushort)byte_val & 0x00FF);
4713 AscWriteLramWord(iop_base, addr, word_data);
4718 * Copy 2 bytes to LRAM.
4720 * The source data is assumed to be in little-endian order in memory
4721 * and is maintained in little-endian order when written to LRAM.
4724 AscMemWordCopyPtrToLram(PortAddr iop_base,
4725 ushort s_addr, uchar *s_buffer, int words)
4729 AscSetChipLramAddr(iop_base, s_addr);
4730 for (i = 0; i < 2 * words; i += 2) {
4732 * On a little-endian system the second argument below
4733 * produces a little-endian ushort which is written to
4734 * LRAM in little-endian order. On a big-endian system
4735 * the second argument produces a big-endian ushort which
4736 * is "transparently" byte-swapped by outpw() and written
4737 * in little-endian order to LRAM.
4739 outpw(iop_base + IOP_RAM_DATA,
4740 ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);
4746 * Copy 4 bytes to LRAM.
4748 * The source data is assumed to be in little-endian order in memory
4749 * and is maintained in little-endian order when writen to LRAM.
4752 AscMemDWordCopyPtrToLram(PortAddr iop_base,
4753 ushort s_addr, uchar *s_buffer, int dwords)
4757 AscSetChipLramAddr(iop_base, s_addr);
4758 for (i = 0; i < 4 * dwords; i += 4) {
4759 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]); /* LSW */
4760 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 3] << 8) | s_buffer[i + 2]); /* MSW */
4766 * Copy 2 bytes from LRAM.
4768 * The source data is assumed to be in little-endian order in LRAM
4769 * and is maintained in little-endian order when written to memory.
4772 AscMemWordCopyPtrFromLram(PortAddr iop_base,
4773 ushort s_addr, uchar *d_buffer, int words)
4778 AscSetChipLramAddr(iop_base, s_addr);
4779 for (i = 0; i < 2 * words; i += 2) {
4780 word = inpw(iop_base + IOP_RAM_DATA);
4781 d_buffer[i] = word & 0xff;
4782 d_buffer[i + 1] = (word >> 8) & 0xff;
4787 static ASC_DCNT AscMemSumLramWord(PortAddr iop_base, ushort s_addr, int words)
4793 for (i = 0; i < words; i++, s_addr += 2) {
4794 sum += AscReadLramWord(iop_base, s_addr);
4799 static ushort AscInitLram(ASC_DVC_VAR *asc_dvc)
4806 iop_base = asc_dvc->iop_base;
4808 AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0,
4809 (ushort)(((int)(asc_dvc->max_total_qng + 2 + 1) *
4811 i = ASC_MIN_ACTIVE_QNO;
4812 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
4813 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4815 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4816 (uchar)(asc_dvc->max_total_qng));
4817 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4820 s_addr += ASC_QBLK_SIZE;
4821 for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
4822 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4824 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4826 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4829 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4830 (uchar)ASC_QLINK_END);
4831 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4832 (uchar)(asc_dvc->max_total_qng - 1));
4833 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4834 (uchar)asc_dvc->max_total_qng);
4836 s_addr += ASC_QBLK_SIZE;
4837 for (; i <= (uchar)(asc_dvc->max_total_qng + 3);
4838 i++, s_addr += ASC_QBLK_SIZE) {
4839 AscWriteLramByte(iop_base,
4840 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_FWD), i);
4841 AscWriteLramByte(iop_base,
4842 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_BWD), i);
4843 AscWriteLramByte(iop_base,
4844 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_QNO), i);
4850 AscLoadMicroCode(PortAddr iop_base,
4851 ushort s_addr, uchar *mcode_buf, ushort mcode_size)
4854 ushort mcode_word_size;
4855 ushort mcode_chksum;
4857 /* Write the microcode buffer starting at LRAM address 0. */
4858 mcode_word_size = (ushort)(mcode_size >> 1);
4859 AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size);
4860 AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size);
4862 chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size);
4863 ASC_DBG1(1, "AscLoadMicroCode: chksum 0x%lx\n", (ulong)chksum);
4864 mcode_chksum = (ushort)AscMemSumLramWord(iop_base,
4865 (ushort)ASC_CODE_SEC_BEG,
4866 (ushort)((mcode_size -
4870 ASC_DBG1(1, "AscLoadMicroCode: mcode_chksum 0x%lx\n",
4871 (ulong)mcode_chksum);
4872 AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum);
4873 AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size);
4877 /* Microcode buffer is kept after initialization for error recovery. */
4878 static uchar _asc_mcode_buf[] = {
4879 0x01, 0x03, 0x01, 0x19, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4880 0x00, 0x00, 0x00, 0x00, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F,
4881 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4882 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4883 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4884 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC3, 0x12, 0x0D, 0x05,
4885 0x01, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4886 0xFF, 0x80, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4887 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0xFF,
4888 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00,
4889 0x00, 0x00, 0xE4, 0x88, 0x00, 0x00, 0x00, 0x00, 0x80, 0x73, 0x48, 0x04,
4890 0x36, 0x00, 0x00, 0xA2, 0xC2, 0x00, 0x80, 0x73, 0x03, 0x23, 0x36, 0x40,
4891 0xB6, 0x00, 0x36, 0x00, 0x05, 0xD6, 0x0C, 0xD2, 0x12, 0xDA, 0x00, 0xA2,
4892 0xC2, 0x00, 0x92, 0x80, 0x1E, 0x98, 0x50, 0x00, 0xF5, 0x00, 0x48, 0x98,
4893 0xDF, 0x23, 0x36, 0x60, 0xB6, 0x00, 0x92, 0x80, 0x4F, 0x00, 0xF5, 0x00,
4894 0x48, 0x98, 0xEF, 0x23, 0x36, 0x60, 0xB6, 0x00, 0x92, 0x80, 0x80, 0x62,
4895 0x92, 0x80, 0x00, 0x46, 0x15, 0xEE, 0x13, 0xEA, 0x02, 0x01, 0x09, 0xD8,
4896 0xCD, 0x04, 0x4D, 0x00, 0x00, 0xA3, 0xD6, 0x00, 0xA6, 0x97, 0x7F, 0x23,
4897 0x04, 0x61, 0x84, 0x01, 0xE6, 0x84, 0xD2, 0xC1, 0x80, 0x73, 0xCD, 0x04,
4898 0x4D, 0x00, 0x00, 0xA3, 0xDA, 0x01, 0xA6, 0x97, 0xC6, 0x81, 0xC2, 0x88,
4899 0x80, 0x73, 0x80, 0x77, 0x00, 0x01, 0x01, 0xA1, 0xFE, 0x00, 0x4F, 0x00,
4900 0x84, 0x97, 0x07, 0xA6, 0x08, 0x01, 0x00, 0x33, 0x03, 0x00, 0xC2, 0x88,
4901 0x03, 0x03, 0x01, 0xDE, 0xC2, 0x88, 0xCE, 0x00, 0x69, 0x60, 0xCE, 0x00,
4902 0x02, 0x03, 0x4A, 0x60, 0x00, 0xA2, 0x78, 0x01, 0x80, 0x63, 0x07, 0xA6,
4903 0x24, 0x01, 0x78, 0x81, 0x03, 0x03, 0x80, 0x63, 0xE2, 0x00, 0x07, 0xA6,
4904 0x34, 0x01, 0x00, 0x33, 0x04, 0x00, 0xC2, 0x88, 0x03, 0x07, 0x02, 0x01,
4905 0x04, 0xCA, 0x0D, 0x23, 0x68, 0x98, 0x4D, 0x04, 0x04, 0x85, 0x05, 0xD8,
4906 0x0D, 0x23, 0x68, 0x98, 0xCD, 0x04, 0x15, 0x23, 0xF8, 0x88, 0xFB, 0x23,
4907 0x02, 0x61, 0x82, 0x01, 0x80, 0x63, 0x02, 0x03, 0x06, 0xA3, 0x62, 0x01,
4908 0x00, 0x33, 0x0A, 0x00, 0xC2, 0x88, 0x4E, 0x00, 0x07, 0xA3, 0x6E, 0x01,
4909 0x00, 0x33, 0x0B, 0x00, 0xC2, 0x88, 0xCD, 0x04, 0x36, 0x2D, 0x00, 0x33,
4910 0x1A, 0x00, 0xC2, 0x88, 0x50, 0x04, 0x88, 0x81, 0x06, 0xAB, 0x82, 0x01,
4911 0x88, 0x81, 0x4E, 0x00, 0x07, 0xA3, 0x92, 0x01, 0x50, 0x00, 0x00, 0xA3,
4912 0x3C, 0x01, 0x00, 0x05, 0x7C, 0x81, 0x46, 0x97, 0x02, 0x01, 0x05, 0xC6,
4913 0x04, 0x23, 0xA0, 0x01, 0x15, 0x23, 0xA1, 0x01, 0xBE, 0x81, 0xFD, 0x23,
4914 0x02, 0x61, 0x82, 0x01, 0x0A, 0xDA, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA0,
4915 0xB4, 0x01, 0x80, 0x63, 0xCD, 0x04, 0x36, 0x2D, 0x00, 0x33, 0x1B, 0x00,
4916 0xC2, 0x88, 0x06, 0x23, 0x68, 0x98, 0xCD, 0x04, 0xE6, 0x84, 0x06, 0x01,
4917 0x00, 0xA2, 0xD4, 0x01, 0x57, 0x60, 0x00, 0xA0, 0xDA, 0x01, 0xE6, 0x84,
4918 0x80, 0x23, 0xA0, 0x01, 0xE6, 0x84, 0x80, 0x73, 0x4B, 0x00, 0x06, 0x61,
4919 0x00, 0xA2, 0x00, 0x02, 0x04, 0x01, 0x0C, 0xDE, 0x02, 0x01, 0x03, 0xCC,
4920 0x4F, 0x00, 0x84, 0x97, 0xFC, 0x81, 0x08, 0x23, 0x02, 0x41, 0x82, 0x01,
4921 0x4F, 0x00, 0x62, 0x97, 0x48, 0x04, 0x84, 0x80, 0xF0, 0x97, 0x00, 0x46,
4922 0x56, 0x00, 0x03, 0xC0, 0x01, 0x23, 0xE8, 0x00, 0x81, 0x73, 0x06, 0x29,
4923 0x03, 0x42, 0x06, 0xE2, 0x03, 0xEE, 0x6B, 0xEB, 0x11, 0x23, 0xF8, 0x88,
4924 0x04, 0x98, 0xF0, 0x80, 0x80, 0x73, 0x80, 0x77, 0x07, 0xA4, 0x2A, 0x02,
4925 0x7C, 0x95, 0x06, 0xA6, 0x34, 0x02, 0x03, 0xA6, 0x4C, 0x04, 0x46, 0x82,
4926 0x04, 0x01, 0x03, 0xD8, 0xB4, 0x98, 0x6A, 0x96, 0x46, 0x82, 0xFE, 0x95,
4927 0x80, 0x67, 0x83, 0x03, 0x80, 0x63, 0xB6, 0x2D, 0x02, 0xA6, 0x6C, 0x02,
4928 0x07, 0xA6, 0x5A, 0x02, 0x06, 0xA6, 0x5E, 0x02, 0x03, 0xA6, 0x62, 0x02,
4929 0xC2, 0x88, 0x7C, 0x95, 0x48, 0x82, 0x60, 0x96, 0x48, 0x82, 0x04, 0x23,
4930 0xA0, 0x01, 0x14, 0x23, 0xA1, 0x01, 0x3C, 0x84, 0x04, 0x01, 0x0C, 0xDC,
4931 0xE0, 0x23, 0x25, 0x61, 0xEF, 0x00, 0x14, 0x01, 0x4F, 0x04, 0xA8, 0x01,
4932 0x6F, 0x00, 0xA5, 0x01, 0x03, 0x23, 0xA4, 0x01, 0x06, 0x23, 0x9C, 0x01,
4933 0x24, 0x2B, 0x1C, 0x01, 0x02, 0xA6, 0xAA, 0x02, 0x07, 0xA6, 0x5A, 0x02,
4934 0x06, 0xA6, 0x5E, 0x02, 0x03, 0xA6, 0x20, 0x04, 0x01, 0xA6, 0xB4, 0x02,
4935 0x00, 0xA6, 0xB4, 0x02, 0x00, 0x33, 0x12, 0x00, 0xC2, 0x88, 0x00, 0x0E,
4936 0x80, 0x63, 0x00, 0x43, 0x00, 0xA0, 0x8C, 0x02, 0x4D, 0x04, 0x04, 0x01,
4937 0x0B, 0xDC, 0xE7, 0x23, 0x04, 0x61, 0x84, 0x01, 0x10, 0x31, 0x12, 0x35,
4938 0x14, 0x01, 0xEC, 0x00, 0x6C, 0x38, 0x00, 0x3F, 0x00, 0x00, 0xEA, 0x82,
4939 0x18, 0x23, 0x04, 0x61, 0x18, 0xA0, 0xE2, 0x02, 0x04, 0x01, 0xA2, 0xC8,
4940 0x00, 0x33, 0x1F, 0x00, 0xC2, 0x88, 0x08, 0x31, 0x0A, 0x35, 0x0C, 0x39,
4941 0x0E, 0x3D, 0x7E, 0x98, 0xB6, 0x2D, 0x01, 0xA6, 0x14, 0x03, 0x00, 0xA6,
4942 0x14, 0x03, 0x07, 0xA6, 0x0C, 0x03, 0x06, 0xA6, 0x10, 0x03, 0x03, 0xA6,
4943 0x20, 0x04, 0x02, 0xA6, 0x6C, 0x02, 0x00, 0x33, 0x33, 0x00, 0xC2, 0x88,
4944 0x7C, 0x95, 0xEE, 0x82, 0x60, 0x96, 0xEE, 0x82, 0x82, 0x98, 0x80, 0x42,
4945 0x7E, 0x98, 0x64, 0xE4, 0x04, 0x01, 0x2D, 0xC8, 0x31, 0x05, 0x07, 0x01,
4946 0x00, 0xA2, 0x54, 0x03, 0x00, 0x43, 0x87, 0x01, 0x05, 0x05, 0x86, 0x98,
4947 0x7E, 0x98, 0x00, 0xA6, 0x16, 0x03, 0x07, 0xA6, 0x4C, 0x03, 0x03, 0xA6,
4948 0x3C, 0x04, 0x06, 0xA6, 0x50, 0x03, 0x01, 0xA6, 0x16, 0x03, 0x00, 0x33,
4949 0x25, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0x32, 0x83, 0x60, 0x96, 0x32, 0x83,
4950 0x04, 0x01, 0x10, 0xCE, 0x07, 0xC8, 0x05, 0x05, 0xEB, 0x04, 0x00, 0x33,
4951 0x00, 0x20, 0xC0, 0x20, 0x81, 0x62, 0x72, 0x83, 0x00, 0x01, 0x05, 0x05,
4952 0xFF, 0xA2, 0x7A, 0x03, 0xB1, 0x01, 0x08, 0x23, 0xB2, 0x01, 0x2E, 0x83,
4953 0x05, 0x05, 0x15, 0x01, 0x00, 0xA2, 0x9A, 0x03, 0xEC, 0x00, 0x6E, 0x00,
4954 0x95, 0x01, 0x6C, 0x38, 0x00, 0x3F, 0x00, 0x00, 0x01, 0xA6, 0x96, 0x03,
4955 0x00, 0xA6, 0x96, 0x03, 0x10, 0x84, 0x80, 0x42, 0x7E, 0x98, 0x01, 0xA6,
4956 0xA4, 0x03, 0x00, 0xA6, 0xBC, 0x03, 0x10, 0x84, 0xA8, 0x98, 0x80, 0x42,
4957 0x01, 0xA6, 0xA4, 0x03, 0x07, 0xA6, 0xB2, 0x03, 0xD4, 0x83, 0x7C, 0x95,
4958 0xA8, 0x83, 0x00, 0x33, 0x2F, 0x00, 0xC2, 0x88, 0xA8, 0x98, 0x80, 0x42,
4959 0x00, 0xA6, 0xBC, 0x03, 0x07, 0xA6, 0xCA, 0x03, 0xD4, 0x83, 0x7C, 0x95,
4960 0xC0, 0x83, 0x00, 0x33, 0x26, 0x00, 0xC2, 0x88, 0x38, 0x2B, 0x80, 0x32,
4961 0x80, 0x36, 0x04, 0x23, 0xA0, 0x01, 0x12, 0x23, 0xA1, 0x01, 0x10, 0x84,
4962 0x07, 0xF0, 0x06, 0xA4, 0xF4, 0x03, 0x80, 0x6B, 0x80, 0x67, 0x05, 0x23,
4963 0x83, 0x03, 0x80, 0x63, 0x03, 0xA6, 0x0E, 0x04, 0x07, 0xA6, 0x06, 0x04,
4964 0x06, 0xA6, 0x0A, 0x04, 0x00, 0x33, 0x17, 0x00, 0xC2, 0x88, 0x7C, 0x95,
4965 0xF4, 0x83, 0x60, 0x96, 0xF4, 0x83, 0x20, 0x84, 0x07, 0xF0, 0x06, 0xA4,
4966 0x20, 0x04, 0x80, 0x6B, 0x80, 0x67, 0x05, 0x23, 0x83, 0x03, 0x80, 0x63,
4967 0xB6, 0x2D, 0x03, 0xA6, 0x3C, 0x04, 0x07, 0xA6, 0x34, 0x04, 0x06, 0xA6,
4968 0x38, 0x04, 0x00, 0x33, 0x30, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0x20, 0x84,
4969 0x60, 0x96, 0x20, 0x84, 0x1D, 0x01, 0x06, 0xCC, 0x00, 0x33, 0x00, 0x84,
4970 0xC0, 0x20, 0x00, 0x23, 0xEA, 0x00, 0x81, 0x62, 0xA2, 0x0D, 0x80, 0x63,
4971 0x07, 0xA6, 0x5A, 0x04, 0x00, 0x33, 0x18, 0x00, 0xC2, 0x88, 0x03, 0x03,
4972 0x80, 0x63, 0xA3, 0x01, 0x07, 0xA4, 0x64, 0x04, 0x23, 0x01, 0x00, 0xA2,
4973 0x86, 0x04, 0x0A, 0xA0, 0x76, 0x04, 0xE0, 0x00, 0x00, 0x33, 0x1D, 0x00,
4974 0xC2, 0x88, 0x0B, 0xA0, 0x82, 0x04, 0xE0, 0x00, 0x00, 0x33, 0x1E, 0x00,
4975 0xC2, 0x88, 0x42, 0x23, 0xF8, 0x88, 0x00, 0x23, 0x22, 0xA3, 0xE6, 0x04,
4976 0x08, 0x23, 0x22, 0xA3, 0xA2, 0x04, 0x28, 0x23, 0x22, 0xA3, 0xAE, 0x04,
4977 0x02, 0x23, 0x22, 0xA3, 0xC4, 0x04, 0x42, 0x23, 0xF8, 0x88, 0x4A, 0x00,
4978 0x06, 0x61, 0x00, 0xA0, 0xAE, 0x04, 0x45, 0x23, 0xF8, 0x88, 0x04, 0x98,
4979 0x00, 0xA2, 0xC0, 0x04, 0xB4, 0x98, 0x00, 0x33, 0x00, 0x82, 0xC0, 0x20,
4980 0x81, 0x62, 0xE8, 0x81, 0x47, 0x23, 0xF8, 0x88, 0x04, 0x01, 0x0B, 0xDE,
4981 0x04, 0x98, 0xB4, 0x98, 0x00, 0x33, 0x00, 0x81, 0xC0, 0x20, 0x81, 0x62,
4982 0x14, 0x01, 0x00, 0xA0, 0x00, 0x02, 0x43, 0x23, 0xF8, 0x88, 0x04, 0x23,
4983 0xA0, 0x01, 0x44, 0x23, 0xA1, 0x01, 0x80, 0x73, 0x4D, 0x00, 0x03, 0xA3,
4984 0xF4, 0x04, 0x00, 0x33, 0x27, 0x00, 0xC2, 0x88, 0x04, 0x01, 0x04, 0xDC,
4985 0x02, 0x23, 0xA2, 0x01, 0x04, 0x23, 0xA0, 0x01, 0x04, 0x98, 0x26, 0x95,
4986 0x4B, 0x00, 0xF6, 0x00, 0x4F, 0x04, 0x4F, 0x00, 0x00, 0xA3, 0x22, 0x05,
4987 0x00, 0x05, 0x76, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x1C, 0x05, 0x0A, 0x85,
4988 0x46, 0x97, 0xCD, 0x04, 0x24, 0x85, 0x48, 0x04, 0x84, 0x80, 0x02, 0x01,
4989 0x03, 0xDA, 0x80, 0x23, 0x82, 0x01, 0x34, 0x85, 0x02, 0x23, 0xA0, 0x01,
4990 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x40, 0x05, 0x1D, 0x01, 0x04, 0xD6,
4991 0xFF, 0x23, 0x86, 0x41, 0x4B, 0x60, 0xCB, 0x00, 0xFF, 0x23, 0x80, 0x01,
4992 0x49, 0x00, 0x81, 0x01, 0x04, 0x01, 0x02, 0xC8, 0x30, 0x01, 0x80, 0x01,
4993 0xF7, 0x04, 0x03, 0x01, 0x49, 0x04, 0x80, 0x01, 0xC9, 0x00, 0x00, 0x05,
4994 0x00, 0x01, 0xFF, 0xA0, 0x60, 0x05, 0x77, 0x04, 0x01, 0x23, 0xEA, 0x00,
4995 0x5D, 0x00, 0xFE, 0xC7, 0x00, 0x62, 0x00, 0x23, 0xEA, 0x00, 0x00, 0x63,
4996 0x07, 0xA4, 0xF8, 0x05, 0x03, 0x03, 0x02, 0xA0, 0x8E, 0x05, 0xF4, 0x85,
4997 0x00, 0x33, 0x2D, 0x00, 0xC2, 0x88, 0x04, 0xA0, 0xB8, 0x05, 0x80, 0x63,
4998 0x00, 0x23, 0xDF, 0x00, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA2, 0xA4, 0x05,
4999 0x1D, 0x01, 0x06, 0xD6, 0x02, 0x23, 0x02, 0x41, 0x82, 0x01, 0x50, 0x00,
5000 0x62, 0x97, 0x04, 0x85, 0x04, 0x23, 0x02, 0x41, 0x82, 0x01, 0x04, 0x85,
5001 0x08, 0xA0, 0xBE, 0x05, 0xF4, 0x85, 0x03, 0xA0, 0xC4, 0x05, 0xF4, 0x85,
5002 0x01, 0xA0, 0xCE, 0x05, 0x88, 0x00, 0x80, 0x63, 0xCC, 0x86, 0x07, 0xA0,
5003 0xEE, 0x05, 0x5F, 0x00, 0x00, 0x2B, 0xDF, 0x08, 0x00, 0xA2, 0xE6, 0x05,
5004 0x80, 0x67, 0x80, 0x63, 0x01, 0xA2, 0x7A, 0x06, 0x7C, 0x85, 0x06, 0x23,
5005 0x68, 0x98, 0x48, 0x23, 0xF8, 0x88, 0x07, 0x23, 0x80, 0x00, 0x06, 0x87,
5006 0x80, 0x63, 0x7C, 0x85, 0x00, 0x23, 0xDF, 0x00, 0x00, 0x63, 0x4A, 0x00,
5007 0x06, 0x61, 0x00, 0xA2, 0x36, 0x06, 0x1D, 0x01, 0x16, 0xD4, 0xC0, 0x23,
5008 0x07, 0x41, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6, 0x1C, 0x06, 0x00, 0x33,
5009 0x37, 0x00, 0xC2, 0x88, 0x1D, 0x01, 0x01, 0xD6, 0x20, 0x23, 0x63, 0x60,
5010 0x83, 0x03, 0x80, 0x63, 0x02, 0x23, 0xDF, 0x00, 0x07, 0xA6, 0x7C, 0x05,
5011 0xEF, 0x04, 0x6F, 0x00, 0x00, 0x63, 0x4B, 0x00, 0x06, 0x41, 0xCB, 0x00,
5012 0x52, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x4E, 0x06, 0x1D, 0x01, 0x03, 0xCA,
5013 0xC0, 0x23, 0x07, 0x41, 0x00, 0x63, 0x1D, 0x01, 0x04, 0xCC, 0x00, 0x33,
5014 0x00, 0x83, 0xC0, 0x20, 0x81, 0x62, 0x80, 0x23, 0x07, 0x41, 0x00, 0x63,
5015 0x80, 0x67, 0x08, 0x23, 0x83, 0x03, 0x80, 0x63, 0x00, 0x63, 0x01, 0x23,
5016 0xDF, 0x00, 0x06, 0xA6, 0x84, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x80, 0x67,
5017 0x80, 0x63, 0x00, 0x33, 0x00, 0x40, 0xC0, 0x20, 0x81, 0x62, 0x00, 0x63,
5018 0x00, 0x00, 0xFE, 0x95, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6, 0x94, 0x06,
5019 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x00, 0x01, 0xA0, 0x14, 0x07, 0x00, 0x2B,
5020 0x40, 0x0E, 0x80, 0x63, 0x01, 0x00, 0x06, 0xA6, 0xAA, 0x06, 0x07, 0xA6,
5021 0x7C, 0x05, 0x40, 0x0E, 0x80, 0x63, 0x00, 0x43, 0x00, 0xA0, 0xA2, 0x06,
5022 0x06, 0xA6, 0xBC, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x80, 0x67, 0x40, 0x0E,
5023 0x80, 0x63, 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x23, 0xDF, 0x00, 0x00, 0x63,
5024 0x07, 0xA6, 0xD6, 0x06, 0x00, 0x33, 0x2A, 0x00, 0xC2, 0x88, 0x03, 0x03,
5025 0x80, 0x63, 0x89, 0x00, 0x0A, 0x2B, 0x07, 0xA6, 0xE8, 0x06, 0x00, 0x33,
5026 0x29, 0x00, 0xC2, 0x88, 0x00, 0x43, 0x00, 0xA2, 0xF4, 0x06, 0xC0, 0x0E,
5027 0x80, 0x63, 0xDE, 0x86, 0xC0, 0x0E, 0x00, 0x33, 0x00, 0x80, 0xC0, 0x20,
5028 0x81, 0x62, 0x04, 0x01, 0x02, 0xDA, 0x80, 0x63, 0x7C, 0x85, 0x80, 0x7B,
5029 0x80, 0x63, 0x06, 0xA6, 0x8C, 0x06, 0x00, 0x33, 0x2C, 0x00, 0xC2, 0x88,
5030 0x0C, 0xA2, 0x2E, 0x07, 0xFE, 0x95, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6,
5031 0x2C, 0x07, 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x33, 0x3D, 0x00, 0xC2, 0x88,
5032 0x00, 0x00, 0x80, 0x67, 0x83, 0x03, 0x80, 0x63, 0x0C, 0xA0, 0x44, 0x07,
5033 0x07, 0xA6, 0x7C, 0x05, 0xBF, 0x23, 0x04, 0x61, 0x84, 0x01, 0xE6, 0x84,
5034 0x00, 0x63, 0xF0, 0x04, 0x01, 0x01, 0xF1, 0x00, 0x00, 0x01, 0xF2, 0x00,
5035 0x01, 0x05, 0x80, 0x01, 0x72, 0x04, 0x71, 0x00, 0x81, 0x01, 0x70, 0x04,
5036 0x80, 0x05, 0x81, 0x05, 0x00, 0x63, 0xF0, 0x04, 0xF2, 0x00, 0x72, 0x04,
5037 0x01, 0x01, 0xF1, 0x00, 0x70, 0x00, 0x81, 0x01, 0x70, 0x04, 0x71, 0x00,
5038 0x81, 0x01, 0x72, 0x00, 0x80, 0x01, 0x71, 0x04, 0x70, 0x00, 0x80, 0x01,
5039 0x70, 0x04, 0x00, 0x63, 0xF0, 0x04, 0xF2, 0x00, 0x72, 0x04, 0x00, 0x01,
5040 0xF1, 0x00, 0x70, 0x00, 0x80, 0x01, 0x70, 0x04, 0x71, 0x00, 0x80, 0x01,
5041 0x72, 0x00, 0x81, 0x01, 0x71, 0x04, 0x70, 0x00, 0x81, 0x01, 0x70, 0x04,
5042 0x00, 0x63, 0x00, 0x23, 0xB3, 0x01, 0x83, 0x05, 0xA3, 0x01, 0xA2, 0x01,
5043 0xA1, 0x01, 0x01, 0x23, 0xA0, 0x01, 0x00, 0x01, 0xC8, 0x00, 0x03, 0xA1,
5044 0xC4, 0x07, 0x00, 0x33, 0x07, 0x00, 0xC2, 0x88, 0x80, 0x05, 0x81, 0x05,
5045 0x04, 0x01, 0x11, 0xC8, 0x48, 0x00, 0xB0, 0x01, 0xB1, 0x01, 0x08, 0x23,
5046 0xB2, 0x01, 0x05, 0x01, 0x48, 0x04, 0x00, 0x43, 0x00, 0xA2, 0xE4, 0x07,
5047 0x00, 0x05, 0xDA, 0x87, 0x00, 0x01, 0xC8, 0x00, 0xFF, 0x23, 0x80, 0x01,
5048 0x05, 0x05, 0x00, 0x63, 0xF7, 0x04, 0x1A, 0x09, 0xF6, 0x08, 0x6E, 0x04,
5049 0x00, 0x02, 0x80, 0x43, 0x76, 0x08, 0x80, 0x02, 0x77, 0x04, 0x00, 0x63,
5050 0xF7, 0x04, 0x1A, 0x09, 0xF6, 0x08, 0x6E, 0x04, 0x00, 0x02, 0x00, 0xA0,
5051 0x14, 0x08, 0x16, 0x88, 0x00, 0x43, 0x76, 0x08, 0x80, 0x02, 0x77, 0x04,
5052 0x00, 0x63, 0xF3, 0x04, 0x00, 0x23, 0xF4, 0x00, 0x74, 0x00, 0x80, 0x43,
5053 0xF4, 0x00, 0xCF, 0x40, 0x00, 0xA2, 0x44, 0x08, 0x74, 0x04, 0x02, 0x01,
5054 0xF7, 0xC9, 0xF6, 0xD9, 0x00, 0x01, 0x01, 0xA1, 0x24, 0x08, 0x04, 0x98,
5055 0x26, 0x95, 0x24, 0x88, 0x73, 0x04, 0x00, 0x63, 0xF3, 0x04, 0x75, 0x04,
5056 0x5A, 0x88, 0x02, 0x01, 0x04, 0xD8, 0x46, 0x97, 0x04, 0x98, 0x26, 0x95,
5057 0x4A, 0x88, 0x75, 0x00, 0x00, 0xA3, 0x64, 0x08, 0x00, 0x05, 0x4E, 0x88,
5058 0x73, 0x04, 0x00, 0x63, 0x80, 0x7B, 0x80, 0x63, 0x06, 0xA6, 0x76, 0x08,
5059 0x00, 0x33, 0x3E, 0x00, 0xC2, 0x88, 0x80, 0x67, 0x83, 0x03, 0x80, 0x63,
5060 0x00, 0x63, 0x38, 0x2B, 0x9C, 0x88, 0x38, 0x2B, 0x92, 0x88, 0x32, 0x09,
5061 0x31, 0x05, 0x92, 0x98, 0x05, 0x05, 0xB2, 0x09, 0x00, 0x63, 0x00, 0x32,
5062 0x00, 0x36, 0x00, 0x3A, 0x00, 0x3E, 0x00, 0x63, 0x80, 0x32, 0x80, 0x36,
5063 0x80, 0x3A, 0x80, 0x3E, 0xB4, 0x3D, 0x00, 0x63, 0x38, 0x2B, 0x40, 0x32,
5064 0x40, 0x36, 0x40, 0x3A, 0x40, 0x3E, 0x00, 0x63, 0x5A, 0x20, 0xC9, 0x40,
5065 0x00, 0xA0, 0xB4, 0x08, 0x5D, 0x00, 0xFE, 0xC3, 0x00, 0x63, 0x80, 0x73,
5066 0xE6, 0x20, 0x02, 0x23, 0xE8, 0x00, 0x82, 0x73, 0xFF, 0xFD, 0x80, 0x73,
5067 0x13, 0x23, 0xF8, 0x88, 0x66, 0x20, 0xC0, 0x20, 0x04, 0x23, 0xA0, 0x01,
5068 0xA1, 0x23, 0xA1, 0x01, 0x81, 0x62, 0xE2, 0x88, 0x80, 0x73, 0x80, 0x77,
5069 0x68, 0x00, 0x00, 0xA2, 0x80, 0x00, 0x03, 0xC2, 0xF1, 0xC7, 0x41, 0x23,
5070 0xF8, 0x88, 0x11, 0x23, 0xA1, 0x01, 0x04, 0x23, 0xA0, 0x01, 0xE6, 0x84,
5073 static unsigned short _asc_mcode_size = sizeof(_asc_mcode_buf);
5074 static ADV_DCNT _asc_mcode_chksum = 0x012C453FUL;
5076 /* Microcode buffer is kept after initialization for error recovery. */
5077 static unsigned char _adv_asc3550_buf[] = {
5078 0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0x16, 0x18, 0xe4, 0x00, 0xfc,
5079 0x01, 0x00, 0x48, 0xe4, 0xbe, 0x18, 0x18, 0x80, 0x03, 0xf6, 0x02, 0x00,
5080 0x00, 0xfa, 0xff, 0xff, 0x28, 0x0e, 0x9e, 0xe7, 0xff, 0x00, 0x82, 0xe7,
5081 0x00, 0xea, 0x00, 0xf6, 0x01, 0xe6, 0x09, 0xe7, 0x55, 0xf0, 0x01, 0xf6,
5082 0x01, 0xfa, 0x08, 0x00, 0x03, 0x00, 0x04, 0x00, 0x18, 0xf4, 0x10, 0x00,
5083 0x00, 0xec, 0x85, 0xf0, 0xbc, 0x00, 0xd5, 0xf0, 0x8e, 0x0c, 0x38, 0x54,
5084 0x00, 0xe6, 0x1e, 0xf0, 0x86, 0xf0, 0xb4, 0x00, 0x98, 0x57, 0xd0, 0x01,
5085 0x0c, 0x1c, 0x3e, 0x1c, 0x0c, 0x00, 0xbb, 0x00, 0xaa, 0x18, 0x02, 0x80,
5086 0x32, 0xf0, 0x01, 0xfc, 0x88, 0x0c, 0xc6, 0x12, 0x02, 0x13, 0x18, 0x40,
5087 0x00, 0x57, 0x01, 0xea, 0x3c, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x04, 0x12,
5088 0x3e, 0x57, 0x00, 0x80, 0x03, 0xe6, 0xb6, 0x00, 0xc0, 0x00, 0x01, 0x01,
5089 0x3e, 0x01, 0xda, 0x0f, 0x22, 0x10, 0x08, 0x12, 0x02, 0x4a, 0xb9, 0x54,
5090 0x03, 0x58, 0x1b, 0x80, 0x30, 0xe4, 0x4b, 0xe4, 0x20, 0x00, 0x32, 0x00,
5091 0x3e, 0x00, 0x80, 0x00, 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01,
5092 0x70, 0x01, 0x72, 0x01, 0x74, 0x01, 0x76, 0x01, 0x78, 0x01, 0x62, 0x0a,
5093 0x92, 0x0c, 0x2c, 0x10, 0x2e, 0x10, 0x06, 0x13, 0x4c, 0x1c, 0xbb, 0x55,
5094 0x3c, 0x56, 0x04, 0x80, 0x4a, 0xe4, 0x02, 0xee, 0x5b, 0xf0, 0xb1, 0xf0,
5095 0x03, 0xf7, 0x06, 0xf7, 0x03, 0xfc, 0x0f, 0x00, 0x40, 0x00, 0xbe, 0x00,
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5391 0x05, 0xc6, 0x28, 0x84, 0x05, 0x3f, 0x28, 0x34, 0x5e, 0x02, 0x5b, 0xfe,
5392 0xc0, 0x5d, 0xfe, 0xf8, 0x14, 0xfe, 0x03, 0x17, 0x05, 0x50, 0xb4, 0x0c,
5393 0x50, 0x5e, 0x2b, 0x01, 0x08, 0x26, 0x5c, 0x01, 0xfe, 0xaa, 0x14, 0x02,
5394 0x5c, 0x01, 0x08, 0x25, 0x32, 0x1f, 0x44, 0x30, 0x2e, 0xd6, 0x07, 0x06,
5395 0x21, 0x44, 0x01, 0xfe, 0x8e, 0x13, 0xfe, 0x42, 0x58, 0xfe, 0x82, 0x14,
5396 0xfe, 0xa4, 0x14, 0x87, 0xfe, 0x4a, 0xf4, 0x0b, 0x16, 0x44, 0xfe, 0x4a,
5397 0xf4, 0x06, 0xfe, 0x0c, 0x12, 0x2f, 0x07, 0x9a, 0x85, 0x02, 0x5b, 0x05,
5398 0x3f, 0xb4, 0x0c, 0x3f, 0x5e, 0x2b, 0x01, 0x08, 0x26, 0x5c, 0x01, 0xfe,
5399 0xd8, 0x14, 0x02, 0x5c, 0x13, 0x06, 0x65, 0xfe, 0xca, 0x12, 0x26, 0xfe,
5400 0xe0, 0x12, 0x72, 0xf1, 0x01, 0x08, 0x23, 0x72, 0x03, 0x8f, 0xfe, 0xdc,
5401 0x12, 0x25, 0xfe, 0xdc, 0x12, 0x1f, 0xfe, 0xca, 0x12, 0x5e, 0x2b, 0x01,
5402 0x08, 0xfe, 0xd5, 0x10, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b,
5403 0x1c, 0xfe, 0xff, 0x7f, 0xfe, 0x30, 0x56, 0xfe, 0x00, 0x5c, 0x03, 0x13,
5404 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b, 0x1c, 0x3d, 0xfe, 0x30, 0x56,
5405 0xfe, 0x00, 0x5c, 0x03, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b,
5406 0x03, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b, 0xfe, 0x0b, 0x58,
5407 0x03, 0x0a, 0x50, 0x01, 0x82, 0x0a, 0x3f, 0x01, 0x82, 0x03, 0xfc, 0x1c,
5408 0x10, 0xff, 0x03, 0x00, 0x54, 0xfe, 0x00, 0xf4, 0x19, 0x48, 0xfe, 0x00,
5409 0x7d, 0xfe, 0x01, 0x7d, 0xfe, 0x02, 0x7d, 0xfe, 0x03, 0x7c, 0x63, 0x27,
5410 0x0c, 0x52, 0x18, 0x53, 0xbe, 0x56, 0xbf, 0x57, 0x03, 0xfe, 0x62, 0x08,
5411 0xfe, 0x82, 0x4a, 0xfe, 0xe1, 0x1a, 0xfe, 0x83, 0x5a, 0x74, 0x03, 0x01,
5412 0xfe, 0x14, 0x18, 0xfe, 0x42, 0x48, 0x5f, 0x60, 0x89, 0x01, 0x08, 0x1f,
5413 0xfe, 0xa2, 0x14, 0x30, 0x2e, 0xd8, 0x01, 0x08, 0x1f, 0xfe, 0xa2, 0x14,
5414 0x30, 0x2e, 0xfe, 0xe8, 0x0a, 0xfe, 0xc1, 0x59, 0x05, 0xc6, 0x28, 0xfe,
5415 0xcc, 0x12, 0x49, 0x04, 0x1b, 0xfe, 0xc4, 0x13, 0x23, 0x62, 0x1b, 0xe2,
5416 0x4b, 0xc3, 0x64, 0xfe, 0xe8, 0x13, 0x3b, 0x13, 0x06, 0x17, 0xc3, 0x78,
5417 0xdb, 0xfe, 0x78, 0x10, 0xff, 0x02, 0x83, 0x55, 0xa1, 0xff, 0x02, 0x83,
5418 0x55, 0x62, 0x1a, 0xa4, 0xbb, 0xfe, 0x30, 0x00, 0x8e, 0xe4, 0x17, 0x2c,
5419 0x13, 0x06, 0xfe, 0x56, 0x10, 0x62, 0x0b, 0xe1, 0xbb, 0xfe, 0x64, 0x00,
5420 0x8e, 0xe4, 0x0a, 0xfe, 0x64, 0x00, 0x17, 0x93, 0x13, 0x06, 0xfe, 0x28,
5421 0x10, 0x62, 0x06, 0xfe, 0x60, 0x13, 0xbb, 0xfe, 0xc8, 0x00, 0x8e, 0xe4,
5422 0x0a, 0xfe, 0xc8, 0x00, 0x17, 0x4d, 0x13, 0x06, 0x83, 0xbb, 0xfe, 0x90,
5423 0x01, 0xba, 0xfe, 0x4e, 0x14, 0x89, 0xfe, 0x12, 0x10, 0xfe, 0x43, 0xf4,
5424 0x94, 0xfe, 0x56, 0xf0, 0xfe, 0x60, 0x14, 0xfe, 0x04, 0xf4, 0x6c, 0xfe,
5425 0x43, 0xf4, 0x93, 0xfe, 0xf3, 0x10, 0xf9, 0x01, 0xfe, 0x22, 0x13, 0x1c,
5426 0x3d, 0xfe, 0x10, 0x13, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4, 0x69, 0xba,
5427 0xfe, 0x9c, 0x14, 0xb7, 0x69, 0xfe, 0x1c, 0x10, 0xfe, 0x00, 0x17, 0xfe,
5428 0x4d, 0xe4, 0x19, 0xba, 0xfe, 0x9c, 0x14, 0xb7, 0x19, 0x83, 0x60, 0x23,
5429 0xfe, 0x4d, 0xf4, 0x00, 0xdf, 0x89, 0x13, 0x06, 0xfe, 0xb4, 0x56, 0xfe,
5430 0xc3, 0x58, 0x03, 0x60, 0x13, 0x0b, 0x03, 0x15, 0x06, 0x01, 0x08, 0x26,
5431 0xe5, 0x15, 0x0b, 0x01, 0x08, 0x26, 0xe5, 0x15, 0x1a, 0x01, 0x08, 0x26,
5432 0xe5, 0x72, 0xfe, 0x89, 0x49, 0x01, 0x08, 0x03, 0x15, 0x06, 0x01, 0x08,
5433 0x26, 0xa6, 0x15, 0x1a, 0x01, 0x08, 0x26, 0xa6, 0x15, 0x06, 0x01, 0x08,
5434 0x26, 0xa6, 0xfe, 0x89, 0x49, 0x01, 0x08, 0x26, 0xa6, 0x72, 0xfe, 0x89,
5435 0x4a, 0x01, 0x08, 0x03, 0x60, 0x03, 0x1e, 0xcc, 0x07, 0x06, 0xfe, 0x44,
5436 0x13, 0xad, 0x12, 0xcc, 0xfe, 0x49, 0xf4, 0x00, 0x3b, 0x72, 0x9f, 0x5e,
5437 0xfe, 0x01, 0xec, 0xfe, 0x27, 0x01, 0xf1, 0x01, 0x08, 0x2f, 0x07, 0xfe,
5438 0xe3, 0x00, 0xfe, 0x20, 0x13, 0x1f, 0xfe, 0x5a, 0x15, 0x23, 0x12, 0xcd,
5439 0x01, 0x43, 0x1e, 0xcd, 0x07, 0x06, 0x45, 0x09, 0x4a, 0x06, 0x35, 0x03,
5440 0x0a, 0x42, 0x01, 0x0e, 0xed, 0x88, 0x07, 0x10, 0xa4, 0x0a, 0x80, 0x01,
5441 0x0e, 0x88, 0x0a, 0x51, 0x01, 0x9e, 0x03, 0x0a, 0x80, 0x01, 0x0e, 0x88,
5442 0xfe, 0x80, 0xe7, 0x10, 0x07, 0x10, 0x84, 0xfe, 0x45, 0x58, 0x01, 0xe3,
5443 0x88, 0x03, 0x0a, 0x42, 0x01, 0x0e, 0x88, 0x0a, 0x51, 0x01, 0x9e, 0x03,
5444 0x0a, 0x42, 0x01, 0x0e, 0xfe, 0x80, 0x80, 0xf2, 0xfe, 0x49, 0xe4, 0x10,
5445 0xa4, 0x0a, 0x80, 0x01, 0x0e, 0xf2, 0x0a, 0x51, 0x01, 0x82, 0x03, 0x17,
5446 0x10, 0x71, 0x66, 0xfe, 0x60, 0x01, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde,
5447 0xfe, 0x24, 0x1c, 0xfe, 0x1d, 0xf7, 0x1d, 0x90, 0xfe, 0xf6, 0x15, 0x01,
5448 0xfe, 0xfc, 0x16, 0xe0, 0x91, 0x1d, 0x66, 0xfe, 0x2c, 0x01, 0xfe, 0x2f,
5449 0x19, 0x03, 0xae, 0x21, 0xfe, 0xe6, 0x15, 0xfe, 0xda, 0x10, 0x17, 0x10,
5450 0x71, 0x05, 0xfe, 0x64, 0x01, 0xfe, 0x00, 0xf4, 0x19, 0xfe, 0x18, 0x58,
5451 0x05, 0xfe, 0x66, 0x01, 0xfe, 0x19, 0x58, 0x91, 0x19, 0xfe, 0x3c, 0x90,
5452 0xfe, 0x30, 0xf4, 0x06, 0xfe, 0x3c, 0x50, 0x66, 0xfe, 0x38, 0x00, 0xfe,
5453 0x0f, 0x79, 0xfe, 0x1c, 0xf7, 0x19, 0x90, 0xfe, 0x40, 0x16, 0xfe, 0xb6,
5454 0x14, 0x34, 0x03, 0xae, 0x21, 0xfe, 0x18, 0x16, 0xfe, 0x9c, 0x10, 0x17,
5455 0x10, 0x71, 0xfe, 0x83, 0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe,
5456 0x1d, 0xf7, 0x38, 0x90, 0xfe, 0x62, 0x16, 0xfe, 0x94, 0x14, 0xfe, 0x10,
5457 0x13, 0x91, 0x38, 0x66, 0x1b, 0xfe, 0xaf, 0x19, 0xfe, 0x98, 0xe7, 0x00,
5458 0x03, 0xae, 0x21, 0xfe, 0x56, 0x16, 0xfe, 0x6c, 0x10, 0x17, 0x10, 0x71,
5459 0xfe, 0x30, 0xbc, 0xfe, 0xb2, 0xbc, 0x91, 0xc5, 0x66, 0x1b, 0xfe, 0x0f,
5460 0x79, 0xfe, 0x1c, 0xf7, 0xc5, 0x90, 0xfe, 0x9a, 0x16, 0xfe, 0x5c, 0x14,
5461 0x34, 0x03, 0xae, 0x21, 0xfe, 0x86, 0x16, 0xfe, 0x42, 0x10, 0xfe, 0x02,
5462 0xf6, 0x10, 0x71, 0xfe, 0x18, 0xfe, 0x54, 0xfe, 0x19, 0xfe, 0x55, 0xfc,
5463 0xfe, 0x1d, 0xf7, 0x4f, 0x90, 0xfe, 0xc0, 0x16, 0xfe, 0x36, 0x14, 0xfe,
5464 0x1c, 0x13, 0x91, 0x4f, 0x47, 0xfe, 0x83, 0x58, 0xfe, 0xaf, 0x19, 0xfe,
5465 0x80, 0xe7, 0x10, 0xfe, 0x81, 0xe7, 0x10, 0x11, 0xfe, 0xdd, 0x00, 0x63,
5466 0x27, 0x03, 0x63, 0x27, 0xfe, 0x12, 0x45, 0x21, 0xfe, 0xb0, 0x16, 0x14,
5467 0x06, 0x37, 0x95, 0xa9, 0x02, 0x29, 0xfe, 0x39, 0xf0, 0xfe, 0x04, 0x17,
5468 0x23, 0x03, 0xfe, 0x7e, 0x18, 0x1c, 0x1a, 0x5d, 0x13, 0x0d, 0x03, 0x71,
5469 0x05, 0xcb, 0x1c, 0x06, 0xfe, 0xef, 0x12, 0xfe, 0xe1, 0x10, 0x78, 0x2c,
5470 0x46, 0x2f, 0x07, 0x2d, 0xfe, 0x3c, 0x13, 0xfe, 0x82, 0x14, 0xfe, 0x42,
5471 0x13, 0x3c, 0x8a, 0x0a, 0x42, 0x01, 0x0e, 0xb0, 0xfe, 0x3e, 0x12, 0xf0,
5472 0xfe, 0x45, 0x48, 0x01, 0xe3, 0xfe, 0x00, 0xcc, 0xb0, 0xfe, 0xf3, 0x13,
5473 0x3d, 0x75, 0x07, 0x10, 0xa3, 0x0a, 0x80, 0x01, 0x0e, 0xf2, 0x01, 0x6f,
5474 0xfe, 0x16, 0x10, 0x07, 0x7e, 0x85, 0xfe, 0x40, 0x14, 0xfe, 0x24, 0x12,
5475 0xf6, 0xfe, 0xd6, 0xf0, 0xfe, 0x24, 0x17, 0x17, 0x0b, 0x03, 0xfe, 0x9c,
5476 0xe7, 0x0b, 0x0f, 0xfe, 0x15, 0x00, 0x59, 0x76, 0x27, 0x01, 0xda, 0x17,
5477 0x06, 0x03, 0x3c, 0x8a, 0x09, 0x4a, 0x1d, 0x35, 0x11, 0x2d, 0x01, 0x6f,
5478 0x17, 0x06, 0x03, 0xfe, 0x38, 0x90, 0xfe, 0xba, 0x90, 0x79, 0xc7, 0x68,
5479 0xc8, 0xfe, 0x48, 0x55, 0x34, 0xfe, 0xc9, 0x55, 0x03, 0x1e, 0x98, 0x73,
5480 0x12, 0x98, 0x03, 0x0a, 0x99, 0x01, 0x0e, 0xf0, 0x0a, 0x40, 0x01, 0x0e,
5481 0xfe, 0x49, 0x44, 0x16, 0xfe, 0xf0, 0x17, 0x73, 0x75, 0x03, 0x0a, 0x42,
5482 0x01, 0x0e, 0x07, 0x10, 0x45, 0x0a, 0x51, 0x01, 0x9e, 0x0a, 0x40, 0x01,
5483 0x0e, 0x73, 0x75, 0x03, 0xfe, 0x4e, 0xe4, 0x1a, 0x64, 0xfe, 0x24, 0x18,
5484 0x05, 0xfe, 0x90, 0x00, 0xfe, 0x3a, 0x45, 0x5b, 0xfe, 0x4e, 0xe4, 0xc2,
5485 0x64, 0xfe, 0x36, 0x18, 0x05, 0xfe, 0x92, 0x00, 0xfe, 0x02, 0xe6, 0x1b,
5486 0xdc, 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x64, 0xfe, 0x48, 0x18, 0x05,
5487 0xfe, 0x94, 0x00, 0xfe, 0x02, 0xe6, 0x19, 0xfe, 0x08, 0x10, 0x05, 0xfe,
5488 0x96, 0x00, 0xfe, 0x02, 0xe6, 0x2c, 0xfe, 0x4e, 0x45, 0xfe, 0x0c, 0x12,
5489 0xaf, 0xff, 0x04, 0x68, 0x54, 0xde, 0x1c, 0x69, 0x03, 0x07, 0x7a, 0xfe,
5490 0x5a, 0xf0, 0xfe, 0x74, 0x18, 0x24, 0xfe, 0x09, 0x00, 0xfe, 0x34, 0x10,
5491 0x07, 0x1b, 0xfe, 0x5a, 0xf0, 0xfe, 0x82, 0x18, 0x24, 0xc3, 0xfe, 0x26,
5492 0x10, 0x07, 0x1a, 0x5d, 0x24, 0x2c, 0xdc, 0x07, 0x0b, 0x5d, 0x24, 0x93,
5493 0xfe, 0x0e, 0x10, 0x07, 0x06, 0x5d, 0x24, 0x4d, 0x9f, 0xad, 0x03, 0x14,
5494 0xfe, 0x09, 0x00, 0x01, 0x33, 0xfe, 0x04, 0xfe, 0x7d, 0x05, 0x7f, 0xf9,
5495 0x03, 0x25, 0xfe, 0xca, 0x18, 0xfe, 0x14, 0xf0, 0x08, 0x65, 0xfe, 0xc6,
5496 0x18, 0x03, 0xff, 0x1a, 0x00, 0x00,
5499 static unsigned short _adv_asc3550_size = sizeof(_adv_asc3550_buf); /* 0x13AD */
5500 static ADV_DCNT _adv_asc3550_chksum = 0x04D52DDDUL; /* Expanded little-endian checksum. */
5502 /* Microcode buffer is kept after initialization for error recovery. */
5503 static unsigned char _adv_asc38C0800_buf[] = {
5504 0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0xfc, 0x00, 0x16, 0x18, 0xe4,
5505 0x01, 0x00, 0x48, 0xe4, 0x18, 0x80, 0x03, 0xf6, 0x02, 0x00, 0xce, 0x19,
5506 0x00, 0xfa, 0xff, 0xff, 0x1c, 0x0f, 0x00, 0xf6, 0x9e, 0xe7, 0xff, 0x00,
5507 0x82, 0xe7, 0x00, 0xea, 0x01, 0xfa, 0x01, 0xe6, 0x09, 0xe7, 0x55, 0xf0,
5508 0x01, 0xf6, 0x03, 0x00, 0x04, 0x00, 0x10, 0x00, 0x1e, 0xf0, 0x85, 0xf0,
5509 0x18, 0xf4, 0x08, 0x00, 0xbc, 0x00, 0x38, 0x54, 0x00, 0xec, 0xd5, 0xf0,
5510 0x82, 0x0d, 0x00, 0xe6, 0x86, 0xf0, 0xb1, 0xf0, 0x98, 0x57, 0x01, 0xfc,
5511 0xb4, 0x00, 0xd4, 0x01, 0x0c, 0x1c, 0x3e, 0x1c, 0x3c, 0x00, 0xbb, 0x00,
5512 0x00, 0x10, 0xba, 0x19, 0x02, 0x80, 0x32, 0xf0, 0x7c, 0x0d, 0x02, 0x13,
5513 0xba, 0x13, 0x18, 0x40, 0x00, 0x57, 0x01, 0xea, 0x02, 0xfc, 0x03, 0xfc,
5514 0x3e, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x74, 0x01, 0x76, 0x01, 0xb9, 0x54,
5515 0x3e, 0x57, 0x00, 0x80, 0x03, 0xe6, 0xb6, 0x00, 0xc0, 0x00, 0x01, 0x01,
5516 0x3e, 0x01, 0x7a, 0x01, 0xca, 0x08, 0xce, 0x10, 0x16, 0x11, 0x04, 0x12,
5517 0x08, 0x12, 0x02, 0x4a, 0xbb, 0x55, 0x3c, 0x56, 0x03, 0x58, 0x1b, 0x80,
5518 0x30, 0xe4, 0x4b, 0xe4, 0x5d, 0xf0, 0x02, 0xfa, 0x20, 0x00, 0x32, 0x00,
5519 0x40, 0x00, 0x80, 0x00, 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01,
5520 0x70, 0x01, 0x72, 0x01, 0x78, 0x01, 0x7c, 0x01, 0x62, 0x0a, 0x86, 0x0d,
5521 0x06, 0x13, 0x4c, 0x1c, 0x04, 0x80, 0x4a, 0xe4, 0x02, 0xee, 0x5b, 0xf0,
5522 0x03, 0xf7, 0x0c, 0x00, 0x0f, 0x00, 0x47, 0x00, 0xbe, 0x00, 0x00, 0x01,
5523 0x20, 0x11, 0x5c, 0x16, 0x32, 0x1c, 0x38, 0x1c, 0x4e, 0x1c, 0x10, 0x44,
5524 0x00, 0x4c, 0x04, 0xea, 0x5c, 0xf0, 0xa7, 0xf0, 0x04, 0xf6, 0x03, 0xfa,
5525 0x05, 0x00, 0x34, 0x00, 0x36, 0x00, 0x98, 0x00, 0xcc, 0x00, 0x20, 0x01,
5526 0x4e, 0x01, 0x4a, 0x0b, 0x42, 0x0c, 0x12, 0x0f, 0x0c, 0x10, 0x22, 0x11,
5527 0x0a, 0x12, 0x04, 0x13, 0x30, 0x1c, 0x02, 0x48, 0x00, 0x4e, 0x42, 0x54,
5528 0x44, 0x55, 0xbd, 0x56, 0x06, 0x83, 0x00, 0xdc, 0x05, 0xf0, 0x09, 0xf0,
5529 0x59, 0xf0, 0xb8, 0xf0, 0x4b, 0xf4, 0x06, 0xf7, 0x0e, 0xf7, 0x04, 0xfc,
5530 0x05, 0xfc, 0x06, 0x00, 0x19, 0x00, 0x33, 0x00, 0x9b, 0x00, 0xa4, 0x00,
5531 0xb5, 0x00, 0xba, 0x00, 0xd0, 0x00, 0xe1, 0x00, 0xe7, 0x00, 0xe2, 0x03,
5532 0x08, 0x0f, 0x02, 0x10, 0x04, 0x10, 0x0a, 0x10, 0x0a, 0x13, 0x0c, 0x13,
5533 0x12, 0x13, 0x24, 0x14, 0x34, 0x14, 0x04, 0x16, 0x08, 0x16, 0xa4, 0x17,
5534 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c, 0x08, 0x44, 0x38, 0x44, 0x91, 0x44,
5535 0x0a, 0x45, 0x48, 0x46, 0x01, 0x48, 0x68, 0x54, 0x3a, 0x55, 0x83, 0x55,
5536 0xe5, 0x55, 0xb0, 0x57, 0x01, 0x58, 0x83, 0x59, 0x05, 0xe6, 0x0b, 0xf0,
5537 0x0c, 0xf0, 0x04, 0xf8, 0x05, 0xf8, 0x07, 0x00, 0x0a, 0x00, 0x1c, 0x00,
5538 0x1e, 0x00, 0x9e, 0x00, 0xa8, 0x00, 0xaa, 0x00, 0xb9, 0x00, 0xe0, 0x00,
5539 0x22, 0x01, 0x26, 0x01, 0x79, 0x01, 0x7e, 0x01, 0xc4, 0x01, 0xc6, 0x01,
5540 0x80, 0x02, 0x5e, 0x03, 0xee, 0x04, 0x9a, 0x06, 0xf8, 0x07, 0x62, 0x08,
5541 0x68, 0x08, 0x69, 0x08, 0xd6, 0x08, 0xe9, 0x09, 0xfa, 0x0b, 0x2e, 0x0f,
5542 0x12, 0x10, 0x1a, 0x10, 0xed, 0x10, 0xf1, 0x10, 0x2a, 0x11, 0x06, 0x12,
5543 0x0c, 0x12, 0x3e, 0x12, 0x10, 0x13, 0x16, 0x13, 0x1e, 0x13, 0x46, 0x14,
5544 0x76, 0x14, 0x82, 0x14, 0x36, 0x15, 0xca, 0x15, 0x6b, 0x18, 0xbe, 0x18,
5545 0xca, 0x18, 0xe6, 0x19, 0x12, 0x1c, 0x46, 0x1c, 0x9c, 0x32, 0x00, 0x40,
5546 0x0e, 0x47, 0xfe, 0x9c, 0xf0, 0x2b, 0x02, 0xfe, 0xac, 0x0d, 0xff, 0x10,
5547 0x00, 0x00, 0xd7, 0xfe, 0xe8, 0x19, 0x00, 0xd6, 0xfe, 0x84, 0x01, 0xff,
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5843 0x31, 0xdf, 0x07, 0x06, 0x23, 0x4c, 0x01, 0xf1, 0xfe, 0x42, 0x58, 0xf1,
5844 0xfe, 0xa4, 0x14, 0x8c, 0xfe, 0x4a, 0xf4, 0x0a, 0x17, 0x4c, 0xfe, 0x4a,
5845 0xf4, 0x06, 0xea, 0x32, 0x07, 0xa5, 0x8b, 0x02, 0x72, 0x03, 0x45, 0xc1,
5846 0x0c, 0x45, 0x67, 0x2d, 0x01, 0x0b, 0x26, 0x89, 0x01, 0xfe, 0xcc, 0x15,
5847 0x02, 0x89, 0x0f, 0x06, 0x27, 0xfe, 0xbe, 0x13, 0x26, 0xfe, 0xd4, 0x13,
5848 0x76, 0xfe, 0x89, 0x48, 0x01, 0x0b, 0x21, 0x76, 0x04, 0x7b, 0xfe, 0xd0,
5849 0x13, 0x1c, 0xfe, 0xd0, 0x13, 0x1d, 0xfe, 0xbe, 0x13, 0x67, 0x2d, 0x01,
5850 0x0b, 0xfe, 0xd5, 0x10, 0x0f, 0x71, 0xff, 0x02, 0x00, 0x57, 0x52, 0x93,
5851 0x1e, 0xfe, 0xff, 0x7f, 0xfe, 0x30, 0x56, 0xfe, 0x00, 0x5c, 0x04, 0x0f,
5852 0x71, 0xff, 0x02, 0x00, 0x57, 0x52, 0x93, 0x1e, 0x43, 0xfe, 0x30, 0x56,
5853 0xfe, 0x00, 0x5c, 0x04, 0x0f, 0x71, 0xff, 0x02, 0x00, 0x57, 0x52, 0x93,
5854 0x04, 0x0f, 0x71, 0xff, 0x02, 0x00, 0x57, 0x52, 0x93, 0xfe, 0x0b, 0x58,
5855 0x04, 0x09, 0x5c, 0x01, 0x87, 0x09, 0x45, 0x01, 0x87, 0x04, 0xfe, 0x03,
5856 0xa1, 0x1e, 0x11, 0xff, 0x03, 0x00, 0x54, 0xfe, 0x00, 0xf4, 0x1f, 0x52,
5857 0xfe, 0x00, 0x7d, 0xfe, 0x01, 0x7d, 0xfe, 0x02, 0x7d, 0xfe, 0x03, 0x7c,
5858 0x6a, 0x2a, 0x0c, 0x5e, 0x14, 0x5f, 0x57, 0x3f, 0x7d, 0x40, 0x04, 0xdd,
5859 0xfe, 0x82, 0x4a, 0xfe, 0xe1, 0x1a, 0xfe, 0x83, 0x5a, 0x8d, 0x04, 0x01,
5860 0xfe, 0x0c, 0x19, 0xfe, 0x42, 0x48, 0x50, 0x51, 0x91, 0x01, 0x0b, 0x1d,
5861 0xfe, 0x96, 0x15, 0x33, 0x31, 0xe1, 0x01, 0x0b, 0x1d, 0xfe, 0x96, 0x15,
5862 0x33, 0x31, 0xfe, 0xe8, 0x0a, 0xfe, 0xc1, 0x59, 0x03, 0xcd, 0x28, 0xfe,
5863 0xcc, 0x12, 0x53, 0x05, 0x1a, 0xfe, 0xc4, 0x13, 0x21, 0x69, 0x1a, 0xee,
5864 0x55, 0xca, 0x6b, 0xfe, 0xdc, 0x14, 0x4d, 0x0f, 0x06, 0x18, 0xca, 0x7c,
5865 0x30, 0xfe, 0x78, 0x10, 0xff, 0x02, 0x83, 0x55, 0xab, 0xff, 0x02, 0x83,
5866 0x55, 0x69, 0x19, 0xae, 0x98, 0xfe, 0x30, 0x00, 0x96, 0xf2, 0x18, 0x6d,
5867 0x0f, 0x06, 0xfe, 0x56, 0x10, 0x69, 0x0a, 0xed, 0x98, 0xfe, 0x64, 0x00,
5868 0x96, 0xf2, 0x09, 0xfe, 0x64, 0x00, 0x18, 0x9e, 0x0f, 0x06, 0xfe, 0x28,
5869 0x10, 0x69, 0x06, 0xfe, 0x60, 0x13, 0x98, 0xfe, 0xc8, 0x00, 0x96, 0xf2,
5870 0x09, 0xfe, 0xc8, 0x00, 0x18, 0x59, 0x0f, 0x06, 0x88, 0x98, 0xfe, 0x90,
5871 0x01, 0x7a, 0xfe, 0x42, 0x15, 0x91, 0xe4, 0xfe, 0x43, 0xf4, 0x9f, 0xfe,
5872 0x56, 0xf0, 0xfe, 0x54, 0x15, 0xfe, 0x04, 0xf4, 0x71, 0xfe, 0x43, 0xf4,
5873 0x9e, 0xfe, 0xf3, 0x10, 0xfe, 0x40, 0x5c, 0x01, 0xfe, 0x16, 0x14, 0x1e,
5874 0x43, 0xec, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4, 0x6e, 0x7a, 0xfe, 0x90,
5875 0x15, 0xc4, 0x6e, 0xfe, 0x1c, 0x10, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4,
5876 0xcc, 0x7a, 0xfe, 0x90, 0x15, 0xc4, 0xcc, 0x88, 0x51, 0x21, 0xfe, 0x4d,
5877 0xf4, 0x00, 0xe9, 0x91, 0x0f, 0x06, 0xfe, 0xb4, 0x56, 0xfe, 0xc3, 0x58,
5878 0x04, 0x51, 0x0f, 0x0a, 0x04, 0x16, 0x06, 0x01, 0x0b, 0x26, 0xf3, 0x16,
5879 0x0a, 0x01, 0x0b, 0x26, 0xf3, 0x16, 0x19, 0x01, 0x0b, 0x26, 0xf3, 0x76,
5880 0xfe, 0x89, 0x49, 0x01, 0x0b, 0x04, 0x16, 0x06, 0x01, 0x0b, 0x26, 0xb1,
5881 0x16, 0x19, 0x01, 0x0b, 0x26, 0xb1, 0x16, 0x06, 0x01, 0x0b, 0x26, 0xb1,
5882 0xfe, 0x89, 0x49, 0x01, 0x0b, 0x26, 0xb1, 0x76, 0xfe, 0x89, 0x4a, 0x01,
5883 0x0b, 0x04, 0x51, 0x04, 0x22, 0xd3, 0x07, 0x06, 0xfe, 0x48, 0x13, 0xb8,
5884 0x13, 0xd3, 0xfe, 0x49, 0xf4, 0x00, 0x4d, 0x76, 0xa9, 0x67, 0xfe, 0x01,
5885 0xec, 0xfe, 0x27, 0x01, 0xfe, 0x89, 0x48, 0xff, 0x02, 0x00, 0x10, 0x27,
5886 0xfe, 0x2e, 0x16, 0x32, 0x07, 0xfe, 0xe3, 0x00, 0xfe, 0x20, 0x13, 0x1d,
5887 0xfe, 0x52, 0x16, 0x21, 0x13, 0xd4, 0x01, 0x4b, 0x22, 0xd4, 0x07, 0x06,
5888 0x4e, 0x08, 0x54, 0x06, 0x37, 0x04, 0x09, 0x48, 0x01, 0x0e, 0xfb, 0x8e,
5889 0x07, 0x11, 0xae, 0x09, 0x84, 0x01, 0x0e, 0x8e, 0x09, 0x5d, 0x01, 0xa8,
5890 0x04, 0x09, 0x84, 0x01, 0x0e, 0x8e, 0xfe, 0x80, 0xe7, 0x11, 0x07, 0x11,
5891 0x8a, 0xfe, 0x45, 0x58, 0x01, 0xf0, 0x8e, 0x04, 0x09, 0x48, 0x01, 0x0e,
5892 0x8e, 0x09, 0x5d, 0x01, 0xa8, 0x04, 0x09, 0x48, 0x01, 0x0e, 0xfe, 0x80,
5893 0x80, 0xfe, 0x80, 0x4c, 0xfe, 0x49, 0xe4, 0x11, 0xae, 0x09, 0x84, 0x01,
5894 0x0e, 0xfe, 0x80, 0x4c, 0x09, 0x5d, 0x01, 0x87, 0x04, 0x18, 0x11, 0x75,
5895 0x6c, 0xfe, 0x60, 0x01, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x24,
5896 0x1c, 0xfe, 0x1d, 0xf7, 0x1b, 0x97, 0xfe, 0xee, 0x16, 0x01, 0xfe, 0xf4,
5897 0x17, 0xad, 0x9a, 0x1b, 0x6c, 0xfe, 0x2c, 0x01, 0xfe, 0x2f, 0x19, 0x04,
5898 0xb9, 0x23, 0xfe, 0xde, 0x16, 0xfe, 0xda, 0x10, 0x18, 0x11, 0x75, 0x03,
5899 0xfe, 0x64, 0x01, 0xfe, 0x00, 0xf4, 0x1f, 0xfe, 0x18, 0x58, 0x03, 0xfe,
5900 0x66, 0x01, 0xfe, 0x19, 0x58, 0x9a, 0x1f, 0xfe, 0x3c, 0x90, 0xfe, 0x30,
5901 0xf4, 0x06, 0xfe, 0x3c, 0x50, 0x6c, 0xfe, 0x38, 0x00, 0xfe, 0x0f, 0x79,
5902 0xfe, 0x1c, 0xf7, 0x1f, 0x97, 0xfe, 0x38, 0x17, 0xfe, 0xb6, 0x14, 0x35,
5903 0x04, 0xb9, 0x23, 0xfe, 0x10, 0x17, 0xfe, 0x9c, 0x10, 0x18, 0x11, 0x75,
5904 0xfe, 0x83, 0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x1d, 0xf7,
5905 0x2e, 0x97, 0xfe, 0x5a, 0x17, 0xfe, 0x94, 0x14, 0xec, 0x9a, 0x2e, 0x6c,
5906 0x1a, 0xfe, 0xaf, 0x19, 0xfe, 0x98, 0xe7, 0x00, 0x04, 0xb9, 0x23, 0xfe,
5907 0x4e, 0x17, 0xfe, 0x6c, 0x10, 0x18, 0x11, 0x75, 0xfe, 0x30, 0xbc, 0xfe,
5908 0xb2, 0xbc, 0x9a, 0xcb, 0x6c, 0x1a, 0xfe, 0x0f, 0x79, 0xfe, 0x1c, 0xf7,
5909 0xcb, 0x97, 0xfe, 0x92, 0x17, 0xfe, 0x5c, 0x14, 0x35, 0x04, 0xb9, 0x23,
5910 0xfe, 0x7e, 0x17, 0xfe, 0x42, 0x10, 0xfe, 0x02, 0xf6, 0x11, 0x75, 0xfe,
5911 0x18, 0xfe, 0x60, 0xfe, 0x19, 0xfe, 0x61, 0xfe, 0x03, 0xa1, 0xfe, 0x1d,
5912 0xf7, 0x5b, 0x97, 0xfe, 0xb8, 0x17, 0xfe, 0x36, 0x14, 0xfe, 0x1c, 0x13,
5913 0x9a, 0x5b, 0x41, 0xfe, 0x83, 0x58, 0xfe, 0xaf, 0x19, 0xfe, 0x80, 0xe7,
5914 0x11, 0xfe, 0x81, 0xe7, 0x11, 0x12, 0xfe, 0xdd, 0x00, 0x6a, 0x2a, 0x04,
5915 0x6a, 0x2a, 0xfe, 0x12, 0x45, 0x23, 0xfe, 0xa8, 0x17, 0x15, 0x06, 0x39,
5916 0xa0, 0xb4, 0x02, 0x2b, 0xfe, 0x39, 0xf0, 0xfe, 0xfc, 0x17, 0x21, 0x04,
5917 0xfe, 0x7e, 0x18, 0x1e, 0x19, 0x66, 0x0f, 0x0d, 0x04, 0x75, 0x03, 0xd2,
5918 0x1e, 0x06, 0xfe, 0xef, 0x12, 0xfe, 0xe1, 0x10, 0x7c, 0x6f, 0x4f, 0x32,
5919 0x07, 0x2f, 0xfe, 0x3c, 0x13, 0xf1, 0xfe, 0x42, 0x13, 0x42, 0x92, 0x09,
5920 0x48, 0x01, 0x0e, 0xbb, 0xeb, 0xfe, 0x41, 0x48, 0xfe, 0x45, 0x48, 0x01,
5921 0xf0, 0xfe, 0x00, 0xcc, 0xbb, 0xfe, 0xf3, 0x13, 0x43, 0x78, 0x07, 0x11,
5922 0xac, 0x09, 0x84, 0x01, 0x0e, 0xfe, 0x80, 0x4c, 0x01, 0x73, 0xfe, 0x16,
5923 0x10, 0x07, 0x82, 0x8b, 0xfe, 0x40, 0x14, 0xfe, 0x24, 0x12, 0xfe, 0x14,
5924 0x56, 0xfe, 0xd6, 0xf0, 0xfe, 0x1c, 0x18, 0x18, 0x0a, 0x04, 0xfe, 0x9c,
5925 0xe7, 0x0a, 0x10, 0xfe, 0x15, 0x00, 0x64, 0x79, 0x2a, 0x01, 0xe3, 0x18,
5926 0x06, 0x04, 0x42, 0x92, 0x08, 0x54, 0x1b, 0x37, 0x12, 0x2f, 0x01, 0x73,
5927 0x18, 0x06, 0x04, 0xfe, 0x38, 0x90, 0xfe, 0xba, 0x90, 0x3a, 0xce, 0x3b,
5928 0xcf, 0xfe, 0x48, 0x55, 0x35, 0xfe, 0xc9, 0x55, 0x04, 0x22, 0xa3, 0x77,
5929 0x13, 0xa3, 0x04, 0x09, 0xa4, 0x01, 0x0e, 0xfe, 0x41, 0x48, 0x09, 0x46,
5930 0x01, 0x0e, 0xfe, 0x49, 0x44, 0x17, 0xfe, 0xe8, 0x18, 0x77, 0x78, 0x04,
5931 0x09, 0x48, 0x01, 0x0e, 0x07, 0x11, 0x4e, 0x09, 0x5d, 0x01, 0xa8, 0x09,
5932 0x46, 0x01, 0x0e, 0x77, 0x78, 0x04, 0xfe, 0x4e, 0xe4, 0x19, 0x6b, 0xfe,
5933 0x1c, 0x19, 0x03, 0xfe, 0x90, 0x00, 0xfe, 0x3a, 0x45, 0xfe, 0x2c, 0x10,
5934 0xfe, 0x4e, 0xe4, 0xc9, 0x6b, 0xfe, 0x2e, 0x19, 0x03, 0xfe, 0x92, 0x00,
5935 0xfe, 0x02, 0xe6, 0x1a, 0xe5, 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x6b,
5936 0xfe, 0x40, 0x19, 0x03, 0xfe, 0x94, 0x00, 0xfe, 0x02, 0xe6, 0x1f, 0xfe,
5937 0x08, 0x10, 0x03, 0xfe, 0x96, 0x00, 0xfe, 0x02, 0xe6, 0x6d, 0xfe, 0x4e,
5938 0x45, 0xea, 0xba, 0xff, 0x04, 0x68, 0x54, 0xe7, 0x1e, 0x6e, 0xfe, 0x08,
5939 0x1c, 0xfe, 0x67, 0x19, 0xfe, 0x0a, 0x1c, 0xfe, 0x1a, 0xf4, 0xfe, 0x00,
5940 0x04, 0xea, 0xfe, 0x48, 0xf4, 0x19, 0x7a, 0xfe, 0x74, 0x19, 0x0f, 0x19,
5941 0x04, 0x07, 0x7e, 0xfe, 0x5a, 0xf0, 0xfe, 0x84, 0x19, 0x25, 0xfe, 0x09,
5942 0x00, 0xfe, 0x34, 0x10, 0x07, 0x1a, 0xfe, 0x5a, 0xf0, 0xfe, 0x92, 0x19,
5943 0x25, 0xca, 0xfe, 0x26, 0x10, 0x07, 0x19, 0x66, 0x25, 0x6d, 0xe5, 0x07,
5944 0x0a, 0x66, 0x25, 0x9e, 0xfe, 0x0e, 0x10, 0x07, 0x06, 0x66, 0x25, 0x59,
5945 0xa9, 0xb8, 0x04, 0x15, 0xfe, 0x09, 0x00, 0x01, 0x36, 0xfe, 0x04, 0xfe,
5946 0x81, 0x03, 0x83, 0xfe, 0x40, 0x5c, 0x04, 0x1c, 0xf7, 0xfe, 0x14, 0xf0,
5947 0x0b, 0x27, 0xfe, 0xd6, 0x19, 0x1c, 0xf7, 0x7b, 0xf7, 0xfe, 0x82, 0xf0,
5948 0xfe, 0xda, 0x19, 0x04, 0xff, 0xcc, 0x00, 0x00,
5951 static unsigned short _adv_asc38C0800_size = sizeof(_adv_asc38C0800_buf); /* 0x14E1 */
5952 static ADV_DCNT _adv_asc38C0800_chksum = 0x050D3FD8UL; /* Expanded little-endian checksum. */
5954 /* Microcode buffer is kept after initialization for error recovery. */
5955 static unsigned char _adv_asc38C1600_buf[] = {
5956 0x00, 0x00, 0x00, 0xf2, 0x00, 0x16, 0x00, 0xfc, 0x00, 0x10, 0x00, 0xf0,
5957 0x18, 0xe4, 0x01, 0x00, 0x04, 0x1e, 0x48, 0xe4, 0x03, 0xf6, 0xf7, 0x13,
5958 0x2e, 0x1e, 0x02, 0x00, 0x07, 0x17, 0xc0, 0x5f, 0x00, 0xfa, 0xff, 0xff,
5959 0x04, 0x00, 0x00, 0xf6, 0x09, 0xe7, 0x82, 0xe7, 0x85, 0xf0, 0x86, 0xf0,
5960 0x4e, 0x10, 0x9e, 0xe7, 0xff, 0x00, 0x55, 0xf0, 0x01, 0xf6, 0x03, 0x00,
5961 0x98, 0x57, 0x01, 0xe6, 0x00, 0xea, 0x00, 0xec, 0x01, 0xfa, 0x18, 0xf4,
5962 0x08, 0x00, 0xf0, 0x1d, 0x38, 0x54, 0x32, 0xf0, 0x10, 0x00, 0xc2, 0x0e,
5963 0x1e, 0xf0, 0xd5, 0xf0, 0xbc, 0x00, 0x4b, 0xe4, 0x00, 0xe6, 0xb1, 0xf0,
5964 0xb4, 0x00, 0x02, 0x13, 0x3e, 0x1c, 0xc8, 0x47, 0x3e, 0x00, 0xd8, 0x01,
5965 0x06, 0x13, 0x0c, 0x1c, 0x5e, 0x1e, 0x00, 0x57, 0xc8, 0x57, 0x01, 0xfc,
5966 0xbc, 0x0e, 0xa2, 0x12, 0xb9, 0x54, 0x00, 0x80, 0x62, 0x0a, 0x5a, 0x12,
5967 0xc8, 0x15, 0x3e, 0x1e, 0x18, 0x40, 0xbd, 0x56, 0x03, 0xe6, 0x01, 0xea,
5968 0x5c, 0xf0, 0x0f, 0x00, 0x20, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x04, 0x12,
5969 0x04, 0x13, 0xbb, 0x55, 0x3c, 0x56, 0x3e, 0x57, 0x03, 0x58, 0x4a, 0xe4,
5970 0x40, 0x00, 0xb6, 0x00, 0xbb, 0x00, 0xc0, 0x00, 0x00, 0x01, 0x01, 0x01,
5971 0x3e, 0x01, 0x58, 0x0a, 0x44, 0x10, 0x0a, 0x12, 0x4c, 0x1c, 0x4e, 0x1c,
5972 0x02, 0x4a, 0x30, 0xe4, 0x05, 0xe6, 0x0c, 0x00, 0x3c, 0x00, 0x80, 0x00,
5973 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01, 0x70, 0x01, 0x72, 0x01,
5974 0x74, 0x01, 0x76, 0x01, 0x78, 0x01, 0x7c, 0x01, 0xc6, 0x0e, 0x0c, 0x10,
5975 0xac, 0x12, 0xae, 0x12, 0x16, 0x1a, 0x32, 0x1c, 0x6e, 0x1e, 0x02, 0x48,
5976 0x3a, 0x55, 0xc9, 0x57, 0x02, 0xee, 0x5b, 0xf0, 0x03, 0xf7, 0x06, 0xf7,
5977 0x03, 0xfc, 0x06, 0x00, 0x1e, 0x00, 0xbe, 0x00, 0xe1, 0x00, 0x0c, 0x12,
5978 0x18, 0x1a, 0x70, 0x1a, 0x30, 0x1c, 0x38, 0x1c, 0x10, 0x44, 0x00, 0x4c,
5979 0xb0, 0x57, 0x40, 0x5c, 0x4d, 0xe4, 0x04, 0xea, 0x5d, 0xf0, 0xa7, 0xf0,
5980 0x04, 0xf6, 0x02, 0xfc, 0x05, 0x00, 0x09, 0x00, 0x19, 0x00, 0x32, 0x00,
5981 0x33, 0x00, 0x34, 0x00, 0x36, 0x00, 0x98, 0x00, 0x9e, 0x00, 0xcc, 0x00,
5982 0x20, 0x01, 0x4e, 0x01, 0x79, 0x01, 0x3c, 0x09, 0x68, 0x0d, 0x02, 0x10,
5983 0x04, 0x10, 0x3a, 0x10, 0x08, 0x12, 0x0a, 0x13, 0x40, 0x16, 0x50, 0x16,
5984 0x00, 0x17, 0x4a, 0x19, 0x00, 0x4e, 0x00, 0x54, 0x01, 0x58, 0x00, 0xdc,
5985 0x05, 0xf0, 0x09, 0xf0, 0x59, 0xf0, 0xb8, 0xf0, 0x48, 0xf4, 0x0e, 0xf7,
5986 0x0a, 0x00, 0x9b, 0x00, 0x9c, 0x00, 0xa4, 0x00, 0xb5, 0x00, 0xba, 0x00,
5987 0xd0, 0x00, 0xe7, 0x00, 0xf0, 0x03, 0x69, 0x08, 0xe9, 0x09, 0x5c, 0x0c,
5988 0xb6, 0x12, 0xbc, 0x19, 0xd8, 0x1b, 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c,
5989 0x42, 0x1d, 0x08, 0x44, 0x38, 0x44, 0x91, 0x44, 0x0a, 0x45, 0x48, 0x46,
5990 0x89, 0x48, 0x68, 0x54, 0x83, 0x55, 0x83, 0x59, 0x31, 0xe4, 0x02, 0xe6,
5991 0x07, 0xf0, 0x08, 0xf0, 0x0b, 0xf0, 0x0c, 0xf0, 0x4b, 0xf4, 0x04, 0xf8,
5992 0x05, 0xf8, 0x02, 0xfa, 0x03, 0xfa, 0x04, 0xfc, 0x05, 0xfc, 0x07, 0x00,
5993 0xa8, 0x00, 0xaa, 0x00, 0xb9, 0x00, 0xe0, 0x00, 0xe5, 0x00, 0x22, 0x01,
5994 0x26, 0x01, 0x60, 0x01, 0x7a, 0x01, 0x82, 0x01, 0xc8, 0x01, 0xca, 0x01,
5995 0x86, 0x02, 0x6a, 0x03, 0x18, 0x05, 0xb2, 0x07, 0x68, 0x08, 0x10, 0x0d,
5996 0x06, 0x10, 0x0a, 0x10, 0x0e, 0x10, 0x12, 0x10, 0x60, 0x10, 0xed, 0x10,
5997 0xf3, 0x10, 0x06, 0x12, 0x10, 0x12, 0x1e, 0x12, 0x0c, 0x13, 0x0e, 0x13,
5998 0x10, 0x13, 0xfe, 0x9c, 0xf0, 0x35, 0x05, 0xfe, 0xec, 0x0e, 0xff, 0x10,
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6444 0x61, 0x28, 0x44, 0x15, 0x56, 0x01, 0x85, 0x1c, 0x07, 0x02, 0xfe, 0x38,
6445 0x90, 0xfe, 0xba, 0x90, 0x91, 0xde, 0x7e, 0xdf, 0xfe, 0x48, 0x55, 0x31,
6446 0xfe, 0xc9, 0x55, 0x02, 0x21, 0xb9, 0x88, 0x20, 0xb9, 0x02, 0x0a, 0xba,
6447 0x01, 0x18, 0xfe, 0x41, 0x48, 0x0a, 0x57, 0x01, 0x18, 0xfe, 0x49, 0x44,
6448 0x1b, 0xfe, 0x1e, 0x1d, 0x88, 0x89, 0x02, 0x0a, 0x5a, 0x01, 0x18, 0x09,
6449 0x1a, 0xa4, 0x0a, 0x67, 0x01, 0xa3, 0x0a, 0x57, 0x01, 0x18, 0x88, 0x89,
6450 0x02, 0xfe, 0x4e, 0xe4, 0x1d, 0x7b, 0xfe, 0x52, 0x1d, 0x03, 0xfe, 0x90,
6451 0x00, 0xfe, 0x3a, 0x45, 0xfe, 0x2c, 0x10, 0xfe, 0x4e, 0xe4, 0xdd, 0x7b,
6452 0xfe, 0x64, 0x1d, 0x03, 0xfe, 0x92, 0x00, 0xd1, 0x12, 0xfe, 0x1a, 0x10,
6453 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x7b, 0xfe, 0x76, 0x1d, 0x03, 0xfe,
6454 0x94, 0x00, 0xd1, 0x24, 0xfe, 0x08, 0x10, 0x03, 0xfe, 0x96, 0x00, 0xd1,
6455 0x63, 0xfe, 0x4e, 0x45, 0x83, 0xca, 0xff, 0x04, 0x68, 0x54, 0xfe, 0xf1,
6456 0x10, 0x23, 0x49, 0xfe, 0x08, 0x1c, 0xfe, 0x67, 0x19, 0xfe, 0x0a, 0x1c,
6457 0xfe, 0x1a, 0xf4, 0xfe, 0x00, 0x04, 0x83, 0xb2, 0x1d, 0x48, 0xfe, 0xaa,
6458 0x1d, 0x13, 0x1d, 0x02, 0x09, 0x92, 0xfe, 0x5a, 0xf0, 0xfe, 0xba, 0x1d,
6459 0x2e, 0x93, 0xfe, 0x34, 0x10, 0x09, 0x12, 0xfe, 0x5a, 0xf0, 0xfe, 0xc8,
6460 0x1d, 0x2e, 0xb4, 0xfe, 0x26, 0x10, 0x09, 0x1d, 0x36, 0x2e, 0x63, 0xfe,
6461 0x1a, 0x10, 0x09, 0x0d, 0x36, 0x2e, 0x94, 0xf2, 0x09, 0x07, 0x36, 0x2e,
6462 0x95, 0xa1, 0xc8, 0x02, 0x1f, 0x93, 0x01, 0x42, 0xfe, 0x04, 0xfe, 0x99,
6463 0x03, 0x9c, 0x8b, 0x02, 0x2a, 0xfe, 0x1c, 0x1e, 0xfe, 0x14, 0xf0, 0x08,
6464 0x2f, 0xfe, 0x0c, 0x1e, 0x2a, 0xfe, 0x1c, 0x1e, 0x8f, 0xfe, 0x1c, 0x1e,
6465 0xfe, 0x82, 0xf0, 0xfe, 0x10, 0x1e, 0x02, 0x0f, 0x3f, 0x04, 0xfe, 0x80,
6466 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x18, 0x80, 0x04, 0xfe, 0x98,
6467 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x02, 0x80, 0x04, 0xfe, 0x82,
6468 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x06, 0x80, 0x04, 0xfe, 0x86,
6469 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x1b, 0x80, 0x04, 0xfe, 0x9b,
6470 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x04, 0x80, 0x04, 0xfe, 0x84,
6471 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x80, 0x80, 0x04, 0xfe, 0x80,
6472 0x83, 0xfe, 0xc9, 0x47, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x19, 0x81, 0x04,
6473 0xfe, 0x99, 0x83, 0xfe, 0xca, 0x47, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x06,
6474 0x83, 0x04, 0xfe, 0x86, 0x83, 0xfe, 0xce, 0x47, 0x0b, 0x0e, 0x02, 0x0f,
6475 0xfe, 0x2c, 0x90, 0x04, 0xfe, 0xac, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f,
6476 0xfe, 0xae, 0x90, 0x04, 0xfe, 0xae, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f,
6477 0xfe, 0x08, 0x90, 0x04, 0xfe, 0x88, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f,
6478 0xfe, 0x8a, 0x90, 0x04, 0xfe, 0x8a, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f,
6479 0xfe, 0x0c, 0x90, 0x04, 0xfe, 0x8c, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f,
6480 0xfe, 0x8e, 0x90, 0x04, 0xfe, 0x8e, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f,
6481 0xfe, 0x3c, 0x90, 0x04, 0xfe, 0xbc, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x8b,
6482 0x0f, 0xfe, 0x03, 0x80, 0x04, 0xfe, 0x83, 0x83, 0x33, 0x0b, 0x77, 0x0e,
6483 0xa8, 0x02, 0xff, 0x66, 0x00, 0x00,
6486 static unsigned short _adv_asc38C1600_size = sizeof(_adv_asc38C1600_buf); /* 0x1673 */
6487 static ADV_DCNT _adv_asc38C1600_chksum = 0x0604EF77UL; /* Expanded little-endian checksum. */
6489 static void AscInitQLinkVar(ASC_DVC_VAR *asc_dvc)
6495 iop_base = asc_dvc->iop_base;
6496 AscPutRiscVarFreeQHead(iop_base, 1);
6497 AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng);
6498 AscPutVarFreeQHead(iop_base, 1);
6499 AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng);
6500 AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B,
6501 (uchar)((int)asc_dvc->max_total_qng + 1));
6502 AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B,
6503 (uchar)((int)asc_dvc->max_total_qng + 2));
6504 AscWriteLramByte(iop_base, (ushort)ASCV_TOTAL_READY_Q_B,
6505 asc_dvc->max_total_qng);
6506 AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0);
6507 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6508 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0);
6509 AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0);
6510 AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0);
6511 AscPutQDoneInProgress(iop_base, 0);
6512 lram_addr = ASC_QADR_BEG;
6513 for (i = 0; i < 32; i++, lram_addr += 2) {
6514 AscWriteLramWord(iop_base, lram_addr, 0);
6518 static ushort AscInitMicroCodeVar(ASC_DVC_VAR *asc_dvc)
6526 iop_base = asc_dvc->iop_base;
6528 for (i = 0; i <= ASC_MAX_TID; i++) {
6529 AscPutMCodeInitSDTRAtID(iop_base, i,
6530 asc_dvc->cfg->sdtr_period_offset[i]);
6533 AscInitQLinkVar(asc_dvc);
6534 AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B,
6535 asc_dvc->cfg->disc_enable);
6536 AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B,
6537 ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id));
6539 /* Align overrun buffer on an 8 byte boundary. */
6540 phy_addr = virt_to_bus(asc_dvc->cfg->overrun_buf);
6541 phy_addr = cpu_to_le32((phy_addr + 7) & ~0x7);
6542 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D,
6543 (uchar *)&phy_addr, 1);
6544 phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE - 8);
6545 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D,
6546 (uchar *)&phy_size, 1);
6548 asc_dvc->cfg->mcode_date =
6549 AscReadLramWord(iop_base, (ushort)ASCV_MC_DATE_W);
6550 asc_dvc->cfg->mcode_version =
6551 AscReadLramWord(iop_base, (ushort)ASCV_MC_VER_W);
6553 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
6554 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
6555 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
6558 if (AscStartChip(iop_base) != 1) {
6559 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
6566 static ushort AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc)
6571 iop_base = asc_dvc->iop_base;
6573 if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) &&
6574 !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) {
6575 AscResetChipAndScsiBus(asc_dvc);
6576 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
6578 asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC;
6579 if (asc_dvc->err_code != 0)
6581 if (!AscFindSignature(asc_dvc->iop_base)) {
6582 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
6585 AscDisableInterrupt(iop_base);
6586 warn_code |= AscInitLram(asc_dvc);
6587 if (asc_dvc->err_code != 0)
6589 ASC_DBG1(1, "AscInitAsc1000Driver: _asc_mcode_chksum 0x%lx\n",
6590 (ulong)_asc_mcode_chksum);
6591 if (AscLoadMicroCode(iop_base, 0, _asc_mcode_buf,
6592 _asc_mcode_size) != _asc_mcode_chksum) {
6593 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
6596 warn_code |= AscInitMicroCodeVar(asc_dvc);
6597 asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC;
6598 AscEnableInterrupt(iop_base);
6603 * Load the Microcode
6605 * Write the microcode image to RISC memory starting at address 0.
6607 * The microcode is stored compressed in the following format:
6609 * 254 word (508 byte) table indexed by byte code followed
6610 * by the following byte codes:
6613 * 00: Emit word 0 in table.
6614 * 01: Emit word 1 in table.
6616 * FD: Emit word 253 in table.
6619 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
6620 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
6622 * Returns 0 or an error if the checksum doesn't match
6624 static int AdvLoadMicrocode(AdvPortAddr iop_base, unsigned char *buf, int size,
6625 int memsize, int chksum)
6627 int i, j, end, len = 0;
6630 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
6632 for (i = 253 * 2; i < size; i++) {
6633 if (buf[i] == 0xff) {
6634 unsigned short word = (buf[i + 3] << 8) | buf[i + 2];
6635 for (j = 0; j < buf[i + 1]; j++) {
6636 AdvWriteWordAutoIncLram(iop_base, word);
6640 } else if (buf[i] == 0xfe) {
6641 unsigned short word = (buf[i + 2] << 8) | buf[i + 1];
6642 AdvWriteWordAutoIncLram(iop_base, word);
6646 unsigned char off = buf[i] * 2;
6647 unsigned short word = (buf[off + 1] << 8) | buf[off];
6648 AdvWriteWordAutoIncLram(iop_base, word);
6655 while (len < memsize) {
6656 AdvWriteWordAutoIncLram(iop_base, 0);
6660 /* Verify the microcode checksum. */
6662 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
6664 for (len = 0; len < end; len += 2) {
6665 sum += AdvReadWordAutoIncLram(iop_base);
6669 return ASC_IERR_MCODE_CHKSUM;
6677 * Return the physical address of 'vaddr' and set '*lenp' to the
6678 * number of physically contiguous bytes that follow 'vaddr'.
6679 * 'flag' indicates the type of structure whose physical address
6680 * is being translated.
6682 * Note: Because Linux currently doesn't page the kernel and all
6683 * kernel buffers are physically contiguous, leave '*lenp' unchanged.
6686 DvcGetPhyAddr(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq,
6687 uchar *vaddr, ADV_SDCNT *lenp, int flag)
6689 ADV_PADDR paddr = virt_to_bus(vaddr);
6691 ASC_DBG4(4, "DvcGetPhyAddr: vaddr 0x%p, lenp 0x%p *lenp %lu, paddr 0x%lx\n",
6692 vaddr, lenp, (ulong)*((ulong *)lenp), (ulong)paddr);
6697 static void AdvBuildCarrierFreelist(struct adv_dvc_var *asc_dvc)
6701 ADV_PADDR carr_paddr;
6703 BUG_ON(!asc_dvc->carrier_buf);
6705 carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
6706 asc_dvc->carr_freelist = NULL;
6707 if (carrp == asc_dvc->carrier_buf) {
6708 buf_size = ADV_CARRIER_BUFSIZE;
6710 buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T);
6714 /* Get physical address of the carrier 'carrp'. */
6715 ADV_DCNT contig_len = sizeof(ADV_CARR_T);
6716 carr_paddr = cpu_to_le32(DvcGetPhyAddr(asc_dvc, NULL,
6718 (ADV_SDCNT *)&contig_len,
6719 ADV_IS_CARRIER_FLAG));
6721 buf_size -= sizeof(ADV_CARR_T);
6724 * If the current carrier is not physically contiguous, then
6725 * maybe there was a page crossing. Try the next carrier
6726 * aligned start address.
6728 if (contig_len < sizeof(ADV_CARR_T)) {
6733 carrp->carr_pa = carr_paddr;
6734 carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp));
6737 * Insert the carrier at the beginning of the freelist.
6740 cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
6741 asc_dvc->carr_freelist = carrp;
6744 } while (buf_size > 0);
6748 * Send an idle command to the chip and wait for completion.
6750 * Command completion is polled for once per microsecond.
6752 * The function can be called from anywhere including an interrupt handler.
6753 * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical()
6754 * functions to prevent reentrancy.
6757 * ADV_TRUE - command completed successfully
6758 * ADV_FALSE - command failed
6759 * ADV_ERROR - command timed out
6762 AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc,
6763 ushort idle_cmd, ADV_DCNT idle_cmd_parameter)
6767 AdvPortAddr iop_base;
6769 iop_base = asc_dvc->iop_base;
6772 * Clear the idle command status which is set by the microcode
6773 * to a non-zero value to indicate when the command is completed.
6774 * The non-zero result is one of the IDLE_CMD_STATUS_* values
6776 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort)0);
6779 * Write the idle command value after the idle command parameter
6780 * has been written to avoid a race condition. If the order is not
6781 * followed, the microcode may process the idle command before the
6782 * parameters have been written to LRAM.
6784 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER,
6785 cpu_to_le32(idle_cmd_parameter));
6786 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd);
6789 * Tickle the RISC to tell it to process the idle command.
6791 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B);
6792 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
6794 * Clear the tickle value. In the ASC-3550 the RISC flag
6795 * command 'clr_tickle_b' does not work unless the host
6798 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
6801 /* Wait for up to 100 millisecond for the idle command to timeout. */
6802 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) {
6803 /* Poll once each microsecond for command completion. */
6804 for (j = 0; j < SCSI_US_PER_MSEC; j++) {
6805 AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS,
6813 BUG(); /* The idle command should never timeout. */
6818 * Reset SCSI Bus and purge all outstanding requests.
6821 * ADV_TRUE(1) - All requests are purged and SCSI Bus is reset.
6822 * ADV_FALSE(0) - Microcode command failed.
6823 * ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC
6824 * may be hung which requires driver recovery.
6826 static int AdvResetSB(ADV_DVC_VAR *asc_dvc)
6831 * Send the SCSI Bus Reset idle start idle command which asserts
6832 * the SCSI Bus Reset signal.
6834 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_START, 0L);
6835 if (status != ADV_TRUE) {
6840 * Delay for the specified SCSI Bus Reset hold time.
6842 * The hold time delay is done on the host because the RISC has no
6843 * microsecond accurate timer.
6845 udelay(ASC_SCSI_RESET_HOLD_TIME_US);
6848 * Send the SCSI Bus Reset end idle command which de-asserts
6849 * the SCSI Bus Reset signal and purges any pending requests.
6851 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_END, 0L);
6852 if (status != ADV_TRUE) {
6856 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
6862 * Initialize the ASC-3550.
6864 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
6866 * For a non-fatal error return a warning code. If there are no warnings
6867 * then 0 is returned.
6869 * Needed after initialization for error recovery.
6871 static int AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc)
6873 AdvPortAddr iop_base;
6882 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
6883 ushort wdtr_able = 0, sdtr_able, tagqng_able;
6884 uchar max_cmd[ADV_MAX_TID + 1];
6886 /* If there is already an error, don't continue. */
6887 if (asc_dvc->err_code != 0)
6891 * The caller must set 'chip_type' to ADV_CHIP_ASC3550.
6893 if (asc_dvc->chip_type != ADV_CHIP_ASC3550) {
6894 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
6899 iop_base = asc_dvc->iop_base;
6902 * Save the RISC memory BIOS region before writing the microcode.
6903 * The BIOS may already be loaded and using its RISC LRAM region
6904 * so its region must be saved and restored.
6906 * Note: This code makes the assumption, which is currently true,
6907 * that a chip reset does not clear RISC LRAM.
6909 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
6910 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
6915 * Save current per TID negotiated values.
6917 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 0x55AA) {
6918 ushort bios_version, major, minor;
6921 bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM) / 2];
6922 major = (bios_version >> 12) & 0xF;
6923 minor = (bios_version >> 8) & 0xF;
6924 if (major < 3 || (major == 3 && minor == 1)) {
6925 /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */
6926 AdvReadWordLram(iop_base, 0x120, wdtr_able);
6928 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
6931 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
6932 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
6933 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
6934 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
6938 asc_dvc->err_code = AdvLoadMicrocode(iop_base, _adv_asc3550_buf,
6939 _adv_asc3550_size, ADV_3550_MEMSIZE,
6940 _adv_asc3550_chksum);
6941 if (asc_dvc->err_code)
6945 * Restore the RISC memory BIOS region.
6947 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
6948 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
6953 * Calculate and write the microcode code checksum to the microcode
6954 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
6956 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
6957 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
6959 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
6960 for (word = begin_addr; word < end_addr; word += 2) {
6961 code_sum += AdvReadWordAutoIncLram(iop_base);
6963 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
6966 * Read and save microcode version and date.
6968 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
6969 asc_dvc->cfg->mcode_date);
6970 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
6971 asc_dvc->cfg->mcode_version);
6974 * Set the chip type to indicate the ASC3550.
6976 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550);
6979 * If the PCI Configuration Command Register "Parity Error Response
6980 * Control" Bit was clear (0), then set the microcode variable
6981 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
6982 * to ignore DMA parity errors.
6984 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
6985 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
6986 word |= CONTROL_FLAG_IGNORE_PERR;
6987 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
6991 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO
6992 * threshold of 128 bytes. This register is only accessible to the host.
6994 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
6995 START_CTL_EMFU | READ_CMD_MRM);
6998 * Microcode operating variables for WDTR, SDTR, and command tag
6999 * queuing will be set in slave_configure() based on what a
7000 * device reports it is capable of in Inquiry byte 7.
7002 * If SCSI Bus Resets have been disabled, then directly set
7003 * SDTR and WDTR from the EEPROM configuration. This will allow
7004 * the BIOS and warm boot to work without a SCSI bus hang on
7005 * the Inquiry caused by host and target mismatched DTR values.
7006 * Without the SCSI Bus Reset, before an Inquiry a device can't
7007 * be assumed to be in Asynchronous, Narrow mode.
7009 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
7010 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
7011 asc_dvc->wdtr_able);
7012 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
7013 asc_dvc->sdtr_able);
7017 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
7018 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
7019 * bitmask. These values determine the maximum SDTR speed negotiated
7022 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
7023 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
7024 * without determining here whether the device supports SDTR.
7026 * 4-bit speed SDTR speed name
7027 * =========== ===============
7028 * 0000b (0x0) SDTR disabled
7030 * 0010b (0x2) 10 Mhz
7031 * 0011b (0x3) 20 Mhz (Ultra)
7032 * 0100b (0x4) 40 Mhz (LVD/Ultra2)
7033 * 0101b (0x5) 80 Mhz (LVD2/Ultra3)
7034 * 0110b (0x6) Undefined
7036 * 1111b (0xF) Undefined
7039 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
7040 if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able) {
7041 /* Set Ultra speed for TID 'tid'. */
7042 word |= (0x3 << (4 * (tid % 4)));
7044 /* Set Fast speed for TID 'tid'. */
7045 word |= (0x2 << (4 * (tid % 4)));
7047 if (tid == 3) { /* Check if done with sdtr_speed1. */
7048 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word);
7050 } else if (tid == 7) { /* Check if done with sdtr_speed2. */
7051 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word);
7053 } else if (tid == 11) { /* Check if done with sdtr_speed3. */
7054 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word);
7056 } else if (tid == 15) { /* Check if done with sdtr_speed4. */
7057 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word);
7063 * Set microcode operating variable for the disconnect per TID bitmask.
7065 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
7066 asc_dvc->cfg->disc_enable);
7069 * Set SCSI_CFG0 Microcode Default Value.
7071 * The microcode will set the SCSI_CFG0 register using this value
7072 * after it is started below.
7074 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
7075 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
7076 asc_dvc->chip_scsi_id);
7079 * Determine SCSI_CFG1 Microcode Default Value.
7081 * The microcode will set the SCSI_CFG1 register using this value
7082 * after it is started below.
7085 /* Read current SCSI_CFG1 Register value. */
7086 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
7089 * If all three connectors are in use, return an error.
7091 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
7092 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) {
7093 asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION;
7098 * If the internal narrow cable is reversed all of the SCSI_CTRL
7099 * register signals will be set. Check for and return an error if
7100 * this condition is found.
7102 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
7103 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
7108 * If this is a differential board and a single-ended device
7109 * is attached to one of the connectors, return an error.
7111 if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0) {
7112 asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE;
7117 * If automatic termination control is enabled, then set the
7118 * termination value based on a table listed in a_condor.h.
7120 * If manual termination was specified with an EEPROM setting
7121 * then 'termination' was set-up in AdvInitFrom3550EEPROM() and
7122 * is ready to be 'ored' into SCSI_CFG1.
7124 if (asc_dvc->cfg->termination == 0) {
7126 * The software always controls termination by setting TERM_CTL_SEL.
7127 * If TERM_CTL_SEL were set to 0, the hardware would set termination.
7129 asc_dvc->cfg->termination |= TERM_CTL_SEL;
7131 switch (scsi_cfg1 & CABLE_DETECT) {
7132 /* TERM_CTL_H: on, TERM_CTL_L: on */
7139 asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L);
7142 /* TERM_CTL_H: on, TERM_CTL_L: off */
7148 asc_dvc->cfg->termination |= TERM_CTL_H;
7151 /* TERM_CTL_H: off, TERM_CTL_L: off */
7159 * Clear any set TERM_CTL_H and TERM_CTL_L bits.
7161 scsi_cfg1 &= ~TERM_CTL;
7164 * Invert the TERM_CTL_H and TERM_CTL_L bits and then
7165 * set 'scsi_cfg1'. The TERM_POL bit does not need to be
7166 * referenced, because the hardware internally inverts
7167 * the Termination High and Low bits if TERM_POL is set.
7169 scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL));
7172 * Set SCSI_CFG1 Microcode Default Value
7174 * Set filter value and possibly modified termination control
7175 * bits in the Microcode SCSI_CFG1 Register Value.
7177 * The microcode will set the SCSI_CFG1 register using this value
7178 * after it is started below.
7180 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1,
7181 FLTR_DISABLE | scsi_cfg1);
7184 * Set MEM_CFG Microcode Default Value
7186 * The microcode will set the MEM_CFG register using this value
7187 * after it is started below.
7189 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
7192 * ASC-3550 has 8KB internal memory.
7194 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
7195 BIOS_EN | RAM_SZ_8KB);
7198 * Set SEL_MASK Microcode Default Value
7200 * The microcode will set the SEL_MASK register using this value
7201 * after it is started below.
7203 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
7204 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
7206 AdvBuildCarrierFreelist(asc_dvc);
7209 * Set-up the Host->RISC Initiator Command Queue (ICQ).
7212 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
7213 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
7216 asc_dvc->carr_freelist = (ADV_CARR_T *)
7217 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
7220 * The first command issued will be placed in the stopper carrier.
7222 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
7225 * Set RISC ICQ physical address start value.
7227 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
7230 * Set-up the RISC->Host Initiator Response Queue (IRQ).
7232 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
7233 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
7236 asc_dvc->carr_freelist = (ADV_CARR_T *)
7237 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
7240 * The first command completed by the RISC will be placed in
7243 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
7244 * completed the RISC will set the ASC_RQ_STOPPER bit.
7246 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
7249 * Set RISC IRQ physical address start value.
7251 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
7252 asc_dvc->carr_pending_cnt = 0;
7254 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
7255 (ADV_INTR_ENABLE_HOST_INTR |
7256 ADV_INTR_ENABLE_GLOBAL_INTR));
7258 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
7259 AdvWriteWordRegister(iop_base, IOPW_PC, word);
7261 /* finally, finally, gentlemen, start your engine */
7262 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
7265 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
7266 * Resets should be performed. The RISC has to be running
7267 * to issue a SCSI Bus Reset.
7269 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
7271 * If the BIOS Signature is present in memory, restore the
7272 * BIOS Handshake Configuration Table and do not perform
7275 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
7278 * Restore per TID negotiated values.
7280 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
7281 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
7282 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
7284 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
7285 AdvWriteByteLram(iop_base,
7286 ASC_MC_NUMBER_OF_MAX_CMD + tid,
7290 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
7291 warn_code = ASC_WARN_BUSRESET_ERROR;
7300 * Initialize the ASC-38C0800.
7302 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
7304 * For a non-fatal error return a warning code. If there are no warnings
7305 * then 0 is returned.
7307 * Needed after initialization for error recovery.
7309 static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc)
7311 AdvPortAddr iop_base;
7321 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
7322 ushort wdtr_able, sdtr_able, tagqng_able;
7323 uchar max_cmd[ADV_MAX_TID + 1];
7325 /* If there is already an error, don't continue. */
7326 if (asc_dvc->err_code != 0)
7330 * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800.
7332 if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800) {
7333 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
7338 iop_base = asc_dvc->iop_base;
7341 * Save the RISC memory BIOS region before writing the microcode.
7342 * The BIOS may already be loaded and using its RISC LRAM region
7343 * so its region must be saved and restored.
7345 * Note: This code makes the assumption, which is currently true,
7346 * that a chip reset does not clear RISC LRAM.
7348 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
7349 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
7354 * Save current per TID negotiated values.
7356 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
7357 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
7358 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
7359 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
7360 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
7365 * RAM BIST (RAM Built-In Self Test)
7367 * Address : I/O base + offset 0x38h register (byte).
7368 * Function: Bit 7-6(RW) : RAM mode
7369 * Normal Mode : 0x00
7370 * Pre-test Mode : 0x40
7371 * RAM Test Mode : 0x80
7373 * Bit 4(RO) : Done bit
7374 * Bit 3-0(RO) : Status
7376 * Int_RAM Error : 0x04
7381 * Note: RAM BIST code should be put right here, before loading the
7382 * microcode and after saving the RISC memory BIOS region.
7388 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
7389 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
7390 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
7391 * to NORMAL_MODE, return an error too.
7393 for (i = 0; i < 2; i++) {
7394 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
7395 mdelay(10); /* Wait for 10ms before reading back. */
7396 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
7397 if ((byte & RAM_TEST_DONE) == 0
7398 || (byte & 0x0F) != PRE_TEST_VALUE) {
7399 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
7403 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
7404 mdelay(10); /* Wait for 10ms before reading back. */
7405 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
7407 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
7413 * LRAM Test - It takes about 1.5 ms to run through the test.
7415 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
7416 * If Done bit not set or Status not 0, save register byte, set the
7417 * err_code, and return an error.
7419 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
7420 mdelay(10); /* Wait for 10ms before checking status. */
7422 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
7423 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
7424 /* Get here if Done bit not set or Status not 0. */
7425 asc_dvc->bist_err_code = byte; /* for BIOS display message */
7426 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
7430 /* We need to reset back to normal mode after LRAM test passes. */
7431 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
7433 asc_dvc->err_code = AdvLoadMicrocode(iop_base, _adv_asc38C0800_buf,
7434 _adv_asc38C0800_size, ADV_38C0800_MEMSIZE,
7435 _adv_asc38C0800_chksum);
7436 if (asc_dvc->err_code)
7440 * Restore the RISC memory BIOS region.
7442 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
7443 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
7448 * Calculate and write the microcode code checksum to the microcode
7449 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
7451 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
7452 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
7454 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
7455 for (word = begin_addr; word < end_addr; word += 2) {
7456 code_sum += AdvReadWordAutoIncLram(iop_base);
7458 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
7461 * Read microcode version and date.
7463 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
7464 asc_dvc->cfg->mcode_date);
7465 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
7466 asc_dvc->cfg->mcode_version);
7469 * Set the chip type to indicate the ASC38C0800.
7471 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800);
7474 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
7475 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
7476 * cable detection and then we are able to read C_DET[3:0].
7478 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
7479 * Microcode Default Value' section below.
7481 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
7482 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
7483 scsi_cfg1 | DIS_TERM_DRV);
7486 * If the PCI Configuration Command Register "Parity Error Response
7487 * Control" Bit was clear (0), then set the microcode variable
7488 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
7489 * to ignore DMA parity errors.
7491 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
7492 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7493 word |= CONTROL_FLAG_IGNORE_PERR;
7494 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7498 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2]
7499 * bits for the default FIFO threshold.
7501 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
7503 * For DMA Errata #4 set the BC_THRESH_ENB bit.
7505 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
7506 BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH |
7510 * Microcode operating variables for WDTR, SDTR, and command tag
7511 * queuing will be set in slave_configure() based on what a
7512 * device reports it is capable of in Inquiry byte 7.
7514 * If SCSI Bus Resets have been disabled, then directly set
7515 * SDTR and WDTR from the EEPROM configuration. This will allow
7516 * the BIOS and warm boot to work without a SCSI bus hang on
7517 * the Inquiry caused by host and target mismatched DTR values.
7518 * Without the SCSI Bus Reset, before an Inquiry a device can't
7519 * be assumed to be in Asynchronous, Narrow mode.
7521 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
7522 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
7523 asc_dvc->wdtr_able);
7524 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
7525 asc_dvc->sdtr_able);
7529 * Set microcode operating variables for DISC and SDTR_SPEED1,
7530 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
7531 * configuration values.
7533 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
7534 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
7535 * without determining here whether the device supports SDTR.
7537 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
7538 asc_dvc->cfg->disc_enable);
7539 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
7540 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
7541 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
7542 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
7545 * Set SCSI_CFG0 Microcode Default Value.
7547 * The microcode will set the SCSI_CFG0 register using this value
7548 * after it is started below.
7550 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
7551 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
7552 asc_dvc->chip_scsi_id);
7555 * Determine SCSI_CFG1 Microcode Default Value.
7557 * The microcode will set the SCSI_CFG1 register using this value
7558 * after it is started below.
7561 /* Read current SCSI_CFG1 Register value. */
7562 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
7565 * If the internal narrow cable is reversed all of the SCSI_CTRL
7566 * register signals will be set. Check for and return an error if
7567 * this condition is found.
7569 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
7570 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
7575 * All kind of combinations of devices attached to one of four
7576 * connectors are acceptable except HVD device attached. For example,
7577 * LVD device can be attached to SE connector while SE device attached
7578 * to LVD connector. If LVD device attached to SE connector, it only
7579 * runs up to Ultra speed.
7581 * If an HVD device is attached to one of LVD connectors, return an
7582 * error. However, there is no way to detect HVD device attached to
7585 if (scsi_cfg1 & HVD) {
7586 asc_dvc->err_code = ASC_IERR_HVD_DEVICE;
7591 * If either SE or LVD automatic termination control is enabled, then
7592 * set the termination value based on a table listed in a_condor.h.
7594 * If manual termination was specified with an EEPROM setting then
7595 * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready
7596 * to be 'ored' into SCSI_CFG1.
7598 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
7599 /* SE automatic termination control is enabled. */
7600 switch (scsi_cfg1 & C_DET_SE) {
7601 /* TERM_SE_HI: on, TERM_SE_LO: on */
7605 asc_dvc->cfg->termination |= TERM_SE;
7608 /* TERM_SE_HI: on, TERM_SE_LO: off */
7610 asc_dvc->cfg->termination |= TERM_SE_HI;
7615 if ((asc_dvc->cfg->termination & TERM_LVD) == 0) {
7616 /* LVD automatic termination control is enabled. */
7617 switch (scsi_cfg1 & C_DET_LVD) {
7618 /* TERM_LVD_HI: on, TERM_LVD_LO: on */
7622 asc_dvc->cfg->termination |= TERM_LVD;
7625 /* TERM_LVD_HI: off, TERM_LVD_LO: off */
7632 * Clear any set TERM_SE and TERM_LVD bits.
7634 scsi_cfg1 &= (~TERM_SE & ~TERM_LVD);
7637 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
7639 scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0);
7642 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE
7643 * bits and set possibly modified termination control bits in the
7644 * Microcode SCSI_CFG1 Register Value.
7646 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE);
7649 * Set SCSI_CFG1 Microcode Default Value
7651 * Set possibly modified termination control and reset DIS_TERM_DRV
7652 * bits in the Microcode SCSI_CFG1 Register Value.
7654 * The microcode will set the SCSI_CFG1 register using this value
7655 * after it is started below.
7657 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
7660 * Set MEM_CFG Microcode Default Value
7662 * The microcode will set the MEM_CFG register using this value
7663 * after it is started below.
7665 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
7668 * ASC-38C0800 has 16KB internal memory.
7670 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
7671 BIOS_EN | RAM_SZ_16KB);
7674 * Set SEL_MASK Microcode Default Value
7676 * The microcode will set the SEL_MASK register using this value
7677 * after it is started below.
7679 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
7680 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
7682 AdvBuildCarrierFreelist(asc_dvc);
7685 * Set-up the Host->RISC Initiator Command Queue (ICQ).
7688 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
7689 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
7692 asc_dvc->carr_freelist = (ADV_CARR_T *)
7693 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
7696 * The first command issued will be placed in the stopper carrier.
7698 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
7701 * Set RISC ICQ physical address start value.
7702 * carr_pa is LE, must be native before write
7704 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
7707 * Set-up the RISC->Host Initiator Response Queue (IRQ).
7709 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
7710 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
7713 asc_dvc->carr_freelist = (ADV_CARR_T *)
7714 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
7717 * The first command completed by the RISC will be placed in
7720 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
7721 * completed the RISC will set the ASC_RQ_STOPPER bit.
7723 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
7726 * Set RISC IRQ physical address start value.
7728 * carr_pa is LE, must be native before write *
7730 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
7731 asc_dvc->carr_pending_cnt = 0;
7733 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
7734 (ADV_INTR_ENABLE_HOST_INTR |
7735 ADV_INTR_ENABLE_GLOBAL_INTR));
7737 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
7738 AdvWriteWordRegister(iop_base, IOPW_PC, word);
7740 /* finally, finally, gentlemen, start your engine */
7741 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
7744 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
7745 * Resets should be performed. The RISC has to be running
7746 * to issue a SCSI Bus Reset.
7748 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
7750 * If the BIOS Signature is present in memory, restore the
7751 * BIOS Handshake Configuration Table and do not perform
7754 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
7757 * Restore per TID negotiated values.
7759 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
7760 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
7761 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
7763 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
7764 AdvWriteByteLram(iop_base,
7765 ASC_MC_NUMBER_OF_MAX_CMD + tid,
7769 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
7770 warn_code = ASC_WARN_BUSRESET_ERROR;
7779 * Initialize the ASC-38C1600.
7781 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
7783 * For a non-fatal error return a warning code. If there are no warnings
7784 * then 0 is returned.
7786 * Needed after initialization for error recovery.
7788 static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc)
7790 AdvPortAddr iop_base;
7800 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
7801 ushort wdtr_able, sdtr_able, ppr_able, tagqng_able;
7802 uchar max_cmd[ASC_MAX_TID + 1];
7804 /* If there is already an error, don't continue. */
7805 if (asc_dvc->err_code != 0) {
7810 * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600.
7812 if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
7813 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
7818 iop_base = asc_dvc->iop_base;
7821 * Save the RISC memory BIOS region before writing the microcode.
7822 * The BIOS may already be loaded and using its RISC LRAM region
7823 * so its region must be saved and restored.
7825 * Note: This code makes the assumption, which is currently true,
7826 * that a chip reset does not clear RISC LRAM.
7828 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
7829 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
7834 * Save current per TID negotiated values.
7836 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
7837 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
7838 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
7839 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
7840 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
7841 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
7846 * RAM BIST (Built-In Self Test)
7848 * Address : I/O base + offset 0x38h register (byte).
7849 * Function: Bit 7-6(RW) : RAM mode
7850 * Normal Mode : 0x00
7851 * Pre-test Mode : 0x40
7852 * RAM Test Mode : 0x80
7854 * Bit 4(RO) : Done bit
7855 * Bit 3-0(RO) : Status
7857 * Int_RAM Error : 0x04
7862 * Note: RAM BIST code should be put right here, before loading the
7863 * microcode and after saving the RISC memory BIOS region.
7869 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
7870 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
7871 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
7872 * to NORMAL_MODE, return an error too.
7874 for (i = 0; i < 2; i++) {
7875 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
7876 mdelay(10); /* Wait for 10ms before reading back. */
7877 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
7878 if ((byte & RAM_TEST_DONE) == 0
7879 || (byte & 0x0F) != PRE_TEST_VALUE) {
7880 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
7884 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
7885 mdelay(10); /* Wait for 10ms before reading back. */
7886 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
7888 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
7894 * LRAM Test - It takes about 1.5 ms to run through the test.
7896 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
7897 * If Done bit not set or Status not 0, save register byte, set the
7898 * err_code, and return an error.
7900 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
7901 mdelay(10); /* Wait for 10ms before checking status. */
7903 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
7904 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
7905 /* Get here if Done bit not set or Status not 0. */
7906 asc_dvc->bist_err_code = byte; /* for BIOS display message */
7907 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
7911 /* We need to reset back to normal mode after LRAM test passes. */
7912 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
7914 asc_dvc->err_code = AdvLoadMicrocode(iop_base, _adv_asc38C1600_buf,
7915 _adv_asc38C1600_size, ADV_38C1600_MEMSIZE,
7916 _adv_asc38C1600_chksum);
7917 if (asc_dvc->err_code)
7921 * Restore the RISC memory BIOS region.
7923 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
7924 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
7929 * Calculate and write the microcode code checksum to the microcode
7930 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
7932 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
7933 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
7935 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
7936 for (word = begin_addr; word < end_addr; word += 2) {
7937 code_sum += AdvReadWordAutoIncLram(iop_base);
7939 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
7942 * Read microcode version and date.
7944 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
7945 asc_dvc->cfg->mcode_date);
7946 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
7947 asc_dvc->cfg->mcode_version);
7950 * Set the chip type to indicate the ASC38C1600.
7952 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600);
7955 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
7956 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
7957 * cable detection and then we are able to read C_DET[3:0].
7959 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
7960 * Microcode Default Value' section below.
7962 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
7963 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
7964 scsi_cfg1 | DIS_TERM_DRV);
7967 * If the PCI Configuration Command Register "Parity Error Response
7968 * Control" Bit was clear (0), then set the microcode variable
7969 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
7970 * to ignore DMA parity errors.
7972 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
7973 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7974 word |= CONTROL_FLAG_IGNORE_PERR;
7975 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7979 * If the BIOS control flag AIPP (Asynchronous Information
7980 * Phase Protection) disable bit is not set, then set the firmware
7981 * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable
7982 * AIPP checking and encoding.
7984 if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) {
7985 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7986 word |= CONTROL_FLAG_ENABLE_AIPP;
7987 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7991 * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4],
7992 * and START_CTL_TH [3:2].
7994 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
7995 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
7998 * Microcode operating variables for WDTR, SDTR, and command tag
7999 * queuing will be set in slave_configure() based on what a
8000 * device reports it is capable of in Inquiry byte 7.
8002 * If SCSI Bus Resets have been disabled, then directly set
8003 * SDTR and WDTR from the EEPROM configuration. This will allow
8004 * the BIOS and warm boot to work without a SCSI bus hang on
8005 * the Inquiry caused by host and target mismatched DTR values.
8006 * Without the SCSI Bus Reset, before an Inquiry a device can't
8007 * be assumed to be in Asynchronous, Narrow mode.
8009 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
8010 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
8011 asc_dvc->wdtr_able);
8012 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
8013 asc_dvc->sdtr_able);
8017 * Set microcode operating variables for DISC and SDTR_SPEED1,
8018 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
8019 * configuration values.
8021 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
8022 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
8023 * without determining here whether the device supports SDTR.
8025 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
8026 asc_dvc->cfg->disc_enable);
8027 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
8028 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
8029 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
8030 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
8033 * Set SCSI_CFG0 Microcode Default Value.
8035 * The microcode will set the SCSI_CFG0 register using this value
8036 * after it is started below.
8038 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
8039 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
8040 asc_dvc->chip_scsi_id);
8043 * Calculate SCSI_CFG1 Microcode Default Value.
8045 * The microcode will set the SCSI_CFG1 register using this value
8046 * after it is started below.
8048 * Each ASC-38C1600 function has only two cable detect bits.
8049 * The bus mode override bits are in IOPB_SOFT_OVER_WR.
8051 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
8054 * If the cable is reversed all of the SCSI_CTRL register signals
8055 * will be set. Check for and return an error if this condition is
8058 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
8059 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
8064 * Each ASC-38C1600 function has two connectors. Only an HVD device
8065 * can not be connected to either connector. An LVD device or SE device
8066 * may be connected to either connecor. If an SE device is connected,
8067 * then at most Ultra speed (20 Mhz) can be used on both connectors.
8069 * If an HVD device is attached, return an error.
8071 if (scsi_cfg1 & HVD) {
8072 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
8077 * Each function in the ASC-38C1600 uses only the SE cable detect and
8078 * termination because there are two connectors for each function. Each
8079 * function may use either LVD or SE mode. Corresponding the SE automatic
8080 * termination control EEPROM bits are used for each function. Each
8081 * function has its own EEPROM. If SE automatic control is enabled for
8082 * the function, then set the termination value based on a table listed
8085 * If manual termination is specified in the EEPROM for the function,
8086 * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is
8087 * ready to be 'ored' into SCSI_CFG1.
8089 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
8090 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
8091 /* SE automatic termination control is enabled. */
8092 switch (scsi_cfg1 & C_DET_SE) {
8093 /* TERM_SE_HI: on, TERM_SE_LO: on */
8097 asc_dvc->cfg->termination |= TERM_SE;
8101 if (PCI_FUNC(pdev->devfn) == 0) {
8102 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
8104 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
8105 asc_dvc->cfg->termination |= TERM_SE_HI;
8112 * Clear any set TERM_SE bits.
8114 scsi_cfg1 &= ~TERM_SE;
8117 * Invert the TERM_SE bits and then set 'scsi_cfg1'.
8119 scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE);
8122 * Clear Big Endian and Terminator Polarity bits and set possibly
8123 * modified termination control bits in the Microcode SCSI_CFG1
8126 * Big Endian bit is not used even on big endian machines.
8128 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL);
8131 * Set SCSI_CFG1 Microcode Default Value
8133 * Set possibly modified termination control bits in the Microcode
8134 * SCSI_CFG1 Register Value.
8136 * The microcode will set the SCSI_CFG1 register using this value
8137 * after it is started below.
8139 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
8142 * Set MEM_CFG Microcode Default Value
8144 * The microcode will set the MEM_CFG register using this value
8145 * after it is started below.
8147 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
8150 * ASC-38C1600 has 32KB internal memory.
8152 * XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come
8153 * out a special 16K Adv Library and Microcode version. After the issue
8154 * resolved, we should turn back to the 32K support. Both a_condor.h and
8155 * mcode.sas files also need to be updated.
8157 * AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
8158 * BIOS_EN | RAM_SZ_32KB);
8160 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
8161 BIOS_EN | RAM_SZ_16KB);
8164 * Set SEL_MASK Microcode Default Value
8166 * The microcode will set the SEL_MASK register using this value
8167 * after it is started below.
8169 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
8170 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
8172 AdvBuildCarrierFreelist(asc_dvc);
8175 * Set-up the Host->RISC Initiator Command Queue (ICQ).
8177 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
8178 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
8181 asc_dvc->carr_freelist = (ADV_CARR_T *)
8182 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
8185 * The first command issued will be placed in the stopper carrier.
8187 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
8190 * Set RISC ICQ physical address start value. Initialize the
8191 * COMMA register to the same value otherwise the RISC will
8192 * prematurely detect a command is available.
8194 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
8195 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
8196 le32_to_cpu(asc_dvc->icq_sp->carr_pa));
8199 * Set-up the RISC->Host Initiator Response Queue (IRQ).
8201 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
8202 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
8205 asc_dvc->carr_freelist = (ADV_CARR_T *)
8206 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
8209 * The first command completed by the RISC will be placed in
8212 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
8213 * completed the RISC will set the ASC_RQ_STOPPER bit.
8215 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
8218 * Set RISC IRQ physical address start value.
8220 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
8221 asc_dvc->carr_pending_cnt = 0;
8223 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
8224 (ADV_INTR_ENABLE_HOST_INTR |
8225 ADV_INTR_ENABLE_GLOBAL_INTR));
8226 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
8227 AdvWriteWordRegister(iop_base, IOPW_PC, word);
8229 /* finally, finally, gentlemen, start your engine */
8230 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
8233 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
8234 * Resets should be performed. The RISC has to be running
8235 * to issue a SCSI Bus Reset.
8237 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
8239 * If the BIOS Signature is present in memory, restore the
8240 * per TID microcode operating variables.
8242 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
8245 * Restore per TID negotiated values.
8247 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
8248 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
8249 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
8250 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
8252 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
8253 AdvWriteByteLram(iop_base,
8254 ASC_MC_NUMBER_OF_MAX_CMD + tid,
8258 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
8259 warn_code = ASC_WARN_BUSRESET_ERROR;
8268 * Reset chip and SCSI Bus.
8271 * ADV_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful.
8272 * ADV_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure.
8274 static int AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc)
8277 ushort wdtr_able, sdtr_able, tagqng_able;
8278 ushort ppr_able = 0;
8279 uchar tid, max_cmd[ADV_MAX_TID + 1];
8280 AdvPortAddr iop_base;
8283 iop_base = asc_dvc->iop_base;
8286 * Save current per TID negotiated values.
8288 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
8289 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
8290 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
8291 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
8293 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
8294 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
8295 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
8300 * Force the AdvInitAsc3550/38C0800Driver() function to
8301 * perform a SCSI Bus Reset by clearing the BIOS signature word.
8302 * The initialization functions assumes a SCSI Bus Reset is not
8303 * needed if the BIOS signature word is present.
8305 AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
8306 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0);
8309 * Stop chip and reset it.
8311 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP);
8312 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET);
8314 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
8315 ADV_CTRL_REG_CMD_WR_IO_REG);
8318 * Reset Adv Library error code, if any, and try
8319 * re-initializing the chip.
8321 asc_dvc->err_code = 0;
8322 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
8323 status = AdvInitAsc38C1600Driver(asc_dvc);
8324 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
8325 status = AdvInitAsc38C0800Driver(asc_dvc);
8327 status = AdvInitAsc3550Driver(asc_dvc);
8330 /* Translate initialization return value to status value. */
8338 * Restore the BIOS signature word.
8340 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
8343 * Restore per TID negotiated values.
8345 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
8346 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
8347 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
8348 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
8350 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
8351 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
8352 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
8360 * adv_async_callback() - Adv Library asynchronous event callback function.
8362 static void adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code)
8365 case ADV_ASYNC_SCSI_BUS_RESET_DET:
8367 * The firmware detected a SCSI Bus reset.
8370 "adv_async_callback: ADV_ASYNC_SCSI_BUS_RESET_DET\n");
8373 case ADV_ASYNC_RDMA_FAILURE:
8375 * Handle RDMA failure by resetting the SCSI Bus and
8376 * possibly the chip if it is unresponsive. Log the error
8377 * with a unique code.
8379 ASC_DBG(0, "adv_async_callback: ADV_ASYNC_RDMA_FAILURE\n");
8380 AdvResetChipAndSB(adv_dvc_varp);
8383 case ADV_HOST_SCSI_BUS_RESET:
8385 * Host generated SCSI bus reset occurred.
8387 ASC_DBG(0, "adv_async_callback: ADV_HOST_SCSI_BUS_RESET\n");
8391 ASC_DBG1(0, "DvcAsyncCallBack: unknown code 0x%x\n", code);
8397 * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR().
8399 * Callback function for the Wide SCSI Adv Library.
8401 static void adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp)
8403 asc_board_t *boardp;
8405 adv_sgblk_t *sgblkp;
8406 struct scsi_cmnd *scp;
8407 struct Scsi_Host *shost;
8410 ASC_DBG2(1, "adv_isr_callback: adv_dvc_varp 0x%lx, scsiqp 0x%lx\n",
8411 (ulong)adv_dvc_varp, (ulong)scsiqp);
8412 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
8415 * Get the adv_req_t structure for the command that has been
8416 * completed. The adv_req_t structure actually contains the
8417 * completed ADV_SCSI_REQ_Q structure.
8419 reqp = (adv_req_t *)ADV_U32_TO_VADDR(scsiqp->srb_ptr);
8420 ASC_DBG1(1, "adv_isr_callback: reqp 0x%lx\n", (ulong)reqp);
8422 ASC_PRINT("adv_isr_callback: reqp is NULL\n");
8427 * Get the struct scsi_cmnd structure and Scsi_Host structure for the
8428 * command that has been completed.
8430 * Note: The adv_req_t request structure and adv_sgblk_t structure,
8431 * if any, are dropped, because a board structure pointer can not be
8435 ASC_DBG1(1, "adv_isr_callback: scp 0x%lx\n", (ulong)scp);
8438 ("adv_isr_callback: scp is NULL; adv_req_t dropped.\n");
8441 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
8443 shost = scp->device->host;
8444 ASC_STATS(shost, callback);
8445 ASC_DBG1(1, "adv_isr_callback: shost 0x%lx\n", (ulong)shost);
8447 boardp = ASC_BOARDP(shost);
8448 BUG_ON(adv_dvc_varp != &boardp->dvc_var.adv_dvc_var);
8451 * 'done_status' contains the command's ending status.
8453 switch (scsiqp->done_status) {
8455 ASC_DBG(2, "adv_isr_callback: QD_NO_ERROR\n");
8459 * Check for an underrun condition.
8461 * If there was no error and an underrun condition, then
8462 * then return the number of underrun bytes.
8464 resid_cnt = le32_to_cpu(scsiqp->data_cnt);
8465 if (scp->request_bufflen != 0 && resid_cnt != 0 &&
8466 resid_cnt <= scp->request_bufflen) {
8468 "adv_isr_callback: underrun condition %lu bytes\n",
8470 scp->resid = resid_cnt;
8475 ASC_DBG(2, "adv_isr_callback: QD_WITH_ERROR\n");
8476 switch (scsiqp->host_status) {
8477 case QHSTA_NO_ERROR:
8478 if (scsiqp->scsi_status == SAM_STAT_CHECK_CONDITION) {
8480 "adv_isr_callback: SAM_STAT_CHECK_CONDITION\n");
8481 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
8482 sizeof(scp->sense_buffer));
8484 * Note: The 'status_byte()' macro used by
8485 * target drivers defined in scsi.h shifts the
8486 * status byte returned by host drivers right
8487 * by 1 bit. This is why target drivers also
8488 * use right shifted status byte definitions.
8489 * For instance target drivers use
8490 * CHECK_CONDITION, defined to 0x1, instead of
8491 * the SCSI defined check condition value of
8492 * 0x2. Host drivers are supposed to return
8493 * the status byte as it is defined by SCSI.
8495 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
8496 STATUS_BYTE(scsiqp->scsi_status);
8498 scp->result = STATUS_BYTE(scsiqp->scsi_status);
8503 /* Some other QHSTA error occurred. */
8504 ASC_DBG1(1, "adv_isr_callback: host_status 0x%x\n",
8505 scsiqp->host_status);
8506 scp->result = HOST_BYTE(DID_BAD_TARGET);
8511 case QD_ABORTED_BY_HOST:
8512 ASC_DBG(1, "adv_isr_callback: QD_ABORTED_BY_HOST\n");
8514 HOST_BYTE(DID_ABORT) | STATUS_BYTE(scsiqp->scsi_status);
8518 ASC_DBG1(1, "adv_isr_callback: done_status 0x%x\n",
8519 scsiqp->done_status);
8521 HOST_BYTE(DID_ERROR) | STATUS_BYTE(scsiqp->scsi_status);
8526 * If the 'init_tidmask' bit isn't already set for the target and the
8527 * current request finished normally, then set the bit for the target
8528 * to indicate that a device is present.
8530 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
8531 scsiqp->done_status == QD_NO_ERROR &&
8532 scsiqp->host_status == QHSTA_NO_ERROR) {
8533 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
8539 * Free all 'adv_sgblk_t' structures allocated for the request.
8541 while ((sgblkp = reqp->sgblkp) != NULL) {
8542 /* Remove 'sgblkp' from the request list. */
8543 reqp->sgblkp = sgblkp->next_sgblkp;
8545 /* Add 'sgblkp' to the board free list. */
8546 sgblkp->next_sgblkp = boardp->adv_sgblkp;
8547 boardp->adv_sgblkp = sgblkp;
8551 * Free the adv_req_t structure used with the command by adding
8552 * it back to the board free list.
8554 reqp->next_reqp = boardp->adv_reqp;
8555 boardp->adv_reqp = reqp;
8557 ASC_DBG(1, "adv_isr_callback: done\n");
8563 * Adv Library Interrupt Service Routine
8565 * This function is called by a driver's interrupt service routine.
8566 * The function disables and re-enables interrupts.
8568 * When a microcode idle command is completed, the ADV_DVC_VAR
8569 * 'idle_cmd_done' field is set to ADV_TRUE.
8571 * Note: AdvISR() can be called when interrupts are disabled or even
8572 * when there is no hardware interrupt condition present. It will
8573 * always check for completed idle commands and microcode requests.
8574 * This is an important feature that shouldn't be changed because it
8575 * allows commands to be completed from polling mode loops.
8578 * ADV_TRUE(1) - interrupt was pending
8579 * ADV_FALSE(0) - no interrupt was pending
8581 static int AdvISR(ADV_DVC_VAR *asc_dvc)
8583 AdvPortAddr iop_base;
8586 ADV_CARR_T *free_carrp;
8587 ADV_VADDR irq_next_vpa;
8588 ADV_SCSI_REQ_Q *scsiq;
8590 iop_base = asc_dvc->iop_base;
8592 /* Reading the register clears the interrupt. */
8593 int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG);
8595 if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB |
8596 ADV_INTR_STATUS_INTRC)) == 0) {
8601 * Notify the driver of an asynchronous microcode condition by
8602 * calling the adv_async_callback function. The function
8603 * is passed the microcode ASC_MC_INTRB_CODE byte value.
8605 if (int_stat & ADV_INTR_STATUS_INTRB) {
8608 AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code);
8610 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
8611 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
8612 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE &&
8613 asc_dvc->carr_pending_cnt != 0) {
8614 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
8616 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
8617 AdvWriteByteRegister(iop_base,
8624 adv_async_callback(asc_dvc, intrb_code);
8628 * Check if the IRQ stopper carrier contains a completed request.
8630 while (((irq_next_vpa =
8631 le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ASC_RQ_DONE) != 0) {
8633 * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure.
8634 * The RISC will have set 'areq_vpa' to a virtual address.
8636 * The firmware will have copied the ASC_SCSI_REQ_Q.scsiq_ptr
8637 * field to the carrier ADV_CARR_T.areq_vpa field. The conversion
8638 * below complements the conversion of ASC_SCSI_REQ_Q.scsiq_ptr'
8639 * in AdvExeScsiQueue().
8641 scsiq = (ADV_SCSI_REQ_Q *)
8642 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->areq_vpa));
8645 * Request finished with good status and the queue was not
8646 * DMAed to host memory by the firmware. Set all status fields
8647 * to indicate good status.
8649 if ((irq_next_vpa & ASC_RQ_GOOD) != 0) {
8650 scsiq->done_status = QD_NO_ERROR;
8651 scsiq->host_status = scsiq->scsi_status = 0;
8652 scsiq->data_cnt = 0L;
8656 * Advance the stopper pointer to the next carrier
8657 * ignoring the lower four bits. Free the previous
8660 free_carrp = asc_dvc->irq_sp;
8661 asc_dvc->irq_sp = (ADV_CARR_T *)
8662 ADV_U32_TO_VADDR(ASC_GET_CARRP(irq_next_vpa));
8664 free_carrp->next_vpa =
8665 cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
8666 asc_dvc->carr_freelist = free_carrp;
8667 asc_dvc->carr_pending_cnt--;
8669 target_bit = ADV_TID_TO_TIDMASK(scsiq->target_id);
8672 * Clear request microcode control flag.
8677 * Notify the driver of the completed request by passing
8678 * the ADV_SCSI_REQ_Q pointer to its callback function.
8680 scsiq->a_flag |= ADV_SCSIQ_DONE;
8681 adv_isr_callback(asc_dvc, scsiq);
8683 * Note: After the driver callback function is called, 'scsiq'
8684 * can no longer be referenced.
8686 * Fall through and continue processing other completed
8693 static int AscSetLibErrorCode(ASC_DVC_VAR *asc_dvc, ushort err_code)
8695 if (asc_dvc->err_code == 0) {
8696 asc_dvc->err_code = err_code;
8697 AscWriteLramWord(asc_dvc->iop_base, ASCV_ASCDVC_ERR_CODE_W,
8703 static void AscAckInterrupt(PortAddr iop_base)
8711 risc_flag = AscReadLramByte(iop_base, ASCV_RISC_FLAG_B);
8712 if (loop++ > 0x7FFF) {
8715 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0);
8717 AscReadLramByte(iop_base,
8718 ASCV_HOST_FLAG_B) & (~ASC_HOST_FLAG_ACK_INT);
8719 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
8720 (uchar)(host_flag | ASC_HOST_FLAG_ACK_INT));
8721 AscSetChipStatus(iop_base, CIW_INT_ACK);
8723 while (AscGetChipStatus(iop_base) & CSW_INT_PENDING) {
8724 AscSetChipStatus(iop_base, CIW_INT_ACK);
8729 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
8733 static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *asc_dvc, uchar syn_time)
8735 uchar *period_table;
8740 period_table = asc_dvc->sdtr_period_tbl;
8741 max_index = (int)asc_dvc->max_sdtr_index;
8742 min_index = (int)asc_dvc->host_init_sdtr_index;
8743 if ((syn_time <= period_table[max_index])) {
8744 for (i = min_index; i < (max_index - 1); i++) {
8745 if (syn_time <= period_table[i]) {
8749 return (uchar)max_index;
8751 return (uchar)(max_index + 1);
8756 AscMsgOutSDTR(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar sdtr_offset)
8759 uchar sdtr_period_index;
8762 iop_base = asc_dvc->iop_base;
8763 sdtr_buf.msg_type = EXTENDED_MESSAGE;
8764 sdtr_buf.msg_len = MS_SDTR_LEN;
8765 sdtr_buf.msg_req = EXTENDED_SDTR;
8766 sdtr_buf.xfer_period = sdtr_period;
8767 sdtr_offset &= ASC_SYN_MAX_OFFSET;
8768 sdtr_buf.req_ack_offset = sdtr_offset;
8769 sdtr_period_index = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
8770 if (sdtr_period_index <= asc_dvc->max_sdtr_index) {
8771 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
8773 sizeof(EXT_MSG) >> 1);
8774 return ((sdtr_period_index << 4) | sdtr_offset);
8776 sdtr_buf.req_ack_offset = 0;
8777 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
8779 sizeof(EXT_MSG) >> 1);
8785 AscCalSDTRData(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar syn_offset)
8788 uchar sdtr_period_ix;
8790 sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
8791 if (sdtr_period_ix > asc_dvc->max_sdtr_index) {
8794 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
8798 static int AscSetChipSynRegAtID(PortAddr iop_base, uchar id, uchar sdtr_data)
8800 ASC_SCSI_BIT_ID_TYPE org_id;
8804 AscSetBank(iop_base, 1);
8805 org_id = AscReadChipDvcID(iop_base);
8806 for (i = 0; i <= ASC_MAX_TID; i++) {
8807 if (org_id == (0x01 << i))
8810 org_id = (ASC_SCSI_BIT_ID_TYPE) i;
8811 AscWriteChipDvcID(iop_base, id);
8812 if (AscReadChipDvcID(iop_base) == (0x01 << id)) {
8813 AscSetBank(iop_base, 0);
8814 AscSetChipSyn(iop_base, sdtr_data);
8815 if (AscGetChipSyn(iop_base) != sdtr_data) {
8821 AscSetBank(iop_base, 1);
8822 AscWriteChipDvcID(iop_base, org_id);
8823 AscSetBank(iop_base, 0);
8827 static void AscSetChipSDTR(PortAddr iop_base, uchar sdtr_data, uchar tid_no)
8829 AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
8830 AscPutMCodeSDTRDoneAtID(iop_base, tid_no, sdtr_data);
8833 static int AscIsrChipHalted(ASC_DVC_VAR *asc_dvc)
8839 ushort int_halt_code;
8840 ASC_SCSI_BIT_ID_TYPE scsi_busy;
8841 ASC_SCSI_BIT_ID_TYPE target_id;
8848 uchar q_cntl, tid_no;
8852 asc_board_t *boardp;
8854 BUG_ON(!asc_dvc->drv_ptr);
8855 boardp = asc_dvc->drv_ptr;
8857 iop_base = asc_dvc->iop_base;
8858 int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W);
8860 halt_qp = AscReadLramByte(iop_base, ASCV_CURCDB_B);
8861 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp);
8862 target_ix = AscReadLramByte(iop_base,
8863 (ushort)(halt_q_addr +
8864 (ushort)ASC_SCSIQ_B_TARGET_IX));
8865 q_cntl = AscReadLramByte(iop_base,
8866 (ushort)(halt_q_addr + (ushort)ASC_SCSIQ_B_CNTL));
8867 tid_no = ASC_TIX_TO_TID(target_ix);
8868 target_id = (uchar)ASC_TID_TO_TARGET_ID(tid_no);
8869 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
8870 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB;
8874 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) {
8875 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
8876 AscSetChipSDTR(iop_base, 0, tid_no);
8877 boardp->sdtr_data[tid_no] = 0;
8879 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8881 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) {
8882 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
8883 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
8884 boardp->sdtr_data[tid_no] = asyn_sdtr;
8886 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8888 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) {
8889 AscMemWordCopyPtrFromLram(iop_base,
8892 sizeof(EXT_MSG) >> 1);
8894 if (ext_msg.msg_type == EXTENDED_MESSAGE &&
8895 ext_msg.msg_req == EXTENDED_SDTR &&
8896 ext_msg.msg_len == MS_SDTR_LEN) {
8898 if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) {
8900 sdtr_accept = FALSE;
8901 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
8903 if ((ext_msg.xfer_period <
8904 asc_dvc->sdtr_period_tbl[asc_dvc->
8905 host_init_sdtr_index])
8906 || (ext_msg.xfer_period >
8907 asc_dvc->sdtr_period_tbl[asc_dvc->
8909 sdtr_accept = FALSE;
8910 ext_msg.xfer_period =
8911 asc_dvc->sdtr_period_tbl[asc_dvc->
8912 host_init_sdtr_index];
8916 AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
8917 ext_msg.req_ack_offset);
8918 if ((sdtr_data == 0xFF)) {
8920 q_cntl |= QC_MSG_OUT;
8921 asc_dvc->init_sdtr &= ~target_id;
8922 asc_dvc->sdtr_done &= ~target_id;
8923 AscSetChipSDTR(iop_base, asyn_sdtr,
8925 boardp->sdtr_data[tid_no] = asyn_sdtr;
8928 if (ext_msg.req_ack_offset == 0) {
8930 q_cntl &= ~QC_MSG_OUT;
8931 asc_dvc->init_sdtr &= ~target_id;
8932 asc_dvc->sdtr_done &= ~target_id;
8933 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
8935 if (sdtr_accept && (q_cntl & QC_MSG_OUT)) {
8937 q_cntl &= ~QC_MSG_OUT;
8938 asc_dvc->sdtr_done |= target_id;
8939 asc_dvc->init_sdtr |= target_id;
8940 asc_dvc->pci_fix_asyn_xfer &=
8943 AscCalSDTRData(asc_dvc,
8944 ext_msg.xfer_period,
8947 AscSetChipSDTR(iop_base, sdtr_data,
8949 boardp->sdtr_data[tid_no] = sdtr_data;
8952 q_cntl |= QC_MSG_OUT;
8953 AscMsgOutSDTR(asc_dvc,
8954 ext_msg.xfer_period,
8955 ext_msg.req_ack_offset);
8956 asc_dvc->pci_fix_asyn_xfer &=
8959 AscCalSDTRData(asc_dvc,
8960 ext_msg.xfer_period,
8963 AscSetChipSDTR(iop_base, sdtr_data,
8965 boardp->sdtr_data[tid_no] = sdtr_data;
8966 asc_dvc->sdtr_done |= target_id;
8967 asc_dvc->init_sdtr |= target_id;
8971 AscWriteLramByte(iop_base,
8972 (ushort)(halt_q_addr +
8973 (ushort)ASC_SCSIQ_B_CNTL),
8975 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8977 } else if (ext_msg.msg_type == EXTENDED_MESSAGE &&
8978 ext_msg.msg_req == EXTENDED_WDTR &&
8979 ext_msg.msg_len == MS_WDTR_LEN) {
8981 ext_msg.wdtr_width = 0;
8982 AscMemWordCopyPtrToLram(iop_base,
8985 sizeof(EXT_MSG) >> 1);
8986 q_cntl |= QC_MSG_OUT;
8987 AscWriteLramByte(iop_base,
8988 (ushort)(halt_q_addr +
8989 (ushort)ASC_SCSIQ_B_CNTL),
8991 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8995 ext_msg.msg_type = MESSAGE_REJECT;
8996 AscMemWordCopyPtrToLram(iop_base,
8999 sizeof(EXT_MSG) >> 1);
9000 q_cntl |= QC_MSG_OUT;
9001 AscWriteLramByte(iop_base,
9002 (ushort)(halt_q_addr +
9003 (ushort)ASC_SCSIQ_B_CNTL),
9005 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
9008 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) {
9010 q_cntl |= QC_REQ_SENSE;
9012 if ((asc_dvc->init_sdtr & target_id) != 0) {
9014 asc_dvc->sdtr_done &= ~target_id;
9016 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
9017 q_cntl |= QC_MSG_OUT;
9018 AscMsgOutSDTR(asc_dvc,
9020 sdtr_period_tbl[(sdtr_data >> 4) &
9024 (uchar)(sdtr_data & (uchar)
9025 ASC_SYN_MAX_OFFSET));
9028 AscWriteLramByte(iop_base,
9029 (ushort)(halt_q_addr +
9030 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
9032 tag_code = AscReadLramByte(iop_base,
9033 (ushort)(halt_q_addr + (ushort)
9034 ASC_SCSIQ_B_TAG_CODE));
9036 if ((asc_dvc->pci_fix_asyn_xfer & target_id)
9037 && !(asc_dvc->pci_fix_asyn_xfer_always & target_id)
9040 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT
9041 | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX);
9044 AscWriteLramByte(iop_base,
9045 (ushort)(halt_q_addr +
9046 (ushort)ASC_SCSIQ_B_TAG_CODE),
9049 q_status = AscReadLramByte(iop_base,
9050 (ushort)(halt_q_addr + (ushort)
9051 ASC_SCSIQ_B_STATUS));
9052 q_status |= (QS_READY | QS_BUSY);
9053 AscWriteLramByte(iop_base,
9054 (ushort)(halt_q_addr +
9055 (ushort)ASC_SCSIQ_B_STATUS),
9058 scsi_busy = AscReadLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B);
9059 scsi_busy &= ~target_id;
9060 AscWriteLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B, scsi_busy);
9062 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
9064 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) {
9066 AscMemWordCopyPtrFromLram(iop_base,
9069 sizeof(EXT_MSG) >> 1);
9071 if ((out_msg.msg_type == EXTENDED_MESSAGE) &&
9072 (out_msg.msg_len == MS_SDTR_LEN) &&
9073 (out_msg.msg_req == EXTENDED_SDTR)) {
9075 asc_dvc->init_sdtr &= ~target_id;
9076 asc_dvc->sdtr_done &= ~target_id;
9077 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
9078 boardp->sdtr_data[tid_no] = asyn_sdtr;
9080 q_cntl &= ~QC_MSG_OUT;
9081 AscWriteLramByte(iop_base,
9082 (ushort)(halt_q_addr +
9083 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
9084 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
9086 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) {
9088 scsi_status = AscReadLramByte(iop_base,
9089 (ushort)((ushort)halt_q_addr +
9091 ASC_SCSIQ_SCSI_STATUS));
9093 AscReadLramByte(iop_base,
9094 (ushort)((ushort)ASC_QADR_BEG +
9095 (ushort)target_ix));
9096 if ((cur_dvc_qng > 0) && (asc_dvc->cur_dvc_qng[tid_no] > 0)) {
9098 scsi_busy = AscReadLramByte(iop_base,
9099 (ushort)ASCV_SCSIBUSY_B);
9100 scsi_busy |= target_id;
9101 AscWriteLramByte(iop_base,
9102 (ushort)ASCV_SCSIBUSY_B, scsi_busy);
9103 asc_dvc->queue_full_or_busy |= target_id;
9105 if (scsi_status == SAM_STAT_TASK_SET_FULL) {
9106 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) {
9108 asc_dvc->max_dvc_qng[tid_no] =
9111 AscWriteLramByte(iop_base,
9113 ASCV_MAX_DVC_QNG_BEG
9119 * Set the device queue depth to the
9120 * number of active requests when the
9121 * QUEUE FULL condition was encountered.
9123 boardp->queue_full |= target_id;
9124 boardp->queue_full_cnt[tid_no] =
9129 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
9132 #if CC_VERY_LONG_SG_LIST
9133 else if (int_halt_code == ASC_HALT_HOST_COPY_SG_LIST_TO_RISC) {
9137 uchar first_sg_wk_q_no;
9138 ASC_SCSI_Q *scsiq; /* Ptr to driver request. */
9139 ASC_SG_HEAD *sg_head; /* Ptr to driver SG request. */
9140 ASC_SG_LIST_Q scsi_sg_q; /* Structure written to queue. */
9141 ushort sg_list_dwords;
9142 ushort sg_entry_cnt;
9146 q_no = AscReadLramByte(iop_base, (ushort)ASCV_REQ_SG_LIST_QP);
9147 if (q_no == ASC_QLINK_END)
9150 q_addr = ASC_QNO_TO_QADDR(q_no);
9153 * Convert the request's SRB pointer to a host ASC_SCSI_REQ
9154 * structure pointer using a macro provided by the driver.
9155 * The ASC_SCSI_REQ pointer provides a pointer to the
9156 * host ASC_SG_HEAD structure.
9158 /* Read request's SRB pointer. */
9159 scsiq = (ASC_SCSI_Q *)
9160 ASC_SRB2SCSIQ(ASC_U32_TO_VADDR(AscReadLramDWord(iop_base,
9163 ASC_SCSIQ_D_SRBPTR))));
9166 * Get request's first and working SG queue.
9168 sg_wk_q_no = AscReadLramByte(iop_base,
9170 ASC_SCSIQ_B_SG_WK_QP));
9172 first_sg_wk_q_no = AscReadLramByte(iop_base,
9174 ASC_SCSIQ_B_FIRST_SG_WK_QP));
9177 * Reset request's working SG queue back to the
9180 AscWriteLramByte(iop_base,
9182 (ushort)ASC_SCSIQ_B_SG_WK_QP),
9185 sg_head = scsiq->sg_head;
9188 * Set sg_entry_cnt to the number of SG elements
9189 * that will be completed on this interrupt.
9191 * Note: The allocated SG queues contain ASC_MAX_SG_LIST - 1
9192 * SG elements. The data_cnt and data_addr fields which
9193 * add 1 to the SG element capacity are not used when
9194 * restarting SG handling after a halt.
9196 if (scsiq->remain_sg_entry_cnt > (ASC_MAX_SG_LIST - 1)) {
9197 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
9200 * Keep track of remaining number of SG elements that
9201 * will need to be handled on the next interrupt.
9203 scsiq->remain_sg_entry_cnt -= (ASC_MAX_SG_LIST - 1);
9205 sg_entry_cnt = scsiq->remain_sg_entry_cnt;
9206 scsiq->remain_sg_entry_cnt = 0;
9210 * Copy SG elements into the list of allocated SG queues.
9212 * Last index completed is saved in scsiq->next_sg_index.
9214 next_qp = first_sg_wk_q_no;
9215 q_addr = ASC_QNO_TO_QADDR(next_qp);
9216 scsi_sg_q.sg_head_qp = q_no;
9217 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
9218 for (i = 0; i < sg_head->queue_cnt; i++) {
9219 scsi_sg_q.seq_no = i + 1;
9220 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
9221 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
9222 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
9224 * After very first SG queue RISC FW uses next
9225 * SG queue first element then checks sg_list_cnt
9226 * against zero and then decrements, so set
9227 * sg_list_cnt 1 less than number of SG elements
9230 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1;
9231 scsi_sg_q.sg_cur_list_cnt =
9232 ASC_SG_LIST_PER_Q - 1;
9235 * This is the last SG queue in the list of
9236 * allocated SG queues. If there are more
9237 * SG elements than will fit in the allocated
9238 * queues, then set the QCSG_SG_XFER_MORE flag.
9240 if (scsiq->remain_sg_entry_cnt != 0) {
9241 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
9243 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
9245 /* equals sg_entry_cnt * 2 */
9246 sg_list_dwords = sg_entry_cnt << 1;
9247 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1;
9248 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1;
9252 scsi_sg_q.q_no = next_qp;
9253 AscMemWordCopyPtrToLram(iop_base,
9254 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
9255 (uchar *)&scsi_sg_q,
9256 sizeof(ASC_SG_LIST_Q) >> 1);
9258 AscMemDWordCopyPtrToLram(iop_base,
9259 q_addr + ASC_SGQ_LIST_BEG,
9261 sg_list[scsiq->next_sg_index],
9264 scsiq->next_sg_index += ASC_SG_LIST_PER_Q;
9267 * If the just completed SG queue contained the
9268 * last SG element, then no more SG queues need
9271 if (scsi_sg_q.cntl & QCSG_SG_XFER_END) {
9275 next_qp = AscReadLramByte(iop_base,
9278 q_addr = ASC_QNO_TO_QADDR(next_qp);
9282 * Clear the halt condition so the RISC will be restarted
9285 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
9288 #endif /* CC_VERY_LONG_SG_LIST */
9294 * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
9296 * Calling/Exit State:
9300 * Input an ASC_QDONE_INFO structure from the chip
9303 DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
9308 AscSetChipLramAddr(iop_base, s_addr);
9309 for (i = 0; i < 2 * words; i += 2) {
9313 word = inpw(iop_base + IOP_RAM_DATA);
9314 inbuf[i] = word & 0xff;
9315 inbuf[i + 1] = (word >> 8) & 0xff;
9317 ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf, 2 * words);
9321 _AscCopyLramScsiDoneQ(PortAddr iop_base,
9323 ASC_QDONE_INFO *scsiq, ASC_DCNT max_dma_count)
9328 DvcGetQinfo(iop_base,
9329 q_addr + ASC_SCSIQ_DONE_INFO_BEG,
9331 (sizeof(ASC_SCSIQ_2) + sizeof(ASC_SCSIQ_3)) / 2);
9333 _val = AscReadLramWord(iop_base,
9334 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS));
9335 scsiq->q_status = (uchar)_val;
9336 scsiq->q_no = (uchar)(_val >> 8);
9337 _val = AscReadLramWord(iop_base,
9338 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_CNTL));
9339 scsiq->cntl = (uchar)_val;
9340 sg_queue_cnt = (uchar)(_val >> 8);
9341 _val = AscReadLramWord(iop_base,
9343 (ushort)ASC_SCSIQ_B_SENSE_LEN));
9344 scsiq->sense_len = (uchar)_val;
9345 scsiq->extra_bytes = (uchar)(_val >> 8);
9348 * Read high word of remain bytes from alternate location.
9350 scsiq->remain_bytes = (((ADV_DCNT)AscReadLramWord(iop_base,
9353 ASC_SCSIQ_W_ALT_DC1)))
9356 * Read low word of remain bytes from original location.
9358 scsiq->remain_bytes += AscReadLramWord(iop_base,
9359 (ushort)(q_addr + (ushort)
9360 ASC_SCSIQ_DW_REMAIN_XFER_CNT));
9362 scsiq->remain_bytes &= max_dma_count;
9363 return sg_queue_cnt;
9367 * asc_isr_callback() - Second Level Interrupt Handler called by AscISR().
9369 * Interrupt callback function for the Narrow SCSI Asc Library.
9371 static void asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep)
9373 asc_board_t *boardp;
9374 struct scsi_cmnd *scp;
9375 struct Scsi_Host *shost;
9377 ASC_DBG2(1, "asc_isr_callback: asc_dvc_varp 0x%lx, qdonep 0x%lx\n",
9378 (ulong)asc_dvc_varp, (ulong)qdonep);
9379 ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep);
9382 * Get the struct scsi_cmnd structure and Scsi_Host structure for the
9383 * command that has been completed.
9385 scp = (struct scsi_cmnd *)ASC_U32_TO_VADDR(qdonep->d2.srb_ptr);
9386 ASC_DBG1(1, "asc_isr_callback: scp 0x%lx\n", (ulong)scp);
9389 ASC_PRINT("asc_isr_callback: scp is NULL\n");
9392 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
9394 shost = scp->device->host;
9395 ASC_STATS(shost, callback);
9396 ASC_DBG1(1, "asc_isr_callback: shost 0x%lx\n", (ulong)shost);
9398 boardp = ASC_BOARDP(shost);
9399 BUG_ON(asc_dvc_varp != &boardp->dvc_var.asc_dvc_var);
9402 * 'qdonep' contains the command's ending status.
9404 switch (qdonep->d3.done_stat) {
9406 ASC_DBG(2, "asc_isr_callback: QD_NO_ERROR\n");
9410 * Check for an underrun condition.
9412 * If there was no error and an underrun condition, then
9413 * return the number of underrun bytes.
9415 if (scp->request_bufflen != 0 && qdonep->remain_bytes != 0 &&
9416 qdonep->remain_bytes <= scp->request_bufflen) {
9418 "asc_isr_callback: underrun condition %u bytes\n",
9419 (unsigned)qdonep->remain_bytes);
9420 scp->resid = qdonep->remain_bytes;
9425 ASC_DBG(2, "asc_isr_callback: QD_WITH_ERROR\n");
9426 switch (qdonep->d3.host_stat) {
9427 case QHSTA_NO_ERROR:
9428 if (qdonep->d3.scsi_stat == SAM_STAT_CHECK_CONDITION) {
9430 "asc_isr_callback: SAM_STAT_CHECK_CONDITION\n");
9431 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
9432 sizeof(scp->sense_buffer));
9434 * Note: The 'status_byte()' macro used by
9435 * target drivers defined in scsi.h shifts the
9436 * status byte returned by host drivers right
9437 * by 1 bit. This is why target drivers also
9438 * use right shifted status byte definitions.
9439 * For instance target drivers use
9440 * CHECK_CONDITION, defined to 0x1, instead of
9441 * the SCSI defined check condition value of
9442 * 0x2. Host drivers are supposed to return
9443 * the status byte as it is defined by SCSI.
9445 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
9446 STATUS_BYTE(qdonep->d3.scsi_stat);
9448 scp->result = STATUS_BYTE(qdonep->d3.scsi_stat);
9453 /* QHSTA error occurred */
9454 ASC_DBG1(1, "asc_isr_callback: host_stat 0x%x\n",
9455 qdonep->d3.host_stat);
9456 scp->result = HOST_BYTE(DID_BAD_TARGET);
9461 case QD_ABORTED_BY_HOST:
9462 ASC_DBG(1, "asc_isr_callback: QD_ABORTED_BY_HOST\n");
9464 HOST_BYTE(DID_ABORT) | MSG_BYTE(qdonep->d3.
9466 STATUS_BYTE(qdonep->d3.scsi_stat);
9470 ASC_DBG1(1, "asc_isr_callback: done_stat 0x%x\n",
9471 qdonep->d3.done_stat);
9473 HOST_BYTE(DID_ERROR) | MSG_BYTE(qdonep->d3.
9475 STATUS_BYTE(qdonep->d3.scsi_stat);
9480 * If the 'init_tidmask' bit isn't already set for the target and the
9481 * current request finished normally, then set the bit for the target
9482 * to indicate that a device is present.
9484 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
9485 qdonep->d3.done_stat == QD_NO_ERROR &&
9486 qdonep->d3.host_stat == QHSTA_NO_ERROR) {
9487 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
9495 static int AscIsrQDone(ASC_DVC_VAR *asc_dvc)
9504 ASC_SCSI_BIT_ID_TYPE scsi_busy;
9505 ASC_SCSI_BIT_ID_TYPE target_id;
9509 uchar cur_target_qng;
9510 ASC_QDONE_INFO scsiq_buf;
9511 ASC_QDONE_INFO *scsiq;
9514 iop_base = asc_dvc->iop_base;
9516 scsiq = (ASC_QDONE_INFO *)&scsiq_buf;
9517 done_q_tail = (uchar)AscGetVarDoneQTail(iop_base);
9518 q_addr = ASC_QNO_TO_QADDR(done_q_tail);
9519 next_qp = AscReadLramByte(iop_base,
9520 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_FWD));
9521 if (next_qp != ASC_QLINK_END) {
9522 AscPutVarDoneQTail(iop_base, next_qp);
9523 q_addr = ASC_QNO_TO_QADDR(next_qp);
9524 sg_queue_cnt = _AscCopyLramScsiDoneQ(iop_base, q_addr, scsiq,
9525 asc_dvc->max_dma_count);
9526 AscWriteLramByte(iop_base,
9528 (ushort)ASC_SCSIQ_B_STATUS),
9530 q_status & (uchar)~(QS_READY |
9532 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix);
9533 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix);
9534 if ((scsiq->cntl & QC_SG_HEAD) != 0) {
9536 sg_list_qp = next_qp;
9537 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) {
9538 sg_list_qp = AscReadLramByte(iop_base,
9542 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp);
9543 if (sg_list_qp == ASC_QLINK_END) {
9544 AscSetLibErrorCode(asc_dvc,
9545 ASCQ_ERR_SG_Q_LINKS);
9546 scsiq->d3.done_stat = QD_WITH_ERROR;
9547 scsiq->d3.host_stat =
9548 QHSTA_D_QDONE_SG_LIST_CORRUPTED;
9549 goto FATAL_ERR_QDONE;
9551 AscWriteLramByte(iop_base,
9552 (ushort)(sg_q_addr + (ushort)
9553 ASC_SCSIQ_B_STATUS),
9556 n_q_used = sg_queue_cnt + 1;
9557 AscPutVarDoneQTail(iop_base, sg_list_qp);
9559 if (asc_dvc->queue_full_or_busy & target_id) {
9560 cur_target_qng = AscReadLramByte(iop_base,
9566 if (cur_target_qng < asc_dvc->max_dvc_qng[tid_no]) {
9567 scsi_busy = AscReadLramByte(iop_base, (ushort)
9569 scsi_busy &= ~target_id;
9570 AscWriteLramByte(iop_base,
9571 (ushort)ASCV_SCSIBUSY_B,
9573 asc_dvc->queue_full_or_busy &= ~target_id;
9576 if (asc_dvc->cur_total_qng >= n_q_used) {
9577 asc_dvc->cur_total_qng -= n_q_used;
9578 if (asc_dvc->cur_dvc_qng[tid_no] != 0) {
9579 asc_dvc->cur_dvc_qng[tid_no]--;
9582 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CUR_QNG);
9583 scsiq->d3.done_stat = QD_WITH_ERROR;
9584 goto FATAL_ERR_QDONE;
9586 if ((scsiq->d2.srb_ptr == 0UL) ||
9587 ((scsiq->q_status & QS_ABORTED) != 0)) {
9589 } else if (scsiq->q_status == QS_DONE) {
9590 false_overrun = FALSE;
9591 if (scsiq->extra_bytes != 0) {
9592 scsiq->remain_bytes +=
9593 (ADV_DCNT)scsiq->extra_bytes;
9595 if (scsiq->d3.done_stat == QD_WITH_ERROR) {
9596 if (scsiq->d3.host_stat ==
9597 QHSTA_M_DATA_OVER_RUN) {
9599 cntl & (QC_DATA_IN | QC_DATA_OUT))
9601 scsiq->d3.done_stat =
9603 scsiq->d3.host_stat =
9605 } else if (false_overrun) {
9606 scsiq->d3.done_stat =
9608 scsiq->d3.host_stat =
9611 } else if (scsiq->d3.host_stat ==
9612 QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) {
9613 AscStopChip(iop_base);
9614 AscSetChipControl(iop_base,
9615 (uchar)(CC_SCSI_RESET
9618 AscSetChipControl(iop_base, CC_HALT);
9619 AscSetChipStatus(iop_base,
9620 CIW_CLR_SCSI_RESET_INT);
9621 AscSetChipStatus(iop_base, 0);
9622 AscSetChipControl(iop_base, 0);
9625 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
9626 asc_isr_callback(asc_dvc, scsiq);
9628 if ((AscReadLramByte(iop_base,
9629 (ushort)(q_addr + (ushort)
9632 asc_dvc->unit_not_ready &= ~target_id;
9633 if (scsiq->d3.done_stat != QD_NO_ERROR) {
9634 asc_dvc->start_motor &=
9641 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_Q_STATUS);
9643 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
9644 asc_isr_callback(asc_dvc, scsiq);
9652 static int AscISR(ASC_DVC_VAR *asc_dvc)
9654 ASC_CS_TYPE chipstat;
9656 ushort saved_ram_addr;
9658 uchar saved_ctrl_reg;
9663 iop_base = asc_dvc->iop_base;
9664 int_pending = FALSE;
9666 if (AscIsIntPending(iop_base) == 0)
9669 if ((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0) {
9672 if (asc_dvc->in_critical_cnt != 0) {
9673 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL);
9676 if (asc_dvc->is_in_int) {
9677 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY);
9680 asc_dvc->is_in_int = TRUE;
9681 ctrl_reg = AscGetChipControl(iop_base);
9682 saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET |
9683 CC_SINGLE_STEP | CC_DIAG | CC_TEST));
9684 chipstat = AscGetChipStatus(iop_base);
9685 if (chipstat & CSW_SCSI_RESET_LATCH) {
9686 if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) {
9689 asc_dvc->sdtr_done = 0;
9690 saved_ctrl_reg &= (uchar)(~CC_HALT);
9691 while ((AscGetChipStatus(iop_base) &
9692 CSW_SCSI_RESET_ACTIVE) && (i-- > 0)) {
9695 AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT));
9696 AscSetChipControl(iop_base, CC_HALT);
9697 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
9698 AscSetChipStatus(iop_base, 0);
9699 chipstat = AscGetChipStatus(iop_base);
9702 saved_ram_addr = AscGetChipLramAddr(iop_base);
9703 host_flag = AscReadLramByte(iop_base,
9705 (uchar)(~ASC_HOST_FLAG_IN_ISR);
9706 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
9707 (uchar)(host_flag | (uchar)ASC_HOST_FLAG_IN_ISR));
9708 if ((chipstat & CSW_INT_PENDING) || (int_pending)) {
9709 AscAckInterrupt(iop_base);
9711 if ((chipstat & CSW_HALTED) && (ctrl_reg & CC_SINGLE_STEP)) {
9712 if (AscIsrChipHalted(asc_dvc) == ERR) {
9713 goto ISR_REPORT_QDONE_FATAL_ERROR;
9715 saved_ctrl_reg &= (uchar)(~CC_HALT);
9718 ISR_REPORT_QDONE_FATAL_ERROR:
9719 if ((asc_dvc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) != 0) {
9721 AscIsrQDone(asc_dvc)) & 0x01) != 0) {
9726 AscIsrQDone(asc_dvc)) == 1) {
9729 } while (status == 0x11);
9731 if ((status & 0x80) != 0)
9735 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
9736 AscSetChipLramAddr(iop_base, saved_ram_addr);
9737 AscSetChipControl(iop_base, saved_ctrl_reg);
9738 asc_dvc->is_in_int = FALSE;
9745 * Reset the bus associated with the command 'scp'.
9747 * This function runs its own thread. Interrupts must be blocked but
9748 * sleeping is allowed and no locking other than for host structures is
9749 * required. Returns SUCCESS or FAILED.
9751 static int advansys_reset(struct scsi_cmnd *scp)
9753 struct Scsi_Host *shost = scp->device->host;
9754 struct asc_board *boardp = ASC_BOARDP(shost);
9755 unsigned long flags;
9759 ASC_DBG1(1, "advansys_reset: 0x%p\n", scp);
9761 ASC_STATS(shost, reset);
9763 scmd_printk(KERN_INFO, scp, "SCSI bus reset started...\n");
9765 if (ASC_NARROW_BOARD(boardp)) {
9766 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
9768 /* Reset the chip and SCSI bus. */
9769 ASC_DBG(1, "advansys_reset: before AscInitAsc1000Driver()\n");
9770 status = AscInitAsc1000Driver(asc_dvc);
9772 /* Refer to ASC_IERR_* defintions for meaning of 'err_code'. */
9773 if (asc_dvc->err_code) {
9774 scmd_printk(KERN_INFO, scp, "SCSI bus reset error: "
9775 "0x%x\n", asc_dvc->err_code);
9777 } else if (status) {
9778 scmd_printk(KERN_INFO, scp, "SCSI bus reset warning: "
9781 scmd_printk(KERN_INFO, scp, "SCSI bus reset "
9785 ASC_DBG(1, "advansys_reset: after AscInitAsc1000Driver()\n");
9786 spin_lock_irqsave(&boardp->lock, flags);
9789 * If the suggest reset bus flags are set, then reset the bus.
9790 * Otherwise only reset the device.
9792 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
9795 * Reset the target's SCSI bus.
9797 ASC_DBG(1, "advansys_reset: before AdvResetChipAndSB()\n");
9798 switch (AdvResetChipAndSB(adv_dvc)) {
9800 scmd_printk(KERN_INFO, scp, "SCSI bus reset "
9805 scmd_printk(KERN_INFO, scp, "SCSI bus reset error\n");
9809 spin_lock_irqsave(&boardp->lock, flags);
9813 /* Save the time of the most recently completed reset. */
9814 boardp->last_reset = jiffies;
9815 spin_unlock_irqrestore(&boardp->lock, flags);
9817 ASC_DBG1(1, "advansys_reset: ret %d\n", ret);
9823 * advansys_biosparam()
9825 * Translate disk drive geometry if the "BIOS greater than 1 GB"
9826 * support is enabled for a drive.
9828 * ip (information pointer) is an int array with the following definition:
9834 advansys_biosparam(struct scsi_device *sdev, struct block_device *bdev,
9835 sector_t capacity, int ip[])
9837 asc_board_t *boardp;
9839 ASC_DBG(1, "advansys_biosparam: begin\n");
9840 ASC_STATS(sdev->host, biosparam);
9841 boardp = ASC_BOARDP(sdev->host);
9842 if (ASC_NARROW_BOARD(boardp)) {
9843 if ((boardp->dvc_var.asc_dvc_var.dvc_cntl &
9844 ASC_CNTL_BIOS_GT_1GB) && capacity > 0x200000) {
9852 if ((boardp->dvc_var.adv_dvc_var.bios_ctrl &
9853 BIOS_CTRL_EXTENDED_XLAT) && capacity > 0x200000) {
9861 ip[2] = (unsigned long)capacity / (ip[0] * ip[1]);
9862 ASC_DBG(1, "advansys_biosparam: end\n");
9867 * First-level interrupt handler.
9869 * 'dev_id' is a pointer to the interrupting adapter's Scsi_Host.
9871 static irqreturn_t advansys_interrupt(int irq, void *dev_id)
9873 unsigned long flags;
9874 struct Scsi_Host *shost = dev_id;
9875 asc_board_t *boardp = ASC_BOARDP(shost);
9876 irqreturn_t result = IRQ_NONE;
9878 ASC_DBG1(2, "advansys_interrupt: boardp 0x%p\n", boardp);
9879 spin_lock_irqsave(&boardp->lock, flags);
9880 if (ASC_NARROW_BOARD(boardp)) {
9881 if (AscIsIntPending(shost->io_port)) {
9882 result = IRQ_HANDLED;
9883 ASC_STATS(shost, interrupt);
9884 ASC_DBG(1, "advansys_interrupt: before AscISR()\n");
9885 AscISR(&boardp->dvc_var.asc_dvc_var);
9888 ASC_DBG(1, "advansys_interrupt: before AdvISR()\n");
9889 if (AdvISR(&boardp->dvc_var.adv_dvc_var)) {
9890 result = IRQ_HANDLED;
9891 ASC_STATS(shost, interrupt);
9894 spin_unlock_irqrestore(&boardp->lock, flags);
9896 ASC_DBG(1, "advansys_interrupt: end\n");
9900 static int AscHostReqRiscHalt(PortAddr iop_base)
9904 uchar saved_stop_code;
9906 if (AscIsChipHalted(iop_base))
9908 saved_stop_code = AscReadLramByte(iop_base, ASCV_STOP_CODE_B);
9909 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
9910 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP);
9912 if (AscIsChipHalted(iop_base)) {
9917 } while (count++ < 20);
9918 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, saved_stop_code);
9923 AscSetRunChipSynRegAtID(PortAddr iop_base, uchar tid_no, uchar sdtr_data)
9927 if (AscHostReqRiscHalt(iop_base)) {
9928 sta = AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
9929 AscStartChip(iop_base);
9934 static void AscAsyncFix(ASC_DVC_VAR *asc_dvc, struct scsi_device *sdev)
9936 char type = sdev->type;
9937 ASC_SCSI_BIT_ID_TYPE tid_bits = 1 << sdev->id;
9939 if (!(asc_dvc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN))
9941 if (asc_dvc->init_sdtr & tid_bits)
9944 if ((type == TYPE_ROM) && (strncmp(sdev->vendor, "HP ", 3) == 0))
9945 asc_dvc->pci_fix_asyn_xfer_always |= tid_bits;
9947 asc_dvc->pci_fix_asyn_xfer |= tid_bits;
9948 if ((type == TYPE_PROCESSOR) || (type == TYPE_SCANNER) ||
9949 (type == TYPE_ROM) || (type == TYPE_TAPE))
9950 asc_dvc->pci_fix_asyn_xfer &= ~tid_bits;
9952 if (asc_dvc->pci_fix_asyn_xfer & tid_bits)
9953 AscSetRunChipSynRegAtID(asc_dvc->iop_base, sdev->id,
9954 ASYN_SDTR_DATA_FIX_PCI_REV_AB);
9958 advansys_narrow_slave_configure(struct scsi_device *sdev, ASC_DVC_VAR *asc_dvc)
9960 ASC_SCSI_BIT_ID_TYPE tid_bit = 1 << sdev->id;
9961 ASC_SCSI_BIT_ID_TYPE orig_use_tagged_qng = asc_dvc->use_tagged_qng;
9963 if (sdev->lun == 0) {
9964 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr = asc_dvc->init_sdtr;
9965 if ((asc_dvc->cfg->sdtr_enable & tid_bit) && sdev->sdtr) {
9966 asc_dvc->init_sdtr |= tid_bit;
9968 asc_dvc->init_sdtr &= ~tid_bit;
9971 if (orig_init_sdtr != asc_dvc->init_sdtr)
9972 AscAsyncFix(asc_dvc, sdev);
9975 if (sdev->tagged_supported) {
9976 if (asc_dvc->cfg->cmd_qng_enabled & tid_bit) {
9977 if (sdev->lun == 0) {
9978 asc_dvc->cfg->can_tagged_qng |= tid_bit;
9979 asc_dvc->use_tagged_qng |= tid_bit;
9981 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG,
9982 asc_dvc->max_dvc_qng[sdev->id]);
9985 if (sdev->lun == 0) {
9986 asc_dvc->cfg->can_tagged_qng &= ~tid_bit;
9987 asc_dvc->use_tagged_qng &= ~tid_bit;
9989 scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
9992 if ((sdev->lun == 0) &&
9993 (orig_use_tagged_qng != asc_dvc->use_tagged_qng)) {
9994 AscWriteLramByte(asc_dvc->iop_base, ASCV_DISC_ENABLE_B,
9995 asc_dvc->cfg->disc_enable);
9996 AscWriteLramByte(asc_dvc->iop_base, ASCV_USE_TAGGED_QNG_B,
9997 asc_dvc->use_tagged_qng);
9998 AscWriteLramByte(asc_dvc->iop_base, ASCV_CAN_TAGGED_QNG_B,
9999 asc_dvc->cfg->can_tagged_qng);
10001 asc_dvc->max_dvc_qng[sdev->id] =
10002 asc_dvc->cfg->max_tag_qng[sdev->id];
10003 AscWriteLramByte(asc_dvc->iop_base,
10004 (ushort)(ASCV_MAX_DVC_QNG_BEG + sdev->id),
10005 asc_dvc->max_dvc_qng[sdev->id]);
10012 * If the EEPROM enabled WDTR for the device and the device supports wide
10013 * bus (16 bit) transfers, then turn on the device's 'wdtr_able' bit and
10014 * write the new value to the microcode.
10017 advansys_wide_enable_wdtr(AdvPortAddr iop_base, unsigned short tidmask)
10019 unsigned short cfg_word;
10020 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
10021 if ((cfg_word & tidmask) != 0)
10024 cfg_word |= tidmask;
10025 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
10028 * Clear the microcode SDTR and WDTR negotiation done indicators for
10029 * the target to cause it to negotiate with the new setting set above.
10030 * WDTR when accepted causes the target to enter asynchronous mode, so
10031 * SDTR must be negotiated.
10033 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
10034 cfg_word &= ~tidmask;
10035 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
10036 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
10037 cfg_word &= ~tidmask;
10038 AdvWriteWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
10042 * Synchronous Transfers
10044 * If the EEPROM enabled SDTR for the device and the device
10045 * supports synchronous transfers, then turn on the device's
10046 * 'sdtr_able' bit. Write the new value to the microcode.
10049 advansys_wide_enable_sdtr(AdvPortAddr iop_base, unsigned short tidmask)
10051 unsigned short cfg_word;
10052 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
10053 if ((cfg_word & tidmask) != 0)
10056 cfg_word |= tidmask;
10057 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
10060 * Clear the microcode "SDTR negotiation" done indicator for the
10061 * target to cause it to negotiate with the new setting set above.
10063 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
10064 cfg_word &= ~tidmask;
10065 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
10069 * PPR (Parallel Protocol Request) Capable
10071 * If the device supports DT mode, then it must be PPR capable.
10072 * The PPR message will be used in place of the SDTR and WDTR
10073 * messages to negotiate synchronous speed and offset, transfer
10074 * width, and protocol options.
10076 static void advansys_wide_enable_ppr(ADV_DVC_VAR *adv_dvc,
10077 AdvPortAddr iop_base, unsigned short tidmask)
10079 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
10080 adv_dvc->ppr_able |= tidmask;
10081 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
10085 advansys_wide_slave_configure(struct scsi_device *sdev, ADV_DVC_VAR *adv_dvc)
10087 AdvPortAddr iop_base = adv_dvc->iop_base;
10088 unsigned short tidmask = 1 << sdev->id;
10090 if (sdev->lun == 0) {
10092 * Handle WDTR, SDTR, and Tag Queuing. If the feature
10093 * is enabled in the EEPROM and the device supports the
10094 * feature, then enable it in the microcode.
10097 if ((adv_dvc->wdtr_able & tidmask) && sdev->wdtr)
10098 advansys_wide_enable_wdtr(iop_base, tidmask);
10099 if ((adv_dvc->sdtr_able & tidmask) && sdev->sdtr)
10100 advansys_wide_enable_sdtr(iop_base, tidmask);
10101 if (adv_dvc->chip_type == ADV_CHIP_ASC38C1600 && sdev->ppr)
10102 advansys_wide_enable_ppr(adv_dvc, iop_base, tidmask);
10105 * Tag Queuing is disabled for the BIOS which runs in polled
10106 * mode and would see no benefit from Tag Queuing. Also by
10107 * disabling Tag Queuing in the BIOS devices with Tag Queuing
10108 * bugs will at least work with the BIOS.
10110 if ((adv_dvc->tagqng_able & tidmask) &&
10111 sdev->tagged_supported) {
10112 unsigned short cfg_word;
10113 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word);
10114 cfg_word |= tidmask;
10115 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
10117 AdvWriteByteLram(iop_base,
10118 ASC_MC_NUMBER_OF_MAX_CMD + sdev->id,
10119 adv_dvc->max_dvc_qng);
10123 if ((adv_dvc->tagqng_able & tidmask) && sdev->tagged_supported) {
10124 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG,
10125 adv_dvc->max_dvc_qng);
10127 scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
10132 * Set the number of commands to queue per device for the
10133 * specified host adapter.
10135 static int advansys_slave_configure(struct scsi_device *sdev)
10137 asc_board_t *boardp = ASC_BOARDP(sdev->host);
10138 boardp->flags |= ASC_SELECT_QUEUE_DEPTHS;
10140 if (ASC_NARROW_BOARD(boardp))
10141 advansys_narrow_slave_configure(sdev,
10142 &boardp->dvc_var.asc_dvc_var);
10144 advansys_wide_slave_configure(sdev,
10145 &boardp->dvc_var.adv_dvc_var);
10150 static int asc_build_req(asc_board_t *boardp, struct scsi_cmnd *scp,
10151 struct asc_scsi_q *asc_scsi_q)
10153 memset(asc_scsi_q, 0, sizeof(*asc_scsi_q));
10156 * Point the ASC_SCSI_Q to the 'struct scsi_cmnd'.
10158 asc_scsi_q->q2.srb_ptr = ASC_VADDR_TO_U32(scp);
10161 * Build the ASC_SCSI_Q request.
10163 asc_scsi_q->cdbptr = &scp->cmnd[0];
10164 asc_scsi_q->q2.cdb_len = scp->cmd_len;
10165 asc_scsi_q->q1.target_id = ASC_TID_TO_TARGET_ID(scp->device->id);
10166 asc_scsi_q->q1.target_lun = scp->device->lun;
10167 asc_scsi_q->q2.target_ix =
10168 ASC_TIDLUN_TO_IX(scp->device->id, scp->device->lun);
10169 asc_scsi_q->q1.sense_addr =
10170 cpu_to_le32(virt_to_bus(&scp->sense_buffer[0]));
10171 asc_scsi_q->q1.sense_len = sizeof(scp->sense_buffer);
10174 * If there are any outstanding requests for the current target,
10175 * then every 255th request send an ORDERED request. This heuristic
10176 * tries to retain the benefit of request sorting while preventing
10177 * request starvation. 255 is the max number of tags or pending commands
10178 * a device may have outstanding.
10180 * The request count is incremented below for every successfully
10184 if ((boardp->dvc_var.asc_dvc_var.cur_dvc_qng[scp->device->id] > 0) &&
10185 (boardp->reqcnt[scp->device->id] % 255) == 0) {
10186 asc_scsi_q->q2.tag_code = MSG_ORDERED_TAG;
10188 asc_scsi_q->q2.tag_code = MSG_SIMPLE_TAG;
10192 * Build ASC_SCSI_Q for a contiguous buffer or a scatter-gather
10195 if (scp->use_sg == 0) {
10197 * CDB request of single contiguous buffer.
10199 ASC_STATS(scp->device->host, cont_cnt);
10200 scp->SCp.dma_handle = scp->request_bufflen ?
10201 dma_map_single(boardp->dev, scp->request_buffer,
10202 scp->request_bufflen,
10203 scp->sc_data_direction) : 0;
10204 asc_scsi_q->q1.data_addr = cpu_to_le32(scp->SCp.dma_handle);
10205 asc_scsi_q->q1.data_cnt = cpu_to_le32(scp->request_bufflen);
10206 ASC_STATS_ADD(scp->device->host, cont_xfer,
10207 ASC_CEILING(scp->request_bufflen, 512));
10208 asc_scsi_q->q1.sg_queue_cnt = 0;
10209 asc_scsi_q->sg_head = NULL;
10212 * CDB scatter-gather request list.
10216 struct scatterlist *slp;
10217 struct asc_sg_head *asc_sg_head;
10219 slp = (struct scatterlist *)scp->request_buffer;
10220 use_sg = dma_map_sg(boardp->dev, slp, scp->use_sg,
10221 scp->sc_data_direction);
10223 if (use_sg > scp->device->host->sg_tablesize) {
10224 ASC_PRINT3("asc_build_req: board %d: use_sg %d > "
10225 "sg_tablesize %d\n", boardp->id, use_sg,
10226 scp->device->host->sg_tablesize);
10227 dma_unmap_sg(boardp->dev, slp, scp->use_sg,
10228 scp->sc_data_direction);
10229 scp->result = HOST_BYTE(DID_ERROR);
10233 ASC_STATS(scp->device->host, sg_cnt);
10235 asc_sg_head = kzalloc(sizeof(asc_scsi_q->sg_head) +
10236 use_sg * sizeof(struct asc_sg_list), GFP_ATOMIC);
10237 if (!asc_sg_head) {
10238 dma_unmap_sg(boardp->dev, slp, scp->use_sg,
10239 scp->sc_data_direction);
10240 scp->result = HOST_BYTE(DID_SOFT_ERROR);
10244 asc_scsi_q->q1.cntl |= QC_SG_HEAD;
10245 asc_scsi_q->sg_head = asc_sg_head;
10246 asc_scsi_q->q1.data_cnt = 0;
10247 asc_scsi_q->q1.data_addr = 0;
10248 /* This is a byte value, otherwise it would need to be swapped. */
10249 asc_sg_head->entry_cnt = asc_scsi_q->q1.sg_queue_cnt = use_sg;
10250 ASC_STATS_ADD(scp->device->host, sg_elem,
10251 asc_sg_head->entry_cnt);
10254 * Convert scatter-gather list into ASC_SG_HEAD list.
10256 for (sgcnt = 0; sgcnt < use_sg; sgcnt++, slp++) {
10257 asc_sg_head->sg_list[sgcnt].addr =
10258 cpu_to_le32(sg_dma_address(slp));
10259 asc_sg_head->sg_list[sgcnt].bytes =
10260 cpu_to_le32(sg_dma_len(slp));
10261 ASC_STATS_ADD(scp->device->host, sg_xfer,
10262 ASC_CEILING(sg_dma_len(slp), 512));
10266 ASC_DBG_PRT_ASC_SCSI_Q(2, &asc_scsi_q);
10267 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
10269 return ASC_NOERROR;
10273 * Build scatter-gather list for Adv Library (Wide Board).
10275 * Additional ADV_SG_BLOCK structures will need to be allocated
10276 * if the total number of scatter-gather elements exceeds
10277 * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are
10278 * assumed to be physically contiguous.
10281 * ADV_SUCCESS(1) - SG List successfully created
10282 * ADV_ERROR(-1) - SG List creation failed
10285 adv_get_sglist(asc_board_t *boardp, adv_req_t *reqp, struct scsi_cmnd *scp,
10288 adv_sgblk_t *sgblkp;
10289 ADV_SCSI_REQ_Q *scsiqp;
10290 struct scatterlist *slp;
10292 ADV_SG_BLOCK *sg_block, *prev_sg_block;
10293 ADV_PADDR sg_block_paddr;
10296 scsiqp = (ADV_SCSI_REQ_Q *)ADV_32BALIGN(&reqp->scsi_req_q);
10297 slp = (struct scatterlist *)scp->request_buffer;
10298 sg_elem_cnt = use_sg;
10299 prev_sg_block = NULL;
10300 reqp->sgblkp = NULL;
10304 * Allocate a 'adv_sgblk_t' structure from the board free
10305 * list. One 'adv_sgblk_t' structure holds NO_OF_SG_PER_BLOCK
10306 * (15) scatter-gather elements.
10308 if ((sgblkp = boardp->adv_sgblkp) == NULL) {
10309 ASC_DBG(1, "adv_get_sglist: no free adv_sgblk_t\n");
10310 ASC_STATS(scp->device->host, adv_build_nosg);
10313 * Allocation failed. Free 'adv_sgblk_t' structures
10314 * already allocated for the request.
10316 while ((sgblkp = reqp->sgblkp) != NULL) {
10317 /* Remove 'sgblkp' from the request list. */
10318 reqp->sgblkp = sgblkp->next_sgblkp;
10320 /* Add 'sgblkp' to the board free list. */
10321 sgblkp->next_sgblkp = boardp->adv_sgblkp;
10322 boardp->adv_sgblkp = sgblkp;
10327 /* Complete 'adv_sgblk_t' board allocation. */
10328 boardp->adv_sgblkp = sgblkp->next_sgblkp;
10329 sgblkp->next_sgblkp = NULL;
10332 * Get 8 byte aligned virtual and physical addresses
10333 * for the allocated ADV_SG_BLOCK structure.
10335 sg_block = (ADV_SG_BLOCK *)ADV_8BALIGN(&sgblkp->sg_block);
10336 sg_block_paddr = virt_to_bus(sg_block);
10339 * Check if this is the first 'adv_sgblk_t' for the
10342 if (reqp->sgblkp == NULL) {
10343 /* Request's first scatter-gather block. */
10344 reqp->sgblkp = sgblkp;
10347 * Set ADV_SCSI_REQ_T ADV_SG_BLOCK virtual and physical
10348 * address pointers.
10350 scsiqp->sg_list_ptr = sg_block;
10351 scsiqp->sg_real_addr = cpu_to_le32(sg_block_paddr);
10353 /* Request's second or later scatter-gather block. */
10354 sgblkp->next_sgblkp = reqp->sgblkp;
10355 reqp->sgblkp = sgblkp;
10358 * Point the previous ADV_SG_BLOCK structure to
10359 * the newly allocated ADV_SG_BLOCK structure.
10361 prev_sg_block->sg_ptr = cpu_to_le32(sg_block_paddr);
10364 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) {
10365 sg_block->sg_list[i].sg_addr =
10366 cpu_to_le32(sg_dma_address(slp));
10367 sg_block->sg_list[i].sg_count =
10368 cpu_to_le32(sg_dma_len(slp));
10369 ASC_STATS_ADD(scp->device->host, sg_xfer,
10370 ASC_CEILING(sg_dma_len(slp), 512));
10372 if (--sg_elem_cnt == 0) { /* Last ADV_SG_BLOCK and scatter-gather entry. */
10373 sg_block->sg_cnt = i + 1;
10374 sg_block->sg_ptr = 0L; /* Last ADV_SG_BLOCK in list. */
10375 return ADV_SUCCESS;
10379 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK;
10380 prev_sg_block = sg_block;
10385 * Build a request structure for the Adv Library (Wide Board).
10387 * If an adv_req_t can not be allocated to issue the request,
10388 * then return ASC_BUSY. If an error occurs, then return ASC_ERROR.
10390 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the
10391 * microcode for DMA addresses or math operations are byte swapped
10392 * to little-endian order.
10395 adv_build_req(asc_board_t *boardp, struct scsi_cmnd *scp,
10396 ADV_SCSI_REQ_Q **adv_scsiqpp)
10399 ADV_SCSI_REQ_Q *scsiqp;
10404 * Allocate an adv_req_t structure from the board to execute
10407 if (boardp->adv_reqp == NULL) {
10408 ASC_DBG(1, "adv_build_req: no free adv_req_t\n");
10409 ASC_STATS(scp->device->host, adv_build_noreq);
10412 reqp = boardp->adv_reqp;
10413 boardp->adv_reqp = reqp->next_reqp;
10414 reqp->next_reqp = NULL;
10418 * Get 32-byte aligned ADV_SCSI_REQ_Q and ADV_SG_BLOCK pointers.
10420 scsiqp = (ADV_SCSI_REQ_Q *)ADV_32BALIGN(&reqp->scsi_req_q);
10423 * Initialize the structure.
10425 scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0;
10428 * Set the ADV_SCSI_REQ_Q 'srb_ptr' to point to the adv_req_t structure.
10430 scsiqp->srb_ptr = ASC_VADDR_TO_U32(reqp);
10433 * Set the adv_req_t 'cmndp' to point to the struct scsi_cmnd structure.
10438 * Build the ADV_SCSI_REQ_Q request.
10441 /* Set CDB length and copy it to the request structure. */
10442 scsiqp->cdb_len = scp->cmd_len;
10443 /* Copy first 12 CDB bytes to cdb[]. */
10444 for (i = 0; i < scp->cmd_len && i < 12; i++) {
10445 scsiqp->cdb[i] = scp->cmnd[i];
10447 /* Copy last 4 CDB bytes, if present, to cdb16[]. */
10448 for (; i < scp->cmd_len; i++) {
10449 scsiqp->cdb16[i - 12] = scp->cmnd[i];
10452 scsiqp->target_id = scp->device->id;
10453 scsiqp->target_lun = scp->device->lun;
10455 scsiqp->sense_addr = cpu_to_le32(virt_to_bus(&scp->sense_buffer[0]));
10456 scsiqp->sense_len = sizeof(scp->sense_buffer);
10459 * Build ADV_SCSI_REQ_Q for a contiguous buffer or a scatter-gather
10463 scsiqp->data_cnt = cpu_to_le32(scp->request_bufflen);
10464 scsiqp->vdata_addr = scp->request_buffer;
10465 scsiqp->data_addr = cpu_to_le32(virt_to_bus(scp->request_buffer));
10467 if (scp->use_sg == 0) {
10469 * CDB request of single contiguous buffer.
10471 reqp->sgblkp = NULL;
10472 scsiqp->data_cnt = cpu_to_le32(scp->request_bufflen);
10473 if (scp->request_bufflen) {
10474 scsiqp->vdata_addr = scp->request_buffer;
10475 scp->SCp.dma_handle =
10476 dma_map_single(boardp->dev, scp->request_buffer,
10477 scp->request_bufflen,
10478 scp->sc_data_direction);
10480 scsiqp->vdata_addr = NULL;
10481 scp->SCp.dma_handle = 0;
10483 scsiqp->data_addr = cpu_to_le32(scp->SCp.dma_handle);
10484 scsiqp->sg_list_ptr = NULL;
10485 scsiqp->sg_real_addr = 0;
10486 ASC_STATS(scp->device->host, cont_cnt);
10487 ASC_STATS_ADD(scp->device->host, cont_xfer,
10488 ASC_CEILING(scp->request_bufflen, 512));
10491 * CDB scatter-gather request list.
10493 struct scatterlist *slp;
10496 slp = (struct scatterlist *)scp->request_buffer;
10497 use_sg = dma_map_sg(boardp->dev, slp, scp->use_sg,
10498 scp->sc_data_direction);
10500 if (use_sg > ADV_MAX_SG_LIST) {
10501 ASC_PRINT3("adv_build_req: board %d: use_sg %d > "
10502 "ADV_MAX_SG_LIST %d\n", boardp->id, use_sg,
10503 scp->device->host->sg_tablesize);
10504 dma_unmap_sg(boardp->dev, slp, scp->use_sg,
10505 scp->sc_data_direction);
10506 scp->result = HOST_BYTE(DID_ERROR);
10509 * Free the 'adv_req_t' structure by adding it back
10510 * to the board free list.
10512 reqp->next_reqp = boardp->adv_reqp;
10513 boardp->adv_reqp = reqp;
10518 ret = adv_get_sglist(boardp, reqp, scp, use_sg);
10519 if (ret != ADV_SUCCESS) {
10521 * Free the adv_req_t structure by adding it back to
10522 * the board free list.
10524 reqp->next_reqp = boardp->adv_reqp;
10525 boardp->adv_reqp = reqp;
10530 ASC_STATS(scp->device->host, sg_cnt);
10531 ASC_STATS_ADD(scp->device->host, sg_elem, use_sg);
10534 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
10535 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
10537 *adv_scsiqpp = scsiqp;
10539 return ASC_NOERROR;
10542 static int AscSgListToQueue(int sg_list)
10546 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q);
10547 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0)
10549 return n_sg_list_qs + 1;
10553 AscGetNumOfFreeQueue(ASC_DVC_VAR *asc_dvc, uchar target_ix, uchar n_qs)
10557 ASC_SCSI_BIT_ID_TYPE target_id;
10560 target_id = ASC_TIX_TO_TARGET_ID(target_ix);
10561 tid_no = ASC_TIX_TO_TID(target_ix);
10562 if ((asc_dvc->unit_not_ready & target_id) ||
10563 (asc_dvc->queue_full_or_busy & target_id)) {
10567 cur_used_qs = (uint) asc_dvc->cur_total_qng +
10568 (uint) asc_dvc->last_q_shortage + (uint) ASC_MIN_FREE_Q;
10570 cur_used_qs = (uint) asc_dvc->cur_total_qng +
10571 (uint) ASC_MIN_FREE_Q;
10573 if ((uint) (cur_used_qs + n_qs) <= (uint) asc_dvc->max_total_qng) {
10574 cur_free_qs = (uint) asc_dvc->max_total_qng - cur_used_qs;
10575 if (asc_dvc->cur_dvc_qng[tid_no] >=
10576 asc_dvc->max_dvc_qng[tid_no]) {
10579 return cur_free_qs;
10582 if ((n_qs > asc_dvc->last_q_shortage)
10583 && (n_qs <= (asc_dvc->max_total_qng - ASC_MIN_FREE_Q))) {
10584 asc_dvc->last_q_shortage = n_qs;
10590 static uchar AscAllocFreeQueue(PortAddr iop_base, uchar free_q_head)
10596 q_addr = ASC_QNO_TO_QADDR(free_q_head);
10597 q_status = (uchar)AscReadLramByte(iop_base,
10599 ASC_SCSIQ_B_STATUS));
10600 next_qp = AscReadLramByte(iop_base, (ushort)(q_addr + ASC_SCSIQ_B_FWD));
10601 if (((q_status & QS_READY) == 0) && (next_qp != ASC_QLINK_END))
10603 return ASC_QLINK_END;
10607 AscAllocMultipleFreeQueue(PortAddr iop_base, uchar free_q_head, uchar n_free_q)
10611 for (i = 0; i < n_free_q; i++) {
10612 free_q_head = AscAllocFreeQueue(iop_base, free_q_head);
10613 if (free_q_head == ASC_QLINK_END)
10616 return free_q_head;
10621 * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
10623 * Calling/Exit State:
10627 * Output an ASC_SCSI_Q structure to the chip
10630 DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
10634 ASC_DBG_PRT_HEX(2, "DvcPutScsiQ", outbuf, 2 * words);
10635 AscSetChipLramAddr(iop_base, s_addr);
10636 for (i = 0; i < 2 * words; i += 2) {
10637 if (i == 4 || i == 20) {
10640 outpw(iop_base + IOP_RAM_DATA,
10641 ((ushort)outbuf[i + 1] << 8) | outbuf[i]);
10645 static int AscPutReadyQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
10650 uchar syn_period_ix;
10654 iop_base = asc_dvc->iop_base;
10655 if (((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) &&
10656 ((asc_dvc->sdtr_done & scsiq->q1.target_id) == 0)) {
10657 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix);
10658 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
10660 (sdtr_data >> 4) & (asc_dvc->max_sdtr_index - 1);
10661 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET;
10662 AscMsgOutSDTR(asc_dvc,
10663 asc_dvc->sdtr_period_tbl[syn_period_ix],
10665 scsiq->q1.cntl |= QC_MSG_OUT;
10667 q_addr = ASC_QNO_TO_QADDR(q_no);
10668 if ((scsiq->q1.target_id & asc_dvc->use_tagged_qng) == 0) {
10669 scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG;
10671 scsiq->q1.status = QS_FREE;
10672 AscMemWordCopyPtrToLram(iop_base,
10673 q_addr + ASC_SCSIQ_CDB_BEG,
10674 (uchar *)scsiq->cdbptr, scsiq->q2.cdb_len >> 1);
10676 DvcPutScsiQ(iop_base,
10677 q_addr + ASC_SCSIQ_CPY_BEG,
10678 (uchar *)&scsiq->q1.cntl,
10679 ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1);
10680 AscWriteLramWord(iop_base,
10681 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS),
10682 (ushort)(((ushort)scsiq->q1.
10683 q_no << 8) | (ushort)QS_READY));
10688 AscPutReadySgListQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
10692 ASC_SG_HEAD *sg_head;
10693 ASC_SG_LIST_Q scsi_sg_q;
10694 ASC_DCNT saved_data_addr;
10695 ASC_DCNT saved_data_cnt;
10697 ushort sg_list_dwords;
10699 ushort sg_entry_cnt;
10703 iop_base = asc_dvc->iop_base;
10704 sg_head = scsiq->sg_head;
10705 saved_data_addr = scsiq->q1.data_addr;
10706 saved_data_cnt = scsiq->q1.data_cnt;
10707 scsiq->q1.data_addr = (ASC_PADDR) sg_head->sg_list[0].addr;
10708 scsiq->q1.data_cnt = (ASC_DCNT) sg_head->sg_list[0].bytes;
10709 #if CC_VERY_LONG_SG_LIST
10711 * If sg_head->entry_cnt is greater than ASC_MAX_SG_LIST
10712 * then not all SG elements will fit in the allocated queues.
10713 * The rest of the SG elements will be copied when the RISC
10714 * completes the SG elements that fit and halts.
10716 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
10718 * Set sg_entry_cnt to be the number of SG elements that
10719 * will fit in the allocated SG queues. It is minus 1, because
10720 * the first SG element is handled above. ASC_MAX_SG_LIST is
10721 * already inflated by 1 to account for this. For example it
10722 * may be 50 which is 1 + 7 queues * 7 SG elements.
10724 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
10727 * Keep track of remaining number of SG elements that will
10728 * need to be handled from a_isr.c.
10730 scsiq->remain_sg_entry_cnt =
10731 sg_head->entry_cnt - ASC_MAX_SG_LIST;
10733 #endif /* CC_VERY_LONG_SG_LIST */
10735 * Set sg_entry_cnt to be the number of SG elements that
10736 * will fit in the allocated SG queues. It is minus 1, because
10737 * the first SG element is handled above.
10739 sg_entry_cnt = sg_head->entry_cnt - 1;
10740 #if CC_VERY_LONG_SG_LIST
10742 #endif /* CC_VERY_LONG_SG_LIST */
10743 if (sg_entry_cnt != 0) {
10744 scsiq->q1.cntl |= QC_SG_HEAD;
10745 q_addr = ASC_QNO_TO_QADDR(q_no);
10747 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt;
10748 scsi_sg_q.sg_head_qp = q_no;
10749 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
10750 for (i = 0; i < sg_head->queue_cnt; i++) {
10751 scsi_sg_q.seq_no = i + 1;
10752 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
10753 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
10754 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
10756 scsi_sg_q.sg_list_cnt =
10758 scsi_sg_q.sg_cur_list_cnt =
10761 scsi_sg_q.sg_list_cnt =
10762 ASC_SG_LIST_PER_Q - 1;
10763 scsi_sg_q.sg_cur_list_cnt =
10764 ASC_SG_LIST_PER_Q - 1;
10767 #if CC_VERY_LONG_SG_LIST
10769 * This is the last SG queue in the list of
10770 * allocated SG queues. If there are more
10771 * SG elements than will fit in the allocated
10772 * queues, then set the QCSG_SG_XFER_MORE flag.
10774 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
10775 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
10777 #endif /* CC_VERY_LONG_SG_LIST */
10778 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
10779 #if CC_VERY_LONG_SG_LIST
10781 #endif /* CC_VERY_LONG_SG_LIST */
10782 sg_list_dwords = sg_entry_cnt << 1;
10784 scsi_sg_q.sg_list_cnt = sg_entry_cnt;
10785 scsi_sg_q.sg_cur_list_cnt =
10788 scsi_sg_q.sg_list_cnt =
10790 scsi_sg_q.sg_cur_list_cnt =
10795 next_qp = AscReadLramByte(iop_base,
10798 scsi_sg_q.q_no = next_qp;
10799 q_addr = ASC_QNO_TO_QADDR(next_qp);
10800 AscMemWordCopyPtrToLram(iop_base,
10801 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
10802 (uchar *)&scsi_sg_q,
10803 sizeof(ASC_SG_LIST_Q) >> 1);
10804 AscMemDWordCopyPtrToLram(iop_base,
10805 q_addr + ASC_SGQ_LIST_BEG,
10806 (uchar *)&sg_head->
10809 sg_index += ASC_SG_LIST_PER_Q;
10810 scsiq->next_sg_index = sg_index;
10813 scsiq->q1.cntl &= ~QC_SG_HEAD;
10815 sta = AscPutReadyQueue(asc_dvc, scsiq, q_no);
10816 scsiq->q1.data_addr = saved_data_addr;
10817 scsiq->q1.data_cnt = saved_data_cnt;
10822 AscSendScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar n_q_required)
10831 iop_base = asc_dvc->iop_base;
10832 target_ix = scsiq->q2.target_ix;
10833 tid_no = ASC_TIX_TO_TID(target_ix);
10835 free_q_head = (uchar)AscGetVarFreeQHead(iop_base);
10836 if (n_q_required > 1) {
10837 next_qp = AscAllocMultipleFreeQueue(iop_base, free_q_head,
10838 (uchar)n_q_required);
10839 if (next_qp != ASC_QLINK_END) {
10840 asc_dvc->last_q_shortage = 0;
10841 scsiq->sg_head->queue_cnt = n_q_required - 1;
10842 scsiq->q1.q_no = free_q_head;
10843 sta = AscPutReadySgListQueue(asc_dvc, scsiq,
10846 } else if (n_q_required == 1) {
10847 next_qp = AscAllocFreeQueue(iop_base, free_q_head);
10848 if (next_qp != ASC_QLINK_END) {
10849 scsiq->q1.q_no = free_q_head;
10850 sta = AscPutReadyQueue(asc_dvc, scsiq, free_q_head);
10854 AscPutVarFreeQHead(iop_base, next_qp);
10855 asc_dvc->cur_total_qng += n_q_required;
10856 asc_dvc->cur_dvc_qng[tid_no]++;
10861 #define ASC_SYN_OFFSET_ONE_DISABLE_LIST 16
10862 static uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] = {
10881 static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq)
10886 int disable_syn_offset_one_fix;
10889 ushort sg_entry_cnt = 0;
10890 ushort sg_entry_cnt_minus_one = 0;
10897 ASC_SG_HEAD *sg_head;
10900 iop_base = asc_dvc->iop_base;
10901 sg_head = scsiq->sg_head;
10902 if (asc_dvc->err_code != 0)
10904 scsiq->q1.q_no = 0;
10905 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) {
10906 scsiq->q1.extra_bytes = 0;
10909 target_ix = scsiq->q2.target_ix;
10910 tid_no = ASC_TIX_TO_TID(target_ix);
10912 if (scsiq->cdbptr[0] == REQUEST_SENSE) {
10913 if ((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) {
10914 asc_dvc->sdtr_done &= ~scsiq->q1.target_id;
10915 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
10916 AscMsgOutSDTR(asc_dvc,
10918 sdtr_period_tbl[(sdtr_data >> 4) &
10922 (uchar)(sdtr_data & (uchar)
10923 ASC_SYN_MAX_OFFSET));
10924 scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT);
10927 if (asc_dvc->in_critical_cnt != 0) {
10928 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CRITICAL_RE_ENTRY);
10931 asc_dvc->in_critical_cnt++;
10932 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
10933 if ((sg_entry_cnt = sg_head->entry_cnt) == 0) {
10934 asc_dvc->in_critical_cnt--;
10937 #if !CC_VERY_LONG_SG_LIST
10938 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
10939 asc_dvc->in_critical_cnt--;
10942 #endif /* !CC_VERY_LONG_SG_LIST */
10943 if (sg_entry_cnt == 1) {
10944 scsiq->q1.data_addr =
10945 (ADV_PADDR)sg_head->sg_list[0].addr;
10946 scsiq->q1.data_cnt =
10947 (ADV_DCNT)sg_head->sg_list[0].bytes;
10948 scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE);
10950 sg_entry_cnt_minus_one = sg_entry_cnt - 1;
10952 scsi_cmd = scsiq->cdbptr[0];
10953 disable_syn_offset_one_fix = FALSE;
10954 if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) &&
10955 !(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) {
10956 if (scsiq->q1.cntl & QC_SG_HEAD) {
10958 for (i = 0; i < sg_entry_cnt; i++) {
10960 (ADV_DCNT)le32_to_cpu(sg_head->sg_list[i].
10964 data_cnt = le32_to_cpu(scsiq->q1.data_cnt);
10966 if (data_cnt != 0UL) {
10967 if (data_cnt < 512UL) {
10968 disable_syn_offset_one_fix = TRUE;
10970 for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST;
10973 _syn_offset_one_disable_cmd[i];
10974 if (disable_cmd == 0xFF) {
10977 if (scsi_cmd == disable_cmd) {
10978 disable_syn_offset_one_fix =
10986 if (disable_syn_offset_one_fix) {
10987 scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG;
10988 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX |
10989 ASC_TAG_FLAG_DISABLE_DISCONNECT);
10991 scsiq->q2.tag_code &= 0x27;
10993 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
10994 if (asc_dvc->bug_fix_cntl) {
10995 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
10996 if ((scsi_cmd == READ_6) ||
10997 (scsi_cmd == READ_10)) {
10999 (ADV_PADDR)le32_to_cpu(sg_head->
11001 [sg_entry_cnt_minus_one].
11003 (ADV_DCNT)le32_to_cpu(sg_head->
11005 [sg_entry_cnt_minus_one].
11008 (uchar)((ushort)addr & 0x0003);
11009 if ((extra_bytes != 0)
11013 ASC_TAG_FLAG_EXTRA_BYTES)
11015 scsiq->q2.tag_code |=
11016 ASC_TAG_FLAG_EXTRA_BYTES;
11017 scsiq->q1.extra_bytes =
11020 le32_to_cpu(sg_head->
11022 [sg_entry_cnt_minus_one].
11025 (ASC_DCNT) extra_bytes;
11028 [sg_entry_cnt_minus_one].
11030 cpu_to_le32(data_cnt);
11035 sg_head->entry_to_copy = sg_head->entry_cnt;
11036 #if CC_VERY_LONG_SG_LIST
11038 * Set the sg_entry_cnt to the maximum possible. The rest of
11039 * the SG elements will be copied when the RISC completes the
11040 * SG elements that fit and halts.
11042 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
11043 sg_entry_cnt = ASC_MAX_SG_LIST;
11045 #endif /* CC_VERY_LONG_SG_LIST */
11046 n_q_required = AscSgListToQueue(sg_entry_cnt);
11047 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, n_q_required) >=
11048 (uint) n_q_required)
11049 || ((scsiq->q1.cntl & QC_URGENT) != 0)) {
11051 AscSendScsiQueue(asc_dvc, scsiq,
11052 n_q_required)) == 1) {
11053 asc_dvc->in_critical_cnt--;
11058 if (asc_dvc->bug_fix_cntl) {
11059 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
11060 if ((scsi_cmd == READ_6) ||
11061 (scsi_cmd == READ_10)) {
11063 le32_to_cpu(scsiq->q1.data_addr) +
11064 le32_to_cpu(scsiq->q1.data_cnt);
11066 (uchar)((ushort)addr & 0x0003);
11067 if ((extra_bytes != 0)
11071 ASC_TAG_FLAG_EXTRA_BYTES)
11074 le32_to_cpu(scsiq->q1.
11076 if (((ushort)data_cnt & 0x01FF)
11078 scsiq->q2.tag_code |=
11079 ASC_TAG_FLAG_EXTRA_BYTES;
11080 data_cnt -= (ASC_DCNT)
11082 scsiq->q1.data_cnt =
11085 scsiq->q1.extra_bytes =
11093 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, 1) >= 1) ||
11094 ((scsiq->q1.cntl & QC_URGENT) != 0)) {
11095 if ((sta = AscSendScsiQueue(asc_dvc, scsiq,
11096 n_q_required)) == 1) {
11097 asc_dvc->in_critical_cnt--;
11102 asc_dvc->in_critical_cnt--;
11107 * AdvExeScsiQueue() - Send a request to the RISC microcode program.
11109 * Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q,
11110 * add the carrier to the ICQ (Initiator Command Queue), and tickle the
11111 * RISC to notify it a new command is ready to be executed.
11113 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be
11114 * set to SCSI_MAX_RETRY.
11116 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the microcode
11117 * for DMA addresses or math operations are byte swapped to little-endian
11121 * ADV_SUCCESS(1) - The request was successfully queued.
11122 * ADV_BUSY(0) - Resource unavailable; Retry again after pending
11123 * request completes.
11124 * ADV_ERROR(-1) - Invalid ADV_SCSI_REQ_Q request structure
11127 static int AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq)
11129 AdvPortAddr iop_base;
11131 ADV_PADDR req_paddr;
11132 ADV_CARR_T *new_carrp;
11135 * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID.
11137 if (scsiq->target_id > ADV_MAX_TID) {
11138 scsiq->host_status = QHSTA_M_INVALID_DEVICE;
11139 scsiq->done_status = QD_WITH_ERROR;
11143 iop_base = asc_dvc->iop_base;
11146 * Allocate a carrier ensuring at least one carrier always
11147 * remains on the freelist and initialize fields.
11149 if ((new_carrp = asc_dvc->carr_freelist) == NULL) {
11152 asc_dvc->carr_freelist = (ADV_CARR_T *)
11153 ADV_U32_TO_VADDR(le32_to_cpu(new_carrp->next_vpa));
11154 asc_dvc->carr_pending_cnt++;
11157 * Set the carrier to be a stopper by setting 'next_vpa'
11158 * to the stopper value. The current stopper will be changed
11159 * below to point to the new stopper.
11161 new_carrp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
11164 * Clear the ADV_SCSI_REQ_Q done flag.
11166 scsiq->a_flag &= ~ADV_SCSIQ_DONE;
11168 req_size = sizeof(ADV_SCSI_REQ_Q);
11169 req_paddr = DvcGetPhyAddr(asc_dvc, scsiq, (uchar *)scsiq,
11170 (ADV_SDCNT *)&req_size, ADV_IS_SCSIQ_FLAG);
11172 BUG_ON(req_paddr & 31);
11173 BUG_ON(req_size < sizeof(ADV_SCSI_REQ_Q));
11175 /* Wait for assertion before making little-endian */
11176 req_paddr = cpu_to_le32(req_paddr);
11178 /* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */
11179 scsiq->scsiq_ptr = cpu_to_le32(ADV_VADDR_TO_U32(scsiq));
11180 scsiq->scsiq_rptr = req_paddr;
11182 scsiq->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->icq_sp));
11184 * Every ADV_CARR_T.carr_pa is byte swapped to little-endian
11185 * order during initialization.
11187 scsiq->carr_pa = asc_dvc->icq_sp->carr_pa;
11190 * Use the current stopper to send the ADV_SCSI_REQ_Q command to
11191 * the microcode. The newly allocated stopper will become the new
11194 asc_dvc->icq_sp->areq_vpa = req_paddr;
11197 * Set the 'next_vpa' pointer for the old stopper to be the
11198 * physical address of the new stopper. The RISC can only
11199 * follow physical addresses.
11201 asc_dvc->icq_sp->next_vpa = new_carrp->carr_pa;
11204 * Set the host adapter stopper pointer to point to the new carrier.
11206 asc_dvc->icq_sp = new_carrp;
11208 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
11209 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
11211 * Tickle the RISC to tell it to read its Command Queue Head pointer.
11213 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A);
11214 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
11216 * Clear the tickle value. In the ASC-3550 the RISC flag
11217 * command 'clr_tickle_a' does not work unless the host
11218 * value is cleared.
11220 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
11223 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
11225 * Notify the RISC a carrier is ready by writing the physical
11226 * address of the new carrier stopper to the COMMA register.
11228 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
11229 le32_to_cpu(new_carrp->carr_pa));
11232 return ADV_SUCCESS;
11236 * Execute a single 'Scsi_Cmnd'.
11238 * The function 'done' is called when the request has been completed.
11242 * host - board controlling device
11243 * device - device to send command
11244 * target - target of device
11245 * lun - lun of device
11246 * cmd_len - length of SCSI CDB
11247 * cmnd - buffer for SCSI 8, 10, or 12 byte CDB
11248 * use_sg - if non-zero indicates scatter-gather request with use_sg elements
11250 * if (use_sg == 0) {
11251 * request_buffer - buffer address for request
11252 * request_bufflen - length of request buffer
11254 * request_buffer - pointer to scatterlist structure
11257 * sense_buffer - sense command buffer
11259 * result (4 bytes of an int):
11261 * 0 SCSI Status Byte Code
11262 * 1 SCSI One Byte Message Code
11263 * 2 Host Error Code
11264 * 3 Mid-Level Error Code
11266 * host driver fields:
11267 * SCp - Scsi_Pointer used for command processing status
11268 * scsi_done - used to save caller's done function
11269 * host_scribble - used for pointer to another struct scsi_cmnd
11271 * If this function returns ASC_NOERROR the request will be completed
11272 * from the interrupt handler.
11274 * If this function returns ASC_ERROR the host error code has been set,
11275 * and the called must call asc_scsi_done.
11277 * If ASC_BUSY is returned the request will be returned to the midlayer
11278 * and re-tried later.
11280 static int asc_execute_scsi_cmnd(struct scsi_cmnd *scp)
11283 asc_board_t *boardp = ASC_BOARDP(scp->device->host);
11285 ASC_DBG1(1, "asc_execute_scsi_cmnd: scp 0x%p\n", scp);
11287 if (ASC_NARROW_BOARD(boardp)) {
11288 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
11289 struct asc_scsi_q asc_scsi_q;
11291 /* asc_build_req() can not return ASC_BUSY. */
11292 ret = asc_build_req(boardp, scp, &asc_scsi_q);
11293 if (ret == ASC_ERROR) {
11294 ASC_STATS(scp->device->host, build_error);
11298 ret = AscExeScsiQueue(asc_dvc, &asc_scsi_q);
11299 kfree(asc_scsi_q.sg_head);
11300 err_code = asc_dvc->err_code;
11302 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
11303 ADV_SCSI_REQ_Q *adv_scsiqp;
11305 switch (adv_build_req(boardp, scp, &adv_scsiqp)) {
11307 ASC_DBG(3, "asc_execute_scsi_cmnd: adv_build_req "
11311 ASC_DBG(1, "asc_execute_scsi_cmnd: adv_build_req "
11314 * The asc_stats fields 'adv_build_noreq' and
11315 * 'adv_build_nosg' count wide board busy conditions.
11316 * They are updated in adv_build_req and
11317 * adv_get_sglist, respectively.
11322 ASC_DBG(1, "asc_execute_scsi_cmnd: adv_build_req "
11324 ASC_STATS(scp->device->host, build_error);
11328 ret = AdvExeScsiQueue(adv_dvc, adv_scsiqp);
11329 err_code = adv_dvc->err_code;
11334 ASC_STATS(scp->device->host, exe_noerror);
11336 * Increment monotonically increasing per device
11337 * successful request counter. Wrapping doesn't matter.
11339 boardp->reqcnt[scp->device->id]++;
11340 ASC_DBG(1, "asc_execute_scsi_cmnd: ExeScsiQueue(), "
11344 ASC_STATS(scp->device->host, exe_busy);
11347 ASC_PRINT2("asc_execute_scsi_cmnd: board %d: ExeScsiQueue() "
11348 "ASC_ERROR, err_code 0x%x\n", boardp->id, err_code);
11349 ASC_STATS(scp->device->host, exe_error);
11350 scp->result = HOST_BYTE(DID_ERROR);
11353 ASC_PRINT2("asc_execute_scsi_cmnd: board %d: ExeScsiQueue() "
11354 "unknown, err_code 0x%x\n", boardp->id, err_code);
11355 ASC_STATS(scp->device->host, exe_unknown);
11356 scp->result = HOST_BYTE(DID_ERROR);
11360 ASC_DBG(1, "asc_execute_scsi_cmnd: end\n");
11365 * advansys_queuecommand() - interrupt-driven I/O entrypoint.
11367 * This function always returns 0. Command return status is saved
11368 * in the 'scp' result field.
11371 advansys_queuecommand(struct scsi_cmnd *scp, void (*done)(struct scsi_cmnd *))
11373 struct Scsi_Host *shost = scp->device->host;
11374 asc_board_t *boardp = ASC_BOARDP(shost);
11375 unsigned long flags;
11376 int asc_res, result = 0;
11378 ASC_STATS(shost, queuecommand);
11379 scp->scsi_done = done;
11382 * host_lock taken by mid-level prior to call, but need
11383 * to protect against own ISR
11385 spin_lock_irqsave(&boardp->lock, flags);
11386 asc_res = asc_execute_scsi_cmnd(scp);
11387 spin_unlock_irqrestore(&boardp->lock, flags);
11393 result = SCSI_MLQUEUE_HOST_BUSY;
11397 asc_scsi_done(scp);
11404 static ushort __devinit AscGetEisaChipCfg(PortAddr iop_base)
11406 PortAddr eisa_cfg_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
11407 (PortAddr) (ASC_EISA_CFG_IOP_MASK);
11408 return inpw(eisa_cfg_iop);
11412 * Return the BIOS address of the adapter at the specified
11413 * I/O port and with the specified bus type.
11415 static unsigned short __devinit
11416 AscGetChipBiosAddress(PortAddr iop_base, unsigned short bus_type)
11418 unsigned short cfg_lsw;
11419 unsigned short bios_addr;
11422 * The PCI BIOS is re-located by the motherboard BIOS. Because
11423 * of this the driver can not determine where a PCI BIOS is
11424 * loaded and executes.
11426 if (bus_type & ASC_IS_PCI)
11429 if ((bus_type & ASC_IS_EISA) != 0) {
11430 cfg_lsw = AscGetEisaChipCfg(iop_base);
11432 bios_addr = ASC_BIOS_MIN_ADDR + cfg_lsw * ASC_BIOS_BANK_SIZE;
11436 cfg_lsw = AscGetChipCfgLsw(iop_base);
11439 * ISA PnP uses the top bit as the 32K BIOS flag
11441 if (bus_type == ASC_IS_ISAPNP)
11443 bios_addr = ASC_BIOS_MIN_ADDR + (cfg_lsw >> 12) * ASC_BIOS_BANK_SIZE;
11447 static uchar __devinit AscSetChipScsiID(PortAddr iop_base, uchar new_host_id)
11451 if (AscGetChipScsiID(iop_base) == new_host_id) {
11452 return (new_host_id);
11454 cfg_lsw = AscGetChipCfgLsw(iop_base);
11456 cfg_lsw |= (ushort)((new_host_id & ASC_MAX_TID) << 8);
11457 AscSetChipCfgLsw(iop_base, cfg_lsw);
11458 return (AscGetChipScsiID(iop_base));
11461 static unsigned char __devinit AscGetChipScsiCtrl(PortAddr iop_base)
11465 AscSetBank(iop_base, 1);
11466 sc = inp(iop_base + IOP_REG_SC);
11467 AscSetBank(iop_base, 0);
11471 static unsigned char __devinit
11472 AscGetChipVersion(PortAddr iop_base, unsigned short bus_type)
11474 if (bus_type & ASC_IS_EISA) {
11476 unsigned char revision;
11477 eisa_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
11478 (PortAddr) ASC_EISA_REV_IOP_MASK;
11479 revision = inp(eisa_iop);
11480 return ASC_CHIP_MIN_VER_EISA - 1 + revision;
11482 return AscGetChipVerNo(iop_base);
11485 static void __devinit AscToggleIRQAct(PortAddr iop_base)
11487 AscSetChipStatus(iop_base, CIW_IRQ_ACT);
11488 AscSetChipStatus(iop_base, 0);
11492 static uchar __devinit AscGetChipIRQ(PortAddr iop_base, ushort bus_type)
11497 if ((bus_type & ASC_IS_EISA) != 0) {
11498 cfg_lsw = AscGetEisaChipCfg(iop_base);
11499 chip_irq = (uchar)(((cfg_lsw >> 8) & 0x07) + 10);
11500 if ((chip_irq == 13) || (chip_irq > 15)) {
11505 if ((bus_type & ASC_IS_VL) != 0) {
11506 cfg_lsw = AscGetChipCfgLsw(iop_base);
11507 chip_irq = (uchar)(((cfg_lsw >> 2) & 0x07));
11508 if ((chip_irq == 0) || (chip_irq == 4) || (chip_irq == 7)) {
11511 return ((uchar)(chip_irq + (ASC_MIN_IRQ_NO - 1)));
11513 cfg_lsw = AscGetChipCfgLsw(iop_base);
11514 chip_irq = (uchar)(((cfg_lsw >> 2) & 0x03));
11516 chip_irq += (uchar)2;
11517 return ((uchar)(chip_irq + ASC_MIN_IRQ_NO));
11520 static uchar __devinit
11521 AscSetChipIRQ(PortAddr iop_base, uchar irq_no, ushort bus_type)
11525 if ((bus_type & ASC_IS_VL) != 0) {
11527 if ((irq_no < ASC_MIN_IRQ_NO)
11528 || (irq_no > ASC_MAX_IRQ_NO)) {
11531 irq_no -= (uchar)((ASC_MIN_IRQ_NO - 1));
11534 cfg_lsw = (ushort)(AscGetChipCfgLsw(iop_base) & 0xFFE3);
11535 cfg_lsw |= (ushort)0x0010;
11536 AscSetChipCfgLsw(iop_base, cfg_lsw);
11537 AscToggleIRQAct(iop_base);
11538 cfg_lsw = (ushort)(AscGetChipCfgLsw(iop_base) & 0xFFE0);
11539 cfg_lsw |= (ushort)((irq_no & 0x07) << 2);
11540 AscSetChipCfgLsw(iop_base, cfg_lsw);
11541 AscToggleIRQAct(iop_base);
11542 return (AscGetChipIRQ(iop_base, bus_type));
11544 if ((bus_type & (ASC_IS_ISA)) != 0) {
11546 irq_no -= (uchar)2;
11547 irq_no -= (uchar)ASC_MIN_IRQ_NO;
11548 cfg_lsw = (ushort)(AscGetChipCfgLsw(iop_base) & 0xFFF3);
11549 cfg_lsw |= (ushort)((irq_no & 0x03) << 2);
11550 AscSetChipCfgLsw(iop_base, cfg_lsw);
11551 return (AscGetChipIRQ(iop_base, bus_type));
11557 static void __devinit AscEnableIsaDma(uchar dma_channel)
11559 if (dma_channel < 4) {
11560 outp(0x000B, (ushort)(0xC0 | dma_channel));
11561 outp(0x000A, dma_channel);
11562 } else if (dma_channel < 8) {
11563 outp(0x00D6, (ushort)(0xC0 | (dma_channel - 4)));
11564 outp(0x00D4, (ushort)(dma_channel - 4));
11568 #endif /* CONFIG_ISA */
11570 static int AscStopQueueExe(PortAddr iop_base)
11574 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) == 0) {
11575 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
11576 ASC_STOP_REQ_RISC_STOP);
11578 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) &
11579 ASC_STOP_ACK_RISC_STOP) {
11583 } while (count++ < 20);
11588 static ASC_DCNT __devinit AscGetMaxDmaCount(ushort bus_type)
11590 if (bus_type & ASC_IS_ISA)
11591 return ASC_MAX_ISA_DMA_COUNT;
11592 else if (bus_type & (ASC_IS_EISA | ASC_IS_VL))
11593 return ASC_MAX_VL_DMA_COUNT;
11594 return ASC_MAX_PCI_DMA_COUNT;
11598 static ushort __devinit AscGetIsaDmaChannel(PortAddr iop_base)
11602 channel = AscGetChipCfgLsw(iop_base) & 0x0003;
11603 if (channel == 0x03)
11605 else if (channel == 0x00)
11607 return (channel + 4);
11610 static ushort __devinit AscSetIsaDmaChannel(PortAddr iop_base, ushort dma_channel)
11615 if ((dma_channel >= 5) && (dma_channel <= 7)) {
11616 if (dma_channel == 7)
11619 value = dma_channel - 4;
11620 cfg_lsw = AscGetChipCfgLsw(iop_base) & 0xFFFC;
11622 AscSetChipCfgLsw(iop_base, cfg_lsw);
11623 return (AscGetIsaDmaChannel(iop_base));
11628 static uchar __devinit AscGetIsaDmaSpeed(PortAddr iop_base)
11632 AscSetBank(iop_base, 1);
11633 speed_value = AscReadChipDmaSpeed(iop_base);
11634 speed_value &= 0x07;
11635 AscSetBank(iop_base, 0);
11636 return speed_value;
11639 static uchar __devinit AscSetIsaDmaSpeed(PortAddr iop_base, uchar speed_value)
11641 speed_value &= 0x07;
11642 AscSetBank(iop_base, 1);
11643 AscWriteChipDmaSpeed(iop_base, speed_value);
11644 AscSetBank(iop_base, 0);
11645 return AscGetIsaDmaSpeed(iop_base);
11647 #endif /* CONFIG_ISA */
11649 static ushort __devinit AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc)
11654 uchar chip_version;
11656 iop_base = asc_dvc->iop_base;
11658 asc_dvc->err_code = 0;
11659 if ((asc_dvc->bus_type &
11660 (ASC_IS_ISA | ASC_IS_PCI | ASC_IS_EISA | ASC_IS_VL)) == 0) {
11661 asc_dvc->err_code |= ASC_IERR_NO_BUS_TYPE;
11663 AscSetChipControl(iop_base, CC_HALT);
11664 AscSetChipStatus(iop_base, 0);
11665 asc_dvc->bug_fix_cntl = 0;
11666 asc_dvc->pci_fix_asyn_xfer = 0;
11667 asc_dvc->pci_fix_asyn_xfer_always = 0;
11668 /* asc_dvc->init_state initalized in AscInitGetConfig(). */
11669 asc_dvc->sdtr_done = 0;
11670 asc_dvc->cur_total_qng = 0;
11671 asc_dvc->is_in_int = 0;
11672 asc_dvc->in_critical_cnt = 0;
11673 asc_dvc->last_q_shortage = 0;
11674 asc_dvc->use_tagged_qng = 0;
11675 asc_dvc->no_scam = 0;
11676 asc_dvc->unit_not_ready = 0;
11677 asc_dvc->queue_full_or_busy = 0;
11678 asc_dvc->redo_scam = 0;
11680 asc_dvc->host_init_sdtr_index = 0;
11681 asc_dvc->cfg->can_tagged_qng = 0;
11682 asc_dvc->cfg->cmd_qng_enabled = 0;
11683 asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL;
11684 asc_dvc->init_sdtr = 0;
11685 asc_dvc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG;
11686 asc_dvc->scsi_reset_wait = 3;
11687 asc_dvc->start_motor = ASC_SCSI_WIDTH_BIT_SET;
11688 asc_dvc->max_dma_count = AscGetMaxDmaCount(asc_dvc->bus_type);
11689 asc_dvc->cfg->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET;
11690 asc_dvc->cfg->disc_enable = ASC_SCSI_WIDTH_BIT_SET;
11691 asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID;
11692 asc_dvc->cfg->lib_serial_no = ASC_LIB_SERIAL_NUMBER;
11693 asc_dvc->cfg->lib_version = (ASC_LIB_VERSION_MAJOR << 8) |
11694 ASC_LIB_VERSION_MINOR;
11695 chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type);
11696 asc_dvc->cfg->chip_version = chip_version;
11697 asc_dvc->sdtr_period_tbl[0] = SYN_XFER_NS_0;
11698 asc_dvc->sdtr_period_tbl[1] = SYN_XFER_NS_1;
11699 asc_dvc->sdtr_period_tbl[2] = SYN_XFER_NS_2;
11700 asc_dvc->sdtr_period_tbl[3] = SYN_XFER_NS_3;
11701 asc_dvc->sdtr_period_tbl[4] = SYN_XFER_NS_4;
11702 asc_dvc->sdtr_period_tbl[5] = SYN_XFER_NS_5;
11703 asc_dvc->sdtr_period_tbl[6] = SYN_XFER_NS_6;
11704 asc_dvc->sdtr_period_tbl[7] = SYN_XFER_NS_7;
11705 asc_dvc->max_sdtr_index = 7;
11706 if ((asc_dvc->bus_type & ASC_IS_PCI) &&
11707 (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) {
11708 asc_dvc->bus_type = ASC_IS_PCI_ULTRA;
11709 asc_dvc->sdtr_period_tbl[0] = SYN_ULTRA_XFER_NS_0;
11710 asc_dvc->sdtr_period_tbl[1] = SYN_ULTRA_XFER_NS_1;
11711 asc_dvc->sdtr_period_tbl[2] = SYN_ULTRA_XFER_NS_2;
11712 asc_dvc->sdtr_period_tbl[3] = SYN_ULTRA_XFER_NS_3;
11713 asc_dvc->sdtr_period_tbl[4] = SYN_ULTRA_XFER_NS_4;
11714 asc_dvc->sdtr_period_tbl[5] = SYN_ULTRA_XFER_NS_5;
11715 asc_dvc->sdtr_period_tbl[6] = SYN_ULTRA_XFER_NS_6;
11716 asc_dvc->sdtr_period_tbl[7] = SYN_ULTRA_XFER_NS_7;
11717 asc_dvc->sdtr_period_tbl[8] = SYN_ULTRA_XFER_NS_8;
11718 asc_dvc->sdtr_period_tbl[9] = SYN_ULTRA_XFER_NS_9;
11719 asc_dvc->sdtr_period_tbl[10] = SYN_ULTRA_XFER_NS_10;
11720 asc_dvc->sdtr_period_tbl[11] = SYN_ULTRA_XFER_NS_11;
11721 asc_dvc->sdtr_period_tbl[12] = SYN_ULTRA_XFER_NS_12;
11722 asc_dvc->sdtr_period_tbl[13] = SYN_ULTRA_XFER_NS_13;
11723 asc_dvc->sdtr_period_tbl[14] = SYN_ULTRA_XFER_NS_14;
11724 asc_dvc->sdtr_period_tbl[15] = SYN_ULTRA_XFER_NS_15;
11725 asc_dvc->max_sdtr_index = 15;
11726 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) {
11727 AscSetExtraControl(iop_base,
11728 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
11729 } else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) {
11730 AscSetExtraControl(iop_base,
11731 (SEC_ACTIVE_NEGATE |
11732 SEC_ENABLE_FILTER));
11735 if (asc_dvc->bus_type == ASC_IS_PCI) {
11736 AscSetExtraControl(iop_base,
11737 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
11740 asc_dvc->cfg->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED;
11742 if ((asc_dvc->bus_type & ASC_IS_ISA) != 0) {
11743 if (chip_version >= ASC_CHIP_MIN_VER_ISA_PNP) {
11744 AscSetChipIFC(iop_base, IFC_INIT_DEFAULT);
11745 asc_dvc->bus_type = ASC_IS_ISAPNP;
11747 asc_dvc->cfg->isa_dma_channel =
11748 (uchar)AscGetIsaDmaChannel(iop_base);
11750 #endif /* CONFIG_ISA */
11751 for (i = 0; i <= ASC_MAX_TID; i++) {
11752 asc_dvc->cur_dvc_qng[i] = 0;
11753 asc_dvc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG;
11754 asc_dvc->scsiq_busy_head[i] = (ASC_SCSI_Q *)0L;
11755 asc_dvc->scsiq_busy_tail[i] = (ASC_SCSI_Q *)0L;
11756 asc_dvc->cfg->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG;
11761 static int __devinit AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg)
11765 for (retry = 0; retry < ASC_EEP_MAX_RETRY; retry++) {
11766 unsigned char read_back;
11767 AscSetChipEEPCmd(iop_base, cmd_reg);
11769 read_back = AscGetChipEEPCmd(iop_base);
11770 if (read_back == cmd_reg)
11776 static void __devinit AscWaitEEPRead(void)
11781 static ushort __devinit AscReadEEPWord(PortAddr iop_base, uchar addr)
11786 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
11788 cmd_reg = addr | ASC_EEP_CMD_READ;
11789 AscWriteEEPCmdReg(iop_base, cmd_reg);
11791 read_wval = AscGetChipEEPData(iop_base);
11796 static ushort __devinit
11797 AscGetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type)
11804 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
11807 wbuf = (ushort *)cfg_buf;
11809 /* Read two config words; Byte-swapping done by AscReadEEPWord(). */
11810 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
11811 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
11814 if (bus_type & ASC_IS_VL) {
11815 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
11816 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
11818 cfg_beg = ASC_EEP_DVC_CFG_BEG;
11819 cfg_end = ASC_EEP_MAX_DVC_ADDR;
11821 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
11822 wval = AscReadEEPWord(iop_base, (uchar)s_addr);
11823 if (s_addr <= uchar_end_in_config) {
11825 * Swap all char fields - must unswap bytes already swapped
11826 * by AscReadEEPWord().
11828 *wbuf = le16_to_cpu(wval);
11830 /* Don't swap word field at the end - cntl field. */
11833 sum += wval; /* Checksum treats all EEPROM data as words. */
11836 * Read the checksum word which will be compared against 'sum'
11837 * by the caller. Word field already swapped.
11839 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
11843 static int __devinit AscTestExternalLram(ASC_DVC_VAR *asc_dvc)
11850 iop_base = asc_dvc->iop_base;
11852 q_addr = ASC_QNO_TO_QADDR(241);
11853 saved_word = AscReadLramWord(iop_base, q_addr);
11854 AscSetChipLramAddr(iop_base, q_addr);
11855 AscSetChipLramData(iop_base, 0x55AA);
11857 AscSetChipLramAddr(iop_base, q_addr);
11858 if (AscGetChipLramData(iop_base) == 0x55AA) {
11860 AscWriteLramWord(iop_base, q_addr, saved_word);
11865 static void __devinit AscWaitEEPWrite(void)
11871 static int __devinit AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg)
11878 AscSetChipEEPData(iop_base, data_reg);
11880 read_back = AscGetChipEEPData(iop_base);
11881 if (read_back == data_reg) {
11884 if (retry++ > ASC_EEP_MAX_RETRY) {
11890 static ushort __devinit
11891 AscWriteEEPWord(PortAddr iop_base, uchar addr, ushort word_val)
11895 read_wval = AscReadEEPWord(iop_base, addr);
11896 if (read_wval != word_val) {
11897 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_ABLE);
11899 AscWriteEEPDataReg(iop_base, word_val);
11901 AscWriteEEPCmdReg(iop_base,
11902 (uchar)((uchar)ASC_EEP_CMD_WRITE | addr));
11904 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
11906 return (AscReadEEPWord(iop_base, addr));
11908 return (read_wval);
11911 static int __devinit
11912 AscSetEEPConfigOnce(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type)
11921 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
11923 wbuf = (ushort *)cfg_buf;
11926 /* Write two config words; AscWriteEEPWord() will swap bytes. */
11927 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
11929 if (*wbuf != AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
11933 if (bus_type & ASC_IS_VL) {
11934 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
11935 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
11937 cfg_beg = ASC_EEP_DVC_CFG_BEG;
11938 cfg_end = ASC_EEP_MAX_DVC_ADDR;
11940 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
11941 if (s_addr <= uchar_end_in_config) {
11943 * This is a char field. Swap char fields before they are
11944 * swapped again by AscWriteEEPWord().
11946 word = cpu_to_le16(*wbuf);
11948 AscWriteEEPWord(iop_base, (uchar)s_addr, word)) {
11952 /* Don't swap word field at the end - cntl field. */
11954 AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
11958 sum += *wbuf; /* Checksum calculated from word values. */
11960 /* Write checksum word. It will be swapped by AscWriteEEPWord(). */
11962 if (sum != AscWriteEEPWord(iop_base, (uchar)s_addr, sum)) {
11966 /* Read EEPROM back again. */
11967 wbuf = (ushort *)cfg_buf;
11969 * Read two config words; Byte-swapping done by AscReadEEPWord().
11971 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
11972 if (*wbuf != AscReadEEPWord(iop_base, (uchar)s_addr)) {
11976 if (bus_type & ASC_IS_VL) {
11977 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
11978 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
11980 cfg_beg = ASC_EEP_DVC_CFG_BEG;
11981 cfg_end = ASC_EEP_MAX_DVC_ADDR;
11983 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
11984 if (s_addr <= uchar_end_in_config) {
11986 * Swap all char fields. Must unswap bytes already swapped
11987 * by AscReadEEPWord().
11990 le16_to_cpu(AscReadEEPWord
11991 (iop_base, (uchar)s_addr));
11993 /* Don't swap word field at the end - cntl field. */
11994 word = AscReadEEPWord(iop_base, (uchar)s_addr);
11996 if (*wbuf != word) {
12000 /* Read checksum; Byte swapping not needed. */
12001 if (AscReadEEPWord(iop_base, (uchar)s_addr) != sum) {
12007 static int __devinit
12008 AscSetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type)
12015 if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf,
12019 if (++retry > ASC_EEP_MAX_RETRY) {
12026 static ushort __devinit AscInitFromEEP(ASC_DVC_VAR *asc_dvc)
12028 ASCEEP_CONFIG eep_config_buf;
12029 ASCEEP_CONFIG *eep_config;
12033 ushort cfg_msw, cfg_lsw;
12037 iop_base = asc_dvc->iop_base;
12039 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE);
12040 AscStopQueueExe(iop_base);
12041 if ((AscStopChip(iop_base) == FALSE) ||
12042 (AscGetChipScsiCtrl(iop_base) != 0)) {
12043 asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE;
12044 AscResetChipAndScsiBus(asc_dvc);
12045 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
12047 if (AscIsChipHalted(iop_base) == FALSE) {
12048 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
12049 return (warn_code);
12051 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
12052 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
12053 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
12054 return (warn_code);
12056 eep_config = (ASCEEP_CONFIG *)&eep_config_buf;
12057 cfg_msw = AscGetChipCfgMsw(iop_base);
12058 cfg_lsw = AscGetChipCfgLsw(iop_base);
12059 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
12060 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
12061 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
12062 AscSetChipCfgMsw(iop_base, cfg_msw);
12064 chksum = AscGetEEPConfig(iop_base, eep_config, asc_dvc->bus_type);
12065 ASC_DBG1(1, "AscInitFromEEP: chksum 0x%x\n", chksum);
12069 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
12070 warn_code |= ASC_WARN_AUTO_CONFIG;
12071 if (asc_dvc->cfg->chip_version == 3) {
12072 if (eep_config->cfg_lsw != cfg_lsw) {
12073 warn_code |= ASC_WARN_EEPROM_RECOVER;
12074 eep_config->cfg_lsw =
12075 AscGetChipCfgLsw(iop_base);
12077 if (eep_config->cfg_msw != cfg_msw) {
12078 warn_code |= ASC_WARN_EEPROM_RECOVER;
12079 eep_config->cfg_msw =
12080 AscGetChipCfgMsw(iop_base);
12084 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
12085 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON;
12086 ASC_DBG1(1, "AscInitFromEEP: eep_config->chksum 0x%x\n",
12087 eep_config->chksum);
12088 if (chksum != eep_config->chksum) {
12089 if (AscGetChipVersion(iop_base, asc_dvc->bus_type) ==
12090 ASC_CHIP_VER_PCI_ULTRA_3050) {
12092 "AscInitFromEEP: chksum error ignored; EEPROM-less board\n");
12093 eep_config->init_sdtr = 0xFF;
12094 eep_config->disc_enable = 0xFF;
12095 eep_config->start_motor = 0xFF;
12096 eep_config->use_cmd_qng = 0;
12097 eep_config->max_total_qng = 0xF0;
12098 eep_config->max_tag_qng = 0x20;
12099 eep_config->cntl = 0xBFFF;
12100 ASC_EEP_SET_CHIP_ID(eep_config, 7);
12101 eep_config->no_scam = 0;
12102 eep_config->adapter_info[0] = 0;
12103 eep_config->adapter_info[1] = 0;
12104 eep_config->adapter_info[2] = 0;
12105 eep_config->adapter_info[3] = 0;
12106 eep_config->adapter_info[4] = 0;
12107 /* Indicate EEPROM-less board. */
12108 eep_config->adapter_info[5] = 0xBB;
12111 ("AscInitFromEEP: EEPROM checksum error; Will try to re-write EEPROM.\n");
12113 warn_code |= ASC_WARN_EEPROM_CHKSUM;
12116 asc_dvc->cfg->sdtr_enable = eep_config->init_sdtr;
12117 asc_dvc->cfg->disc_enable = eep_config->disc_enable;
12118 asc_dvc->cfg->cmd_qng_enabled = eep_config->use_cmd_qng;
12119 asc_dvc->cfg->isa_dma_speed = ASC_EEP_GET_DMA_SPD(eep_config);
12120 asc_dvc->start_motor = eep_config->start_motor;
12121 asc_dvc->dvc_cntl = eep_config->cntl;
12122 asc_dvc->no_scam = eep_config->no_scam;
12123 asc_dvc->cfg->adapter_info[0] = eep_config->adapter_info[0];
12124 asc_dvc->cfg->adapter_info[1] = eep_config->adapter_info[1];
12125 asc_dvc->cfg->adapter_info[2] = eep_config->adapter_info[2];
12126 asc_dvc->cfg->adapter_info[3] = eep_config->adapter_info[3];
12127 asc_dvc->cfg->adapter_info[4] = eep_config->adapter_info[4];
12128 asc_dvc->cfg->adapter_info[5] = eep_config->adapter_info[5];
12129 if (!AscTestExternalLram(asc_dvc)) {
12130 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) ==
12131 ASC_IS_PCI_ULTRA)) {
12132 eep_config->max_total_qng =
12133 ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
12134 eep_config->max_tag_qng =
12135 ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG;
12137 eep_config->cfg_msw |= 0x0800;
12139 AscSetChipCfgMsw(iop_base, cfg_msw);
12140 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG;
12141 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG;
12145 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) {
12146 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG;
12148 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) {
12149 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG;
12151 if (eep_config->max_tag_qng > eep_config->max_total_qng) {
12152 eep_config->max_tag_qng = eep_config->max_total_qng;
12154 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) {
12155 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC;
12157 asc_dvc->max_total_qng = eep_config->max_total_qng;
12158 if ((eep_config->use_cmd_qng & eep_config->disc_enable) !=
12159 eep_config->use_cmd_qng) {
12160 eep_config->disc_enable = eep_config->use_cmd_qng;
12161 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
12163 if (asc_dvc->bus_type & (ASC_IS_ISA | ASC_IS_VL | ASC_IS_EISA)) {
12164 asc_dvc->irq_no = AscGetChipIRQ(iop_base, asc_dvc->bus_type);
12166 ASC_EEP_SET_CHIP_ID(eep_config,
12167 ASC_EEP_GET_CHIP_ID(eep_config) & ASC_MAX_TID);
12168 asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config);
12169 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) &&
12170 !(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) {
12171 asc_dvc->host_init_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX;
12174 for (i = 0; i <= ASC_MAX_TID; i++) {
12175 asc_dvc->dos_int13_table[i] = eep_config->dos_int13_table[i];
12176 asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng;
12177 asc_dvc->cfg->sdtr_period_offset[i] =
12178 (uchar)(ASC_DEF_SDTR_OFFSET |
12179 (asc_dvc->host_init_sdtr_index << 4));
12181 eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
12183 if ((i = AscSetEEPConfig(iop_base, eep_config,
12184 asc_dvc->bus_type)) != 0) {
12186 ("AscInitFromEEP: Failed to re-write EEPROM with %d errors.\n",
12190 ("AscInitFromEEP: Successfully re-wrote EEPROM.\n");
12193 return (warn_code);
12196 static int __devinit AscInitGetConfig(asc_board_t *boardp)
12198 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
12199 unsigned short warn_code = 0;
12201 asc_dvc->init_state = ASC_INIT_STATE_BEG_GET_CFG;
12202 if (asc_dvc->err_code != 0)
12203 return asc_dvc->err_code;
12205 if (AscFindSignature(asc_dvc->iop_base)) {
12206 warn_code |= AscInitAscDvcVar(asc_dvc);
12207 warn_code |= AscInitFromEEP(asc_dvc);
12208 asc_dvc->init_state |= ASC_INIT_STATE_END_GET_CFG;
12209 if (asc_dvc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT)
12210 asc_dvc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
12212 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
12215 switch (warn_code) {
12216 case 0: /* No error */
12218 case ASC_WARN_IO_PORT_ROTATE:
12219 ASC_PRINT1("AscInitGetConfig: board %d: I/O port address "
12220 "modified\n", boardp->id);
12222 case ASC_WARN_AUTO_CONFIG:
12223 ASC_PRINT1("AscInitGetConfig: board %d: I/O port increment "
12224 "switch enabled\n", boardp->id);
12226 case ASC_WARN_EEPROM_CHKSUM:
12227 ASC_PRINT1("AscInitGetConfig: board %d: EEPROM checksum "
12228 "error\n", boardp->id);
12230 case ASC_WARN_IRQ_MODIFIED:
12231 ASC_PRINT1("AscInitGetConfig: board %d: IRQ modified\n",
12234 case ASC_WARN_CMD_QNG_CONFLICT:
12235 ASC_PRINT1("AscInitGetConfig: board %d: tag queuing enabled "
12236 "w/o disconnects\n", boardp->id);
12239 ASC_PRINT2("AscInitGetConfig: board %d: unknown warning: "
12240 "0x%x\n", boardp->id, warn_code);
12244 if (asc_dvc->err_code != 0) {
12245 ASC_PRINT3("AscInitGetConfig: board %d error: init_state 0x%x, "
12246 "err_code 0x%x\n", boardp->id, asc_dvc->init_state,
12247 asc_dvc->err_code);
12250 return asc_dvc->err_code;
12253 static int __devinit AscInitSetConfig(struct pci_dev *pdev, asc_board_t *boardp)
12255 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
12256 PortAddr iop_base = asc_dvc->iop_base;
12257 unsigned short cfg_msw;
12258 unsigned short warn_code = 0;
12260 asc_dvc->init_state |= ASC_INIT_STATE_BEG_SET_CFG;
12261 if (asc_dvc->err_code != 0)
12262 return asc_dvc->err_code;
12263 if (!AscFindSignature(asc_dvc->iop_base)) {
12264 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
12265 return asc_dvc->err_code;
12268 cfg_msw = AscGetChipCfgMsw(iop_base);
12269 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
12270 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
12271 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
12272 AscSetChipCfgMsw(iop_base, cfg_msw);
12274 if ((asc_dvc->cfg->cmd_qng_enabled & asc_dvc->cfg->disc_enable) !=
12275 asc_dvc->cfg->cmd_qng_enabled) {
12276 asc_dvc->cfg->disc_enable = asc_dvc->cfg->cmd_qng_enabled;
12277 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
12279 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
12280 warn_code |= ASC_WARN_AUTO_CONFIG;
12282 if ((asc_dvc->bus_type & (ASC_IS_ISA | ASC_IS_VL)) != 0) {
12283 if (AscSetChipIRQ(iop_base, asc_dvc->irq_no, asc_dvc->bus_type)
12284 != asc_dvc->irq_no) {
12285 asc_dvc->err_code |= ASC_IERR_SET_IRQ_NO;
12289 if (asc_dvc->bus_type & ASC_IS_PCI) {
12291 AscSetChipCfgMsw(iop_base, cfg_msw);
12292 if ((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) {
12294 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
12295 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
12296 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB;
12297 asc_dvc->bug_fix_cntl |=
12298 ASC_BUG_FIX_ASYN_USE_SYN;
12302 #endif /* CONFIG_PCI */
12303 if (asc_dvc->bus_type == ASC_IS_ISAPNP) {
12304 if (AscGetChipVersion(iop_base, asc_dvc->bus_type)
12305 == ASC_CHIP_VER_ASYN_BUG) {
12306 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
12309 if (AscSetChipScsiID(iop_base, asc_dvc->cfg->chip_scsi_id) !=
12310 asc_dvc->cfg->chip_scsi_id) {
12311 asc_dvc->err_code |= ASC_IERR_SET_SCSI_ID;
12314 if (asc_dvc->bus_type & ASC_IS_ISA) {
12315 AscSetIsaDmaChannel(iop_base, asc_dvc->cfg->isa_dma_channel);
12316 AscSetIsaDmaSpeed(iop_base, asc_dvc->cfg->isa_dma_speed);
12318 #endif /* CONFIG_ISA */
12320 asc_dvc->init_state |= ASC_INIT_STATE_END_SET_CFG;
12322 switch (warn_code) {
12323 case 0: /* No error. */
12325 case ASC_WARN_IO_PORT_ROTATE:
12326 ASC_PRINT1("AscInitSetConfig: board %d: I/O port address "
12327 "modified\n", boardp->id);
12329 case ASC_WARN_AUTO_CONFIG:
12330 ASC_PRINT1("AscInitSetConfig: board %d: I/O port increment "
12331 "switch enabled\n", boardp->id);
12333 case ASC_WARN_EEPROM_CHKSUM:
12334 ASC_PRINT1("AscInitSetConfig: board %d: EEPROM checksum "
12335 "error\n", boardp->id);
12337 case ASC_WARN_IRQ_MODIFIED:
12338 ASC_PRINT1("AscInitSetConfig: board %d: IRQ modified\n",
12341 case ASC_WARN_CMD_QNG_CONFLICT:
12342 ASC_PRINT1("AscInitSetConfig: board %d: tag queuing w/o "
12347 ASC_PRINT2("AscInitSetConfig: board %d: unknown warning: "
12348 "0x%x\n", boardp->id, warn_code);
12352 if (asc_dvc->err_code != 0) {
12353 ASC_PRINT3("AscInitSetConfig: board %d error: init_state 0x%x, "
12354 "err_code 0x%x\n", boardp->id, asc_dvc->init_state,
12355 asc_dvc->err_code);
12358 return asc_dvc->err_code;
12362 * EEPROM Configuration.
12364 * All drivers should use this structure to set the default EEPROM
12365 * configuration. The BIOS now uses this structure when it is built.
12366 * Additional structure information can be found in a_condor.h where
12367 * the structure is defined.
12369 * The *_Field_IsChar structs are needed to correct for endianness.
12370 * These values are read from the board 16 bits at a time directly
12371 * into the structs. Because some fields are char, the values will be
12372 * in the wrong order. The *_Field_IsChar tells when to flip the
12373 * bytes. Data read and written to PCI memory is automatically swapped
12374 * on big-endian platforms so char fields read as words are actually being
12375 * unswapped on big-endian platforms.
12377 static ADVEEP_3550_CONFIG Default_3550_EEPROM_Config __devinitdata = {
12378 ADV_EEPROM_BIOS_ENABLE, /* cfg_lsw */
12379 0x0000, /* cfg_msw */
12380 0xFFFF, /* disc_enable */
12381 0xFFFF, /* wdtr_able */
12382 0xFFFF, /* sdtr_able */
12383 0xFFFF, /* start_motor */
12384 0xFFFF, /* tagqng_able */
12385 0xFFFF, /* bios_scan */
12386 0, /* scam_tolerant */
12387 7, /* adapter_scsi_id */
12388 0, /* bios_boot_delay */
12389 3, /* scsi_reset_delay */
12390 0, /* bios_id_lun */
12391 0, /* termination */
12393 0xFFE7, /* bios_ctrl */
12394 0xFFFF, /* ultra_able */
12396 ASC_DEF_MAX_HOST_QNG, /* max_host_qng */
12397 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
12400 0, /* serial_number_word1 */
12401 0, /* serial_number_word2 */
12402 0, /* serial_number_word3 */
12404 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
12405 , /* oem_name[16] */
12406 0, /* dvc_err_code */
12407 0, /* adv_err_code */
12408 0, /* adv_err_addr */
12409 0, /* saved_dvc_err_code */
12410 0, /* saved_adv_err_code */
12411 0, /* saved_adv_err_addr */
12415 static ADVEEP_3550_CONFIG ADVEEP_3550_Config_Field_IsChar __devinitdata = {
12418 0, /* -disc_enable */
12421 0, /* start_motor */
12422 0, /* tagqng_able */
12424 0, /* scam_tolerant */
12425 1, /* adapter_scsi_id */
12426 1, /* bios_boot_delay */
12427 1, /* scsi_reset_delay */
12428 1, /* bios_id_lun */
12429 1, /* termination */
12432 0, /* ultra_able */
12434 1, /* max_host_qng */
12435 1, /* max_dvc_qng */
12438 0, /* serial_number_word1 */
12439 0, /* serial_number_word2 */
12440 0, /* serial_number_word3 */
12442 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
12443 , /* oem_name[16] */
12444 0, /* dvc_err_code */
12445 0, /* adv_err_code */
12446 0, /* adv_err_addr */
12447 0, /* saved_dvc_err_code */
12448 0, /* saved_adv_err_code */
12449 0, /* saved_adv_err_addr */
12453 static ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config __devinitdata = {
12454 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
12455 0x0000, /* 01 cfg_msw */
12456 0xFFFF, /* 02 disc_enable */
12457 0xFFFF, /* 03 wdtr_able */
12458 0x4444, /* 04 sdtr_speed1 */
12459 0xFFFF, /* 05 start_motor */
12460 0xFFFF, /* 06 tagqng_able */
12461 0xFFFF, /* 07 bios_scan */
12462 0, /* 08 scam_tolerant */
12463 7, /* 09 adapter_scsi_id */
12464 0, /* bios_boot_delay */
12465 3, /* 10 scsi_reset_delay */
12466 0, /* bios_id_lun */
12467 0, /* 11 termination_se */
12468 0, /* termination_lvd */
12469 0xFFE7, /* 12 bios_ctrl */
12470 0x4444, /* 13 sdtr_speed2 */
12471 0x4444, /* 14 sdtr_speed3 */
12472 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
12473 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
12474 0, /* 16 dvc_cntl */
12475 0x4444, /* 17 sdtr_speed4 */
12476 0, /* 18 serial_number_word1 */
12477 0, /* 19 serial_number_word2 */
12478 0, /* 20 serial_number_word3 */
12479 0, /* 21 check_sum */
12480 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
12481 , /* 22-29 oem_name[16] */
12482 0, /* 30 dvc_err_code */
12483 0, /* 31 adv_err_code */
12484 0, /* 32 adv_err_addr */
12485 0, /* 33 saved_dvc_err_code */
12486 0, /* 34 saved_adv_err_code */
12487 0, /* 35 saved_adv_err_addr */
12488 0, /* 36 reserved */
12489 0, /* 37 reserved */
12490 0, /* 38 reserved */
12491 0, /* 39 reserved */
12492 0, /* 40 reserved */
12493 0, /* 41 reserved */
12494 0, /* 42 reserved */
12495 0, /* 43 reserved */
12496 0, /* 44 reserved */
12497 0, /* 45 reserved */
12498 0, /* 46 reserved */
12499 0, /* 47 reserved */
12500 0, /* 48 reserved */
12501 0, /* 49 reserved */
12502 0, /* 50 reserved */
12503 0, /* 51 reserved */
12504 0, /* 52 reserved */
12505 0, /* 53 reserved */
12506 0, /* 54 reserved */
12507 0, /* 55 reserved */
12508 0, /* 56 cisptr_lsw */
12509 0, /* 57 cisprt_msw */
12510 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
12511 PCI_DEVICE_ID_38C0800_REV1, /* 59 subsysid */
12512 0, /* 60 reserved */
12513 0, /* 61 reserved */
12514 0, /* 62 reserved */
12515 0 /* 63 reserved */
12518 static ADVEEP_38C0800_CONFIG ADVEEP_38C0800_Config_Field_IsChar __devinitdata = {
12519 0, /* 00 cfg_lsw */
12520 0, /* 01 cfg_msw */
12521 0, /* 02 disc_enable */
12522 0, /* 03 wdtr_able */
12523 0, /* 04 sdtr_speed1 */
12524 0, /* 05 start_motor */
12525 0, /* 06 tagqng_able */
12526 0, /* 07 bios_scan */
12527 0, /* 08 scam_tolerant */
12528 1, /* 09 adapter_scsi_id */
12529 1, /* bios_boot_delay */
12530 1, /* 10 scsi_reset_delay */
12531 1, /* bios_id_lun */
12532 1, /* 11 termination_se */
12533 1, /* termination_lvd */
12534 0, /* 12 bios_ctrl */
12535 0, /* 13 sdtr_speed2 */
12536 0, /* 14 sdtr_speed3 */
12537 1, /* 15 max_host_qng */
12538 1, /* max_dvc_qng */
12539 0, /* 16 dvc_cntl */
12540 0, /* 17 sdtr_speed4 */
12541 0, /* 18 serial_number_word1 */
12542 0, /* 19 serial_number_word2 */
12543 0, /* 20 serial_number_word3 */
12544 0, /* 21 check_sum */
12545 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
12546 , /* 22-29 oem_name[16] */
12547 0, /* 30 dvc_err_code */
12548 0, /* 31 adv_err_code */
12549 0, /* 32 adv_err_addr */
12550 0, /* 33 saved_dvc_err_code */
12551 0, /* 34 saved_adv_err_code */
12552 0, /* 35 saved_adv_err_addr */
12553 0, /* 36 reserved */
12554 0, /* 37 reserved */
12555 0, /* 38 reserved */
12556 0, /* 39 reserved */
12557 0, /* 40 reserved */
12558 0, /* 41 reserved */
12559 0, /* 42 reserved */
12560 0, /* 43 reserved */
12561 0, /* 44 reserved */
12562 0, /* 45 reserved */
12563 0, /* 46 reserved */
12564 0, /* 47 reserved */
12565 0, /* 48 reserved */
12566 0, /* 49 reserved */
12567 0, /* 50 reserved */
12568 0, /* 51 reserved */
12569 0, /* 52 reserved */
12570 0, /* 53 reserved */
12571 0, /* 54 reserved */
12572 0, /* 55 reserved */
12573 0, /* 56 cisptr_lsw */
12574 0, /* 57 cisprt_msw */
12575 0, /* 58 subsysvid */
12576 0, /* 59 subsysid */
12577 0, /* 60 reserved */
12578 0, /* 61 reserved */
12579 0, /* 62 reserved */
12580 0 /* 63 reserved */
12583 static ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config __devinitdata = {
12584 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
12585 0x0000, /* 01 cfg_msw */
12586 0xFFFF, /* 02 disc_enable */
12587 0xFFFF, /* 03 wdtr_able */
12588 0x5555, /* 04 sdtr_speed1 */
12589 0xFFFF, /* 05 start_motor */
12590 0xFFFF, /* 06 tagqng_able */
12591 0xFFFF, /* 07 bios_scan */
12592 0, /* 08 scam_tolerant */
12593 7, /* 09 adapter_scsi_id */
12594 0, /* bios_boot_delay */
12595 3, /* 10 scsi_reset_delay */
12596 0, /* bios_id_lun */
12597 0, /* 11 termination_se */
12598 0, /* termination_lvd */
12599 0xFFE7, /* 12 bios_ctrl */
12600 0x5555, /* 13 sdtr_speed2 */
12601 0x5555, /* 14 sdtr_speed3 */
12602 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
12603 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
12604 0, /* 16 dvc_cntl */
12605 0x5555, /* 17 sdtr_speed4 */
12606 0, /* 18 serial_number_word1 */
12607 0, /* 19 serial_number_word2 */
12608 0, /* 20 serial_number_word3 */
12609 0, /* 21 check_sum */
12610 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
12611 , /* 22-29 oem_name[16] */
12612 0, /* 30 dvc_err_code */
12613 0, /* 31 adv_err_code */
12614 0, /* 32 adv_err_addr */
12615 0, /* 33 saved_dvc_err_code */
12616 0, /* 34 saved_adv_err_code */
12617 0, /* 35 saved_adv_err_addr */
12618 0, /* 36 reserved */
12619 0, /* 37 reserved */
12620 0, /* 38 reserved */
12621 0, /* 39 reserved */
12622 0, /* 40 reserved */
12623 0, /* 41 reserved */
12624 0, /* 42 reserved */
12625 0, /* 43 reserved */
12626 0, /* 44 reserved */
12627 0, /* 45 reserved */
12628 0, /* 46 reserved */
12629 0, /* 47 reserved */
12630 0, /* 48 reserved */
12631 0, /* 49 reserved */
12632 0, /* 50 reserved */
12633 0, /* 51 reserved */
12634 0, /* 52 reserved */
12635 0, /* 53 reserved */
12636 0, /* 54 reserved */
12637 0, /* 55 reserved */
12638 0, /* 56 cisptr_lsw */
12639 0, /* 57 cisprt_msw */
12640 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
12641 PCI_DEVICE_ID_38C1600_REV1, /* 59 subsysid */
12642 0, /* 60 reserved */
12643 0, /* 61 reserved */
12644 0, /* 62 reserved */
12645 0 /* 63 reserved */
12648 static ADVEEP_38C1600_CONFIG ADVEEP_38C1600_Config_Field_IsChar __devinitdata = {
12649 0, /* 00 cfg_lsw */
12650 0, /* 01 cfg_msw */
12651 0, /* 02 disc_enable */
12652 0, /* 03 wdtr_able */
12653 0, /* 04 sdtr_speed1 */
12654 0, /* 05 start_motor */
12655 0, /* 06 tagqng_able */
12656 0, /* 07 bios_scan */
12657 0, /* 08 scam_tolerant */
12658 1, /* 09 adapter_scsi_id */
12659 1, /* bios_boot_delay */
12660 1, /* 10 scsi_reset_delay */
12661 1, /* bios_id_lun */
12662 1, /* 11 termination_se */
12663 1, /* termination_lvd */
12664 0, /* 12 bios_ctrl */
12665 0, /* 13 sdtr_speed2 */
12666 0, /* 14 sdtr_speed3 */
12667 1, /* 15 max_host_qng */
12668 1, /* max_dvc_qng */
12669 0, /* 16 dvc_cntl */
12670 0, /* 17 sdtr_speed4 */
12671 0, /* 18 serial_number_word1 */
12672 0, /* 19 serial_number_word2 */
12673 0, /* 20 serial_number_word3 */
12674 0, /* 21 check_sum */
12675 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
12676 , /* 22-29 oem_name[16] */
12677 0, /* 30 dvc_err_code */
12678 0, /* 31 adv_err_code */
12679 0, /* 32 adv_err_addr */
12680 0, /* 33 saved_dvc_err_code */
12681 0, /* 34 saved_adv_err_code */
12682 0, /* 35 saved_adv_err_addr */
12683 0, /* 36 reserved */
12684 0, /* 37 reserved */
12685 0, /* 38 reserved */
12686 0, /* 39 reserved */
12687 0, /* 40 reserved */
12688 0, /* 41 reserved */
12689 0, /* 42 reserved */
12690 0, /* 43 reserved */
12691 0, /* 44 reserved */
12692 0, /* 45 reserved */
12693 0, /* 46 reserved */
12694 0, /* 47 reserved */
12695 0, /* 48 reserved */
12696 0, /* 49 reserved */
12697 0, /* 50 reserved */
12698 0, /* 51 reserved */
12699 0, /* 52 reserved */
12700 0, /* 53 reserved */
12701 0, /* 54 reserved */
12702 0, /* 55 reserved */
12703 0, /* 56 cisptr_lsw */
12704 0, /* 57 cisprt_msw */
12705 0, /* 58 subsysvid */
12706 0, /* 59 subsysid */
12707 0, /* 60 reserved */
12708 0, /* 61 reserved */
12709 0, /* 62 reserved */
12710 0 /* 63 reserved */
12715 * Wait for EEPROM command to complete
12717 static void __devinit AdvWaitEEPCmd(AdvPortAddr iop_base)
12721 for (eep_delay_ms = 0; eep_delay_ms < ADV_EEP_DELAY_MS; eep_delay_ms++) {
12722 if (AdvReadWordRegister(iop_base, IOPW_EE_CMD) &
12723 ASC_EEP_CMD_DONE) {
12728 if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) ==
12734 * Read the EEPROM from specified location
12736 static ushort __devinit AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr)
12738 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12739 ASC_EEP_CMD_READ | eep_word_addr);
12740 AdvWaitEEPCmd(iop_base);
12741 return AdvReadWordRegister(iop_base, IOPW_EE_DATA);
12745 * Write the EEPROM from 'cfg_buf'.
12748 AdvSet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf)
12751 ushort addr, chksum;
12752 ushort *charfields;
12754 wbuf = (ushort *)cfg_buf;
12755 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
12758 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
12759 AdvWaitEEPCmd(iop_base);
12762 * Write EEPROM from word 0 to word 20.
12764 for (addr = ADV_EEP_DVC_CFG_BEGIN;
12765 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
12768 if (*charfields++) {
12769 word = cpu_to_le16(*wbuf);
12773 chksum += *wbuf; /* Checksum is calculated from word values. */
12774 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12775 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12776 ASC_EEP_CMD_WRITE | addr);
12777 AdvWaitEEPCmd(iop_base);
12778 mdelay(ADV_EEP_DELAY_MS);
12782 * Write EEPROM checksum at word 21.
12784 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
12785 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
12786 AdvWaitEEPCmd(iop_base);
12791 * Write EEPROM OEM name at words 22 to 29.
12793 for (addr = ADV_EEP_DVC_CTL_BEGIN;
12794 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
12797 if (*charfields++) {
12798 word = cpu_to_le16(*wbuf);
12802 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12803 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12804 ASC_EEP_CMD_WRITE | addr);
12805 AdvWaitEEPCmd(iop_base);
12807 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
12808 AdvWaitEEPCmd(iop_base);
12812 * Write the EEPROM from 'cfg_buf'.
12815 AdvSet38C0800EEPConfig(AdvPortAddr iop_base, ADVEEP_38C0800_CONFIG *cfg_buf)
12818 ushort *charfields;
12819 ushort addr, chksum;
12821 wbuf = (ushort *)cfg_buf;
12822 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
12825 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
12826 AdvWaitEEPCmd(iop_base);
12829 * Write EEPROM from word 0 to word 20.
12831 for (addr = ADV_EEP_DVC_CFG_BEGIN;
12832 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
12835 if (*charfields++) {
12836 word = cpu_to_le16(*wbuf);
12840 chksum += *wbuf; /* Checksum is calculated from word values. */
12841 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12842 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12843 ASC_EEP_CMD_WRITE | addr);
12844 AdvWaitEEPCmd(iop_base);
12845 mdelay(ADV_EEP_DELAY_MS);
12849 * Write EEPROM checksum at word 21.
12851 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
12852 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
12853 AdvWaitEEPCmd(iop_base);
12858 * Write EEPROM OEM name at words 22 to 29.
12860 for (addr = ADV_EEP_DVC_CTL_BEGIN;
12861 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
12864 if (*charfields++) {
12865 word = cpu_to_le16(*wbuf);
12869 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12870 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12871 ASC_EEP_CMD_WRITE | addr);
12872 AdvWaitEEPCmd(iop_base);
12874 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
12875 AdvWaitEEPCmd(iop_base);
12879 * Write the EEPROM from 'cfg_buf'.
12882 AdvSet38C1600EEPConfig(AdvPortAddr iop_base, ADVEEP_38C1600_CONFIG *cfg_buf)
12885 ushort *charfields;
12886 ushort addr, chksum;
12888 wbuf = (ushort *)cfg_buf;
12889 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
12892 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
12893 AdvWaitEEPCmd(iop_base);
12896 * Write EEPROM from word 0 to word 20.
12898 for (addr = ADV_EEP_DVC_CFG_BEGIN;
12899 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
12902 if (*charfields++) {
12903 word = cpu_to_le16(*wbuf);
12907 chksum += *wbuf; /* Checksum is calculated from word values. */
12908 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12909 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12910 ASC_EEP_CMD_WRITE | addr);
12911 AdvWaitEEPCmd(iop_base);
12912 mdelay(ADV_EEP_DELAY_MS);
12916 * Write EEPROM checksum at word 21.
12918 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
12919 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
12920 AdvWaitEEPCmd(iop_base);
12925 * Write EEPROM OEM name at words 22 to 29.
12927 for (addr = ADV_EEP_DVC_CTL_BEGIN;
12928 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
12931 if (*charfields++) {
12932 word = cpu_to_le16(*wbuf);
12936 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12937 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12938 ASC_EEP_CMD_WRITE | addr);
12939 AdvWaitEEPCmd(iop_base);
12941 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
12942 AdvWaitEEPCmd(iop_base);
12946 * Read EEPROM configuration into the specified buffer.
12948 * Return a checksum based on the EEPROM configuration read.
12950 static ushort __devinit
12951 AdvGet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf)
12953 ushort wval, chksum;
12956 ushort *charfields;
12958 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
12959 wbuf = (ushort *)cfg_buf;
12962 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
12963 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
12964 wval = AdvReadEEPWord(iop_base, eep_addr);
12965 chksum += wval; /* Checksum is calculated from word values. */
12966 if (*charfields++) {
12967 *wbuf = le16_to_cpu(wval);
12972 /* Read checksum word. */
12973 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
12977 /* Read rest of EEPROM not covered by the checksum. */
12978 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
12979 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
12980 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
12981 if (*charfields++) {
12982 *wbuf = le16_to_cpu(*wbuf);
12989 * Read EEPROM configuration into the specified buffer.
12991 * Return a checksum based on the EEPROM configuration read.
12993 static ushort __devinit
12994 AdvGet38C0800EEPConfig(AdvPortAddr iop_base, ADVEEP_38C0800_CONFIG *cfg_buf)
12996 ushort wval, chksum;
12999 ushort *charfields;
13001 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
13002 wbuf = (ushort *)cfg_buf;
13005 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
13006 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
13007 wval = AdvReadEEPWord(iop_base, eep_addr);
13008 chksum += wval; /* Checksum is calculated from word values. */
13009 if (*charfields++) {
13010 *wbuf = le16_to_cpu(wval);
13015 /* Read checksum word. */
13016 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
13020 /* Read rest of EEPROM not covered by the checksum. */
13021 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
13022 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
13023 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
13024 if (*charfields++) {
13025 *wbuf = le16_to_cpu(*wbuf);
13032 * Read EEPROM configuration into the specified buffer.
13034 * Return a checksum based on the EEPROM configuration read.
13036 static ushort __devinit
13037 AdvGet38C1600EEPConfig(AdvPortAddr iop_base, ADVEEP_38C1600_CONFIG *cfg_buf)
13039 ushort wval, chksum;
13042 ushort *charfields;
13044 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
13045 wbuf = (ushort *)cfg_buf;
13048 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
13049 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
13050 wval = AdvReadEEPWord(iop_base, eep_addr);
13051 chksum += wval; /* Checksum is calculated from word values. */
13052 if (*charfields++) {
13053 *wbuf = le16_to_cpu(wval);
13058 /* Read checksum word. */
13059 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
13063 /* Read rest of EEPROM not covered by the checksum. */
13064 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
13065 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
13066 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
13067 if (*charfields++) {
13068 *wbuf = le16_to_cpu(*wbuf);
13075 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
13076 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
13077 * all of this is done.
13079 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
13081 * For a non-fatal error return a warning code. If there are no warnings
13082 * then 0 is returned.
13084 * Note: Chip is stopped on entry.
13086 static int __devinit AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc)
13088 AdvPortAddr iop_base;
13090 ADVEEP_3550_CONFIG eep_config;
13092 iop_base = asc_dvc->iop_base;
13097 * Read the board's EEPROM configuration.
13099 * Set default values if a bad checksum is found.
13101 if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum) {
13102 warn_code |= ASC_WARN_EEPROM_CHKSUM;
13105 * Set EEPROM default values.
13107 memcpy(&eep_config, &Default_3550_EEPROM_Config,
13108 sizeof(ADVEEP_3550_CONFIG));
13111 * Assume the 6 byte board serial number that was read from
13112 * EEPROM is correct even if the EEPROM checksum failed.
13114 eep_config.serial_number_word3 =
13115 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
13117 eep_config.serial_number_word2 =
13118 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
13120 eep_config.serial_number_word1 =
13121 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
13123 AdvSet3550EEPConfig(iop_base, &eep_config);
13126 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
13127 * EEPROM configuration that was read.
13129 * This is the mapping of EEPROM fields to Adv Library fields.
13131 asc_dvc->wdtr_able = eep_config.wdtr_able;
13132 asc_dvc->sdtr_able = eep_config.sdtr_able;
13133 asc_dvc->ultra_able = eep_config.ultra_able;
13134 asc_dvc->tagqng_able = eep_config.tagqng_able;
13135 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
13136 asc_dvc->max_host_qng = eep_config.max_host_qng;
13137 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
13138 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
13139 asc_dvc->start_motor = eep_config.start_motor;
13140 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
13141 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
13142 asc_dvc->no_scam = eep_config.scam_tolerant;
13143 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
13144 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
13145 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
13148 * Set the host maximum queuing (max. 253, min. 16) and the per device
13149 * maximum queuing (max. 63, min. 4).
13151 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
13152 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
13153 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
13154 /* If the value is zero, assume it is uninitialized. */
13155 if (eep_config.max_host_qng == 0) {
13156 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
13158 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
13162 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
13163 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
13164 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
13165 /* If the value is zero, assume it is uninitialized. */
13166 if (eep_config.max_dvc_qng == 0) {
13167 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
13169 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
13174 * If 'max_dvc_qng' is greater than 'max_host_qng', then
13175 * set 'max_dvc_qng' to 'max_host_qng'.
13177 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
13178 eep_config.max_dvc_qng = eep_config.max_host_qng;
13182 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
13183 * values based on possibly adjusted EEPROM values.
13185 asc_dvc->max_host_qng = eep_config.max_host_qng;
13186 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
13189 * If the EEPROM 'termination' field is set to automatic (0), then set
13190 * the ADV_DVC_CFG 'termination' field to automatic also.
13192 * If the termination is specified with a non-zero 'termination'
13193 * value check that a legal value is set and set the ADV_DVC_CFG
13194 * 'termination' field appropriately.
13196 if (eep_config.termination == 0) {
13197 asc_dvc->cfg->termination = 0; /* auto termination */
13199 /* Enable manual control with low off / high off. */
13200 if (eep_config.termination == 1) {
13201 asc_dvc->cfg->termination = TERM_CTL_SEL;
13203 /* Enable manual control with low off / high on. */
13204 } else if (eep_config.termination == 2) {
13205 asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H;
13207 /* Enable manual control with low on / high on. */
13208 } else if (eep_config.termination == 3) {
13209 asc_dvc->cfg->termination =
13210 TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L;
13213 * The EEPROM 'termination' field contains a bad value. Use
13214 * automatic termination instead.
13216 asc_dvc->cfg->termination = 0;
13217 warn_code |= ASC_WARN_EEPROM_TERMINATION;
13225 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
13226 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
13227 * all of this is done.
13229 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
13231 * For a non-fatal error return a warning code. If there are no warnings
13232 * then 0 is returned.
13234 * Note: Chip is stopped on entry.
13236 static int __devinit AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc)
13238 AdvPortAddr iop_base;
13240 ADVEEP_38C0800_CONFIG eep_config;
13241 uchar tid, termination;
13242 ushort sdtr_speed = 0;
13244 iop_base = asc_dvc->iop_base;
13249 * Read the board's EEPROM configuration.
13251 * Set default values if a bad checksum is found.
13253 if (AdvGet38C0800EEPConfig(iop_base, &eep_config) !=
13254 eep_config.check_sum) {
13255 warn_code |= ASC_WARN_EEPROM_CHKSUM;
13258 * Set EEPROM default values.
13260 memcpy(&eep_config, &Default_38C0800_EEPROM_Config,
13261 sizeof(ADVEEP_38C0800_CONFIG));
13264 * Assume the 6 byte board serial number that was read from
13265 * EEPROM is correct even if the EEPROM checksum failed.
13267 eep_config.serial_number_word3 =
13268 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
13270 eep_config.serial_number_word2 =
13271 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
13273 eep_config.serial_number_word1 =
13274 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
13276 AdvSet38C0800EEPConfig(iop_base, &eep_config);
13279 * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the
13280 * EEPROM configuration that was read.
13282 * This is the mapping of EEPROM fields to Adv Library fields.
13284 asc_dvc->wdtr_able = eep_config.wdtr_able;
13285 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
13286 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
13287 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
13288 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
13289 asc_dvc->tagqng_able = eep_config.tagqng_able;
13290 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
13291 asc_dvc->max_host_qng = eep_config.max_host_qng;
13292 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
13293 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
13294 asc_dvc->start_motor = eep_config.start_motor;
13295 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
13296 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
13297 asc_dvc->no_scam = eep_config.scam_tolerant;
13298 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
13299 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
13300 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
13303 * For every Target ID if any of its 'sdtr_speed[1234]' bits
13304 * are set, then set an 'sdtr_able' bit for it.
13306 asc_dvc->sdtr_able = 0;
13307 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
13309 sdtr_speed = asc_dvc->sdtr_speed1;
13310 } else if (tid == 4) {
13311 sdtr_speed = asc_dvc->sdtr_speed2;
13312 } else if (tid == 8) {
13313 sdtr_speed = asc_dvc->sdtr_speed3;
13314 } else if (tid == 12) {
13315 sdtr_speed = asc_dvc->sdtr_speed4;
13317 if (sdtr_speed & ADV_MAX_TID) {
13318 asc_dvc->sdtr_able |= (1 << tid);
13324 * Set the host maximum queuing (max. 253, min. 16) and the per device
13325 * maximum queuing (max. 63, min. 4).
13327 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
13328 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
13329 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
13330 /* If the value is zero, assume it is uninitialized. */
13331 if (eep_config.max_host_qng == 0) {
13332 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
13334 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
13338 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
13339 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
13340 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
13341 /* If the value is zero, assume it is uninitialized. */
13342 if (eep_config.max_dvc_qng == 0) {
13343 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
13345 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
13350 * If 'max_dvc_qng' is greater than 'max_host_qng', then
13351 * set 'max_dvc_qng' to 'max_host_qng'.
13353 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
13354 eep_config.max_dvc_qng = eep_config.max_host_qng;
13358 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
13359 * values based on possibly adjusted EEPROM values.
13361 asc_dvc->max_host_qng = eep_config.max_host_qng;
13362 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
13365 * If the EEPROM 'termination' field is set to automatic (0), then set
13366 * the ADV_DVC_CFG 'termination' field to automatic also.
13368 * If the termination is specified with a non-zero 'termination'
13369 * value check that a legal value is set and set the ADV_DVC_CFG
13370 * 'termination' field appropriately.
13372 if (eep_config.termination_se == 0) {
13373 termination = 0; /* auto termination for SE */
13375 /* Enable manual control with low off / high off. */
13376 if (eep_config.termination_se == 1) {
13379 /* Enable manual control with low off / high on. */
13380 } else if (eep_config.termination_se == 2) {
13381 termination = TERM_SE_HI;
13383 /* Enable manual control with low on / high on. */
13384 } else if (eep_config.termination_se == 3) {
13385 termination = TERM_SE;
13388 * The EEPROM 'termination_se' field contains a bad value.
13389 * Use automatic termination instead.
13392 warn_code |= ASC_WARN_EEPROM_TERMINATION;
13396 if (eep_config.termination_lvd == 0) {
13397 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
13399 /* Enable manual control with low off / high off. */
13400 if (eep_config.termination_lvd == 1) {
13401 asc_dvc->cfg->termination = termination;
13403 /* Enable manual control with low off / high on. */
13404 } else if (eep_config.termination_lvd == 2) {
13405 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
13407 /* Enable manual control with low on / high on. */
13408 } else if (eep_config.termination_lvd == 3) {
13409 asc_dvc->cfg->termination = termination | TERM_LVD;
13412 * The EEPROM 'termination_lvd' field contains a bad value.
13413 * Use automatic termination instead.
13415 asc_dvc->cfg->termination = termination;
13416 warn_code |= ASC_WARN_EEPROM_TERMINATION;
13424 * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and
13425 * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while
13426 * all of this is done.
13428 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
13430 * For a non-fatal error return a warning code. If there are no warnings
13431 * then 0 is returned.
13433 * Note: Chip is stopped on entry.
13435 static int __devinit AdvInitFrom38C1600EEP(ADV_DVC_VAR *asc_dvc)
13437 AdvPortAddr iop_base;
13439 ADVEEP_38C1600_CONFIG eep_config;
13440 uchar tid, termination;
13441 ushort sdtr_speed = 0;
13443 iop_base = asc_dvc->iop_base;
13448 * Read the board's EEPROM configuration.
13450 * Set default values if a bad checksum is found.
13452 if (AdvGet38C1600EEPConfig(iop_base, &eep_config) !=
13453 eep_config.check_sum) {
13454 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
13455 warn_code |= ASC_WARN_EEPROM_CHKSUM;
13458 * Set EEPROM default values.
13460 memcpy(&eep_config, &Default_38C1600_EEPROM_Config,
13461 sizeof(ADVEEP_38C1600_CONFIG));
13463 if (PCI_FUNC(pdev->devfn) != 0) {
13466 * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60
13467 * and old Mac system booting problem. The Expansion
13468 * ROM must be disabled in Function 1 for these systems
13470 eep_config.cfg_lsw &= ~ADV_EEPROM_BIOS_ENABLE;
13472 * Clear the INTAB (bit 11) if the GPIO 0 input
13473 * indicates the Function 1 interrupt line is wired
13476 * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input:
13477 * 1 - Function 1 interrupt line wired to INT A.
13478 * 0 - Function 1 interrupt line wired to INT B.
13480 * Note: Function 0 is always wired to INTA.
13481 * Put all 5 GPIO bits in input mode and then read
13482 * their input values.
13484 AdvWriteByteRegister(iop_base, IOPB_GPIO_CNTL, 0);
13485 ints = AdvReadByteRegister(iop_base, IOPB_GPIO_DATA);
13486 if ((ints & 0x01) == 0)
13487 eep_config.cfg_lsw &= ~ADV_EEPROM_INTAB;
13491 * Assume the 6 byte board serial number that was read from
13492 * EEPROM is correct even if the EEPROM checksum failed.
13494 eep_config.serial_number_word3 =
13495 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
13496 eep_config.serial_number_word2 =
13497 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
13498 eep_config.serial_number_word1 =
13499 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
13501 AdvSet38C1600EEPConfig(iop_base, &eep_config);
13505 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
13506 * EEPROM configuration that was read.
13508 * This is the mapping of EEPROM fields to Adv Library fields.
13510 asc_dvc->wdtr_able = eep_config.wdtr_able;
13511 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
13512 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
13513 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
13514 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
13515 asc_dvc->ppr_able = 0;
13516 asc_dvc->tagqng_able = eep_config.tagqng_able;
13517 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
13518 asc_dvc->max_host_qng = eep_config.max_host_qng;
13519 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
13520 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ASC_MAX_TID);
13521 asc_dvc->start_motor = eep_config.start_motor;
13522 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
13523 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
13524 asc_dvc->no_scam = eep_config.scam_tolerant;
13527 * For every Target ID if any of its 'sdtr_speed[1234]' bits
13528 * are set, then set an 'sdtr_able' bit for it.
13530 asc_dvc->sdtr_able = 0;
13531 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
13533 sdtr_speed = asc_dvc->sdtr_speed1;
13534 } else if (tid == 4) {
13535 sdtr_speed = asc_dvc->sdtr_speed2;
13536 } else if (tid == 8) {
13537 sdtr_speed = asc_dvc->sdtr_speed3;
13538 } else if (tid == 12) {
13539 sdtr_speed = asc_dvc->sdtr_speed4;
13541 if (sdtr_speed & ASC_MAX_TID) {
13542 asc_dvc->sdtr_able |= (1 << tid);
13548 * Set the host maximum queuing (max. 253, min. 16) and the per device
13549 * maximum queuing (max. 63, min. 4).
13551 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
13552 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
13553 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
13554 /* If the value is zero, assume it is uninitialized. */
13555 if (eep_config.max_host_qng == 0) {
13556 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
13558 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
13562 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
13563 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
13564 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
13565 /* If the value is zero, assume it is uninitialized. */
13566 if (eep_config.max_dvc_qng == 0) {
13567 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
13569 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
13574 * If 'max_dvc_qng' is greater than 'max_host_qng', then
13575 * set 'max_dvc_qng' to 'max_host_qng'.
13577 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
13578 eep_config.max_dvc_qng = eep_config.max_host_qng;
13582 * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng'
13583 * values based on possibly adjusted EEPROM values.
13585 asc_dvc->max_host_qng = eep_config.max_host_qng;
13586 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
13589 * If the EEPROM 'termination' field is set to automatic (0), then set
13590 * the ASC_DVC_CFG 'termination' field to automatic also.
13592 * If the termination is specified with a non-zero 'termination'
13593 * value check that a legal value is set and set the ASC_DVC_CFG
13594 * 'termination' field appropriately.
13596 if (eep_config.termination_se == 0) {
13597 termination = 0; /* auto termination for SE */
13599 /* Enable manual control with low off / high off. */
13600 if (eep_config.termination_se == 1) {
13603 /* Enable manual control with low off / high on. */
13604 } else if (eep_config.termination_se == 2) {
13605 termination = TERM_SE_HI;
13607 /* Enable manual control with low on / high on. */
13608 } else if (eep_config.termination_se == 3) {
13609 termination = TERM_SE;
13612 * The EEPROM 'termination_se' field contains a bad value.
13613 * Use automatic termination instead.
13616 warn_code |= ASC_WARN_EEPROM_TERMINATION;
13620 if (eep_config.termination_lvd == 0) {
13621 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
13623 /* Enable manual control with low off / high off. */
13624 if (eep_config.termination_lvd == 1) {
13625 asc_dvc->cfg->termination = termination;
13627 /* Enable manual control with low off / high on. */
13628 } else if (eep_config.termination_lvd == 2) {
13629 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
13631 /* Enable manual control with low on / high on. */
13632 } else if (eep_config.termination_lvd == 3) {
13633 asc_dvc->cfg->termination = termination | TERM_LVD;
13636 * The EEPROM 'termination_lvd' field contains a bad value.
13637 * Use automatic termination instead.
13639 asc_dvc->cfg->termination = termination;
13640 warn_code |= ASC_WARN_EEPROM_TERMINATION;
13648 * Initialize the ADV_DVC_VAR structure.
13650 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
13652 * For a non-fatal error return a warning code. If there are no warnings
13653 * then 0 is returned.
13655 static int __devinit
13656 AdvInitGetConfig(struct pci_dev *pdev, asc_board_t *boardp)
13658 ADV_DVC_VAR *asc_dvc = &boardp->dvc_var.adv_dvc_var;
13659 unsigned short warn_code = 0;
13660 AdvPortAddr iop_base = asc_dvc->iop_base;
13664 asc_dvc->err_code = 0;
13667 * Save the state of the PCI Configuration Command Register
13668 * "Parity Error Response Control" Bit. If the bit is clear (0),
13669 * in AdvInitAsc3550/38C0800Driver() tell the microcode to ignore
13670 * DMA parity errors.
13672 asc_dvc->cfg->control_flag = 0;
13673 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
13674 if ((cmd & PCI_COMMAND_PARITY) == 0)
13675 asc_dvc->cfg->control_flag |= CONTROL_FLAG_IGNORE_PERR;
13677 asc_dvc->cfg->lib_version = (ADV_LIB_VERSION_MAJOR << 8) |
13678 ADV_LIB_VERSION_MINOR;
13679 asc_dvc->cfg->chip_version =
13680 AdvGetChipVersion(iop_base, asc_dvc->bus_type);
13682 ASC_DBG2(1, "AdvInitGetConfig: iopb_chip_id_1: 0x%x 0x%x\n",
13683 (ushort)AdvReadByteRegister(iop_base, IOPB_CHIP_ID_1),
13684 (ushort)ADV_CHIP_ID_BYTE);
13686 ASC_DBG2(1, "AdvInitGetConfig: iopw_chip_id_0: 0x%x 0x%x\n",
13687 (ushort)AdvReadWordRegister(iop_base, IOPW_CHIP_ID_0),
13688 (ushort)ADV_CHIP_ID_WORD);
13691 * Reset the chip to start and allow register writes.
13693 if (AdvFindSignature(iop_base) == 0) {
13694 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
13698 * The caller must set 'chip_type' to a valid setting.
13700 if (asc_dvc->chip_type != ADV_CHIP_ASC3550 &&
13701 asc_dvc->chip_type != ADV_CHIP_ASC38C0800 &&
13702 asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
13703 asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE;
13710 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
13711 ADV_CTRL_REG_CMD_RESET);
13713 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
13714 ADV_CTRL_REG_CMD_WR_IO_REG);
13716 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
13717 status = AdvInitFrom38C1600EEP(asc_dvc);
13718 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
13719 status = AdvInitFrom38C0800EEP(asc_dvc);
13721 status = AdvInitFrom3550EEP(asc_dvc);
13723 warn_code |= status;
13726 if (warn_code != 0) {
13727 ASC_PRINT2("AdvInitGetConfig: board %d: warning: 0x%x\n",
13728 boardp->id, warn_code);
13731 if (asc_dvc->err_code) {
13732 ASC_PRINT2("AdvInitGetConfig: board %d error: err_code 0x%x\n",
13733 boardp->id, asc_dvc->err_code);
13736 return asc_dvc->err_code;
13740 static struct scsi_host_template advansys_template = {
13741 .proc_name = DRV_NAME,
13742 #ifdef CONFIG_PROC_FS
13743 .proc_info = advansys_proc_info,
13746 .info = advansys_info,
13747 .queuecommand = advansys_queuecommand,
13748 .eh_bus_reset_handler = advansys_reset,
13749 .bios_param = advansys_biosparam,
13750 .slave_configure = advansys_slave_configure,
13752 * Because the driver may control an ISA adapter 'unchecked_isa_dma'
13753 * must be set. The flag will be cleared in advansys_board_found
13754 * for non-ISA adapters.
13756 .unchecked_isa_dma = 1,
13758 * All adapters controlled by this driver are capable of large
13759 * scatter-gather lists. According to the mid-level SCSI documentation
13760 * this obviates any performance gain provided by setting
13761 * 'use_clustering'. But empirically while CPU utilization is increased
13762 * by enabling clustering, I/O throughput increases as well.
13764 .use_clustering = ENABLE_CLUSTERING,
13767 static int __devinit
13768 advansys_wide_init_chip(asc_board_t *boardp, ADV_DVC_VAR *adv_dvc_varp)
13771 adv_req_t *reqp = NULL;
13774 int warn_code, err_code;
13777 * Allocate buffer carrier structures. The total size
13778 * is about 4 KB, so allocate all at once.
13780 boardp->carrp = kmalloc(ADV_CARRIER_BUFSIZE, GFP_KERNEL);
13781 ASC_DBG1(1, "advansys_wide_init_chip: carrp 0x%p\n", boardp->carrp);
13783 if (!boardp->carrp)
13784 goto kmalloc_failed;
13787 * Allocate up to 'max_host_qng' request structures for the Wide
13788 * board. The total size is about 16 KB, so allocate all at once.
13789 * If the allocation fails decrement and try again.
13791 for (req_cnt = adv_dvc_varp->max_host_qng; req_cnt > 0; req_cnt--) {
13792 reqp = kmalloc(sizeof(adv_req_t) * req_cnt, GFP_KERNEL);
13794 ASC_DBG3(1, "advansys_wide_init_chip: reqp 0x%p, req_cnt %d, "
13795 "bytes %lu\n", reqp, req_cnt,
13796 (ulong)sizeof(adv_req_t) * req_cnt);
13803 goto kmalloc_failed;
13805 boardp->orig_reqp = reqp;
13808 * Allocate up to ADV_TOT_SG_BLOCK request structures for
13809 * the Wide board. Each structure is about 136 bytes.
13811 boardp->adv_sgblkp = NULL;
13812 for (sg_cnt = 0; sg_cnt < ADV_TOT_SG_BLOCK; sg_cnt++) {
13813 sgp = kmalloc(sizeof(adv_sgblk_t), GFP_KERNEL);
13818 sgp->next_sgblkp = boardp->adv_sgblkp;
13819 boardp->adv_sgblkp = sgp;
13823 ASC_DBG3(1, "advansys_wide_init_chip: sg_cnt %d * %u = %u bytes\n",
13824 sg_cnt, sizeof(adv_sgblk_t),
13825 (unsigned)(sizeof(adv_sgblk_t) * sg_cnt));
13827 if (!boardp->adv_sgblkp)
13828 goto kmalloc_failed;
13830 adv_dvc_varp->carrier_buf = boardp->carrp;
13833 * Point 'adv_reqp' to the request structures and
13834 * link them together.
13837 reqp[req_cnt].next_reqp = NULL;
13838 for (; req_cnt > 0; req_cnt--) {
13839 reqp[req_cnt - 1].next_reqp = &reqp[req_cnt];
13841 boardp->adv_reqp = &reqp[0];
13843 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
13844 ASC_DBG(2, "advansys_wide_init_chip: AdvInitAsc3550Driver()\n");
13845 warn_code = AdvInitAsc3550Driver(adv_dvc_varp);
13846 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
13847 ASC_DBG(2, "advansys_wide_init_chip: AdvInitAsc38C0800Driver()"
13849 warn_code = AdvInitAsc38C0800Driver(adv_dvc_varp);
13851 ASC_DBG(2, "advansys_wide_init_chip: AdvInitAsc38C1600Driver()"
13853 warn_code = AdvInitAsc38C1600Driver(adv_dvc_varp);
13855 err_code = adv_dvc_varp->err_code;
13857 if (warn_code || err_code) {
13858 ASC_PRINT3("advansys_wide_init_chip: board %d error: warn 0x%x,"
13859 " error 0x%x\n", boardp->id, warn_code, err_code);
13865 ASC_PRINT1("advansys_wide_init_chip: board %d error: kmalloc() "
13866 "failed\n", boardp->id);
13867 err_code = ADV_ERROR;
13872 static void advansys_wide_free_mem(asc_board_t *boardp)
13874 kfree(boardp->carrp);
13875 boardp->carrp = NULL;
13876 kfree(boardp->orig_reqp);
13877 boardp->orig_reqp = boardp->adv_reqp = NULL;
13878 while (boardp->adv_sgblkp) {
13879 adv_sgblk_t *sgp = boardp->adv_sgblkp;
13880 boardp->adv_sgblkp = sgp->next_sgblkp;
13885 static struct Scsi_Host *__devinit
13886 advansys_board_found(int iop, struct device *dev, int bus_type)
13888 struct Scsi_Host *shost;
13889 struct pci_dev *pdev = bus_type == ASC_IS_PCI ? to_pci_dev(dev) : NULL;
13890 asc_board_t *boardp;
13891 ASC_DVC_VAR *asc_dvc_varp = NULL;
13892 ADV_DVC_VAR *adv_dvc_varp = NULL;
13894 int warn_code, err_code;
13898 * Register the adapter, get its configuration, and
13901 ASC_DBG(2, "advansys_board_found: scsi_host_alloc()\n");
13902 shost = scsi_host_alloc(&advansys_template, sizeof(asc_board_t));
13906 /* Initialize private per board data */
13907 boardp = ASC_BOARDP(shost);
13908 memset(boardp, 0, sizeof(asc_board_t));
13909 boardp->id = asc_board_count++;
13910 spin_lock_init(&boardp->lock);
13914 * Handle both narrow and wide boards.
13916 * If a Wide board was detected, set the board structure
13917 * wide board flag. Set-up the board structure based on
13921 if (bus_type == ASC_IS_PCI &&
13922 (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW ||
13923 pdev->device == PCI_DEVICE_ID_38C0800_REV1 ||
13924 pdev->device == PCI_DEVICE_ID_38C1600_REV1)) {
13925 boardp->flags |= ASC_IS_WIDE_BOARD;
13927 #endif /* CONFIG_PCI */
13929 if (ASC_NARROW_BOARD(boardp)) {
13930 ASC_DBG(1, "advansys_board_found: narrow board\n");
13931 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
13932 asc_dvc_varp->bus_type = bus_type;
13933 asc_dvc_varp->drv_ptr = boardp;
13934 asc_dvc_varp->cfg = &boardp->dvc_cfg.asc_dvc_cfg;
13935 asc_dvc_varp->cfg->overrun_buf = &overrun_buf[0];
13936 asc_dvc_varp->iop_base = iop;
13939 ASC_DBG(1, "advansys_board_found: wide board\n");
13940 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
13941 adv_dvc_varp->drv_ptr = boardp;
13942 adv_dvc_varp->cfg = &boardp->dvc_cfg.adv_dvc_cfg;
13943 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW) {
13944 ASC_DBG(1, "advansys_board_found: ASC-3550\n");
13945 adv_dvc_varp->chip_type = ADV_CHIP_ASC3550;
13946 } else if (pdev->device == PCI_DEVICE_ID_38C0800_REV1) {
13947 ASC_DBG(1, "advansys_board_found: ASC-38C0800\n");
13948 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C0800;
13950 ASC_DBG(1, "advansys_board_found: ASC-38C1600\n");
13951 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C1600;
13954 boardp->asc_n_io_port = pci_resource_len(pdev, 1);
13955 boardp->ioremap_addr = ioremap(pci_resource_start(pdev, 1),
13956 boardp->asc_n_io_port);
13957 if (!boardp->ioremap_addr) {
13959 ("advansys_board_found: board %d: ioremap(%x, %d) returned NULL\n",
13960 boardp->id, pci_resource_start(pdev, 1),
13961 boardp->asc_n_io_port);
13964 adv_dvc_varp->iop_base = (AdvPortAddr)boardp->ioremap_addr
13965 ASC_DBG1(1, "advansys_board_found: iop_base: 0x%lx\n",
13966 adv_dvc_varp->iop_base);
13969 * Even though it isn't used to access wide boards, other
13970 * than for the debug line below, save I/O Port address so
13971 * that it can be reported.
13973 boardp->ioport = iop;
13975 ASC_DBG2(1, "advansys_board_found: iopb_chip_id_1 0x%x, "
13976 "iopw_chip_id_0 0x%x\n", (ushort)inp(iop + 1),
13977 (ushort)inpw(iop));
13978 #endif /* CONFIG_PCI */
13981 #ifdef CONFIG_PROC_FS
13983 * Allocate buffer for printing information from
13984 * /proc/scsi/advansys/[0...].
13986 boardp->prtbuf = kmalloc(ASC_PRTBUF_SIZE, GFP_KERNEL);
13987 if (!boardp->prtbuf) {
13988 ASC_PRINT2("advansys_board_found: board %d: kmalloc(%d) "
13989 "returned NULL\n", boardp->id, ASC_PRTBUF_SIZE);
13992 #endif /* CONFIG_PROC_FS */
13994 if (ASC_NARROW_BOARD(boardp)) {
13996 * Set the board bus type and PCI IRQ before
13997 * calling AscInitGetConfig().
13999 switch (asc_dvc_varp->bus_type) {
14002 shost->unchecked_isa_dma = TRUE;
14006 shost->unchecked_isa_dma = FALSE;
14010 shost->unchecked_isa_dma = FALSE;
14011 share_irq = IRQF_SHARED;
14013 #endif /* CONFIG_ISA */
14016 shost->irq = asc_dvc_varp->irq_no = pdev->irq;
14017 shost->unchecked_isa_dma = FALSE;
14018 share_irq = IRQF_SHARED;
14020 #endif /* CONFIG_PCI */
14023 ("advansys_board_found: board %d: unknown adapter type: %d\n",
14024 boardp->id, asc_dvc_varp->bus_type);
14025 shost->unchecked_isa_dma = TRUE;
14031 * NOTE: AscInitGetConfig() may change the board's
14032 * bus_type value. The bus_type value should no
14033 * longer be used. If the bus_type field must be
14034 * referenced only use the bit-wise AND operator "&".
14036 ASC_DBG(2, "advansys_board_found: AscInitGetConfig()\n");
14037 err_code = AscInitGetConfig(boardp);
14041 * For Wide boards set PCI information before calling
14042 * AdvInitGetConfig().
14044 shost->irq = adv_dvc_varp->irq_no = pdev->irq;
14045 shost->unchecked_isa_dma = FALSE;
14046 share_irq = IRQF_SHARED;
14047 ASC_DBG(2, "advansys_board_found: AdvInitGetConfig()\n");
14049 err_code = AdvInitGetConfig(pdev, boardp);
14050 #endif /* CONFIG_PCI */
14054 goto err_free_proc;
14057 * Save the EEPROM configuration so that it can be displayed
14058 * from /proc/scsi/advansys/[0...].
14060 if (ASC_NARROW_BOARD(boardp)) {
14065 * Set the adapter's target id bit in the 'init_tidmask' field.
14067 boardp->init_tidmask |=
14068 ADV_TID_TO_TIDMASK(asc_dvc_varp->cfg->chip_scsi_id);
14071 * Save EEPROM settings for the board.
14073 ep = &boardp->eep_config.asc_eep;
14075 ep->init_sdtr = asc_dvc_varp->cfg->sdtr_enable;
14076 ep->disc_enable = asc_dvc_varp->cfg->disc_enable;
14077 ep->use_cmd_qng = asc_dvc_varp->cfg->cmd_qng_enabled;
14078 ASC_EEP_SET_DMA_SPD(ep, asc_dvc_varp->cfg->isa_dma_speed);
14079 ep->start_motor = asc_dvc_varp->start_motor;
14080 ep->cntl = asc_dvc_varp->dvc_cntl;
14081 ep->no_scam = asc_dvc_varp->no_scam;
14082 ep->max_total_qng = asc_dvc_varp->max_total_qng;
14083 ASC_EEP_SET_CHIP_ID(ep, asc_dvc_varp->cfg->chip_scsi_id);
14084 /* 'max_tag_qng' is set to the same value for every device. */
14085 ep->max_tag_qng = asc_dvc_varp->cfg->max_tag_qng[0];
14086 ep->adapter_info[0] = asc_dvc_varp->cfg->adapter_info[0];
14087 ep->adapter_info[1] = asc_dvc_varp->cfg->adapter_info[1];
14088 ep->adapter_info[2] = asc_dvc_varp->cfg->adapter_info[2];
14089 ep->adapter_info[3] = asc_dvc_varp->cfg->adapter_info[3];
14090 ep->adapter_info[4] = asc_dvc_varp->cfg->adapter_info[4];
14091 ep->adapter_info[5] = asc_dvc_varp->cfg->adapter_info[5];
14094 * Modify board configuration.
14096 ASC_DBG(2, "advansys_board_found: AscInitSetConfig()\n");
14097 err_code = AscInitSetConfig(pdev, boardp);
14099 goto err_free_proc;
14102 * Finish initializing the 'Scsi_Host' structure.
14104 /* AscInitSetConfig() will set the IRQ for non-PCI boards. */
14105 if ((asc_dvc_varp->bus_type & ASC_IS_PCI) == 0) {
14106 shost->irq = asc_dvc_varp->irq_no;
14109 ADVEEP_3550_CONFIG *ep_3550;
14110 ADVEEP_38C0800_CONFIG *ep_38C0800;
14111 ADVEEP_38C1600_CONFIG *ep_38C1600;
14114 * Save Wide EEP Configuration Information.
14116 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
14117 ep_3550 = &boardp->eep_config.adv_3550_eep;
14119 ep_3550->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
14120 ep_3550->max_host_qng = adv_dvc_varp->max_host_qng;
14121 ep_3550->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
14122 ep_3550->termination = adv_dvc_varp->cfg->termination;
14123 ep_3550->disc_enable = adv_dvc_varp->cfg->disc_enable;
14124 ep_3550->bios_ctrl = adv_dvc_varp->bios_ctrl;
14125 ep_3550->wdtr_able = adv_dvc_varp->wdtr_able;
14126 ep_3550->sdtr_able = adv_dvc_varp->sdtr_able;
14127 ep_3550->ultra_able = adv_dvc_varp->ultra_able;
14128 ep_3550->tagqng_able = adv_dvc_varp->tagqng_able;
14129 ep_3550->start_motor = adv_dvc_varp->start_motor;
14130 ep_3550->scsi_reset_delay =
14131 adv_dvc_varp->scsi_reset_wait;
14132 ep_3550->serial_number_word1 =
14133 adv_dvc_varp->cfg->serial1;
14134 ep_3550->serial_number_word2 =
14135 adv_dvc_varp->cfg->serial2;
14136 ep_3550->serial_number_word3 =
14137 adv_dvc_varp->cfg->serial3;
14138 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
14139 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
14141 ep_38C0800->adapter_scsi_id =
14142 adv_dvc_varp->chip_scsi_id;
14143 ep_38C0800->max_host_qng = adv_dvc_varp->max_host_qng;
14144 ep_38C0800->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
14145 ep_38C0800->termination_lvd =
14146 adv_dvc_varp->cfg->termination;
14147 ep_38C0800->disc_enable =
14148 adv_dvc_varp->cfg->disc_enable;
14149 ep_38C0800->bios_ctrl = adv_dvc_varp->bios_ctrl;
14150 ep_38C0800->wdtr_able = adv_dvc_varp->wdtr_able;
14151 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
14152 ep_38C0800->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
14153 ep_38C0800->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
14154 ep_38C0800->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
14155 ep_38C0800->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
14156 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
14157 ep_38C0800->start_motor = adv_dvc_varp->start_motor;
14158 ep_38C0800->scsi_reset_delay =
14159 adv_dvc_varp->scsi_reset_wait;
14160 ep_38C0800->serial_number_word1 =
14161 adv_dvc_varp->cfg->serial1;
14162 ep_38C0800->serial_number_word2 =
14163 adv_dvc_varp->cfg->serial2;
14164 ep_38C0800->serial_number_word3 =
14165 adv_dvc_varp->cfg->serial3;
14167 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
14169 ep_38C1600->adapter_scsi_id =
14170 adv_dvc_varp->chip_scsi_id;
14171 ep_38C1600->max_host_qng = adv_dvc_varp->max_host_qng;
14172 ep_38C1600->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
14173 ep_38C1600->termination_lvd =
14174 adv_dvc_varp->cfg->termination;
14175 ep_38C1600->disc_enable =
14176 adv_dvc_varp->cfg->disc_enable;
14177 ep_38C1600->bios_ctrl = adv_dvc_varp->bios_ctrl;
14178 ep_38C1600->wdtr_able = adv_dvc_varp->wdtr_able;
14179 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
14180 ep_38C1600->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
14181 ep_38C1600->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
14182 ep_38C1600->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
14183 ep_38C1600->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
14184 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
14185 ep_38C1600->start_motor = adv_dvc_varp->start_motor;
14186 ep_38C1600->scsi_reset_delay =
14187 adv_dvc_varp->scsi_reset_wait;
14188 ep_38C1600->serial_number_word1 =
14189 adv_dvc_varp->cfg->serial1;
14190 ep_38C1600->serial_number_word2 =
14191 adv_dvc_varp->cfg->serial2;
14192 ep_38C1600->serial_number_word3 =
14193 adv_dvc_varp->cfg->serial3;
14197 * Set the adapter's target id bit in the 'init_tidmask' field.
14199 boardp->init_tidmask |=
14200 ADV_TID_TO_TIDMASK(adv_dvc_varp->chip_scsi_id);
14204 * Channels are numbered beginning with 0. For AdvanSys one host
14205 * structure supports one channel. Multi-channel boards have a
14206 * separate host structure for each channel.
14208 shost->max_channel = 0;
14209 if (ASC_NARROW_BOARD(boardp)) {
14210 shost->max_id = ASC_MAX_TID + 1;
14211 shost->max_lun = ASC_MAX_LUN + 1;
14212 shost->max_cmd_len = ASC_MAX_CDB_LEN;
14214 shost->io_port = asc_dvc_varp->iop_base;
14215 boardp->asc_n_io_port = ASC_IOADR_GAP;
14216 shost->this_id = asc_dvc_varp->cfg->chip_scsi_id;
14218 /* Set maximum number of queues the adapter can handle. */
14219 shost->can_queue = asc_dvc_varp->max_total_qng;
14221 shost->max_id = ADV_MAX_TID + 1;
14222 shost->max_lun = ADV_MAX_LUN + 1;
14223 shost->max_cmd_len = ADV_MAX_CDB_LEN;
14226 * Save the I/O Port address and length even though
14227 * I/O ports are not used to access Wide boards.
14228 * Instead the Wide boards are accessed with
14229 * PCI Memory Mapped I/O.
14231 shost->io_port = iop;
14233 shost->this_id = adv_dvc_varp->chip_scsi_id;
14235 /* Set maximum number of queues the adapter can handle. */
14236 shost->can_queue = adv_dvc_varp->max_host_qng;
14240 * Following v1.3.89, 'cmd_per_lun' is no longer needed
14241 * and should be set to zero.
14243 * But because of a bug introduced in v1.3.89 if the driver is
14244 * compiled as a module and 'cmd_per_lun' is zero, the Mid-Level
14245 * SCSI function 'allocate_device' will panic. To allow the driver
14246 * to work as a module in these kernels set 'cmd_per_lun' to 1.
14248 * Note: This is wrong. cmd_per_lun should be set to the depth
14249 * you want on untagged devices always.
14252 shost->cmd_per_lun = 1;
14254 shost->cmd_per_lun = 0;
14258 * Set the maximum number of scatter-gather elements the
14259 * adapter can handle.
14261 if (ASC_NARROW_BOARD(boardp)) {
14263 * Allow two commands with 'sg_tablesize' scatter-gather
14264 * elements to be executed simultaneously. This value is
14265 * the theoretical hardware limit. It may be decreased
14268 shost->sg_tablesize =
14269 (((asc_dvc_varp->max_total_qng - 2) / 2) *
14270 ASC_SG_LIST_PER_Q) + 1;
14272 shost->sg_tablesize = ADV_MAX_SG_LIST;
14276 * The value of 'sg_tablesize' can not exceed the SCSI
14277 * mid-level driver definition of SG_ALL. SG_ALL also
14278 * must not be exceeded, because it is used to define the
14279 * size of the scatter-gather table in 'struct asc_sg_head'.
14281 if (shost->sg_tablesize > SG_ALL) {
14282 shost->sg_tablesize = SG_ALL;
14285 ASC_DBG1(1, "advansys_board_found: sg_tablesize: %d\n", shost->sg_tablesize);
14287 /* BIOS start address. */
14288 if (ASC_NARROW_BOARD(boardp)) {
14289 shost->base = AscGetChipBiosAddress(asc_dvc_varp->iop_base,
14290 asc_dvc_varp->bus_type);
14293 * Fill-in BIOS board variables. The Wide BIOS saves
14294 * information in LRAM that is used by the driver.
14296 AdvReadWordLram(adv_dvc_varp->iop_base,
14297 BIOS_SIGNATURE, boardp->bios_signature);
14298 AdvReadWordLram(adv_dvc_varp->iop_base,
14299 BIOS_VERSION, boardp->bios_version);
14300 AdvReadWordLram(adv_dvc_varp->iop_base,
14301 BIOS_CODESEG, boardp->bios_codeseg);
14302 AdvReadWordLram(adv_dvc_varp->iop_base,
14303 BIOS_CODELEN, boardp->bios_codelen);
14306 "advansys_board_found: bios_signature 0x%x, bios_version 0x%x\n",
14307 boardp->bios_signature, boardp->bios_version);
14310 "advansys_board_found: bios_codeseg 0x%x, bios_codelen 0x%x\n",
14311 boardp->bios_codeseg, boardp->bios_codelen);
14314 * If the BIOS saved a valid signature, then fill in
14315 * the BIOS code segment base address.
14317 if (boardp->bios_signature == 0x55AA) {
14319 * Convert x86 realmode code segment to a linear
14320 * address by shifting left 4.
14322 shost->base = ((ulong)boardp->bios_codeseg << 4);
14329 * Register Board Resources - I/O Port, DMA, IRQ
14332 /* Register DMA Channel for Narrow boards. */
14333 shost->dma_channel = NO_ISA_DMA; /* Default to no ISA DMA. */
14335 if (ASC_NARROW_BOARD(boardp)) {
14336 /* Register DMA channel for ISA bus. */
14337 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
14338 shost->dma_channel = asc_dvc_varp->cfg->isa_dma_channel;
14339 ret = request_dma(shost->dma_channel, DRV_NAME);
14342 ("advansys_board_found: board %d: request_dma() %d failed %d\n",
14343 boardp->id, shost->dma_channel, ret);
14344 goto err_free_proc;
14346 AscEnableIsaDma(shost->dma_channel);
14349 #endif /* CONFIG_ISA */
14351 /* Register IRQ Number. */
14352 ASC_DBG1(2, "advansys_board_found: request_irq() %d\n", shost->irq);
14354 ret = request_irq(shost->irq, advansys_interrupt, share_irq,
14358 if (ret == -EBUSY) {
14360 ("advansys_board_found: board %d: request_irq(): IRQ 0x%x already in use.\n",
14361 boardp->id, shost->irq);
14362 } else if (ret == -EINVAL) {
14364 ("advansys_board_found: board %d: request_irq(): IRQ 0x%x not valid.\n",
14365 boardp->id, shost->irq);
14368 ("advansys_board_found: board %d: request_irq(): IRQ 0x%x failed with %d\n",
14369 boardp->id, shost->irq, ret);
14375 * Initialize board RISC chip and enable interrupts.
14377 if (ASC_NARROW_BOARD(boardp)) {
14378 ASC_DBG(2, "advansys_board_found: AscInitAsc1000Driver()\n");
14379 warn_code = AscInitAsc1000Driver(asc_dvc_varp);
14380 err_code = asc_dvc_varp->err_code;
14382 if (warn_code || err_code) {
14384 ("advansys_board_found: board %d error: init_state 0x%x, warn 0x%x, error 0x%x\n",
14386 asc_dvc_varp->init_state, warn_code, err_code);
14389 err_code = advansys_wide_init_chip(boardp, adv_dvc_varp);
14393 goto err_free_wide_mem;
14395 ASC_DBG_PRT_SCSI_HOST(2, shost);
14397 ret = scsi_add_host(shost, dev);
14399 goto err_free_wide_mem;
14401 scsi_scan_host(shost);
14405 advansys_wide_free_mem(boardp);
14406 free_irq(shost->irq, shost);
14408 if (shost->dma_channel != NO_ISA_DMA)
14409 free_dma(shost->dma_channel);
14411 kfree(boardp->prtbuf);
14413 if (boardp->ioremap_addr)
14414 iounmap(boardp->ioremap_addr);
14416 scsi_host_put(shost);
14421 * advansys_release()
14423 * Release resources allocated for a single AdvanSys adapter.
14425 static int advansys_release(struct Scsi_Host *shost)
14427 asc_board_t *boardp;
14429 ASC_DBG(1, "advansys_release: begin\n");
14430 scsi_remove_host(shost);
14431 boardp = ASC_BOARDP(shost);
14432 free_irq(shost->irq, shost);
14433 if (shost->dma_channel != NO_ISA_DMA) {
14434 ASC_DBG(1, "advansys_release: free_dma()\n");
14435 free_dma(shost->dma_channel);
14437 if (ASC_WIDE_BOARD(boardp)) {
14438 iounmap(boardp->ioremap_addr);
14439 advansys_wide_free_mem(boardp);
14441 kfree(boardp->prtbuf);
14442 scsi_host_put(shost);
14443 ASC_DBG(1, "advansys_release: end\n");
14447 #define ASC_IOADR_TABLE_MAX_IX 11
14449 static PortAddr _asc_def_iop_base[ASC_IOADR_TABLE_MAX_IX] __devinitdata = {
14450 0x100, 0x0110, 0x120, 0x0130, 0x140, 0x0150, 0x0190,
14451 0x0210, 0x0230, 0x0250, 0x0330
14454 static int __devinit advansys_isa_probe(struct device *dev, unsigned int id)
14456 PortAddr iop_base = _asc_def_iop_base[id];
14457 struct Scsi_Host *shost;
14459 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
14460 ASC_DBG1(1, "advansys_isa_match: I/O port 0x%x busy\n",
14464 ASC_DBG1(1, "advansys_isa_match: probing I/O port 0x%x\n", iop_base);
14465 if (!AscFindSignature(iop_base))
14467 if (!(AscGetChipVersion(iop_base, ASC_IS_ISA) & ASC_CHIP_VER_ISA_BIT))
14470 shost = advansys_board_found(iop_base, dev, ASC_IS_ISA);
14474 dev_set_drvdata(dev, shost);
14478 release_region(iop_base, ASC_IOADR_GAP);
14482 static int __devexit advansys_isa_remove(struct device *dev, unsigned int id)
14484 int ioport = _asc_def_iop_base[id];
14485 advansys_release(dev_get_drvdata(dev));
14486 release_region(ioport, ASC_IOADR_GAP);
14490 static struct isa_driver advansys_isa_driver = {
14491 .probe = advansys_isa_probe,
14492 .remove = __devexit_p(advansys_isa_remove),
14494 .owner = THIS_MODULE,
14499 static int __devinit advansys_vlb_probe(struct device *dev, unsigned int id)
14501 PortAddr iop_base = _asc_def_iop_base[id];
14502 struct Scsi_Host *shost;
14504 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
14505 ASC_DBG1(1, "advansys_vlb_match: I/O port 0x%x busy\n",
14509 ASC_DBG1(1, "advansys_vlb_match: probing I/O port 0x%x\n", iop_base);
14510 if (!AscFindSignature(iop_base))
14513 * I don't think this condition can actually happen, but the old
14514 * driver did it, and the chances of finding a VLB setup in 2007
14515 * to do testing with is slight to none.
14517 if (AscGetChipVersion(iop_base, ASC_IS_VL) > ASC_CHIP_MAX_VER_VL)
14520 shost = advansys_board_found(iop_base, dev, ASC_IS_VL);
14524 dev_set_drvdata(dev, shost);
14528 release_region(iop_base, ASC_IOADR_GAP);
14532 static struct isa_driver advansys_vlb_driver = {
14533 .probe = advansys_vlb_probe,
14534 .remove = __devexit_p(advansys_isa_remove),
14536 .owner = THIS_MODULE,
14537 .name = "advansys_vlb",
14541 static struct eisa_device_id advansys_eisa_table[] __devinitdata = {
14547 MODULE_DEVICE_TABLE(eisa, advansys_eisa_table);
14550 * EISA is a little more tricky than PCI; each EISA device may have two
14551 * channels, and this driver is written to make each channel its own Scsi_Host
14553 struct eisa_scsi_data {
14554 struct Scsi_Host *host[2];
14557 static int __devinit advansys_eisa_probe(struct device *dev)
14561 struct eisa_device *edev = to_eisa_device(dev);
14562 struct eisa_scsi_data *data;
14565 data = kzalloc(sizeof(*data), GFP_KERNEL);
14568 ioport = edev->base_addr + 0xc30;
14571 for (i = 0; i < 2; i++, ioport += 0x20) {
14572 if (!request_region(ioport, ASC_IOADR_GAP, DRV_NAME)) {
14573 printk(KERN_WARNING "Region %x-%x busy\n", ioport,
14574 ioport + ASC_IOADR_GAP - 1);
14577 if (!AscFindSignature(ioport)) {
14578 release_region(ioport, ASC_IOADR_GAP);
14583 * I don't know why we need to do this for EISA chips, but
14584 * not for any others. It looks to be equivalent to
14585 * AscGetChipCfgMsw, but I may have overlooked something,
14586 * so I'm not converting it until I get an EISA board to
14590 data->host[i] = advansys_board_found(ioport, dev, ASC_IS_EISA);
14591 if (data->host[i]) {
14594 release_region(ioport, ASC_IOADR_GAP);
14601 dev_set_drvdata(dev, data);
14608 static __devexit int advansys_eisa_remove(struct device *dev)
14611 struct eisa_scsi_data *data = dev_get_drvdata(dev);
14613 for (i = 0; i < 2; i++) {
14615 struct Scsi_Host *shost = data->host[i];
14618 ioport = shost->io_port;
14619 advansys_release(shost);
14620 release_region(ioport, ASC_IOADR_GAP);
14627 static struct eisa_driver advansys_eisa_driver = {
14628 .id_table = advansys_eisa_table,
14631 .probe = advansys_eisa_probe,
14632 .remove = __devexit_p(advansys_eisa_remove),
14636 /* PCI Devices supported by this driver */
14637 static struct pci_device_id advansys_pci_tbl[] __devinitdata = {
14638 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_1200A,
14639 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14640 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940,
14641 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14642 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940U,
14643 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14644 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940UW,
14645 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14646 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C0800_REV1,
14647 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14648 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C1600_REV1,
14649 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14653 MODULE_DEVICE_TABLE(pci, advansys_pci_tbl);
14655 static void __devinit advansys_set_latency(struct pci_dev *pdev)
14657 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
14658 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
14659 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0);
14662 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency);
14663 if (latency < 0x20)
14664 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20);
14668 static int __devinit
14669 advansys_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
14672 struct Scsi_Host *shost;
14674 err = pci_enable_device(pdev);
14677 err = pci_request_regions(pdev, DRV_NAME);
14679 goto disable_device;
14680 pci_set_master(pdev);
14681 advansys_set_latency(pdev);
14683 if (pci_resource_len(pdev, 0) == 0)
14686 ioport = pci_resource_start(pdev, 0);
14687 shost = advansys_board_found(ioport, &pdev->dev, ASC_IS_PCI);
14692 pci_set_drvdata(pdev, shost);
14697 pci_release_regions(pdev);
14699 pci_disable_device(pdev);
14704 static void __devexit advansys_pci_remove(struct pci_dev *pdev)
14706 advansys_release(pci_get_drvdata(pdev));
14707 pci_release_regions(pdev);
14708 pci_disable_device(pdev);
14711 static struct pci_driver advansys_pci_driver = {
14713 .id_table = advansys_pci_tbl,
14714 .probe = advansys_pci_probe,
14715 .remove = __devexit_p(advansys_pci_remove),
14718 static int __init advansys_init(void)
14722 error = isa_register_driver(&advansys_isa_driver,
14723 ASC_IOADR_TABLE_MAX_IX);
14727 error = isa_register_driver(&advansys_vlb_driver,
14728 ASC_IOADR_TABLE_MAX_IX);
14730 goto unregister_isa;
14732 error = eisa_driver_register(&advansys_eisa_driver);
14734 goto unregister_vlb;
14736 error = pci_register_driver(&advansys_pci_driver);
14738 goto unregister_eisa;
14743 eisa_driver_unregister(&advansys_eisa_driver);
14745 isa_unregister_driver(&advansys_vlb_driver);
14747 isa_unregister_driver(&advansys_isa_driver);
14752 static void __exit advansys_exit(void)
14754 pci_unregister_driver(&advansys_pci_driver);
14755 eisa_driver_unregister(&advansys_eisa_driver);
14756 isa_unregister_driver(&advansys_vlb_driver);
14757 isa_unregister_driver(&advansys_isa_driver);
14760 module_init(advansys_init);
14761 module_exit(advansys_exit);
14763 MODULE_LICENSE("GPL");