Pileus Git - ~andy/linux/blob - drivers/regulator/wm8350-regulator.c

   1 /*
   2  * wm8350.c  --  Voltage and current regulation for the Wolfson WM8350 PMIC
   3  *
   4  * Copyright 2007, 2008 Wolfson Microelectronics PLC.
   5  *
   6  * Author: Liam Girdwood
   7  *         linux@wolfsonmicro.com
   8  *
   9  *  This program is free software; you can redistribute  it and/or modify it
  10  *  under  the terms of  the GNU General  Public License as published by the
  11  *  Free Software Foundation;  either version 2 of the  License, or (at your
  12  *  option) any later version.
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/moduleparam.h>
  17 #include <linux/init.h>
  18 #include <linux/bitops.h>
  19 #include <linux/err.h>
  20 #include <linux/i2c.h>
  21 #include <linux/mfd/wm8350/core.h>
  22 #include <linux/mfd/wm8350/pmic.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/regulator/driver.h>
  25 #include <linux/regulator/machine.h>
  26
  27 /* Maximum value possible for VSEL */
  28 #define WM8350_DCDC_MAX_VSEL 0x66
  29
  30 /* Microamps */
  31 static const int isink_cur[] = {
  32         4,
  33         5,
  34         6,
  35         7,
  36         8,
  37         10,
  38         11,
  39         14,
  40         16,
  41         19,
  42         23,
  43         27,
  44         32,
  45         39,
  46         46,
  47         54,
  48         65,
  49         77,
  50         92,
  51         109,
  52         130,
  53         154,
  54         183,
  55         218,
  56         259,
  57         308,
  58         367,
  59         436,
  60         518,
  61         616,
  62         733,
  63         872,
  64         1037,
  65         1233,
  66         1466,
  67         1744,
  68         2073,
  69         2466,
  70         2933,
  71         3487,
  72         4147,
  73         4932,
  74         5865,
  75         6975,
  76         8294,
  77         9864,
  78         11730,
  79         13949,
  80         16589,
  81         19728,
  82         23460,
  83         27899,
  84         33178,
  85         39455,
  86         46920,
  87         55798,
  88         66355,
  89         78910,
  90         93840,
  91         111596,
  92         132710,
  93         157820,
  94         187681,
  95         223191
  96 };
  97
  98 static int get_isink_val(int min_uA, int max_uA, u16 *setting)
  99 {
 100         int i;
 101
 102         for (i = 0; i < ARRAY_SIZE(isink_cur); i++) {
 103                 if (min_uA <= isink_cur[i] && max_uA >= isink_cur[i]) {
 104                         *setting = i;
 105                         return 0;
 106                 }
 107         }
 108         return -EINVAL;
 109 }
 110
 111 static int wm8350_isink_set_current(struct regulator_dev *rdev, int min_uA,
 112         int max_uA)
 113 {
 114         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 115         int isink = rdev_get_id(rdev);
 116         u16 val, setting;
 117         int ret;
 118
 119         ret = get_isink_val(min_uA, max_uA, &setting);
 120         if (ret != 0)
 121                 return ret;
 122
 123         switch (isink) {
 124         case WM8350_ISINK_A:
 125                 val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_A) &
 126                     ~WM8350_CS1_ISEL_MASK;
 127                 wm8350_reg_write(wm8350, WM8350_CURRENT_SINK_DRIVER_A,
 128                                  val | setting);
 129                 break;
 130         case WM8350_ISINK_B:
 131                 val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_B) &
 132                     ~WM8350_CS1_ISEL_MASK;
 133                 wm8350_reg_write(wm8350, WM8350_CURRENT_SINK_DRIVER_B,
 134                                  val | setting);
 135                 break;
 136         default:
 137                 return -EINVAL;
 138         }
 139
 140         return 0;
 141 }
 142
 143 static int wm8350_isink_get_current(struct regulator_dev *rdev)
 144 {
 145         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 146         int isink = rdev_get_id(rdev);
 147         u16 val;
 148
 149         switch (isink) {
 150         case WM8350_ISINK_A:
 151                 val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_A) &
 152                     WM8350_CS1_ISEL_MASK;
 153                 break;
 154         case WM8350_ISINK_B:
 155                 val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_B) &
 156                     WM8350_CS1_ISEL_MASK;
 157                 break;
 158         default:
 159                 return 0;
 160         }
 161
 162         return isink_cur[val];
 163 }
 164
 165 /* turn on ISINK followed by DCDC */
 166 static int wm8350_isink_enable(struct regulator_dev *rdev)
 167 {
 168         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 169         int isink = rdev_get_id(rdev);
 170
 171         switch (isink) {
 172         case WM8350_ISINK_A:
 173                 switch (wm8350->pmic.isink_A_dcdc) {
 174                 case WM8350_DCDC_2:
 175                 case WM8350_DCDC_5:
 176                         wm8350_set_bits(wm8350, WM8350_POWER_MGMT_7,
 177                                         WM8350_CS1_ENA);
 178                         wm8350_set_bits(wm8350, WM8350_CSA_FLASH_CONTROL,
 179                                         WM8350_CS1_DRIVE);
 180                         wm8350_set_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
 181                                         1 << (wm8350->pmic.isink_A_dcdc -
 182                                               WM8350_DCDC_1));
 183                         break;
 184                 default:
 185                         return -EINVAL;
 186                 }
 187                 break;
 188         case WM8350_ISINK_B:
 189                 switch (wm8350->pmic.isink_B_dcdc) {
 190                 case WM8350_DCDC_2:
 191                 case WM8350_DCDC_5:
 192                         wm8350_set_bits(wm8350, WM8350_POWER_MGMT_7,
 193                                         WM8350_CS2_ENA);
 194                         wm8350_set_bits(wm8350, WM8350_CSB_FLASH_CONTROL,
 195                                         WM8350_CS2_DRIVE);
 196                         wm8350_set_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
 197                                         1 << (wm8350->pmic.isink_B_dcdc -
 198                                               WM8350_DCDC_1));
 199                         break;
 200                 default:
 201                         return -EINVAL;
 202                 }
 203                 break;
 204         default:
 205                 return -EINVAL;
 206         }
 207         return 0;
 208 }
 209
 210 static int wm8350_isink_disable(struct regulator_dev *rdev)
 211 {
 212         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 213         int isink = rdev_get_id(rdev);
 214
 215         switch (isink) {
 216         case WM8350_ISINK_A:
 217                 switch (wm8350->pmic.isink_A_dcdc) {
 218                 case WM8350_DCDC_2:
 219                 case WM8350_DCDC_5:
 220                         wm8350_clear_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
 221                                           1 << (wm8350->pmic.isink_A_dcdc -
 222                                                 WM8350_DCDC_1));
 223                         wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_7,
 224                                           WM8350_CS1_ENA);
 225                         break;
 226                 default:
 227                         return -EINVAL;
 228                 }
 229                 break;
 230         case WM8350_ISINK_B:
 231                 switch (wm8350->pmic.isink_B_dcdc) {
 232                 case WM8350_DCDC_2:
 233                 case WM8350_DCDC_5:
 234                         wm8350_clear_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
 235                                           1 << (wm8350->pmic.isink_B_dcdc -
 236                                                 WM8350_DCDC_1));
 237                         wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_7,
 238                                           WM8350_CS2_ENA);
 239                         break;
 240                 default:
 241                         return -EINVAL;
 242                 }
 243                 break;
 244         default:
 245                 return -EINVAL;
 246         }
 247         return 0;
 248 }
 249
 250 static int wm8350_isink_is_enabled(struct regulator_dev *rdev)
 251 {
 252         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 253         int isink = rdev_get_id(rdev);
 254
 255         switch (isink) {
 256         case WM8350_ISINK_A:
 257                 return wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_A) &
 258                     0x8000;
 259         case WM8350_ISINK_B:
 260                 return wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_B) &
 261                     0x8000;
 262         }
 263         return -EINVAL;
 264 }
 265
 266 static int wm8350_isink_enable_time(struct regulator_dev *rdev)
 267 {
 268         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 269         int isink = rdev_get_id(rdev);
 270         int reg;
 271
 272         switch (isink) {
 273         case WM8350_ISINK_A:
 274                 reg = wm8350_reg_read(wm8350, WM8350_CSA_FLASH_CONTROL);
 275                 break;
 276         case WM8350_ISINK_B:
 277                 reg = wm8350_reg_read(wm8350, WM8350_CSB_FLASH_CONTROL);
 278                 break;
 279         default:
 280                 return -EINVAL;
 281         }
 282
 283         if (reg & WM8350_CS1_FLASH_MODE) {
 284                 switch (reg & WM8350_CS1_ON_RAMP_MASK) {
 285                 case 0:
 286                         return 0;
 287                 case 1:
 288                         return 1950;
 289                 case 2:
 290                         return 3910;
 291                 case 3:
 292                         return 7800;
 293                 }
 294         } else {
 295                 switch (reg & WM8350_CS1_ON_RAMP_MASK) {
 296                 case 0:
 297                         return 0;
 298                 case 1:
 299                         return 250000;
 300                 case 2:
 301                         return 500000;
 302                 case 3:
 303                         return 1000000;
 304                 }
 305         }
 306
 307         return -EINVAL;
 308 }
 309
 310
 311 int wm8350_isink_set_flash(struct wm8350 *wm8350, int isink, u16 mode,
 312                            u16 trigger, u16 duration, u16 on_ramp, u16 off_ramp,
 313                            u16 drive)
 314 {
 315         switch (isink) {
 316         case WM8350_ISINK_A:
 317                 wm8350_reg_write(wm8350, WM8350_CSA_FLASH_CONTROL,
 318                                  (mode ? WM8350_CS1_FLASH_MODE : 0) |
 319                                  (trigger ? WM8350_CS1_TRIGSRC : 0) |
 320                                  duration | on_ramp | off_ramp | drive);
 321                 break;
 322         case WM8350_ISINK_B:
 323                 wm8350_reg_write(wm8350, WM8350_CSB_FLASH_CONTROL,
 324                                  (mode ? WM8350_CS2_FLASH_MODE : 0) |
 325                                  (trigger ? WM8350_CS2_TRIGSRC : 0) |
 326                                  duration | on_ramp | off_ramp | drive);
 327                 break;
 328         default:
 329                 return -EINVAL;
 330         }
 331         return 0;
 332 }
 333 EXPORT_SYMBOL_GPL(wm8350_isink_set_flash);
 334
 335 static int wm8350_dcdc_set_suspend_voltage(struct regulator_dev *rdev, int uV)
 336 {
 337         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 338         int sel, volt_reg, dcdc = rdev_get_id(rdev);
 339         u16 val;
 340
 341         dev_dbg(wm8350->dev, "%s %d mV %d\n", __func__, dcdc, uV / 1000);
 342
 343         switch (dcdc) {
 344         case WM8350_DCDC_1:
 345                 volt_reg = WM8350_DCDC1_LOW_POWER;
 346                 break;
 347         case WM8350_DCDC_3:
 348                 volt_reg = WM8350_DCDC3_LOW_POWER;
 349                 break;
 350         case WM8350_DCDC_4:
 351                 volt_reg = WM8350_DCDC4_LOW_POWER;
 352                 break;
 353         case WM8350_DCDC_6:
 354                 volt_reg = WM8350_DCDC6_LOW_POWER;
 355                 break;
 356         case WM8350_DCDC_2:
 357         case WM8350_DCDC_5:
 358         default:
 359                 return -EINVAL;
 360         }
 361
 362         sel = regulator_map_voltage_linear(rdev, uV, uV);
 363         if (sel < 0)
 364                 return -EINVAL;
 365
 366         /* all DCDCs have same mV bits */
 367         val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_DC1_VSEL_MASK;
 368         wm8350_reg_write(wm8350, volt_reg, val | sel);
 369         return 0;
 370 }
 371
 372 static int wm8350_dcdc_set_suspend_enable(struct regulator_dev *rdev)
 373 {
 374         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 375         int dcdc = rdev_get_id(rdev);
 376         u16 val;
 377
 378         switch (dcdc) {
 379         case WM8350_DCDC_1:
 380                 val = wm8350_reg_read(wm8350, WM8350_DCDC1_LOW_POWER)
 381                         & ~WM8350_DCDC_HIB_MODE_MASK;
 382                 wm8350_reg_write(wm8350, WM8350_DCDC1_LOW_POWER,
 383                         val | wm8350->pmic.dcdc1_hib_mode);
 384                 break;
 385         case WM8350_DCDC_3:
 386                 val = wm8350_reg_read(wm8350, WM8350_DCDC3_LOW_POWER)
 387                         & ~WM8350_DCDC_HIB_MODE_MASK;
 388                 wm8350_reg_write(wm8350, WM8350_DCDC3_LOW_POWER,
 389                         val | wm8350->pmic.dcdc3_hib_mode);
 390                 break;
 391         case WM8350_DCDC_4:
 392                 val = wm8350_reg_read(wm8350, WM8350_DCDC4_LOW_POWER)
 393                         & ~WM8350_DCDC_HIB_MODE_MASK;
 394                 wm8350_reg_write(wm8350, WM8350_DCDC4_LOW_POWER,
 395                         val | wm8350->pmic.dcdc4_hib_mode);
 396                 break;
 397         case WM8350_DCDC_6:
 398                 val = wm8350_reg_read(wm8350, WM8350_DCDC6_LOW_POWER)
 399                         & ~WM8350_DCDC_HIB_MODE_MASK;
 400                 wm8350_reg_write(wm8350, WM8350_DCDC6_LOW_POWER,
 401                         val | wm8350->pmic.dcdc6_hib_mode);
 402                 break;
 403         case WM8350_DCDC_2:
 404         case WM8350_DCDC_5:
 405         default:
 406                 return -EINVAL;
 407         }
 408
 409         return 0;
 410 }
 411
 412 static int wm8350_dcdc_set_suspend_disable(struct regulator_dev *rdev)
 413 {
 414         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 415         int dcdc = rdev_get_id(rdev);
 416         u16 val;
 417
 418         switch (dcdc) {
 419         case WM8350_DCDC_1:
 420                 val = wm8350_reg_read(wm8350, WM8350_DCDC1_LOW_POWER);
 421                 wm8350->pmic.dcdc1_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
 422                 wm8350_reg_write(wm8350, WM8350_DCDC1_LOW_POWER,
 423                                  val | WM8350_DCDC_HIB_MODE_DIS);
 424                 break;
 425         case WM8350_DCDC_3:
 426                 val = wm8350_reg_read(wm8350, WM8350_DCDC3_LOW_POWER);
 427                 wm8350->pmic.dcdc3_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
 428                 wm8350_reg_write(wm8350, WM8350_DCDC3_LOW_POWER,
 429                                  val | WM8350_DCDC_HIB_MODE_DIS);
 430                 break;
 431         case WM8350_DCDC_4:
 432                 val = wm8350_reg_read(wm8350, WM8350_DCDC4_LOW_POWER);
 433                 wm8350->pmic.dcdc4_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
 434                 wm8350_reg_write(wm8350, WM8350_DCDC4_LOW_POWER,
 435                                  val | WM8350_DCDC_HIB_MODE_DIS);
 436                 break;
 437         case WM8350_DCDC_6:
 438                 val = wm8350_reg_read(wm8350, WM8350_DCDC6_LOW_POWER);
 439                 wm8350->pmic.dcdc6_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
 440                 wm8350_reg_write(wm8350, WM8350_DCDC6_LOW_POWER,
 441                                  val | WM8350_DCDC_HIB_MODE_DIS);
 442                 break;
 443         case WM8350_DCDC_2:
 444         case WM8350_DCDC_5:
 445         default:
 446                 return -EINVAL;
 447         }
 448
 449         return 0;
 450 }
 451
 452 static int wm8350_dcdc25_set_suspend_enable(struct regulator_dev *rdev)
 453 {
 454         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 455         int dcdc = rdev_get_id(rdev);
 456         u16 val;
 457
 458         switch (dcdc) {
 459         case WM8350_DCDC_2:
 460                 val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL)
 461                     & ~WM8350_DC2_HIB_MODE_MASK;
 462                 wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val |
 463                     (WM8350_DC2_HIB_MODE_ACTIVE << WM8350_DC2_HIB_MODE_SHIFT));
 464                 break;
 465         case WM8350_DCDC_5:
 466                 val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL)
 467                     & ~WM8350_DC5_HIB_MODE_MASK;
 468                 wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val |
 469                     (WM8350_DC5_HIB_MODE_ACTIVE << WM8350_DC5_HIB_MODE_SHIFT));
 470                 break;
 471         default:
 472                 return -EINVAL;
 473         }
 474         return 0;
 475 }
 476
 477 static int wm8350_dcdc25_set_suspend_disable(struct regulator_dev *rdev)
 478 {
 479         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 480         int dcdc = rdev_get_id(rdev);
 481         u16 val;
 482
 483         switch (dcdc) {
 484         case WM8350_DCDC_2:
 485                 val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL)
 486                     & ~WM8350_DC2_HIB_MODE_MASK;
 487                 wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val |
 488                     (WM8350_DC2_HIB_MODE_DISABLE << WM8350_DC2_HIB_MODE_SHIFT));
 489                 break;
 490         case WM8350_DCDC_5:
 491                 val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL)
 492                     & ~WM8350_DC5_HIB_MODE_MASK;
 493                 wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val |
 494                     (WM8350_DC5_HIB_MODE_DISABLE << WM8350_DC5_HIB_MODE_SHIFT));
 495                 break;
 496         default:
 497                 return -EINVAL;
 498         }
 499         return 0;
 500 }
 501
 502 static int wm8350_dcdc_set_suspend_mode(struct regulator_dev *rdev,
 503         unsigned int mode)
 504 {
 505         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 506         int dcdc = rdev_get_id(rdev);
 507         u16 *hib_mode;
 508
 509         switch (dcdc) {
 510         case WM8350_DCDC_1:
 511                 hib_mode = &wm8350->pmic.dcdc1_hib_mode;
 512                 break;
 513         case WM8350_DCDC_3:
 514                 hib_mode = &wm8350->pmic.dcdc3_hib_mode;
 515                 break;
 516         case WM8350_DCDC_4:
 517                 hib_mode = &wm8350->pmic.dcdc4_hib_mode;
 518                 break;
 519         case WM8350_DCDC_6:
 520                 hib_mode = &wm8350->pmic.dcdc6_hib_mode;
 521                 break;
 522         case WM8350_DCDC_2:
 523         case WM8350_DCDC_5:
 524         default:
 525                 return -EINVAL;
 526         }
 527
 528         switch (mode) {
 529         case REGULATOR_MODE_NORMAL:
 530                 *hib_mode = WM8350_DCDC_HIB_MODE_IMAGE;
 531                 break;
 532         case REGULATOR_MODE_IDLE:
 533                 *hib_mode = WM8350_DCDC_HIB_MODE_STANDBY;
 534                 break;
 535         case REGULATOR_MODE_STANDBY:
 536                 *hib_mode = WM8350_DCDC_HIB_MODE_LDO_IM;
 537                 break;
 538         default:
 539                 return -EINVAL;
 540         }
 541
 542         return 0;
 543 }
 544
 545 static const struct regulator_linear_range wm8350_ldo_ranges[] = {
 546         { .min_uV =  900000, .max_uV = 1650000, .min_sel =  0, .max_sel = 15,
 547           .uV_step =  50000 },
 548         { .min_uV = 1800000, .max_uV = 3300000, .min_sel = 16, .max_sel = 31,
 549           .uV_step = 100000 },
 550 };
 551
 552 static int wm8350_ldo_set_suspend_voltage(struct regulator_dev *rdev, int uV)
 553 {
 554         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 555         int sel, volt_reg, ldo = rdev_get_id(rdev);
 556         u16 val;
 557
 558         dev_dbg(wm8350->dev, "%s %d mV %d\n", __func__, ldo, uV / 1000);
 559
 560         switch (ldo) {
 561         case WM8350_LDO_1:
 562                 volt_reg = WM8350_LDO1_LOW_POWER;
 563                 break;
 564         case WM8350_LDO_2:
 565                 volt_reg = WM8350_LDO2_LOW_POWER;
 566                 break;
 567         case WM8350_LDO_3:
 568                 volt_reg = WM8350_LDO3_LOW_POWER;
 569                 break;
 570         case WM8350_LDO_4:
 571                 volt_reg = WM8350_LDO4_LOW_POWER;
 572                 break;
 573         default:
 574                 return -EINVAL;
 575         }
 576
 577         sel = regulator_map_voltage_linear_range(rdev, uV, uV);
 578         if (sel < 0)
 579                 return -EINVAL;
 580
 581         /* all LDOs have same mV bits */
 582         val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_VSEL_MASK;
 583         wm8350_reg_write(wm8350, volt_reg, val | sel);
 584         return 0;
 585 }
 586
 587 static int wm8350_ldo_set_suspend_enable(struct regulator_dev *rdev)
 588 {
 589         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 590         int volt_reg, ldo = rdev_get_id(rdev);
 591         u16 val;
 592
 593         switch (ldo) {
 594         case WM8350_LDO_1:
 595                 volt_reg = WM8350_LDO1_LOW_POWER;
 596                 break;
 597         case WM8350_LDO_2:
 598                 volt_reg = WM8350_LDO2_LOW_POWER;
 599                 break;
 600         case WM8350_LDO_3:
 601                 volt_reg = WM8350_LDO3_LOW_POWER;
 602                 break;
 603         case WM8350_LDO_4:
 604                 volt_reg = WM8350_LDO4_LOW_POWER;
 605                 break;
 606         default:
 607                 return -EINVAL;
 608         }
 609
 610         /* all LDOs have same mV bits */
 611         val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_HIB_MODE_MASK;
 612         wm8350_reg_write(wm8350, volt_reg, val);
 613         return 0;
 614 }
 615
 616 static int wm8350_ldo_set_suspend_disable(struct regulator_dev *rdev)
 617 {
 618         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 619         int volt_reg, ldo = rdev_get_id(rdev);
 620         u16 val;
 621
 622         switch (ldo) {
 623         case WM8350_LDO_1:
 624                 volt_reg = WM8350_LDO1_LOW_POWER;
 625                 break;
 626         case WM8350_LDO_2:
 627                 volt_reg = WM8350_LDO2_LOW_POWER;
 628                 break;
 629         case WM8350_LDO_3:
 630                 volt_reg = WM8350_LDO3_LOW_POWER;
 631                 break;
 632         case WM8350_LDO_4:
 633                 volt_reg = WM8350_LDO4_LOW_POWER;
 634                 break;
 635         default:
 636                 return -EINVAL;
 637         }
 638
 639         /* all LDOs have same mV bits */
 640         val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_HIB_MODE_MASK;
 641         wm8350_reg_write(wm8350, volt_reg, val | WM8350_LDO1_HIB_MODE_DIS);
 642         return 0;
 643 }
 644
 645 int wm8350_dcdc_set_slot(struct wm8350 *wm8350, int dcdc, u16 start,
 646                          u16 stop, u16 fault)
 647 {
 648         int slot_reg;
 649         u16 val;
 650
 651         dev_dbg(wm8350->dev, "%s %d start %d stop %d\n",
 652                 __func__, dcdc, start, stop);
 653
 654         /* slot valid ? */
 655         if (start > 15 || stop > 15)
 656                 return -EINVAL;
 657
 658         switch (dcdc) {
 659         case WM8350_DCDC_1:
 660                 slot_reg = WM8350_DCDC1_TIMEOUTS;
 661                 break;
 662         case WM8350_DCDC_2:
 663                 slot_reg = WM8350_DCDC2_TIMEOUTS;
 664                 break;
 665         case WM8350_DCDC_3:
 666                 slot_reg = WM8350_DCDC3_TIMEOUTS;
 667                 break;
 668         case WM8350_DCDC_4:
 669                 slot_reg = WM8350_DCDC4_TIMEOUTS;
 670                 break;
 671         case WM8350_DCDC_5:
 672                 slot_reg = WM8350_DCDC5_TIMEOUTS;
 673                 break;
 674         case WM8350_DCDC_6:
 675                 slot_reg = WM8350_DCDC6_TIMEOUTS;
 676                 break;
 677         default:
 678                 return -EINVAL;
 679         }
 680
 681         val = wm8350_reg_read(wm8350, slot_reg) &
 682             ~(WM8350_DC1_ENSLOT_MASK | WM8350_DC1_SDSLOT_MASK |
 683               WM8350_DC1_ERRACT_MASK);
 684         wm8350_reg_write(wm8350, slot_reg,
 685                          val | (start << WM8350_DC1_ENSLOT_SHIFT) |
 686                          (stop << WM8350_DC1_SDSLOT_SHIFT) |
 687                          (fault << WM8350_DC1_ERRACT_SHIFT));
 688
 689         return 0;
 690 }
 691 EXPORT_SYMBOL_GPL(wm8350_dcdc_set_slot);
 692
 693 int wm8350_ldo_set_slot(struct wm8350 *wm8350, int ldo, u16 start, u16 stop)
 694 {
 695         int slot_reg;
 696         u16 val;
 697
 698         dev_dbg(wm8350->dev, "%s %d start %d stop %d\n",
 699                 __func__, ldo, start, stop);
 700
 701         /* slot valid ? */
 702         if (start > 15 || stop > 15)
 703                 return -EINVAL;
 704
 705         switch (ldo) {
 706         case WM8350_LDO_1:
 707                 slot_reg = WM8350_LDO1_TIMEOUTS;
 708                 break;
 709         case WM8350_LDO_2:
 710                 slot_reg = WM8350_LDO2_TIMEOUTS;
 711                 break;
 712         case WM8350_LDO_3:
 713                 slot_reg = WM8350_LDO3_TIMEOUTS;
 714                 break;
 715         case WM8350_LDO_4:
 716                 slot_reg = WM8350_LDO4_TIMEOUTS;
 717                 break;
 718         default:
 719                 return -EINVAL;
 720         }
 721
 722         val = wm8350_reg_read(wm8350, slot_reg) & ~WM8350_LDO1_SDSLOT_MASK;
 723         wm8350_reg_write(wm8350, slot_reg, val | ((start << 10) | (stop << 6)));
 724         return 0;
 725 }
 726 EXPORT_SYMBOL_GPL(wm8350_ldo_set_slot);
 727
 728 int wm8350_dcdc25_set_mode(struct wm8350 *wm8350, int dcdc, u16 mode,
 729                            u16 ilim, u16 ramp, u16 feedback)
 730 {
 731         u16 val;
 732
 733         dev_dbg(wm8350->dev, "%s %d mode: %s %s\n", __func__, dcdc,
 734                 mode ? "normal" : "boost", ilim ? "low" : "normal");
 735
 736         switch (dcdc) {
 737         case WM8350_DCDC_2:
 738                 val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL)
 739                     & ~(WM8350_DC2_MODE_MASK | WM8350_DC2_ILIM_MASK |
 740                         WM8350_DC2_RMP_MASK | WM8350_DC2_FBSRC_MASK);
 741                 wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val |
 742                                  (mode << WM8350_DC2_MODE_SHIFT) |
 743                                  (ilim << WM8350_DC2_ILIM_SHIFT) |
 744                                  (ramp << WM8350_DC2_RMP_SHIFT) |
 745                                  (feedback << WM8350_DC2_FBSRC_SHIFT));
 746                 break;
 747         case WM8350_DCDC_5:
 748                 val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL)
 749                     & ~(WM8350_DC5_MODE_MASK | WM8350_DC5_ILIM_MASK |
 750                         WM8350_DC5_RMP_MASK | WM8350_DC5_FBSRC_MASK);
 751                 wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val |
 752                                  (mode << WM8350_DC5_MODE_SHIFT) |
 753                                  (ilim << WM8350_DC5_ILIM_SHIFT) |
 754                                  (ramp << WM8350_DC5_RMP_SHIFT) |
 755                                  (feedback << WM8350_DC5_FBSRC_SHIFT));
 756                 break;
 757         default:
 758                 return -EINVAL;
 759         }
 760
 761         return 0;
 762 }
 763 EXPORT_SYMBOL_GPL(wm8350_dcdc25_set_mode);
 764
 765 static int force_continuous_enable(struct wm8350 *wm8350, int dcdc, int enable)
 766 {
 767         int reg = 0, ret;
 768
 769         switch (dcdc) {
 770         case WM8350_DCDC_1:
 771                 reg = WM8350_DCDC1_FORCE_PWM;
 772                 break;
 773         case WM8350_DCDC_3:
 774                 reg = WM8350_DCDC3_FORCE_PWM;
 775                 break;
 776         case WM8350_DCDC_4:
 777                 reg = WM8350_DCDC4_FORCE_PWM;
 778                 break;
 779         case WM8350_DCDC_6:
 780                 reg = WM8350_DCDC6_FORCE_PWM;
 781                 break;
 782         default:
 783                 return -EINVAL;
 784         }
 785
 786         if (enable)
 787                 ret = wm8350_set_bits(wm8350, reg,
 788                         WM8350_DCDC1_FORCE_PWM_ENA);
 789         else
 790                 ret = wm8350_clear_bits(wm8350, reg,
 791                         WM8350_DCDC1_FORCE_PWM_ENA);
 792         return ret;
 793 }
 794
 795 static int wm8350_dcdc_set_mode(struct regulator_dev *rdev, unsigned int mode)
 796 {
 797         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 798         int dcdc = rdev_get_id(rdev);
 799         u16 val;
 800
 801         if (dcdc < WM8350_DCDC_1 || dcdc > WM8350_DCDC_6)
 802                 return -EINVAL;
 803
 804         if (dcdc == WM8350_DCDC_2 || dcdc == WM8350_DCDC_5)
 805                 return -EINVAL;
 806
 807         val = 1 << (dcdc - WM8350_DCDC_1);
 808
 809         switch (mode) {
 810         case REGULATOR_MODE_FAST:
 811                 /* force continuous mode */
 812                 wm8350_set_bits(wm8350, WM8350_DCDC_ACTIVE_OPTIONS, val);
 813                 wm8350_clear_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val);
 814                 force_continuous_enable(wm8350, dcdc, 1);
 815                 break;
 816         case REGULATOR_MODE_NORMAL:
 817                 /* active / pulse skipping */
 818                 wm8350_set_bits(wm8350, WM8350_DCDC_ACTIVE_OPTIONS, val);
 819                 wm8350_clear_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val);
 820                 force_continuous_enable(wm8350, dcdc, 0);
 821                 break;
 822         case REGULATOR_MODE_IDLE:
 823                 /* standby mode */
 824                 force_continuous_enable(wm8350, dcdc, 0);
 825                 wm8350_clear_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val);
 826                 wm8350_clear_bits(wm8350, WM8350_DCDC_ACTIVE_OPTIONS, val);
 827                 break;
 828         case REGULATOR_MODE_STANDBY:
 829                 /* LDO mode */
 830                 force_continuous_enable(wm8350, dcdc, 0);
 831                 wm8350_set_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val);
 832                 break;
 833         }
 834
 835         return 0;
 836 }
 837
 838 static unsigned int wm8350_dcdc_get_mode(struct regulator_dev *rdev)
 839 {
 840         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 841         int dcdc = rdev_get_id(rdev);
 842         u16 mask, sleep, active, force;
 843         int mode = REGULATOR_MODE_NORMAL;
 844         int reg;
 845
 846         switch (dcdc) {
 847         case WM8350_DCDC_1:
 848                 reg = WM8350_DCDC1_FORCE_PWM;
 849                 break;
 850         case WM8350_DCDC_3:
 851                 reg = WM8350_DCDC3_FORCE_PWM;
 852                 break;
 853         case WM8350_DCDC_4:
 854                 reg = WM8350_DCDC4_FORCE_PWM;
 855                 break;
 856         case WM8350_DCDC_6:
 857                 reg = WM8350_DCDC6_FORCE_PWM;
 858                 break;
 859         default:
 860                 return -EINVAL;
 861         }
 862
 863         mask = 1 << (dcdc - WM8350_DCDC_1);
 864         active = wm8350_reg_read(wm8350, WM8350_DCDC_ACTIVE_OPTIONS) & mask;
 865         force = wm8350_reg_read(wm8350, reg) & WM8350_DCDC1_FORCE_PWM_ENA;
 866         sleep = wm8350_reg_read(wm8350, WM8350_DCDC_SLEEP_OPTIONS) & mask;
 867
 868         dev_dbg(wm8350->dev, "mask %x active %x sleep %x force %x",
 869                 mask, active, sleep, force);
 870
 871         if (active && !sleep) {
 872                 if (force)
 873                         mode = REGULATOR_MODE_FAST;
 874                 else
 875                         mode = REGULATOR_MODE_NORMAL;
 876         } else if (!active && !sleep)
 877                 mode = REGULATOR_MODE_IDLE;
 878         else if (sleep)
 879                 mode = REGULATOR_MODE_STANDBY;
 880
 881         return mode;
 882 }
 883
 884 static unsigned int wm8350_ldo_get_mode(struct regulator_dev *rdev)
 885 {
 886         return REGULATOR_MODE_NORMAL;
 887 }
 888
 889 struct wm8350_dcdc_efficiency {
 890         int uA_load_min;
 891         int uA_load_max;
 892         unsigned int mode;
 893 };
 894
 895 static const struct wm8350_dcdc_efficiency dcdc1_6_efficiency[] = {
 896         {0, 10000, REGULATOR_MODE_STANDBY},       /* 0 - 10mA - LDO */
 897         {10000, 100000, REGULATOR_MODE_IDLE},     /* 10mA - 100mA - Standby */
 898         {100000, 1000000, REGULATOR_MODE_NORMAL}, /* > 100mA - Active */
 899         {-1, -1, REGULATOR_MODE_NORMAL},
 900 };
 901
 902 static const struct wm8350_dcdc_efficiency dcdc3_4_efficiency[] = {
 903         {0, 10000, REGULATOR_MODE_STANDBY},      /* 0 - 10mA - LDO */
 904         {10000, 100000, REGULATOR_MODE_IDLE},    /* 10mA - 100mA - Standby */
 905         {100000, 800000, REGULATOR_MODE_NORMAL}, /* > 100mA - Active */
 906         {-1, -1, REGULATOR_MODE_NORMAL},
 907 };
 908
 909 static unsigned int get_mode(int uA, const struct wm8350_dcdc_efficiency *eff)
 910 {
 911         int i = 0;
 912
 913         while (eff[i].uA_load_min != -1) {
 914                 if (uA >= eff[i].uA_load_min && uA <= eff[i].uA_load_max)
 915                         return eff[i].mode;
 916         }
 917         return REGULATOR_MODE_NORMAL;
 918 }
 919
 920 /* Query the regulator for it's most efficient mode @ uV,uA
 921  * WM8350 regulator efficiency is pretty similar over
 922  * different input and output uV.
 923  */
 924 static unsigned int wm8350_dcdc_get_optimum_mode(struct regulator_dev *rdev,
 925                                                  int input_uV, int output_uV,
 926                                                  int output_uA)
 927 {
 928         int dcdc = rdev_get_id(rdev), mode;
 929
 930         switch (dcdc) {
 931         case WM8350_DCDC_1:
 932         case WM8350_DCDC_6:
 933                 mode = get_mode(output_uA, dcdc1_6_efficiency);
 934                 break;
 935         case WM8350_DCDC_3:
 936         case WM8350_DCDC_4:
 937                 mode = get_mode(output_uA, dcdc3_4_efficiency);
 938                 break;
 939         default:
 940                 mode = REGULATOR_MODE_NORMAL;
 941                 break;
 942         }
 943         return mode;
 944 }
 945
 946 static struct regulator_ops wm8350_dcdc_ops = {
 947         .set_voltage_sel = regulator_set_voltage_sel_regmap,
 948         .get_voltage_sel = regulator_get_voltage_sel_regmap,
 949         .list_voltage = regulator_list_voltage_linear,
 950         .map_voltage = regulator_map_voltage_linear,
 951         .enable = regulator_enable_regmap,
 952         .disable = regulator_disable_regmap,
 953         .is_enabled = regulator_is_enabled_regmap,
 954         .get_mode = wm8350_dcdc_get_mode,
 955         .set_mode = wm8350_dcdc_set_mode,
 956         .get_optimum_mode = wm8350_dcdc_get_optimum_mode,
 957         .set_suspend_voltage = wm8350_dcdc_set_suspend_voltage,
 958         .set_suspend_enable = wm8350_dcdc_set_suspend_enable,
 959         .set_suspend_disable = wm8350_dcdc_set_suspend_disable,
 960         .set_suspend_mode = wm8350_dcdc_set_suspend_mode,
 961 };
 962
 963 static struct regulator_ops wm8350_dcdc2_5_ops = {
 964         .enable = regulator_enable_regmap,
 965         .disable = regulator_disable_regmap,
 966         .is_enabled = regulator_is_enabled_regmap,
 967         .set_suspend_enable = wm8350_dcdc25_set_suspend_enable,
 968         .set_suspend_disable = wm8350_dcdc25_set_suspend_disable,
 969 };
 970
 971 static struct regulator_ops wm8350_ldo_ops = {
 972         .map_voltage = regulator_map_voltage_linear_range,
 973         .set_voltage_sel = regulator_set_voltage_sel_regmap,
 974         .get_voltage_sel = regulator_get_voltage_sel_regmap,
 975         .list_voltage = regulator_list_voltage_linear_range,
 976         .enable = regulator_enable_regmap,
 977         .disable = regulator_disable_regmap,
 978         .is_enabled = regulator_is_enabled_regmap,
 979         .get_mode = wm8350_ldo_get_mode,
 980         .set_suspend_voltage = wm8350_ldo_set_suspend_voltage,
 981         .set_suspend_enable = wm8350_ldo_set_suspend_enable,
 982         .set_suspend_disable = wm8350_ldo_set_suspend_disable,
 983 };
 984
 985 static struct regulator_ops wm8350_isink_ops = {
 986         .set_current_limit = wm8350_isink_set_current,
 987         .get_current_limit = wm8350_isink_get_current,
 988         .enable = wm8350_isink_enable,
 989         .disable = wm8350_isink_disable,
 990         .is_enabled = wm8350_isink_is_enabled,
 991         .enable_time = wm8350_isink_enable_time,
 992 };
 993
 994 static const struct regulator_desc wm8350_reg[NUM_WM8350_REGULATORS] = {
 995         {
 996                 .name = "DCDC1",
 997                 .id = WM8350_DCDC_1,
 998                 .ops = &wm8350_dcdc_ops,
 999                 .irq = WM8350_IRQ_UV_DC1,
1000                 .type = REGULATOR_VOLTAGE,
1001                 .n_voltages = WM8350_DCDC_MAX_VSEL + 1,
1002                 .min_uV = 850000,
1003                 .uV_step = 25000,
1004                 .vsel_reg = WM8350_DCDC1_CONTROL,
1005                 .vsel_mask = WM8350_DC1_VSEL_MASK,
1006                 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1007                 .enable_mask = WM8350_DC1_ENA,
1008                 .owner = THIS_MODULE,
1009         },
1010         {
1011                 .name = "DCDC2",
1012                 .id = WM8350_DCDC_2,
1013                 .ops = &wm8350_dcdc2_5_ops,
1014                 .irq = WM8350_IRQ_UV_DC2,
1015                 .type = REGULATOR_VOLTAGE,
1016                 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1017                 .enable_mask = WM8350_DC2_ENA,
1018                 .owner = THIS_MODULE,
1019         },
1020         {
1021                 .name = "DCDC3",
1022                 .id = WM8350_DCDC_3,
1023                 .ops = &wm8350_dcdc_ops,
1024                 .irq = WM8350_IRQ_UV_DC3,
1025                 .type = REGULATOR_VOLTAGE,
1026                 .n_voltages = WM8350_DCDC_MAX_VSEL + 1,
1027                 .min_uV = 850000,
1028                 .uV_step = 25000,
1029                 .vsel_reg = WM8350_DCDC3_CONTROL,
1030                 .vsel_mask = WM8350_DC3_VSEL_MASK,
1031                 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1032                 .enable_mask = WM8350_DC3_ENA,
1033                 .owner = THIS_MODULE,
1034         },
1035         {
1036                 .name = "DCDC4",
1037                 .id = WM8350_DCDC_4,
1038                 .ops = &wm8350_dcdc_ops,
1039                 .irq = WM8350_IRQ_UV_DC4,
1040                 .type = REGULATOR_VOLTAGE,
1041                 .n_voltages = WM8350_DCDC_MAX_VSEL + 1,
1042                 .min_uV = 850000,
1043                 .uV_step = 25000,
1044                 .vsel_reg = WM8350_DCDC4_CONTROL,
1045                 .vsel_mask = WM8350_DC4_VSEL_MASK,
1046                 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1047                 .enable_mask = WM8350_DC4_ENA,
1048                 .owner = THIS_MODULE,
1049         },
1050         {
1051                 .name = "DCDC5",
1052                 .id = WM8350_DCDC_5,
1053                 .ops = &wm8350_dcdc2_5_ops,
1054                 .irq = WM8350_IRQ_UV_DC5,
1055                 .type = REGULATOR_VOLTAGE,
1056                 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1057                 .enable_mask = WM8350_DC5_ENA,
1058                 .owner = THIS_MODULE,
1059          },
1060         {
1061                 .name = "DCDC6",
1062                 .id = WM8350_DCDC_6,
1063                 .ops = &wm8350_dcdc_ops,
1064                 .irq = WM8350_IRQ_UV_DC6,
1065                 .type = REGULATOR_VOLTAGE,
1066                 .n_voltages = WM8350_DCDC_MAX_VSEL + 1,
1067                 .min_uV = 850000,
1068                 .uV_step = 25000,
1069                 .vsel_reg = WM8350_DCDC6_CONTROL,
1070                 .vsel_mask = WM8350_DC6_VSEL_MASK,
1071                 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1072                 .enable_mask = WM8350_DC6_ENA,
1073                 .owner = THIS_MODULE,
1074         },
1075         {
1076                 .name = "LDO1",
1077                 .id = WM8350_LDO_1,
1078                 .ops = &wm8350_ldo_ops,
1079                 .irq = WM8350_IRQ_UV_LDO1,
1080                 .type = REGULATOR_VOLTAGE,
1081                 .n_voltages = WM8350_LDO1_VSEL_MASK + 1,
1082                 .linear_ranges = wm8350_ldo_ranges,
1083                 .n_linear_ranges = ARRAY_SIZE(wm8350_ldo_ranges),
1084                 .vsel_reg = WM8350_LDO1_CONTROL,
1085                 .vsel_mask = WM8350_LDO1_VSEL_MASK,
1086                 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1087                 .enable_mask = WM8350_LDO1_ENA,
1088                 .owner = THIS_MODULE,
1089         },
1090         {
1091                 .name = "LDO2",
1092                 .id = WM8350_LDO_2,
1093                 .ops = &wm8350_ldo_ops,
1094                 .irq = WM8350_IRQ_UV_LDO2,
1095                 .type = REGULATOR_VOLTAGE,
1096                 .n_voltages = WM8350_LDO2_VSEL_MASK + 1,
1097                 .linear_ranges = wm8350_ldo_ranges,
1098                 .n_linear_ranges = ARRAY_SIZE(wm8350_ldo_ranges),
1099                 .vsel_reg = WM8350_LDO2_CONTROL,
1100                 .vsel_mask = WM8350_LDO2_VSEL_MASK,
1101                 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1102                 .enable_mask = WM8350_LDO2_ENA,
1103                 .owner = THIS_MODULE,
1104         },
1105         {
1106                 .name = "LDO3",
1107                 .id = WM8350_LDO_3,
1108                 .ops = &wm8350_ldo_ops,
1109                 .irq = WM8350_IRQ_UV_LDO3,
1110                 .type = REGULATOR_VOLTAGE,
1111                 .n_voltages = WM8350_LDO3_VSEL_MASK + 1,
1112                 .linear_ranges = wm8350_ldo_ranges,
1113                 .n_linear_ranges = ARRAY_SIZE(wm8350_ldo_ranges),
1114                 .vsel_reg = WM8350_LDO3_CONTROL,
1115                 .vsel_mask = WM8350_LDO3_VSEL_MASK,
1116                 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1117                 .enable_mask = WM8350_LDO3_ENA,
1118                 .owner = THIS_MODULE,
1119         },
1120         {
1121                 .name = "LDO4",
1122                 .id = WM8350_LDO_4,
1123                 .ops = &wm8350_ldo_ops,
1124                 .irq = WM8350_IRQ_UV_LDO4,
1125                 .type = REGULATOR_VOLTAGE,
1126                 .n_voltages = WM8350_LDO4_VSEL_MASK + 1,
1127                 .linear_ranges = wm8350_ldo_ranges,
1128                 .n_linear_ranges = ARRAY_SIZE(wm8350_ldo_ranges),
1129                 .vsel_reg = WM8350_LDO4_CONTROL,
1130                 .vsel_mask = WM8350_LDO4_VSEL_MASK,
1131                 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1132                 .enable_mask = WM8350_LDO4_ENA,
1133                 .owner = THIS_MODULE,
1134         },
1135         {
1136                 .name = "ISINKA",
1137                 .id = WM8350_ISINK_A,
1138                 .ops = &wm8350_isink_ops,
1139                 .irq = WM8350_IRQ_CS1,
1140                 .type = REGULATOR_CURRENT,
1141                 .owner = THIS_MODULE,
1142          },
1143         {
1144                 .name = "ISINKB",
1145                 .id = WM8350_ISINK_B,
1146                 .ops = &wm8350_isink_ops,
1147                 .irq = WM8350_IRQ_CS2,
1148                 .type = REGULATOR_CURRENT,
1149                 .owner = THIS_MODULE,
1150          },
1151 };
1152
1153 static irqreturn_t pmic_uv_handler(int irq, void *data)
1154 {
1155         struct regulator_dev *rdev = (struct regulator_dev *)data;
1156         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
1157
1158         mutex_lock(&rdev->mutex);
1159         if (irq == WM8350_IRQ_CS1 || irq == WM8350_IRQ_CS2)
1160                 regulator_notifier_call_chain(rdev,
1161                                               REGULATOR_EVENT_REGULATION_OUT,
1162                                               wm8350);
1163         else
1164                 regulator_notifier_call_chain(rdev,
1165                                               REGULATOR_EVENT_UNDER_VOLTAGE,
1166                                               wm8350);
1167         mutex_unlock(&rdev->mutex);
1168
1169         return IRQ_HANDLED;
1170 }
1171
1172 static int wm8350_regulator_probe(struct platform_device *pdev)
1173 {
1174         struct wm8350 *wm8350 = dev_get_drvdata(&pdev->dev);
1175         struct regulator_config config = { };
1176         struct regulator_dev *rdev;
1177         int ret;
1178         u16 val;
1179
1180         if (pdev->id < WM8350_DCDC_1 || pdev->id > WM8350_ISINK_B)
1181                 return -ENODEV;
1182
1183         /* do any regulatior specific init */
1184         switch (pdev->id) {
1185         case WM8350_DCDC_1:
1186                 val = wm8350_reg_read(wm8350, WM8350_DCDC1_LOW_POWER);
1187                 wm8350->pmic.dcdc1_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
1188                 break;
1189         case WM8350_DCDC_3:
1190                 val = wm8350_reg_read(wm8350, WM8350_DCDC3_LOW_POWER);
1191                 wm8350->pmic.dcdc3_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
1192                 break;
1193         case WM8350_DCDC_4:
1194                 val = wm8350_reg_read(wm8350, WM8350_DCDC4_LOW_POWER);
1195                 wm8350->pmic.dcdc4_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
1196                 break;
1197         case WM8350_DCDC_6:
1198                 val = wm8350_reg_read(wm8350, WM8350_DCDC6_LOW_POWER);
1199                 wm8350->pmic.dcdc6_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
1200                 break;
1201         }
1202
1203         config.dev = &pdev->dev;
1204         config.init_data = dev_get_platdata(&pdev->dev);
1205         config.driver_data = dev_get_drvdata(&pdev->dev);
1206         config.regmap = wm8350->regmap;
1207
1208         /* register regulator */
1209         rdev = regulator_register(&wm8350_reg[pdev->id], &config);
1210         if (IS_ERR(rdev)) {
1211                 dev_err(&pdev->dev, "failed to register %s\n",
1212                         wm8350_reg[pdev->id].name);
1213                 return PTR_ERR(rdev);
1214         }
1215
1216         /* register regulator IRQ */
1217         ret = wm8350_register_irq(wm8350, wm8350_reg[pdev->id].irq,
1218                                   pmic_uv_handler, 0, "UV", rdev);
1219         if (ret < 0) {
1220                 regulator_unregister(rdev);
1221                 dev_err(&pdev->dev, "failed to register regulator %s IRQ\n",
1222                         wm8350_reg[pdev->id].name);
1223                 return ret;
1224         }
1225
1226         return 0;
1227 }
1228
1229 static int wm8350_regulator_remove(struct platform_device *pdev)
1230 {
1231         struct regulator_dev *rdev = platform_get_drvdata(pdev);
1232         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
1233
1234         wm8350_free_irq(wm8350, wm8350_reg[pdev->id].irq, rdev);
1235
1236         regulator_unregister(rdev);
1237
1238         return 0;
1239 }
1240
1241 int wm8350_register_regulator(struct wm8350 *wm8350, int reg,
1242                               struct regulator_init_data *initdata)
1243 {
1244         struct platform_device *pdev;
1245         int ret;
1246         if (reg < 0 || reg >= NUM_WM8350_REGULATORS)
1247                 return -EINVAL;
1248
1249         if (wm8350->pmic.pdev[reg])
1250                 return -EBUSY;
1251
1252         if (reg >= WM8350_DCDC_1 && reg <= WM8350_DCDC_6 &&
1253             reg > wm8350->pmic.max_dcdc)
1254                 return -ENODEV;
1255         if (reg >= WM8350_ISINK_A && reg <= WM8350_ISINK_B &&
1256             reg > wm8350->pmic.max_isink)
1257                 return -ENODEV;
1258
1259         pdev = platform_device_alloc("wm8350-regulator", reg);
1260         if (!pdev)
1261                 return -ENOMEM;
1262
1263         wm8350->pmic.pdev[reg] = pdev;
1264
1265         initdata->driver_data = wm8350;
1266
1267         pdev->dev.platform_data = initdata;
1268         pdev->dev.parent = wm8350->dev;
1269         platform_set_drvdata(pdev, wm8350);
1270
1271         ret = platform_device_add(pdev);
1272
1273         if (ret != 0) {
1274                 dev_err(wm8350->dev, "Failed to register regulator %d: %d\n",
1275                         reg, ret);
1276                 platform_device_put(pdev);
1277                 wm8350->pmic.pdev[reg] = NULL;
1278         }
1279
1280         return ret;
1281 }
1282 EXPORT_SYMBOL_GPL(wm8350_register_regulator);
1283
1284 /**
1285  * wm8350_register_led - Register a WM8350 LED output
1286  *
1287  * @param wm8350 The WM8350 device to configure.
1288  * @param lednum LED device index to create.
1289  * @param dcdc The DCDC to use for the LED.
1290  * @param isink The ISINK to use for the LED.
1291  * @param pdata Configuration for the LED.
1292  *
1293  * The WM8350 supports the use of an ISINK together with a DCDC to
1294  * provide a power-efficient LED driver.  This function registers the
1295  * regulators and instantiates the platform device for a LED.  The
1296  * operating modes for the LED regulators must be configured using
1297  * wm8350_isink_set_flash(), wm8350_dcdc25_set_mode() and
1298  * wm8350_dcdc_set_slot() prior to calling this function.
1299  */
1300 int wm8350_register_led(struct wm8350 *wm8350, int lednum, int dcdc, int isink,
1301                         struct wm8350_led_platform_data *pdata)
1302 {
1303         struct wm8350_led *led;
1304         struct platform_device *pdev;
1305         int ret;
1306
1307         if (lednum >= ARRAY_SIZE(wm8350->pmic.led) || lednum < 0) {
1308                 dev_err(wm8350->dev, "Invalid LED index %d\n", lednum);
1309                 return -ENODEV;
1310         }
1311
1312         led = &wm8350->pmic.led[lednum];
1313
1314         if (led->pdev) {
1315                 dev_err(wm8350->dev, "LED %d already allocated\n", lednum);
1316                 return -EINVAL;
1317         }
1318
1319         pdev = platform_device_alloc("wm8350-led", lednum);
1320         if (pdev == NULL) {
1321                 dev_err(wm8350->dev, "Failed to allocate LED %d\n", lednum);
1322                 return -ENOMEM;
1323         }
1324
1325         led->isink_consumer.dev_name = dev_name(&pdev->dev);
1326         led->isink_consumer.supply = "led_isink";
1327         led->isink_init.num_consumer_supplies = 1;
1328         led->isink_init.consumer_supplies = &led->isink_consumer;
1329         led->isink_init.constraints.min_uA = 0;
1330         led->isink_init.constraints.max_uA = pdata->max_uA;
1331         led->isink_init.constraints.valid_ops_mask
1332                 = REGULATOR_CHANGE_CURRENT | REGULATOR_CHANGE_STATUS;
1333         led->isink_init.constraints.valid_modes_mask = REGULATOR_MODE_NORMAL;
1334         ret = wm8350_register_regulator(wm8350, isink, &led->isink_init);
1335         if (ret != 0) {
1336                 platform_device_put(pdev);
1337                 return ret;
1338         }
1339
1340         led->dcdc_consumer.dev_name = dev_name(&pdev->dev);
1341         led->dcdc_consumer.supply = "led_vcc";
1342         led->dcdc_init.num_consumer_supplies = 1;
1343         led->dcdc_init.consumer_supplies = &led->dcdc_consumer;
1344         led->dcdc_init.constraints.valid_modes_mask = REGULATOR_MODE_NORMAL;
1345         led->dcdc_init.constraints.valid_ops_mask =  REGULATOR_CHANGE_STATUS;
1346         ret = wm8350_register_regulator(wm8350, dcdc, &led->dcdc_init);
1347         if (ret != 0) {
1348                 platform_device_put(pdev);
1349                 return ret;
1350         }
1351
1352         switch (isink) {
1353         case WM8350_ISINK_A:
1354                 wm8350->pmic.isink_A_dcdc = dcdc;
1355                 break;
1356         case WM8350_ISINK_B:
1357                 wm8350->pmic.isink_B_dcdc = dcdc;
1358                 break;
1359         }
1360
1361         pdev->dev.platform_data = pdata;
1362         pdev->dev.parent = wm8350->dev;
1363         ret = platform_device_add(pdev);
1364         if (ret != 0) {
1365                 dev_err(wm8350->dev, "Failed to register LED %d: %d\n",
1366                         lednum, ret);
1367                 platform_device_put(pdev);
1368                 return ret;
1369         }
1370
1371         led->pdev = pdev;
1372
1373         return 0;
1374 }
1375 EXPORT_SYMBOL_GPL(wm8350_register_led);
1376
1377 static struct platform_driver wm8350_regulator_driver = {
1378         .probe = wm8350_regulator_probe,
1379         .remove = wm8350_regulator_remove,
1380         .driver         = {
1381                 .name   = "wm8350-regulator",
1382         },
1383 };
1384
1385 static int __init wm8350_regulator_init(void)
1386 {
1387         return platform_driver_register(&wm8350_regulator_driver);
1388 }
1389 subsys_initcall(wm8350_regulator_init);
1390
1391 static void __exit wm8350_regulator_exit(void)
1392 {
1393         platform_driver_unregister(&wm8350_regulator_driver);
1394 }
1395 module_exit(wm8350_regulator_exit);
1396
1397 /* Module information */
1398 MODULE_AUTHOR("Liam Girdwood");
1399 MODULE_DESCRIPTION("WM8350 voltage and current regulator driver");
1400 MODULE_LICENSE("GPL");
1401 MODULE_ALIAS("platform:wm8350-regulator");