Pileus Git - ~andy/linux/blob - drivers/pinctrl/sirf/pinctrl-atlas6.c

   1 /*
   2  * pinctrl pads, groups, functions for CSR SiRFatlasVI
   3  *
   4  * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 #include <linux/pinctrl/pinctrl.h>
  10 #include <linux/bitops.h>
  11
  12 #include "pinctrl-sirf.h"
  13
  14 /*
  15  * pad list for the pinmux subsystem
  16  * refer to atlasVI_io_table_v0.93.xls
  17  */
  18 static const struct pinctrl_pin_desc sirfsoc_pads[] = {
  19         PINCTRL_PIN(0, "gpio0-0"),
  20         PINCTRL_PIN(1, "gpio0-1"),
  21         PINCTRL_PIN(2, "gpio0-2"),
  22         PINCTRL_PIN(3, "gpio0-3"),
  23         PINCTRL_PIN(4, "pwm0"),
  24         PINCTRL_PIN(5, "pwm1"),
  25         PINCTRL_PIN(6, "pwm2"),
  26         PINCTRL_PIN(7, "pwm3"),
  27         PINCTRL_PIN(8, "warm_rst_b"),
  28         PINCTRL_PIN(9, "odo_0"),
  29         PINCTRL_PIN(10, "odo_1"),
  30         PINCTRL_PIN(11, "dr_dir"),
  31         PINCTRL_PIN(12, "rts_0"),
  32         PINCTRL_PIN(13, "scl_1"),
  33         PINCTRL_PIN(14, "ntrst"),
  34         PINCTRL_PIN(15, "sda_1"),
  35         PINCTRL_PIN(16, "x_ldd[16]"),
  36         PINCTRL_PIN(17, "x_ldd[17]"),
  37         PINCTRL_PIN(18, "x_ldd[18]"),
  38         PINCTRL_PIN(19, "x_ldd[19]"),
  39         PINCTRL_PIN(20, "x_ldd[20]"),
  40         PINCTRL_PIN(21, "x_ldd[21]"),
  41         PINCTRL_PIN(22, "x_ldd[22]"),
  42         PINCTRL_PIN(23, "x_ldd[23]"),
  43         PINCTRL_PIN(24, "gps_sgn"),
  44         PINCTRL_PIN(25, "gps_mag"),
  45         PINCTRL_PIN(26, "gps_clk"),
  46         PINCTRL_PIN(27, "sd_cd_b_2"),
  47         PINCTRL_PIN(28, "sd_vcc_on_2"),
  48         PINCTRL_PIN(29, "sd_wp_b_2"),
  49         PINCTRL_PIN(30, "sd_clk_3"),
  50         PINCTRL_PIN(31, "sd_cmd_3"),
  51
  52         PINCTRL_PIN(32, "x_sd_dat_3[0]"),
  53         PINCTRL_PIN(33, "x_sd_dat_3[1]"),
  54         PINCTRL_PIN(34, "x_sd_dat_3[2]"),
  55         PINCTRL_PIN(35, "x_sd_dat_3[3]"),
  56         PINCTRL_PIN(36, "usb_clk"),
  57         PINCTRL_PIN(37, "usb_dir"),
  58         PINCTRL_PIN(38, "usb_nxt"),
  59         PINCTRL_PIN(39, "usb_stp"),
  60         PINCTRL_PIN(40, "usb_dat[7]"),
  61         PINCTRL_PIN(41, "usb_dat[6]"),
  62         PINCTRL_PIN(42, "x_cko_1"),
  63         PINCTRL_PIN(43, "spi_clk_1"),
  64         PINCTRL_PIN(44, "spi_dout_1"),
  65         PINCTRL_PIN(45, "spi_din_1"),
  66         PINCTRL_PIN(46, "spi_en_1"),
  67         PINCTRL_PIN(47, "x_txd_1"),
  68         PINCTRL_PIN(48, "x_txd_2"),
  69         PINCTRL_PIN(49, "x_rxd_1"),
  70         PINCTRL_PIN(50, "x_rxd_2"),
  71         PINCTRL_PIN(51, "x_usclk_0"),
  72         PINCTRL_PIN(52, "x_utxd_0"),
  73         PINCTRL_PIN(53, "x_urxd_0"),
  74         PINCTRL_PIN(54, "x_utfs_0"),
  75         PINCTRL_PIN(55, "x_urfs_0"),
  76         PINCTRL_PIN(56, "usb_dat5"),
  77         PINCTRL_PIN(57, "usb_dat4"),
  78         PINCTRL_PIN(58, "usb_dat3"),
  79         PINCTRL_PIN(59, "usb_dat2"),
  80         PINCTRL_PIN(60, "usb_dat1"),
  81         PINCTRL_PIN(61, "usb_dat0"),
  82         PINCTRL_PIN(62, "x_ldd[14]"),
  83         PINCTRL_PIN(63, "x_ldd[15]"),
  84
  85         PINCTRL_PIN(64, "x_gps_gpio"),
  86         PINCTRL_PIN(65, "x_ldd[13]"),
  87         PINCTRL_PIN(66, "x_df_we_b"),
  88         PINCTRL_PIN(67, "x_df_re_b"),
  89         PINCTRL_PIN(68, "x_txd_0"),
  90         PINCTRL_PIN(69, "x_rxd_0"),
  91         PINCTRL_PIN(70, "x_l_lck"),
  92         PINCTRL_PIN(71, "x_l_fck"),
  93         PINCTRL_PIN(72, "x_l_de"),
  94         PINCTRL_PIN(73, "x_ldd[0]"),
  95         PINCTRL_PIN(74, "x_ldd[1]"),
  96         PINCTRL_PIN(75, "x_ldd[2]"),
  97         PINCTRL_PIN(76, "x_ldd[3]"),
  98         PINCTRL_PIN(77, "x_ldd[4]"),
  99         PINCTRL_PIN(78, "x_cko_0"),
 100         PINCTRL_PIN(79, "x_ldd[5]"),
 101         PINCTRL_PIN(80, "x_ldd[6]"),
 102         PINCTRL_PIN(81, "x_ldd[7]"),
 103         PINCTRL_PIN(82, "x_ldd[8]"),
 104         PINCTRL_PIN(83, "x_ldd[9]"),
 105         PINCTRL_PIN(84, "x_ldd[10]"),
 106         PINCTRL_PIN(85, "x_ldd[11]"),
 107         PINCTRL_PIN(86, "x_ldd[12]"),
 108         PINCTRL_PIN(87, "x_vip_vsync"),
 109         PINCTRL_PIN(88, "x_vip_hsync"),
 110         PINCTRL_PIN(89, "x_vip_pxclk"),
 111         PINCTRL_PIN(90, "x_sda_0"),
 112         PINCTRL_PIN(91, "x_scl_0"),
 113         PINCTRL_PIN(92, "x_df_ry_by"),
 114         PINCTRL_PIN(93, "x_df_cs_b[1]"),
 115         PINCTRL_PIN(94, "x_df_cs_b[0]"),
 116         PINCTRL_PIN(95, "x_l_pclk"),
 117
 118         PINCTRL_PIN(96, "x_df_dqs"),
 119         PINCTRL_PIN(97, "x_df_wp_b"),
 120         PINCTRL_PIN(98, "ac97_sync"),
 121         PINCTRL_PIN(99, "ac97_bit_clk "),
 122         PINCTRL_PIN(100, "ac97_dout"),
 123         PINCTRL_PIN(101, "ac97_din"),
 124         PINCTRL_PIN(102, "x_rtc_io"),
 125
 126         PINCTRL_PIN(103, "x_usb1_dp"),
 127         PINCTRL_PIN(104, "x_usb1_dn"),
 128 };
 129
 130 static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
 131         {
 132                 .group = 1,
 133                 .mask = BIT(30) | BIT(31),
 134         }, {
 135                 .group = 2,
 136                 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
 137                         BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) |
 138                         BIT(20) | BIT(21) | BIT(22) | BIT(31),
 139         },
 140 };
 141
 142 static const struct sirfsoc_padmux lcd_16bits_padmux = {
 143         .muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask),
 144         .muxmask = lcd_16bits_sirfsoc_muxmask,
 145         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 146         .funcmask = BIT(4),
 147         .funcval = 0,
 148 };
 149
 150 static const unsigned lcd_16bits_pins[] = { 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83,
 151         84, 85, 86, 95 };
 152
 153 static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = {
 154         {
 155                 .group = 2,
 156                 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
 157                         BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) |
 158                         BIT(20) | BIT(21) | BIT(22) | BIT(31),
 159         }, {
 160                 .group = 1,
 161                 .mask = BIT(30) | BIT(31),
 162         }, {
 163                 .group = 0,
 164                 .mask = BIT(16) | BIT(17),
 165         },
 166 };
 167
 168 static const struct sirfsoc_padmux lcd_18bits_padmux = {
 169         .muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask),
 170         .muxmask = lcd_18bits_muxmask,
 171         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 172         .funcmask = BIT(4) | BIT(15),
 173         .funcval = 0,
 174 };
 175
 176 static const unsigned lcd_18bits_pins[] = { 16, 17, 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83,
 177         84, 85, 86, 95 };
 178
 179 static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = {
 180         {
 181                 .group = 2,
 182                 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
 183                         BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) |
 184                         BIT(20) | BIT(21) | BIT(22) | BIT(31),
 185         }, {
 186                 .group = 1,
 187                 .mask = BIT(30) | BIT(31),
 188         }, {
 189                 .group = 0,
 190                 .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
 191         },
 192 };
 193
 194 static const struct sirfsoc_padmux lcd_24bits_padmux = {
 195         .muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask),
 196         .muxmask = lcd_24bits_muxmask,
 197         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 198         .funcmask = BIT(4) | BIT(15),
 199         .funcval = 0,
 200 };
 201
 202 static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79,
 203         80, 81, 82, 83, 84, 85, 86, 95};
 204
 205 static const struct sirfsoc_muxmask lcdrom_muxmask[] = {
 206         {
 207                 .group = 2,
 208                 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
 209                         BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) |
 210                         BIT(20) | BIT(21) | BIT(22) | BIT(31),
 211         }, {
 212                 .group = 1,
 213                 .mask = BIT(30) | BIT(31),
 214         }, {
 215                 .group = 0,
 216                 .mask = BIT(8),
 217         },
 218 };
 219
 220 static const struct sirfsoc_padmux lcdrom_padmux = {
 221         .muxmask_counts = ARRAY_SIZE(lcdrom_muxmask),
 222         .muxmask = lcdrom_muxmask,
 223         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 224         .funcmask = BIT(4),
 225         .funcval = BIT(4),
 226 };
 227
 228 static const unsigned lcdrom_pins[] = { 8, 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83,
 229         84, 85, 86, 95};
 230
 231 static const struct sirfsoc_muxmask uart0_muxmask[] = {
 232         {
 233                 .group = 0,
 234                 .mask = BIT(12),
 235         }, {
 236                 .group = 1,
 237                 .mask = BIT(23),
 238         }, {
 239                 .group = 2,
 240                 .mask = BIT(4) | BIT(5),
 241         },
 242 };
 243
 244 static const struct sirfsoc_padmux uart0_padmux = {
 245         .muxmask_counts = ARRAY_SIZE(uart0_muxmask),
 246         .muxmask = uart0_muxmask,
 247         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 248         .funcmask = BIT(9),
 249         .funcval = BIT(9),
 250 };
 251
 252 static const unsigned uart0_pins[] = { 12, 55, 68, 69 };
 253
 254 static const struct sirfsoc_muxmask uart0_nostreamctrl_muxmask[] = {
 255         {
 256                 .group = 2,
 257                 .mask = BIT(4) | BIT(5),
 258         },
 259 };
 260
 261 static const struct sirfsoc_padmux uart0_nostreamctrl_padmux = {
 262         .muxmask_counts = ARRAY_SIZE(uart0_nostreamctrl_muxmask),
 263         .muxmask = uart0_nostreamctrl_muxmask,
 264 };
 265
 266 static const unsigned uart0_nostreamctrl_pins[] = { 68, 69 };
 267
 268 static const struct sirfsoc_muxmask uart1_muxmask[] = {
 269         {
 270                 .group = 1,
 271                 .mask = BIT(15) | BIT(17),
 272         },
 273 };
 274
 275 static const struct sirfsoc_padmux uart1_padmux = {
 276         .muxmask_counts = ARRAY_SIZE(uart1_muxmask),
 277         .muxmask = uart1_muxmask,
 278 };
 279
 280 static const unsigned uart1_pins[] = { 47, 49 };
 281
 282 static const struct sirfsoc_muxmask uart2_muxmask[] = {
 283         {
 284                 .group = 0,
 285                 .mask = BIT(10) | BIT(14),
 286         }, {
 287                 .group = 1,
 288                 .mask = BIT(16) | BIT(18),
 289         },
 290 };
 291
 292 static const struct sirfsoc_padmux uart2_padmux = {
 293         .muxmask_counts = ARRAY_SIZE(uart2_muxmask),
 294         .muxmask = uart2_muxmask,
 295         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 296         .funcmask = BIT(10),
 297         .funcval = BIT(10),
 298 };
 299
 300 static const unsigned uart2_pins[] = { 10, 14, 48, 50 };
 301
 302 static const struct sirfsoc_muxmask uart2_nostreamctrl_muxmask[] = {
 303         {
 304                 .group = 1,
 305                 .mask = BIT(16) | BIT(18),
 306         },
 307 };
 308
 309 static const struct sirfsoc_padmux uart2_nostreamctrl_padmux = {
 310         .muxmask_counts = ARRAY_SIZE(uart2_nostreamctrl_muxmask),
 311         .muxmask = uart2_nostreamctrl_muxmask,
 312 };
 313
 314 static const unsigned uart2_nostreamctrl_pins[] = { 48, 50 };
 315
 316 static const struct sirfsoc_muxmask sdmmc3_muxmask[] = {
 317         {
 318                 .group = 0,
 319                 .mask = BIT(30) | BIT(31),
 320         }, {
 321                 .group = 1,
 322                 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
 323         },
 324 };
 325
 326 static const struct sirfsoc_padmux sdmmc3_padmux = {
 327         .muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask),
 328         .muxmask = sdmmc3_muxmask,
 329         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 330         .funcmask = BIT(7),
 331         .funcval = 0,
 332 };
 333
 334 static const unsigned sdmmc3_pins[] = { 30, 31, 32, 33, 34, 35 };
 335
 336 static const struct sirfsoc_muxmask spi0_muxmask[] = {
 337         {
 338                 .group = 0,
 339                 .mask = BIT(30),
 340         }, {
 341                 .group = 1,
 342                 .mask = BIT(0) | BIT(2) | BIT(3),
 343         },
 344 };
 345
 346 static const struct sirfsoc_padmux spi0_padmux = {
 347         .muxmask_counts = ARRAY_SIZE(spi0_muxmask),
 348         .muxmask = spi0_muxmask,
 349         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 350         .funcmask = BIT(7),
 351         .funcval = BIT(7),
 352 };
 353
 354 static const unsigned spi0_pins[] = { 30, 32, 34, 35 };
 355
 356 static const struct sirfsoc_muxmask cko1_muxmask[] = {
 357         {
 358                 .group = 1,
 359                 .mask = BIT(10),
 360         },
 361 };
 362
 363 static const struct sirfsoc_padmux cko1_padmux = {
 364         .muxmask_counts = ARRAY_SIZE(cko1_muxmask),
 365         .muxmask = cko1_muxmask,
 366         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 367         .funcmask = BIT(3),
 368         .funcval = 0,
 369 };
 370
 371 static const unsigned cko1_pins[] = { 42 };
 372
 373 static const struct sirfsoc_muxmask i2s_muxmask[] = {
 374         {
 375                 .group = 1,
 376                 .mask = BIT(10),
 377         }, {
 378                 .group = 3,
 379                 .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
 380         },
 381 };
 382
 383 static const struct sirfsoc_padmux i2s_padmux = {
 384         .muxmask_counts = ARRAY_SIZE(i2s_muxmask),
 385         .muxmask = i2s_muxmask,
 386         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 387         .funcmask = BIT(3),
 388         .funcval = BIT(3),
 389 };
 390
 391 static const unsigned i2s_pins[] = { 42, 98, 99, 100, 101 };
 392
 393 static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = {
 394         {
 395                 .group = 1,
 396                 .mask = BIT(10),
 397         }, {
 398                 .group = 3,
 399                 .mask = BIT(2) | BIT(3) | BIT(4),
 400         },
 401 };
 402
 403 static const struct sirfsoc_padmux i2s_no_din_padmux = {
 404         .muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask),
 405         .muxmask = i2s_no_din_muxmask,
 406         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 407         .funcmask = BIT(3),
 408         .funcval = BIT(3),
 409 };
 410
 411 static const unsigned i2s_no_din_pins[] = { 42, 98, 99, 100 };
 412
 413 static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = {
 414         {
 415                 .group = 1,
 416                 .mask = BIT(10) | BIT(20) | BIT(23),
 417         }, {
 418                 .group = 3,
 419                 .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
 420         },
 421 };
 422
 423 static const struct sirfsoc_padmux i2s_6chn_padmux = {
 424         .muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask),
 425         .muxmask = i2s_6chn_muxmask,
 426         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 427         .funcmask = BIT(1) | BIT(3) | BIT(9),
 428         .funcval = BIT(1) | BIT(3) | BIT(9),
 429 };
 430
 431 static const unsigned i2s_6chn_pins[] = { 42, 52, 55, 98, 99, 100, 101 };
 432
 433 static const struct sirfsoc_muxmask ac97_muxmask[] = {
 434         {
 435                 .group = 3,
 436                 .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
 437         },
 438 };
 439
 440 static const struct sirfsoc_padmux ac97_padmux = {
 441         .muxmask_counts = ARRAY_SIZE(ac97_muxmask),
 442         .muxmask = ac97_muxmask,
 443 };
 444
 445 static const unsigned ac97_pins[] = { 98, 99, 100, 101 };
 446
 447 static const struct sirfsoc_muxmask spi1_muxmask[] = {
 448         {
 449                 .group = 1,
 450                 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
 451         },
 452 };
 453
 454 static const struct sirfsoc_padmux spi1_padmux = {
 455         .muxmask_counts = ARRAY_SIZE(spi1_muxmask),
 456         .muxmask = spi1_muxmask,
 457         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 458         .funcmask = BIT(16),
 459         .funcval = 0,
 460 };
 461
 462 static const unsigned spi1_pins[] = { 43, 44, 45, 46 };
 463
 464 static const struct sirfsoc_muxmask sdmmc1_muxmask[] = {
 465         {
 466                 .group = 2,
 467                 .mask = BIT(2) | BIT(3),
 468         },
 469 };
 470
 471 static const struct sirfsoc_padmux sdmmc1_padmux = {
 472         .muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask),
 473         .muxmask = sdmmc1_muxmask,
 474         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 475         .funcmask = BIT(5),
 476         .funcval = BIT(5),
 477 };
 478
 479 static const unsigned sdmmc1_pins[] = { 66, 67 };
 480
 481 static const struct sirfsoc_muxmask gps_muxmask[] = {
 482         {
 483                 .group = 0,
 484                 .mask = BIT(24) | BIT(25) | BIT(26),
 485         },
 486 };
 487
 488 static const struct sirfsoc_padmux gps_padmux = {
 489         .muxmask_counts = ARRAY_SIZE(gps_muxmask),
 490         .muxmask = gps_muxmask,
 491         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 492         .funcmask = BIT(13),
 493         .funcval = 0,
 494 };
 495
 496 static const unsigned gps_pins[] = { 24, 25, 26 };
 497
 498 static const struct sirfsoc_muxmask sdmmc5_muxmask[] = {
 499         {
 500                 .group = 0,
 501                 .mask = BIT(24) | BIT(25) | BIT(26),
 502         },
 503 };
 504
 505 static const struct sirfsoc_padmux sdmmc5_padmux = {
 506         .muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask),
 507         .muxmask = sdmmc5_muxmask,
 508         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 509         .funcmask = BIT(13),
 510         .funcval = BIT(13),
 511 };
 512
 513 static const unsigned sdmmc5_pins[] = { 24, 25, 26 };
 514
 515 static const struct sirfsoc_muxmask usp0_muxmask[] = {
 516         {
 517                 .group = 1,
 518                 .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
 519         },
 520 };
 521
 522 static const struct sirfsoc_padmux usp0_padmux = {
 523         .muxmask_counts = ARRAY_SIZE(usp0_muxmask),
 524         .muxmask = usp0_muxmask,
 525         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 526         .funcmask = BIT(1) | BIT(2) | BIT(9),
 527         .funcval = 0,
 528 };
 529
 530 static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 };
 531
 532 static const struct sirfsoc_muxmask usp0_uart_nostreamctrl_muxmask[] = {
 533         {
 534                 .group = 1,
 535                 .mask = BIT(20) | BIT(21),
 536         },
 537 };
 538
 539 static const struct sirfsoc_padmux usp0_uart_nostreamctrl_padmux = {
 540         .muxmask_counts = ARRAY_SIZE(usp0_uart_nostreamctrl_muxmask),
 541         .muxmask = usp0_uart_nostreamctrl_muxmask,
 542 };
 543
 544 static const unsigned usp0_uart_nostreamctrl_pins[] = { 52, 53 };
 545 static const struct sirfsoc_muxmask usp1_muxmask[] = {
 546         {
 547                 .group = 0,
 548                 .mask = BIT(15),
 549         }, {
 550                 .group = 1,
 551                 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
 552         },
 553 };
 554
 555 static const struct sirfsoc_padmux usp1_padmux = {
 556         .muxmask_counts = ARRAY_SIZE(usp1_muxmask),
 557         .muxmask = usp1_muxmask,
 558         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 559         .funcmask = BIT(16),
 560         .funcval = BIT(16),
 561 };
 562
 563 static const unsigned usp1_pins[] = { 15, 43, 44, 45, 46 };
 564
 565 static const struct sirfsoc_muxmask usp1_uart_nostreamctrl_muxmask[] = {
 566         {
 567                 .group = 1,
 568                 .mask = BIT(12) | BIT(13),
 569         },
 570 };
 571
 572 static const struct sirfsoc_padmux usp1_uart_nostreamctrl_padmux = {
 573         .muxmask_counts = ARRAY_SIZE(usp1_uart_nostreamctrl_muxmask),
 574         .muxmask = usp1_uart_nostreamctrl_muxmask,
 575         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 576         .funcmask = BIT(16),
 577         .funcval = BIT(16),
 578 };
 579
 580 static const unsigned usp1_uart_nostreamctrl_pins[] = { 44, 45 };
 581
 582 static const struct sirfsoc_muxmask nand_muxmask[] = {
 583         {
 584                 .group = 2,
 585                 .mask = BIT(2) | BIT(3) | BIT(28) | BIT(29) | BIT(30),
 586         }, {
 587                 .group = 3,
 588                 .mask = BIT(0) | BIT(1),
 589         },
 590 };
 591
 592 static const struct sirfsoc_padmux nand_padmux = {
 593         .muxmask_counts = ARRAY_SIZE(nand_muxmask),
 594         .muxmask = nand_muxmask,
 595         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 596         .funcmask = BIT(5) | BIT(19),
 597         .funcval = 0,
 598 };
 599
 600 static const unsigned nand_pins[] = { 66, 67, 92, 93, 94, 96, 97 };
 601
 602 static const struct sirfsoc_muxmask sdmmc0_muxmask[] = {
 603         {
 604                 .group = 3,
 605                 .mask = BIT(1),
 606         },
 607 };
 608
 609 static const struct sirfsoc_padmux sdmmc0_padmux = {
 610         .muxmask_counts = ARRAY_SIZE(sdmmc0_muxmask),
 611         .muxmask = sdmmc0_muxmask,
 612         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 613         .funcmask = BIT(5) | BIT(19),
 614         .funcval = BIT(19),
 615 };
 616
 617 static const unsigned sdmmc0_pins[] = { 97 };
 618
 619 static const struct sirfsoc_muxmask sdmmc2_muxmask[] = {
 620         {
 621                 .group = 0,
 622                 .mask = BIT(27) | BIT(28) | BIT(29),
 623         },
 624 };
 625
 626 static const struct sirfsoc_padmux sdmmc2_padmux = {
 627         .muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask),
 628         .muxmask = sdmmc2_muxmask,
 629         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 630         .funcmask = BIT(11),
 631         .funcval = 0,
 632 };
 633
 634 static const unsigned sdmmc2_pins[] = { 27, 28, 29 };
 635
 636 static const struct sirfsoc_muxmask sdmmc2_nowp_muxmask[] = {
 637         {
 638                 .group = 0,
 639                 .mask = BIT(27) | BIT(28),
 640         },
 641 };
 642
 643 static const struct sirfsoc_padmux sdmmc2_nowp_padmux = {
 644         .muxmask_counts = ARRAY_SIZE(sdmmc2_nowp_muxmask),
 645         .muxmask = sdmmc2_nowp_muxmask,
 646         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 647         .funcmask = BIT(11),
 648         .funcval = 0,
 649 };
 650
 651 static const unsigned sdmmc2_nowp_pins[] = { 27, 28 };
 652
 653 static const struct sirfsoc_muxmask cko0_muxmask[] = {
 654         {
 655                 .group = 2,
 656                 .mask = BIT(14),
 657         },
 658 };
 659
 660 static const struct sirfsoc_padmux cko0_padmux = {
 661         .muxmask_counts = ARRAY_SIZE(cko0_muxmask),
 662         .muxmask = cko0_muxmask,
 663 };
 664
 665 static const unsigned cko0_pins[] = { 78 };
 666
 667 static const struct sirfsoc_muxmask vip_muxmask[] = {
 668         {
 669                 .group = 1,
 670                 .mask = BIT(4) | BIT(5) | BIT(6) | BIT(8) | BIT(9)
 671                         | BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28) |
 672                         BIT(29),
 673         },
 674 };
 675
 676 static const struct sirfsoc_padmux vip_padmux = {
 677         .muxmask_counts = ARRAY_SIZE(vip_muxmask),
 678         .muxmask = vip_muxmask,
 679         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 680         .funcmask = BIT(18),
 681         .funcval = BIT(18),
 682 };
 683
 684 static const unsigned vip_pins[] = { 36, 37, 38, 40, 41, 56, 57, 58, 59, 60, 61 };
 685
 686 static const struct sirfsoc_muxmask vip_noupli_muxmask[] = {
 687         {
 688                 .group = 0,
 689                 .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20)
 690                         | BIT(21) | BIT(22) | BIT(23),
 691         }, {
 692                 .group = 2,
 693                 .mask = BIT(23) | BIT(24) | BIT(25),
 694         },
 695 };
 696
 697 static const struct sirfsoc_padmux vip_noupli_padmux = {
 698         .muxmask_counts = ARRAY_SIZE(vip_noupli_muxmask),
 699         .muxmask = vip_noupli_muxmask,
 700         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 701         .funcmask = BIT(15),
 702         .funcval = BIT(15),
 703 };
 704
 705 static const unsigned vip_noupli_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 87, 88, 89 };
 706
 707 static const struct sirfsoc_muxmask i2c0_muxmask[] = {
 708         {
 709                 .group = 2,
 710                 .mask = BIT(26) | BIT(27),
 711         },
 712 };
 713
 714 static const struct sirfsoc_padmux i2c0_padmux = {
 715         .muxmask_counts = ARRAY_SIZE(i2c0_muxmask),
 716         .muxmask = i2c0_muxmask,
 717 };
 718
 719 static const unsigned i2c0_pins[] = { 90, 91 };
 720
 721 static const struct sirfsoc_muxmask i2c1_muxmask[] = {
 722         {
 723                 .group = 0,
 724                 .mask = BIT(13) | BIT(15),
 725         },
 726 };
 727
 728 static const struct sirfsoc_padmux i2c1_padmux = {
 729         .muxmask_counts = ARRAY_SIZE(i2c1_muxmask),
 730         .muxmask = i2c1_muxmask,
 731         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 732         .funcmask = BIT(16),
 733         .funcval = 0,
 734 };
 735
 736 static const unsigned i2c1_pins[] = { 13, 15 };
 737
 738 static const struct sirfsoc_muxmask pwm0_muxmask[] = {
 739         {
 740                 .group = 0,
 741                 .mask = BIT(4),
 742         },
 743 };
 744
 745 static const struct sirfsoc_padmux pwm0_padmux = {
 746         .muxmask_counts = ARRAY_SIZE(pwm0_muxmask),
 747         .muxmask = pwm0_muxmask,
 748         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 749         .funcmask = BIT(12),
 750         .funcval = 0,
 751 };
 752
 753 static const unsigned pwm0_pins[] = { 4 };
 754
 755 static const struct sirfsoc_muxmask pwm1_muxmask[] = {
 756         {
 757                 .group = 0,
 758                 .mask = BIT(5),
 759         },
 760 };
 761
 762 static const struct sirfsoc_padmux pwm1_padmux = {
 763         .muxmask_counts = ARRAY_SIZE(pwm1_muxmask),
 764         .muxmask = pwm1_muxmask,
 765 };
 766
 767 static const unsigned pwm1_pins[] = { 5 };
 768
 769 static const struct sirfsoc_muxmask pwm2_muxmask[] = {
 770         {
 771                 .group = 0,
 772                 .mask = BIT(6),
 773         },
 774 };
 775
 776 static const struct sirfsoc_padmux pwm2_padmux = {
 777         .muxmask_counts = ARRAY_SIZE(pwm2_muxmask),
 778         .muxmask = pwm2_muxmask,
 779 };
 780
 781 static const unsigned pwm2_pins[] = { 6 };
 782
 783 static const struct sirfsoc_muxmask pwm3_muxmask[] = {
 784         {
 785                 .group = 0,
 786                 .mask = BIT(7),
 787         },
 788 };
 789
 790 static const struct sirfsoc_padmux pwm3_padmux = {
 791         .muxmask_counts = ARRAY_SIZE(pwm3_muxmask),
 792         .muxmask = pwm3_muxmask,
 793 };
 794
 795 static const unsigned pwm3_pins[] = { 7 };
 796
 797 static const struct sirfsoc_muxmask pwm4_muxmask[] = {
 798         {
 799                 .group = 2,
 800                 .mask = BIT(14),
 801         },
 802 };
 803
 804 static const struct sirfsoc_padmux pwm4_padmux = {
 805         .muxmask_counts = ARRAY_SIZE(pwm4_muxmask),
 806         .muxmask = pwm4_muxmask,
 807 };
 808
 809 static const unsigned pwm4_pins[] = { 78 };
 810
 811 static const struct sirfsoc_muxmask warm_rst_muxmask[] = {
 812         {
 813                 .group = 0,
 814                 .mask = BIT(8),
 815         },
 816 };
 817
 818 static const struct sirfsoc_padmux warm_rst_padmux = {
 819         .muxmask_counts = ARRAY_SIZE(warm_rst_muxmask),
 820         .muxmask = warm_rst_muxmask,
 821         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 822         .funcmask = BIT(4),
 823         .funcval = 0,
 824 };
 825
 826 static const unsigned warm_rst_pins[] = { 8 };
 827
 828 static const struct sirfsoc_muxmask usb0_upli_drvbus_muxmask[] = {
 829         {
 830                 .group = 1,
 831                 .mask = BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8)
 832                         | BIT(9) | BIT(24) | BIT(25) | BIT(26) |
 833                         BIT(27) | BIT(28) | BIT(29),
 834         },
 835 };
 836 static const struct sirfsoc_padmux usb0_upli_drvbus_padmux = {
 837         .muxmask_counts = ARRAY_SIZE(usb0_upli_drvbus_muxmask),
 838         .muxmask = usb0_upli_drvbus_muxmask,
 839         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 840         .funcmask = BIT(18),
 841         .funcval = 0,
 842 };
 843
 844 static const unsigned usb0_upli_drvbus_pins[] = { 36, 37, 38, 39, 40, 41, 56, 57, 58, 59, 60, 61 };
 845
 846 static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = {
 847         {
 848                 .group = 0,
 849                 .mask = BIT(28),
 850         },
 851 };
 852
 853 static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = {
 854         .muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask),
 855         .muxmask = usb1_utmi_drvbus_muxmask,
 856         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 857         .funcmask = BIT(11),
 858         .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */
 859 };
 860
 861 static const unsigned usb1_utmi_drvbus_pins[] = { 28 };
 862
 863 static const struct sirfsoc_padmux usb1_dp_dn_padmux = {
 864         .muxmask_counts = 0,
 865         .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
 866         .funcmask = BIT(2),
 867         .funcval = BIT(2),
 868 };
 869
 870 static const unsigned usb1_dp_dn_pins[] = { 103, 104 };
 871
 872 static const struct sirfsoc_padmux uart1_route_io_usb1_padmux = {
 873         .muxmask_counts = 0,
 874         .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
 875         .funcmask = BIT(2),
 876         .funcval = 0,
 877 };
 878
 879 static const unsigned uart1_route_io_usb1_pins[] = { 103, 104 };
 880
 881 static const struct sirfsoc_muxmask pulse_count_muxmask[] = {
 882         {
 883                 .group = 0,
 884                 .mask = BIT(9) | BIT(10) | BIT(11),
 885         },
 886 };
 887
 888 static const struct sirfsoc_padmux pulse_count_padmux = {
 889         .muxmask_counts = ARRAY_SIZE(pulse_count_muxmask),
 890         .muxmask = pulse_count_muxmask,
 891 };
 892
 893 static const unsigned pulse_count_pins[] = { 9, 10, 11 };
 894
 895 static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
 896         SIRFSOC_PIN_GROUP("lcd_16bitsgrp", lcd_16bits_pins),
 897         SIRFSOC_PIN_GROUP("lcd_18bitsgrp", lcd_18bits_pins),
 898         SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins),
 899         SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins),
 900         SIRFSOC_PIN_GROUP("uart0grp", uart0_pins),
 901         SIRFSOC_PIN_GROUP("uart0_nostreamctrlgrp", uart0_nostreamctrl_pins),
 902         SIRFSOC_PIN_GROUP("uart1grp", uart1_pins),
 903         SIRFSOC_PIN_GROUP("uart2grp", uart2_pins),
 904         SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins),
 905         SIRFSOC_PIN_GROUP("usp0grp", usp0_pins),
 906         SIRFSOC_PIN_GROUP("usp0_uart_nostreamctrl_grp",
 907                                         usp0_uart_nostreamctrl_pins),
 908         SIRFSOC_PIN_GROUP("usp1grp", usp1_pins),
 909         SIRFSOC_PIN_GROUP("usp1_uart_nostreamctrl_grp",
 910                                         usp1_uart_nostreamctrl_pins),
 911         SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins),
 912         SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins),
 913         SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins),
 914         SIRFSOC_PIN_GROUP("pwm1grp", pwm1_pins),
 915         SIRFSOC_PIN_GROUP("pwm2grp", pwm2_pins),
 916         SIRFSOC_PIN_GROUP("pwm3grp", pwm3_pins),
 917         SIRFSOC_PIN_GROUP("pwm4grp", pwm4_pins),
 918         SIRFSOC_PIN_GROUP("vipgrp", vip_pins),
 919         SIRFSOC_PIN_GROUP("vip_noupligrp", vip_noupli_pins),
 920         SIRFSOC_PIN_GROUP("warm_rstgrp", warm_rst_pins),
 921         SIRFSOC_PIN_GROUP("cko0grp", cko0_pins),
 922         SIRFSOC_PIN_GROUP("cko1grp", cko1_pins),
 923         SIRFSOC_PIN_GROUP("sdmmc0grp", sdmmc0_pins),
 924         SIRFSOC_PIN_GROUP("sdmmc1grp", sdmmc1_pins),
 925         SIRFSOC_PIN_GROUP("sdmmc2grp", sdmmc2_pins),
 926         SIRFSOC_PIN_GROUP("sdmmc2_nowpgrp", sdmmc2_nowp_pins),
 927         SIRFSOC_PIN_GROUP("sdmmc3grp", sdmmc3_pins),
 928         SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins),
 929         SIRFSOC_PIN_GROUP("usb0_upli_drvbusgrp", usb0_upli_drvbus_pins),
 930         SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins),
 931         SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins),
 932         SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins),
 933         SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
 934         SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
 935         SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins),
 936         SIRFSOC_PIN_GROUP("i2s_6chngrp", i2s_6chn_pins),
 937         SIRFSOC_PIN_GROUP("ac97grp", ac97_pins),
 938         SIRFSOC_PIN_GROUP("nandgrp", nand_pins),
 939         SIRFSOC_PIN_GROUP("spi0grp", spi0_pins),
 940         SIRFSOC_PIN_GROUP("spi1grp", spi1_pins),
 941         SIRFSOC_PIN_GROUP("gpsgrp", gps_pins),
 942 };
 943
 944 static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" };
 945 static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" };
 946 static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" };
 947 static const char * const lcdromgrp[] = { "lcdromgrp" };
 948 static const char * const uart0grp[] = { "uart0grp" };
 949 static const char * const uart0_nostreamctrlgrp[] = { "uart0_nostreamctrlgrp" };
 950 static const char * const uart1grp[] = { "uart1grp" };
 951 static const char * const uart2grp[] = { "uart2grp" };
 952 static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" };
 953 static const char * const usp0_uart_nostreamctrl_grp[] = {
 954                                         "usp0_uart_nostreamctrl_grp" };
 955 static const char * const usp0grp[] = { "usp0grp" };
 956 static const char * const usp1grp[] = { "usp1grp" };
 957 static const char * const usp1_uart_nostreamctrl_grp[] = {
 958                                         "usp1_uart_nostreamctrl_grp" };
 959 static const char * const i2c0grp[] = { "i2c0grp" };
 960 static const char * const i2c1grp[] = { "i2c1grp" };
 961 static const char * const pwm0grp[] = { "pwm0grp" };
 962 static const char * const pwm1grp[] = { "pwm1grp" };
 963 static const char * const pwm2grp[] = { "pwm2grp" };
 964 static const char * const pwm3grp[] = { "pwm3grp" };
 965 static const char * const pwm4grp[] = { "pwm4grp" };
 966 static const char * const vipgrp[] = { "vipgrp" };
 967 static const char * const vip_noupligrp[] = { "vip_noupligrp" };
 968 static const char * const warm_rstgrp[] = { "warm_rstgrp" };
 969 static const char * const cko0grp[] = { "cko0grp" };
 970 static const char * const cko1grp[] = { "cko1grp" };
 971 static const char * const sdmmc0grp[] = { "sdmmc0grp" };
 972 static const char * const sdmmc1grp[] = { "sdmmc1grp" };
 973 static const char * const sdmmc2grp[] = { "sdmmc2grp" };
 974 static const char * const sdmmc3grp[] = { "sdmmc3grp" };
 975 static const char * const sdmmc5grp[] = { "sdmmc5grp" };
 976 static const char * const sdmmc2_nowpgrp[] = { "sdmmc2_nowpgrp" };
 977 static const char * const usb0_upli_drvbusgrp[] = { "usb0_upli_drvbusgrp" };
 978 static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
 979 static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" };
 980 static const char * const uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" };
 981 static const char * const pulse_countgrp[] = { "pulse_countgrp" };
 982 static const char * const i2sgrp[] = { "i2sgrp" };
 983 static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" };
 984 static const char * const i2s_6chngrp[] = { "i2s_6chngrp" };
 985 static const char * const ac97grp[] = { "ac97grp" };
 986 static const char * const nandgrp[] = { "nandgrp" };
 987 static const char * const spi0grp[] = { "spi0grp" };
 988 static const char * const spi1grp[] = { "spi1grp" };
 989 static const char * const gpsgrp[] = { "gpsgrp" };
 990
 991 static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
 992         SIRFSOC_PMX_FUNCTION("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux),
 993         SIRFSOC_PMX_FUNCTION("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux),
 994         SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux),
 995         SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux),
 996         SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux),
 997         SIRFSOC_PMX_FUNCTION("uart0_nostreamctrl", uart0_nostreamctrlgrp,
 998                                                 uart0_nostreamctrl_padmux),
 999         SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux),
1000         SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
1001         SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
1002         SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
1003         SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl",
1004                                                 usp0_uart_nostreamctrl_grp,
1005                                                 usp0_uart_nostreamctrl_padmux),
1006         SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux),
1007         SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl",
1008                                                 usp1_uart_nostreamctrl_grp,
1009                                                 usp1_uart_nostreamctrl_padmux),
1010         SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux),
1011         SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux),
1012         SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux),
1013         SIRFSOC_PMX_FUNCTION("pwm1", pwm1grp, pwm1_padmux),
1014         SIRFSOC_PMX_FUNCTION("pwm2", pwm2grp, pwm2_padmux),
1015         SIRFSOC_PMX_FUNCTION("pwm3", pwm3grp, pwm3_padmux),
1016         SIRFSOC_PMX_FUNCTION("pwm4", pwm4grp, pwm4_padmux),
1017         SIRFSOC_PMX_FUNCTION("vip", vipgrp, vip_padmux),
1018         SIRFSOC_PMX_FUNCTION("vip_noupli", vip_noupligrp, vip_noupli_padmux),
1019         SIRFSOC_PMX_FUNCTION("warm_rst", warm_rstgrp, warm_rst_padmux),
1020         SIRFSOC_PMX_FUNCTION("cko0", cko0grp, cko0_padmux),
1021         SIRFSOC_PMX_FUNCTION("cko1", cko1grp, cko1_padmux),
1022         SIRFSOC_PMX_FUNCTION("sdmmc0", sdmmc0grp, sdmmc0_padmux),
1023         SIRFSOC_PMX_FUNCTION("sdmmc1", sdmmc1grp, sdmmc1_padmux),
1024         SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux),
1025         SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux),
1026         SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux),
1027         SIRFSOC_PMX_FUNCTION("sdmmc2_nowp", sdmmc2_nowpgrp, sdmmc2_nowp_padmux),
1028         SIRFSOC_PMX_FUNCTION("usb0_upli_drvbus", usb0_upli_drvbusgrp, usb0_upli_drvbus_padmux),
1029         SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
1030         SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux),
1031         SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1", uart1_route_io_usb1grp, uart1_route_io_usb1_padmux),
1032         SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
1033         SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
1034         SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux),
1035         SIRFSOC_PMX_FUNCTION("i2s_6chn", i2s_6chngrp, i2s_6chn_padmux),
1036         SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux),
1037         SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux),
1038         SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux),
1039         SIRFSOC_PMX_FUNCTION("spi1", spi1grp, spi1_padmux),
1040         SIRFSOC_PMX_FUNCTION("gps", gpsgrp, gps_padmux),
1041 };
1042
1043 struct sirfsoc_pinctrl_data atlas6_pinctrl_data = {
1044         (struct pinctrl_pin_desc *)sirfsoc_pads,
1045         ARRAY_SIZE(sirfsoc_pads),
1046         (struct sirfsoc_pin_group *)sirfsoc_pin_groups,
1047         ARRAY_SIZE(sirfsoc_pin_groups),
1048         (struct sirfsoc_pmx_func *)sirfsoc_pmx_functions,
1049         ARRAY_SIZE(sirfsoc_pmx_functions),
1050 };
1051