Pileus Git - ~andy/linux/blob - drivers/pinctrl/pinctrl-sunxi.c

   1 /*
   2  * Allwinner A1X SoCs pinctrl driver.
   3  *
   4  * Copyright (C) 2012 Maxime Ripard
   5  *
   6  * Maxime Ripard <maxime.ripard@free-electrons.com>
   7  *
   8  * This file is licensed under the terms of the GNU General Public
   9  * License version 2.  This program is licensed "as is" without any
  10  * warranty of any kind, whether express or implied.
  11  */
  12
  13 #include <linux/io.h>
  14 #include <linux/clk.h>
  15 #include <linux/gpio.h>
  16 #include <linux/irqdomain.h>
  17 #include <linux/module.h>
  18 #include <linux/of.h>
  19 #include <linux/of_address.h>
  20 #include <linux/of_device.h>
  21 #include <linux/of_irq.h>
  22 #include <linux/pinctrl/consumer.h>
  23 #include <linux/pinctrl/machine.h>
  24 #include <linux/pinctrl/pinctrl.h>
  25 #include <linux/pinctrl/pinconf-generic.h>
  26 #include <linux/pinctrl/pinmux.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/slab.h>
  29
  30 #include "core.h"
  31 #include "pinctrl-sunxi.h"
  32 #include "pinctrl-sunxi-pins.h"
  33
  34 static struct sunxi_pinctrl_group *
  35 sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
  36 {
  37         int i;
  38
  39         for (i = 0; i < pctl->ngroups; i++) {
  40                 struct sunxi_pinctrl_group *grp = pctl->groups + i;
  41
  42                 if (!strcmp(grp->name, group))
  43                         return grp;
  44         }
  45
  46         return NULL;
  47 }
  48
  49 static struct sunxi_pinctrl_function *
  50 sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl,
  51                                     const char *name)
  52 {
  53         struct sunxi_pinctrl_function *func = pctl->functions;
  54         int i;
  55
  56         for (i = 0; i < pctl->nfunctions; i++) {
  57                 if (!func[i].name)
  58                         break;
  59
  60                 if (!strcmp(func[i].name, name))
  61                         return func + i;
  62         }
  63
  64         return NULL;
  65 }
  66
  67 static struct sunxi_desc_function *
  68 sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl,
  69                                          const char *pin_name,
  70                                          const char *func_name)
  71 {
  72         int i;
  73
  74         for (i = 0; i < pctl->desc->npins; i++) {
  75                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
  76
  77                 if (!strcmp(pin->pin.name, pin_name)) {
  78                         struct sunxi_desc_function *func = pin->functions;
  79
  80                         while (func->name) {
  81                                 if (!strcmp(func->name, func_name))
  82                                         return func;
  83
  84                                 func++;
  85                         }
  86                 }
  87         }
  88
  89         return NULL;
  90 }
  91
  92 static struct sunxi_desc_function *
  93 sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl,
  94                                         const u16 pin_num,
  95                                         const char *func_name)
  96 {
  97         int i;
  98
  99         for (i = 0; i < pctl->desc->npins; i++) {
 100                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
 101
 102                 if (pin->pin.number == pin_num) {
 103                         struct sunxi_desc_function *func = pin->functions;
 104
 105                         while (func->name) {
 106                                 if (!strcmp(func->name, func_name))
 107                                         return func;
 108
 109                                 func++;
 110                         }
 111                 }
 112         }
 113
 114         return NULL;
 115 }
 116
 117 static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
 118 {
 119         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 120
 121         return pctl->ngroups;
 122 }
 123
 124 static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev,
 125                                               unsigned group)
 126 {
 127         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 128
 129         return pctl->groups[group].name;
 130 }
 131
 132 static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
 133                                       unsigned group,
 134                                       const unsigned **pins,
 135                                       unsigned *num_pins)
 136 {
 137         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 138
 139         *pins = (unsigned *)&pctl->groups[group].pin;
 140         *num_pins = 1;
 141
 142         return 0;
 143 }
 144
 145 static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
 146                                       struct device_node *node,
 147                                       struct pinctrl_map **map,
 148                                       unsigned *num_maps)
 149 {
 150         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 151         unsigned long *pinconfig;
 152         struct property *prop;
 153         const char *function;
 154         const char *group;
 155         int ret, nmaps, i = 0;
 156         u32 val;
 157
 158         *map = NULL;
 159         *num_maps = 0;
 160
 161         ret = of_property_read_string(node, "allwinner,function", &function);
 162         if (ret) {
 163                 dev_err(pctl->dev,
 164                         "missing allwinner,function property in node %s\n",
 165                         node->name);
 166                 return -EINVAL;
 167         }
 168
 169         nmaps = of_property_count_strings(node, "allwinner,pins") * 2;
 170         if (nmaps < 0) {
 171                 dev_err(pctl->dev,
 172                         "missing allwinner,pins property in node %s\n",
 173                         node->name);
 174                 return -EINVAL;
 175         }
 176
 177         *map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL);
 178         if (!*map)
 179                 return -ENOMEM;
 180
 181         of_property_for_each_string(node, "allwinner,pins", prop, group) {
 182                 struct sunxi_pinctrl_group *grp =
 183                         sunxi_pinctrl_find_group_by_name(pctl, group);
 184                 int j = 0, configlen = 0;
 185
 186                 if (!grp) {
 187                         dev_err(pctl->dev, "unknown pin %s", group);
 188                         continue;
 189                 }
 190
 191                 if (!sunxi_pinctrl_desc_find_function_by_name(pctl,
 192                                                               grp->name,
 193                                                               function)) {
 194                         dev_err(pctl->dev, "unsupported function %s on pin %s",
 195                                 function, group);
 196                         continue;
 197                 }
 198
 199                 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP;
 200                 (*map)[i].data.mux.group = group;
 201                 (*map)[i].data.mux.function = function;
 202
 203                 i++;
 204
 205                 (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
 206                 (*map)[i].data.configs.group_or_pin = group;
 207
 208                 if (of_find_property(node, "allwinner,drive", NULL))
 209                         configlen++;
 210                 if (of_find_property(node, "allwinner,pull", NULL))
 211                         configlen++;
 212
 213                 pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL);
 214
 215                 if (!of_property_read_u32(node, "allwinner,drive", &val)) {
 216                         u16 strength = (val + 1) * 10;
 217                         pinconfig[j++] =
 218                                 pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH,
 219                                                          strength);
 220                 }
 221
 222                 if (!of_property_read_u32(node, "allwinner,pull", &val)) {
 223                         enum pin_config_param pull = PIN_CONFIG_END;
 224                         if (val == 1)
 225                                 pull = PIN_CONFIG_BIAS_PULL_UP;
 226                         else if (val == 2)
 227                                 pull = PIN_CONFIG_BIAS_PULL_DOWN;
 228                         pinconfig[j++] = pinconf_to_config_packed(pull, 0);
 229                 }
 230
 231                 (*map)[i].data.configs.configs = pinconfig;
 232                 (*map)[i].data.configs.num_configs = configlen;
 233
 234                 i++;
 235         }
 236
 237         *num_maps = nmaps;
 238
 239         return 0;
 240 }
 241
 242 static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
 243                                     struct pinctrl_map *map,
 244                                     unsigned num_maps)
 245 {
 246         int i;
 247
 248         for (i = 0; i < num_maps; i++) {
 249                 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
 250                         kfree(map[i].data.configs.configs);
 251         }
 252
 253         kfree(map);
 254 }
 255
 256 static const struct pinctrl_ops sunxi_pctrl_ops = {
 257         .dt_node_to_map         = sunxi_pctrl_dt_node_to_map,
 258         .dt_free_map            = sunxi_pctrl_dt_free_map,
 259         .get_groups_count       = sunxi_pctrl_get_groups_count,
 260         .get_group_name         = sunxi_pctrl_get_group_name,
 261         .get_group_pins         = sunxi_pctrl_get_group_pins,
 262 };
 263
 264 static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev,
 265                                  unsigned group,
 266                                  unsigned long *config)
 267 {
 268         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 269
 270         *config = pctl->groups[group].config;
 271
 272         return 0;
 273 }
 274
 275 static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
 276                                  unsigned group,
 277                                  unsigned long *configs,
 278                                  unsigned num_configs)
 279 {
 280         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 281         struct sunxi_pinctrl_group *g = &pctl->groups[group];
 282         unsigned long flags;
 283         u32 val, mask;
 284         u16 strength;
 285         u8 dlevel;
 286         int i;
 287
 288         spin_lock_irqsave(&pctl->lock, flags);
 289
 290         for (i = 0; i < num_configs; i++) {
 291                 switch (pinconf_to_config_param(configs[i])) {
 292                 case PIN_CONFIG_DRIVE_STRENGTH:
 293                         strength = pinconf_to_config_argument(configs[i]);
 294                         if (strength > 40)
 295                                 return -EINVAL;
 296                         /*
 297                          * We convert from mA to what the register expects:
 298                          *   0: 10mA
 299                          *   1: 20mA
 300                          *   2: 30mA
 301                          *   3: 40mA
 302                          */
 303                         dlevel = strength / 10 - 1;
 304                         val = readl(pctl->membase + sunxi_dlevel_reg(g->pin));
 305                         mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(g->pin);
 306                         writel((val & ~mask)
 307                                 | dlevel << sunxi_dlevel_offset(g->pin),
 308                                 pctl->membase + sunxi_dlevel_reg(g->pin));
 309                         break;
 310                 case PIN_CONFIG_BIAS_PULL_UP:
 311                         val = readl(pctl->membase + sunxi_pull_reg(g->pin));
 312                         mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
 313                         writel((val & ~mask) | 1 << sunxi_pull_offset(g->pin),
 314                                 pctl->membase + sunxi_pull_reg(g->pin));
 315                         break;
 316                 case PIN_CONFIG_BIAS_PULL_DOWN:
 317                         val = readl(pctl->membase + sunxi_pull_reg(g->pin));
 318                         mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
 319                         writel((val & ~mask) | 2 << sunxi_pull_offset(g->pin),
 320                                 pctl->membase + sunxi_pull_reg(g->pin));
 321                         break;
 322                 default:
 323                         break;
 324                 }
 325                 /* cache the config value */
 326                 g->config = configs[i];
 327         } /* for each config */
 328
 329         spin_unlock_irqrestore(&pctl->lock, flags);
 330
 331         return 0;
 332 }
 333
 334 static const struct pinconf_ops sunxi_pconf_ops = {
 335         .pin_config_group_get   = sunxi_pconf_group_get,
 336         .pin_config_group_set   = sunxi_pconf_group_set,
 337 };
 338
 339 static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
 340 {
 341         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 342
 343         return pctl->nfunctions;
 344 }
 345
 346 static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev,
 347                                            unsigned function)
 348 {
 349         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 350
 351         return pctl->functions[function].name;
 352 }
 353
 354 static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev,
 355                                      unsigned function,
 356                                      const char * const **groups,
 357                                      unsigned * const num_groups)
 358 {
 359         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 360
 361         *groups = pctl->functions[function].groups;
 362         *num_groups = pctl->functions[function].ngroups;
 363
 364         return 0;
 365 }
 366
 367 static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
 368                                  unsigned pin,
 369                                  u8 config)
 370 {
 371         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 372         unsigned long flags;
 373         u32 val, mask;
 374
 375         spin_lock_irqsave(&pctl->lock, flags);
 376
 377         val = readl(pctl->membase + sunxi_mux_reg(pin));
 378         mask = MUX_PINS_MASK << sunxi_mux_offset(pin);
 379         writel((val & ~mask) | config << sunxi_mux_offset(pin),
 380                 pctl->membase + sunxi_mux_reg(pin));
 381
 382         spin_unlock_irqrestore(&pctl->lock, flags);
 383 }
 384
 385 static int sunxi_pmx_enable(struct pinctrl_dev *pctldev,
 386                             unsigned function,
 387                             unsigned group)
 388 {
 389         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 390         struct sunxi_pinctrl_group *g = pctl->groups + group;
 391         struct sunxi_pinctrl_function *func = pctl->functions + function;
 392         struct sunxi_desc_function *desc =
 393                 sunxi_pinctrl_desc_find_function_by_name(pctl,
 394                                                          g->name,
 395                                                          func->name);
 396
 397         if (!desc)
 398                 return -EINVAL;
 399
 400         sunxi_pmx_set(pctldev, g->pin, desc->muxval);
 401
 402         return 0;
 403 }
 404
 405 static int
 406 sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
 407                         struct pinctrl_gpio_range *range,
 408                         unsigned offset,
 409                         bool input)
 410 {
 411         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 412         struct sunxi_desc_function *desc;
 413         const char *func;
 414
 415         if (input)
 416                 func = "gpio_in";
 417         else
 418                 func = "gpio_out";
 419
 420         desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func);
 421         if (!desc)
 422                 return -EINVAL;
 423
 424         sunxi_pmx_set(pctldev, offset, desc->muxval);
 425
 426         return 0;
 427 }
 428
 429 static const struct pinmux_ops sunxi_pmx_ops = {
 430         .get_functions_count    = sunxi_pmx_get_funcs_cnt,
 431         .get_function_name      = sunxi_pmx_get_func_name,
 432         .get_function_groups    = sunxi_pmx_get_func_groups,
 433         .enable                 = sunxi_pmx_enable,
 434         .gpio_set_direction     = sunxi_pmx_gpio_set_direction,
 435 };
 436
 437 static struct pinctrl_desc sunxi_pctrl_desc = {
 438         .confops        = &sunxi_pconf_ops,
 439         .pctlops        = &sunxi_pctrl_ops,
 440         .pmxops         = &sunxi_pmx_ops,
 441 };
 442
 443 static int sunxi_pinctrl_gpio_request(struct gpio_chip *chip, unsigned offset)
 444 {
 445         return pinctrl_request_gpio(chip->base + offset);
 446 }
 447
 448 static void sunxi_pinctrl_gpio_free(struct gpio_chip *chip, unsigned offset)
 449 {
 450         pinctrl_free_gpio(chip->base + offset);
 451 }
 452
 453 static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip,
 454                                         unsigned offset)
 455 {
 456         return pinctrl_gpio_direction_input(chip->base + offset);
 457 }
 458
 459 static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
 460 {
 461         struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
 462
 463         u32 reg = sunxi_data_reg(offset);
 464         u8 index = sunxi_data_offset(offset);
 465         u32 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;
 466
 467         return val;
 468 }
 469
 470 static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip,
 471                                         unsigned offset, int value)
 472 {
 473         return pinctrl_gpio_direction_output(chip->base + offset);
 474 }
 475
 476 static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
 477                                 unsigned offset, int value)
 478 {
 479         struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
 480         u32 reg = sunxi_data_reg(offset);
 481         u8 index = sunxi_data_offset(offset);
 482         unsigned long flags;
 483         u32 regval;
 484
 485         spin_lock_irqsave(&pctl->lock, flags);
 486
 487         regval = readl(pctl->membase + reg);
 488
 489         if (value)
 490                 regval |= BIT(index);
 491         else
 492                 regval &= ~(BIT(index));
 493
 494         writel(regval, pctl->membase + reg);
 495
 496         spin_unlock_irqrestore(&pctl->lock, flags);
 497 }
 498
 499 static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
 500                                 const struct of_phandle_args *gpiospec,
 501                                 u32 *flags)
 502 {
 503         int pin, base;
 504
 505         base = PINS_PER_BANK * gpiospec->args[0];
 506         pin = base + gpiospec->args[1];
 507
 508         if (pin > (gc->base + gc->ngpio))
 509                 return -EINVAL;
 510
 511         if (flags)
 512                 *flags = gpiospec->args[2];
 513
 514         return pin;
 515 }
 516
 517 static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 518 {
 519         struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
 520         struct sunxi_desc_function *desc;
 521
 522         if (offset > chip->ngpio)
 523                 return -ENXIO;
 524
 525         desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, "irq");
 526         if (!desc)
 527                 return -EINVAL;
 528
 529         pctl->irq_array[desc->irqnum] = offset;
 530
 531         dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
 532                 chip->label, offset + chip->base, desc->irqnum);
 533
 534         return irq_find_mapping(pctl->domain, desc->irqnum);
 535 }
 536
 537 static struct gpio_chip sunxi_pinctrl_gpio_chip = {
 538         .owner                  = THIS_MODULE,
 539         .request                = sunxi_pinctrl_gpio_request,
 540         .free                   = sunxi_pinctrl_gpio_free,
 541         .direction_input        = sunxi_pinctrl_gpio_direction_input,
 542         .direction_output       = sunxi_pinctrl_gpio_direction_output,
 543         .get                    = sunxi_pinctrl_gpio_get,
 544         .set                    = sunxi_pinctrl_gpio_set,
 545         .of_xlate               = sunxi_pinctrl_gpio_of_xlate,
 546         .to_irq                 = sunxi_pinctrl_gpio_to_irq,
 547         .of_gpio_n_cells        = 3,
 548         .can_sleep              = 0,
 549 };
 550
 551 static int sunxi_pinctrl_irq_set_type(struct irq_data *d,
 552                                       unsigned int type)
 553 {
 554         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
 555         u32 reg = sunxi_irq_cfg_reg(d->hwirq);
 556         u8 index = sunxi_irq_cfg_offset(d->hwirq);
 557         unsigned long flags;
 558         u32 regval;
 559         u8 mode;
 560
 561         switch (type) {
 562         case IRQ_TYPE_EDGE_RISING:
 563                 mode = IRQ_EDGE_RISING;
 564                 break;
 565         case IRQ_TYPE_EDGE_FALLING:
 566                 mode = IRQ_EDGE_FALLING;
 567                 break;
 568         case IRQ_TYPE_EDGE_BOTH:
 569                 mode = IRQ_EDGE_BOTH;
 570                 break;
 571         case IRQ_TYPE_LEVEL_HIGH:
 572                 mode = IRQ_LEVEL_HIGH;
 573                 break;
 574         case IRQ_TYPE_LEVEL_LOW:
 575                 mode = IRQ_LEVEL_LOW;
 576                 break;
 577         default:
 578                 return -EINVAL;
 579         }
 580
 581         spin_lock_irqsave(&pctl->lock, flags);
 582
 583         regval = readl(pctl->membase + reg);
 584         regval &= ~IRQ_CFG_IRQ_MASK;
 585         writel(regval | (mode << index), pctl->membase + reg);
 586
 587         spin_unlock_irqrestore(&pctl->lock, flags);
 588
 589         return 0;
 590 }
 591
 592 static void sunxi_pinctrl_irq_mask_ack(struct irq_data *d)
 593 {
 594         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
 595         u32 ctrl_reg = sunxi_irq_ctrl_reg(d->hwirq);
 596         u8 ctrl_idx = sunxi_irq_ctrl_offset(d->hwirq);
 597         u32 status_reg = sunxi_irq_status_reg(d->hwirq);
 598         u8 status_idx = sunxi_irq_status_offset(d->hwirq);
 599         unsigned long flags;
 600         u32 val;
 601
 602         spin_lock_irqsave(&pctl->lock, flags);
 603
 604         /* Mask the IRQ */
 605         val = readl(pctl->membase + ctrl_reg);
 606         writel(val & ~(1 << ctrl_idx), pctl->membase + ctrl_reg);
 607
 608         /* Clear the IRQ */
 609         writel(1 << status_idx, pctl->membase + status_reg);
 610
 611         spin_unlock_irqrestore(&pctl->lock, flags);
 612 }
 613
 614 static void sunxi_pinctrl_irq_mask(struct irq_data *d)
 615 {
 616         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
 617         u32 reg = sunxi_irq_ctrl_reg(d->hwirq);
 618         u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
 619         unsigned long flags;
 620         u32 val;
 621
 622         spin_lock_irqsave(&pctl->lock, flags);
 623
 624         /* Mask the IRQ */
 625         val = readl(pctl->membase + reg);
 626         writel(val & ~(1 << idx), pctl->membase + reg);
 627
 628         spin_unlock_irqrestore(&pctl->lock, flags);
 629 }
 630
 631 static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
 632 {
 633         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
 634         struct sunxi_desc_function *func;
 635         u32 reg = sunxi_irq_ctrl_reg(d->hwirq);
 636         u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
 637         unsigned long flags;
 638         u32 val;
 639
 640         func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
 641                                                        pctl->irq_array[d->hwirq],
 642                                                        "irq");
 643
 644         /* Change muxing to INT mode */
 645         sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
 646
 647         spin_lock_irqsave(&pctl->lock, flags);
 648
 649         /* Unmask the IRQ */
 650         val = readl(pctl->membase + reg);
 651         writel(val | (1 << idx), pctl->membase + reg);
 652
 653         spin_unlock_irqrestore(&pctl->lock, flags);
 654 }
 655
 656 static struct irq_chip sunxi_pinctrl_irq_chip = {
 657         .irq_mask       = sunxi_pinctrl_irq_mask,
 658         .irq_mask_ack   = sunxi_pinctrl_irq_mask_ack,
 659         .irq_unmask     = sunxi_pinctrl_irq_unmask,
 660         .irq_set_type   = sunxi_pinctrl_irq_set_type,
 661 };
 662
 663 static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc)
 664 {
 665         struct sunxi_pinctrl *pctl = irq_get_handler_data(irq);
 666         const unsigned long reg = readl(pctl->membase + IRQ_STATUS_REG);
 667
 668         /* Clear all interrupts */
 669         writel(reg, pctl->membase + IRQ_STATUS_REG);
 670
 671         if (reg) {
 672                 int irqoffset;
 673
 674                 for_each_set_bit(irqoffset, &reg, SUNXI_IRQ_NUMBER) {
 675                         int pin_irq = irq_find_mapping(pctl->domain, irqoffset);
 676                         generic_handle_irq(pin_irq);
 677                 }
 678         }
 679 }
 680
 681 static struct of_device_id sunxi_pinctrl_match[] = {
 682         { .compatible = "allwinner,sun4i-a10-pinctrl", .data = (void *)&sun4i_a10_pinctrl_data },
 683         { .compatible = "allwinner,sun5i-a10s-pinctrl", .data = (void *)&sun5i_a10s_pinctrl_data },
 684         { .compatible = "allwinner,sun5i-a13-pinctrl", .data = (void *)&sun5i_a13_pinctrl_data },
 685         { .compatible = "allwinner,sun6i-a31-pinctrl", .data = (void *)&sun6i_a31_pinctrl_data },
 686         { .compatible = "allwinner,sun7i-a20-pinctrl", .data = (void *)&sun7i_a20_pinctrl_data },
 687         {}
 688 };
 689 MODULE_DEVICE_TABLE(of, sunxi_pinctrl_match);
 690
 691 static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,
 692                                         const char *name)
 693 {
 694         struct sunxi_pinctrl_function *func = pctl->functions;
 695
 696         while (func->name) {
 697                 /* function already there */
 698                 if (strcmp(func->name, name) == 0) {
 699                         func->ngroups++;
 700                         return -EEXIST;
 701                 }
 702                 func++;
 703         }
 704
 705         func->name = name;
 706         func->ngroups = 1;
 707
 708         pctl->nfunctions++;
 709
 710         return 0;
 711 }
 712
 713 static int sunxi_pinctrl_build_state(struct platform_device *pdev)
 714 {
 715         struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev);
 716         int i;
 717
 718         pctl->ngroups = pctl->desc->npins;
 719
 720         /* Allocate groups */
 721         pctl->groups = devm_kzalloc(&pdev->dev,
 722                                     pctl->ngroups * sizeof(*pctl->groups),
 723                                     GFP_KERNEL);
 724         if (!pctl->groups)
 725                 return -ENOMEM;
 726
 727         for (i = 0; i < pctl->desc->npins; i++) {
 728                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
 729                 struct sunxi_pinctrl_group *group = pctl->groups + i;
 730
 731                 group->name = pin->pin.name;
 732                 group->pin = pin->pin.number;
 733         }
 734
 735         /*
 736          * We suppose that we won't have any more functions than pins,
 737          * we'll reallocate that later anyway
 738          */
 739         pctl->functions = devm_kzalloc(&pdev->dev,
 740                                 pctl->desc->npins * sizeof(*pctl->functions),
 741                                 GFP_KERNEL);
 742         if (!pctl->functions)
 743                 return -ENOMEM;
 744
 745         /* Count functions and their associated groups */
 746         for (i = 0; i < pctl->desc->npins; i++) {
 747                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
 748                 struct sunxi_desc_function *func = pin->functions;
 749
 750                 while (func->name) {
 751                         sunxi_pinctrl_add_function(pctl, func->name);
 752                         func++;
 753                 }
 754         }
 755
 756         pctl->functions = krealloc(pctl->functions,
 757                                 pctl->nfunctions * sizeof(*pctl->functions),
 758                                 GFP_KERNEL);
 759
 760         for (i = 0; i < pctl->desc->npins; i++) {
 761                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
 762                 struct sunxi_desc_function *func = pin->functions;
 763
 764                 while (func->name) {
 765                         struct sunxi_pinctrl_function *func_item;
 766                         const char **func_grp;
 767
 768                         func_item = sunxi_pinctrl_find_function_by_name(pctl,
 769                                                                         func->name);
 770                         if (!func_item)
 771                                 return -EINVAL;
 772
 773                         if (!func_item->groups) {
 774                                 func_item->groups =
 775                                         devm_kzalloc(&pdev->dev,
 776                                                      func_item->ngroups * sizeof(*func_item->groups),
 777                                                      GFP_KERNEL);
 778                                 if (!func_item->groups)
 779                                         return -ENOMEM;
 780                         }
 781
 782                         func_grp = func_item->groups;
 783                         while (*func_grp)
 784                                 func_grp++;
 785
 786                         *func_grp = pin->pin.name;
 787                         func++;
 788                 }
 789         }
 790
 791         return 0;
 792 }
 793
 794 static int sunxi_pinctrl_probe(struct platform_device *pdev)
 795 {
 796         struct device_node *node = pdev->dev.of_node;
 797         const struct of_device_id *device;
 798         struct pinctrl_pin_desc *pins;
 799         struct sunxi_pinctrl *pctl;
 800         int i, ret, last_pin;
 801         struct clk *clk;
 802
 803         pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
 804         if (!pctl)
 805                 return -ENOMEM;
 806         platform_set_drvdata(pdev, pctl);
 807
 808         spin_lock_init(&pctl->lock);
 809
 810         pctl->membase = of_iomap(node, 0);
 811         if (!pctl->membase)
 812                 return -ENOMEM;
 813
 814         device = of_match_device(sunxi_pinctrl_match, &pdev->dev);
 815         if (!device)
 816                 return -ENODEV;
 817
 818         pctl->desc = (struct sunxi_pinctrl_desc *)device->data;
 819
 820         ret = sunxi_pinctrl_build_state(pdev);
 821         if (ret) {
 822                 dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
 823                 return ret;
 824         }
 825
 826         pins = devm_kzalloc(&pdev->dev,
 827                             pctl->desc->npins * sizeof(*pins),
 828                             GFP_KERNEL);
 829         if (!pins)
 830                 return -ENOMEM;
 831
 832         for (i = 0; i < pctl->desc->npins; i++)
 833                 pins[i] = pctl->desc->pins[i].pin;
 834
 835         sunxi_pctrl_desc.name = dev_name(&pdev->dev);
 836         sunxi_pctrl_desc.owner = THIS_MODULE;
 837         sunxi_pctrl_desc.pins = pins;
 838         sunxi_pctrl_desc.npins = pctl->desc->npins;
 839         pctl->dev = &pdev->dev;
 840         pctl->pctl_dev = pinctrl_register(&sunxi_pctrl_desc,
 841                                           &pdev->dev, pctl);
 842         if (!pctl->pctl_dev) {
 843                 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
 844                 return -EINVAL;
 845         }
 846
 847         pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
 848         if (!pctl->chip) {
 849                 ret = -ENOMEM;
 850                 goto pinctrl_error;
 851         }
 852
 853         last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;
 854         pctl->chip = &sunxi_pinctrl_gpio_chip;
 855         pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK);
 856         pctl->chip->label = dev_name(&pdev->dev);
 857         pctl->chip->dev = &pdev->dev;
 858         pctl->chip->base = 0;
 859
 860         ret = gpiochip_add(pctl->chip);
 861         if (ret)
 862                 goto pinctrl_error;
 863
 864         for (i = 0; i < pctl->desc->npins; i++) {
 865                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
 866
 867                 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
 868                                              pin->pin.number,
 869                                              pin->pin.number, 1);
 870                 if (ret)
 871                         goto gpiochip_error;
 872         }
 873
 874         clk = devm_clk_get(&pdev->dev, NULL);
 875         if (IS_ERR(clk)) {
 876                 ret = PTR_ERR(clk);
 877                 goto gpiochip_error;
 878         }
 879
 880         clk_prepare_enable(clk);
 881
 882         pctl->irq = irq_of_parse_and_map(node, 0);
 883         if (!pctl->irq) {
 884                 ret = -EINVAL;
 885                 goto gpiochip_error;
 886         }
 887
 888         pctl->domain = irq_domain_add_linear(node, SUNXI_IRQ_NUMBER,
 889                                              &irq_domain_simple_ops, NULL);
 890         if (!pctl->domain) {
 891                 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
 892                 ret = -ENOMEM;
 893                 goto gpiochip_error;
 894         }
 895
 896         for (i = 0; i < SUNXI_IRQ_NUMBER; i++) {
 897                 int irqno = irq_create_mapping(pctl->domain, i);
 898
 899                 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_irq_chip,
 900                                          handle_simple_irq);
 901                 irq_set_chip_data(irqno, pctl);
 902         };
 903
 904         irq_set_chained_handler(pctl->irq, sunxi_pinctrl_irq_handler);
 905         irq_set_handler_data(pctl->irq, pctl);
 906
 907         dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
 908
 909         return 0;
 910
 911 gpiochip_error:
 912         if (gpiochip_remove(pctl->chip))
 913                 dev_err(&pdev->dev, "failed to remove gpio chip\n");
 914 pinctrl_error:
 915         pinctrl_unregister(pctl->pctl_dev);
 916         return ret;
 917 }
 918
 919 static struct platform_driver sunxi_pinctrl_driver = {
 920         .probe = sunxi_pinctrl_probe,
 921         .driver = {
 922                 .name = "sunxi-pinctrl",
 923                 .owner = THIS_MODULE,
 924                 .of_match_table = sunxi_pinctrl_match,
 925         },
 926 };
 927 module_platform_driver(sunxi_pinctrl_driver);
 928
 929 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
 930 MODULE_DESCRIPTION("Allwinner A1X pinctrl driver");
 931 MODULE_LICENSE("GPL");