2 * pinmux driver for CSR SiRFprimaII
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
6 * Licensed under GPLv2 or later.
9 #include <linux/init.h>
10 #include <linux/module.h>
11 #include <linux/irq.h>
12 #include <linux/platform_device.h>
14 #include <linux/slab.h>
15 #include <linux/err.h>
16 #include <linux/irqdomain.h>
17 #include <linux/pinctrl/pinctrl.h>
18 #include <linux/pinctrl/pinmux.h>
19 #include <linux/pinctrl/consumer.h>
20 #include <linux/pinctrl/machine.h>
22 #include <linux/of_address.h>
23 #include <linux/of_device.h>
24 #include <linux/of_platform.h>
25 #include <linux/bitops.h>
26 #include <linux/gpio.h>
27 #include <linux/of_gpio.h>
29 #define DRIVER_NAME "pinmux-sirf"
31 #define SIRFSOC_NUM_PADS 622
32 #define SIRFSOC_RSC_PIN_MUX 0x4
34 #define SIRFSOC_GPIO_PAD_EN(g) ((g)*0x100 + 0x84)
35 #define SIRFSOC_GPIO_CTRL(g, i) ((g)*0x100 + (i)*4)
36 #define SIRFSOC_GPIO_DSP_EN0 (0x80)
37 #define SIRFSOC_GPIO_PAD_EN(g) ((g)*0x100 + 0x84)
38 #define SIRFSOC_GPIO_INT_STATUS(g) ((g)*0x100 + 0x8C)
40 #define SIRFSOC_GPIO_CTL_INTR_LOW_MASK 0x1
41 #define SIRFSOC_GPIO_CTL_INTR_HIGH_MASK 0x2
42 #define SIRFSOC_GPIO_CTL_INTR_TYPE_MASK 0x4
43 #define SIRFSOC_GPIO_CTL_INTR_EN_MASK 0x8
44 #define SIRFSOC_GPIO_CTL_INTR_STS_MASK 0x10
45 #define SIRFSOC_GPIO_CTL_OUT_EN_MASK 0x20
46 #define SIRFSOC_GPIO_CTL_DATAOUT_MASK 0x40
47 #define SIRFSOC_GPIO_CTL_DATAIN_MASK 0x80
48 #define SIRFSOC_GPIO_CTL_PULL_MASK 0x100
49 #define SIRFSOC_GPIO_CTL_PULL_HIGH 0x200
50 #define SIRFSOC_GPIO_CTL_DSP_INT 0x400
52 #define SIRFSOC_GPIO_NO_OF_BANKS 5
53 #define SIRFSOC_GPIO_BANK_SIZE 32
54 #define SIRFSOC_GPIO_NUM(bank, index) (((bank)*(32)) + (index))
56 struct sirfsoc_gpio_bank {
57 struct of_mm_gpio_chip chip;
58 struct irq_domain *domain;
64 static struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS];
65 static DEFINE_SPINLOCK(sgpio_lock);
68 * pad list for the pinmux subsystem
69 * refer to CS-131858-DC-6A.xls
71 static const struct pinctrl_pin_desc sirfsoc_pads[] = {
72 PINCTRL_PIN(4, "pwm0"),
73 PINCTRL_PIN(5, "pwm1"),
74 PINCTRL_PIN(6, "pwm2"),
75 PINCTRL_PIN(7, "pwm3"),
76 PINCTRL_PIN(8, "warm_rst_b"),
77 PINCTRL_PIN(9, "odo_0"),
78 PINCTRL_PIN(10, "odo_1"),
79 PINCTRL_PIN(11, "dr_dir"),
80 PINCTRL_PIN(13, "scl_1"),
81 PINCTRL_PIN(15, "sda_1"),
82 PINCTRL_PIN(16, "x_ldd[16]"),
83 PINCTRL_PIN(17, "x_ldd[17]"),
84 PINCTRL_PIN(18, "x_ldd[18]"),
85 PINCTRL_PIN(19, "x_ldd[19]"),
86 PINCTRL_PIN(20, "x_ldd[20]"),
87 PINCTRL_PIN(21, "x_ldd[21]"),
88 PINCTRL_PIN(22, "x_ldd[22]"),
89 PINCTRL_PIN(23, "x_ldd[23], lcdrom_frdy"),
90 PINCTRL_PIN(24, "gps_sgn"),
91 PINCTRL_PIN(25, "gps_mag"),
92 PINCTRL_PIN(26, "gps_clk"),
93 PINCTRL_PIN(27, "sd_cd_b_1"),
94 PINCTRL_PIN(28, "sd_vcc_on_1"),
95 PINCTRL_PIN(29, "sd_wp_b_1"),
96 PINCTRL_PIN(30, "sd_clk_3"),
97 PINCTRL_PIN(31, "sd_cmd_3"),
99 PINCTRL_PIN(32, "x_sd_dat_3[0]"),
100 PINCTRL_PIN(33, "x_sd_dat_3[1]"),
101 PINCTRL_PIN(34, "x_sd_dat_3[2]"),
102 PINCTRL_PIN(35, "x_sd_dat_3[3]"),
103 PINCTRL_PIN(36, "x_sd_clk_4"),
104 PINCTRL_PIN(37, "x_sd_cmd_4"),
105 PINCTRL_PIN(38, "x_sd_dat_4[0]"),
106 PINCTRL_PIN(39, "x_sd_dat_4[1]"),
107 PINCTRL_PIN(40, "x_sd_dat_4[2]"),
108 PINCTRL_PIN(41, "x_sd_dat_4[3]"),
109 PINCTRL_PIN(42, "x_cko_1"),
110 PINCTRL_PIN(43, "x_ac97_bit_clk"),
111 PINCTRL_PIN(44, "x_ac97_dout"),
112 PINCTRL_PIN(45, "x_ac97_din"),
113 PINCTRL_PIN(46, "x_ac97_sync"),
114 PINCTRL_PIN(47, "x_txd_1"),
115 PINCTRL_PIN(48, "x_txd_2"),
116 PINCTRL_PIN(49, "x_rxd_1"),
117 PINCTRL_PIN(50, "x_rxd_2"),
118 PINCTRL_PIN(51, "x_usclk_0"),
119 PINCTRL_PIN(52, "x_utxd_0"),
120 PINCTRL_PIN(53, "x_urxd_0"),
121 PINCTRL_PIN(54, "x_utfs_0"),
122 PINCTRL_PIN(55, "x_urfs_0"),
123 PINCTRL_PIN(56, "x_usclk_1"),
124 PINCTRL_PIN(57, "x_utxd_1"),
125 PINCTRL_PIN(58, "x_urxd_1"),
126 PINCTRL_PIN(59, "x_utfs_1"),
127 PINCTRL_PIN(60, "x_urfs_1"),
128 PINCTRL_PIN(61, "x_usclk_2"),
129 PINCTRL_PIN(62, "x_utxd_2"),
130 PINCTRL_PIN(63, "x_urxd_2"),
132 PINCTRL_PIN(64, "x_utfs_2"),
133 PINCTRL_PIN(65, "x_urfs_2"),
134 PINCTRL_PIN(66, "x_df_we_b"),
135 PINCTRL_PIN(67, "x_df_re_b"),
136 PINCTRL_PIN(68, "x_txd_0"),
137 PINCTRL_PIN(69, "x_rxd_0"),
138 PINCTRL_PIN(78, "x_cko_0"),
139 PINCTRL_PIN(79, "x_vip_pxd[7]"),
140 PINCTRL_PIN(80, "x_vip_pxd[6]"),
141 PINCTRL_PIN(81, "x_vip_pxd[5]"),
142 PINCTRL_PIN(82, "x_vip_pxd[4]"),
143 PINCTRL_PIN(83, "x_vip_pxd[3]"),
144 PINCTRL_PIN(84, "x_vip_pxd[2]"),
145 PINCTRL_PIN(85, "x_vip_pxd[1]"),
146 PINCTRL_PIN(86, "x_vip_pxd[0]"),
147 PINCTRL_PIN(87, "x_vip_vsync"),
148 PINCTRL_PIN(88, "x_vip_hsync"),
149 PINCTRL_PIN(89, "x_vip_pxclk"),
150 PINCTRL_PIN(90, "x_sda_0"),
151 PINCTRL_PIN(91, "x_scl_0"),
152 PINCTRL_PIN(92, "x_df_ry_by"),
153 PINCTRL_PIN(93, "x_df_cs_b[1]"),
154 PINCTRL_PIN(94, "x_df_cs_b[0]"),
155 PINCTRL_PIN(95, "x_l_pclk"),
157 PINCTRL_PIN(96, "x_l_lck"),
158 PINCTRL_PIN(97, "x_l_fck"),
159 PINCTRL_PIN(98, "x_l_de"),
160 PINCTRL_PIN(99, "x_ldd[0]"),
161 PINCTRL_PIN(100, "x_ldd[1]"),
162 PINCTRL_PIN(101, "x_ldd[2]"),
163 PINCTRL_PIN(102, "x_ldd[3]"),
164 PINCTRL_PIN(103, "x_ldd[4]"),
165 PINCTRL_PIN(104, "x_ldd[5]"),
166 PINCTRL_PIN(105, "x_ldd[6]"),
167 PINCTRL_PIN(106, "x_ldd[7]"),
168 PINCTRL_PIN(107, "x_ldd[8]"),
169 PINCTRL_PIN(108, "x_ldd[9]"),
170 PINCTRL_PIN(109, "x_ldd[10]"),
171 PINCTRL_PIN(110, "x_ldd[11]"),
172 PINCTRL_PIN(111, "x_ldd[12]"),
173 PINCTRL_PIN(112, "x_ldd[13]"),
174 PINCTRL_PIN(113, "x_ldd[14]"),
175 PINCTRL_PIN(114, "x_ldd[15]"),
179 * @dev: a pointer back to containing device
180 * @virtbase: the offset to the controller in virtual memory
184 struct pinctrl_dev *pmx;
185 void __iomem *gpio_virtbase;
186 void __iomem *rsc_virtbase;
189 /* SIRFSOC_GPIO_PAD_EN set */
190 struct sirfsoc_muxmask {
195 struct sirfsoc_padmux {
196 unsigned long muxmask_counts;
197 const struct sirfsoc_muxmask *muxmask;
198 /* RSC_PIN_MUX set */
199 unsigned long funcmask;
200 unsigned long funcval;
204 * struct sirfsoc_pin_group - describes a SiRFprimaII pin group
205 * @name: the name of this specific pin group
206 * @pins: an array of discrete physical pins used in this group, taken
207 * from the driver-local pin enumeration space
208 * @num_pins: the number of pins in this group array, i.e. the number of
209 * elements in .pins so we can iterate over that array
211 struct sirfsoc_pin_group {
213 const unsigned int *pins;
214 const unsigned num_pins;
217 static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
220 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
221 BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
229 static const struct sirfsoc_padmux lcd_16bits_padmux = {
230 .muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask),
231 .muxmask = lcd_16bits_sirfsoc_muxmask,
236 static const unsigned lcd_16bits_pins[] = { 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
237 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
239 static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = {
242 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
243 BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
250 .mask = BIT(16) | BIT(17),
254 static const struct sirfsoc_padmux lcd_18bits_padmux = {
255 .muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask),
256 .muxmask = lcd_18bits_muxmask,
261 static const unsigned lcd_18bits_pins[] = { 16, 17, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
262 105, 106, 107, 108, 109, 110, 111, 112, 113, 114};
264 static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = {
267 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
268 BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
275 .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
279 static const struct sirfsoc_padmux lcd_24bits_padmux = {
280 .muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask),
281 .muxmask = lcd_24bits_muxmask,
286 static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
287 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
289 static const struct sirfsoc_muxmask lcdrom_muxmask[] = {
292 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
293 BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
304 static const struct sirfsoc_padmux lcdrom_padmux = {
305 .muxmask_counts = ARRAY_SIZE(lcdrom_muxmask),
306 .muxmask = lcdrom_muxmask,
311 static const unsigned lcdrom_pins[] = { 23, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
312 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
314 static const struct sirfsoc_muxmask uart0_muxmask[] = {
317 .mask = BIT(4) | BIT(5),
320 .mask = BIT(23) | BIT(28),
324 static const struct sirfsoc_padmux uart0_padmux = {
325 .muxmask_counts = ARRAY_SIZE(uart0_muxmask),
326 .muxmask = uart0_muxmask,
331 static const unsigned uart0_pins[] = { 55, 60, 68, 69 };
333 static const struct sirfsoc_muxmask uart0_nostreamctrl_muxmask[] = {
336 .mask = BIT(4) | BIT(5),
340 static const struct sirfsoc_padmux uart0_nostreamctrl_padmux = {
341 .muxmask_counts = ARRAY_SIZE(uart0_nostreamctrl_muxmask),
342 .muxmask = uart0_nostreamctrl_muxmask,
345 static const unsigned uart0_nostreamctrl_pins[] = { 68, 39 };
347 static const struct sirfsoc_muxmask uart1_muxmask[] = {
350 .mask = BIT(15) | BIT(17),
354 static const struct sirfsoc_padmux uart1_padmux = {
355 .muxmask_counts = ARRAY_SIZE(uart1_muxmask),
356 .muxmask = uart1_muxmask,
359 static const unsigned uart1_pins[] = { 47, 49 };
361 static const struct sirfsoc_muxmask uart2_muxmask[] = {
364 .mask = BIT(16) | BIT(18) | BIT(24) | BIT(27),
368 static const struct sirfsoc_padmux uart2_padmux = {
369 .muxmask_counts = ARRAY_SIZE(uart2_muxmask),
370 .muxmask = uart2_muxmask,
375 static const unsigned uart2_pins[] = { 48, 50, 56, 59 };
377 static const struct sirfsoc_muxmask uart2_nostreamctrl_muxmask[] = {
380 .mask = BIT(16) | BIT(18),
384 static const struct sirfsoc_padmux uart2_nostreamctrl_padmux = {
385 .muxmask_counts = ARRAY_SIZE(uart2_nostreamctrl_muxmask),
386 .muxmask = uart2_nostreamctrl_muxmask,
389 static const unsigned uart2_nostreamctrl_pins[] = { 48, 50 };
391 static const struct sirfsoc_muxmask sdmmc3_muxmask[] = {
394 .mask = BIT(30) | BIT(31),
397 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
401 static const struct sirfsoc_padmux sdmmc3_padmux = {
402 .muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask),
403 .muxmask = sdmmc3_muxmask,
408 static const unsigned sdmmc3_pins[] = { 30, 31, 32, 33, 34, 35 };
410 static const struct sirfsoc_muxmask spi0_muxmask[] = {
413 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
417 static const struct sirfsoc_padmux spi0_padmux = {
418 .muxmask_counts = ARRAY_SIZE(spi0_muxmask),
419 .muxmask = spi0_muxmask,
424 static const unsigned spi0_pins[] = { 32, 33, 34, 35 };
426 static const struct sirfsoc_muxmask sdmmc4_muxmask[] = {
429 .mask = BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9),
433 static const struct sirfsoc_padmux sdmmc4_padmux = {
434 .muxmask_counts = ARRAY_SIZE(sdmmc4_muxmask),
435 .muxmask = sdmmc4_muxmask,
438 static const unsigned sdmmc4_pins[] = { 36, 37, 38, 39, 40, 41 };
440 static const struct sirfsoc_muxmask cko1_muxmask[] = {
447 static const struct sirfsoc_padmux cko1_padmux = {
448 .muxmask_counts = ARRAY_SIZE(cko1_muxmask),
449 .muxmask = cko1_muxmask,
454 static const unsigned cko1_pins[] = { 42 };
456 static const struct sirfsoc_muxmask i2s_muxmask[] = {
460 BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(19)
465 static const struct sirfsoc_padmux i2s_padmux = {
466 .muxmask_counts = ARRAY_SIZE(i2s_muxmask),
467 .muxmask = i2s_muxmask,
468 .funcmask = BIT(3) | BIT(9),
472 static const unsigned i2s_pins[] = { 42, 43, 44, 45, 46, 51, 55, 60 };
474 static const struct sirfsoc_muxmask ac97_muxmask[] = {
477 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
481 static const struct sirfsoc_padmux ac97_padmux = {
482 .muxmask_counts = ARRAY_SIZE(ac97_muxmask),
483 .muxmask = ac97_muxmask,
488 static const unsigned ac97_pins[] = { 33, 34, 35, 36 };
490 static const struct sirfsoc_muxmask spi1_muxmask[] = {
493 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
497 static const struct sirfsoc_padmux spi1_padmux = {
498 .muxmask_counts = ARRAY_SIZE(spi1_muxmask),
499 .muxmask = spi1_muxmask,
504 static const unsigned spi1_pins[] = { 43, 44, 45, 46 };
506 static const struct sirfsoc_muxmask sdmmc1_muxmask[] = {
509 .mask = BIT(27) | BIT(28) | BIT(29),
513 static const struct sirfsoc_padmux sdmmc1_padmux = {
514 .muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask),
515 .muxmask = sdmmc1_muxmask,
518 static const unsigned sdmmc1_pins[] = { 27, 28, 29 };
520 static const struct sirfsoc_muxmask gps_muxmask[] = {
523 .mask = BIT(24) | BIT(25) | BIT(26),
527 static const struct sirfsoc_padmux gps_padmux = {
528 .muxmask_counts = ARRAY_SIZE(gps_muxmask),
529 .muxmask = gps_muxmask,
530 .funcmask = BIT(12) | BIT(13) | BIT(14),
534 static const unsigned gps_pins[] = { 24, 25, 26 };
536 static const struct sirfsoc_muxmask sdmmc5_muxmask[] = {
539 .mask = BIT(24) | BIT(25) | BIT(26),
545 .mask = BIT(0) | BIT(1),
549 static const struct sirfsoc_padmux sdmmc5_padmux = {
550 .muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask),
551 .muxmask = sdmmc5_muxmask,
552 .funcmask = BIT(13) | BIT(14),
553 .funcval = BIT(13) | BIT(14),
556 static const unsigned sdmmc5_pins[] = { 24, 25, 26, 61, 64, 65 };
558 static const struct sirfsoc_muxmask usp0_muxmask[] = {
561 .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
565 static const struct sirfsoc_padmux usp0_padmux = {
566 .muxmask_counts = ARRAY_SIZE(usp0_muxmask),
567 .muxmask = usp0_muxmask,
568 .funcmask = BIT(1) | BIT(2) | BIT(6) | BIT(9),
572 static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 };
574 static const struct sirfsoc_muxmask usp1_muxmask[] = {
577 .mask = BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28),
581 static const struct sirfsoc_padmux usp1_padmux = {
582 .muxmask_counts = ARRAY_SIZE(usp1_muxmask),
583 .muxmask = usp1_muxmask,
584 .funcmask = BIT(1) | BIT(9) | BIT(10) | BIT(11),
588 static const unsigned usp1_pins[] = { 56, 57, 58, 59, 60 };
590 static const struct sirfsoc_muxmask usp2_muxmask[] = {
593 .mask = BIT(29) | BIT(30) | BIT(31),
596 .mask = BIT(0) | BIT(1),
600 static const struct sirfsoc_padmux usp2_padmux = {
601 .muxmask_counts = ARRAY_SIZE(usp2_muxmask),
602 .muxmask = usp2_muxmask,
603 .funcmask = BIT(13) | BIT(14),
607 static const unsigned usp2_pins[] = { 61, 62, 63, 64, 65 };
609 static const struct sirfsoc_muxmask nand_muxmask[] = {
612 .mask = BIT(2) | BIT(3) | BIT(28) | BIT(29) | BIT(30),
616 static const struct sirfsoc_padmux nand_padmux = {
617 .muxmask_counts = ARRAY_SIZE(nand_muxmask),
618 .muxmask = nand_muxmask,
623 static const unsigned nand_pins[] = { 64, 65, 92, 93, 94 };
625 static const struct sirfsoc_padmux sdmmc0_padmux = {
631 static const unsigned sdmmc0_pins[] = { };
633 static const struct sirfsoc_muxmask sdmmc2_muxmask[] = {
636 .mask = BIT(2) | BIT(3),
640 static const struct sirfsoc_padmux sdmmc2_padmux = {
641 .muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask),
642 .muxmask = sdmmc2_muxmask,
647 static const unsigned sdmmc2_pins[] = { 66, 67 };
649 static const struct sirfsoc_muxmask cko0_muxmask[] = {
656 static const struct sirfsoc_padmux cko0_padmux = {
657 .muxmask_counts = ARRAY_SIZE(cko0_muxmask),
658 .muxmask = cko0_muxmask,
661 static const unsigned cko0_pins[] = { 78 };
663 static const struct sirfsoc_muxmask vip_muxmask[] = {
666 .mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19)
667 | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) |
672 static const struct sirfsoc_padmux vip_padmux = {
673 .muxmask_counts = ARRAY_SIZE(vip_muxmask),
674 .muxmask = vip_muxmask,
679 static const unsigned vip_pins[] = { 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89 };
681 static const struct sirfsoc_muxmask i2c0_muxmask[] = {
684 .mask = BIT(26) | BIT(27),
688 static const struct sirfsoc_padmux i2c0_padmux = {
689 .muxmask_counts = ARRAY_SIZE(i2c0_muxmask),
690 .muxmask = i2c0_muxmask,
693 static const unsigned i2c0_pins[] = { 90, 91 };
695 static const struct sirfsoc_muxmask i2c1_muxmask[] = {
698 .mask = BIT(13) | BIT(15),
702 static const struct sirfsoc_padmux i2c1_padmux = {
703 .muxmask_counts = ARRAY_SIZE(i2c1_muxmask),
704 .muxmask = i2c1_muxmask,
707 static const unsigned i2c1_pins[] = { 13, 15 };
709 static const struct sirfsoc_muxmask viprom_muxmask[] = {
712 .mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19)
713 | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) |
721 static const struct sirfsoc_padmux viprom_padmux = {
722 .muxmask_counts = ARRAY_SIZE(viprom_muxmask),
723 .muxmask = viprom_muxmask,
728 static const unsigned viprom_pins[] = { 12, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89 };
730 static const struct sirfsoc_muxmask pwm0_muxmask[] = {
737 static const struct sirfsoc_padmux pwm0_padmux = {
738 .muxmask_counts = ARRAY_SIZE(pwm0_muxmask),
739 .muxmask = pwm0_muxmask,
744 static const unsigned pwm0_pins[] = { 4 };
746 static const struct sirfsoc_muxmask pwm1_muxmask[] = {
753 static const struct sirfsoc_padmux pwm1_padmux = {
754 .muxmask_counts = ARRAY_SIZE(pwm1_muxmask),
755 .muxmask = pwm1_muxmask,
758 static const unsigned pwm1_pins[] = { 5 };
760 static const struct sirfsoc_muxmask pwm2_muxmask[] = {
767 static const struct sirfsoc_padmux pwm2_padmux = {
768 .muxmask_counts = ARRAY_SIZE(pwm2_muxmask),
769 .muxmask = pwm2_muxmask,
772 static const unsigned pwm2_pins[] = { 6 };
774 static const struct sirfsoc_muxmask pwm3_muxmask[] = {
781 static const struct sirfsoc_padmux pwm3_padmux = {
782 .muxmask_counts = ARRAY_SIZE(pwm3_muxmask),
783 .muxmask = pwm3_muxmask,
786 static const unsigned pwm3_pins[] = { 7 };
788 static const struct sirfsoc_muxmask warm_rst_muxmask[] = {
795 static const struct sirfsoc_padmux warm_rst_padmux = {
796 .muxmask_counts = ARRAY_SIZE(warm_rst_muxmask),
797 .muxmask = warm_rst_muxmask,
800 static const unsigned warm_rst_pins[] = { 8 };
802 static const struct sirfsoc_muxmask usb0_utmi_drvbus_muxmask[] = {
808 static const struct sirfsoc_padmux usb0_utmi_drvbus_padmux = {
809 .muxmask_counts = ARRAY_SIZE(usb0_utmi_drvbus_muxmask),
810 .muxmask = usb0_utmi_drvbus_muxmask,
812 .funcval = BIT(6), /* refer to PAD_UTMI_DRVVBUS0_ENABLE */
815 static const unsigned usb0_utmi_drvbus_pins[] = { 54 };
817 static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = {
824 static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = {
825 .muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask),
826 .muxmask = usb1_utmi_drvbus_muxmask,
828 .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */
831 static const unsigned usb1_utmi_drvbus_pins[] = { 59 };
833 static const struct sirfsoc_muxmask pulse_count_muxmask[] = {
836 .mask = BIT(9) | BIT(10) | BIT(11),
840 static const struct sirfsoc_padmux pulse_count_padmux = {
841 .muxmask_counts = ARRAY_SIZE(pulse_count_muxmask),
842 .muxmask = pulse_count_muxmask,
845 static const unsigned pulse_count_pins[] = { 9, 10, 11 };
847 #define SIRFSOC_PIN_GROUP(n, p) \
851 .num_pins = ARRAY_SIZE(p), \
854 static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
855 SIRFSOC_PIN_GROUP("lcd_16bitsgrp", lcd_16bits_pins),
856 SIRFSOC_PIN_GROUP("lcd_18bitsgrp", lcd_18bits_pins),
857 SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins),
858 SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins),
859 SIRFSOC_PIN_GROUP("uart0grp", uart0_pins),
860 SIRFSOC_PIN_GROUP("uart1grp", uart1_pins),
861 SIRFSOC_PIN_GROUP("uart2grp", uart2_pins),
862 SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins),
863 SIRFSOC_PIN_GROUP("usp0grp", usp0_pins),
864 SIRFSOC_PIN_GROUP("usp1grp", usp1_pins),
865 SIRFSOC_PIN_GROUP("usp2grp", usp2_pins),
866 SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins),
867 SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins),
868 SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins),
869 SIRFSOC_PIN_GROUP("pwm1grp", pwm1_pins),
870 SIRFSOC_PIN_GROUP("pwm2grp", pwm2_pins),
871 SIRFSOC_PIN_GROUP("pwm3grp", pwm3_pins),
872 SIRFSOC_PIN_GROUP("vipgrp", vip_pins),
873 SIRFSOC_PIN_GROUP("vipromgrp", viprom_pins),
874 SIRFSOC_PIN_GROUP("warm_rstgrp", warm_rst_pins),
875 SIRFSOC_PIN_GROUP("cko0_rstgrp", cko0_pins),
876 SIRFSOC_PIN_GROUP("cko1_rstgrp", cko1_pins),
877 SIRFSOC_PIN_GROUP("sdmmc0grp", sdmmc0_pins),
878 SIRFSOC_PIN_GROUP("sdmmc1grp", sdmmc1_pins),
879 SIRFSOC_PIN_GROUP("sdmmc2grp", sdmmc2_pins),
880 SIRFSOC_PIN_GROUP("sdmmc3grp", sdmmc3_pins),
881 SIRFSOC_PIN_GROUP("sdmmc4grp", sdmmc4_pins),
882 SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins),
883 SIRFSOC_PIN_GROUP("usb0_utmi_drvbusgrp", usb0_utmi_drvbus_pins),
884 SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins),
885 SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
886 SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
887 SIRFSOC_PIN_GROUP("ac97grp", ac97_pins),
888 SIRFSOC_PIN_GROUP("nandgrp", nand_pins),
889 SIRFSOC_PIN_GROUP("spi0grp", spi0_pins),
890 SIRFSOC_PIN_GROUP("spi1grp", spi1_pins),
891 SIRFSOC_PIN_GROUP("gpsgrp", gps_pins),
894 static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev)
896 return ARRAY_SIZE(sirfsoc_pin_groups);
899 static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev,
902 return sirfsoc_pin_groups[selector].name;
905 static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
906 const unsigned **pins,
909 *pins = sirfsoc_pin_groups[selector].pins;
910 *num_pins = sirfsoc_pin_groups[selector].num_pins;
914 static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
917 seq_printf(s, " " DRIVER_NAME);
920 static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev,
921 struct device_node *np_config,
922 struct pinctrl_map **map, unsigned *num_maps)
924 struct sirfsoc_pmx *spmx = pinctrl_dev_get_drvdata(pctldev);
925 struct device_node *np;
926 struct property *prop;
927 const char *function, *group;
928 int ret, index = 0, count = 0;
930 /* calculate number of maps required */
931 for_each_child_of_node(np_config, np) {
932 ret = of_property_read_string(np, "sirf,function", &function);
936 ret = of_property_count_strings(np, "sirf,pins");
944 dev_err(spmx->dev, "No child nodes passed via DT\n");
948 *map = kzalloc(sizeof(**map) * count, GFP_KERNEL);
952 for_each_child_of_node(np_config, np) {
953 of_property_read_string(np, "sirf,function", &function);
954 of_property_for_each_string(np, "sirf,pins", prop, group) {
955 (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP;
956 (*map)[index].data.mux.group = group;
957 (*map)[index].data.mux.function = function;
967 static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev,
968 struct pinctrl_map *map, unsigned num_maps)
973 static struct pinctrl_ops sirfsoc_pctrl_ops = {
974 .get_groups_count = sirfsoc_get_groups_count,
975 .get_group_name = sirfsoc_get_group_name,
976 .get_group_pins = sirfsoc_get_group_pins,
977 .pin_dbg_show = sirfsoc_pin_dbg_show,
978 .dt_node_to_map = sirfsoc_dt_node_to_map,
979 .dt_free_map = sirfsoc_dt_free_map,
982 struct sirfsoc_pmx_func {
984 const char * const *groups;
985 const unsigned num_groups;
986 const struct sirfsoc_padmux *padmux;
989 static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" };
990 static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" };
991 static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" };
992 static const char * const lcdromgrp[] = { "lcdromgrp" };
993 static const char * const uart0grp[] = { "uart0grp" };
994 static const char * const uart1grp[] = { "uart1grp" };
995 static const char * const uart2grp[] = { "uart2grp" };
996 static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" };
997 static const char * const usp0grp[] = { "usp0grp" };
998 static const char * const usp1grp[] = { "usp1grp" };
999 static const char * const usp2grp[] = { "usp2grp" };
1000 static const char * const i2c0grp[] = { "i2c0grp" };
1001 static const char * const i2c1grp[] = { "i2c1grp" };
1002 static const char * const pwm0grp[] = { "pwm0grp" };
1003 static const char * const pwm1grp[] = { "pwm1grp" };
1004 static const char * const pwm2grp[] = { "pwm2grp" };
1005 static const char * const pwm3grp[] = { "pwm3grp" };
1006 static const char * const vipgrp[] = { "vipgrp" };
1007 static const char * const vipromgrp[] = { "vipromgrp" };
1008 static const char * const warm_rstgrp[] = { "warm_rstgrp" };
1009 static const char * const cko0grp[] = { "cko0grp" };
1010 static const char * const cko1grp[] = { "cko1grp" };
1011 static const char * const sdmmc0grp[] = { "sdmmc0grp" };
1012 static const char * const sdmmc1grp[] = { "sdmmc1grp" };
1013 static const char * const sdmmc2grp[] = { "sdmmc2grp" };
1014 static const char * const sdmmc3grp[] = { "sdmmc3grp" };
1015 static const char * const sdmmc4grp[] = { "sdmmc4grp" };
1016 static const char * const sdmmc5grp[] = { "sdmmc5grp" };
1017 static const char * const usb0_utmi_drvbusgrp[] = { "usb0_utmi_drvbusgrp" };
1018 static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
1019 static const char * const pulse_countgrp[] = { "pulse_countgrp" };
1020 static const char * const i2sgrp[] = { "i2sgrp" };
1021 static const char * const ac97grp[] = { "ac97grp" };
1022 static const char * const nandgrp[] = { "nandgrp" };
1023 static const char * const spi0grp[] = { "spi0grp" };
1024 static const char * const spi1grp[] = { "spi1grp" };
1025 static const char * const gpsgrp[] = { "gpsgrp" };
1027 #define SIRFSOC_PMX_FUNCTION(n, g, m) \
1031 .num_groups = ARRAY_SIZE(g), \
1035 static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
1036 SIRFSOC_PMX_FUNCTION("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux),
1037 SIRFSOC_PMX_FUNCTION("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux),
1038 SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux),
1039 SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux),
1040 SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux),
1041 SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux),
1042 SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
1043 SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
1044 SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
1045 SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux),
1046 SIRFSOC_PMX_FUNCTION("usp2", usp2grp, usp2_padmux),
1047 SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux),
1048 SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux),
1049 SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux),
1050 SIRFSOC_PMX_FUNCTION("pwm1", pwm1grp, pwm1_padmux),
1051 SIRFSOC_PMX_FUNCTION("pwm2", pwm2grp, pwm2_padmux),
1052 SIRFSOC_PMX_FUNCTION("pwm3", pwm3grp, pwm3_padmux),
1053 SIRFSOC_PMX_FUNCTION("vip", vipgrp, vip_padmux),
1054 SIRFSOC_PMX_FUNCTION("viprom", vipromgrp, viprom_padmux),
1055 SIRFSOC_PMX_FUNCTION("warm_rst", warm_rstgrp, warm_rst_padmux),
1056 SIRFSOC_PMX_FUNCTION("cko0", cko0grp, cko0_padmux),
1057 SIRFSOC_PMX_FUNCTION("cko1", cko1grp, cko1_padmux),
1058 SIRFSOC_PMX_FUNCTION("sdmmc0", sdmmc0grp, sdmmc0_padmux),
1059 SIRFSOC_PMX_FUNCTION("sdmmc1", sdmmc1grp, sdmmc1_padmux),
1060 SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux),
1061 SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux),
1062 SIRFSOC_PMX_FUNCTION("sdmmc4", sdmmc4grp, sdmmc4_padmux),
1063 SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux),
1064 SIRFSOC_PMX_FUNCTION("usb0_utmi_drvbus", usb0_utmi_drvbusgrp, usb0_utmi_drvbus_padmux),
1065 SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
1066 SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
1067 SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
1068 SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux),
1069 SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux),
1070 SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux),
1071 SIRFSOC_PMX_FUNCTION("spi1", spi1grp, spi1_padmux),
1072 SIRFSOC_PMX_FUNCTION("gps", gpsgrp, gps_padmux),
1075 static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, unsigned selector,
1079 const struct sirfsoc_padmux *mux = sirfsoc_pmx_functions[selector].padmux;
1080 const struct sirfsoc_muxmask *mask = mux->muxmask;
1082 for (i = 0; i < mux->muxmask_counts; i++) {
1084 muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group));
1086 muxval = muxval & ~mask[i].mask;
1088 muxval = muxval | mask[i].mask;
1089 writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group));
1092 if (mux->funcmask && enable) {
1095 readl(spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX);
1097 (func_en_val & ~mux->funcmask) | (mux->
1099 writel(func_en_val, spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX);
1103 static int sirfsoc_pinmux_enable(struct pinctrl_dev *pmxdev, unsigned selector,
1106 struct sirfsoc_pmx *spmx;
1108 spmx = pinctrl_dev_get_drvdata(pmxdev);
1109 sirfsoc_pinmux_endisable(spmx, selector, true);
1114 static void sirfsoc_pinmux_disable(struct pinctrl_dev *pmxdev, unsigned selector,
1117 struct sirfsoc_pmx *spmx;
1119 spmx = pinctrl_dev_get_drvdata(pmxdev);
1120 sirfsoc_pinmux_endisable(spmx, selector, false);
1123 static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev)
1125 return ARRAY_SIZE(sirfsoc_pmx_functions);
1128 static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev,
1131 return sirfsoc_pmx_functions[selector].name;
1134 static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
1135 const char * const **groups,
1136 unsigned * const num_groups)
1138 *groups = sirfsoc_pmx_functions[selector].groups;
1139 *num_groups = sirfsoc_pmx_functions[selector].num_groups;
1143 static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
1144 struct pinctrl_gpio_range *range, unsigned offset)
1146 struct sirfsoc_pmx *spmx;
1148 int group = range->id;
1152 spmx = pinctrl_dev_get_drvdata(pmxdev);
1154 muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group));
1155 muxval = muxval | (1 << (offset - range->pin_base));
1156 writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group));
1161 static struct pinmux_ops sirfsoc_pinmux_ops = {
1162 .enable = sirfsoc_pinmux_enable,
1163 .disable = sirfsoc_pinmux_disable,
1164 .get_functions_count = sirfsoc_pinmux_get_funcs_count,
1165 .get_function_name = sirfsoc_pinmux_get_func_name,
1166 .get_function_groups = sirfsoc_pinmux_get_groups,
1167 .gpio_request_enable = sirfsoc_pinmux_request_gpio,
1170 static struct pinctrl_desc sirfsoc_pinmux_desc = {
1171 .name = DRIVER_NAME,
1172 .pins = sirfsoc_pads,
1173 .npins = ARRAY_SIZE(sirfsoc_pads),
1174 .pctlops = &sirfsoc_pctrl_ops,
1175 .pmxops = &sirfsoc_pinmux_ops,
1176 .owner = THIS_MODULE,
1180 * Todo: bind irq_chip to every pinctrl_gpio_range
1182 static struct pinctrl_gpio_range sirfsoc_gpio_ranges[] = {
1184 .name = "sirfsoc-gpio*",
1190 .name = "sirfsoc-gpio*",
1196 .name = "sirfsoc-gpio*",
1202 .name = "sirfsoc-gpio*",
1210 static void __iomem *sirfsoc_rsc_of_iomap(void)
1212 const struct of_device_id rsc_ids[] = {
1213 { .compatible = "sirf,prima2-rsc" },
1216 struct device_node *np;
1218 np = of_find_matching_node(NULL, rsc_ids);
1220 panic("unable to find compatible rsc node in dtb\n");
1222 return of_iomap(np, 0);
1225 static int __devinit sirfsoc_pinmux_probe(struct platform_device *pdev)
1228 struct sirfsoc_pmx *spmx;
1229 struct device_node *np = pdev->dev.of_node;
1232 /* Create state holders etc for this driver */
1233 spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL);
1237 spmx->dev = &pdev->dev;
1239 platform_set_drvdata(pdev, spmx);
1241 spmx->gpio_virtbase = of_iomap(np, 0);
1242 if (!spmx->gpio_virtbase) {
1244 dev_err(&pdev->dev, "can't map gpio registers\n");
1245 goto out_no_gpio_remap;
1248 spmx->rsc_virtbase = sirfsoc_rsc_of_iomap();
1249 if (!spmx->rsc_virtbase) {
1251 dev_err(&pdev->dev, "can't map rsc registers\n");
1252 goto out_no_rsc_remap;
1255 /* Now register the pin controller and all pins it handles */
1256 spmx->pmx = pinctrl_register(&sirfsoc_pinmux_desc, &pdev->dev, spmx);
1258 dev_err(&pdev->dev, "could not register SIRFSOC pinmux driver\n");
1263 for (i = 0; i < ARRAY_SIZE(sirfsoc_gpio_ranges); i++)
1264 pinctrl_add_gpio_range(spmx->pmx, &sirfsoc_gpio_ranges[i]);
1266 dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n");
1271 iounmap(spmx->rsc_virtbase);
1273 iounmap(spmx->gpio_virtbase);
1275 platform_set_drvdata(pdev, NULL);
1279 static const struct of_device_id pinmux_ids[] __devinitconst = {
1280 { .compatible = "sirf,prima2-pinctrl" },
1284 static struct platform_driver sirfsoc_pinmux_driver = {
1286 .name = DRIVER_NAME,
1287 .owner = THIS_MODULE,
1288 .of_match_table = pinmux_ids,
1290 .probe = sirfsoc_pinmux_probe,
1293 static int __init sirfsoc_pinmux_init(void)
1295 return platform_driver_register(&sirfsoc_pinmux_driver);
1297 arch_initcall(sirfsoc_pinmux_init);
1299 static inline int sirfsoc_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
1301 struct sirfsoc_gpio_bank *bank = container_of(to_of_mm_gpio_chip(chip),
1302 struct sirfsoc_gpio_bank, chip);
1304 return irq_find_mapping(bank->domain, offset);
1307 static inline int sirfsoc_gpio_to_offset(unsigned int gpio)
1309 return gpio % SIRFSOC_GPIO_BANK_SIZE;
1312 static inline struct sirfsoc_gpio_bank *sirfsoc_gpio_to_bank(unsigned int gpio)
1314 return &sgpio_bank[gpio / SIRFSOC_GPIO_BANK_SIZE];
1317 void sirfsoc_gpio_set_pull(unsigned gpio, unsigned mode)
1319 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(gpio);
1320 int idx = sirfsoc_gpio_to_offset(gpio);
1322 unsigned long flags;
1324 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1326 spin_lock_irqsave(&sgpio_lock, flags);
1328 val = readl(bank->chip.regs + offset);
1331 case SIRFSOC_GPIO_PULL_NONE:
1332 val &= ~SIRFSOC_GPIO_CTL_PULL_MASK;
1334 case SIRFSOC_GPIO_PULL_UP:
1335 val |= SIRFSOC_GPIO_CTL_PULL_MASK;
1336 val |= SIRFSOC_GPIO_CTL_PULL_HIGH;
1338 case SIRFSOC_GPIO_PULL_DOWN:
1339 val |= SIRFSOC_GPIO_CTL_PULL_MASK;
1340 val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH;
1346 writel(val, bank->chip.regs + offset);
1348 spin_unlock_irqrestore(&sgpio_lock, flags);
1350 EXPORT_SYMBOL(sirfsoc_gpio_set_pull);
1352 static inline struct sirfsoc_gpio_bank *sirfsoc_irqchip_to_bank(struct gpio_chip *chip)
1354 return container_of(to_of_mm_gpio_chip(chip), struct sirfsoc_gpio_bank, chip);
1357 static void sirfsoc_gpio_irq_ack(struct irq_data *d)
1359 struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
1360 int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
1362 unsigned long flags;
1364 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1366 spin_lock_irqsave(&sgpio_lock, flags);
1368 val = readl(bank->chip.regs + offset);
1370 writel(val, bank->chip.regs + offset);
1372 spin_unlock_irqrestore(&sgpio_lock, flags);
1375 static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_bank *bank, int idx)
1378 unsigned long flags;
1380 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1382 spin_lock_irqsave(&sgpio_lock, flags);
1384 val = readl(bank->chip.regs + offset);
1385 val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
1386 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
1387 writel(val, bank->chip.regs + offset);
1389 spin_unlock_irqrestore(&sgpio_lock, flags);
1392 static void sirfsoc_gpio_irq_mask(struct irq_data *d)
1394 struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
1396 __sirfsoc_gpio_irq_mask(bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE);
1399 static void sirfsoc_gpio_irq_unmask(struct irq_data *d)
1401 struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
1402 int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
1404 unsigned long flags;
1406 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1408 spin_lock_irqsave(&sgpio_lock, flags);
1410 val = readl(bank->chip.regs + offset);
1411 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
1412 val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK;
1413 writel(val, bank->chip.regs + offset);
1415 spin_unlock_irqrestore(&sgpio_lock, flags);
1418 static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
1420 struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
1421 int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
1423 unsigned long flags;
1425 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1427 spin_lock_irqsave(&sgpio_lock, flags);
1429 val = readl(bank->chip.regs + offset);
1430 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
1435 case IRQ_TYPE_EDGE_RISING:
1436 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
1437 val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
1439 case IRQ_TYPE_EDGE_FALLING:
1440 val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
1441 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
1443 case IRQ_TYPE_EDGE_BOTH:
1444 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
1445 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
1447 case IRQ_TYPE_LEVEL_LOW:
1448 val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
1449 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
1451 case IRQ_TYPE_LEVEL_HIGH:
1452 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
1453 val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
1457 writel(val, bank->chip.regs + offset);
1459 spin_unlock_irqrestore(&sgpio_lock, flags);
1464 static struct irq_chip sirfsoc_irq_chip = {
1465 .name = "sirf-gpio-irq",
1466 .irq_ack = sirfsoc_gpio_irq_ack,
1467 .irq_mask = sirfsoc_gpio_irq_mask,
1468 .irq_unmask = sirfsoc_gpio_irq_unmask,
1469 .irq_set_type = sirfsoc_gpio_irq_type,
1472 static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
1474 struct sirfsoc_gpio_bank *bank = irq_get_handler_data(irq);
1477 unsigned int first_irq;
1479 status = readl(bank->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id));
1482 "%s: gpio id %d status %#x no interrupt is flaged\n",
1483 __func__, bank->id, status);
1484 handle_bad_irq(irq, desc);
1488 first_irq = bank->domain->revmap_data.legacy.first_irq;
1491 ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx));
1494 * Here we must check whether the corresponding GPIO's interrupt
1495 * has been enabled, otherwise just skip it
1497 if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) {
1498 pr_debug("%s: gpio id %d idx %d happens\n",
1499 __func__, bank->id, idx);
1500 generic_handle_irq(first_irq + idx);
1504 status = status >> 1;
1508 static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_bank *bank, unsigned ctrl_offset)
1511 unsigned long flags;
1513 spin_lock_irqsave(&bank->lock, flags);
1515 val = readl(bank->chip.regs + ctrl_offset);
1516 val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK;
1517 writel(val, bank->chip.regs + ctrl_offset);
1519 spin_unlock_irqrestore(&bank->lock, flags);
1522 static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset)
1524 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1525 unsigned long flags;
1527 if (pinctrl_request_gpio(chip->base + offset))
1530 spin_lock_irqsave(&bank->lock, flags);
1534 * set direction as input and mask irq
1536 sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset));
1537 __sirfsoc_gpio_irq_mask(bank, offset);
1539 spin_unlock_irqrestore(&bank->lock, flags);
1544 static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset)
1546 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1547 unsigned long flags;
1549 spin_lock_irqsave(&bank->lock, flags);
1551 __sirfsoc_gpio_irq_mask(bank, offset);
1552 sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset));
1554 spin_unlock_irqrestore(&bank->lock, flags);
1556 pinctrl_free_gpio(chip->base + offset);
1559 static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
1561 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1562 int idx = sirfsoc_gpio_to_offset(gpio);
1563 unsigned long flags;
1566 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1568 spin_lock_irqsave(&bank->lock, flags);
1570 sirfsoc_gpio_set_input(bank, offset);
1572 spin_unlock_irqrestore(&bank->lock, flags);
1577 static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_bank *bank, unsigned offset,
1581 unsigned long flags;
1583 spin_lock_irqsave(&bank->lock, flags);
1585 out_ctrl = readl(bank->chip.regs + offset);
1587 out_ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
1589 out_ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
1591 out_ctrl &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
1592 out_ctrl |= SIRFSOC_GPIO_CTL_OUT_EN_MASK;
1593 writel(out_ctrl, bank->chip.regs + offset);
1595 spin_unlock_irqrestore(&bank->lock, flags);
1598 static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
1600 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1601 int idx = sirfsoc_gpio_to_offset(gpio);
1603 unsigned long flags;
1605 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1607 spin_lock_irqsave(&sgpio_lock, flags);
1609 sirfsoc_gpio_set_output(bank, offset, value);
1611 spin_unlock_irqrestore(&sgpio_lock, flags);
1616 static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset)
1618 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1620 unsigned long flags;
1622 spin_lock_irqsave(&bank->lock, flags);
1624 val = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
1626 spin_unlock_irqrestore(&bank->lock, flags);
1628 return !!(val & SIRFSOC_GPIO_CTL_DATAIN_MASK);
1631 static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset,
1634 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1636 unsigned long flags;
1638 spin_lock_irqsave(&bank->lock, flags);
1640 ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
1642 ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
1644 ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
1645 writel(ctrl, bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
1647 spin_unlock_irqrestore(&bank->lock, flags);
1650 int sirfsoc_gpio_irq_map(struct irq_domain *d, unsigned int irq,
1651 irq_hw_number_t hwirq)
1653 struct sirfsoc_gpio_bank *bank = d->host_data;
1658 irq_set_chip(irq, &sirfsoc_irq_chip);
1659 irq_set_handler(irq, handle_level_irq);
1660 irq_set_chip_data(irq, bank);
1661 set_irq_flags(irq, IRQF_VALID);
1666 const struct irq_domain_ops sirfsoc_gpio_irq_simple_ops = {
1667 .map = sirfsoc_gpio_irq_map,
1668 .xlate = irq_domain_xlate_twocell,
1671 static int __devinit sirfsoc_gpio_probe(struct device_node *np)
1674 struct sirfsoc_gpio_bank *bank;
1676 struct platform_device *pdev;
1678 pdev = of_find_device_by_node(np);
1682 regs = of_iomap(np, 0);
1686 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
1687 bank = &sgpio_bank[i];
1688 spin_lock_init(&bank->lock);
1689 bank->chip.gc.request = sirfsoc_gpio_request;
1690 bank->chip.gc.free = sirfsoc_gpio_free;
1691 bank->chip.gc.direction_input = sirfsoc_gpio_direction_input;
1692 bank->chip.gc.get = sirfsoc_gpio_get_value;
1693 bank->chip.gc.direction_output = sirfsoc_gpio_direction_output;
1694 bank->chip.gc.set = sirfsoc_gpio_set_value;
1695 bank->chip.gc.to_irq = sirfsoc_gpio_to_irq;
1696 bank->chip.gc.base = i * SIRFSOC_GPIO_BANK_SIZE;
1697 bank->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE;
1698 bank->chip.gc.label = kstrdup(np->full_name, GFP_KERNEL);
1699 bank->chip.gc.of_node = np;
1700 bank->chip.regs = regs;
1702 bank->parent_irq = platform_get_irq(pdev, i);
1703 if (bank->parent_irq < 0) {
1704 err = bank->parent_irq;
1708 err = gpiochip_add(&bank->chip.gc);
1710 pr_err("%s: error in probe function with status %d\n",
1711 np->full_name, err);
1715 bank->domain = irq_domain_add_legacy(np, SIRFSOC_GPIO_BANK_SIZE,
1716 SIRFSOC_GPIO_IRQ_START + i * SIRFSOC_GPIO_BANK_SIZE, 0,
1717 &sirfsoc_gpio_irq_simple_ops, bank);
1719 if (!bank->domain) {
1720 pr_err("%s: Failed to create irqdomain\n", np->full_name);
1725 irq_set_chained_handler(bank->parent_irq, sirfsoc_gpio_handle_irq);
1726 irq_set_handler_data(bank->parent_irq, bank);
1734 static int __init sirfsoc_gpio_init(void)
1737 struct device_node *np;
1739 np = of_find_matching_node(NULL, pinmux_ids);
1744 return sirfsoc_gpio_probe(np);
1746 subsys_initcall(sirfsoc_gpio_init);
1748 MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>, "
1749 "Yuping Luo <yuping.luo@csr.com>, "
1750 "Barry Song <baohua.song@csr.com>");
1751 MODULE_DESCRIPTION("SIRFSOC pin control driver");
1752 MODULE_LICENSE("GPL");