2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/slab.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/string.h>
19 #include <linux/log2.h>
20 #include <linux/pci-aspm.h>
21 #include <linux/pm_wakeup.h>
22 #include <linux/interrupt.h>
23 #include <linux/device.h>
24 #include <linux/pm_runtime.h>
25 #include <asm/setup.h>
28 const char *pci_power_names[] = {
29 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
31 EXPORT_SYMBOL_GPL(pci_power_names);
33 int isa_dma_bridge_buggy;
34 EXPORT_SYMBOL(isa_dma_bridge_buggy);
37 EXPORT_SYMBOL(pci_pci_problems);
39 unsigned int pci_pm_d3_delay;
41 static void pci_pme_list_scan(struct work_struct *work);
43 static LIST_HEAD(pci_pme_list);
44 static DEFINE_MUTEX(pci_pme_list_mutex);
45 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
47 struct pci_pme_device {
48 struct list_head list;
52 #define PME_TIMEOUT 1000 /* How long between PME checks */
54 static void pci_dev_d3_sleep(struct pci_dev *dev)
56 unsigned int delay = dev->d3_delay;
58 if (delay < pci_pm_d3_delay)
59 delay = pci_pm_d3_delay;
64 #ifdef CONFIG_PCI_DOMAINS
65 int pci_domains_supported = 1;
68 #define DEFAULT_CARDBUS_IO_SIZE (256)
69 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
70 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
71 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
72 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
74 #define DEFAULT_HOTPLUG_IO_SIZE (256)
75 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
76 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
77 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
78 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
81 * The default CLS is used if arch didn't set CLS explicitly and not
82 * all pci devices agree on the same value. Arch can override either
83 * the dfl or actual value as it sees fit. Don't forget this is
84 * measured in 32-bit words, not bytes.
86 u8 pci_dfl_cache_line_size __devinitdata = L1_CACHE_BYTES >> 2;
87 u8 pci_cache_line_size;
90 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
91 * @bus: pointer to PCI bus structure to search
93 * Given a PCI bus, returns the highest PCI bus number present in the set
94 * including the given PCI bus and its list of child PCI buses.
96 unsigned char pci_bus_max_busnr(struct pci_bus* bus)
98 struct list_head *tmp;
101 max = bus->subordinate;
102 list_for_each(tmp, &bus->children) {
103 n = pci_bus_max_busnr(pci_bus_b(tmp));
109 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
111 #ifdef CONFIG_HAS_IOMEM
112 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
115 * Make sure the BAR is actually a memory resource, not an IO resource
117 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
121 return ioremap_nocache(pci_resource_start(pdev, bar),
122 pci_resource_len(pdev, bar));
124 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
129 * pci_max_busnr - returns maximum PCI bus number
131 * Returns the highest PCI bus number present in the system global list of
134 unsigned char __devinit
137 struct pci_bus *bus = NULL;
138 unsigned char max, n;
141 while ((bus = pci_find_next_bus(bus)) != NULL) {
142 n = pci_bus_max_busnr(bus);
151 #define PCI_FIND_CAP_TTL 48
153 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
154 u8 pos, int cap, int *ttl)
159 pci_bus_read_config_byte(bus, devfn, pos, &pos);
163 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
169 pos += PCI_CAP_LIST_NEXT;
174 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
177 int ttl = PCI_FIND_CAP_TTL;
179 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
182 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
184 return __pci_find_next_cap(dev->bus, dev->devfn,
185 pos + PCI_CAP_LIST_NEXT, cap);
187 EXPORT_SYMBOL_GPL(pci_find_next_capability);
189 static int __pci_bus_find_cap_start(struct pci_bus *bus,
190 unsigned int devfn, u8 hdr_type)
194 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
195 if (!(status & PCI_STATUS_CAP_LIST))
199 case PCI_HEADER_TYPE_NORMAL:
200 case PCI_HEADER_TYPE_BRIDGE:
201 return PCI_CAPABILITY_LIST;
202 case PCI_HEADER_TYPE_CARDBUS:
203 return PCI_CB_CAPABILITY_LIST;
212 * pci_find_capability - query for devices' capabilities
213 * @dev: PCI device to query
214 * @cap: capability code
216 * Tell if a device supports a given PCI capability.
217 * Returns the address of the requested capability structure within the
218 * device's PCI configuration space or 0 in case the device does not
219 * support it. Possible values for @cap:
221 * %PCI_CAP_ID_PM Power Management
222 * %PCI_CAP_ID_AGP Accelerated Graphics Port
223 * %PCI_CAP_ID_VPD Vital Product Data
224 * %PCI_CAP_ID_SLOTID Slot Identification
225 * %PCI_CAP_ID_MSI Message Signalled Interrupts
226 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
227 * %PCI_CAP_ID_PCIX PCI-X
228 * %PCI_CAP_ID_EXP PCI Express
230 int pci_find_capability(struct pci_dev *dev, int cap)
234 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
236 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
242 * pci_bus_find_capability - query for devices' capabilities
243 * @bus: the PCI bus to query
244 * @devfn: PCI device to query
245 * @cap: capability code
247 * Like pci_find_capability() but works for pci devices that do not have a
248 * pci_dev structure set up yet.
250 * Returns the address of the requested capability structure within the
251 * device's PCI configuration space or 0 in case the device does not
254 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
259 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
261 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
263 pos = __pci_find_next_cap(bus, devfn, pos, cap);
269 * pci_find_ext_capability - Find an extended capability
270 * @dev: PCI device to query
271 * @cap: capability code
273 * Returns the address of the requested extended capability structure
274 * within the device's PCI configuration space or 0 if the device does
275 * not support it. Possible values for @cap:
277 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
278 * %PCI_EXT_CAP_ID_VC Virtual Channel
279 * %PCI_EXT_CAP_ID_DSN Device Serial Number
280 * %PCI_EXT_CAP_ID_PWR Power Budgeting
282 int pci_find_ext_capability(struct pci_dev *dev, int cap)
286 int pos = PCI_CFG_SPACE_SIZE;
288 /* minimum 8 bytes per capability */
289 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
291 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
294 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
298 * If we have no capabilities, this is indicated by cap ID,
299 * cap version and next pointer all being 0.
305 if (PCI_EXT_CAP_ID(header) == cap)
308 pos = PCI_EXT_CAP_NEXT(header);
309 if (pos < PCI_CFG_SPACE_SIZE)
312 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
318 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
321 * pci_bus_find_ext_capability - find an extended capability
322 * @bus: the PCI bus to query
323 * @devfn: PCI device to query
324 * @cap: capability code
326 * Like pci_find_ext_capability() but works for pci devices that do not have a
327 * pci_dev structure set up yet.
329 * Returns the address of the requested capability structure within the
330 * device's PCI configuration space or 0 in case the device does not
333 int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
338 int pos = PCI_CFG_SPACE_SIZE;
340 /* minimum 8 bytes per capability */
341 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
343 if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
345 if (header == 0xffffffff || header == 0)
349 if (PCI_EXT_CAP_ID(header) == cap)
352 pos = PCI_EXT_CAP_NEXT(header);
353 if (pos < PCI_CFG_SPACE_SIZE)
356 if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
363 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
365 int rc, ttl = PCI_FIND_CAP_TTL;
368 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
369 mask = HT_3BIT_CAP_MASK;
371 mask = HT_5BIT_CAP_MASK;
373 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
374 PCI_CAP_ID_HT, &ttl);
376 rc = pci_read_config_byte(dev, pos + 3, &cap);
377 if (rc != PCIBIOS_SUCCESSFUL)
380 if ((cap & mask) == ht_cap)
383 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
384 pos + PCI_CAP_LIST_NEXT,
385 PCI_CAP_ID_HT, &ttl);
391 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
392 * @dev: PCI device to query
393 * @pos: Position from which to continue searching
394 * @ht_cap: Hypertransport capability code
396 * To be used in conjunction with pci_find_ht_capability() to search for
397 * all capabilities matching @ht_cap. @pos should always be a value returned
398 * from pci_find_ht_capability().
400 * NB. To be 100% safe against broken PCI devices, the caller should take
401 * steps to avoid an infinite loop.
403 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
405 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
407 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
410 * pci_find_ht_capability - query a device's Hypertransport capabilities
411 * @dev: PCI device to query
412 * @ht_cap: Hypertransport capability code
414 * Tell if a device supports a given Hypertransport capability.
415 * Returns an address within the device's PCI configuration space
416 * or 0 in case the device does not support the request capability.
417 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
418 * which has a Hypertransport capability matching @ht_cap.
420 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
424 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
426 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
430 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
433 * pci_find_parent_resource - return resource region of parent bus of given region
434 * @dev: PCI device structure contains resources to be searched
435 * @res: child resource record for which parent is sought
437 * For given resource region of given device, return the resource
438 * region of parent bus the given region is contained in or where
439 * it should be allocated from.
442 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
444 const struct pci_bus *bus = dev->bus;
446 struct resource *best = NULL, *r;
448 pci_bus_for_each_resource(bus, r, i) {
451 if (res->start && !(res->start >= r->start && res->end <= r->end))
452 continue; /* Not contained */
453 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
454 continue; /* Wrong type */
455 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
456 return r; /* Exact match */
457 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
458 if (r->flags & IORESOURCE_PREFETCH)
460 /* .. but we can put a prefetchable resource inside a non-prefetchable one */
468 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
469 * @dev: PCI device to have its BARs restored
471 * Restore the BAR values for a given device, so as to make it
472 * accessible by its driver.
475 pci_restore_bars(struct pci_dev *dev)
479 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
480 pci_update_resource(dev, i);
483 static struct pci_platform_pm_ops *pci_platform_pm;
485 int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
487 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
488 || !ops->sleep_wake || !ops->can_wakeup)
490 pci_platform_pm = ops;
494 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
496 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
499 static inline int platform_pci_set_power_state(struct pci_dev *dev,
502 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
505 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
507 return pci_platform_pm ?
508 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
511 static inline bool platform_pci_can_wakeup(struct pci_dev *dev)
513 return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false;
516 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
518 return pci_platform_pm ?
519 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
522 static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
524 return pci_platform_pm ?
525 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
529 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
531 * @dev: PCI device to handle.
532 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
535 * -EINVAL if the requested state is invalid.
536 * -EIO if device does not support PCI PM or its PM capabilities register has a
537 * wrong version, or device doesn't support the requested state.
538 * 0 if device already is in the requested state.
539 * 0 if device's power state has been successfully changed.
541 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
544 bool need_restore = false;
546 /* Check if we're already there */
547 if (dev->current_state == state)
553 if (state < PCI_D0 || state > PCI_D3hot)
556 /* Validate current state:
557 * Can enter D0 from any state, but if we can only go deeper
558 * to sleep if we're already in a low power state
560 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
561 && dev->current_state > state) {
562 dev_err(&dev->dev, "invalid power transition "
563 "(from state %d to %d)\n", dev->current_state, state);
567 /* check if this device supports the desired state */
568 if ((state == PCI_D1 && !dev->d1_support)
569 || (state == PCI_D2 && !dev->d2_support))
572 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
574 /* If we're (effectively) in D3, force entire word to 0.
575 * This doesn't affect PME_Status, disables PME_En, and
576 * sets PowerState to 0.
578 switch (dev->current_state) {
582 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
587 case PCI_UNKNOWN: /* Boot-up */
588 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
589 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
591 /* Fall-through: force to D0 */
597 /* enter specified state */
598 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
600 /* Mandatory power management transition delays */
601 /* see PCI PM 1.1 5.6.1 table 18 */
602 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
603 pci_dev_d3_sleep(dev);
604 else if (state == PCI_D2 || dev->current_state == PCI_D2)
605 udelay(PCI_PM_D2_DELAY);
607 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
608 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
609 if (dev->current_state != state && printk_ratelimit())
610 dev_info(&dev->dev, "Refused to change power state, "
611 "currently in D%d\n", dev->current_state);
613 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
614 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
615 * from D3hot to D0 _may_ perform an internal reset, thereby
616 * going to "D0 Uninitialized" rather than "D0 Initialized".
617 * For example, at least some versions of the 3c905B and the
618 * 3c556B exhibit this behaviour.
620 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
621 * devices in a D3hot state at boot. Consequently, we need to
622 * restore at least the BARs so that the device will be
623 * accessible to its driver.
626 pci_restore_bars(dev);
629 pcie_aspm_pm_state_change(dev->bus->self);
635 * pci_update_current_state - Read PCI power state of given device from its
636 * PCI PM registers and cache it
637 * @dev: PCI device to handle.
638 * @state: State to cache in case the device doesn't have the PM capability
640 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
645 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
646 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
648 dev->current_state = state;
653 * pci_platform_power_transition - Use platform to change device power state
654 * @dev: PCI device to handle.
655 * @state: State to put the device into.
657 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
661 if (platform_pci_power_manageable(dev)) {
662 error = platform_pci_set_power_state(dev, state);
664 pci_update_current_state(dev, state);
667 /* Fall back to PCI_D0 if native PM is not supported */
669 dev->current_state = PCI_D0;
676 * __pci_start_power_transition - Start power transition of a PCI device
677 * @dev: PCI device to handle.
678 * @state: State to put the device into.
680 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
683 pci_platform_power_transition(dev, PCI_D0);
687 * __pci_complete_power_transition - Complete power transition of a PCI device
688 * @dev: PCI device to handle.
689 * @state: State to put the device into.
691 * This function should not be called directly by device drivers.
693 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
695 return state >= PCI_D0 ?
696 pci_platform_power_transition(dev, state) : -EINVAL;
698 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
701 * pci_set_power_state - Set the power state of a PCI device
702 * @dev: PCI device to handle.
703 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
705 * Transition a device to a new power state, using the platform firmware and/or
706 * the device's PCI PM registers.
709 * -EINVAL if the requested state is invalid.
710 * -EIO if device does not support PCI PM or its PM capabilities register has a
711 * wrong version, or device doesn't support the requested state.
712 * 0 if device already is in the requested state.
713 * 0 if device's power state has been successfully changed.
715 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
719 /* bound the state we're entering */
720 if (state > PCI_D3hot)
722 else if (state < PCI_D0)
724 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
726 * If the device or the parent bridge do not support PCI PM,
727 * ignore the request if we're doing anything other than putting
728 * it into D0 (which would only happen on boot).
732 __pci_start_power_transition(dev, state);
734 /* This device is quirked not to be put into D3, so
735 don't put it in D3 */
736 if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
739 error = pci_raw_set_power_state(dev, state);
741 if (!__pci_complete_power_transition(dev, state))
748 * pci_choose_state - Choose the power state of a PCI device
749 * @dev: PCI device to be suspended
750 * @state: target sleep state for the whole system. This is the value
751 * that is passed to suspend() function.
753 * Returns PCI power state suitable for given device and given system
757 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
761 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
764 ret = platform_pci_choose_state(dev);
765 if (ret != PCI_POWER_ERROR)
768 switch (state.event) {
771 case PM_EVENT_FREEZE:
772 case PM_EVENT_PRETHAW:
773 /* REVISIT both freeze and pre-thaw "should" use D0 */
774 case PM_EVENT_SUSPEND:
775 case PM_EVENT_HIBERNATE:
778 dev_info(&dev->dev, "unrecognized suspend event %d\n",
785 EXPORT_SYMBOL(pci_choose_state);
787 #define PCI_EXP_SAVE_REGS 7
789 #define pcie_cap_has_devctl(type, flags) 1
790 #define pcie_cap_has_lnkctl(type, flags) \
791 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
792 (type == PCI_EXP_TYPE_ROOT_PORT || \
793 type == PCI_EXP_TYPE_ENDPOINT || \
794 type == PCI_EXP_TYPE_LEG_END))
795 #define pcie_cap_has_sltctl(type, flags) \
796 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
797 ((type == PCI_EXP_TYPE_ROOT_PORT) || \
798 (type == PCI_EXP_TYPE_DOWNSTREAM && \
799 (flags & PCI_EXP_FLAGS_SLOT))))
800 #define pcie_cap_has_rtctl(type, flags) \
801 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
802 (type == PCI_EXP_TYPE_ROOT_PORT || \
803 type == PCI_EXP_TYPE_RC_EC))
804 #define pcie_cap_has_devctl2(type, flags) \
805 ((flags & PCI_EXP_FLAGS_VERS) > 1)
806 #define pcie_cap_has_lnkctl2(type, flags) \
807 ((flags & PCI_EXP_FLAGS_VERS) > 1)
808 #define pcie_cap_has_sltctl2(type, flags) \
809 ((flags & PCI_EXP_FLAGS_VERS) > 1)
811 static int pci_save_pcie_state(struct pci_dev *dev)
814 struct pci_cap_saved_state *save_state;
818 pos = pci_pcie_cap(dev);
822 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
824 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
827 cap = (u16 *)&save_state->data[0];
829 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
831 if (pcie_cap_has_devctl(dev->pcie_type, flags))
832 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
833 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
834 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
835 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
836 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
837 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
838 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
839 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
840 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
841 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
842 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
843 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
844 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
849 static void pci_restore_pcie_state(struct pci_dev *dev)
852 struct pci_cap_saved_state *save_state;
856 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
857 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
858 if (!save_state || pos <= 0)
860 cap = (u16 *)&save_state->data[0];
862 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
864 if (pcie_cap_has_devctl(dev->pcie_type, flags))
865 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
866 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
867 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
868 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
869 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
870 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
871 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
872 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
873 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
874 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
875 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
876 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
877 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
881 static int pci_save_pcix_state(struct pci_dev *dev)
884 struct pci_cap_saved_state *save_state;
886 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
890 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
892 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
896 pci_read_config_word(dev, pos + PCI_X_CMD, (u16 *)save_state->data);
901 static void pci_restore_pcix_state(struct pci_dev *dev)
904 struct pci_cap_saved_state *save_state;
907 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
908 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
909 if (!save_state || pos <= 0)
911 cap = (u16 *)&save_state->data[0];
913 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
918 * pci_save_state - save the PCI configuration space of a device before suspending
919 * @dev: - PCI device that we're dealing with
922 pci_save_state(struct pci_dev *dev)
925 /* XXX: 100% dword access ok here? */
926 for (i = 0; i < 16; i++)
927 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
928 dev->state_saved = true;
929 if ((i = pci_save_pcie_state(dev)) != 0)
931 if ((i = pci_save_pcix_state(dev)) != 0)
937 * pci_restore_state - Restore the saved state of a PCI device
938 * @dev: - PCI device that we're dealing with
940 void pci_restore_state(struct pci_dev *dev)
945 if (!dev->state_saved)
948 /* PCI Express register must be restored first */
949 pci_restore_pcie_state(dev);
952 * The Base Address register should be programmed before the command
955 for (i = 15; i >= 0; i--) {
956 pci_read_config_dword(dev, i * 4, &val);
957 if (val != dev->saved_config_space[i]) {
958 dev_printk(KERN_DEBUG, &dev->dev, "restoring config "
959 "space at offset %#x (was %#x, writing %#x)\n",
960 i, val, (int)dev->saved_config_space[i]);
961 pci_write_config_dword(dev,i * 4,
962 dev->saved_config_space[i]);
965 pci_restore_pcix_state(dev);
966 pci_restore_msi_state(dev);
967 pci_restore_iov_state(dev);
969 dev->state_saved = false;
972 static int do_pci_enable_device(struct pci_dev *dev, int bars)
976 err = pci_set_power_state(dev, PCI_D0);
977 if (err < 0 && err != -EIO)
979 err = pcibios_enable_device(dev, bars);
982 pci_fixup_device(pci_fixup_enable, dev);
988 * pci_reenable_device - Resume abandoned device
989 * @dev: PCI device to be resumed
991 * Note this function is a backend of pci_default_resume and is not supposed
992 * to be called by normal code, write proper resume handler and use it instead.
994 int pci_reenable_device(struct pci_dev *dev)
996 if (pci_is_enabled(dev))
997 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1001 static int __pci_enable_device_flags(struct pci_dev *dev,
1002 resource_size_t flags)
1008 * Power state could be unknown at this point, either due to a fresh
1009 * boot or a device removal call. So get the current power state
1010 * so that things like MSI message writing will behave as expected
1011 * (e.g. if the device really is in D0 at enable time).
1015 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1016 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1019 if (atomic_add_return(1, &dev->enable_cnt) > 1)
1020 return 0; /* already enabled */
1022 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1023 if (dev->resource[i].flags & flags)
1026 err = do_pci_enable_device(dev, bars);
1028 atomic_dec(&dev->enable_cnt);
1033 * pci_enable_device_io - Initialize a device for use with IO space
1034 * @dev: PCI device to be initialized
1036 * Initialize device before it's used by a driver. Ask low-level code
1037 * to enable I/O resources. Wake up the device if it was suspended.
1038 * Beware, this function can fail.
1040 int pci_enable_device_io(struct pci_dev *dev)
1042 return __pci_enable_device_flags(dev, IORESOURCE_IO);
1046 * pci_enable_device_mem - Initialize a device for use with Memory space
1047 * @dev: PCI device to be initialized
1049 * Initialize device before it's used by a driver. Ask low-level code
1050 * to enable Memory resources. Wake up the device if it was suspended.
1051 * Beware, this function can fail.
1053 int pci_enable_device_mem(struct pci_dev *dev)
1055 return __pci_enable_device_flags(dev, IORESOURCE_MEM);
1059 * pci_enable_device - Initialize device before it's used by a driver.
1060 * @dev: PCI device to be initialized
1062 * Initialize device before it's used by a driver. Ask low-level code
1063 * to enable I/O and memory. Wake up the device if it was suspended.
1064 * Beware, this function can fail.
1066 * Note we don't actually enable the device many times if we call
1067 * this function repeatedly (we just increment the count).
1069 int pci_enable_device(struct pci_dev *dev)
1071 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1075 * Managed PCI resources. This manages device on/off, intx/msi/msix
1076 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1077 * there's no need to track it separately. pci_devres is initialized
1078 * when a device is enabled using managed PCI device enable interface.
1081 unsigned int enabled:1;
1082 unsigned int pinned:1;
1083 unsigned int orig_intx:1;
1084 unsigned int restore_intx:1;
1088 static void pcim_release(struct device *gendev, void *res)
1090 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1091 struct pci_devres *this = res;
1094 if (dev->msi_enabled)
1095 pci_disable_msi(dev);
1096 if (dev->msix_enabled)
1097 pci_disable_msix(dev);
1099 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1100 if (this->region_mask & (1 << i))
1101 pci_release_region(dev, i);
1103 if (this->restore_intx)
1104 pci_intx(dev, this->orig_intx);
1106 if (this->enabled && !this->pinned)
1107 pci_disable_device(dev);
1110 static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
1112 struct pci_devres *dr, *new_dr;
1114 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1118 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1121 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1124 static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1126 if (pci_is_managed(pdev))
1127 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1132 * pcim_enable_device - Managed pci_enable_device()
1133 * @pdev: PCI device to be initialized
1135 * Managed pci_enable_device().
1137 int pcim_enable_device(struct pci_dev *pdev)
1139 struct pci_devres *dr;
1142 dr = get_pci_dr(pdev);
1148 rc = pci_enable_device(pdev);
1150 pdev->is_managed = 1;
1157 * pcim_pin_device - Pin managed PCI device
1158 * @pdev: PCI device to pin
1160 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1161 * driver detach. @pdev must have been enabled with
1162 * pcim_enable_device().
1164 void pcim_pin_device(struct pci_dev *pdev)
1166 struct pci_devres *dr;
1168 dr = find_pci_dr(pdev);
1169 WARN_ON(!dr || !dr->enabled);
1175 * pcibios_disable_device - disable arch specific PCI resources for device dev
1176 * @dev: the PCI device to disable
1178 * Disables architecture specific PCI resources for the device. This
1179 * is the default implementation. Architecture implementations can
1182 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
1184 static void do_pci_disable_device(struct pci_dev *dev)
1188 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1189 if (pci_command & PCI_COMMAND_MASTER) {
1190 pci_command &= ~PCI_COMMAND_MASTER;
1191 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1194 pcibios_disable_device(dev);
1198 * pci_disable_enabled_device - Disable device without updating enable_cnt
1199 * @dev: PCI device to disable
1201 * NOTE: This function is a backend of PCI power management routines and is
1202 * not supposed to be called drivers.
1204 void pci_disable_enabled_device(struct pci_dev *dev)
1206 if (pci_is_enabled(dev))
1207 do_pci_disable_device(dev);
1211 * pci_disable_device - Disable PCI device after use
1212 * @dev: PCI device to be disabled
1214 * Signal to the system that the PCI device is not in use by the system
1215 * anymore. This only involves disabling PCI bus-mastering, if active.
1217 * Note we don't actually disable the device until all callers of
1218 * pci_enable_device() have called pci_disable_device().
1221 pci_disable_device(struct pci_dev *dev)
1223 struct pci_devres *dr;
1225 dr = find_pci_dr(dev);
1229 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
1232 do_pci_disable_device(dev);
1234 dev->is_busmaster = 0;
1238 * pcibios_set_pcie_reset_state - set reset state for device dev
1239 * @dev: the PCIe device reset
1240 * @state: Reset state to enter into
1243 * Sets the PCIe reset state for the device. This is the default
1244 * implementation. Architecture implementations can override this.
1246 int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
1247 enum pcie_reset_state state)
1253 * pci_set_pcie_reset_state - set reset state for device dev
1254 * @dev: the PCIe device reset
1255 * @state: Reset state to enter into
1258 * Sets the PCI reset state for the device.
1260 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1262 return pcibios_set_pcie_reset_state(dev, state);
1266 * pci_check_pme_status - Check if given device has generated PME.
1267 * @dev: Device to check.
1269 * Check the PME status of the device and if set, clear it and clear PME enable
1270 * (if set). Return 'true' if PME status and PME enable were both set or
1271 * 'false' otherwise.
1273 bool pci_check_pme_status(struct pci_dev *dev)
1282 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1283 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1284 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1287 /* Clear PME status. */
1288 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1289 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1290 /* Disable PME to avoid interrupt flood. */
1291 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1295 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1301 * Time to wait before the system can be put into a sleep state after reporting
1302 * a wakeup event signaled by a PCI device.
1304 #define PCI_WAKEUP_COOLDOWN 100
1307 * pci_wakeup_event - Report a wakeup event related to a given PCI device.
1308 * @dev: Device to report the wakeup event for.
1310 void pci_wakeup_event(struct pci_dev *dev)
1312 if (device_may_wakeup(&dev->dev))
1313 pm_wakeup_event(&dev->dev, PCI_WAKEUP_COOLDOWN);
1317 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1318 * @dev: Device to handle.
1321 * Check if @dev has generated PME and queue a resume request for it in that
1324 static int pci_pme_wakeup(struct pci_dev *dev, void *ign)
1326 if (pci_check_pme_status(dev)) {
1327 pm_request_resume(&dev->dev);
1328 pci_wakeup_event(dev);
1334 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1335 * @bus: Top bus of the subtree to walk.
1337 void pci_pme_wakeup_bus(struct pci_bus *bus)
1340 pci_walk_bus(bus, pci_pme_wakeup, NULL);
1344 * pci_pme_capable - check the capability of PCI device to generate PME#
1345 * @dev: PCI device to handle.
1346 * @state: PCI state from which device will issue PME#.
1348 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1353 return !!(dev->pme_support & (1 << state));
1356 static void pci_pme_list_scan(struct work_struct *work)
1358 struct pci_pme_device *pme_dev;
1360 mutex_lock(&pci_pme_list_mutex);
1361 if (!list_empty(&pci_pme_list)) {
1362 list_for_each_entry(pme_dev, &pci_pme_list, list)
1363 pci_pme_wakeup(pme_dev->dev, NULL);
1364 schedule_delayed_work(&pci_pme_work, msecs_to_jiffies(PME_TIMEOUT));
1366 mutex_unlock(&pci_pme_list_mutex);
1370 * pci_external_pme - is a device an external PCI PME source?
1371 * @dev: PCI device to check
1375 static bool pci_external_pme(struct pci_dev *dev)
1377 if (pci_is_pcie(dev) || dev->bus->number == 0)
1383 * pci_pme_active - enable or disable PCI device's PME# function
1384 * @dev: PCI device to handle.
1385 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1387 * The caller must verify that the device is capable of generating PME# before
1388 * calling this function with @enable equal to 'true'.
1390 void pci_pme_active(struct pci_dev *dev, bool enable)
1397 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1398 /* Clear PME_Status by writing 1 to it and enable PME# */
1399 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1401 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1403 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1405 /* PCI (as opposed to PCIe) PME requires that the device have
1406 its PME# line hooked up correctly. Not all hardware vendors
1407 do this, so the PME never gets delivered and the device
1408 remains asleep. The easiest way around this is to
1409 periodically walk the list of suspended devices and check
1410 whether any have their PME flag set. The assumption is that
1411 we'll wake up often enough anyway that this won't be a huge
1412 hit, and the power savings from the devices will still be a
1415 if (pci_external_pme(dev)) {
1416 struct pci_pme_device *pme_dev;
1418 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1423 mutex_lock(&pci_pme_list_mutex);
1424 list_add(&pme_dev->list, &pci_pme_list);
1425 if (list_is_singular(&pci_pme_list))
1426 schedule_delayed_work(&pci_pme_work,
1427 msecs_to_jiffies(PME_TIMEOUT));
1428 mutex_unlock(&pci_pme_list_mutex);
1430 mutex_lock(&pci_pme_list_mutex);
1431 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1432 if (pme_dev->dev == dev) {
1433 list_del(&pme_dev->list);
1438 mutex_unlock(&pci_pme_list_mutex);
1443 dev_printk(KERN_DEBUG, &dev->dev, "PME# %s\n",
1444 enable ? "enabled" : "disabled");
1448 * __pci_enable_wake - enable PCI device as wakeup event source
1449 * @dev: PCI device affected
1450 * @state: PCI state from which device will issue wakeup events
1451 * @runtime: True if the events are to be generated at run time
1452 * @enable: True to enable event generation; false to disable
1454 * This enables the device as a wakeup event source, or disables it.
1455 * When such events involves platform-specific hooks, those hooks are
1456 * called automatically by this routine.
1458 * Devices with legacy power management (no standard PCI PM capabilities)
1459 * always require such platform hooks.
1462 * 0 is returned on success
1463 * -EINVAL is returned if device is not supposed to wake up the system
1464 * Error code depending on the platform is returned if both the platform and
1465 * the native mechanism fail to enable the generation of wake-up events
1467 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1468 bool runtime, bool enable)
1472 if (enable && !runtime && !device_may_wakeup(&dev->dev))
1475 /* Don't do the same thing twice in a row for one device. */
1476 if (!!enable == !!dev->wakeup_prepared)
1480 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1481 * Anderson we should be doing PME# wake enable followed by ACPI wake
1482 * enable. To disable wake-up we call the platform first, for symmetry.
1488 if (pci_pme_capable(dev, state))
1489 pci_pme_active(dev, true);
1492 error = runtime ? platform_pci_run_wake(dev, true) :
1493 platform_pci_sleep_wake(dev, true);
1497 dev->wakeup_prepared = true;
1500 platform_pci_run_wake(dev, false);
1502 platform_pci_sleep_wake(dev, false);
1503 pci_pme_active(dev, false);
1504 dev->wakeup_prepared = false;
1509 EXPORT_SYMBOL(__pci_enable_wake);
1512 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1513 * @dev: PCI device to prepare
1514 * @enable: True to enable wake-up event generation; false to disable
1516 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1517 * and this function allows them to set that up cleanly - pci_enable_wake()
1518 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1519 * ordering constraints.
1521 * This function only returns error code if the device is not capable of
1522 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1523 * enable wake-up power for it.
1525 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1527 return pci_pme_capable(dev, PCI_D3cold) ?
1528 pci_enable_wake(dev, PCI_D3cold, enable) :
1529 pci_enable_wake(dev, PCI_D3hot, enable);
1533 * pci_target_state - find an appropriate low power state for a given PCI dev
1536 * Use underlying platform code to find a supported low power state for @dev.
1537 * If the platform can't manage @dev, return the deepest state from which it
1538 * can generate wake events, based on any available PME info.
1540 pci_power_t pci_target_state(struct pci_dev *dev)
1542 pci_power_t target_state = PCI_D3hot;
1544 if (platform_pci_power_manageable(dev)) {
1546 * Call the platform to choose the target state of the device
1547 * and enable wake-up from this state if supported.
1549 pci_power_t state = platform_pci_choose_state(dev);
1552 case PCI_POWER_ERROR:
1557 if (pci_no_d1d2(dev))
1560 target_state = state;
1562 } else if (!dev->pm_cap) {
1563 target_state = PCI_D0;
1564 } else if (device_may_wakeup(&dev->dev)) {
1566 * Find the deepest state from which the device can generate
1567 * wake-up events, make it the target state and enable device
1570 if (dev->pme_support) {
1572 && !(dev->pme_support & (1 << target_state)))
1577 return target_state;
1581 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1582 * @dev: Device to handle.
1584 * Choose the power state appropriate for the device depending on whether
1585 * it can wake up the system and/or is power manageable by the platform
1586 * (PCI_D3hot is the default) and put the device into that state.
1588 int pci_prepare_to_sleep(struct pci_dev *dev)
1590 pci_power_t target_state = pci_target_state(dev);
1593 if (target_state == PCI_POWER_ERROR)
1596 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1598 error = pci_set_power_state(dev, target_state);
1601 pci_enable_wake(dev, target_state, false);
1607 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1608 * @dev: Device to handle.
1610 * Disable device's system wake-up capability and put it into D0.
1612 int pci_back_from_sleep(struct pci_dev *dev)
1614 pci_enable_wake(dev, PCI_D0, false);
1615 return pci_set_power_state(dev, PCI_D0);
1619 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1620 * @dev: PCI device being suspended.
1622 * Prepare @dev to generate wake-up events at run time and put it into a low
1625 int pci_finish_runtime_suspend(struct pci_dev *dev)
1627 pci_power_t target_state = pci_target_state(dev);
1630 if (target_state == PCI_POWER_ERROR)
1633 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1635 error = pci_set_power_state(dev, target_state);
1638 __pci_enable_wake(dev, target_state, true, false);
1644 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1645 * @dev: Device to check.
1647 * Return true if the device itself is cabable of generating wake-up events
1648 * (through the platform or using the native PCIe PME) or if the device supports
1649 * PME and one of its upstream bridges can generate wake-up events.
1651 bool pci_dev_run_wake(struct pci_dev *dev)
1653 struct pci_bus *bus = dev->bus;
1655 if (device_run_wake(&dev->dev))
1658 if (!dev->pme_support)
1661 while (bus->parent) {
1662 struct pci_dev *bridge = bus->self;
1664 if (device_run_wake(&bridge->dev))
1670 /* We have reached the root bus. */
1672 return device_run_wake(bus->bridge);
1676 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
1679 * pci_pm_init - Initialize PM functions of given PCI device
1680 * @dev: PCI device to handle.
1682 void pci_pm_init(struct pci_dev *dev)
1687 pm_runtime_forbid(&dev->dev);
1688 device_enable_async_suspend(&dev->dev);
1689 dev->wakeup_prepared = false;
1693 /* find PCI PM capability in list */
1694 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1697 /* Check device's ability to generate PME# */
1698 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
1700 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1701 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1702 pmc & PCI_PM_CAP_VER_MASK);
1707 dev->d3_delay = PCI_PM_D3_WAIT;
1709 dev->d1_support = false;
1710 dev->d2_support = false;
1711 if (!pci_no_d1d2(dev)) {
1712 if (pmc & PCI_PM_CAP_D1)
1713 dev->d1_support = true;
1714 if (pmc & PCI_PM_CAP_D2)
1715 dev->d2_support = true;
1717 if (dev->d1_support || dev->d2_support)
1718 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
1719 dev->d1_support ? " D1" : "",
1720 dev->d2_support ? " D2" : "");
1723 pmc &= PCI_PM_CAP_PME_MASK;
1725 dev_printk(KERN_DEBUG, &dev->dev,
1726 "PME# supported from%s%s%s%s%s\n",
1727 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1728 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
1729 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
1730 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
1731 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
1732 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
1734 * Make device's PM flags reflect the wake-up capability, but
1735 * let the user space enable it to wake up the system as needed.
1737 device_set_wakeup_capable(&dev->dev, true);
1738 /* Disable the PME# generation functionality */
1739 pci_pme_active(dev, false);
1741 dev->pme_support = 0;
1746 * platform_pci_wakeup_init - init platform wakeup if present
1749 * Some devices don't have PCI PM caps but can still generate wakeup
1750 * events through platform methods (like ACPI events). If @dev supports
1751 * platform wakeup events, set the device flag to indicate as much. This
1752 * may be redundant if the device also supports PCI PM caps, but double
1753 * initialization should be safe in that case.
1755 void platform_pci_wakeup_init(struct pci_dev *dev)
1757 if (!platform_pci_can_wakeup(dev))
1760 device_set_wakeup_capable(&dev->dev, true);
1761 platform_pci_sleep_wake(dev, false);
1765 * pci_add_save_buffer - allocate buffer for saving given capability registers
1766 * @dev: the PCI device
1767 * @cap: the capability to allocate the buffer for
1768 * @size: requested size of the buffer
1770 static int pci_add_cap_save_buffer(
1771 struct pci_dev *dev, char cap, unsigned int size)
1774 struct pci_cap_saved_state *save_state;
1776 pos = pci_find_capability(dev, cap);
1780 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
1784 save_state->cap_nr = cap;
1785 pci_add_saved_cap(dev, save_state);
1791 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1792 * @dev: the PCI device
1794 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
1798 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
1799 PCI_EXP_SAVE_REGS * sizeof(u16));
1802 "unable to preallocate PCI Express save buffer\n");
1804 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
1807 "unable to preallocate PCI-X save buffer\n");
1811 * pci_enable_ari - enable ARI forwarding if hardware support it
1812 * @dev: the PCI device
1814 void pci_enable_ari(struct pci_dev *dev)
1819 struct pci_dev *bridge;
1821 if (!pci_is_pcie(dev) || dev->devfn)
1824 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1828 bridge = dev->bus->self;
1829 if (!bridge || !pci_is_pcie(bridge))
1832 pos = pci_pcie_cap(bridge);
1836 pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
1837 if (!(cap & PCI_EXP_DEVCAP2_ARI))
1840 pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl);
1841 ctrl |= PCI_EXP_DEVCTL2_ARI;
1842 pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl);
1844 bridge->ari_enabled = 1;
1847 static int pci_acs_enable;
1850 * pci_request_acs - ask for ACS to be enabled if supported
1852 void pci_request_acs(void)
1858 * pci_enable_acs - enable ACS if hardware support it
1859 * @dev: the PCI device
1861 void pci_enable_acs(struct pci_dev *dev)
1867 if (!pci_acs_enable)
1870 if (!pci_is_pcie(dev))
1873 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
1877 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
1878 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
1880 /* Source Validation */
1881 ctrl |= (cap & PCI_ACS_SV);
1883 /* P2P Request Redirect */
1884 ctrl |= (cap & PCI_ACS_RR);
1886 /* P2P Completion Redirect */
1887 ctrl |= (cap & PCI_ACS_CR);
1889 /* Upstream Forwarding */
1890 ctrl |= (cap & PCI_ACS_UF);
1892 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
1896 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
1897 * @dev: the PCI device
1898 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1900 * Perform INTx swizzling for a device behind one level of bridge. This is
1901 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
1902 * behind bridges on add-in cards. For devices with ARI enabled, the slot
1903 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
1904 * the PCI Express Base Specification, Revision 2.1)
1906 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin)
1910 if (pci_ari_enabled(dev->bus))
1913 slot = PCI_SLOT(dev->devfn);
1915 return (((pin - 1) + slot) % 4) + 1;
1919 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
1927 while (!pci_is_root_bus(dev->bus)) {
1928 pin = pci_swizzle_interrupt_pin(dev, pin);
1929 dev = dev->bus->self;
1936 * pci_common_swizzle - swizzle INTx all the way to root bridge
1937 * @dev: the PCI device
1938 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1940 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
1941 * bridges all the way up to a PCI root bus.
1943 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
1947 while (!pci_is_root_bus(dev->bus)) {
1948 pin = pci_swizzle_interrupt_pin(dev, pin);
1949 dev = dev->bus->self;
1952 return PCI_SLOT(dev->devfn);
1956 * pci_release_region - Release a PCI bar
1957 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1958 * @bar: BAR to release
1960 * Releases the PCI I/O and memory resources previously reserved by a
1961 * successful call to pci_request_region. Call this function only
1962 * after all use of the PCI regions has ceased.
1964 void pci_release_region(struct pci_dev *pdev, int bar)
1966 struct pci_devres *dr;
1968 if (pci_resource_len(pdev, bar) == 0)
1970 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
1971 release_region(pci_resource_start(pdev, bar),
1972 pci_resource_len(pdev, bar));
1973 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
1974 release_mem_region(pci_resource_start(pdev, bar),
1975 pci_resource_len(pdev, bar));
1977 dr = find_pci_dr(pdev);
1979 dr->region_mask &= ~(1 << bar);
1983 * __pci_request_region - Reserved PCI I/O and memory resource
1984 * @pdev: PCI device whose resources are to be reserved
1985 * @bar: BAR to be reserved
1986 * @res_name: Name to be associated with resource.
1987 * @exclusive: whether the region access is exclusive or not
1989 * Mark the PCI region associated with PCI device @pdev BR @bar as
1990 * being reserved by owner @res_name. Do not access any
1991 * address inside the PCI regions unless this call returns
1994 * If @exclusive is set, then the region is marked so that userspace
1995 * is explicitly not allowed to map the resource via /dev/mem or
1996 * sysfs MMIO access.
1998 * Returns 0 on success, or %EBUSY on error. A warning
1999 * message is also printed on failure.
2001 static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
2004 struct pci_devres *dr;
2006 if (pci_resource_len(pdev, bar) == 0)
2009 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
2010 if (!request_region(pci_resource_start(pdev, bar),
2011 pci_resource_len(pdev, bar), res_name))
2014 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
2015 if (!__request_mem_region(pci_resource_start(pdev, bar),
2016 pci_resource_len(pdev, bar), res_name,
2021 dr = find_pci_dr(pdev);
2023 dr->region_mask |= 1 << bar;
2028 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
2029 &pdev->resource[bar]);
2034 * pci_request_region - Reserve PCI I/O and memory resource
2035 * @pdev: PCI device whose resources are to be reserved
2036 * @bar: BAR to be reserved
2037 * @res_name: Name to be associated with resource
2039 * Mark the PCI region associated with PCI device @pdev BAR @bar as
2040 * being reserved by owner @res_name. Do not access any
2041 * address inside the PCI regions unless this call returns
2044 * Returns 0 on success, or %EBUSY on error. A warning
2045 * message is also printed on failure.
2047 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
2049 return __pci_request_region(pdev, bar, res_name, 0);
2053 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2054 * @pdev: PCI device whose resources are to be reserved
2055 * @bar: BAR to be reserved
2056 * @res_name: Name to be associated with resource.
2058 * Mark the PCI region associated with PCI device @pdev BR @bar as
2059 * being reserved by owner @res_name. Do not access any
2060 * address inside the PCI regions unless this call returns
2063 * Returns 0 on success, or %EBUSY on error. A warning
2064 * message is also printed on failure.
2066 * The key difference that _exclusive makes it that userspace is
2067 * explicitly not allowed to map the resource via /dev/mem or
2070 int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
2072 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
2075 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2076 * @pdev: PCI device whose resources were previously reserved
2077 * @bars: Bitmask of BARs to be released
2079 * Release selected PCI I/O and memory resources previously reserved.
2080 * Call this function only after all use of the PCI regions has ceased.
2082 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
2086 for (i = 0; i < 6; i++)
2087 if (bars & (1 << i))
2088 pci_release_region(pdev, i);
2091 int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
2092 const char *res_name, int excl)
2096 for (i = 0; i < 6; i++)
2097 if (bars & (1 << i))
2098 if (__pci_request_region(pdev, i, res_name, excl))
2104 if (bars & (1 << i))
2105 pci_release_region(pdev, i);
2112 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2113 * @pdev: PCI device whose resources are to be reserved
2114 * @bars: Bitmask of BARs to be requested
2115 * @res_name: Name to be associated with resource
2117 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
2118 const char *res_name)
2120 return __pci_request_selected_regions(pdev, bars, res_name, 0);
2123 int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
2124 int bars, const char *res_name)
2126 return __pci_request_selected_regions(pdev, bars, res_name,
2127 IORESOURCE_EXCLUSIVE);
2131 * pci_release_regions - Release reserved PCI I/O and memory resources
2132 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2134 * Releases all PCI I/O and memory resources previously reserved by a
2135 * successful call to pci_request_regions. Call this function only
2136 * after all use of the PCI regions has ceased.
2139 void pci_release_regions(struct pci_dev *pdev)
2141 pci_release_selected_regions(pdev, (1 << 6) - 1);
2145 * pci_request_regions - Reserved PCI I/O and memory resources
2146 * @pdev: PCI device whose resources are to be reserved
2147 * @res_name: Name to be associated with resource.
2149 * Mark all PCI regions associated with PCI device @pdev as
2150 * being reserved by owner @res_name. Do not access any
2151 * address inside the PCI regions unless this call returns
2154 * Returns 0 on success, or %EBUSY on error. A warning
2155 * message is also printed on failure.
2157 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
2159 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
2163 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2164 * @pdev: PCI device whose resources are to be reserved
2165 * @res_name: Name to be associated with resource.
2167 * Mark all PCI regions associated with PCI device @pdev as
2168 * being reserved by owner @res_name. Do not access any
2169 * address inside the PCI regions unless this call returns
2172 * pci_request_regions_exclusive() will mark the region so that
2173 * /dev/mem and the sysfs MMIO access will not be allowed.
2175 * Returns 0 on success, or %EBUSY on error. A warning
2176 * message is also printed on failure.
2178 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
2180 return pci_request_selected_regions_exclusive(pdev,
2181 ((1 << 6) - 1), res_name);
2184 static void __pci_set_master(struct pci_dev *dev, bool enable)
2188 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
2190 cmd = old_cmd | PCI_COMMAND_MASTER;
2192 cmd = old_cmd & ~PCI_COMMAND_MASTER;
2193 if (cmd != old_cmd) {
2194 dev_dbg(&dev->dev, "%s bus mastering\n",
2195 enable ? "enabling" : "disabling");
2196 pci_write_config_word(dev, PCI_COMMAND, cmd);
2198 dev->is_busmaster = enable;
2202 * pci_set_master - enables bus-mastering for device dev
2203 * @dev: the PCI device to enable
2205 * Enables bus-mastering on the device and calls pcibios_set_master()
2206 * to do the needed arch specific settings.
2208 void pci_set_master(struct pci_dev *dev)
2210 __pci_set_master(dev, true);
2211 pcibios_set_master(dev);
2215 * pci_clear_master - disables bus-mastering for device dev
2216 * @dev: the PCI device to disable
2218 void pci_clear_master(struct pci_dev *dev)
2220 __pci_set_master(dev, false);
2224 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2225 * @dev: the PCI device for which MWI is to be enabled
2227 * Helper function for pci_set_mwi.
2228 * Originally copied from drivers/net/acenic.c.
2229 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2231 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2233 int pci_set_cacheline_size(struct pci_dev *dev)
2237 if (!pci_cache_line_size)
2240 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2241 equal to or multiple of the right value. */
2242 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2243 if (cacheline_size >= pci_cache_line_size &&
2244 (cacheline_size % pci_cache_line_size) == 0)
2247 /* Write the correct value. */
2248 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
2250 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2251 if (cacheline_size == pci_cache_line_size)
2254 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
2255 "supported\n", pci_cache_line_size << 2);
2259 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
2261 #ifdef PCI_DISABLE_MWI
2262 int pci_set_mwi(struct pci_dev *dev)
2267 int pci_try_set_mwi(struct pci_dev *dev)
2272 void pci_clear_mwi(struct pci_dev *dev)
2279 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2280 * @dev: the PCI device for which MWI is enabled
2282 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2284 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2287 pci_set_mwi(struct pci_dev *dev)
2292 rc = pci_set_cacheline_size(dev);
2296 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2297 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
2298 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
2299 cmd |= PCI_COMMAND_INVALIDATE;
2300 pci_write_config_word(dev, PCI_COMMAND, cmd);
2307 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2308 * @dev: the PCI device for which MWI is enabled
2310 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2311 * Callers are not required to check the return value.
2313 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2315 int pci_try_set_mwi(struct pci_dev *dev)
2317 int rc = pci_set_mwi(dev);
2322 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2323 * @dev: the PCI device to disable
2325 * Disables PCI Memory-Write-Invalidate transaction on the device
2328 pci_clear_mwi(struct pci_dev *dev)
2332 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2333 if (cmd & PCI_COMMAND_INVALIDATE) {
2334 cmd &= ~PCI_COMMAND_INVALIDATE;
2335 pci_write_config_word(dev, PCI_COMMAND, cmd);
2338 #endif /* ! PCI_DISABLE_MWI */
2341 * pci_intx - enables/disables PCI INTx for device dev
2342 * @pdev: the PCI device to operate on
2343 * @enable: boolean: whether to enable or disable PCI INTx
2345 * Enables/disables PCI INTx for device dev
2348 pci_intx(struct pci_dev *pdev, int enable)
2350 u16 pci_command, new;
2352 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
2355 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
2357 new = pci_command | PCI_COMMAND_INTX_DISABLE;
2360 if (new != pci_command) {
2361 struct pci_devres *dr;
2363 pci_write_config_word(pdev, PCI_COMMAND, new);
2365 dr = find_pci_dr(pdev);
2366 if (dr && !dr->restore_intx) {
2367 dr->restore_intx = 1;
2368 dr->orig_intx = !enable;
2374 * pci_msi_off - disables any msi or msix capabilities
2375 * @dev: the PCI device to operate on
2377 * If you want to use msi see pci_enable_msi and friends.
2378 * This is a lower level primitive that allows us to disable
2379 * msi operation at the device level.
2381 void pci_msi_off(struct pci_dev *dev)
2386 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
2388 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
2389 control &= ~PCI_MSI_FLAGS_ENABLE;
2390 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
2392 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
2394 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
2395 control &= ~PCI_MSIX_FLAGS_ENABLE;
2396 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
2399 EXPORT_SYMBOL_GPL(pci_msi_off);
2401 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
2403 return dma_set_max_seg_size(&dev->dev, size);
2405 EXPORT_SYMBOL(pci_set_dma_max_seg_size);
2407 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
2409 return dma_set_seg_boundary(&dev->dev, mask);
2411 EXPORT_SYMBOL(pci_set_dma_seg_boundary);
2413 static int pcie_flr(struct pci_dev *dev, int probe)
2418 u16 status, control;
2420 pos = pci_pcie_cap(dev);
2424 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap);
2425 if (!(cap & PCI_EXP_DEVCAP_FLR))
2431 /* Wait for Transaction Pending bit clean */
2432 for (i = 0; i < 4; i++) {
2434 msleep((1 << (i - 1)) * 100);
2436 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
2437 if (!(status & PCI_EXP_DEVSTA_TRPND))
2441 dev_err(&dev->dev, "transaction is not cleared; "
2442 "proceeding with reset anyway\n");
2445 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &control);
2446 control |= PCI_EXP_DEVCTL_BCR_FLR;
2447 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, control);
2454 static int pci_af_flr(struct pci_dev *dev, int probe)
2461 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
2465 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
2466 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
2472 /* Wait for Transaction Pending bit clean */
2473 for (i = 0; i < 4; i++) {
2475 msleep((1 << (i - 1)) * 100);
2477 pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
2478 if (!(status & PCI_AF_STATUS_TP))
2482 dev_err(&dev->dev, "transaction is not cleared; "
2483 "proceeding with reset anyway\n");
2486 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
2492 static int pci_pm_reset(struct pci_dev *dev, int probe)
2499 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
2500 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
2506 if (dev->current_state != PCI_D0)
2509 csr &= ~PCI_PM_CTRL_STATE_MASK;
2511 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
2512 pci_dev_d3_sleep(dev);
2514 csr &= ~PCI_PM_CTRL_STATE_MASK;
2516 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
2517 pci_dev_d3_sleep(dev);
2522 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
2525 struct pci_dev *pdev;
2527 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
2530 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
2537 pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl);
2538 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
2539 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2542 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
2543 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2549 static int pci_dev_reset(struct pci_dev *dev, int probe)
2556 pci_block_user_cfg_access(dev);
2557 /* block PM suspend, driver probe, etc. */
2558 device_lock(&dev->dev);
2561 rc = pci_dev_specific_reset(dev, probe);
2565 rc = pcie_flr(dev, probe);
2569 rc = pci_af_flr(dev, probe);
2573 rc = pci_pm_reset(dev, probe);
2577 rc = pci_parent_bus_reset(dev, probe);
2580 device_unlock(&dev->dev);
2581 pci_unblock_user_cfg_access(dev);
2588 * __pci_reset_function - reset a PCI device function
2589 * @dev: PCI device to reset
2591 * Some devices allow an individual function to be reset without affecting
2592 * other functions in the same device. The PCI device must be responsive
2593 * to PCI config space in order to use this function.
2595 * The device function is presumed to be unused when this function is called.
2596 * Resetting the device will make the contents of PCI configuration space
2597 * random, so any caller of this must be prepared to reinitialise the
2598 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
2601 * Returns 0 if the device function was successfully reset or negative if the
2602 * device doesn't support resetting a single function.
2604 int __pci_reset_function(struct pci_dev *dev)
2606 return pci_dev_reset(dev, 0);
2608 EXPORT_SYMBOL_GPL(__pci_reset_function);
2611 * pci_probe_reset_function - check whether the device can be safely reset
2612 * @dev: PCI device to reset
2614 * Some devices allow an individual function to be reset without affecting
2615 * other functions in the same device. The PCI device must be responsive
2616 * to PCI config space in order to use this function.
2618 * Returns 0 if the device function can be reset or negative if the
2619 * device doesn't support resetting a single function.
2621 int pci_probe_reset_function(struct pci_dev *dev)
2623 return pci_dev_reset(dev, 1);
2627 * pci_reset_function - quiesce and reset a PCI device function
2628 * @dev: PCI device to reset
2630 * Some devices allow an individual function to be reset without affecting
2631 * other functions in the same device. The PCI device must be responsive
2632 * to PCI config space in order to use this function.
2634 * This function does not just reset the PCI portion of a device, but
2635 * clears all the state associated with the device. This function differs
2636 * from __pci_reset_function in that it saves and restores device state
2639 * Returns 0 if the device function was successfully reset or negative if the
2640 * device doesn't support resetting a single function.
2642 int pci_reset_function(struct pci_dev *dev)
2646 rc = pci_dev_reset(dev, 1);
2650 pci_save_state(dev);
2653 * both INTx and MSI are disabled after the Interrupt Disable bit
2654 * is set and the Bus Master bit is cleared.
2656 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
2658 rc = pci_dev_reset(dev, 0);
2660 pci_restore_state(dev);
2664 EXPORT_SYMBOL_GPL(pci_reset_function);
2667 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
2668 * @dev: PCI device to query
2670 * Returns mmrbc: maximum designed memory read count in bytes
2671 * or appropriate error value.
2673 int pcix_get_max_mmrbc(struct pci_dev *dev)
2678 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2682 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
2685 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
2687 EXPORT_SYMBOL(pcix_get_max_mmrbc);
2690 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
2691 * @dev: PCI device to query
2693 * Returns mmrbc: maximum memory read count in bytes
2694 * or appropriate error value.
2696 int pcix_get_mmrbc(struct pci_dev *dev)
2701 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2705 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
2708 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
2710 EXPORT_SYMBOL(pcix_get_mmrbc);
2713 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
2714 * @dev: PCI device to query
2715 * @mmrbc: maximum memory read count in bytes
2716 * valid values are 512, 1024, 2048, 4096
2718 * If possible sets maximum memory read byte count, some bridges have erratas
2719 * that prevent this.
2721 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
2727 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
2730 v = ffs(mmrbc) - 10;
2732 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2736 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
2739 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
2742 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
2745 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
2747 if (v > o && dev->bus &&
2748 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
2751 cmd &= ~PCI_X_CMD_MAX_READ;
2753 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
2758 EXPORT_SYMBOL(pcix_set_mmrbc);
2761 * pcie_get_readrq - get PCI Express read request size
2762 * @dev: PCI device to query
2764 * Returns maximum memory read request in bytes
2765 * or appropriate error value.
2767 int pcie_get_readrq(struct pci_dev *dev)
2772 cap = pci_pcie_cap(dev);
2776 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
2778 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
2782 EXPORT_SYMBOL(pcie_get_readrq);
2785 * pcie_set_readrq - set PCI Express maximum memory read request
2786 * @dev: PCI device to query
2787 * @rq: maximum memory read count in bytes
2788 * valid values are 128, 256, 512, 1024, 2048, 4096
2790 * If possible sets maximum read byte count
2792 int pcie_set_readrq(struct pci_dev *dev, int rq)
2794 int cap, err = -EINVAL;
2797 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
2800 v = (ffs(rq) - 8) << 12;
2802 cap = pci_pcie_cap(dev);
2806 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
2810 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
2811 ctl &= ~PCI_EXP_DEVCTL_READRQ;
2813 err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl);
2819 EXPORT_SYMBOL(pcie_set_readrq);
2822 * pci_select_bars - Make BAR mask from the type of resource
2823 * @dev: the PCI device for which BAR mask is made
2824 * @flags: resource type mask to be selected
2826 * This helper routine makes bar mask from the type of resource.
2828 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
2831 for (i = 0; i < PCI_NUM_RESOURCES; i++)
2832 if (pci_resource_flags(dev, i) & flags)
2838 * pci_resource_bar - get position of the BAR associated with a resource
2839 * @dev: the PCI device
2840 * @resno: the resource number
2841 * @type: the BAR type to be filled in
2843 * Returns BAR position in config space, or 0 if the BAR is invalid.
2845 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
2849 if (resno < PCI_ROM_RESOURCE) {
2850 *type = pci_bar_unknown;
2851 return PCI_BASE_ADDRESS_0 + 4 * resno;
2852 } else if (resno == PCI_ROM_RESOURCE) {
2853 *type = pci_bar_mem32;
2854 return dev->rom_base_reg;
2855 } else if (resno < PCI_BRIDGE_RESOURCES) {
2856 /* device specific resource */
2857 reg = pci_iov_resource_bar(dev, resno, type);
2862 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
2866 /* Some architectures require additional programming to enable VGA */
2867 static arch_set_vga_state_t arch_set_vga_state;
2869 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
2871 arch_set_vga_state = func; /* NULL disables */
2874 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
2875 unsigned int command_bits, bool change_bridge)
2877 if (arch_set_vga_state)
2878 return arch_set_vga_state(dev, decode, command_bits,
2884 * pci_set_vga_state - set VGA decode state on device and parents if requested
2885 * @dev: the PCI device
2886 * @decode: true = enable decoding, false = disable decoding
2887 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
2888 * @change_bridge: traverse ancestors and change bridges
2890 int pci_set_vga_state(struct pci_dev *dev, bool decode,
2891 unsigned int command_bits, bool change_bridge)
2893 struct pci_bus *bus;
2894 struct pci_dev *bridge;
2898 WARN_ON(command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY));
2900 /* ARCH specific VGA enables */
2901 rc = pci_set_vga_state_arch(dev, decode, command_bits, change_bridge);
2905 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2907 cmd |= command_bits;
2909 cmd &= ~command_bits;
2910 pci_write_config_word(dev, PCI_COMMAND, cmd);
2912 if (change_bridge == false)
2919 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
2922 cmd |= PCI_BRIDGE_CTL_VGA;
2924 cmd &= ~PCI_BRIDGE_CTL_VGA;
2925 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
2933 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
2934 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
2935 static DEFINE_SPINLOCK(resource_alignment_lock);
2938 * pci_specified_resource_alignment - get resource alignment specified by user.
2939 * @dev: the PCI device to get
2941 * RETURNS: Resource alignment if it is specified.
2942 * Zero if it is not specified.
2944 resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
2946 int seg, bus, slot, func, align_order, count;
2947 resource_size_t align = 0;
2950 spin_lock(&resource_alignment_lock);
2951 p = resource_alignment_param;
2954 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
2960 if (sscanf(p, "%x:%x:%x.%x%n",
2961 &seg, &bus, &slot, &func, &count) != 4) {
2963 if (sscanf(p, "%x:%x.%x%n",
2964 &bus, &slot, &func, &count) != 3) {
2965 /* Invalid format */
2966 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
2972 if (seg == pci_domain_nr(dev->bus) &&
2973 bus == dev->bus->number &&
2974 slot == PCI_SLOT(dev->devfn) &&
2975 func == PCI_FUNC(dev->devfn)) {
2976 if (align_order == -1) {
2979 align = 1 << align_order;
2984 if (*p != ';' && *p != ',') {
2985 /* End of param or invalid format */
2990 spin_unlock(&resource_alignment_lock);
2995 * pci_is_reassigndev - check if specified PCI is target device to reassign
2996 * @dev: the PCI device to check
2998 * RETURNS: non-zero for PCI device is a target device to reassign,
3001 int pci_is_reassigndev(struct pci_dev *dev)
3003 return (pci_specified_resource_alignment(dev) != 0);
3006 ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
3008 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
3009 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
3010 spin_lock(&resource_alignment_lock);
3011 strncpy(resource_alignment_param, buf, count);
3012 resource_alignment_param[count] = '\0';
3013 spin_unlock(&resource_alignment_lock);
3017 ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
3020 spin_lock(&resource_alignment_lock);
3021 count = snprintf(buf, size, "%s", resource_alignment_param);
3022 spin_unlock(&resource_alignment_lock);
3026 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
3028 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
3031 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
3032 const char *buf, size_t count)
3034 return pci_set_resource_alignment_param(buf, count);
3037 BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
3038 pci_resource_alignment_store);
3040 static int __init pci_resource_alignment_sysfs_init(void)
3042 return bus_create_file(&pci_bus_type,
3043 &bus_attr_resource_alignment);
3046 late_initcall(pci_resource_alignment_sysfs_init);
3048 static void __devinit pci_no_domains(void)
3050 #ifdef CONFIG_PCI_DOMAINS
3051 pci_domains_supported = 0;
3056 * pci_ext_cfg_enabled - can we access extended PCI config space?
3057 * @dev: The PCI device of the root bridge.
3059 * Returns 1 if we can access PCI extended config space (offsets
3060 * greater than 0xff). This is the default implementation. Architecture
3061 * implementations can override this.
3063 int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev)
3068 void __weak pci_fixup_cardbus(struct pci_bus *bus)
3071 EXPORT_SYMBOL(pci_fixup_cardbus);
3073 static int __init pci_setup(char *str)
3076 char *k = strchr(str, ',');
3079 if (*str && (str = pcibios_setup(str)) && *str) {
3080 if (!strcmp(str, "nomsi")) {
3082 } else if (!strcmp(str, "noaer")) {
3084 } else if (!strcmp(str, "nodomains")) {
3086 } else if (!strncmp(str, "cbiosize=", 9)) {
3087 pci_cardbus_io_size = memparse(str + 9, &str);
3088 } else if (!strncmp(str, "cbmemsize=", 10)) {
3089 pci_cardbus_mem_size = memparse(str + 10, &str);
3090 } else if (!strncmp(str, "resource_alignment=", 19)) {
3091 pci_set_resource_alignment_param(str + 19,
3093 } else if (!strncmp(str, "ecrc=", 5)) {
3094 pcie_ecrc_get_policy(str + 5);
3095 } else if (!strncmp(str, "hpiosize=", 9)) {
3096 pci_hotplug_io_size = memparse(str + 9, &str);
3097 } else if (!strncmp(str, "hpmemsize=", 10)) {
3098 pci_hotplug_mem_size = memparse(str + 10, &str);
3100 printk(KERN_ERR "PCI: Unknown option `%s'\n",
3108 early_param("pci", pci_setup);
3110 EXPORT_SYMBOL(pci_reenable_device);
3111 EXPORT_SYMBOL(pci_enable_device_io);
3112 EXPORT_SYMBOL(pci_enable_device_mem);
3113 EXPORT_SYMBOL(pci_enable_device);
3114 EXPORT_SYMBOL(pcim_enable_device);
3115 EXPORT_SYMBOL(pcim_pin_device);
3116 EXPORT_SYMBOL(pci_disable_device);
3117 EXPORT_SYMBOL(pci_find_capability);
3118 EXPORT_SYMBOL(pci_bus_find_capability);
3119 EXPORT_SYMBOL(pci_release_regions);
3120 EXPORT_SYMBOL(pci_request_regions);
3121 EXPORT_SYMBOL(pci_request_regions_exclusive);
3122 EXPORT_SYMBOL(pci_release_region);
3123 EXPORT_SYMBOL(pci_request_region);
3124 EXPORT_SYMBOL(pci_request_region_exclusive);
3125 EXPORT_SYMBOL(pci_release_selected_regions);
3126 EXPORT_SYMBOL(pci_request_selected_regions);
3127 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3128 EXPORT_SYMBOL(pci_set_master);
3129 EXPORT_SYMBOL(pci_clear_master);
3130 EXPORT_SYMBOL(pci_set_mwi);
3131 EXPORT_SYMBOL(pci_try_set_mwi);
3132 EXPORT_SYMBOL(pci_clear_mwi);
3133 EXPORT_SYMBOL_GPL(pci_intx);
3134 EXPORT_SYMBOL(pci_assign_resource);
3135 EXPORT_SYMBOL(pci_find_parent_resource);
3136 EXPORT_SYMBOL(pci_select_bars);
3138 EXPORT_SYMBOL(pci_set_power_state);
3139 EXPORT_SYMBOL(pci_save_state);
3140 EXPORT_SYMBOL(pci_restore_state);
3141 EXPORT_SYMBOL(pci_pme_capable);
3142 EXPORT_SYMBOL(pci_pme_active);
3143 EXPORT_SYMBOL(pci_wake_from_d3);
3144 EXPORT_SYMBOL(pci_target_state);
3145 EXPORT_SYMBOL(pci_prepare_to_sleep);
3146 EXPORT_SYMBOL(pci_back_from_sleep);
3147 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);