2 * PCI Express PCI Hot Plug Driver
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/signal.h>
34 #include <linux/jiffies.h>
35 #include <linux/timer.h>
36 #include <linux/pci.h>
37 #include <linux/interrupt.h>
38 #include <linux/time.h>
39 #include <linux/slab.h>
44 static inline struct pci_dev *ctrl_dev(struct controller *ctrl)
46 return ctrl->pcie->port;
49 /* Power Control Command */
51 #define POWER_OFF PCI_EXP_SLTCTL_PCC
53 static irqreturn_t pcie_isr(int irq, void *dev_id);
54 static void start_int_poll_timer(struct controller *ctrl, int sec);
56 /* This is the interrupt polling timeout function. */
57 static void int_poll_timeout(unsigned long data)
59 struct controller *ctrl = (struct controller *)data;
61 /* Poll for interrupt events. regs == NULL => polling */
64 init_timer(&ctrl->poll_timer);
65 if (!pciehp_poll_time)
66 pciehp_poll_time = 2; /* default polling interval is 2 sec */
68 start_int_poll_timer(ctrl, pciehp_poll_time);
71 /* This function starts the interrupt polling timer. */
72 static void start_int_poll_timer(struct controller *ctrl, int sec)
74 /* Clamp to sane value */
75 if ((sec <= 0) || (sec > 60))
78 ctrl->poll_timer.function = &int_poll_timeout;
79 ctrl->poll_timer.data = (unsigned long)ctrl;
80 ctrl->poll_timer.expires = jiffies + sec * HZ;
81 add_timer(&ctrl->poll_timer);
84 static inline int pciehp_request_irq(struct controller *ctrl)
86 int retval, irq = ctrl->pcie->irq;
88 /* Install interrupt polling timer. Start with 10 sec delay */
89 if (pciehp_poll_mode) {
90 init_timer(&ctrl->poll_timer);
91 start_int_poll_timer(ctrl, 10);
95 /* Installs the interrupt handler */
96 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
98 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
103 static inline void pciehp_free_irq(struct controller *ctrl)
105 if (pciehp_poll_mode)
106 del_timer_sync(&ctrl->poll_timer);
108 free_irq(ctrl->pcie->irq, ctrl);
111 static int pcie_poll_cmd(struct controller *ctrl)
113 struct pci_dev *pdev = ctrl_dev(ctrl);
117 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
118 if (slot_status & PCI_EXP_SLTSTA_CC) {
119 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
123 while (timeout > 0) {
126 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
127 if (slot_status & PCI_EXP_SLTSTA_CC) {
128 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
133 return 0; /* timeout */
136 static void pcie_wait_cmd(struct controller *ctrl, int poll)
138 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
139 unsigned long timeout = msecs_to_jiffies(msecs);
143 rc = pcie_poll_cmd(ctrl);
145 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
147 ctrl_dbg(ctrl, "Command not completed in 1000 msec\n");
151 * pcie_write_cmd - Issue controller command
152 * @ctrl: controller to which the command is issued
153 * @cmd: command value written to slot control register
154 * @mask: bitmask of slot control register to be modified
156 static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
158 struct pci_dev *pdev = ctrl_dev(ctrl);
162 mutex_lock(&ctrl->ctrl_lock);
164 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
165 if (slot_status & PCI_EXP_SLTSTA_CC) {
166 if (!ctrl->no_cmd_complete) {
168 * After 1 sec and CMD_COMPLETED still not set, just
169 * proceed forward to issue the next command according
170 * to spec. Just print out the error message.
172 ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n");
173 } else if (!NO_CMD_CMPL(ctrl)) {
175 * This controller seems to notify of command completed
176 * event even though it supports none of power
177 * controller, attention led, power led and EMI.
179 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to "
180 "wait for command completed event.\n");
181 ctrl->no_cmd_complete = 0;
183 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe "
184 "the controller is broken.\n");
188 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
190 slot_ctrl |= (cmd & mask);
193 pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
196 * Wait for command completion.
198 if (!ctrl->no_cmd_complete) {
201 * if hotplug interrupt is not enabled or command
202 * completed interrupt is not enabled, we need to poll
203 * command completed event.
205 if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) ||
206 !(slot_ctrl & PCI_EXP_SLTCTL_CCIE))
208 pcie_wait_cmd(ctrl, poll);
210 mutex_unlock(&ctrl->ctrl_lock);
213 static bool check_link_active(struct controller *ctrl)
215 struct pci_dev *pdev = ctrl_dev(ctrl);
219 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
220 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
223 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
228 static void __pcie_wait_link_active(struct controller *ctrl, bool active)
232 if (check_link_active(ctrl) == active)
234 while (timeout > 0) {
237 if (check_link_active(ctrl) == active)
240 ctrl_dbg(ctrl, "Data Link Layer Link Active not %s in 1000 msec\n",
241 active ? "set" : "cleared");
244 static void pcie_wait_link_active(struct controller *ctrl)
246 __pcie_wait_link_active(ctrl, true);
249 static void pcie_wait_link_not_active(struct controller *ctrl)
251 __pcie_wait_link_active(ctrl, false);
254 static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
258 int delay = 1000, step = 20;
262 found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0);
272 if (count > 1 && pciehp_debug)
273 printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
274 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
275 PCI_FUNC(devfn), count, step, l);
280 int pciehp_check_link_status(struct controller *ctrl)
282 struct pci_dev *pdev = ctrl_dev(ctrl);
287 * Data Link Layer Link Active Reporting must be capable for
288 * hot-plug capable downstream port. But old controller might
289 * not implement it. In this case, we wait for 1000 ms.
291 if (ctrl->link_active_reporting)
292 pcie_wait_link_active(ctrl);
296 /* wait 100ms before read pci conf, and try in 1s */
298 found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
301 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
302 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
303 if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
304 !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
305 ctrl_err(ctrl, "Link Training Error occurs \n");
309 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
317 static int __pciehp_link_set(struct controller *ctrl, bool enable)
319 struct pci_dev *pdev = ctrl_dev(ctrl);
322 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl);
325 lnk_ctrl &= ~PCI_EXP_LNKCTL_LD;
327 lnk_ctrl |= PCI_EXP_LNKCTL_LD;
329 pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl);
330 ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl);
334 static int pciehp_link_enable(struct controller *ctrl)
336 return __pciehp_link_set(ctrl, true);
339 static int pciehp_link_disable(struct controller *ctrl)
341 return __pciehp_link_set(ctrl, false);
344 void pciehp_get_attention_status(struct slot *slot, u8 *status)
346 struct controller *ctrl = slot->ctrl;
347 struct pci_dev *pdev = ctrl_dev(ctrl);
351 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
352 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
353 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
355 atten_led_state = (slot_ctrl & PCI_EXP_SLTCTL_AIC) >> 6;
357 switch (atten_led_state) {
359 *status = 0xFF; /* Reserved */
362 *status = 1; /* On */
365 *status = 2; /* Blink */
368 *status = 0; /* Off */
376 void pciehp_get_power_status(struct slot *slot, u8 *status)
378 struct controller *ctrl = slot->ctrl;
379 struct pci_dev *pdev = ctrl_dev(ctrl);
383 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
384 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
385 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
387 pwr_state = (slot_ctrl & PCI_EXP_SLTCTL_PCC) >> 10;
402 void pciehp_get_latch_status(struct slot *slot, u8 *status)
404 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
407 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
408 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
411 void pciehp_get_adapter_status(struct slot *slot, u8 *status)
413 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
416 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
417 *status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
420 int pciehp_query_power_fault(struct slot *slot)
422 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
425 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
426 return !!(slot_status & PCI_EXP_SLTSTA_PFD);
429 void pciehp_set_attention_status(struct slot *slot, u8 value)
431 struct controller *ctrl = slot->ctrl;
435 cmd_mask = PCI_EXP_SLTCTL_AIC;
437 case 0 : /* turn off */
440 case 1: /* turn on */
443 case 2: /* turn blink */
449 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
450 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
451 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
454 void pciehp_green_led_on(struct slot *slot)
456 struct controller *ctrl = slot->ctrl;
461 cmd_mask = PCI_EXP_SLTCTL_PIC;
462 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
463 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
464 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
467 void pciehp_green_led_off(struct slot *slot)
469 struct controller *ctrl = slot->ctrl;
474 cmd_mask = PCI_EXP_SLTCTL_PIC;
475 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
476 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
477 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
480 void pciehp_green_led_blink(struct slot *slot)
482 struct controller *ctrl = slot->ctrl;
487 cmd_mask = PCI_EXP_SLTCTL_PIC;
488 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
489 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
490 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
493 int pciehp_power_on_slot(struct slot * slot)
495 struct controller *ctrl = slot->ctrl;
496 struct pci_dev *pdev = ctrl_dev(ctrl);
502 /* Clear sticky power-fault bit from previous power failures */
503 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
504 if (slot_status & PCI_EXP_SLTSTA_PFD)
505 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
507 ctrl->power_fault_detected = 0;
510 cmd_mask = PCI_EXP_SLTCTL_PCC;
511 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
512 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
513 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
515 retval = pciehp_link_enable(ctrl);
517 ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);
522 void pciehp_power_off_slot(struct slot * slot)
524 struct controller *ctrl = slot->ctrl;
528 /* Disable the link at first */
529 pciehp_link_disable(ctrl);
530 /* wait the link is down */
531 if (ctrl->link_active_reporting)
532 pcie_wait_link_not_active(ctrl);
536 slot_cmd = POWER_OFF;
537 cmd_mask = PCI_EXP_SLTCTL_PCC;
538 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
539 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
540 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
543 static irqreturn_t pcie_isr(int irq, void *dev_id)
545 struct controller *ctrl = (struct controller *)dev_id;
546 struct pci_dev *pdev = ctrl_dev(ctrl);
547 struct slot *slot = ctrl->slot;
548 u16 detected, intr_loc;
551 * In order to guarantee that all interrupt events are
552 * serviced, we need to re-inspect Slot Status register after
553 * clearing what is presumed to be the last pending interrupt.
557 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &detected);
559 detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
560 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
562 detected &= ~intr_loc;
563 intr_loc |= detected;
567 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
571 ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc);
573 /* Check Command Complete Interrupt Pending */
574 if (intr_loc & PCI_EXP_SLTSTA_CC) {
577 wake_up(&ctrl->queue);
580 if (!(intr_loc & ~PCI_EXP_SLTSTA_CC))
583 /* Check MRL Sensor Changed */
584 if (intr_loc & PCI_EXP_SLTSTA_MRLSC)
585 pciehp_handle_switch_change(slot);
587 /* Check Attention Button Pressed */
588 if (intr_loc & PCI_EXP_SLTSTA_ABP)
589 pciehp_handle_attention_button(slot);
591 /* Check Presence Detect Changed */
592 if (intr_loc & PCI_EXP_SLTSTA_PDC)
593 pciehp_handle_presence_change(slot);
595 /* Check Power Fault Detected */
596 if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
597 ctrl->power_fault_detected = 1;
598 pciehp_handle_power_fault(slot);
603 void pcie_enable_notification(struct controller *ctrl)
608 * TBD: Power fault detected software notification support.
610 * Power fault detected software notification is not enabled
611 * now, because it caused power fault detected interrupt storm
612 * on some machines. On those machines, power fault detected
613 * bit in the slot status register was set again immediately
614 * when it is cleared in the interrupt service routine, and
615 * next power fault detected interrupt was notified again.
617 cmd = PCI_EXP_SLTCTL_PDCE;
618 if (ATTN_BUTTN(ctrl))
619 cmd |= PCI_EXP_SLTCTL_ABPE;
621 cmd |= PCI_EXP_SLTCTL_MRLSCE;
622 if (!pciehp_poll_mode)
623 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
625 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
626 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
627 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE);
629 pcie_write_cmd(ctrl, cmd, mask);
632 static void pcie_disable_notification(struct controller *ctrl)
636 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
637 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
638 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
639 PCI_EXP_SLTCTL_DLLSCE);
640 pcie_write_cmd(ctrl, 0, mask);
644 * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary
645 * bus reset of the bridge, but if the slot supports surprise removal we need
646 * to disable presence detection around the bus reset and clear any spurious
649 int pciehp_reset_slot(struct slot *slot, int probe)
651 struct controller *ctrl = slot->ctrl;
652 struct pci_dev *pdev = ctrl_dev(ctrl);
657 if (HP_SUPR_RM(ctrl)) {
658 pcie_write_cmd(ctrl, 0, PCI_EXP_SLTCTL_PDCE);
659 if (pciehp_poll_mode)
660 del_timer_sync(&ctrl->poll_timer);
663 pci_reset_bridge_secondary_bus(ctrl->pcie->port);
665 if (HP_SUPR_RM(ctrl)) {
666 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
668 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PDCE, PCI_EXP_SLTCTL_PDCE);
669 if (pciehp_poll_mode)
670 int_poll_timeout(ctrl->poll_timer.data);
676 int pcie_init_notification(struct controller *ctrl)
678 if (pciehp_request_irq(ctrl))
680 pcie_enable_notification(ctrl);
681 ctrl->notification_enabled = 1;
685 static void pcie_shutdown_notification(struct controller *ctrl)
687 if (ctrl->notification_enabled) {
688 pcie_disable_notification(ctrl);
689 pciehp_free_irq(ctrl);
690 ctrl->notification_enabled = 0;
694 static int pcie_init_slot(struct controller *ctrl)
698 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
702 slot->wq = alloc_workqueue("pciehp-%u", 0, 0, PSN(ctrl));
707 mutex_init(&slot->lock);
708 INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
716 static void pcie_cleanup_slot(struct controller *ctrl)
718 struct slot *slot = ctrl->slot;
719 cancel_delayed_work(&slot->work);
720 destroy_workqueue(slot->wq);
724 static inline void dbg_ctrl(struct controller *ctrl)
728 struct pci_dev *pdev = ctrl->pcie->port;
733 ctrl_info(ctrl, "Hotplug Controller:\n");
734 ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n",
735 pci_name(pdev), pdev->irq);
736 ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor);
737 ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device);
738 ctrl_info(ctrl, " Subsystem ID : 0x%04x\n",
739 pdev->subsystem_device);
740 ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n",
741 pdev->subsystem_vendor);
742 ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n",
744 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
745 if (!pci_resource_len(pdev, i))
747 ctrl_info(ctrl, " PCI resource [%d] : %pR\n",
748 i, &pdev->resource[i]);
750 ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
751 ctrl_info(ctrl, " Physical Slot Number : %d\n", PSN(ctrl));
752 ctrl_info(ctrl, " Attention Button : %3s\n",
753 ATTN_BUTTN(ctrl) ? "yes" : "no");
754 ctrl_info(ctrl, " Power Controller : %3s\n",
755 POWER_CTRL(ctrl) ? "yes" : "no");
756 ctrl_info(ctrl, " MRL Sensor : %3s\n",
757 MRL_SENS(ctrl) ? "yes" : "no");
758 ctrl_info(ctrl, " Attention Indicator : %3s\n",
759 ATTN_LED(ctrl) ? "yes" : "no");
760 ctrl_info(ctrl, " Power Indicator : %3s\n",
761 PWR_LED(ctrl) ? "yes" : "no");
762 ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n",
763 HP_SUPR_RM(ctrl) ? "yes" : "no");
764 ctrl_info(ctrl, " EMI Present : %3s\n",
765 EMI(ctrl) ? "yes" : "no");
766 ctrl_info(ctrl, " Command Completed : %3s\n",
767 NO_CMD_CMPL(ctrl) ? "no" : "yes");
768 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, ®16);
769 ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16);
770 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, ®16);
771 ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16);
774 #define FLAG(x,y) (((x) & (y)) ? '+' : '-')
776 struct controller *pcie_init(struct pcie_device *dev)
778 struct controller *ctrl;
779 u32 slot_cap, link_cap;
780 struct pci_dev *pdev = dev->port;
782 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
784 dev_err(&dev->device, "%s: Out of memory\n", __func__);
788 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
789 ctrl->slot_cap = slot_cap;
790 mutex_init(&ctrl->ctrl_lock);
791 init_waitqueue_head(&ctrl->queue);
794 * Controller doesn't notify of command completion if the "No
795 * Command Completed Support" bit is set in Slot Capability
796 * register or the controller supports none of power
797 * controller, attention led, power led and EMI.
799 if (NO_CMD_CMPL(ctrl) ||
800 !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl)))
801 ctrl->no_cmd_complete = 1;
803 /* Check if Data Link Layer Link Active Reporting is implemented */
804 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap);
805 if (link_cap & PCI_EXP_LNKCAP_DLLLARC) {
806 ctrl_dbg(ctrl, "Link Active Reporting supported\n");
807 ctrl->link_active_reporting = 1;
810 /* Clear all remaining event bits in Slot Status register */
811 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, 0x1f);
813 /* Disable software notification */
814 pcie_disable_notification(ctrl);
816 ctrl_info(ctrl, "Slot #%d AttnBtn%c AttnInd%c PwrInd%c PwrCtrl%c MRL%c Interlock%c NoCompl%c LLActRep%c\n",
817 (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19,
818 FLAG(slot_cap, PCI_EXP_SLTCAP_ABP),
819 FLAG(slot_cap, PCI_EXP_SLTCAP_AIP),
820 FLAG(slot_cap, PCI_EXP_SLTCAP_PIP),
821 FLAG(slot_cap, PCI_EXP_SLTCAP_PCP),
822 FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP),
823 FLAG(slot_cap, PCI_EXP_SLTCAP_EIP),
824 FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS),
825 FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC));
827 if (pcie_init_slot(ctrl))
838 void pciehp_release_ctrl(struct controller *ctrl)
840 pcie_shutdown_notification(ctrl);
841 pcie_cleanup_slot(ctrl);