Pileus Git - ~andy/linux/blob - drivers/net/wireless/wl12xx/boot.c

   1 /*
   2  * This file is part of wl1271
   3  *
   4  * Copyright (C) 2008-2010 Nokia Corporation
   5  *
   6  * Contact: Luciano Coelho <luciano.coelho@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20  * 02110-1301 USA
  21  *
  22  */
  23
  24 #include <linux/slab.h>
  25 #include <linux/wl12xx.h>
  26
  27 #include "acx.h"
  28 #include "reg.h"
  29 #include "boot.h"
  30 #include "io.h"
  31 #include "event.h"
  32 #include "rx.h"
  33
  34 static struct wl1271_partition_set part_table[PART_TABLE_LEN] = {
  35         [PART_DOWN] = {
  36                 .mem = {
  37                         .start = 0x00000000,
  38                         .size  = 0x000177c0
  39                 },
  40                 .reg = {
  41                         .start = REGISTERS_BASE,
  42                         .size  = 0x00008800
  43                 },
  44                 .mem2 = {
  45                         .start = 0x00000000,
  46                         .size  = 0x00000000
  47                 },
  48                 .mem3 = {
  49                         .start = 0x00000000,
  50                         .size  = 0x00000000
  51                 },
  52         },
  53
  54         [PART_WORK] = {
  55                 .mem = {
  56                         .start = 0x00040000,
  57                         .size  = 0x00014fc0
  58                 },
  59                 .reg = {
  60                         .start = REGISTERS_BASE,
  61                         .size  = 0x0000a000
  62                 },
  63                 .mem2 = {
  64                         .start = 0x003004f8,
  65                         .size  = 0x00000004
  66                 },
  67                 .mem3 = {
  68                         .start = 0x00040404,
  69                         .size  = 0x00000000
  70                 },
  71         },
  72
  73         [PART_DRPW] = {
  74                 .mem = {
  75                         .start = 0x00040000,
  76                         .size  = 0x00014fc0
  77                 },
  78                 .reg = {
  79                         .start = DRPW_BASE,
  80                         .size  = 0x00006000
  81                 },
  82                 .mem2 = {
  83                         .start = 0x00000000,
  84                         .size  = 0x00000000
  85                 },
  86                 .mem3 = {
  87                         .start = 0x00000000,
  88                         .size  = 0x00000000
  89                 }
  90         }
  91 };
  92
  93 static void wl1271_boot_set_ecpu_ctrl(struct wl1271 *wl, u32 flag)
  94 {
  95         u32 cpu_ctrl;
  96
  97         /* 10.5.0 run the firmware (I) */
  98         cpu_ctrl = wl1271_read32(wl, ACX_REG_ECPU_CONTROL);
  99
 100         /* 10.5.1 run the firmware (II) */
 101         cpu_ctrl |= flag;
 102         wl1271_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
 103 }
 104
 105 static void wl1271_parse_fw_ver(struct wl1271 *wl)
 106 {
 107         int ret;
 108
 109         ret = sscanf(wl->chip.fw_ver_str + 4, "%u.%u.%u.%u.%u",
 110                      &wl->chip.fw_ver[0], &wl->chip.fw_ver[1],
 111                      &wl->chip.fw_ver[2], &wl->chip.fw_ver[3],
 112                      &wl->chip.fw_ver[4]);
 113
 114         if (ret != 5) {
 115                 wl1271_warning("fw version incorrect value");
 116                 memset(wl->chip.fw_ver, 0, sizeof(wl->chip.fw_ver));
 117                 return;
 118         }
 119 }
 120
 121 static void wl1271_boot_fw_version(struct wl1271 *wl)
 122 {
 123         struct wl1271_static_data static_data;
 124
 125         wl1271_read(wl, wl->cmd_box_addr, &static_data, sizeof(static_data),
 126                     false);
 127
 128         strncpy(wl->chip.fw_ver_str, static_data.fw_version,
 129                 sizeof(wl->chip.fw_ver_str));
 130
 131         /* make sure the string is NULL-terminated */
 132         wl->chip.fw_ver_str[sizeof(wl->chip.fw_ver_str) - 1] = '\0';
 133
 134         wl1271_parse_fw_ver(wl);
 135 }
 136
 137 static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf,
 138                                              size_t fw_data_len, u32 dest)
 139 {
 140         struct wl1271_partition_set partition;
 141         int addr, chunk_num, partition_limit;
 142         u8 *p, *chunk;
 143
 144         /* whal_FwCtrl_LoadFwImageSm() */
 145
 146         wl1271_debug(DEBUG_BOOT, "starting firmware upload");
 147
 148         wl1271_debug(DEBUG_BOOT, "fw_data_len %zd chunk_size %d",
 149                      fw_data_len, CHUNK_SIZE);
 150
 151         if ((fw_data_len % 4) != 0) {
 152                 wl1271_error("firmware length not multiple of four");
 153                 return -EIO;
 154         }
 155
 156         chunk = kmalloc(CHUNK_SIZE, GFP_KERNEL);
 157         if (!chunk) {
 158                 wl1271_error("allocation for firmware upload chunk failed");
 159                 return -ENOMEM;
 160         }
 161
 162         memcpy(&partition, &part_table[PART_DOWN], sizeof(partition));
 163         partition.mem.start = dest;
 164         wl1271_set_partition(wl, &partition);
 165
 166         /* 10.1 set partition limit and chunk num */
 167         chunk_num = 0;
 168         partition_limit = part_table[PART_DOWN].mem.size;
 169
 170         while (chunk_num < fw_data_len / CHUNK_SIZE) {
 171                 /* 10.2 update partition, if needed */
 172                 addr = dest + (chunk_num + 2) * CHUNK_SIZE;
 173                 if (addr > partition_limit) {
 174                         addr = dest + chunk_num * CHUNK_SIZE;
 175                         partition_limit = chunk_num * CHUNK_SIZE +
 176                                 part_table[PART_DOWN].mem.size;
 177                         partition.mem.start = addr;
 178                         wl1271_set_partition(wl, &partition);
 179                 }
 180
 181                 /* 10.3 upload the chunk */
 182                 addr = dest + chunk_num * CHUNK_SIZE;
 183                 p = buf + chunk_num * CHUNK_SIZE;
 184                 memcpy(chunk, p, CHUNK_SIZE);
 185                 wl1271_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
 186                              p, addr);
 187                 wl1271_write(wl, addr, chunk, CHUNK_SIZE, false);
 188
 189                 chunk_num++;
 190         }
 191
 192         /* 10.4 upload the last chunk */
 193         addr = dest + chunk_num * CHUNK_SIZE;
 194         p = buf + chunk_num * CHUNK_SIZE;
 195         memcpy(chunk, p, fw_data_len % CHUNK_SIZE);
 196         wl1271_debug(DEBUG_BOOT, "uploading fw last chunk (%zd B) 0x%p to 0x%x",
 197                      fw_data_len % CHUNK_SIZE, p, addr);
 198         wl1271_write(wl, addr, chunk, fw_data_len % CHUNK_SIZE, false);
 199
 200         kfree(chunk);
 201         return 0;
 202 }
 203
 204 static int wl1271_boot_upload_firmware(struct wl1271 *wl)
 205 {
 206         u32 chunks, addr, len;
 207         int ret = 0;
 208         u8 *fw;
 209
 210         fw = wl->fw;
 211         chunks = be32_to_cpup((__be32 *) fw);
 212         fw += sizeof(u32);
 213
 214         wl1271_debug(DEBUG_BOOT, "firmware chunks to be uploaded: %u", chunks);
 215
 216         while (chunks--) {
 217                 addr = be32_to_cpup((__be32 *) fw);
 218                 fw += sizeof(u32);
 219                 len = be32_to_cpup((__be32 *) fw);
 220                 fw += sizeof(u32);
 221
 222                 if (len > 300000) {
 223                         wl1271_info("firmware chunk too long: %u", len);
 224                         return -EINVAL;
 225                 }
 226                 wl1271_debug(DEBUG_BOOT, "chunk %d addr 0x%x len %u",
 227                              chunks, addr, len);
 228                 ret = wl1271_boot_upload_firmware_chunk(wl, fw, len, addr);
 229                 if (ret != 0)
 230                         break;
 231                 fw += len;
 232         }
 233
 234         return ret;
 235 }
 236
 237 static int wl1271_boot_upload_nvs(struct wl1271 *wl)
 238 {
 239         size_t nvs_len, burst_len;
 240         int i;
 241         u32 dest_addr, val;
 242         u8 *nvs_ptr, *nvs_aligned;
 243
 244         if (wl->nvs == NULL)
 245                 return -ENODEV;
 246
 247         if (wl->chip.id == CHIP_ID_1283_PG20) {
 248                 struct wl128x_nvs_file *nvs = (struct wl128x_nvs_file *)wl->nvs;
 249
 250                 if (wl->nvs_len == sizeof(struct wl128x_nvs_file)) {
 251                         if (nvs->general_params.dual_mode_select)
 252                                 wl->enable_11a = true;
 253                 } else {
 254                         wl1271_error("nvs size is not as expected: %zu != %zu",
 255                                      wl->nvs_len,
 256                                      sizeof(struct wl128x_nvs_file));
 257                         kfree(wl->nvs);
 258                         wl->nvs = NULL;
 259                         wl->nvs_len = 0;
 260                         return -EILSEQ;
 261                 }
 262
 263                 /* only the first part of the NVS needs to be uploaded */
 264                 nvs_len = sizeof(nvs->nvs);
 265                 nvs_ptr = (u8 *)nvs->nvs;
 266
 267         } else {
 268                 struct wl1271_nvs_file *nvs =
 269                         (struct wl1271_nvs_file *)wl->nvs;
 270                 /*
 271                  * FIXME: the LEGACY NVS image support (NVS's missing the 5GHz
 272                  * band configurations) can be removed when those NVS files stop
 273                  * floating around.
 274                  */
 275                 if (wl->nvs_len == sizeof(struct wl1271_nvs_file) ||
 276                     wl->nvs_len == WL1271_INI_LEGACY_NVS_FILE_SIZE) {
 277                         /* for now 11a is unsupported in AP mode */
 278                         if (wl->bss_type != BSS_TYPE_AP_BSS &&
 279                             nvs->general_params.dual_mode_select)
 280                                 wl->enable_11a = true;
 281                 }
 282
 283                 if (wl->nvs_len != sizeof(struct wl1271_nvs_file) &&
 284                     (wl->nvs_len != WL1271_INI_LEGACY_NVS_FILE_SIZE ||
 285                      wl->enable_11a)) {
 286                         wl1271_error("nvs size is not as expected: %zu != %zu",
 287                                 wl->nvs_len, sizeof(struct wl1271_nvs_file));
 288                         kfree(wl->nvs);
 289                         wl->nvs = NULL;
 290                         wl->nvs_len = 0;
 291                         return -EILSEQ;
 292                 }
 293
 294                 /* only the first part of the NVS needs to be uploaded */
 295                 nvs_len = sizeof(nvs->nvs);
 296                 nvs_ptr = (u8 *) nvs->nvs;
 297         }
 298
 299         /* update current MAC address to NVS */
 300         nvs_ptr[11] = wl->mac_addr[0];
 301         nvs_ptr[10] = wl->mac_addr[1];
 302         nvs_ptr[6] = wl->mac_addr[2];
 303         nvs_ptr[5] = wl->mac_addr[3];
 304         nvs_ptr[4] = wl->mac_addr[4];
 305         nvs_ptr[3] = wl->mac_addr[5];
 306
 307         /*
 308          * Layout before the actual NVS tables:
 309          * 1 byte : burst length.
 310          * 2 bytes: destination address.
 311          * n bytes: data to burst copy.
 312          *
 313          * This is ended by a 0 length, then the NVS tables.
 314          */
 315
 316         /* FIXME: Do we need to check here whether the LSB is 1? */
 317         while (nvs_ptr[0]) {
 318                 burst_len = nvs_ptr[0];
 319                 dest_addr = (nvs_ptr[1] & 0xfe) | ((u32)(nvs_ptr[2] << 8));
 320
 321                 /*
 322                  * Due to our new wl1271_translate_reg_addr function,
 323                  * we need to add the REGISTER_BASE to the destination
 324                  */
 325                 dest_addr += REGISTERS_BASE;
 326
 327                 /* We move our pointer to the data */
 328                 nvs_ptr += 3;
 329
 330                 for (i = 0; i < burst_len; i++) {
 331                         val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
 332                                | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));
 333
 334                         wl1271_debug(DEBUG_BOOT,
 335                                      "nvs burst write 0x%x: 0x%x",
 336                                      dest_addr, val);
 337                         wl1271_write32(wl, dest_addr, val);
 338
 339                         nvs_ptr += 4;
 340                         dest_addr += 4;
 341                 }
 342         }
 343
 344         /*
 345          * We've reached the first zero length, the first NVS table
 346          * is located at an aligned offset which is at least 7 bytes further.
 347          * NOTE: The wl->nvs->nvs element must be first, in order to
 348          * simplify the casting, we assume it is at the beginning of
 349          * the wl->nvs structure.
 350          */
 351         nvs_ptr = (u8 *)wl->nvs +
 352                         ALIGN(nvs_ptr - (u8 *)wl->nvs + 7, 4);
 353         nvs_len -= nvs_ptr - (u8 *)wl->nvs;
 354
 355         /* Now we must set the partition correctly */
 356         wl1271_set_partition(wl, &part_table[PART_WORK]);
 357
 358         /* Copy the NVS tables to a new block to ensure alignment */
 359         nvs_aligned = kmemdup(nvs_ptr, nvs_len, GFP_KERNEL);
 360         if (!nvs_aligned)
 361                 return -ENOMEM;
 362
 363         /* And finally we upload the NVS tables */
 364         wl1271_write(wl, CMD_MBOX_ADDRESS, nvs_aligned, nvs_len, false);
 365
 366         kfree(nvs_aligned);
 367         return 0;
 368 }
 369
 370 static void wl1271_boot_enable_interrupts(struct wl1271 *wl)
 371 {
 372         wl1271_enable_interrupts(wl);
 373         wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
 374                        WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
 375         wl1271_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
 376 }
 377
 378 static int wl1271_boot_soft_reset(struct wl1271 *wl)
 379 {
 380         unsigned long timeout;
 381         u32 boot_data;
 382
 383         /* perform soft reset */
 384         wl1271_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
 385
 386         /* SOFT_RESET is self clearing */
 387         timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
 388         while (1) {
 389                 boot_data = wl1271_read32(wl, ACX_REG_SLV_SOFT_RESET);
 390                 wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
 391                 if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
 392                         break;
 393
 394                 if (time_after(jiffies, timeout)) {
 395                         /* 1.2 check pWhalBus->uSelfClearTime if the
 396                          * timeout was reached */
 397                         wl1271_error("soft reset timeout");
 398                         return -1;
 399                 }
 400
 401                 udelay(SOFT_RESET_STALL_TIME);
 402         }
 403
 404         /* disable Rx/Tx */
 405         wl1271_write32(wl, ENABLE, 0x0);
 406
 407         /* disable auto calibration on start*/
 408         wl1271_write32(wl, SPARE_A2, 0xffff);
 409
 410         return 0;
 411 }
 412
 413 static int wl1271_boot_run_firmware(struct wl1271 *wl)
 414 {
 415         int loop, ret;
 416         u32 chip_id, intr;
 417
 418         wl1271_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);
 419
 420         chip_id = wl1271_read32(wl, CHIP_ID_B);
 421
 422         wl1271_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);
 423
 424         if (chip_id != wl->chip.id) {
 425                 wl1271_error("chip id doesn't match after firmware boot");
 426                 return -EIO;
 427         }
 428
 429         /* wait for init to complete */
 430         loop = 0;
 431         while (loop++ < INIT_LOOP) {
 432                 udelay(INIT_LOOP_DELAY);
 433                 intr = wl1271_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
 434
 435                 if (intr == 0xffffffff) {
 436                         wl1271_error("error reading hardware complete "
 437                                      "init indication");
 438                         return -EIO;
 439                 }
 440                 /* check that ACX_INTR_INIT_COMPLETE is enabled */
 441                 else if (intr & WL1271_ACX_INTR_INIT_COMPLETE) {
 442                         wl1271_write32(wl, ACX_REG_INTERRUPT_ACK,
 443                                        WL1271_ACX_INTR_INIT_COMPLETE);
 444                         break;
 445                 }
 446         }
 447
 448         if (loop > INIT_LOOP) {
 449                 wl1271_error("timeout waiting for the hardware to "
 450                              "complete initialization");
 451                 return -EIO;
 452         }
 453
 454         /* get hardware config command mail box */
 455         wl->cmd_box_addr = wl1271_read32(wl, REG_COMMAND_MAILBOX_PTR);
 456
 457         /* get hardware config event mail box */
 458         wl->event_box_addr = wl1271_read32(wl, REG_EVENT_MAILBOX_PTR);
 459
 460         /* set the working partition to its "running" mode offset */
 461         wl1271_set_partition(wl, &part_table[PART_WORK]);
 462
 463         wl1271_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x",
 464                      wl->cmd_box_addr, wl->event_box_addr);
 465
 466         wl1271_boot_fw_version(wl);
 467
 468         /*
 469          * in case of full asynchronous mode the firmware event must be
 470          * ready to receive event from the command mailbox
 471          */
 472
 473         /* unmask required mbox events  */
 474         wl->event_mask = BSS_LOSE_EVENT_ID |
 475                 SCAN_COMPLETE_EVENT_ID |
 476                 PS_REPORT_EVENT_ID |
 477                 JOIN_EVENT_COMPLETE_ID |
 478                 DISCONNECT_EVENT_COMPLETE_ID |
 479                 RSSI_SNR_TRIGGER_0_EVENT_ID |
 480                 PSPOLL_DELIVERY_FAILURE_EVENT_ID |
 481                 SOFT_GEMINI_SENSE_EVENT_ID;
 482
 483         if (wl->bss_type == BSS_TYPE_AP_BSS)
 484                 wl->event_mask |= STA_REMOVE_COMPLETE_EVENT_ID;
 485
 486         ret = wl1271_event_unmask(wl);
 487         if (ret < 0) {
 488                 wl1271_error("EVENT mask setting failed");
 489                 return ret;
 490         }
 491
 492         wl1271_event_mbox_config(wl);
 493
 494         /* firmware startup completed */
 495         return 0;
 496 }
 497
 498 static int wl1271_boot_write_irq_polarity(struct wl1271 *wl)
 499 {
 500         u32 polarity;
 501
 502         polarity = wl1271_top_reg_read(wl, OCP_REG_POLARITY);
 503
 504         /* We use HIGH polarity, so unset the LOW bit */
 505         polarity &= ~POLARITY_LOW;
 506         wl1271_top_reg_write(wl, OCP_REG_POLARITY, polarity);
 507
 508         return 0;
 509 }
 510
 511 static void wl1271_boot_hw_version(struct wl1271 *wl)
 512 {
 513         u32 fuse;
 514
 515         fuse = wl1271_top_reg_read(wl, REG_FUSE_DATA_2_1);
 516         fuse = (fuse & PG_VER_MASK) >> PG_VER_OFFSET;
 517
 518         wl->hw_pg_ver = (s8)fuse;
 519
 520         if (((wl->hw_pg_ver & PG_MAJOR_VER_MASK) >> PG_MAJOR_VER_OFFSET) < 3)
 521                 wl->quirks |= WL12XX_QUIRK_END_OF_TRANSACTION;
 522 }
 523
 524 /*
 525  * WL128x has two clocks input - TCXO and FREF.
 526  * TCXO is the main clock of the device, while FREF is used to sync
 527  * between the GPS and the cellular modem.
 528  * In cases where TCXO is 32.736MHz or 16.368MHz, the FREF will be used
 529  * as the WLAN/BT main clock.
 530  */
 531 static int wl128x_switch_fref(struct wl1271 *wl, bool *is_ref_clk)
 532 {
 533         u16 sys_clk_cfg_val;
 534
 535         /* if working on XTAL-only mode go directly to TCXO TO FREF SWITCH */
 536         if ((wl->ref_clock == CONF_REF_CLK_38_4_M_XTAL) ||
 537             (wl->ref_clock == CONF_REF_CLK_26_M_XTAL))
 538                 return true;
 539
 540         /* Read clock source FREF or TCXO */
 541         sys_clk_cfg_val = wl1271_top_reg_read(wl, SYS_CLK_CFG_REG);
 542
 543         if (sys_clk_cfg_val & PRCM_CM_EN_MUX_WLAN_FREF) {
 544                 /* if bit 3 is set - working with FREF clock */
 545                 wl1271_debug(DEBUG_BOOT, "working with FREF clock, skip"
 546                              " to FREF");
 547
 548                 *is_ref_clk = true;
 549         } else {
 550                 /* if bit 3 is clear - working with TCXO clock */
 551                 wl1271_debug(DEBUG_BOOT, "working with TCXO clock");
 552
 553                 /* TCXO to FREF switch, check TXCO clock config */
 554                 if ((wl->tcxo_clock != WL12XX_TCXOCLOCK_16_368) &&
 555                     (wl->tcxo_clock != WL12XX_TCXOCLOCK_32_736)) {
 556                         /*
 557                          * not 16.368Mhz and not 32.736Mhz - skip to
 558                          * configure ELP stage
 559                          */
 560                         wl1271_debug(DEBUG_BOOT, "NEW PLL ALGO:"
 561                                      " TcxoRefClk=%d - not 16.368Mhz and not"
 562                                      " 32.736Mhz - skip to configure ELP"
 563                                      " stage", wl->tcxo_clock);
 564
 565                         *is_ref_clk = false;
 566                 } else {
 567                         wl1271_debug(DEBUG_BOOT, "NEW PLL ALGO:"
 568                                      "TcxoRefClk=%d - 16.368Mhz or 32.736Mhz"
 569                                      " - TCXO to FREF switch",
 570                                      wl->tcxo_clock);
 571
 572                         return true;
 573                 }
 574         }
 575
 576         return false;
 577 }
 578
 579 static int wl128x_boot_clk(struct wl1271 *wl, bool *is_ref_clk)
 580 {
 581         if (wl128x_switch_fref(wl, is_ref_clk)) {
 582                 wl1271_debug(DEBUG_BOOT, "XTAL-only mode go directly to"
 583                                          " TCXO TO FREF SWITCH");
 584                 /* TCXO to FREF switch - for PG2.0 */
 585                 wl1271_top_reg_write(wl, WL_SPARE_REG,
 586                                      WL_SPARE_MASK_8526);
 587
 588                 wl1271_top_reg_write(wl, SYS_CLK_CFG_REG,
 589                         WL_CLK_REQ_TYPE_PG2 | MCS_PLL_CLK_SEL_FREF);
 590
 591                 *is_ref_clk = true;
 592                 mdelay(15);
 593         }
 594
 595         /* Set bit 2 in spare register to avoid illegal access */
 596         wl1271_top_reg_write(wl, WL_SPARE_REG, WL_SPARE_VAL);
 597
 598         /* working with TCXO clock */
 599         if ((*is_ref_clk == false) &&
 600             ((wl->tcxo_clock == WL12XX_TCXOCLOCK_16_8) ||
 601              (wl->tcxo_clock == WL12XX_TCXOCLOCK_33_6))) {
 602                 wl1271_debug(DEBUG_BOOT, "16_8_M or 33_6_M TCXO detected");
 603
 604                 /* Manually Configure MCS PLL settings PG2.0 Only */
 605                 wl1271_top_reg_write(wl, MCS_PLL_M_REG, MCS_PLL_M_REG_VAL);
 606                 wl1271_top_reg_write(wl, MCS_PLL_N_REG, MCS_PLL_N_REG_VAL);
 607                 wl1271_top_reg_write(wl, MCS_PLL_CONFIG_REG,
 608                                      MCS_PLL_CONFIG_REG_VAL);
 609         } else {
 610                 int pll_config;
 611                 u16 mcs_pll_config_val;
 612
 613                 /*
 614                  * Configure MCS PLL settings to FREF Freq
 615                  * Set the values that determine the time elapse since the PLL's
 616                  * get their enable signal until the lock indication is set
 617                  */
 618                 wl1271_top_reg_write(wl, PLL_LOCK_COUNTERS_REG,
 619                         PLL_LOCK_COUNTERS_COEX | PLL_LOCK_COUNTERS_MCS);
 620
 621                 mcs_pll_config_val = wl1271_top_reg_read(wl,
 622                                                  MCS_PLL_CONFIG_REG);
 623                 /*
 624                  * Set the MCS PLL input frequency value according to the
 625                  * reference clock value detected/read
 626                  */
 627                 if (*is_ref_clk == false) {
 628                         if ((wl->tcxo_clock == WL12XX_TCXOCLOCK_19_2) ||
 629                             (wl->tcxo_clock == WL12XX_TCXOCLOCK_38_4))
 630                                 pll_config = 1;
 631                         else if ((wl->tcxo_clock == WL12XX_TCXOCLOCK_26)
 632                                  ||
 633                                  (wl->tcxo_clock == WL12XX_TCXOCLOCK_52))
 634                                 pll_config = 2;
 635                         else
 636                                 return -EINVAL;
 637                 } else {
 638                         if ((wl->ref_clock == CONF_REF_CLK_19_2_E) ||
 639                             (wl->ref_clock == CONF_REF_CLK_38_4_E))
 640                                 pll_config = 1;
 641                         else if ((wl->ref_clock == CONF_REF_CLK_26_E) ||
 642                                  (wl->ref_clock == CONF_REF_CLK_52_E))
 643                                 pll_config = 2;
 644                         else
 645                                 return -EINVAL;
 646                 }
 647
 648                 mcs_pll_config_val |= (pll_config << (MCS_SEL_IN_FREQ_SHIFT)) &
 649                                       (MCS_SEL_IN_FREQ_MASK);
 650                 wl1271_top_reg_write(wl, MCS_PLL_CONFIG_REG,
 651                                      mcs_pll_config_val);
 652         }
 653
 654         return 0;
 655 }
 656
 657 static int wl127x_boot_clk(struct wl1271 *wl)
 658 {
 659         u32 pause;
 660         u32 clk;
 661
 662         wl1271_boot_hw_version(wl);
 663
 664         if (wl->ref_clock == CONF_REF_CLK_19_2_E ||
 665             wl->ref_clock == CONF_REF_CLK_38_4_E ||
 666             wl->ref_clock == CONF_REF_CLK_38_4_M_XTAL)
 667                 /* ref clk: 19.2/38.4/38.4-XTAL */
 668                 clk = 0x3;
 669         else if (wl->ref_clock == CONF_REF_CLK_26_E ||
 670                  wl->ref_clock == CONF_REF_CLK_52_E)
 671                 /* ref clk: 26/52 */
 672                 clk = 0x5;
 673         else
 674                 return -EINVAL;
 675
 676         if (wl->ref_clock != CONF_REF_CLK_19_2_E) {
 677                 u16 val;
 678                 /* Set clock type (open drain) */
 679                 val = wl1271_top_reg_read(wl, OCP_REG_CLK_TYPE);
 680                 val &= FREF_CLK_TYPE_BITS;
 681                 wl1271_top_reg_write(wl, OCP_REG_CLK_TYPE, val);
 682
 683                 /* Set clock pull mode (no pull) */
 684                 val = wl1271_top_reg_read(wl, OCP_REG_CLK_PULL);
 685                 val |= NO_PULL;
 686                 wl1271_top_reg_write(wl, OCP_REG_CLK_PULL, val);
 687         } else {
 688                 u16 val;
 689                 /* Set clock polarity */
 690                 val = wl1271_top_reg_read(wl, OCP_REG_CLK_POLARITY);
 691                 val &= FREF_CLK_POLARITY_BITS;
 692                 val |= CLK_REQ_OUTN_SEL;
 693                 wl1271_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
 694         }
 695
 696         wl1271_write32(wl, PLL_PARAMETERS, clk);
 697
 698         pause = wl1271_read32(wl, PLL_PARAMETERS);
 699
 700         wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);
 701
 702         pause &= ~(WU_COUNTER_PAUSE_VAL);
 703         pause |= WU_COUNTER_PAUSE_VAL;
 704         wl1271_write32(wl, WU_COUNTER_PAUSE, pause);
 705
 706         return 0;
 707 }
 708
 709 /* uploads NVS and firmware */
 710 int wl1271_load_firmware(struct wl1271 *wl)
 711 {
 712         int ret = 0;
 713         u32 tmp, clk;
 714         bool is_ref_clk = false;
 715
 716         if (wl->chip.id == CHIP_ID_1283_PG20) {
 717                 ret = wl128x_boot_clk(wl, &is_ref_clk);
 718                 if (ret < 0)
 719                         goto out;
 720         } else {
 721                 ret = wl127x_boot_clk(wl);
 722                 if (ret < 0)
 723                         goto out;
 724         }
 725
 726         /* Continue the ELP wake up sequence */
 727         wl1271_write32(wl, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
 728         udelay(500);
 729
 730         wl1271_set_partition(wl, &part_table[PART_DRPW]);
 731
 732         /* Read-modify-write DRPW_SCRATCH_START register (see next state)
 733            to be used by DRPw FW. The RTRIM value will be added by the FW
 734            before taking DRPw out of reset */
 735
 736         wl1271_debug(DEBUG_BOOT, "DRPW_SCRATCH_START %08x", DRPW_SCRATCH_START);
 737         clk = wl1271_read32(wl, DRPW_SCRATCH_START);
 738
 739         wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
 740
 741         if (wl->chip.id == CHIP_ID_1283_PG20) {
 742                 if (is_ref_clk == false)
 743                         clk |= ((wl->tcxo_clock & 0x3) << 1) << 4;
 744                 else
 745                         clk |= ((wl->ref_clock & 0x3) << 1) << 4;
 746         } else {
 747                 clk |= (wl->ref_clock << 1) << 4;
 748         }
 749
 750         wl1271_write32(wl, DRPW_SCRATCH_START, clk);
 751
 752         wl1271_set_partition(wl, &part_table[PART_WORK]);
 753
 754         /* Disable interrupts */
 755         wl1271_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
 756
 757         ret = wl1271_boot_soft_reset(wl);
 758         if (ret < 0)
 759                 goto out;
 760
 761         /* 2. start processing NVS file */
 762         ret = wl1271_boot_upload_nvs(wl);
 763         if (ret < 0)
 764                 goto out;
 765
 766         /* write firmware's last address (ie. it's length) to
 767          * ACX_EEPROMLESS_IND_REG */
 768         wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");
 769
 770         wl1271_write32(wl, ACX_EEPROMLESS_IND_REG, ACX_EEPROMLESS_IND_REG);
 771
 772         tmp = wl1271_read32(wl, CHIP_ID_B);
 773
 774         wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
 775
 776         /* 6. read the EEPROM parameters */
 777         tmp = wl1271_read32(wl, SCR_PAD2);
 778
 779         /* WL1271: The reference driver skips steps 7 to 10 (jumps directly
 780          * to upload_fw) */
 781
 782         if (wl->chip.id == CHIP_ID_1283_PG20)
 783                 wl1271_top_reg_write(wl, SDIO_IO_DS, HCI_IO_DS_6MA);
 784
 785         ret = wl1271_boot_upload_firmware(wl);
 786         if (ret < 0)
 787                 goto out;
 788
 789 out:
 790         return ret;
 791 }
 792 EXPORT_SYMBOL_GPL(wl1271_load_firmware);
 793
 794 int wl1271_boot(struct wl1271 *wl)
 795 {
 796         int ret;
 797
 798         /* upload NVS and firmware */
 799         ret = wl1271_load_firmware(wl);
 800         if (ret)
 801                 return ret;
 802
 803         /* 10.5 start firmware */
 804         ret = wl1271_boot_run_firmware(wl);
 805         if (ret < 0)
 806                 goto out;
 807
 808         ret = wl1271_boot_write_irq_polarity(wl);
 809         if (ret < 0)
 810                 goto out;
 811
 812         wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
 813                        WL1271_ACX_ALL_EVENTS_VECTOR);
 814
 815         /* Enable firmware interrupts now */
 816         wl1271_boot_enable_interrupts(wl);
 817
 818         /* set the wl1271 default filters */
 819         wl1271_set_default_filters(wl);
 820
 821         wl1271_event_mbox_config(wl);
 822
 823 out:
 824         return ret;
 825 }