2 * This file is part of wlcore
4 * Copyright (C) 2011 Texas Instruments Inc.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
25 #include <linux/platform_device.h>
31 /* The maximum number of Tx descriptors in all chip families */
32 #define WLCORE_MAX_TX_DESCRIPTORS 32
35 * We always allocate this number of mac addresses. If we don't
36 * have enough allocated addresses, the LAA bit is used
38 #define WLCORE_NUM_MAC_ADDRESSES 3
40 /* forward declaration */
41 struct wl1271_tx_hw_descr;
43 struct wl1271_rx_descriptor;
46 int (*setup)(struct wl1271 *wl);
47 int (*identify_chip)(struct wl1271 *wl);
48 int (*identify_fw)(struct wl1271 *wl);
49 int (*boot)(struct wl1271 *wl);
50 int (*plt_init)(struct wl1271 *wl);
51 int (*trigger_cmd)(struct wl1271 *wl, int cmd_box_addr,
52 void *buf, size_t len);
53 int (*ack_event)(struct wl1271 *wl);
54 u32 (*calc_tx_blocks)(struct wl1271 *wl, u32 len, u32 spare_blks);
55 void (*set_tx_desc_blocks)(struct wl1271 *wl,
56 struct wl1271_tx_hw_descr *desc,
57 u32 blks, u32 spare_blks);
58 void (*set_tx_desc_data_len)(struct wl1271 *wl,
59 struct wl1271_tx_hw_descr *desc,
61 enum wl_rx_buf_align (*get_rx_buf_align)(struct wl1271 *wl,
63 int (*prepare_read)(struct wl1271 *wl, u32 rx_desc, u32 len);
64 u32 (*get_rx_packet_len)(struct wl1271 *wl, void *rx_data,
66 int (*tx_delayed_compl)(struct wl1271 *wl);
67 void (*tx_immediate_compl)(struct wl1271 *wl);
68 int (*hw_init)(struct wl1271 *wl);
69 int (*init_vif)(struct wl1271 *wl, struct wl12xx_vif *wlvif);
70 u32 (*sta_get_ap_rate_mask)(struct wl1271 *wl,
71 struct wl12xx_vif *wlvif);
72 int (*get_pg_ver)(struct wl1271 *wl, s8 *ver);
73 int (*get_mac)(struct wl1271 *wl);
74 void (*set_tx_desc_csum)(struct wl1271 *wl,
75 struct wl1271_tx_hw_descr *desc,
77 void (*set_rx_csum)(struct wl1271 *wl,
78 struct wl1271_rx_descriptor *desc,
80 u32 (*ap_get_mimo_wide_rate_mask)(struct wl1271 *wl,
81 struct wl12xx_vif *wlvif);
82 int (*debugfs_init)(struct wl1271 *wl, struct dentry *rootdir);
83 int (*handle_static_data)(struct wl1271 *wl,
84 struct wl1271_static_data *static_data);
85 int (*get_spare_blocks)(struct wl1271 *wl, bool is_gem);
86 int (*set_key)(struct wl1271 *wl, enum set_key_cmd cmd,
87 struct ieee80211_vif *vif,
88 struct ieee80211_sta *sta,
89 struct ieee80211_key_conf *key_conf);
90 u32 (*pre_pkt_send)(struct wl1271 *wl, u32 buf_offset, u32 last_len);
93 enum wlcore_partitions {
98 PART_TOP_PRCM_ELP_SOC,
104 struct wlcore_partition {
109 struct wlcore_partition_set {
110 struct wlcore_partition mem;
111 struct wlcore_partition reg;
112 struct wlcore_partition mem2;
113 struct wlcore_partition mem3;
116 enum wlcore_registers {
117 /* register addresses, used with partition translation */
119 REG_INTERRUPT_NO_CLEAR,
121 REG_COMMAND_MAILBOX_PTR,
122 REG_EVENT_MAILBOX_PTR,
127 REG_CMD_MBOX_ADDRESS,
129 /* data access memory addresses, used with partition translation */
133 /* raw data access memory addresses */
134 REG_RAW_FW_STATUS_ADDR,
139 struct wl1271_stats {
141 unsigned long fw_stats_update;
144 unsigned int retry_count;
145 unsigned int excessive_retries;
149 struct ieee80211_hw *hw;
150 bool mac80211_registered;
153 struct platform_device *pdev;
157 struct wl1271_if_operations *if_ops;
159 void (*set_power)(bool enable);
164 enum wlcore_state state;
165 enum wl12xx_fw_type fw_type;
167 enum plt_mode plt_mode;
174 struct wlcore_partition_set curr_part;
176 struct wl1271_chip chip;
187 /* address read from the fuse ROM */
191 /* we have up to 2 MAC addresses */
192 struct mac_address addresses[WLCORE_NUM_MAC_ADDRESSES];
196 unsigned long links_map[BITS_TO_LONGS(WL12XX_MAX_LINKS)];
197 unsigned long roles_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
198 unsigned long roc_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
199 unsigned long rate_policies_map[
200 BITS_TO_LONGS(WL12XX_MAX_RATE_POLICIES)];
201 unsigned long klv_templates_map[
202 BITS_TO_LONGS(WLCORE_MAX_KLV_TEMPLATES)];
204 struct list_head wlvif_list;
209 struct wl1271_acx_mem_map *target_mem_map;
211 /* Accounting for allocated / available TX blocks on HW */
213 u32 tx_blocks_available;
214 u32 tx_allocated_blocks;
215 u32 tx_results_count;
217 /* Accounting for allocated / available Tx packets in HW */
218 u32 tx_pkts_freed[NUM_TX_QUEUES];
219 u32 tx_allocated_pkts[NUM_TX_QUEUES];
221 /* Transmitted TX packets counter for chipset interface */
222 u32 tx_packets_count;
224 /* Time-offset between host and chipset clocks */
227 /* Frames scheduled for transmission, not handled yet */
228 int tx_queue_count[NUM_TX_QUEUES];
229 unsigned long queue_stop_reasons[NUM_TX_QUEUES];
231 /* Frames received, not handled yet by mac80211 */
232 struct sk_buff_head deferred_rx_queue;
234 /* Frames sent, not returned yet to mac80211 */
235 struct sk_buff_head deferred_tx_queue;
237 struct work_struct tx_work;
238 struct workqueue_struct *freezable_wq;
240 /* Pending TX frames */
241 unsigned long tx_frames_map[BITS_TO_LONGS(WLCORE_MAX_TX_DESCRIPTORS)];
242 struct sk_buff *tx_frames[WLCORE_MAX_TX_DESCRIPTORS];
248 /* Intermediate buffer, used for packet aggregation */
252 /* Reusable dummy packet template */
253 struct sk_buff *dummy_packet;
255 /* Network stack work */
256 struct work_struct netstack_work;
261 /* Number of valid bytes in the FW log buffer */
264 /* Sysfs FW log entry readers wait queue */
265 wait_queue_head_t fwlog_waitq;
267 /* Hardware recovery work */
268 struct work_struct recovery_work;
269 bool watchdog_recovery;
271 /* Pointer that holds DMA-friendly block for the mailbox */
272 struct event_mailbox *mbox;
274 /* The mbox event mask */
277 /* Mailbox pointers */
280 /* Are we currently scanning */
281 struct ieee80211_vif *scan_vif;
282 struct wl1271_scan scan;
283 struct delayed_work scan_complete_work;
285 /* Connection loss work */
286 struct delayed_work connection_loss_work;
290 /* The current band */
291 enum ieee80211_band band;
293 struct completion *elp_compl;
294 struct delayed_work elp_work;
299 struct wl1271_stats stats;
303 u32 buffer_busyword[WL1271_BUSY_WORD_CNT];
305 struct wl_fw_status_1 *fw_status_1;
306 struct wl_fw_status_2 *fw_status_2;
307 struct wl1271_tx_hw_res_if *tx_res_if;
309 /* Current chipset configuration */
310 struct wlcore_conf conf;
316 /* Most recently reported noise in dBm */
319 /* bands supported by this instance of wl12xx */
320 struct ieee80211_supported_band bands[WLCORE_NUM_BANDS];
323 * wowlan trigger was configured during suspend.
324 * (currently, only "ANY" trigger is supported)
327 bool irq_wake_enabled;
330 * AP-mode - links indexed by HLID. The global and broadcast links
333 struct wl1271_link links[WL12XX_MAX_LINKS];
335 /* AP-mode - a bitmap of links currently in PS mode according to FW */
338 /* AP-mode - a bitmap of links currently in PS mode in mac80211 */
339 unsigned long ap_ps_map;
341 /* Quirks of specific hardware revisions */
344 /* Platform limitations */
345 unsigned int platform_quirks;
347 /* number of currently active RX BA sessions */
348 int ba_rx_session_count;
350 /* AP-mode - number of currently connected stations */
351 int active_sta_count;
353 /* last wlvif we transmitted from */
354 struct wl12xx_vif *last_wlvif;
356 /* work to fire when Tx is stuck */
357 struct delayed_work tx_watchdog_work;
359 struct wlcore_ops *ops;
360 /* pointer to the lower driver partition table */
361 const struct wlcore_partition_set *ptable;
362 /* pointer to the lower driver register table */
364 /* name of the firmwares to load - for PLT, single role, multi-role */
365 const char *plt_fw_name;
366 const char *sr_fw_name;
367 const char *mr_fw_name;
369 /* per-chip-family private structure */
372 /* number of TX descriptors the HW supports. */
374 /* number of RX descriptors the HW supports. */
377 /* translate HW Tx rates to standard rate-indices */
378 const u8 **band_rate_to_idx;
380 /* size of table for HW rates that can be received from chip */
381 u8 hw_tx_rate_tbl_size;
383 /* this HW rate and below are considered HT rates for this chip */
386 /* HW HT (11n) capabilities */
387 struct ieee80211_sta_ht_cap ht_cap[WLCORE_NUM_BANDS];
389 /* size of the private FW status data */
390 size_t fw_status_priv_len;
392 /* RX Data filter rule state - enabled/disabled */
393 bool rx_filter_enabled[WL1271_MAX_RX_FILTERS];
395 /* size of the private static data */
396 size_t static_data_priv_len;
398 /* the current channel type */
399 enum nl80211_channel_type channel_type;
401 /* mutex for protecting the tx_flush function */
402 struct mutex flush_mutex;
404 /* sleep auth value currently configured to FW */
407 /* the number of allocated MAC addresses in this chip */
410 /* the minimum FW version required for the driver to work */
411 unsigned int min_fw_ver[NUM_FW_VER];
414 int __devinit wlcore_probe(struct wl1271 *wl, struct platform_device *pdev);
415 int __devexit wlcore_remove(struct platform_device *pdev);
416 struct ieee80211_hw *wlcore_alloc_hw(size_t priv_size, u32 aggr_buf_size);
417 int wlcore_free_hw(struct wl1271 *wl);
418 int wlcore_set_key(struct wl1271 *wl, enum set_key_cmd cmd,
419 struct ieee80211_vif *vif,
420 struct ieee80211_sta *sta,
421 struct ieee80211_key_conf *key_conf);
424 wlcore_set_ht_cap(struct wl1271 *wl, enum ieee80211_band band,
425 struct ieee80211_sta_ht_cap *ht_cap)
427 memcpy(&wl->ht_cap[band], ht_cap, sizeof(*ht_cap));
431 wlcore_set_min_fw_ver(struct wl1271 *wl, unsigned int chip,
432 unsigned int iftype, unsigned int major,
433 unsigned int subtype, unsigned int minor)
435 wl->min_fw_ver[FW_VER_CHIP] = chip;
436 wl->min_fw_ver[FW_VER_IF_TYPE] = iftype;
437 wl->min_fw_ver[FW_VER_MAJOR] = major;
438 wl->min_fw_ver[FW_VER_SUBTYPE] = subtype;
439 wl->min_fw_ver[FW_VER_MINOR] = minor;
442 /* Firmware image load chunk size */
443 #define CHUNK_SIZE 16384
447 /* Each RX/TX transaction requires an end-of-transaction transfer */
448 #define WLCORE_QUIRK_END_OF_TRANSACTION BIT(0)
450 /* wl127x and SPI don't support SDIO block size alignment */
451 #define WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN BIT(2)
453 /* means aggregated Rx packets are aligned to a SDIO block */
454 #define WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN BIT(3)
456 /* Older firmwares did not implement the FW logger over bus feature */
457 #define WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED BIT(4)
459 /* Older firmwares use an old NVS format */
460 #define WLCORE_QUIRK_LEGACY_NVS BIT(5)
462 /* Some firmwares may not support ELP */
463 #define WLCORE_QUIRK_NO_ELP BIT(6)
465 /* pad only the last frame in the aggregate buffer */
466 #define WLCORE_QUIRK_TX_PAD_LAST_FRAME BIT(7)
468 /* extra header space is required for TKIP */
469 #define WLCORE_QUIRK_TKIP_HEADER_SPACE BIT(8)
471 /* Some firmwares not support sched scans while connected */
472 #define WLCORE_QUIRK_NO_SCHED_SCAN_WHILE_CONN BIT(9)
474 /* separate probe response templates for one-shot and sched scans */
475 #define WLCORE_QUIRK_DUAL_PROBE_TMPL BIT(10)
477 /* TODO: move to the lower drivers when all usages are abstracted */
478 #define CHIP_ID_1271_PG10 (0x4030101)
479 #define CHIP_ID_1271_PG20 (0x4030111)
480 #define CHIP_ID_1283_PG10 (0x05030101)
481 #define CHIP_ID_1283_PG20 (0x05030111)
483 /* TODO: move all these common registers and values elsewhere */
484 #define HW_ACCESS_ELP_CTRL_REG 0x1FFFC
486 /* ELP register commands */
487 #define ELPCTRL_WAKE_UP 0x1
488 #define ELPCTRL_WAKE_UP_WLAN_READY 0x5
489 #define ELPCTRL_SLEEP 0x0
490 /* ELP WLAN_READY bit */
491 #define ELPCTRL_WLAN_READY 0x2
493 /*************************************************************************
495 Interrupt Trigger Register (Host -> WiLink)
497 **************************************************************************/
499 /* Hardware to Embedded CPU Interrupts - first 32-bit register set */
502 * The host sets this bit to inform the Wlan
503 * FW that a TX packet is in the XFER
506 #define INTR_TRIG_TX_PROC0 BIT(2)
509 * The host sets this bit to inform the FW
510 * that it read a packet from RX XFER
513 #define INTR_TRIG_RX_PROC0 BIT(3)
515 #define INTR_TRIG_DEBUG_ACK BIT(4)
517 #define INTR_TRIG_STATE_CHANGED BIT(5)
519 /* Hardware to Embedded CPU Interrupts - second 32-bit register set */
522 * The host sets this bit to inform the FW
523 * that it read a packet from RX XFER
526 #define INTR_TRIG_RX_PROC1 BIT(17)
529 * The host sets this bit to inform the Wlan
530 * hardware that a TX packet is in the XFER
533 #define INTR_TRIG_TX_PROC1 BIT(18)
535 #define ACX_SLV_SOFT_RESET_BIT BIT(1)
536 #define SOFT_RESET_MAX_TIME 1000000
537 #define SOFT_RESET_STALL_TIME 1000
539 #define ECPU_CONTROL_HALT 0x00000101
541 #define WELP_ARM_COMMAND_VAL 0x4
543 #endif /* __WLCORE_H__ */