2 * This file is part of wlcore
4 * Copyright (C) 2011 Texas Instruments Inc.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
25 #include <linux/platform_device.h>
31 /* The maximum number of Tx descriptors in all chip families */
32 #define WLCORE_MAX_TX_DESCRIPTORS 32
35 * We always allocate this number of mac addresses. If we don't
36 * have enough allocated addresses, the LAA bit is used
38 #define WLCORE_NUM_MAC_ADDRESSES 3
40 /* forward declaration */
41 struct wl1271_tx_hw_descr;
43 struct wl1271_rx_descriptor;
46 int (*setup)(struct wl1271 *wl);
47 int (*identify_chip)(struct wl1271 *wl);
48 int (*identify_fw)(struct wl1271 *wl);
49 int (*boot)(struct wl1271 *wl);
50 int (*plt_init)(struct wl1271 *wl);
51 int (*trigger_cmd)(struct wl1271 *wl, int cmd_box_addr,
52 void *buf, size_t len);
53 int (*ack_event)(struct wl1271 *wl);
54 int (*wait_for_event)(struct wl1271 *wl, enum wlcore_wait_event event,
56 int (*process_mailbox_events)(struct wl1271 *wl);
57 u32 (*calc_tx_blocks)(struct wl1271 *wl, u32 len, u32 spare_blks);
58 void (*set_tx_desc_blocks)(struct wl1271 *wl,
59 struct wl1271_tx_hw_descr *desc,
60 u32 blks, u32 spare_blks);
61 void (*set_tx_desc_data_len)(struct wl1271 *wl,
62 struct wl1271_tx_hw_descr *desc,
64 enum wl_rx_buf_align (*get_rx_buf_align)(struct wl1271 *wl,
66 int (*prepare_read)(struct wl1271 *wl, u32 rx_desc, u32 len);
67 u32 (*get_rx_packet_len)(struct wl1271 *wl, void *rx_data,
69 int (*tx_delayed_compl)(struct wl1271 *wl);
70 void (*tx_immediate_compl)(struct wl1271 *wl);
71 int (*hw_init)(struct wl1271 *wl);
72 int (*init_vif)(struct wl1271 *wl, struct wl12xx_vif *wlvif);
73 u32 (*sta_get_ap_rate_mask)(struct wl1271 *wl,
74 struct wl12xx_vif *wlvif);
75 int (*get_pg_ver)(struct wl1271 *wl, s8 *ver);
76 int (*get_mac)(struct wl1271 *wl);
77 void (*set_tx_desc_csum)(struct wl1271 *wl,
78 struct wl1271_tx_hw_descr *desc,
80 void (*set_rx_csum)(struct wl1271 *wl,
81 struct wl1271_rx_descriptor *desc,
83 u32 (*ap_get_mimo_wide_rate_mask)(struct wl1271 *wl,
84 struct wl12xx_vif *wlvif);
85 int (*debugfs_init)(struct wl1271 *wl, struct dentry *rootdir);
86 int (*handle_static_data)(struct wl1271 *wl,
87 struct wl1271_static_data *static_data);
88 int (*scan_start)(struct wl1271 *wl, struct wl12xx_vif *wlvif,
89 struct cfg80211_scan_request *req);
90 int (*scan_stop)(struct wl1271 *wl, struct wl12xx_vif *wlvif);
91 int (*sched_scan_start)(struct wl1271 *wl, struct wl12xx_vif *wlvif,
92 struct cfg80211_sched_scan_request *req,
93 struct ieee80211_sched_scan_ies *ies);
94 void (*sched_scan_stop)(struct wl1271 *wl, struct wl12xx_vif *wlvif);
95 int (*get_spare_blocks)(struct wl1271 *wl, bool is_gem);
96 int (*set_key)(struct wl1271 *wl, enum set_key_cmd cmd,
97 struct ieee80211_vif *vif,
98 struct ieee80211_sta *sta,
99 struct ieee80211_key_conf *key_conf);
100 int (*channel_switch)(struct wl1271 *wl,
101 struct wl12xx_vif *wlvif,
102 struct ieee80211_channel_switch *ch_switch);
103 u32 (*pre_pkt_send)(struct wl1271 *wl, u32 buf_offset, u32 last_len);
106 enum wlcore_partitions {
111 PART_TOP_PRCM_ELP_SOC,
117 struct wlcore_partition {
122 struct wlcore_partition_set {
123 struct wlcore_partition mem;
124 struct wlcore_partition reg;
125 struct wlcore_partition mem2;
126 struct wlcore_partition mem3;
129 enum wlcore_registers {
130 /* register addresses, used with partition translation */
132 REG_INTERRUPT_NO_CLEAR,
134 REG_COMMAND_MAILBOX_PTR,
135 REG_EVENT_MAILBOX_PTR,
140 REG_CMD_MBOX_ADDRESS,
142 /* data access memory addresses, used with partition translation */
146 /* raw data access memory addresses */
147 REG_RAW_FW_STATUS_ADDR,
152 struct wl1271_stats {
154 unsigned long fw_stats_update;
157 unsigned int retry_count;
158 unsigned int excessive_retries;
163 struct ieee80211_hw *hw;
164 bool mac80211_registered;
167 struct platform_device *pdev;
171 struct wl1271_if_operations *if_ops;
173 void (*set_power)(bool enable);
178 enum wlcore_state state;
179 enum wl12xx_fw_type fw_type;
181 enum plt_mode plt_mode;
188 struct wlcore_partition_set curr_part;
190 struct wl1271_chip chip;
201 /* address read from the fuse ROM */
205 /* we have up to 2 MAC addresses */
206 struct mac_address addresses[WLCORE_NUM_MAC_ADDRESSES];
210 unsigned long links_map[BITS_TO_LONGS(WL12XX_MAX_LINKS)];
211 unsigned long roles_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
212 unsigned long roc_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
213 unsigned long rate_policies_map[
214 BITS_TO_LONGS(WL12XX_MAX_RATE_POLICIES)];
215 unsigned long klv_templates_map[
216 BITS_TO_LONGS(WLCORE_MAX_KLV_TEMPLATES)];
218 u8 session_ids[WL12XX_MAX_LINKS];
220 struct list_head wlvif_list;
225 struct wl1271_acx_mem_map *target_mem_map;
227 /* Accounting for allocated / available TX blocks on HW */
229 u32 tx_blocks_available;
230 u32 tx_allocated_blocks;
231 u32 tx_results_count;
233 /* Accounting for allocated / available Tx packets in HW */
234 u32 tx_pkts_freed[NUM_TX_QUEUES];
235 u32 tx_allocated_pkts[NUM_TX_QUEUES];
237 /* Transmitted TX packets counter for chipset interface */
238 u32 tx_packets_count;
240 /* Time-offset between host and chipset clocks */
243 /* Frames scheduled for transmission, not handled yet */
244 int tx_queue_count[NUM_TX_QUEUES];
245 unsigned long queue_stop_reasons[NUM_TX_QUEUES];
247 /* Frames received, not handled yet by mac80211 */
248 struct sk_buff_head deferred_rx_queue;
250 /* Frames sent, not returned yet to mac80211 */
251 struct sk_buff_head deferred_tx_queue;
253 struct work_struct tx_work;
254 struct workqueue_struct *freezable_wq;
256 /* Pending TX frames */
257 unsigned long tx_frames_map[BITS_TO_LONGS(WLCORE_MAX_TX_DESCRIPTORS)];
258 struct sk_buff *tx_frames[WLCORE_MAX_TX_DESCRIPTORS];
264 /* Intermediate buffer, used for packet aggregation */
268 /* Reusable dummy packet template */
269 struct sk_buff *dummy_packet;
271 /* Network stack work */
272 struct work_struct netstack_work;
277 /* Number of valid bytes in the FW log buffer */
280 /* Sysfs FW log entry readers wait queue */
281 wait_queue_head_t fwlog_waitq;
283 /* Hardware recovery work */
284 struct work_struct recovery_work;
285 bool watchdog_recovery;
287 /* Reg domain last configuration */
288 u32 reg_ch_conf_last[2];
289 /* Reg domain pending configuration */
290 u32 reg_ch_conf_pending[2];
292 /* Pointer that holds DMA-friendly block for the mailbox */
295 /* The mbox event mask */
298 /* Mailbox pointers */
302 /* Are we currently scanning */
303 struct wl12xx_vif *scan_wlvif;
304 struct wl1271_scan scan;
305 struct delayed_work scan_complete_work;
307 struct ieee80211_vif *roc_vif;
308 struct delayed_work roc_complete_work;
310 struct wl12xx_vif *sched_vif;
312 /* The current band */
313 enum ieee80211_band band;
315 struct completion *elp_compl;
316 struct delayed_work elp_work;
321 struct wl1271_stats stats;
325 u32 buffer_busyword[WL1271_BUSY_WORD_CNT];
327 struct wl_fw_status_1 *fw_status_1;
328 struct wl_fw_status_2 *fw_status_2;
329 struct wl1271_tx_hw_res_if *tx_res_if;
331 /* Current chipset configuration */
332 struct wlcore_conf conf;
338 /* Most recently reported noise in dBm */
341 /* bands supported by this instance of wl12xx */
342 struct ieee80211_supported_band bands[WLCORE_NUM_BANDS];
345 * wowlan trigger was configured during suspend.
346 * (currently, only "ANY" trigger is supported)
349 bool irq_wake_enabled;
352 * AP-mode - links indexed by HLID. The global and broadcast links
355 struct wl1271_link links[WL12XX_MAX_LINKS];
357 /* AP-mode - a bitmap of links currently in PS mode according to FW */
360 /* AP-mode - a bitmap of links currently in PS mode in mac80211 */
361 unsigned long ap_ps_map;
363 /* Quirks of specific hardware revisions */
366 /* Platform limitations */
367 unsigned int platform_quirks;
369 /* number of currently active RX BA sessions */
370 int ba_rx_session_count;
372 /* AP-mode - number of currently connected stations */
373 int active_sta_count;
375 /* last wlvif we transmitted from */
376 struct wl12xx_vif *last_wlvif;
378 /* work to fire when Tx is stuck */
379 struct delayed_work tx_watchdog_work;
381 struct wlcore_ops *ops;
382 /* pointer to the lower driver partition table */
383 const struct wlcore_partition_set *ptable;
384 /* pointer to the lower driver register table */
386 /* name of the firmwares to load - for PLT, single role, multi-role */
387 const char *plt_fw_name;
388 const char *sr_fw_name;
389 const char *mr_fw_name;
391 u8 scan_templ_id_2_4;
393 u8 sched_scan_templ_id_2_4;
394 u8 sched_scan_templ_id_5;
397 /* per-chip-family private structure */
400 /* number of TX descriptors the HW supports. */
402 /* number of RX descriptors the HW supports. */
405 /* translate HW Tx rates to standard rate-indices */
406 const u8 **band_rate_to_idx;
408 /* size of table for HW rates that can be received from chip */
409 u8 hw_tx_rate_tbl_size;
411 /* this HW rate and below are considered HT rates for this chip */
414 /* HW HT (11n) capabilities */
415 struct ieee80211_sta_ht_cap ht_cap[WLCORE_NUM_BANDS];
417 /* size of the private FW status data */
418 size_t fw_status_priv_len;
420 /* RX Data filter rule state - enabled/disabled */
421 bool rx_filter_enabled[WL1271_MAX_RX_FILTERS];
423 /* size of the private static data */
424 size_t static_data_priv_len;
426 /* the current channel type */
427 enum nl80211_channel_type channel_type;
429 /* mutex for protecting the tx_flush function */
430 struct mutex flush_mutex;
432 /* sleep auth value currently configured to FW */
435 /* the number of allocated MAC addresses in this chip */
438 /* the minimum FW version required for the driver to work */
439 unsigned int min_fw_ver[NUM_FW_VER];
441 struct completion nvs_loading_complete;
444 int __devinit wlcore_probe(struct wl1271 *wl, struct platform_device *pdev);
445 int __devexit wlcore_remove(struct platform_device *pdev);
446 struct ieee80211_hw *wlcore_alloc_hw(size_t priv_size, u32 aggr_buf_size,
448 int wlcore_free_hw(struct wl1271 *wl);
449 int wlcore_set_key(struct wl1271 *wl, enum set_key_cmd cmd,
450 struct ieee80211_vif *vif,
451 struct ieee80211_sta *sta,
452 struct ieee80211_key_conf *key_conf);
453 void wlcore_regdomain_config(struct wl1271 *wl);
456 wlcore_set_ht_cap(struct wl1271 *wl, enum ieee80211_band band,
457 struct ieee80211_sta_ht_cap *ht_cap)
459 memcpy(&wl->ht_cap[band], ht_cap, sizeof(*ht_cap));
463 wlcore_set_min_fw_ver(struct wl1271 *wl, unsigned int chip,
464 unsigned int iftype, unsigned int major,
465 unsigned int subtype, unsigned int minor)
467 wl->min_fw_ver[FW_VER_CHIP] = chip;
468 wl->min_fw_ver[FW_VER_IF_TYPE] = iftype;
469 wl->min_fw_ver[FW_VER_MAJOR] = major;
470 wl->min_fw_ver[FW_VER_SUBTYPE] = subtype;
471 wl->min_fw_ver[FW_VER_MINOR] = minor;
474 /* Firmware image load chunk size */
475 #define CHUNK_SIZE 16384
479 /* Each RX/TX transaction requires an end-of-transaction transfer */
480 #define WLCORE_QUIRK_END_OF_TRANSACTION BIT(0)
482 /* the first start_role(sta) sometimes doesn't work on wl12xx */
483 #define WLCORE_QUIRK_START_STA_FAILS BIT(1)
485 /* wl127x and SPI don't support SDIO block size alignment */
486 #define WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN BIT(2)
488 /* means aggregated Rx packets are aligned to a SDIO block */
489 #define WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN BIT(3)
491 /* Older firmwares did not implement the FW logger over bus feature */
492 #define WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED BIT(4)
494 /* Older firmwares use an old NVS format */
495 #define WLCORE_QUIRK_LEGACY_NVS BIT(5)
497 /* Some firmwares may not support ELP */
498 #define WLCORE_QUIRK_NO_ELP BIT(6)
500 /* pad only the last frame in the aggregate buffer */
501 #define WLCORE_QUIRK_TX_PAD_LAST_FRAME BIT(7)
503 /* extra header space is required for TKIP */
504 #define WLCORE_QUIRK_TKIP_HEADER_SPACE BIT(8)
506 /* Some firmwares not support sched scans while connected */
507 #define WLCORE_QUIRK_NO_SCHED_SCAN_WHILE_CONN BIT(9)
509 /* separate probe response templates for one-shot and sched scans */
510 #define WLCORE_QUIRK_DUAL_PROBE_TMPL BIT(10)
512 /* Firmware requires reg domain configuration for active calibration */
513 #define WLCORE_QUIRK_REGDOMAIN_CONF BIT(11)
516 /* TODO: move to the lower drivers when all usages are abstracted */
517 #define CHIP_ID_1271_PG10 (0x4030101)
518 #define CHIP_ID_1271_PG20 (0x4030111)
519 #define CHIP_ID_1283_PG10 (0x05030101)
520 #define CHIP_ID_1283_PG20 (0x05030111)
522 /* TODO: move all these common registers and values elsewhere */
523 #define HW_ACCESS_ELP_CTRL_REG 0x1FFFC
525 /* ELP register commands */
526 #define ELPCTRL_WAKE_UP 0x1
527 #define ELPCTRL_WAKE_UP_WLAN_READY 0x5
528 #define ELPCTRL_SLEEP 0x0
529 /* ELP WLAN_READY bit */
530 #define ELPCTRL_WLAN_READY 0x2
532 /*************************************************************************
534 Interrupt Trigger Register (Host -> WiLink)
536 **************************************************************************/
538 /* Hardware to Embedded CPU Interrupts - first 32-bit register set */
541 * The host sets this bit to inform the Wlan
542 * FW that a TX packet is in the XFER
545 #define INTR_TRIG_TX_PROC0 BIT(2)
548 * The host sets this bit to inform the FW
549 * that it read a packet from RX XFER
552 #define INTR_TRIG_RX_PROC0 BIT(3)
554 #define INTR_TRIG_DEBUG_ACK BIT(4)
556 #define INTR_TRIG_STATE_CHANGED BIT(5)
558 /* Hardware to Embedded CPU Interrupts - second 32-bit register set */
561 * The host sets this bit to inform the FW
562 * that it read a packet from RX XFER
565 #define INTR_TRIG_RX_PROC1 BIT(17)
568 * The host sets this bit to inform the Wlan
569 * hardware that a TX packet is in the XFER
572 #define INTR_TRIG_TX_PROC1 BIT(18)
574 #define ACX_SLV_SOFT_RESET_BIT BIT(1)
575 #define SOFT_RESET_MAX_TIME 1000000
576 #define SOFT_RESET_STALL_TIME 1000
578 #define ECPU_CONTROL_HALT 0x00000101
580 #define WELP_ARM_COMMAND_VAL 0x4
582 #endif /* __WLCORE_H__ */