Pileus Git - ~andy/linux/blob - drivers/net/wireless/rtlwifi/rtl8192ce/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include "../wifi.h"
  31 #include "../efuse.h"
  32 #include "../base.h"
  33 #include "../regd.h"
  34 #include "../cam.h"
  35 #include "../ps.h"
  36 #include "../pci.h"
  37 #include "reg.h"
  38 #include "def.h"
  39 #include "phy.h"
  40 #include "../rtl8192c/fw_common.h"
  41 #include "dm.h"
  42 #include "led.h"
  43 #include "hw.h"
  44
  45 #define LLT_CONFIG      5
  46
  47 static void _rtl92ce_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
  48                                       u8 set_bits, u8 clear_bits)
  49 {
  50         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  51         struct rtl_priv *rtlpriv = rtl_priv(hw);
  52
  53         rtlpci->reg_bcn_ctrl_val |= set_bits;
  54         rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
  55
  56         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
  57 }
  58
  59 static void _rtl92ce_stop_tx_beacon(struct ieee80211_hw *hw)
  60 {
  61         struct rtl_priv *rtlpriv = rtl_priv(hw);
  62         u8 tmp1byte;
  63
  64         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  65         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
  66         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
  67         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  68         tmp1byte &= ~(BIT(0));
  69         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  70 }
  71
  72 static void _rtl92ce_resume_tx_beacon(struct ieee80211_hw *hw)
  73 {
  74         struct rtl_priv *rtlpriv = rtl_priv(hw);
  75         u8 tmp1byte;
  76
  77         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  78         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
  79         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
  80         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  81         tmp1byte |= BIT(0);
  82         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  83 }
  84
  85 static void _rtl92ce_enable_bcn_sub_func(struct ieee80211_hw *hw)
  86 {
  87         _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(1));
  88 }
  89
  90 static void _rtl92ce_disable_bcn_sub_func(struct ieee80211_hw *hw)
  91 {
  92         _rtl92ce_set_bcn_ctrl_reg(hw, BIT(1), 0);
  93 }
  94
  95 void rtl92ce_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
  96 {
  97         struct rtl_priv *rtlpriv = rtl_priv(hw);
  98         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  99         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 100
 101         switch (variable) {
 102         case HW_VAR_RCR:
 103                 *((u32 *) (val)) = rtlpci->receive_config;
 104                 break;
 105         case HW_VAR_RF_STATE:
 106                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
 107                 break;
 108         case HW_VAR_FWLPS_RF_ON:{
 109                         enum rf_pwrstate rfState;
 110                         u32 val_rcr;
 111
 112                         rtlpriv->cfg->ops->get_hw_reg(hw,
 113                                                       HW_VAR_RF_STATE,
 114                                                       (u8 *) (&rfState));
 115                         if (rfState == ERFOFF) {
 116                                 *((bool *) (val)) = true;
 117                         } else {
 118                                 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
 119                                 val_rcr &= 0x00070000;
 120                                 if (val_rcr)
 121                                         *((bool *) (val)) = false;
 122                                 else
 123                                         *((bool *) (val)) = true;
 124                         }
 125                         break;
 126                 }
 127         case HW_VAR_FW_PSMODE_STATUS:
 128                 *((bool *) (val)) = ppsc->fw_current_inpsmode;
 129                 break;
 130         case HW_VAR_CORRECT_TSF:{
 131                 u64 tsf;
 132                 u32 *ptsf_low = (u32 *)&tsf;
 133                 u32 *ptsf_high = ((u32 *)&tsf) + 1;
 134
 135                 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
 136                 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
 137
 138                 *((u64 *) (val)) = tsf;
 139
 140                 break;
 141                 }
 142         default:
 143                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 144                          ("switch case not process\n"));
 145                 break;
 146         }
 147 }
 148
 149 void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 150 {
 151         struct rtl_priv *rtlpriv = rtl_priv(hw);
 152         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
 153         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 154         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 155         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 156         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 157         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 158         u8 idx;
 159
 160         switch (variable) {
 161         case HW_VAR_ETHER_ADDR:{
 162                         for (idx = 0; idx < ETH_ALEN; idx++) {
 163                                 rtl_write_byte(rtlpriv, (REG_MACID + idx),
 164                                                val[idx]);
 165                         }
 166                         break;
 167                 }
 168         case HW_VAR_BASIC_RATE:{
 169                         u16 rate_cfg = ((u16 *) val)[0];
 170                         u8 rate_index = 0;
 171                         rate_cfg &= 0x15f;
 172                         rate_cfg |= 0x01;
 173                         rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
 174                         rtl_write_byte(rtlpriv, REG_RRSR + 1,
 175                                        (rate_cfg >> 8) & 0xff);
 176                         while (rate_cfg > 0x1) {
 177                                 rate_cfg = (rate_cfg >> 1);
 178                                 rate_index++;
 179                         }
 180                         rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
 181                                        rate_index);
 182                         break;
 183                 }
 184         case HW_VAR_BSSID:{
 185                         for (idx = 0; idx < ETH_ALEN; idx++) {
 186                                 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
 187                                                val[idx]);
 188                         }
 189                         break;
 190                 }
 191         case HW_VAR_SIFS:{
 192                         rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
 193                         rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
 194
 195                         rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
 196                         rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
 197
 198                         if (!mac->ht_enable)
 199                                 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 200                                                0x0e0e);
 201                         else
 202                                 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 203                                                *((u16 *) val));
 204                         break;
 205                 }
 206         case HW_VAR_SLOT_TIME:{
 207                         u8 e_aci;
 208
 209                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 210                                  ("HW_VAR_SLOT_TIME %x\n", val[0]));
 211
 212                         rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
 213
 214                         for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 215                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 216                                                               HW_VAR_AC_PARAM,
 217                                                               (u8 *) (&e_aci));
 218                         }
 219                         break;
 220                 }
 221         case HW_VAR_ACK_PREAMBLE:{
 222                         u8 reg_tmp;
 223                         u8 short_preamble = (bool) (*(u8 *) val);
 224                         reg_tmp = (mac->cur_40_prime_sc) << 5;
 225                         if (short_preamble)
 226                                 reg_tmp |= 0x80;
 227
 228                         rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
 229                         break;
 230                 }
 231         case HW_VAR_AMPDU_MIN_SPACE:{
 232                         u8 min_spacing_to_set;
 233                         u8 sec_min_space;
 234
 235                         min_spacing_to_set = *((u8 *) val);
 236                         if (min_spacing_to_set <= 7) {
 237                                 sec_min_space = 0;
 238
 239                                 if (min_spacing_to_set < sec_min_space)
 240                                         min_spacing_to_set = sec_min_space;
 241
 242                                 mac->min_space_cfg = ((mac->min_space_cfg &
 243                                                        0xf8) |
 244                                                       min_spacing_to_set);
 245
 246                                 *val = min_spacing_to_set;
 247
 248                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 249                                          ("Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
 250                                           mac->min_space_cfg));
 251
 252                                 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 253                                                mac->min_space_cfg);
 254                         }
 255                         break;
 256                 }
 257         case HW_VAR_SHORTGI_DENSITY:{
 258                         u8 density_to_set;
 259
 260                         density_to_set = *((u8 *) val);
 261                         mac->min_space_cfg |= (density_to_set << 3);
 262
 263                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 264                                  ("Set HW_VAR_SHORTGI_DENSITY: %#x\n",
 265                                   mac->min_space_cfg));
 266
 267                         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 268                                        mac->min_space_cfg);
 269
 270                         break;
 271                 }
 272         case HW_VAR_AMPDU_FACTOR:{
 273                         u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
 274                         u8 regtoset_bt[4] = {0x31, 0x74, 0x42, 0x97};
 275
 276                         u8 factor_toset;
 277                         u8 *p_regtoset = NULL;
 278                         u8 index = 0;
 279
 280                         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
 281                             (rtlpcipriv->bt_coexist.bt_coexist_type ==
 282                             BT_CSR_BC4))
 283                                 p_regtoset = regtoset_bt;
 284                         else
 285                                 p_regtoset = regtoset_normal;
 286
 287                         factor_toset = *((u8 *) val);
 288                         if (factor_toset <= 3) {
 289                                 factor_toset = (1 << (factor_toset + 2));
 290                                 if (factor_toset > 0xf)
 291                                         factor_toset = 0xf;
 292
 293                                 for (index = 0; index < 4; index++) {
 294                                         if ((p_regtoset[index] & 0xf0) >
 295                                             (factor_toset << 4))
 296                                                 p_regtoset[index] =
 297                                                     (p_regtoset[index] & 0x0f) |
 298                                                     (factor_toset << 4);
 299
 300                                         if ((p_regtoset[index] & 0x0f) >
 301                                             factor_toset)
 302                                                 p_regtoset[index] =
 303                                                     (p_regtoset[index] & 0xf0) |
 304                                                     (factor_toset);
 305
 306                                         rtl_write_byte(rtlpriv,
 307                                                        (REG_AGGLEN_LMT + index),
 308                                                        p_regtoset[index]);
 309
 310                                 }
 311
 312                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 313                                          ("Set HW_VAR_AMPDU_FACTOR: %#x\n",
 314                                           factor_toset));
 315                         }
 316                         break;
 317                 }
 318         case HW_VAR_AC_PARAM:{
 319                         u8 e_aci = *((u8 *) val);
 320                         rtl92c_dm_init_edca_turbo(hw);
 321
 322                         if (rtlpci->acm_method != eAcmWay2_SW)
 323                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 324                                                               HW_VAR_ACM_CTRL,
 325                                                               (u8 *) (&e_aci));
 326                         break;
 327                 }
 328         case HW_VAR_ACM_CTRL:{
 329                         u8 e_aci = *((u8 *) val);
 330                         union aci_aifsn *p_aci_aifsn =
 331                             (union aci_aifsn *)(&(mac->ac[0].aifs));
 332                         u8 acm = p_aci_aifsn->f.acm;
 333                         u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
 334
 335                         acm_ctrl =
 336                             acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
 337
 338                         if (acm) {
 339                                 switch (e_aci) {
 340                                 case AC0_BE:
 341                                         acm_ctrl |= AcmHw_BeqEn;
 342                                         break;
 343                                 case AC2_VI:
 344                                         acm_ctrl |= AcmHw_ViqEn;
 345                                         break;
 346                                 case AC3_VO:
 347                                         acm_ctrl |= AcmHw_VoqEn;
 348                                         break;
 349                                 default:
 350                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 351                                                  ("HW_VAR_ACM_CTRL acm set "
 352                                                   "failed: eACI is %d\n", acm));
 353                                         break;
 354                                 }
 355                         } else {
 356                                 switch (e_aci) {
 357                                 case AC0_BE:
 358                                         acm_ctrl &= (~AcmHw_BeqEn);
 359                                         break;
 360                                 case AC2_VI:
 361                                         acm_ctrl &= (~AcmHw_ViqEn);
 362                                         break;
 363                                 case AC3_VO:
 364                                         acm_ctrl &= (~AcmHw_BeqEn);
 365                                         break;
 366                                 default:
 367                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 368                                                  ("switch case not process\n"));
 369                                         break;
 370                                 }
 371                         }
 372
 373                         RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
 374                                  ("SetHwReg8190pci(): [HW_VAR_ACM_CTRL] "
 375                                   "Write 0x%X\n", acm_ctrl));
 376                         rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
 377                         break;
 378                 }
 379         case HW_VAR_RCR:{
 380                         rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
 381                         rtlpci->receive_config = ((u32 *) (val))[0];
 382                         break;
 383                 }
 384         case HW_VAR_RETRY_LIMIT:{
 385                         u8 retry_limit = ((u8 *) (val))[0];
 386
 387                         rtl_write_word(rtlpriv, REG_RL,
 388                                        retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 389                                        retry_limit << RETRY_LIMIT_LONG_SHIFT);
 390                         break;
 391                 }
 392         case HW_VAR_DUAL_TSF_RST:
 393                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
 394                 break;
 395         case HW_VAR_EFUSE_BYTES:
 396                 rtlefuse->efuse_usedbytes = *((u16 *) val);
 397                 break;
 398         case HW_VAR_EFUSE_USAGE:
 399                 rtlefuse->efuse_usedpercentage = *((u8 *) val);
 400                 break;
 401         case HW_VAR_IO_CMD:
 402                 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
 403                 break;
 404         case HW_VAR_WPA_CONFIG:
 405                 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *) val));
 406                 break;
 407         case HW_VAR_SET_RPWM:{
 408                         u8 rpwm_val;
 409
 410                         rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
 411                         udelay(1);
 412
 413                         if (rpwm_val & BIT(7)) {
 414                                 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 415                                                (*(u8 *) val));
 416                         } else {
 417                                 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 418                                                ((*(u8 *) val) | BIT(7)));
 419                         }
 420
 421                         break;
 422                 }
 423         case HW_VAR_H2C_FW_PWRMODE:{
 424                         u8 psmode = (*(u8 *) val);
 425
 426                         if ((psmode != FW_PS_ACTIVE_MODE) &&
 427                             (!IS_92C_SERIAL(rtlhal->version))) {
 428                                 rtl92c_dm_rf_saving(hw, true);
 429                         }
 430
 431                         rtl92c_set_fw_pwrmode_cmd(hw, (*(u8 *) val));
 432                         break;
 433                 }
 434         case HW_VAR_FW_PSMODE_STATUS:
 435                 ppsc->fw_current_inpsmode = *((bool *) val);
 436                 break;
 437         case HW_VAR_H2C_FW_JOINBSSRPT:{
 438                         u8 mstatus = (*(u8 *) val);
 439                         u8 tmp_regcr, tmp_reg422;
 440                         bool recover = false;
 441
 442                         if (mstatus == RT_MEDIA_CONNECT) {
 443                                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
 444                                                               NULL);
 445
 446                                 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 447                                 rtl_write_byte(rtlpriv, REG_CR + 1,
 448                                                (tmp_regcr | BIT(0)));
 449
 450                                 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
 451                                 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
 452
 453                                 tmp_reg422 =
 454                                     rtl_read_byte(rtlpriv,
 455                                                   REG_FWHW_TXQ_CTRL + 2);
 456                                 if (tmp_reg422 & BIT(6))
 457                                         recover = true;
 458                                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
 459                                                tmp_reg422 & (~BIT(6)));
 460
 461                                 rtl92c_set_fw_rsvdpagepkt(hw, 0);
 462
 463                                 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
 464                                 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
 465
 466                                 if (recover) {
 467                                         rtl_write_byte(rtlpriv,
 468                                                        REG_FWHW_TXQ_CTRL + 2,
 469                                                        tmp_reg422);
 470                                 }
 471
 472                                 rtl_write_byte(rtlpriv, REG_CR + 1,
 473                                                (tmp_regcr & ~(BIT(0))));
 474                         }
 475                         rtl92c_set_fw_joinbss_report_cmd(hw, (*(u8 *) val));
 476
 477                         break;
 478                 }
 479         case HW_VAR_AID:{
 480                         u16 u2btmp;
 481                         u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
 482                         u2btmp &= 0xC000;
 483                         rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
 484                                                 mac->assoc_id));
 485
 486                         break;
 487                 }
 488         case HW_VAR_CORRECT_TSF:{
 489                         u8 btype_ibss = ((u8 *) (val))[0];
 490
 491                         if (btype_ibss == true)
 492                                 _rtl92ce_stop_tx_beacon(hw);
 493
 494                         _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
 495
 496                         rtl_write_dword(rtlpriv, REG_TSFTR,
 497                                         (u32) (mac->tsf & 0xffffffff));
 498                         rtl_write_dword(rtlpriv, REG_TSFTR + 4,
 499                                         (u32) ((mac->tsf >> 32) & 0xffffffff));
 500
 501                         _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
 502
 503                         if (btype_ibss == true)
 504                                 _rtl92ce_resume_tx_beacon(hw);
 505
 506                         break;
 507
 508                 }
 509         default:
 510                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("switch case "
 511                                                         "not process\n"));
 512                 break;
 513         }
 514 }
 515
 516 static bool _rtl92ce_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
 517 {
 518         struct rtl_priv *rtlpriv = rtl_priv(hw);
 519         bool status = true;
 520         long count = 0;
 521         u32 value = _LLT_INIT_ADDR(address) |
 522             _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
 523
 524         rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
 525
 526         do {
 527                 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
 528                 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
 529                         break;
 530
 531                 if (count > POLLING_LLT_THRESHOLD) {
 532                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 533                                  ("Failed to polling write LLT done at "
 534                                   "address %d!\n", address));
 535                         status = false;
 536                         break;
 537                 }
 538         } while (++count);
 539
 540         return status;
 541 }
 542
 543 static bool _rtl92ce_llt_table_init(struct ieee80211_hw *hw)
 544 {
 545         struct rtl_priv *rtlpriv = rtl_priv(hw);
 546         unsigned short i;
 547         u8 txpktbuf_bndy;
 548         u8 maxPage;
 549         bool status;
 550
 551 #if LLT_CONFIG == 1
 552         maxPage = 255;
 553         txpktbuf_bndy = 252;
 554 #elif LLT_CONFIG == 2
 555         maxPage = 127;
 556         txpktbuf_bndy = 124;
 557 #elif LLT_CONFIG == 3
 558         maxPage = 255;
 559         txpktbuf_bndy = 174;
 560 #elif LLT_CONFIG == 4
 561         maxPage = 255;
 562         txpktbuf_bndy = 246;
 563 #elif LLT_CONFIG == 5
 564         maxPage = 255;
 565         txpktbuf_bndy = 246;
 566 #endif
 567
 568 #if LLT_CONFIG == 1
 569         rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x1c);
 570         rtl_write_dword(rtlpriv, REG_RQPN, 0x80a71c1c);
 571 #elif LLT_CONFIG == 2
 572         rtl_write_dword(rtlpriv, REG_RQPN, 0x845B1010);
 573 #elif LLT_CONFIG == 3
 574         rtl_write_dword(rtlpriv, REG_RQPN, 0x84838484);
 575 #elif LLT_CONFIG == 4
 576         rtl_write_dword(rtlpriv, REG_RQPN, 0x80bd1c1c);
 577 #elif LLT_CONFIG == 5
 578         rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000);
 579
 580         rtl_write_dword(rtlpriv, REG_RQPN, 0x80b01c29);
 581 #endif
 582
 583         rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy));
 584         rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
 585
 586         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 587         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 588
 589         rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
 590         rtl_write_byte(rtlpriv, REG_PBP, 0x11);
 591         rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
 592
 593         for (i = 0; i < (txpktbuf_bndy - 1); i++) {
 594                 status = _rtl92ce_llt_write(hw, i, i + 1);
 595                 if (true != status)
 596                         return status;
 597         }
 598
 599         status = _rtl92ce_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
 600         if (true != status)
 601                 return status;
 602
 603         for (i = txpktbuf_bndy; i < maxPage; i++) {
 604                 status = _rtl92ce_llt_write(hw, i, (i + 1));
 605                 if (true != status)
 606                         return status;
 607         }
 608
 609         status = _rtl92ce_llt_write(hw, maxPage, txpktbuf_bndy);
 610         if (true != status)
 611                 return status;
 612
 613         return true;
 614 }
 615
 616 static void _rtl92ce_gen_refresh_led_state(struct ieee80211_hw *hw)
 617 {
 618         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 619         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 620         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 621         struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
 622
 623         if (rtlpci->up_first_time)
 624                 return;
 625
 626         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
 627                 rtl92ce_sw_led_on(hw, pLed0);
 628         else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
 629                 rtl92ce_sw_led_on(hw, pLed0);
 630         else
 631                 rtl92ce_sw_led_off(hw, pLed0);
 632 }
 633
 634 static bool _rtl92ce_init_mac(struct ieee80211_hw *hw)
 635 {
 636         struct rtl_priv *rtlpriv = rtl_priv(hw);
 637         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
 638         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 639         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 640
 641         unsigned char bytetmp;
 642         unsigned short wordtmp;
 643         u16 retry;
 644
 645         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
 646         if (rtlpcipriv->bt_coexist.bt_coexistence) {
 647                 u32 value32;
 648                 value32 = rtl_read_dword(rtlpriv, REG_APS_FSMCO);
 649                 value32 |= (SOP_ABG | SOP_AMB | XOP_BTCK);
 650                 rtl_write_dword(rtlpriv, REG_APS_FSMCO, value32);
 651         }
 652         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
 653         rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F);
 654
 655         if (rtlpcipriv->bt_coexist.bt_coexistence) {
 656                 u32 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL);
 657
 658                 u4b_tmp &= (~0x00024800);
 659                 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp);
 660         }
 661
 662         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0);
 663         udelay(2);
 664
 665         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
 666         udelay(2);
 667
 668         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
 669         udelay(2);
 670
 671         retry = 0;
 672         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("reg0xec:%x:%x\n",
 673                                                 rtl_read_dword(rtlpriv, 0xEC),
 674                                                 bytetmp));
 675
 676         while ((bytetmp & BIT(0)) && retry < 1000) {
 677                 retry++;
 678                 udelay(50);
 679                 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
 680                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("reg0xec:%x:%x\n",
 681                                                         rtl_read_dword(rtlpriv,
 682                                                                        0xEC),
 683                                                         bytetmp));
 684                 udelay(50);
 685         }
 686
 687         rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012);
 688
 689         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82);
 690         udelay(2);
 691
 692         if (rtlpcipriv->bt_coexist.bt_coexistence) {
 693                 bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+2) & 0xfd;
 694                 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+2, bytetmp);
 695         }
 696
 697         rtl_write_word(rtlpriv, REG_CR, 0x2ff);
 698
 699         if (_rtl92ce_llt_table_init(hw) == false)
 700                 return false;;
 701
 702         rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
 703         rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
 704
 705         rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff);
 706
 707         wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
 708         wordtmp &= 0xf;
 709         wordtmp |= 0xF771;
 710         rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
 711
 712         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
 713         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
 714         rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
 715
 716         rtl_write_byte(rtlpriv, 0x4d0, 0x0);
 717
 718         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
 719                         ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
 720                         DMA_BIT_MASK(32));
 721         rtl_write_dword(rtlpriv, REG_MGQ_DESA,
 722                         (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
 723                         DMA_BIT_MASK(32));
 724         rtl_write_dword(rtlpriv, REG_VOQ_DESA,
 725                         (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
 726         rtl_write_dword(rtlpriv, REG_VIQ_DESA,
 727                         (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
 728         rtl_write_dword(rtlpriv, REG_BEQ_DESA,
 729                         (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
 730         rtl_write_dword(rtlpriv, REG_BKQ_DESA,
 731                         (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
 732         rtl_write_dword(rtlpriv, REG_HQ_DESA,
 733                         (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
 734                         DMA_BIT_MASK(32));
 735         rtl_write_dword(rtlpriv, REG_RX_DESA,
 736                         (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
 737                         DMA_BIT_MASK(32));
 738
 739         if (IS_92C_SERIAL(rtlhal->version))
 740                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77);
 741         else
 742                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x22);
 743
 744         rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
 745
 746         bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
 747         rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
 748         do {
 749                 retry++;
 750                 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
 751         } while ((retry < 200) && (bytetmp & BIT(7)));
 752
 753         _rtl92ce_gen_refresh_led_state(hw);
 754
 755         rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
 756
 757         return true;;
 758 }
 759
 760 static void _rtl92ce_hw_configure(struct ieee80211_hw *hw)
 761 {
 762         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 763         struct rtl_priv *rtlpriv = rtl_priv(hw);
 764         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
 765         u8 reg_bw_opmode;
 766         u32 reg_ratr, reg_prsr;
 767
 768         reg_bw_opmode = BW_OPMODE_20MHZ;
 769         reg_ratr = RATE_ALL_CCK | RATE_ALL_OFDM_AG |
 770             RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
 771         reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 772
 773         rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
 774
 775         rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
 776
 777         rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
 778
 779         rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
 780
 781         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
 782
 783         rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
 784
 785         rtl_write_word(rtlpriv, REG_RL, 0x0707);
 786
 787         rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
 788
 789         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
 790
 791         rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
 792         rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
 793         rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
 794         rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
 795
 796         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
 797             (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4))
 798                 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x97427431);
 799         else
 800                 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
 801
 802         rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
 803
 804         rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
 805
 806         rtlpci->reg_bcn_ctrl_val = 0x1f;
 807         rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
 808
 809         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
 810
 811         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
 812
 813         rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
 814         rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
 815
 816         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
 817             (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) {
 818                 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
 819                 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0402);
 820         } else {
 821                 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
 822                 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
 823         }
 824
 825         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
 826              (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4))
 827                 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
 828         else
 829                 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666);
 830
 831         rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
 832
 833         rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
 834         rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
 835
 836         rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
 837
 838         rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
 839
 840         rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
 841         rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
 842
 843 }
 844
 845 static void _rtl92ce_enable_aspm_back_door(struct ieee80211_hw *hw)
 846 {
 847         struct rtl_priv *rtlpriv = rtl_priv(hw);
 848         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 849
 850         rtl_write_byte(rtlpriv, 0x34b, 0x93);
 851         rtl_write_word(rtlpriv, 0x350, 0x870c);
 852         rtl_write_byte(rtlpriv, 0x352, 0x1);
 853
 854         if (ppsc->support_backdoor)
 855                 rtl_write_byte(rtlpriv, 0x349, 0x1b);
 856         else
 857                 rtl_write_byte(rtlpriv, 0x349, 0x03);
 858
 859         rtl_write_word(rtlpriv, 0x350, 0x2718);
 860         rtl_write_byte(rtlpriv, 0x352, 0x1);
 861 }
 862
 863 void rtl92ce_enable_hw_security_config(struct ieee80211_hw *hw)
 864 {
 865         struct rtl_priv *rtlpriv = rtl_priv(hw);
 866         u8 sec_reg_value;
 867
 868         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 869                  ("PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
 870                   rtlpriv->sec.pairwise_enc_algorithm,
 871                   rtlpriv->sec.group_enc_algorithm));
 872
 873         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
 874                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, ("not open "
 875                                                         "hw encryption\n"));
 876                 return;
 877         }
 878
 879         sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
 880
 881         if (rtlpriv->sec.use_defaultkey) {
 882                 sec_reg_value |= SCR_TxUseDK;
 883                 sec_reg_value |= SCR_RxUseDK;
 884         }
 885
 886         sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
 887
 888         rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
 889
 890         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
 891                  ("The SECR-value %x\n", sec_reg_value));
 892
 893         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
 894
 895 }
 896
 897 int rtl92ce_hw_init(struct ieee80211_hw *hw)
 898 {
 899         struct rtl_priv *rtlpriv = rtl_priv(hw);
 900         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 901         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 902         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 903         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 904         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 905         static bool iqk_initialized; /* initialized to false */
 906         bool rtstatus = true;
 907         bool is92c;
 908         int err;
 909         u8 tmp_u1b;
 910
 911         rtlpci->being_init_adapter = true;
 912         rtlpriv->intf_ops->disable_aspm(hw);
 913         rtstatus = _rtl92ce_init_mac(hw);
 914         if (rtstatus != true) {
 915                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Init MAC failed\n"));
 916                 err = 1;
 917                 return err;
 918         }
 919
 920         err = rtl92c_download_fw(hw);
 921         if (err) {
 922                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 923                          ("Failed to download FW. Init HW "
 924                           "without FW now..\n"));
 925                 err = 1;
 926                 rtlhal->fw_ready = false;
 927                 return err;
 928         } else {
 929                 rtlhal->fw_ready = true;
 930         }
 931
 932         rtlhal->last_hmeboxnum = 0;
 933 #if 0   /* temporary */
 934         rtl92c_phy_mac_config(hw);
 935         rtl92c_phy_bb_config(hw);
 936 #endif
 937         rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
 938         rtl92c_phy_rf_config(hw);
 939         rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
 940                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
 941         rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
 942                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
 943         rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
 944         rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
 945         rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
 946         _rtl92ce_hw_configure(hw);
 947         rtl_cam_reset_all_entry(hw);
 948         rtl92ce_enable_hw_security_config(hw);
 949
 950         ppsc->rfpwr_state = ERFON;
 951
 952         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
 953         _rtl92ce_enable_aspm_back_door(hw);
 954         rtlpriv->intf_ops->enable_aspm(hw);
 955
 956         rtl8192ce_bt_hw_init(hw);
 957
 958         if (ppsc->rfpwr_state == ERFON) {
 959                 rtl92c_phy_set_rfpath_switch(hw, 1);
 960                 if (iqk_initialized) {
 961                         rtl92c_phy_iq_calibrate(hw, true);
 962                 } else {
 963                         rtl92c_phy_iq_calibrate(hw, false);
 964                         iqk_initialized = true;
 965                 }
 966
 967                 rtl92c_dm_check_txpower_tracking(hw);
 968                 rtl92c_phy_lc_calibrate(hw);
 969         }
 970
 971         is92c = IS_92C_SERIAL(rtlhal->version);
 972         tmp_u1b = efuse_read_1byte(hw, 0x1FA);
 973         if (!(tmp_u1b & BIT(0))) {
 974                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
 975                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("PA BIAS path A\n"));
 976         }
 977
 978         if (!(tmp_u1b & BIT(1)) && is92c) {
 979                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05);
 980                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("PA BIAS path B\n"));
 981         }
 982
 983         if (!(tmp_u1b & BIT(4))) {
 984                 tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
 985                 tmp_u1b &= 0x0F;
 986                 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
 987                 udelay(10);
 988                 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
 989                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("under 1.5V\n"));
 990         }
 991         rtl92c_dm_init(hw);
 992         rtlpci->being_init_adapter = false;
 993         return err;
 994 }
 995
 996 static enum version_8192c _rtl92ce_read_chip_version(struct ieee80211_hw *hw)
 997 {
 998         struct rtl_priv *rtlpriv = rtl_priv(hw);
 999         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1000         enum version_8192c version = VERSION_UNKNOWN;
1001         u32 value32;
1002
1003         value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1004         if (value32 & TRP_VAUX_EN) {
1005                 version = (value32 & TYPE_ID) ? VERSION_A_CHIP_92C :
1006                            VERSION_A_CHIP_88C;
1007         } else {
1008                 version = (value32 & TYPE_ID) ? VERSION_B_CHIP_92C :
1009                            VERSION_B_CHIP_88C;
1010         }
1011
1012         switch (version) {
1013         case VERSION_B_CHIP_92C:
1014                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1015                          ("Chip Version ID: VERSION_B_CHIP_92C.\n"));
1016                 break;
1017         case VERSION_B_CHIP_88C:
1018                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1019                          ("Chip Version ID: VERSION_B_CHIP_88C.\n"));
1020                 break;
1021         case VERSION_A_CHIP_92C:
1022                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1023                          ("Chip Version ID: VERSION_A_CHIP_92C.\n"));
1024                 break;
1025         case VERSION_A_CHIP_88C:
1026                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1027                          ("Chip Version ID: VERSION_A_CHIP_88C.\n"));
1028                 break;
1029         default:
1030                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1031                          ("Chip Version ID: Unknown. Bug?\n"));
1032                 break;
1033         }
1034
1035         switch (version & 0x3) {
1036         case CHIP_88C:
1037                 rtlphy->rf_type = RF_1T1R;
1038                 break;
1039         case CHIP_92C:
1040                 rtlphy->rf_type = RF_2T2R;
1041                 break;
1042         case CHIP_92C_1T2R:
1043                 rtlphy->rf_type = RF_1T2R;
1044                 break;
1045         default:
1046                 rtlphy->rf_type = RF_1T1R;
1047                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1048                          ("ERROR RF_Type is set!!"));
1049                 break;
1050         }
1051
1052         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1053                  ("Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1054                   "RF_2T2R" : "RF_1T1R"));
1055
1056         return version;
1057 }
1058
1059 static int _rtl92ce_set_media_status(struct ieee80211_hw *hw,
1060                                      enum nl80211_iftype type)
1061 {
1062         struct rtl_priv *rtlpriv = rtl_priv(hw);
1063         u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1064         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1065         bt_msr &= 0xfc;
1066
1067         if (type == NL80211_IFTYPE_UNSPECIFIED ||
1068             type == NL80211_IFTYPE_STATION) {
1069                 _rtl92ce_stop_tx_beacon(hw);
1070                 _rtl92ce_enable_bcn_sub_func(hw);
1071         } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) {
1072                 _rtl92ce_resume_tx_beacon(hw);
1073                 _rtl92ce_disable_bcn_sub_func(hw);
1074         } else {
1075                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1076                          ("Set HW_VAR_MEDIA_STATUS: "
1077                           "No such media status(%x).\n", type));
1078         }
1079
1080         switch (type) {
1081         case NL80211_IFTYPE_UNSPECIFIED:
1082                 bt_msr |= MSR_NOLINK;
1083                 ledaction = LED_CTL_LINK;
1084                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1085                          ("Set Network type to NO LINK!\n"));
1086                 break;
1087         case NL80211_IFTYPE_ADHOC:
1088                 bt_msr |= MSR_ADHOC;
1089                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1090                          ("Set Network type to Ad Hoc!\n"));
1091                 break;
1092         case NL80211_IFTYPE_STATION:
1093                 bt_msr |= MSR_INFRA;
1094                 ledaction = LED_CTL_LINK;
1095                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1096                          ("Set Network type to STA!\n"));
1097                 break;
1098         case NL80211_IFTYPE_AP:
1099                 bt_msr |= MSR_AP;
1100                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1101                          ("Set Network type to AP!\n"));
1102                 break;
1103         default:
1104                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1105                          ("Network type %d not support!\n", type));
1106                 return 1;
1107                 break;
1108
1109         }
1110
1111         rtl_write_byte(rtlpriv, (MSR), bt_msr);
1112         rtlpriv->cfg->ops->led_control(hw, ledaction);
1113         if ((bt_msr & 0xfc) == MSR_AP)
1114                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1115         else
1116                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1117         return 0;
1118 }
1119
1120 void rtl92ce_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1121 {
1122         struct rtl_priv *rtlpriv = rtl_priv(hw);
1123         u32 reg_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1124
1125         if (rtlpriv->psc.rfpwr_state != ERFON)
1126                 return;
1127
1128         if (check_bssid == true) {
1129                 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1130                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1131                                               (u8 *) (&reg_rcr));
1132                 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
1133         } else if (check_bssid == false) {
1134                 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1135                 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
1136                 rtlpriv->cfg->ops->set_hw_reg(hw,
1137                                               HW_VAR_RCR, (u8 *) (&reg_rcr));
1138         }
1139
1140 }
1141
1142 int rtl92ce_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1143 {
1144         struct rtl_priv *rtlpriv = rtl_priv(hw);
1145
1146         if (_rtl92ce_set_media_status(hw, type))
1147                 return -EOPNOTSUPP;
1148
1149         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1150                 if (type != NL80211_IFTYPE_AP)
1151                         rtl92ce_set_check_bssid(hw, true);
1152         } else {
1153                 rtl92ce_set_check_bssid(hw, false);
1154         }
1155
1156         return 0;
1157 }
1158
1159 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1160 void rtl92ce_set_qos(struct ieee80211_hw *hw, int aci)
1161 {
1162         struct rtl_priv *rtlpriv = rtl_priv(hw);
1163         rtl92c_dm_init_edca_turbo(hw);
1164         switch (aci) {
1165         case AC1_BK:
1166                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1167                 break;
1168         case AC0_BE:
1169                 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
1170                 break;
1171         case AC2_VI:
1172                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1173                 break;
1174         case AC3_VO:
1175                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1176                 break;
1177         default:
1178                 RT_ASSERT(false, ("invalid aci: %d !\n", aci));
1179                 break;
1180         }
1181 }
1182
1183 void rtl92ce_enable_interrupt(struct ieee80211_hw *hw)
1184 {
1185         struct rtl_priv *rtlpriv = rtl_priv(hw);
1186         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1187
1188         rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1189         rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1190         rtlpci->irq_enabled = true;
1191 }
1192
1193 void rtl92ce_disable_interrupt(struct ieee80211_hw *hw)
1194 {
1195         struct rtl_priv *rtlpriv = rtl_priv(hw);
1196         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1197
1198         rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
1199         rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
1200         rtlpci->irq_enabled = false;
1201 }
1202
1203 static void _rtl92ce_poweroff_adapter(struct ieee80211_hw *hw)
1204 {
1205         struct rtl_priv *rtlpriv = rtl_priv(hw);
1206         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1207         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1208         u8 u1b_tmp;
1209         u32 u4b_tmp;
1210
1211         rtlpriv->intf_ops->enable_aspm(hw);
1212         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1213         rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1214         rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1215         rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1216         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1217         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0);
1218         if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready)
1219                 rtl92c_firmware_selfreset(hw);
1220         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51);
1221         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1222         rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000);
1223         u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL);
1224         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
1225              ((rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) ||
1226              (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC8))) {
1227                 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00F30000 |
1228                                 (u1b_tmp << 8));
1229         } else {
1230                 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00FF0000 |
1231                                 (u1b_tmp << 8));
1232         }
1233         rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790);
1234         rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1235         rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1236         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1237         if (rtlpcipriv->bt_coexist.bt_coexistence) {
1238                 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL);
1239                 u4b_tmp |= 0x03824800;
1240                 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp);
1241         } else {
1242                 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e);
1243         }
1244
1245         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1246         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10);
1247 }
1248
1249 void rtl92ce_card_disable(struct ieee80211_hw *hw)
1250 {
1251         struct rtl_priv *rtlpriv = rtl_priv(hw);
1252         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1253         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1254         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1255         enum nl80211_iftype opmode;
1256
1257         mac->link_state = MAC80211_NOLINK;
1258         opmode = NL80211_IFTYPE_UNSPECIFIED;
1259         _rtl92ce_set_media_status(hw, opmode);
1260         if (rtlpci->driver_is_goingto_unload ||
1261             ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1262                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1263         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1264         _rtl92ce_poweroff_adapter(hw);
1265 }
1266
1267 void rtl92ce_interrupt_recognized(struct ieee80211_hw *hw,
1268                                   u32 *p_inta, u32 *p_intb)
1269 {
1270         struct rtl_priv *rtlpriv = rtl_priv(hw);
1271         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1272
1273         *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1274         rtl_write_dword(rtlpriv, ISR, *p_inta);
1275
1276         /*
1277          * *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1278          * rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1279          */
1280 }
1281
1282 void rtl92ce_set_beacon_related_registers(struct ieee80211_hw *hw)
1283 {
1284
1285         struct rtl_priv *rtlpriv = rtl_priv(hw);
1286         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1287         u16 bcn_interval, atim_window;
1288
1289         bcn_interval = mac->beacon_interval;
1290         atim_window = 2;        /*FIX MERGE */
1291         rtl92ce_disable_interrupt(hw);
1292         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1293         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1294         rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1295         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1296         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1297         rtl_write_byte(rtlpriv, 0x606, 0x30);
1298         rtl92ce_enable_interrupt(hw);
1299 }
1300
1301 void rtl92ce_set_beacon_interval(struct ieee80211_hw *hw)
1302 {
1303         struct rtl_priv *rtlpriv = rtl_priv(hw);
1304         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1305         u16 bcn_interval = mac->beacon_interval;
1306
1307         RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1308                  ("beacon_interval:%d\n", bcn_interval));
1309         rtl92ce_disable_interrupt(hw);
1310         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1311         rtl92ce_enable_interrupt(hw);
1312 }
1313
1314 void rtl92ce_update_interrupt_mask(struct ieee80211_hw *hw,
1315                                    u32 add_msr, u32 rm_msr)
1316 {
1317         struct rtl_priv *rtlpriv = rtl_priv(hw);
1318         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1319
1320         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1321                  ("add_msr:%x, rm_msr:%x\n", add_msr, rm_msr));
1322
1323         if (add_msr)
1324                 rtlpci->irq_mask[0] |= add_msr;
1325         if (rm_msr)
1326                 rtlpci->irq_mask[0] &= (~rm_msr);
1327         rtl92ce_disable_interrupt(hw);
1328         rtl92ce_enable_interrupt(hw);
1329 }
1330
1331 static void _rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1332                                                  bool autoload_fail,
1333                                                  u8 *hwinfo)
1334 {
1335         struct rtl_priv *rtlpriv = rtl_priv(hw);
1336         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1337         u8 rf_path, index, tempval;
1338         u16 i;
1339
1340         for (rf_path = 0; rf_path < 2; rf_path++) {
1341                 for (i = 0; i < 3; i++) {
1342                         if (!autoload_fail) {
1343                                 rtlefuse->
1344                                     eeprom_chnlarea_txpwr_cck[rf_path][i] =
1345                                     hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
1346                                 rtlefuse->
1347                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1348                                     hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
1349                                            i];
1350                         } else {
1351                                 rtlefuse->
1352                                     eeprom_chnlarea_txpwr_cck[rf_path][i] =
1353                                     EEPROM_DEFAULT_TXPOWERLEVEL;
1354                                 rtlefuse->
1355                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1356                                     EEPROM_DEFAULT_TXPOWERLEVEL;
1357                         }
1358                 }
1359         }
1360
1361         for (i = 0; i < 3; i++) {
1362                 if (!autoload_fail)
1363                         tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
1364                 else
1365                         tempval = EEPROM_DEFAULT_HT40_2SDIFF;
1366                 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_A][i] =
1367                     (tempval & 0xf);
1368                 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_B][i] =
1369                     ((tempval & 0xf0) >> 4);
1370         }
1371
1372         for (rf_path = 0; rf_path < 2; rf_path++)
1373                 for (i = 0; i < 3; i++)
1374                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1375                                 ("RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path,
1376                                  i,
1377                                  rtlefuse->
1378                                  eeprom_chnlarea_txpwr_cck[rf_path][i]));
1379         for (rf_path = 0; rf_path < 2; rf_path++)
1380                 for (i = 0; i < 3; i++)
1381                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1382                                 ("RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1383                                  rf_path, i,
1384                                  rtlefuse->
1385                                  eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]));
1386         for (rf_path = 0; rf_path < 2; rf_path++)
1387                 for (i = 0; i < 3; i++)
1388                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1389                                 ("RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1390                                  rf_path, i,
1391                                  rtlefuse->
1392                                  eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path]
1393                                  [i]));
1394
1395         for (rf_path = 0; rf_path < 2; rf_path++) {
1396                 for (i = 0; i < 14; i++) {
1397                         index = _rtl92c_get_chnl_group((u8) i);
1398
1399                         rtlefuse->txpwrlevel_cck[rf_path][i] =
1400                             rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
1401                         rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1402                             rtlefuse->
1403                             eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
1404
1405                         if ((rtlefuse->
1406                              eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
1407                              rtlefuse->
1408                              eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path][index])
1409                             > 0) {
1410                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
1411                                     rtlefuse->
1412                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path]
1413                                     [index] -
1414                                     rtlefuse->
1415                                     eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path]
1416                                     [index];
1417                         } else {
1418                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
1419                         }
1420                 }
1421
1422                 for (i = 0; i < 14; i++) {
1423                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1424                                 ("RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = "
1425                                  "[0x%x / 0x%x / 0x%x]\n", rf_path, i,
1426                                  rtlefuse->txpwrlevel_cck[rf_path][i],
1427                                  rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1428                                  rtlefuse->txpwrlevel_ht40_2s[rf_path][i]));
1429                 }
1430         }
1431
1432         for (i = 0; i < 3; i++) {
1433                 if (!autoload_fail) {
1434                         rtlefuse->eeprom_pwrlimit_ht40[i] =
1435                             hwinfo[EEPROM_TXPWR_GROUP + i];
1436                         rtlefuse->eeprom_pwrlimit_ht20[i] =
1437                             hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
1438                 } else {
1439                         rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
1440                         rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
1441                 }
1442         }
1443
1444         for (rf_path = 0; rf_path < 2; rf_path++) {
1445                 for (i = 0; i < 14; i++) {
1446                         index = _rtl92c_get_chnl_group((u8) i);
1447
1448                         if (rf_path == RF90_PATH_A) {
1449                                 rtlefuse->pwrgroup_ht20[rf_path][i] =
1450                                     (rtlefuse->eeprom_pwrlimit_ht20[index]
1451                                      & 0xf);
1452                                 rtlefuse->pwrgroup_ht40[rf_path][i] =
1453                                     (rtlefuse->eeprom_pwrlimit_ht40[index]
1454                                      & 0xf);
1455                         } else if (rf_path == RF90_PATH_B) {
1456                                 rtlefuse->pwrgroup_ht20[rf_path][i] =
1457                                     ((rtlefuse->eeprom_pwrlimit_ht20[index]
1458                                       & 0xf0) >> 4);
1459                                 rtlefuse->pwrgroup_ht40[rf_path][i] =
1460                                     ((rtlefuse->eeprom_pwrlimit_ht40[index]
1461                                       & 0xf0) >> 4);
1462                         }
1463
1464                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1465                                 ("RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1466                                  rf_path, i,
1467                                  rtlefuse->pwrgroup_ht20[rf_path][i]));
1468                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1469                                 ("RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1470                                  rf_path, i,
1471                                  rtlefuse->pwrgroup_ht40[rf_path][i]));
1472                 }
1473         }
1474
1475         for (i = 0; i < 14; i++) {
1476                 index = _rtl92c_get_chnl_group((u8) i);
1477
1478                 if (!autoload_fail)
1479                         tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
1480                 else
1481                         tempval = EEPROM_DEFAULT_HT20_DIFF;
1482
1483                 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1484                 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1485                     ((tempval >> 4) & 0xF);
1486
1487                 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
1488                         rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
1489
1490                 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
1491                         rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
1492
1493                 index = _rtl92c_get_chnl_group((u8) i);
1494
1495                 if (!autoload_fail)
1496                         tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
1497                 else
1498                         tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1499
1500                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
1501                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1502                     ((tempval >> 4) & 0xF);
1503         }
1504
1505         rtlefuse->legacy_ht_txpowerdiff =
1506             rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
1507
1508         for (i = 0; i < 14; i++)
1509                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1510                         ("RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1511                          rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]));
1512         for (i = 0; i < 14; i++)
1513                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1514                         ("RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i,
1515                          rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]));
1516         for (i = 0; i < 14; i++)
1517                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1518                         ("RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1519                          rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]));
1520         for (i = 0; i < 14; i++)
1521                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1522                         ("RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i,
1523                          rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]));
1524
1525         if (!autoload_fail)
1526                 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
1527         else
1528                 rtlefuse->eeprom_regulatory = 0;
1529         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1530                 ("eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory));
1531
1532         if (!autoload_fail) {
1533                 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
1534                 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
1535         } else {
1536                 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
1537                 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
1538         }
1539         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1540                 ("TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1541                  rtlefuse->eeprom_tssi[RF90_PATH_A],
1542                  rtlefuse->eeprom_tssi[RF90_PATH_B]));
1543
1544         if (!autoload_fail)
1545                 tempval = hwinfo[EEPROM_THERMAL_METER];
1546         else
1547                 tempval = EEPROM_DEFAULT_THERMALMETER;
1548         rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
1549
1550         if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
1551                 rtlefuse->apk_thermalmeterignore = true;
1552
1553         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1554         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1555                 ("thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter));
1556 }
1557
1558 static void _rtl92ce_read_adapter_info(struct ieee80211_hw *hw)
1559 {
1560         struct rtl_priv *rtlpriv = rtl_priv(hw);
1561         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1562         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1563         u16 i, usvalue;
1564         u8 hwinfo[HWSET_MAX_SIZE];
1565         u16 eeprom_id;
1566
1567         if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1568                 rtl_efuse_shadow_map_update(hw);
1569
1570                 memcpy((void *)hwinfo,
1571                        (void *)&rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1572                        HWSET_MAX_SIZE);
1573         } else if (rtlefuse->epromtype == EEPROM_93C46) {
1574                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1575                          ("RTL819X Not boot from eeprom, check it !!"));
1576         }
1577
1578         RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, ("MAP\n"),
1579                       hwinfo, HWSET_MAX_SIZE);
1580
1581         eeprom_id = *((u16 *)&hwinfo[0]);
1582         if (eeprom_id != RTL8190_EEPROM_ID) {
1583                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1584                          ("EEPROM ID(%#x) is invalid!!\n", eeprom_id));
1585                 rtlefuse->autoload_failflag = true;
1586         } else {
1587                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
1588                 rtlefuse->autoload_failflag = false;
1589         }
1590
1591         if (rtlefuse->autoload_failflag == true)
1592                 return;
1593
1594         for (i = 0; i < 6; i += 2) {
1595                 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1596                 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1597         }
1598
1599         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1600                  (MAC_FMT "\n", MAC_ARG(rtlefuse->dev_addr)));
1601
1602         _rtl92ce_read_txpower_info_from_hwpg(hw,
1603                                              rtlefuse->autoload_failflag,
1604                                              hwinfo);
1605
1606         rtl8192ce_read_bt_coexist_info_from_hwpg(hw,
1607                                                  rtlefuse->autoload_failflag,
1608                                                  hwinfo);
1609
1610         rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
1611         rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1612         rtlefuse->txpwr_fromeprom = true;
1613         rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID];
1614
1615         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1616                  ("EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid));
1617
1618         /* set channel paln to world wide 13 */
1619         rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
1620
1621         if (rtlhal->oem_id == RT_CID_DEFAULT) {
1622                 switch (rtlefuse->eeprom_oemid) {
1623                 case EEPROM_CID_DEFAULT:
1624                         if (rtlefuse->eeprom_did == 0x8176) {
1625                                 if ((rtlefuse->eeprom_svid == 0x103C &&
1626                                      rtlefuse->eeprom_smid == 0x1629))
1627                                         rtlhal->oem_id = RT_CID_819x_HP;
1628                                 else
1629                                         rtlhal->oem_id = RT_CID_DEFAULT;
1630                         } else {
1631                                 rtlhal->oem_id = RT_CID_DEFAULT;
1632                         }
1633                         break;
1634                 case EEPROM_CID_TOSHIBA:
1635                         rtlhal->oem_id = RT_CID_TOSHIBA;
1636                         break;
1637                 case EEPROM_CID_QMI:
1638                         rtlhal->oem_id = RT_CID_819x_QMI;
1639                         break;
1640                 case EEPROM_CID_WHQL:
1641                 default:
1642                         rtlhal->oem_id = RT_CID_DEFAULT;
1643                         break;
1644
1645                 }
1646         }
1647
1648 }
1649
1650 static void _rtl92ce_hal_customized_behavior(struct ieee80211_hw *hw)
1651 {
1652         struct rtl_priv *rtlpriv = rtl_priv(hw);
1653         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1654         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1655
1656         switch (rtlhal->oem_id) {
1657         case RT_CID_819x_HP:
1658                 pcipriv->ledctl.led_opendrain = true;
1659                 break;
1660         case RT_CID_819x_Lenovo:
1661         case RT_CID_DEFAULT:
1662         case RT_CID_TOSHIBA:
1663         case RT_CID_CCX:
1664         case RT_CID_819x_Acer:
1665         case RT_CID_WHQL:
1666         default:
1667                 break;
1668         }
1669         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1670                  ("RT Customized ID: 0x%02X\n", rtlhal->oem_id));
1671 }
1672
1673 void rtl92ce_read_eeprom_info(struct ieee80211_hw *hw)
1674 {
1675         struct rtl_priv *rtlpriv = rtl_priv(hw);
1676         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1677         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1678         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1679         u8 tmp_u1b;
1680
1681         rtlhal->version = _rtl92ce_read_chip_version(hw);
1682         if (get_rf_type(rtlphy) == RF_1T1R)
1683                 rtlpriv->dm.rfpath_rxenable[0] = true;
1684         else
1685                 rtlpriv->dm.rfpath_rxenable[0] =
1686                     rtlpriv->dm.rfpath_rxenable[1] = true;
1687         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("VersionID = 0x%4x\n",
1688                                                 rtlhal->version));
1689         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1690         if (tmp_u1b & BIT(4)) {
1691                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from EEPROM\n"));
1692                 rtlefuse->epromtype = EEPROM_93C46;
1693         } else {
1694                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from EFUSE\n"));
1695                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1696         }
1697         if (tmp_u1b & BIT(5)) {
1698                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
1699                 rtlefuse->autoload_failflag = false;
1700                 _rtl92ce_read_adapter_info(hw);
1701         } else {
1702                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Autoload ERR!!\n"));
1703         }
1704         _rtl92ce_hal_customized_behavior(hw);
1705 }
1706
1707 static void rtl92ce_update_hal_rate_table(struct ieee80211_hw *hw,
1708                 struct ieee80211_sta *sta)
1709 {
1710         struct rtl_priv *rtlpriv = rtl_priv(hw);
1711         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1712         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1713         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1714         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1715         u32 ratr_value;
1716         u8 ratr_index = 0;
1717         u8 nmode = mac->ht_enable;
1718         u8 mimo_ps = IEEE80211_SMPS_OFF;
1719         u16 shortgi_rate;
1720         u32 tmp_ratr_value;
1721         u8 curtxbw_40mhz = mac->bw_40;
1722         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1723                                1 : 0;
1724         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1725                                1 : 0;
1726         enum wireless_mode wirelessmode = mac->mode;
1727
1728         if (rtlhal->current_bandtype == BAND_ON_5G)
1729                 ratr_value = sta->supp_rates[1] << 4;
1730         else
1731                 ratr_value = sta->supp_rates[0];
1732         ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1733                         sta->ht_cap.mcs.rx_mask[0] << 12);
1734         switch (wirelessmode) {
1735         case WIRELESS_MODE_B:
1736                 if (ratr_value & 0x0000000c)
1737                         ratr_value &= 0x0000000d;
1738                 else
1739                         ratr_value &= 0x0000000f;
1740                 break;
1741         case WIRELESS_MODE_G:
1742                 ratr_value &= 0x00000FF5;
1743                 break;
1744         case WIRELESS_MODE_N_24G:
1745         case WIRELESS_MODE_N_5G:
1746                 nmode = 1;
1747                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1748                         ratr_value &= 0x0007F005;
1749                 } else {
1750                         u32 ratr_mask;
1751
1752                         if (get_rf_type(rtlphy) == RF_1T2R ||
1753                             get_rf_type(rtlphy) == RF_1T1R)
1754                                 ratr_mask = 0x000ff005;
1755                         else
1756                                 ratr_mask = 0x0f0ff005;
1757
1758                         ratr_value &= ratr_mask;
1759                 }
1760                 break;
1761         default:
1762                 if (rtlphy->rf_type == RF_1T2R)
1763                         ratr_value &= 0x000ff0ff;
1764                 else
1765                         ratr_value &= 0x0f0ff0ff;
1766
1767                 break;
1768         }
1769
1770         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
1771             (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) &&
1772             (rtlpcipriv->bt_coexist.bt_cur_state) &&
1773             (rtlpcipriv->bt_coexist.bt_ant_isolation) &&
1774             ((rtlpcipriv->bt_coexist.bt_service == BT_SCO) ||
1775             (rtlpcipriv->bt_coexist.bt_service == BT_BUSY)))
1776                 ratr_value &= 0x0fffcfc0;
1777         else
1778                 ratr_value &= 0x0FFFFFFF;
1779
1780         if (nmode && ((curtxbw_40mhz &&
1781                          curshortgi_40mhz) || (!curtxbw_40mhz &&
1782                                                curshortgi_20mhz))) {
1783
1784                 ratr_value |= 0x10000000;
1785                 tmp_ratr_value = (ratr_value >> 12);
1786
1787                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
1788                         if ((1 << shortgi_rate) & tmp_ratr_value)
1789                                 break;
1790                 }
1791
1792                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
1793                     (shortgi_rate << 4) | (shortgi_rate);
1794         }
1795
1796         rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1797
1798         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
1799                  ("%x\n", rtl_read_dword(rtlpriv, REG_ARFR0)));
1800 }
1801
1802 static void rtl92ce_update_hal_rate_mask(struct ieee80211_hw *hw,
1803                 struct ieee80211_sta *sta, u8 rssi_level)
1804 {
1805         struct rtl_priv *rtlpriv = rtl_priv(hw);
1806         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1807         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1808         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1809         struct rtl_sta_info *sta_entry = NULL;
1810         u32 ratr_bitmap;
1811         u8 ratr_index;
1812         u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
1813                                 ? 1 : 0;
1814         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1815                                 1 : 0;
1816         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1817                                 1 : 0;
1818         enum wireless_mode wirelessmode = 0;
1819         bool shortgi = false;
1820         u8 rate_mask[5];
1821         u8 macid = 0;
1822         u8 mimo_ps = IEEE80211_SMPS_OFF;
1823
1824         sta_entry = (struct rtl_sta_info *) sta->drv_priv;
1825         wirelessmode = sta_entry->wireless_mode;
1826         if (mac->opmode == NL80211_IFTYPE_STATION)
1827                 curtxbw_40mhz = mac->bw_40;
1828         else if (mac->opmode == NL80211_IFTYPE_AP ||
1829                 mac->opmode == NL80211_IFTYPE_ADHOC)
1830                 macid = sta->aid + 1;
1831
1832         if (rtlhal->current_bandtype == BAND_ON_5G)
1833                 ratr_bitmap = sta->supp_rates[1] << 4;
1834         else
1835                 ratr_bitmap = sta->supp_rates[0];
1836         ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1837                         sta->ht_cap.mcs.rx_mask[0] << 12);
1838         switch (wirelessmode) {
1839         case WIRELESS_MODE_B:
1840                 ratr_index = RATR_INX_WIRELESS_B;
1841                 if (ratr_bitmap & 0x0000000c)
1842                         ratr_bitmap &= 0x0000000d;
1843                 else
1844                         ratr_bitmap &= 0x0000000f;
1845                 break;
1846         case WIRELESS_MODE_G:
1847                 ratr_index = RATR_INX_WIRELESS_GB;
1848
1849                 if (rssi_level == 1)
1850                         ratr_bitmap &= 0x00000f00;
1851                 else if (rssi_level == 2)
1852                         ratr_bitmap &= 0x00000ff0;
1853                 else
1854                         ratr_bitmap &= 0x00000ff5;
1855                 break;
1856         case WIRELESS_MODE_A:
1857                 ratr_index = RATR_INX_WIRELESS_A;
1858                 ratr_bitmap &= 0x00000ff0;
1859                 break;
1860         case WIRELESS_MODE_N_24G:
1861         case WIRELESS_MODE_N_5G:
1862                 ratr_index = RATR_INX_WIRELESS_NGB;
1863
1864                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1865                         if (rssi_level == 1)
1866                                 ratr_bitmap &= 0x00070000;
1867                         else if (rssi_level == 2)
1868                                 ratr_bitmap &= 0x0007f000;
1869                         else
1870                                 ratr_bitmap &= 0x0007f005;
1871                 } else {
1872                         if (rtlphy->rf_type == RF_1T2R ||
1873                             rtlphy->rf_type == RF_1T1R) {
1874                                 if (curtxbw_40mhz) {
1875                                         if (rssi_level == 1)
1876                                                 ratr_bitmap &= 0x000f0000;
1877                                         else if (rssi_level == 2)
1878                                                 ratr_bitmap &= 0x000ff000;
1879                                         else
1880                                                 ratr_bitmap &= 0x000ff015;
1881                                 } else {
1882                                         if (rssi_level == 1)
1883                                                 ratr_bitmap &= 0x000f0000;
1884                                         else if (rssi_level == 2)
1885                                                 ratr_bitmap &= 0x000ff000;
1886                                         else
1887                                                 ratr_bitmap &= 0x000ff005;
1888                                 }
1889                         } else {
1890                                 if (curtxbw_40mhz) {
1891                                         if (rssi_level == 1)
1892                                                 ratr_bitmap &= 0x0f0f0000;
1893                                         else if (rssi_level == 2)
1894                                                 ratr_bitmap &= 0x0f0ff000;
1895                                         else
1896                                                 ratr_bitmap &= 0x0f0ff015;
1897                                 } else {
1898                                         if (rssi_level == 1)
1899                                                 ratr_bitmap &= 0x0f0f0000;
1900                                         else if (rssi_level == 2)
1901                                                 ratr_bitmap &= 0x0f0ff000;
1902                                         else
1903                                                 ratr_bitmap &= 0x0f0ff005;
1904                                 }
1905                         }
1906                 }
1907
1908                 if ((curtxbw_40mhz && curshortgi_40mhz) ||
1909                     (!curtxbw_40mhz && curshortgi_20mhz)) {
1910
1911                         if (macid == 0)
1912                                 shortgi = true;
1913                         else if (macid == 1)
1914                                 shortgi = false;
1915                 }
1916                 break;
1917         default:
1918                 ratr_index = RATR_INX_WIRELESS_NGB;
1919
1920                 if (rtlphy->rf_type == RF_1T2R)
1921                         ratr_bitmap &= 0x000ff0ff;
1922                 else
1923                         ratr_bitmap &= 0x0f0ff0ff;
1924                 break;
1925         }
1926         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
1927                  ("ratr_bitmap :%x\n", ratr_bitmap));
1928         *(u32 *)&rate_mask = EF4BYTE((ratr_bitmap & 0x0fffffff) |
1929                                      (ratr_index << 28));
1930         rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
1931         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, ("Rate_index:%x, "
1932                                                  "ratr_val:%x, %x:%x:%x:%x:%x\n",
1933                                                  ratr_index, ratr_bitmap,
1934                                                  rate_mask[0], rate_mask[1],
1935                                                  rate_mask[2], rate_mask[3],
1936                                                  rate_mask[4]));
1937         rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
1938
1939         if (macid != 0)
1940                 sta_entry->ratr_index = ratr_index;
1941 }
1942
1943 void rtl92ce_update_hal_rate_tbl(struct ieee80211_hw *hw,
1944                 struct ieee80211_sta *sta, u8 rssi_level)
1945 {
1946         struct rtl_priv *rtlpriv = rtl_priv(hw);
1947
1948         if (rtlpriv->dm.useramask)
1949                 rtl92ce_update_hal_rate_mask(hw, sta, rssi_level);
1950         else
1951                 rtl92ce_update_hal_rate_table(hw, sta);
1952 }
1953
1954 void rtl92ce_update_channel_access_setting(struct ieee80211_hw *hw)
1955 {
1956         struct rtl_priv *rtlpriv = rtl_priv(hw);
1957         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1958         u16 sifs_timer;
1959
1960         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
1961                                       (u8 *)&mac->slot_time);
1962         if (!mac->ht_enable)
1963                 sifs_timer = 0x0a0a;
1964         else
1965                 sifs_timer = 0x1010;
1966         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
1967 }
1968
1969 bool rtl92ce_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
1970 {
1971         struct rtl_priv *rtlpriv = rtl_priv(hw);
1972         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1973         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1974         enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
1975         u8 u1tmp;
1976         bool actuallyset = false;
1977         unsigned long flag;
1978
1979         if (rtlpci->being_init_adapter)
1980                 return false;
1981
1982         if (ppsc->swrf_processing)
1983                 return false;
1984
1985         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
1986         if (ppsc->rfchange_inprogress) {
1987                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
1988                 return false;
1989         } else {
1990                 ppsc->rfchange_inprogress = true;
1991                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
1992         }
1993
1994         cur_rfstate = ppsc->rfpwr_state;
1995
1996         rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv,
1997                        REG_MAC_PINMUX_CFG)&~(BIT(3)));
1998
1999         u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2000         e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF;
2001
2002         if ((ppsc->hwradiooff == true) && (e_rfpowerstate_toset == ERFON)) {
2003                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2004                          ("GPIOChangeRF  - HW Radio ON, RF ON\n"));
2005
2006                 e_rfpowerstate_toset = ERFON;
2007                 ppsc->hwradiooff = false;
2008                 actuallyset = true;
2009         } else if ((ppsc->hwradiooff == false)
2010                    && (e_rfpowerstate_toset == ERFOFF)) {
2011                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2012                          ("GPIOChangeRF  - HW Radio OFF, RF OFF\n"));
2013
2014                 e_rfpowerstate_toset = ERFOFF;
2015                 ppsc->hwradiooff = true;
2016                 actuallyset = true;
2017         }
2018
2019         if (actuallyset) {
2020                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2021                 ppsc->rfchange_inprogress = false;
2022                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2023         } else {
2024                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2025                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2026
2027                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2028                 ppsc->rfchange_inprogress = false;
2029                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2030         }
2031
2032         *valid = 1;
2033         return !ppsc->hwradiooff;
2034
2035 }
2036
2037 void rtl92ce_set_key(struct ieee80211_hw *hw, u32 key_index,
2038                      u8 *p_macaddr, bool is_group, u8 enc_algo,
2039                      bool is_wepkey, bool clear_all)
2040 {
2041         struct rtl_priv *rtlpriv = rtl_priv(hw);
2042         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2043         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2044         u8 *macaddr = p_macaddr;
2045         u32 entry_id = 0;
2046         bool is_pairwise = false;
2047
2048         static u8 cam_const_addr[4][6] = {
2049                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2050                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2051                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2052                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2053         };
2054         static u8 cam_const_broad[] = {
2055                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2056         };
2057
2058         if (clear_all) {
2059                 u8 idx = 0;
2060                 u8 cam_offset = 0;
2061                 u8 clear_number = 5;
2062
2063                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, ("clear_all\n"));
2064
2065                 for (idx = 0; idx < clear_number; idx++) {
2066                         rtl_cam_mark_invalid(hw, cam_offset + idx);
2067                         rtl_cam_empty_entry(hw, cam_offset + idx);
2068
2069                         if (idx < 5) {
2070                                 memset(rtlpriv->sec.key_buf[idx], 0,
2071                                        MAX_KEY_LEN);
2072                                 rtlpriv->sec.key_len[idx] = 0;
2073                         }
2074                 }
2075
2076         } else {
2077                 switch (enc_algo) {
2078                 case WEP40_ENCRYPTION:
2079                         enc_algo = CAM_WEP40;
2080                         break;
2081                 case WEP104_ENCRYPTION:
2082                         enc_algo = CAM_WEP104;
2083                         break;
2084                 case TKIP_ENCRYPTION:
2085                         enc_algo = CAM_TKIP;
2086                         break;
2087                 case AESCCMP_ENCRYPTION:
2088                         enc_algo = CAM_AES;
2089                         break;
2090                 default:
2091                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("switch case "
2092                                         "not process\n"));
2093                         enc_algo = CAM_TKIP;
2094                         break;
2095                 }
2096
2097                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2098                         macaddr = cam_const_addr[key_index];
2099                         entry_id = key_index;
2100                 } else {
2101                         if (is_group) {
2102                                 macaddr = cam_const_broad;
2103                                 entry_id = key_index;
2104                         } else {
2105                                 if (mac->opmode == NL80211_IFTYPE_AP) {
2106                                         entry_id = rtl_cam_get_free_entry(hw,
2107                                                                  p_macaddr);
2108                                         if (entry_id >=  TOTAL_CAM_ENTRY) {
2109                                                 RT_TRACE(rtlpriv, COMP_SEC,
2110                                                      DBG_EMERG,
2111                                                      ("Can not find free hw"
2112                                                      " security cam entry\n"));
2113                                                 return;
2114                                         }
2115                                 } else {
2116                                         entry_id = CAM_PAIRWISE_KEY_POSITION;
2117                                 }
2118
2119                                 key_index = PAIRWISE_KEYIDX;
2120                                 is_pairwise = true;
2121                         }
2122                 }
2123
2124                 if (rtlpriv->sec.key_len[key_index] == 0) {
2125                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2126                                  ("delete one entry, entry_id is %d\n",
2127                                  entry_id));
2128                         if (mac->opmode == NL80211_IFTYPE_AP)
2129                                 rtl_cam_del_entry(hw, p_macaddr);
2130                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2131                 } else {
2132                         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2133                                  ("The insert KEY length is %d\n",
2134                                   rtlpriv->sec.key_len[PAIRWISE_KEYIDX]));
2135                         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2136                                  ("The insert KEY  is %x %x\n",
2137                                   rtlpriv->sec.key_buf[0][0],
2138                                   rtlpriv->sec.key_buf[0][1]));
2139
2140                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2141                                  ("add one entry\n"));
2142                         if (is_pairwise) {
2143                                 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2144                                               "Pairwiase Key content :",
2145                                               rtlpriv->sec.pairwise_key,
2146                                               rtlpriv->sec.
2147                                               key_len[PAIRWISE_KEYIDX]);
2148
2149                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2150                                          ("set Pairwiase key\n"));
2151
2152                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2153                                                       entry_id, enc_algo,
2154                                                       CAM_CONFIG_NO_USEDK,
2155                                                       rtlpriv->sec.
2156                                                       key_buf[key_index]);
2157                         } else {
2158                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2159                                          ("set group key\n"));
2160
2161                                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2162                                         rtl_cam_add_one_entry(hw,
2163                                                 rtlefuse->dev_addr,
2164                                                 PAIRWISE_KEYIDX,
2165                                                 CAM_PAIRWISE_KEY_POSITION,
2166                                                 enc_algo,
2167                                                 CAM_CONFIG_NO_USEDK,
2168                                                 rtlpriv->sec.key_buf
2169                                                 [entry_id]);
2170                                 }
2171
2172                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2173                                                 entry_id, enc_algo,
2174                                                 CAM_CONFIG_NO_USEDK,
2175                                                 rtlpriv->sec.key_buf[entry_id]);
2176                         }
2177
2178                 }
2179         }
2180 }
2181
2182 void rtl8192ce_bt_var_init(struct ieee80211_hw *hw)
2183 {
2184         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2185
2186         rtlpcipriv->bt_coexist.bt_coexistence =
2187                         rtlpcipriv->bt_coexist.eeprom_bt_coexist;
2188         rtlpcipriv->bt_coexist.bt_ant_num =
2189                         rtlpcipriv->bt_coexist.eeprom_bt_ant_num;
2190         rtlpcipriv->bt_coexist.bt_coexist_type =
2191                         rtlpcipriv->bt_coexist.eeprom_bt_type;
2192
2193         if (rtlpcipriv->bt_coexist.reg_bt_iso == 2)
2194                 rtlpcipriv->bt_coexist.bt_ant_isolation =
2195                         rtlpcipriv->bt_coexist.eeprom_bt_ant_isolation;
2196         else
2197                 rtlpcipriv->bt_coexist.bt_ant_isolation =
2198                         rtlpcipriv->bt_coexist.reg_bt_iso;
2199
2200         rtlpcipriv->bt_coexist.bt_radio_shared_type =
2201                         rtlpcipriv->bt_coexist.eeprom_bt_radio_shared;
2202
2203         if (rtlpcipriv->bt_coexist.bt_coexistence) {
2204
2205                 if (rtlpcipriv->bt_coexist.reg_bt_sco == 1)
2206                         rtlpcipriv->bt_coexist.bt_service = BT_OTHER_ACTION;
2207                 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 2)
2208                         rtlpcipriv->bt_coexist.bt_service = BT_SCO;
2209                 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 4)
2210                         rtlpcipriv->bt_coexist.bt_service = BT_BUSY;
2211                 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 5)
2212                         rtlpcipriv->bt_coexist.bt_service = BT_OTHERBUSY;
2213                 else
2214                         rtlpcipriv->bt_coexist.bt_service = BT_IDLE;
2215
2216                 rtlpcipriv->bt_coexist.bt_edca_ul = 0;
2217                 rtlpcipriv->bt_coexist.bt_edca_dl = 0;
2218                 rtlpcipriv->bt_coexist.bt_rssi_state = 0xff;
2219         }
2220 }
2221
2222 void rtl8192ce_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2223                                               bool auto_load_fail, u8 *hwinfo)
2224 {
2225         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2226         u8 value;
2227
2228         if (!auto_load_fail) {
2229                 rtlpcipriv->bt_coexist.eeprom_bt_coexist =
2230                                         ((hwinfo[RF_OPTION1] & 0xe0) >> 5);
2231                 value = hwinfo[RF_OPTION4];
2232                 rtlpcipriv->bt_coexist.eeprom_bt_type = ((value & 0xe) >> 1);
2233                 rtlpcipriv->bt_coexist.eeprom_bt_ant_num = (value & 0x1);
2234                 rtlpcipriv->bt_coexist.eeprom_bt_ant_isolation =
2235                                                          ((value & 0x10) >> 4);
2236                 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared =
2237                                                          ((value & 0x20) >> 5);
2238         } else {
2239                 rtlpcipriv->bt_coexist.eeprom_bt_coexist = 0;
2240                 rtlpcipriv->bt_coexist.eeprom_bt_type = BT_2WIRE;
2241                 rtlpcipriv->bt_coexist.eeprom_bt_ant_num = ANT_X2;
2242                 rtlpcipriv->bt_coexist.eeprom_bt_ant_isolation = 0;
2243                 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared = BT_RADIO_SHARED;
2244         }
2245
2246         rtl8192ce_bt_var_init(hw);
2247 }
2248
2249 void rtl8192ce_bt_reg_init(struct ieee80211_hw *hw)
2250 {
2251         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2252
2253         /* 0:Low, 1:High, 2:From Efuse. */
2254         rtlpcipriv->bt_coexist.reg_bt_iso = 2;
2255         /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2256         rtlpcipriv->bt_coexist.reg_bt_sco = 3;
2257         /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2258         rtlpcipriv->bt_coexist.reg_bt_sco = 0;
2259 }
2260
2261
2262 void rtl8192ce_bt_hw_init(struct ieee80211_hw *hw)
2263 {
2264         struct rtl_priv *rtlpriv = rtl_priv(hw);
2265         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2266         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2267
2268         u8 u1_tmp;
2269
2270         if (rtlpcipriv->bt_coexist.bt_coexistence &&
2271             ((rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) ||
2272               rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC8)) {
2273
2274                 if (rtlpcipriv->bt_coexist.bt_ant_isolation)
2275                         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
2276
2277                 u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) &
2278                          BIT_OFFSET_LEN_MASK_32(0, 1);
2279                 u1_tmp = u1_tmp |
2280                          ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ?
2281                          0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
2282                          ((rtlpcipriv->bt_coexist.bt_service == BT_SCO) ?
2283                          0 : BIT_OFFSET_LEN_MASK_32(2, 1));
2284                 rtl_write_byte(rtlpriv, 0x4fd, u1_tmp);
2285
2286                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
2287                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040);
2288                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010);
2289
2290                 /* Config to 1T1R. */
2291                 if (rtlphy->rf_type == RF_1T1R) {
2292                         u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE);
2293                         u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2294                         rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp);
2295
2296                         u1_tmp = rtl_read_byte(rtlpriv, ROFDM1_TRXPATHENABLE);
2297                         u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2298                         rtl_write_byte(rtlpriv, ROFDM1_TRXPATHENABLE, u1_tmp);
2299                 }
2300         }
2301 }
2302
2303 void rtl92ce_suspend(struct ieee80211_hw *hw)
2304 {
2305 }
2306
2307 void rtl92ce_resume(struct ieee80211_hw *hw)
2308 {
2309 }