Pileus Git - ~andy/linux/blob - drivers/net/wireless/rt2x00/rt73usb.c

   1 /*
   2         Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt73usb
  23         Abstract: rt73usb device specific routines.
  24         Supported chipsets: rt2571W & rt2671.
  25  */
  26
  27 #include <linux/crc-itu-t.h>
  28 #include <linux/delay.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/init.h>
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/slab.h>
  34 #include <linux/usb.h>
  35
  36 #include "rt2x00.h"
  37 #include "rt2x00usb.h"
  38 #include "rt73usb.h"
  39
  40 /*
  41  * Allow hardware encryption to be disabled.
  42  */
  43 static int modparam_nohwcrypt;
  44 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  45 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  46
  47 /*
  48  * Register access.
  49  * All access to the CSR registers will go through the methods
  50  * rt2x00usb_register_read and rt2x00usb_register_write.
  51  * BBP and RF register require indirect register access,
  52  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  53  * These indirect registers work with busy bits,
  54  * and we will try maximal REGISTER_BUSY_COUNT times to access
  55  * the register while taking a REGISTER_BUSY_DELAY us delay
  56  * between each attampt. When the busy bit is still set at that time,
  57  * the access attempt is considered to have failed,
  58  * and we will print an error.
  59  * The _lock versions must be used if you already hold the csr_mutex
  60  */
  61 #define WAIT_FOR_BBP(__dev, __reg) \
  62         rt2x00usb_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
  63 #define WAIT_FOR_RF(__dev, __reg) \
  64         rt2x00usb_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
  65
  66 static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
  67                               const unsigned int word, const u8 value)
  68 {
  69         u32 reg;
  70
  71         mutex_lock(&rt2x00dev->csr_mutex);
  72
  73         /*
  74          * Wait until the BBP becomes available, afterwards we
  75          * can safely write the new data into the register.
  76          */
  77         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  78                 reg = 0;
  79                 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
  80                 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
  81                 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
  82                 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
  83
  84                 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
  85         }
  86
  87         mutex_unlock(&rt2x00dev->csr_mutex);
  88 }
  89
  90 static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
  91                              const unsigned int word, u8 *value)
  92 {
  93         u32 reg;
  94
  95         mutex_lock(&rt2x00dev->csr_mutex);
  96
  97         /*
  98          * Wait until the BBP becomes available, afterwards we
  99          * can safely write the read request into the register.
 100          * After the data has been written, we wait until hardware
 101          * returns the correct value, if at any time the register
 102          * doesn't become available in time, reg will be 0xffffffff
 103          * which means we return 0xff to the caller.
 104          */
 105         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 106                 reg = 0;
 107                 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
 108                 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
 109                 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
 110
 111                 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
 112
 113                 WAIT_FOR_BBP(rt2x00dev, &reg);
 114         }
 115
 116         *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
 117
 118         mutex_unlock(&rt2x00dev->csr_mutex);
 119 }
 120
 121 static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
 122                              const unsigned int word, const u32 value)
 123 {
 124         u32 reg;
 125
 126         mutex_lock(&rt2x00dev->csr_mutex);
 127
 128         /*
 129          * Wait until the RF becomes available, afterwards we
 130          * can safely write the new data into the register.
 131          */
 132         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 133                 reg = 0;
 134                 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
 135                 /*
 136                  * RF5225 and RF2527 contain 21 bits per RF register value,
 137                  * all others contain 20 bits.
 138                  */
 139                 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
 140                                    20 + (rt2x00_rf(rt2x00dev, RF5225) ||
 141                                          rt2x00_rf(rt2x00dev, RF2527)));
 142                 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
 143                 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
 144
 145                 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
 146                 rt2x00_rf_write(rt2x00dev, word, value);
 147         }
 148
 149         mutex_unlock(&rt2x00dev->csr_mutex);
 150 }
 151
 152 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 153 static const struct rt2x00debug rt73usb_rt2x00debug = {
 154         .owner  = THIS_MODULE,
 155         .csr    = {
 156                 .read           = rt2x00usb_register_read,
 157                 .write          = rt2x00usb_register_write,
 158                 .flags          = RT2X00DEBUGFS_OFFSET,
 159                 .word_base      = CSR_REG_BASE,
 160                 .word_size      = sizeof(u32),
 161                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 162         },
 163         .eeprom = {
 164                 .read           = rt2x00_eeprom_read,
 165                 .write          = rt2x00_eeprom_write,
 166                 .word_base      = EEPROM_BASE,
 167                 .word_size      = sizeof(u16),
 168                 .word_count     = EEPROM_SIZE / sizeof(u16),
 169         },
 170         .bbp    = {
 171                 .read           = rt73usb_bbp_read,
 172                 .write          = rt73usb_bbp_write,
 173                 .word_base      = BBP_BASE,
 174                 .word_size      = sizeof(u8),
 175                 .word_count     = BBP_SIZE / sizeof(u8),
 176         },
 177         .rf     = {
 178                 .read           = rt2x00_rf_read,
 179                 .write          = rt73usb_rf_write,
 180                 .word_base      = RF_BASE,
 181                 .word_size      = sizeof(u32),
 182                 .word_count     = RF_SIZE / sizeof(u32),
 183         },
 184 };
 185 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 186
 187 static int rt73usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 188 {
 189         u32 reg;
 190
 191         rt2x00usb_register_read(rt2x00dev, MAC_CSR13, &reg);
 192         return rt2x00_get_field32(reg, MAC_CSR13_BIT7);
 193 }
 194
 195 #ifdef CONFIG_RT2X00_LIB_LEDS
 196 static void rt73usb_brightness_set(struct led_classdev *led_cdev,
 197                                    enum led_brightness brightness)
 198 {
 199         struct rt2x00_led *led =
 200            container_of(led_cdev, struct rt2x00_led, led_dev);
 201         unsigned int enabled = brightness != LED_OFF;
 202         unsigned int a_mode =
 203             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
 204         unsigned int bg_mode =
 205             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 206
 207         if (led->type == LED_TYPE_RADIO) {
 208                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 209                                    MCU_LEDCS_RADIO_STATUS, enabled);
 210
 211                 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
 212                                             0, led->rt2x00dev->led_mcu_reg,
 213                                             REGISTER_TIMEOUT);
 214         } else if (led->type == LED_TYPE_ASSOC) {
 215                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 216                                    MCU_LEDCS_LINK_BG_STATUS, bg_mode);
 217                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 218                                    MCU_LEDCS_LINK_A_STATUS, a_mode);
 219
 220                 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
 221                                             0, led->rt2x00dev->led_mcu_reg,
 222                                             REGISTER_TIMEOUT);
 223         } else if (led->type == LED_TYPE_QUALITY) {
 224                 /*
 225                  * The brightness is divided into 6 levels (0 - 5),
 226                  * this means we need to convert the brightness
 227                  * argument into the matching level within that range.
 228                  */
 229                 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
 230                                             brightness / (LED_FULL / 6),
 231                                             led->rt2x00dev->led_mcu_reg,
 232                                             REGISTER_TIMEOUT);
 233         }
 234 }
 235
 236 static int rt73usb_blink_set(struct led_classdev *led_cdev,
 237                              unsigned long *delay_on,
 238                              unsigned long *delay_off)
 239 {
 240         struct rt2x00_led *led =
 241             container_of(led_cdev, struct rt2x00_led, led_dev);
 242         u32 reg;
 243
 244         rt2x00usb_register_read(led->rt2x00dev, MAC_CSR14, &reg);
 245         rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
 246         rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
 247         rt2x00usb_register_write(led->rt2x00dev, MAC_CSR14, reg);
 248
 249         return 0;
 250 }
 251
 252 static void rt73usb_init_led(struct rt2x00_dev *rt2x00dev,
 253                              struct rt2x00_led *led,
 254                              enum led_type type)
 255 {
 256         led->rt2x00dev = rt2x00dev;
 257         led->type = type;
 258         led->led_dev.brightness_set = rt73usb_brightness_set;
 259         led->led_dev.blink_set = rt73usb_blink_set;
 260         led->flags = LED_INITIALIZED;
 261 }
 262 #endif /* CONFIG_RT2X00_LIB_LEDS */
 263
 264 /*
 265  * Configuration handlers.
 266  */
 267 static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
 268                                      struct rt2x00lib_crypto *crypto,
 269                                      struct ieee80211_key_conf *key)
 270 {
 271         struct hw_key_entry key_entry;
 272         struct rt2x00_field32 field;
 273         u32 mask;
 274         u32 reg;
 275
 276         if (crypto->cmd == SET_KEY) {
 277                 /*
 278                  * rt2x00lib can't determine the correct free
 279                  * key_idx for shared keys. We have 1 register
 280                  * with key valid bits. The goal is simple, read
 281                  * the register, if that is full we have no slots
 282                  * left.
 283                  * Note that each BSS is allowed to have up to 4
 284                  * shared keys, so put a mask over the allowed
 285                  * entries.
 286                  */
 287                 mask = (0xf << crypto->bssidx);
 288
 289                 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
 290                 reg &= mask;
 291
 292                 if (reg && reg == mask)
 293                         return -ENOSPC;
 294
 295                 key->hw_key_idx += reg ? ffz(reg) : 0;
 296
 297                 /*
 298                  * Upload key to hardware
 299                  */
 300                 memcpy(key_entry.key, crypto->key,
 301                        sizeof(key_entry.key));
 302                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 303                        sizeof(key_entry.tx_mic));
 304                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 305                        sizeof(key_entry.rx_mic));
 306
 307                 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
 308                 rt2x00usb_register_multiwrite(rt2x00dev, reg,
 309                                               &key_entry, sizeof(key_entry));
 310
 311                 /*
 312                  * The cipher types are stored over 2 registers.
 313                  * bssidx 0 and 1 keys are stored in SEC_CSR1 and
 314                  * bssidx 1 and 2 keys are stored in SEC_CSR5.
 315                  * Using the correct defines correctly will cause overhead,
 316                  * so just calculate the correct offset.
 317                  */
 318                 if (key->hw_key_idx < 8) {
 319                         field.bit_offset = (3 * key->hw_key_idx);
 320                         field.bit_mask = 0x7 << field.bit_offset;
 321
 322                         rt2x00usb_register_read(rt2x00dev, SEC_CSR1, &reg);
 323                         rt2x00_set_field32(&reg, field, crypto->cipher);
 324                         rt2x00usb_register_write(rt2x00dev, SEC_CSR1, reg);
 325                 } else {
 326                         field.bit_offset = (3 * (key->hw_key_idx - 8));
 327                         field.bit_mask = 0x7 << field.bit_offset;
 328
 329                         rt2x00usb_register_read(rt2x00dev, SEC_CSR5, &reg);
 330                         rt2x00_set_field32(&reg, field, crypto->cipher);
 331                         rt2x00usb_register_write(rt2x00dev, SEC_CSR5, reg);
 332                 }
 333
 334                 /*
 335                  * The driver does not support the IV/EIV generation
 336                  * in hardware. However it doesn't support the IV/EIV
 337                  * inside the ieee80211 frame either, but requires it
 338                  * to be provided separately for the descriptor.
 339                  * rt2x00lib will cut the IV/EIV data out of all frames
 340                  * given to us by mac80211, but we must tell mac80211
 341                  * to generate the IV/EIV data.
 342                  */
 343                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 344         }
 345
 346         /*
 347          * SEC_CSR0 contains only single-bit fields to indicate
 348          * a particular key is valid. Because using the FIELD32()
 349          * defines directly will cause a lot of overhead we use
 350          * a calculation to determine the correct bit directly.
 351          */
 352         mask = 1 << key->hw_key_idx;
 353
 354         rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
 355         if (crypto->cmd == SET_KEY)
 356                 reg |= mask;
 357         else if (crypto->cmd == DISABLE_KEY)
 358                 reg &= ~mask;
 359         rt2x00usb_register_write(rt2x00dev, SEC_CSR0, reg);
 360
 361         return 0;
 362 }
 363
 364 static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 365                                        struct rt2x00lib_crypto *crypto,
 366                                        struct ieee80211_key_conf *key)
 367 {
 368         struct hw_pairwise_ta_entry addr_entry;
 369         struct hw_key_entry key_entry;
 370         u32 mask;
 371         u32 reg;
 372
 373         if (crypto->cmd == SET_KEY) {
 374                 /*
 375                  * rt2x00lib can't determine the correct free
 376                  * key_idx for pairwise keys. We have 2 registers
 377                  * with key valid bits. The goal is simple, read
 378                  * the first register, if that is full move to
 379                  * the next register.
 380                  * When both registers are full, we drop the key,
 381                  * otherwise we use the first invalid entry.
 382                  */
 383                 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
 384                 if (reg && reg == ~0) {
 385                         key->hw_key_idx = 32;
 386                         rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
 387                         if (reg && reg == ~0)
 388                                 return -ENOSPC;
 389                 }
 390
 391                 key->hw_key_idx += reg ? ffz(reg) : 0;
 392
 393                 /*
 394                  * Upload key to hardware
 395                  */
 396                 memcpy(key_entry.key, crypto->key,
 397                        sizeof(key_entry.key));
 398                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 399                        sizeof(key_entry.tx_mic));
 400                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 401                        sizeof(key_entry.rx_mic));
 402
 403                 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 404                 rt2x00usb_register_multiwrite(rt2x00dev, reg,
 405                                               &key_entry, sizeof(key_entry));
 406
 407                 /*
 408                  * Send the address and cipher type to the hardware register.
 409                  */
 410                 memset(&addr_entry, 0, sizeof(addr_entry));
 411                 memcpy(&addr_entry, crypto->address, ETH_ALEN);
 412                 addr_entry.cipher = crypto->cipher;
 413
 414                 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
 415                 rt2x00usb_register_multiwrite(rt2x00dev, reg,
 416                                             &addr_entry, sizeof(addr_entry));
 417
 418                 /*
 419                  * Enable pairwise lookup table for given BSS idx,
 420                  * without this received frames will not be decrypted
 421                  * by the hardware.
 422                  */
 423                 rt2x00usb_register_read(rt2x00dev, SEC_CSR4, &reg);
 424                 reg |= (1 << crypto->bssidx);
 425                 rt2x00usb_register_write(rt2x00dev, SEC_CSR4, reg);
 426
 427                 /*
 428                  * The driver does not support the IV/EIV generation
 429                  * in hardware. However it doesn't support the IV/EIV
 430                  * inside the ieee80211 frame either, but requires it
 431                  * to be provided separately for the descriptor.
 432                  * rt2x00lib will cut the IV/EIV data out of all frames
 433                  * given to us by mac80211, but we must tell mac80211
 434                  * to generate the IV/EIV data.
 435                  */
 436                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 437         }
 438
 439         /*
 440          * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
 441          * a particular key is valid. Because using the FIELD32()
 442          * defines directly will cause a lot of overhead we use
 443          * a calculation to determine the correct bit directly.
 444          */
 445         if (key->hw_key_idx < 32) {
 446                 mask = 1 << key->hw_key_idx;
 447
 448                 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
 449                 if (crypto->cmd == SET_KEY)
 450                         reg |= mask;
 451                 else if (crypto->cmd == DISABLE_KEY)
 452                         reg &= ~mask;
 453                 rt2x00usb_register_write(rt2x00dev, SEC_CSR2, reg);
 454         } else {
 455                 mask = 1 << (key->hw_key_idx - 32);
 456
 457                 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
 458                 if (crypto->cmd == SET_KEY)
 459                         reg |= mask;
 460                 else if (crypto->cmd == DISABLE_KEY)
 461                         reg &= ~mask;
 462                 rt2x00usb_register_write(rt2x00dev, SEC_CSR3, reg);
 463         }
 464
 465         return 0;
 466 }
 467
 468 static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev,
 469                                   const unsigned int filter_flags)
 470 {
 471         u32 reg;
 472
 473         /*
 474          * Start configuration steps.
 475          * Note that the version error will always be dropped
 476          * and broadcast frames will always be accepted since
 477          * there is no filter for it at this time.
 478          */
 479         rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
 480         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
 481                            !(filter_flags & FIF_FCSFAIL));
 482         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
 483                            !(filter_flags & FIF_PLCPFAIL));
 484         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
 485                            !(filter_flags & (FIF_CONTROL | FIF_PSPOLL)));
 486         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
 487                            !(filter_flags & FIF_PROMISC_IN_BSS));
 488         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
 489                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
 490                            !rt2x00dev->intf_ap_count);
 491         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
 492         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
 493                            !(filter_flags & FIF_ALLMULTI));
 494         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
 495         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
 496                            !(filter_flags & FIF_CONTROL));
 497         rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
 498 }
 499
 500 static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
 501                                 struct rt2x00_intf *intf,
 502                                 struct rt2x00intf_conf *conf,
 503                                 const unsigned int flags)
 504 {
 505         unsigned int beacon_base;
 506         u32 reg;
 507
 508         if (flags & CONFIG_UPDATE_TYPE) {
 509                 /*
 510                  * Clear current synchronisation setup.
 511                  * For the Beacon base registers we only need to clear
 512                  * the first byte since that byte contains the VALID and OWNER
 513                  * bits which (when set to 0) will invalidate the entire beacon.
 514                  */
 515                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 516                 rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
 517
 518                 /*
 519                  * Enable synchronisation.
 520                  */
 521                 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
 522                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
 523                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
 524                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
 525                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
 526         }
 527
 528         if (flags & CONFIG_UPDATE_MAC) {
 529                 reg = le32_to_cpu(conf->mac[1]);
 530                 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
 531                 conf->mac[1] = cpu_to_le32(reg);
 532
 533                 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR2,
 534                                             conf->mac, sizeof(conf->mac));
 535         }
 536
 537         if (flags & CONFIG_UPDATE_BSSID) {
 538                 reg = le32_to_cpu(conf->bssid[1]);
 539                 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
 540                 conf->bssid[1] = cpu_to_le32(reg);
 541
 542                 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR4,
 543                                             conf->bssid, sizeof(conf->bssid));
 544         }
 545 }
 546
 547 static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev,
 548                                struct rt2x00lib_erp *erp,
 549                                u32 changed)
 550 {
 551         u32 reg;
 552
 553         rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
 554         rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32);
 555         rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
 556         rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
 557
 558         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
 559                 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
 560                 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
 561                 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
 562                                    !!erp->short_preamble);
 563                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
 564         }
 565
 566         if (changed & BSS_CHANGED_BASIC_RATES)
 567                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR5,
 568                                          erp->basic_rates);
 569
 570         if (changed & BSS_CHANGED_BEACON_INT) {
 571                 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
 572                 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
 573                                    erp->beacon_int * 16);
 574                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
 575         }
 576
 577         if (changed & BSS_CHANGED_ERP_SLOT) {
 578                 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
 579                 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
 580                 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
 581
 582                 rt2x00usb_register_read(rt2x00dev, MAC_CSR8, &reg);
 583                 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
 584                 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
 585                 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
 586                 rt2x00usb_register_write(rt2x00dev, MAC_CSR8, reg);
 587         }
 588 }
 589
 590 static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
 591                                       struct antenna_setup *ant)
 592 {
 593         u8 r3;
 594         u8 r4;
 595         u8 r77;
 596         u8 temp;
 597
 598         rt73usb_bbp_read(rt2x00dev, 3, &r3);
 599         rt73usb_bbp_read(rt2x00dev, 4, &r4);
 600         rt73usb_bbp_read(rt2x00dev, 77, &r77);
 601
 602         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
 603
 604         /*
 605          * Configure the RX antenna.
 606          */
 607         switch (ant->rx) {
 608         case ANTENNA_HW_DIVERSITY:
 609                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 610                 temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)
 611                        && (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ);
 612                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
 613                 break;
 614         case ANTENNA_A:
 615                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 616                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 617                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 618                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 619                 else
 620                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 621                 break;
 622         case ANTENNA_B:
 623         default:
 624                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 625                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 626                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 627                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 628                 else
 629                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 630                 break;
 631         }
 632
 633         rt73usb_bbp_write(rt2x00dev, 77, r77);
 634         rt73usb_bbp_write(rt2x00dev, 3, r3);
 635         rt73usb_bbp_write(rt2x00dev, 4, r4);
 636 }
 637
 638 static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
 639                                       struct antenna_setup *ant)
 640 {
 641         u8 r3;
 642         u8 r4;
 643         u8 r77;
 644
 645         rt73usb_bbp_read(rt2x00dev, 3, &r3);
 646         rt73usb_bbp_read(rt2x00dev, 4, &r4);
 647         rt73usb_bbp_read(rt2x00dev, 77, &r77);
 648
 649         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
 650         rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
 651                           !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
 652
 653         /*
 654          * Configure the RX antenna.
 655          */
 656         switch (ant->rx) {
 657         case ANTENNA_HW_DIVERSITY:
 658                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 659                 break;
 660         case ANTENNA_A:
 661                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 662                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 663                 break;
 664         case ANTENNA_B:
 665         default:
 666                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 667                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 668                 break;
 669         }
 670
 671         rt73usb_bbp_write(rt2x00dev, 77, r77);
 672         rt73usb_bbp_write(rt2x00dev, 3, r3);
 673         rt73usb_bbp_write(rt2x00dev, 4, r4);
 674 }
 675
 676 struct antenna_sel {
 677         u8 word;
 678         /*
 679          * value[0] -> non-LNA
 680          * value[1] -> LNA
 681          */
 682         u8 value[2];
 683 };
 684
 685 static const struct antenna_sel antenna_sel_a[] = {
 686         { 96,  { 0x58, 0x78 } },
 687         { 104, { 0x38, 0x48 } },
 688         { 75,  { 0xfe, 0x80 } },
 689         { 86,  { 0xfe, 0x80 } },
 690         { 88,  { 0xfe, 0x80 } },
 691         { 35,  { 0x60, 0x60 } },
 692         { 97,  { 0x58, 0x58 } },
 693         { 98,  { 0x58, 0x58 } },
 694 };
 695
 696 static const struct antenna_sel antenna_sel_bg[] = {
 697         { 96,  { 0x48, 0x68 } },
 698         { 104, { 0x2c, 0x3c } },
 699         { 75,  { 0xfe, 0x80 } },
 700         { 86,  { 0xfe, 0x80 } },
 701         { 88,  { 0xfe, 0x80 } },
 702         { 35,  { 0x50, 0x50 } },
 703         { 97,  { 0x48, 0x48 } },
 704         { 98,  { 0x48, 0x48 } },
 705 };
 706
 707 static void rt73usb_config_ant(struct rt2x00_dev *rt2x00dev,
 708                                struct antenna_setup *ant)
 709 {
 710         const struct antenna_sel *sel;
 711         unsigned int lna;
 712         unsigned int i;
 713         u32 reg;
 714
 715         /*
 716          * We should never come here because rt2x00lib is supposed
 717          * to catch this and send us the correct antenna explicitely.
 718          */
 719         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 720                ant->tx == ANTENNA_SW_DIVERSITY);
 721
 722         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
 723                 sel = antenna_sel_a;
 724                 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
 725         } else {
 726                 sel = antenna_sel_bg;
 727                 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
 728         }
 729
 730         for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
 731                 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
 732
 733         rt2x00usb_register_read(rt2x00dev, PHY_CSR0, &reg);
 734
 735         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
 736                            (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ));
 737         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
 738                            (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ));
 739
 740         rt2x00usb_register_write(rt2x00dev, PHY_CSR0, reg);
 741
 742         if (rt2x00_rf(rt2x00dev, RF5226) || rt2x00_rf(rt2x00dev, RF5225))
 743                 rt73usb_config_antenna_5x(rt2x00dev, ant);
 744         else if (rt2x00_rf(rt2x00dev, RF2528) || rt2x00_rf(rt2x00dev, RF2527))
 745                 rt73usb_config_antenna_2x(rt2x00dev, ant);
 746 }
 747
 748 static void rt73usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 749                                     struct rt2x00lib_conf *libconf)
 750 {
 751         u16 eeprom;
 752         short lna_gain = 0;
 753
 754         if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
 755                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
 756                         lna_gain += 14;
 757
 758                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
 759                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
 760         } else {
 761                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
 762                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
 763         }
 764
 765         rt2x00dev->lna_gain = lna_gain;
 766 }
 767
 768 static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
 769                                    struct rf_channel *rf, const int txpower)
 770 {
 771         u8 r3;
 772         u8 r94;
 773         u8 smart;
 774
 775         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 776         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 777
 778         smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527));
 779
 780         rt73usb_bbp_read(rt2x00dev, 3, &r3);
 781         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
 782         rt73usb_bbp_write(rt2x00dev, 3, r3);
 783
 784         r94 = 6;
 785         if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
 786                 r94 += txpower - MAX_TXPOWER;
 787         else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
 788                 r94 += txpower;
 789         rt73usb_bbp_write(rt2x00dev, 94, r94);
 790
 791         rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
 792         rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
 793         rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 794         rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
 795
 796         rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
 797         rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
 798         rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 799         rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
 800
 801         rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
 802         rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
 803         rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 804         rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
 805
 806         udelay(10);
 807 }
 808
 809 static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
 810                                    const int txpower)
 811 {
 812         struct rf_channel rf;
 813
 814         rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
 815         rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
 816         rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
 817         rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
 818
 819         rt73usb_config_channel(rt2x00dev, &rf, txpower);
 820 }
 821
 822 static void rt73usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 823                                        struct rt2x00lib_conf *libconf)
 824 {
 825         u32 reg;
 826
 827         rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
 828         rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1);
 829         rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_STEP, 0);
 830         rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0);
 831         rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
 832                            libconf->conf->long_frame_max_tx_count);
 833         rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
 834                            libconf->conf->short_frame_max_tx_count);
 835         rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
 836 }
 837
 838 static void rt73usb_config_ps(struct rt2x00_dev *rt2x00dev,
 839                                 struct rt2x00lib_conf *libconf)
 840 {
 841         enum dev_state state =
 842             (libconf->conf->flags & IEEE80211_CONF_PS) ?
 843                 STATE_SLEEP : STATE_AWAKE;
 844         u32 reg;
 845
 846         if (state == STATE_SLEEP) {
 847                 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg);
 848                 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
 849                                    rt2x00dev->beacon_int - 10);
 850                 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
 851                                    libconf->conf->listen_interval - 1);
 852                 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
 853
 854                 /* We must first disable autowake before it can be enabled */
 855                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
 856                 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
 857
 858                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
 859                 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
 860
 861                 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
 862                                             USB_MODE_SLEEP, REGISTER_TIMEOUT);
 863         } else {
 864                 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg);
 865                 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
 866                 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
 867                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
 868                 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
 869                 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
 870
 871                 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
 872                                             USB_MODE_WAKEUP, REGISTER_TIMEOUT);
 873         }
 874 }
 875
 876 static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
 877                            struct rt2x00lib_conf *libconf,
 878                            const unsigned int flags)
 879 {
 880         /* Always recalculate LNA gain before changing configuration */
 881         rt73usb_config_lna_gain(rt2x00dev, libconf);
 882
 883         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
 884                 rt73usb_config_channel(rt2x00dev, &libconf->rf,
 885                                        libconf->conf->power_level);
 886         if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
 887             !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
 888                 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
 889         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
 890                 rt73usb_config_retry_limit(rt2x00dev, libconf);
 891         if (flags & IEEE80211_CONF_CHANGE_PS)
 892                 rt73usb_config_ps(rt2x00dev, libconf);
 893 }
 894
 895 /*
 896  * Link tuning
 897  */
 898 static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
 899                                struct link_qual *qual)
 900 {
 901         u32 reg;
 902
 903         /*
 904          * Update FCS error count from register.
 905          */
 906         rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
 907         qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
 908
 909         /*
 910          * Update False CCA count from register.
 911          */
 912         rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
 913         qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
 914 }
 915
 916 static inline void rt73usb_set_vgc(struct rt2x00_dev *rt2x00dev,
 917                                    struct link_qual *qual, u8 vgc_level)
 918 {
 919         if (qual->vgc_level != vgc_level) {
 920                 rt73usb_bbp_write(rt2x00dev, 17, vgc_level);
 921                 qual->vgc_level = vgc_level;
 922                 qual->vgc_level_reg = vgc_level;
 923         }
 924 }
 925
 926 static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
 927                                 struct link_qual *qual)
 928 {
 929         rt73usb_set_vgc(rt2x00dev, qual, 0x20);
 930 }
 931
 932 static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev,
 933                                struct link_qual *qual, const u32 count)
 934 {
 935         u8 up_bound;
 936         u8 low_bound;
 937
 938         /*
 939          * Determine r17 bounds.
 940          */
 941         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
 942                 low_bound = 0x28;
 943                 up_bound = 0x48;
 944
 945                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
 946                         low_bound += 0x10;
 947                         up_bound += 0x10;
 948                 }
 949         } else {
 950                 if (qual->rssi > -82) {
 951                         low_bound = 0x1c;
 952                         up_bound = 0x40;
 953                 } else if (qual->rssi > -84) {
 954                         low_bound = 0x1c;
 955                         up_bound = 0x20;
 956                 } else {
 957                         low_bound = 0x1c;
 958                         up_bound = 0x1c;
 959                 }
 960
 961                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
 962                         low_bound += 0x14;
 963                         up_bound += 0x10;
 964                 }
 965         }
 966
 967         /*
 968          * If we are not associated, we should go straight to the
 969          * dynamic CCA tuning.
 970          */
 971         if (!rt2x00dev->intf_associated)
 972                 goto dynamic_cca_tune;
 973
 974         /*
 975          * Special big-R17 for very short distance
 976          */
 977         if (qual->rssi > -35) {
 978                 rt73usb_set_vgc(rt2x00dev, qual, 0x60);
 979                 return;
 980         }
 981
 982         /*
 983          * Special big-R17 for short distance
 984          */
 985         if (qual->rssi >= -58) {
 986                 rt73usb_set_vgc(rt2x00dev, qual, up_bound);
 987                 return;
 988         }
 989
 990         /*
 991          * Special big-R17 for middle-short distance
 992          */
 993         if (qual->rssi >= -66) {
 994                 rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x10);
 995                 return;
 996         }
 997
 998         /*
 999          * Special mid-R17 for middle distance
1000          */
1001         if (qual->rssi >= -74) {
1002                 rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x08);
1003                 return;
1004         }
1005
1006         /*
1007          * Special case: Change up_bound based on the rssi.
1008          * Lower up_bound when rssi is weaker then -74 dBm.
1009          */
1010         up_bound -= 2 * (-74 - qual->rssi);
1011         if (low_bound > up_bound)
1012                 up_bound = low_bound;
1013
1014         if (qual->vgc_level > up_bound) {
1015                 rt73usb_set_vgc(rt2x00dev, qual, up_bound);
1016                 return;
1017         }
1018
1019 dynamic_cca_tune:
1020
1021         /*
1022          * r17 does not yet exceed upper limit, continue and base
1023          * the r17 tuning on the false CCA count.
1024          */
1025         if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
1026                 rt73usb_set_vgc(rt2x00dev, qual,
1027                                 min_t(u8, qual->vgc_level + 4, up_bound));
1028         else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
1029                 rt73usb_set_vgc(rt2x00dev, qual,
1030                                 max_t(u8, qual->vgc_level - 4, low_bound));
1031 }
1032
1033 /*
1034  * Firmware functions
1035  */
1036 static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1037 {
1038         return FIRMWARE_RT2571;
1039 }
1040
1041 static int rt73usb_check_firmware(struct rt2x00_dev *rt2x00dev,
1042                                   const u8 *data, const size_t len)
1043 {
1044         u16 fw_crc;
1045         u16 crc;
1046
1047         /*
1048          * Only support 2kb firmware files.
1049          */
1050         if (len != 2048)
1051                 return FW_BAD_LENGTH;
1052
1053         /*
1054          * The last 2 bytes in the firmware array are the crc checksum itself,
1055          * this means that we should never pass those 2 bytes to the crc
1056          * algorithm.
1057          */
1058         fw_crc = (data[len - 2] << 8 | data[len - 1]);
1059
1060         /*
1061          * Use the crc itu-t algorithm.
1062          */
1063         crc = crc_itu_t(0, data, len - 2);
1064         crc = crc_itu_t_byte(crc, 0);
1065         crc = crc_itu_t_byte(crc, 0);
1066
1067         return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
1068 }
1069
1070 static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1071                                  const u8 *data, const size_t len)
1072 {
1073         unsigned int i;
1074         int status;
1075         u32 reg;
1076
1077         /*
1078          * Wait for stable hardware.
1079          */
1080         for (i = 0; i < 100; i++) {
1081                 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1082                 if (reg)
1083                         break;
1084                 msleep(1);
1085         }
1086
1087         if (!reg) {
1088                 ERROR(rt2x00dev, "Unstable hardware.\n");
1089                 return -EBUSY;
1090         }
1091
1092         /*
1093          * Write firmware to device.
1094          */
1095         rt2x00usb_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE, data, len);
1096
1097         /*
1098          * Send firmware request to device to load firmware,
1099          * we need to specify a long timeout time.
1100          */
1101         status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
1102                                              0, USB_MODE_FIRMWARE,
1103                                              REGISTER_TIMEOUT_FIRMWARE);
1104         if (status < 0) {
1105                 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
1106                 return status;
1107         }
1108
1109         return 0;
1110 }
1111
1112 /*
1113  * Initialization functions.
1114  */
1115 static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
1116 {
1117         u32 reg;
1118
1119         rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1120         rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1121         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1122         rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1123         rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1124
1125         rt2x00usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
1126         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1127         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1128         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1129         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1130         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1131         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1132         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1133         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1134         rt2x00usb_register_write(rt2x00dev, TXRX_CSR1, reg);
1135
1136         /*
1137          * CCK TXD BBP registers
1138          */
1139         rt2x00usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
1140         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1141         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1142         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1143         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1144         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1145         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1146         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1147         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1148         rt2x00usb_register_write(rt2x00dev, TXRX_CSR2, reg);
1149
1150         /*
1151          * OFDM TXD BBP registers
1152          */
1153         rt2x00usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
1154         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1155         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1156         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1157         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1158         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1159         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1160         rt2x00usb_register_write(rt2x00dev, TXRX_CSR3, reg);
1161
1162         rt2x00usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
1163         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1164         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1165         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1166         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1167         rt2x00usb_register_write(rt2x00dev, TXRX_CSR7, reg);
1168
1169         rt2x00usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
1170         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1171         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1172         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1173         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1174         rt2x00usb_register_write(rt2x00dev, TXRX_CSR8, reg);
1175
1176         rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1177         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1178         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1179         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1180         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1181         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1182         rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1183         rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1184
1185         rt2x00usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1186
1187         rt2x00usb_register_read(rt2x00dev, MAC_CSR6, &reg);
1188         rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
1189         rt2x00usb_register_write(rt2x00dev, MAC_CSR6, reg);
1190
1191         rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
1192
1193         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1194                 return -EBUSY;
1195
1196         rt2x00usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
1197
1198         /*
1199          * Invalidate all Shared Keys (SEC_CSR0),
1200          * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1201          */
1202         rt2x00usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1203         rt2x00usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1204         rt2x00usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1205
1206         reg = 0x000023b0;
1207         if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527))
1208                 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
1209         rt2x00usb_register_write(rt2x00dev, PHY_CSR1, reg);
1210
1211         rt2x00usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1212         rt2x00usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1213         rt2x00usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
1214
1215         rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
1216         rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1217         rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
1218
1219         /*
1220          * Clear all beacons
1221          * For the Beacon base registers we only need to clear
1222          * the first byte since that byte contains the VALID and OWNER
1223          * bits which (when set to 0) will invalidate the entire beacon.
1224          */
1225         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1226         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1227         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1228         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1229
1230         /*
1231          * We must clear the error counters.
1232          * These registers are cleared on read,
1233          * so we may pass a useless variable to store the value.
1234          */
1235         rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
1236         rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
1237         rt2x00usb_register_read(rt2x00dev, STA_CSR2, &reg);
1238
1239         /*
1240          * Reset MAC and BBP registers.
1241          */
1242         rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1243         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1244         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1245         rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1246
1247         rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1248         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1249         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1250         rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1251
1252         rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1253         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1254         rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1255
1256         return 0;
1257 }
1258
1259 static int rt73usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1260 {
1261         unsigned int i;
1262         u8 value;
1263
1264         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1265                 rt73usb_bbp_read(rt2x00dev, 0, &value);
1266                 if ((value != 0xff) && (value != 0x00))
1267                         return 0;
1268                 udelay(REGISTER_BUSY_DELAY);
1269         }
1270
1271         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1272         return -EACCES;
1273 }
1274
1275 static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1276 {
1277         unsigned int i;
1278         u16 eeprom;
1279         u8 reg_id;
1280         u8 value;
1281
1282         if (unlikely(rt73usb_wait_bbp_ready(rt2x00dev)))
1283                 return -EACCES;
1284
1285         rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1286         rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1287         rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1288         rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1289         rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1290         rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1291         rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1292         rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1293         rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1294         rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1295         rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1296         rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1297         rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1298         rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1299         rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1300         rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1301         rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1302         rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1303         rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1304         rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1305         rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1306         rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1307         rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1308         rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1309         rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1310
1311         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1312                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1313
1314                 if (eeprom != 0xffff && eeprom != 0x0000) {
1315                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1316                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1317                         rt73usb_bbp_write(rt2x00dev, reg_id, value);
1318                 }
1319         }
1320
1321         return 0;
1322 }
1323
1324 /*
1325  * Device state switch handlers.
1326  */
1327 static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1328                               enum dev_state state)
1329 {
1330         u32 reg;
1331
1332         rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1333         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1334                            (state == STATE_RADIO_RX_OFF));
1335         rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1336 }
1337
1338 static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1339 {
1340         /*
1341          * Initialize all registers.
1342          */
1343         if (unlikely(rt73usb_init_registers(rt2x00dev) ||
1344                      rt73usb_init_bbp(rt2x00dev)))
1345                 return -EIO;
1346
1347         return 0;
1348 }
1349
1350 static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1351 {
1352         rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1353
1354         /*
1355          * Disable synchronisation.
1356          */
1357         rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1358
1359         rt2x00usb_disable_radio(rt2x00dev);
1360 }
1361
1362 static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1363 {
1364         u32 reg, reg2;
1365         unsigned int i;
1366         char put_to_sleep;
1367
1368         put_to_sleep = (state != STATE_AWAKE);
1369
1370         rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1371         rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1372         rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1373         rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg);
1374
1375         /*
1376          * Device is not guaranteed to be in the requested state yet.
1377          * We must wait until the register indicates that the
1378          * device has entered the correct state.
1379          */
1380         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1381                 rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg2);
1382                 state = rt2x00_get_field32(reg2, MAC_CSR12_BBP_CURRENT_STATE);
1383                 if (state == !put_to_sleep)
1384                         return 0;
1385                 rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg);
1386                 msleep(10);
1387         }
1388
1389         return -EBUSY;
1390 }
1391
1392 static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1393                                     enum dev_state state)
1394 {
1395         int retval = 0;
1396
1397         switch (state) {
1398         case STATE_RADIO_ON:
1399                 retval = rt73usb_enable_radio(rt2x00dev);
1400                 break;
1401         case STATE_RADIO_OFF:
1402                 rt73usb_disable_radio(rt2x00dev);
1403                 break;
1404         case STATE_RADIO_RX_ON:
1405         case STATE_RADIO_RX_OFF:
1406                 rt73usb_toggle_rx(rt2x00dev, state);
1407                 break;
1408         case STATE_RADIO_IRQ_ON:
1409         case STATE_RADIO_IRQ_ON_ISR:
1410         case STATE_RADIO_IRQ_OFF:
1411         case STATE_RADIO_IRQ_OFF_ISR:
1412                 /* No support, but no error either */
1413                 break;
1414         case STATE_DEEP_SLEEP:
1415         case STATE_SLEEP:
1416         case STATE_STANDBY:
1417         case STATE_AWAKE:
1418                 retval = rt73usb_set_state(rt2x00dev, state);
1419                 break;
1420         default:
1421                 retval = -ENOTSUPP;
1422                 break;
1423         }
1424
1425         if (unlikely(retval))
1426                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1427                       state, retval);
1428
1429         return retval;
1430 }
1431
1432 /*
1433  * TX descriptor initialization
1434  */
1435 static void rt73usb_write_tx_desc(struct queue_entry *entry,
1436                                   struct txentry_desc *txdesc)
1437 {
1438         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1439         __le32 *txd = (__le32 *) entry->skb->data;
1440         u32 word;
1441
1442         /*
1443          * Start writing the descriptor words.
1444          */
1445         rt2x00_desc_read(txd, 0, &word);
1446         rt2x00_set_field32(&word, TXD_W0_BURST,
1447                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1448         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1449         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1450                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1451         rt2x00_set_field32(&word, TXD_W0_ACK,
1452                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1453         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1454                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1455         rt2x00_set_field32(&word, TXD_W0_OFDM,
1456                            (txdesc->rate_mode == RATE_MODE_OFDM));
1457         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1458         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1459                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1460         rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1461                            test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1462         rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1463                            test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1464         rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1465         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
1466         rt2x00_set_field32(&word, TXD_W0_BURST2,
1467                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1468         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1469         rt2x00_desc_write(txd, 0, word);
1470
1471         rt2x00_desc_read(txd, 1, &word);
1472         rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, entry->queue->qid);
1473         rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->queue->aifs);
1474         rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min);
1475         rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max);
1476         rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1477         rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1478                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1479         rt2x00_desc_write(txd, 1, word);
1480
1481         rt2x00_desc_read(txd, 2, &word);
1482         rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1483         rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1484         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1485         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1486         rt2x00_desc_write(txd, 2, word);
1487
1488         if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1489                 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1490                 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
1491         }
1492
1493         rt2x00_desc_read(txd, 5, &word);
1494         rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1495                            TXPOWER_TO_DEV(entry->queue->rt2x00dev->tx_power));
1496         rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1497         rt2x00_desc_write(txd, 5, word);
1498
1499         /*
1500          * Register descriptor details in skb frame descriptor.
1501          */
1502         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
1503         skbdesc->desc = txd;
1504         skbdesc->desc_len = TXD_DESC_SIZE;
1505 }
1506
1507 /*
1508  * TX data initialization
1509  */
1510 static void rt73usb_write_beacon(struct queue_entry *entry,
1511                                  struct txentry_desc *txdesc)
1512 {
1513         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1514         unsigned int beacon_base;
1515         u32 reg;
1516
1517         /*
1518          * Disable beaconing while we are reloading the beacon data,
1519          * otherwise we might be sending out invalid data.
1520          */
1521         rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1522         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1523         rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1524
1525         /*
1526          * Add space for the descriptor in front of the skb.
1527          */
1528         skb_push(entry->skb, TXD_DESC_SIZE);
1529         memset(entry->skb->data, 0, TXD_DESC_SIZE);
1530
1531         /*
1532          * Write the TX descriptor for the beacon.
1533          */
1534         rt73usb_write_tx_desc(entry, txdesc);
1535
1536         /*
1537          * Dump beacon to userspace through debugfs.
1538          */
1539         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1540
1541         /*
1542          * Write entire beacon with descriptor to register.
1543          */
1544         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1545         rt2x00usb_register_multiwrite(rt2x00dev, beacon_base,
1546                                       entry->skb->data, entry->skb->len);
1547
1548         /*
1549          * Enable beaconing again.
1550          *
1551          * For Wi-Fi faily generated beacons between participating stations.
1552          * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1553          */
1554         rt2x00usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1555
1556         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1557         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1558         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1559         rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1560
1561         /*
1562          * Clean up the beacon skb.
1563          */
1564         dev_kfree_skb(entry->skb);
1565         entry->skb = NULL;
1566 }
1567
1568 static int rt73usb_get_tx_data_len(struct queue_entry *entry)
1569 {
1570         int length;
1571
1572         /*
1573          * The length _must_ be a multiple of 4,
1574          * but it must _not_ be a multiple of the USB packet size.
1575          */
1576         length = roundup(entry->skb->len, 4);
1577         length += (4 * !(length % entry->queue->usb_maxpacket));
1578
1579         return length;
1580 }
1581
1582 static void rt73usb_kill_tx_queue(struct data_queue *queue)
1583 {
1584         if (queue->qid == QID_BEACON)
1585                 rt2x00usb_register_write(queue->rt2x00dev, TXRX_CSR9, 0);
1586
1587         rt2x00usb_kill_tx_queue(queue);
1588 }
1589
1590 /*
1591  * RX control handlers
1592  */
1593 static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1594 {
1595         u8 offset = rt2x00dev->lna_gain;
1596         u8 lna;
1597
1598         lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1599         switch (lna) {
1600         case 3:
1601                 offset += 90;
1602                 break;
1603         case 2:
1604                 offset += 74;
1605                 break;
1606         case 1:
1607                 offset += 64;
1608                 break;
1609         default:
1610                 return 0;
1611         }
1612
1613         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1614                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1615                         if (lna == 3 || lna == 2)
1616                                 offset += 10;
1617                 } else {
1618                         if (lna == 3)
1619                                 offset += 6;
1620                         else if (lna == 2)
1621                                 offset += 8;
1622                 }
1623         }
1624
1625         return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1626 }
1627
1628 static void rt73usb_fill_rxdone(struct queue_entry *entry,
1629                                 struct rxdone_entry_desc *rxdesc)
1630 {
1631         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1632         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1633         __le32 *rxd = (__le32 *)entry->skb->data;
1634         u32 word0;
1635         u32 word1;
1636
1637         /*
1638          * Copy descriptor to the skbdesc->desc buffer, making it safe from moving of
1639          * frame data in rt2x00usb.
1640          */
1641         memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
1642         rxd = (__le32 *)skbdesc->desc;
1643
1644         /*
1645          * It is now safe to read the descriptor on all architectures.
1646          */
1647         rt2x00_desc_read(rxd, 0, &word0);
1648         rt2x00_desc_read(rxd, 1, &word1);
1649
1650         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1651                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1652
1653         rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1654         rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1655
1656         if (rxdesc->cipher != CIPHER_NONE) {
1657                 _rt2x00_desc_read(rxd, 2, &rxdesc->iv[0]);
1658                 _rt2x00_desc_read(rxd, 3, &rxdesc->iv[1]);
1659                 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
1660
1661                 _rt2x00_desc_read(rxd, 4, &rxdesc->icv);
1662                 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
1663
1664                 /*
1665                  * Hardware has stripped IV/EIV data from 802.11 frame during
1666                  * decryption. It has provided the data separately but rt2x00lib
1667                  * should decide if it should be reinserted.
1668                  */
1669                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1670
1671                 /*
1672                  * FIXME: Legacy driver indicates that the frame does
1673                  * contain the Michael Mic. Unfortunately, in rt2x00
1674                  * the MIC seems to be missing completely...
1675                  */
1676                 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
1677
1678                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1679                         rxdesc->flags |= RX_FLAG_DECRYPTED;
1680                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1681                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1682         }
1683
1684         /*
1685          * Obtain the status about this packet.
1686          * When frame was received with an OFDM bitrate,
1687          * the signal is the PLCP value. If it was received with
1688          * a CCK bitrate the signal is the rate in 100kbit/s.
1689          */
1690         rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1691         rxdesc->rssi = rt73usb_agc_to_rssi(rt2x00dev, word1);
1692         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1693
1694         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1695                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1696         else
1697                 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
1698         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1699                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1700
1701         /*
1702          * Set skb pointers, and update frame information.
1703          */
1704         skb_pull(entry->skb, entry->queue->desc_size);
1705         skb_trim(entry->skb, rxdesc->size);
1706 }
1707
1708 /*
1709  * Device probe functions.
1710  */
1711 static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1712 {
1713         u16 word;
1714         u8 *mac;
1715         s8 value;
1716
1717         rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1718
1719         /*
1720          * Start validation of the data that has been read.
1721          */
1722         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1723         if (!is_valid_ether_addr(mac)) {
1724                 random_ether_addr(mac);
1725                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1726         }
1727
1728         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1729         if (word == 0xffff) {
1730                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1731                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1732                                    ANTENNA_B);
1733                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1734                                    ANTENNA_B);
1735                 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1736                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1737                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1738                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1739                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1740                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1741         }
1742
1743         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1744         if (word == 0xffff) {
1745                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1746                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1747                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1748         }
1749
1750         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1751         if (word == 0xffff) {
1752                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1753                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1754                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1755                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1756                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1757                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1758                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1759                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1760                 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1761                                    LED_MODE_DEFAULT);
1762                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1763                 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1764         }
1765
1766         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1767         if (word == 0xffff) {
1768                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1769                 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1770                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1771                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1772         }
1773
1774         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1775         if (word == 0xffff) {
1776                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1777                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1778                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1779                 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1780         } else {
1781                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1782                 if (value < -10 || value > 10)
1783                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1784                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1785                 if (value < -10 || value > 10)
1786                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1787                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1788         }
1789
1790         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1791         if (word == 0xffff) {
1792                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1793                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1794                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1795                 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
1796         } else {
1797                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1798                 if (value < -10 || value > 10)
1799                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1800                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1801                 if (value < -10 || value > 10)
1802                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1803                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1804         }
1805
1806         return 0;
1807 }
1808
1809 static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1810 {
1811         u32 reg;
1812         u16 value;
1813         u16 eeprom;
1814
1815         /*
1816          * Read EEPROM word for configuration.
1817          */
1818         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1819
1820         /*
1821          * Identify RF chipset.
1822          */
1823         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1824         rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1825         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
1826                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
1827
1828         if (!rt2x00_rt(rt2x00dev, RT2573) || (rt2x00_rev(rt2x00dev) == 0)) {
1829                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1830                 return -ENODEV;
1831         }
1832
1833         if (!rt2x00_rf(rt2x00dev, RF5226) &&
1834             !rt2x00_rf(rt2x00dev, RF2528) &&
1835             !rt2x00_rf(rt2x00dev, RF5225) &&
1836             !rt2x00_rf(rt2x00dev, RF2527)) {
1837                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1838                 return -ENODEV;
1839         }
1840
1841         /*
1842          * Identify default antenna configuration.
1843          */
1844         rt2x00dev->default_ant.tx =
1845             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1846         rt2x00dev->default_ant.rx =
1847             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1848
1849         /*
1850          * Read the Frame type.
1851          */
1852         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1853                 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1854
1855         /*
1856          * Detect if this device has an hardware controlled radio.
1857          */
1858         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1859                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1860
1861         /*
1862          * Read frequency offset.
1863          */
1864         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1865         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1866
1867         /*
1868          * Read external LNA informations.
1869          */
1870         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1871
1872         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1873                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1874                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1875         }
1876
1877         /*
1878          * Store led settings, for correct led behaviour.
1879          */
1880 #ifdef CONFIG_RT2X00_LIB_LEDS
1881         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1882
1883         rt73usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1884         rt73usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1885         if (value == LED_MODE_SIGNAL_STRENGTH)
1886                 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_qual,
1887                                  LED_TYPE_QUALITY);
1888
1889         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
1890         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
1891                            rt2x00_get_field16(eeprom,
1892                                               EEPROM_LED_POLARITY_GPIO_0));
1893         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
1894                            rt2x00_get_field16(eeprom,
1895                                               EEPROM_LED_POLARITY_GPIO_1));
1896         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
1897                            rt2x00_get_field16(eeprom,
1898                                               EEPROM_LED_POLARITY_GPIO_2));
1899         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
1900                            rt2x00_get_field16(eeprom,
1901                                               EEPROM_LED_POLARITY_GPIO_3));
1902         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
1903                            rt2x00_get_field16(eeprom,
1904                                               EEPROM_LED_POLARITY_GPIO_4));
1905         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
1906                            rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
1907         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
1908                            rt2x00_get_field16(eeprom,
1909                                               EEPROM_LED_POLARITY_RDY_G));
1910         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
1911                            rt2x00_get_field16(eeprom,
1912                                               EEPROM_LED_POLARITY_RDY_A));
1913 #endif /* CONFIG_RT2X00_LIB_LEDS */
1914
1915         return 0;
1916 }
1917
1918 /*
1919  * RF value list for RF2528
1920  * Supports: 2.4 GHz
1921  */
1922 static const struct rf_channel rf_vals_bg_2528[] = {
1923         { 1,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1924         { 2,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1925         { 3,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1926         { 4,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1927         { 5,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1928         { 6,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1929         { 7,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1930         { 8,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1931         { 9,  0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1932         { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1933         { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1934         { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1935         { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1936         { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1937 };
1938
1939 /*
1940  * RF value list for RF5226
1941  * Supports: 2.4 GHz & 5.2 GHz
1942  */
1943 static const struct rf_channel rf_vals_5226[] = {
1944         { 1,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1945         { 2,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1946         { 3,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1947         { 4,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1948         { 5,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1949         { 6,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1950         { 7,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1951         { 8,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1952         { 9,  0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1953         { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1954         { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1955         { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1956         { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1957         { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1958
1959         /* 802.11 UNI / HyperLan 2 */
1960         { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
1961         { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
1962         { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
1963         { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
1964         { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
1965         { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
1966         { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
1967         { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
1968
1969         /* 802.11 HyperLan 2 */
1970         { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
1971         { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
1972         { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
1973         { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
1974         { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
1975         { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
1976         { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
1977         { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
1978         { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
1979         { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
1980
1981         /* 802.11 UNII */
1982         { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
1983         { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
1984         { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
1985         { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
1986         { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
1987         { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
1988
1989         /* MMAC(Japan)J52 ch 34,38,42,46 */
1990         { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
1991         { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
1992         { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
1993         { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
1994 };
1995
1996 /*
1997  * RF value list for RF5225 & RF2527
1998  * Supports: 2.4 GHz & 5.2 GHz
1999  */
2000 static const struct rf_channel rf_vals_5225_2527[] = {
2001         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2002         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2003         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2004         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2005         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2006         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2007         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2008         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2009         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2010         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2011         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2012         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2013         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2014         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2015
2016         /* 802.11 UNI / HyperLan 2 */
2017         { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2018         { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2019         { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2020         { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2021         { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2022         { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2023         { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2024         { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2025
2026         /* 802.11 HyperLan 2 */
2027         { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2028         { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2029         { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2030         { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2031         { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2032         { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2033         { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2034         { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2035         { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2036         { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2037
2038         /* 802.11 UNII */
2039         { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2040         { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2041         { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2042         { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2043         { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2044         { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2045
2046         /* MMAC(Japan)J52 ch 34,38,42,46 */
2047         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2048         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2049         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2050         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2051 };
2052
2053
2054 static int rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2055 {
2056         struct hw_mode_spec *spec = &rt2x00dev->spec;
2057         struct channel_info *info;
2058         char *tx_power;
2059         unsigned int i;
2060
2061         /*
2062          * Initialize all hw fields.
2063          *
2064          * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING unless we are
2065          * capable of sending the buffered frames out after the DTIM
2066          * transmission using rt2x00lib_beacondone. This will send out
2067          * multicast and broadcast traffic immediately instead of buffering it
2068          * infinitly and thus dropping it after some time.
2069          */
2070         rt2x00dev->hw->flags =
2071             IEEE80211_HW_SIGNAL_DBM |
2072             IEEE80211_HW_SUPPORTS_PS |
2073             IEEE80211_HW_PS_NULLFUNC_STACK;
2074
2075         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2076         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2077                                 rt2x00_eeprom_addr(rt2x00dev,
2078                                                    EEPROM_MAC_ADDR_0));
2079
2080         /*
2081          * Initialize hw_mode information.
2082          */
2083         spec->supported_bands = SUPPORT_BAND_2GHZ;
2084         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2085
2086         if (rt2x00_rf(rt2x00dev, RF2528)) {
2087                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
2088                 spec->channels = rf_vals_bg_2528;
2089         } else if (rt2x00_rf(rt2x00dev, RF5226)) {
2090                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2091                 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
2092                 spec->channels = rf_vals_5226;
2093         } else if (rt2x00_rf(rt2x00dev, RF2527)) {
2094                 spec->num_channels = 14;
2095                 spec->channels = rf_vals_5225_2527;
2096         } else if (rt2x00_rf(rt2x00dev, RF5225)) {
2097                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2098                 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
2099                 spec->channels = rf_vals_5225_2527;
2100         }
2101
2102         /*
2103          * Create channel information array
2104          */
2105         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
2106         if (!info)
2107                 return -ENOMEM;
2108
2109         spec->channels_info = info;
2110
2111         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2112         for (i = 0; i < 14; i++) {
2113                 info[i].max_power = MAX_TXPOWER;
2114                 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2115         }
2116
2117         if (spec->num_channels > 14) {
2118                 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2119                 for (i = 14; i < spec->num_channels; i++) {
2120                         info[i].max_power = MAX_TXPOWER;
2121                         info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2122                 }
2123         }
2124
2125         return 0;
2126 }
2127
2128 static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2129 {
2130         int retval;
2131
2132         /*
2133          * Allocate eeprom data.
2134          */
2135         retval = rt73usb_validate_eeprom(rt2x00dev);
2136         if (retval)
2137                 return retval;
2138
2139         retval = rt73usb_init_eeprom(rt2x00dev);
2140         if (retval)
2141                 return retval;
2142
2143         /*
2144          * Initialize hw specifications.
2145          */
2146         retval = rt73usb_probe_hw_mode(rt2x00dev);
2147         if (retval)
2148                 return retval;
2149
2150         /*
2151          * This device has multiple filters for control frames,
2152          * but has no a separate filter for PS Poll frames.
2153          */
2154         __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
2155
2156         /*
2157          * This device requires firmware.
2158          */
2159         __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2160         if (!modparam_nohwcrypt)
2161                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2162         __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
2163         __set_bit(DRIVER_SUPPORT_WATCHDOG, &rt2x00dev->flags);
2164
2165         /*
2166          * Set the rssi offset.
2167          */
2168         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2169
2170         return 0;
2171 }
2172
2173 /*
2174  * IEEE80211 stack callback functions.
2175  */
2176 static int rt73usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2177                            const struct ieee80211_tx_queue_params *params)
2178 {
2179         struct rt2x00_dev *rt2x00dev = hw->priv;
2180         struct data_queue *queue;
2181         struct rt2x00_field32 field;
2182         int retval;
2183         u32 reg;
2184         u32 offset;
2185
2186         /*
2187          * First pass the configuration through rt2x00lib, that will
2188          * update the queue settings and validate the input. After that
2189          * we are free to update the registers based on the value
2190          * in the queue parameter.
2191          */
2192         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2193         if (retval)
2194                 return retval;
2195
2196         /*
2197          * We only need to perform additional register initialization
2198          * for WMM queues/
2199          */
2200         if (queue_idx >= 4)
2201                 return 0;
2202
2203         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2204
2205         /* Update WMM TXOP register */
2206         offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
2207         field.bit_offset = (queue_idx & 1) * 16;
2208         field.bit_mask = 0xffff << field.bit_offset;
2209
2210         rt2x00usb_register_read(rt2x00dev, offset, &reg);
2211         rt2x00_set_field32(&reg, field, queue->txop);
2212         rt2x00usb_register_write(rt2x00dev, offset, reg);
2213
2214         /* Update WMM registers */
2215         field.bit_offset = queue_idx * 4;
2216         field.bit_mask = 0xf << field.bit_offset;
2217
2218         rt2x00usb_register_read(rt2x00dev, AIFSN_CSR, &reg);
2219         rt2x00_set_field32(&reg, field, queue->aifs);
2220         rt2x00usb_register_write(rt2x00dev, AIFSN_CSR, reg);
2221
2222         rt2x00usb_register_read(rt2x00dev, CWMIN_CSR, &reg);
2223         rt2x00_set_field32(&reg, field, queue->cw_min);
2224         rt2x00usb_register_write(rt2x00dev, CWMIN_CSR, reg);
2225
2226         rt2x00usb_register_read(rt2x00dev, CWMAX_CSR, &reg);
2227         rt2x00_set_field32(&reg, field, queue->cw_max);
2228         rt2x00usb_register_write(rt2x00dev, CWMAX_CSR, reg);
2229
2230         return 0;
2231 }
2232
2233 static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
2234 {
2235         struct rt2x00_dev *rt2x00dev = hw->priv;
2236         u64 tsf;
2237         u32 reg;
2238
2239         rt2x00usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
2240         tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2241         rt2x00usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
2242         tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2243
2244         return tsf;
2245 }
2246
2247 static const struct ieee80211_ops rt73usb_mac80211_ops = {
2248         .tx                     = rt2x00mac_tx,
2249         .start                  = rt2x00mac_start,
2250         .stop                   = rt2x00mac_stop,
2251         .add_interface          = rt2x00mac_add_interface,
2252         .remove_interface       = rt2x00mac_remove_interface,
2253         .config                 = rt2x00mac_config,
2254         .configure_filter       = rt2x00mac_configure_filter,
2255         .set_tim                = rt2x00mac_set_tim,
2256         .set_key                = rt2x00mac_set_key,
2257         .sw_scan_start          = rt2x00mac_sw_scan_start,
2258         .sw_scan_complete       = rt2x00mac_sw_scan_complete,
2259         .get_stats              = rt2x00mac_get_stats,
2260         .bss_info_changed       = rt2x00mac_bss_info_changed,
2261         .conf_tx                = rt73usb_conf_tx,
2262         .get_tsf                = rt73usb_get_tsf,
2263         .rfkill_poll            = rt2x00mac_rfkill_poll,
2264         .flush                  = rt2x00mac_flush,
2265 };
2266
2267 static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2268         .probe_hw               = rt73usb_probe_hw,
2269         .get_firmware_name      = rt73usb_get_firmware_name,
2270         .check_firmware         = rt73usb_check_firmware,
2271         .load_firmware          = rt73usb_load_firmware,
2272         .initialize             = rt2x00usb_initialize,
2273         .uninitialize           = rt2x00usb_uninitialize,
2274         .clear_entry            = rt2x00usb_clear_entry,
2275         .set_device_state       = rt73usb_set_device_state,
2276         .rfkill_poll            = rt73usb_rfkill_poll,
2277         .link_stats             = rt73usb_link_stats,
2278         .reset_tuner            = rt73usb_reset_tuner,
2279         .link_tuner             = rt73usb_link_tuner,
2280         .watchdog               = rt2x00usb_watchdog,
2281         .write_tx_desc          = rt73usb_write_tx_desc,
2282         .write_beacon           = rt73usb_write_beacon,
2283         .get_tx_data_len        = rt73usb_get_tx_data_len,
2284         .kick_tx_queue          = rt2x00usb_kick_tx_queue,
2285         .kill_tx_queue          = rt73usb_kill_tx_queue,
2286         .fill_rxdone            = rt73usb_fill_rxdone,
2287         .config_shared_key      = rt73usb_config_shared_key,
2288         .config_pairwise_key    = rt73usb_config_pairwise_key,
2289         .config_filter          = rt73usb_config_filter,
2290         .config_intf            = rt73usb_config_intf,
2291         .config_erp             = rt73usb_config_erp,
2292         .config_ant             = rt73usb_config_ant,
2293         .config                 = rt73usb_config,
2294 };
2295
2296 static const struct data_queue_desc rt73usb_queue_rx = {
2297         .entry_num              = 32,
2298         .data_size              = DATA_FRAME_SIZE,
2299         .desc_size              = RXD_DESC_SIZE,
2300         .priv_size              = sizeof(struct queue_entry_priv_usb),
2301 };
2302
2303 static const struct data_queue_desc rt73usb_queue_tx = {
2304         .entry_num              = 32,
2305         .data_size              = DATA_FRAME_SIZE,
2306         .desc_size              = TXD_DESC_SIZE,
2307         .priv_size              = sizeof(struct queue_entry_priv_usb),
2308 };
2309
2310 static const struct data_queue_desc rt73usb_queue_bcn = {
2311         .entry_num              = 4,
2312         .data_size              = MGMT_FRAME_SIZE,
2313         .desc_size              = TXINFO_SIZE,
2314         .priv_size              = sizeof(struct queue_entry_priv_usb),
2315 };
2316
2317 static const struct rt2x00_ops rt73usb_ops = {
2318         .name                   = KBUILD_MODNAME,
2319         .max_sta_intf           = 1,
2320         .max_ap_intf            = 4,
2321         .eeprom_size            = EEPROM_SIZE,
2322         .rf_size                = RF_SIZE,
2323         .tx_queues              = NUM_TX_QUEUES,
2324         .extra_tx_headroom      = TXD_DESC_SIZE,
2325         .rx                     = &rt73usb_queue_rx,
2326         .tx                     = &rt73usb_queue_tx,
2327         .bcn                    = &rt73usb_queue_bcn,
2328         .lib                    = &rt73usb_rt2x00_ops,
2329         .hw                     = &rt73usb_mac80211_ops,
2330 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2331         .debugfs                = &rt73usb_rt2x00debug,
2332 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2333 };
2334
2335 /*
2336  * rt73usb module information.
2337  */
2338 static struct usb_device_id rt73usb_device_table[] = {
2339         /* AboCom */
2340         { USB_DEVICE(0x07b8, 0xb21b), USB_DEVICE_DATA(&rt73usb_ops) },
2341         { USB_DEVICE(0x07b8, 0xb21c), USB_DEVICE_DATA(&rt73usb_ops) },
2342         { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
2343         { USB_DEVICE(0x07b8, 0xb21e), USB_DEVICE_DATA(&rt73usb_ops) },
2344         { USB_DEVICE(0x07b8, 0xb21f), USB_DEVICE_DATA(&rt73usb_ops) },
2345         /* AL */
2346         { USB_DEVICE(0x14b2, 0x3c10), USB_DEVICE_DATA(&rt73usb_ops) },
2347         /* Amigo */
2348         { USB_DEVICE(0x148f, 0x9021), USB_DEVICE_DATA(&rt73usb_ops) },
2349         { USB_DEVICE(0x0eb0, 0x9021), USB_DEVICE_DATA(&rt73usb_ops) },
2350         /* AMIT  */
2351         { USB_DEVICE(0x18c5, 0x0002), USB_DEVICE_DATA(&rt73usb_ops) },
2352         /* Askey */
2353         { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2354         /* ASUS */
2355         { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2356         { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2357         /* Belkin */
2358         { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2359         { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2360         { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
2361         { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
2362         /* Billionton */
2363         { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
2364         { USB_DEVICE(0x08dd, 0x0120), USB_DEVICE_DATA(&rt73usb_ops) },
2365         /* Buffalo */
2366         { USB_DEVICE(0x0411, 0x00d8), USB_DEVICE_DATA(&rt73usb_ops) },
2367         { USB_DEVICE(0x0411, 0x00d9), USB_DEVICE_DATA(&rt73usb_ops) },
2368         { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
2369         { USB_DEVICE(0x0411, 0x0116), USB_DEVICE_DATA(&rt73usb_ops) },
2370         { USB_DEVICE(0x0411, 0x0119), USB_DEVICE_DATA(&rt73usb_ops) },
2371         { USB_DEVICE(0x0411, 0x0137), USB_DEVICE_DATA(&rt73usb_ops) },
2372         /* CEIVA */
2373         { USB_DEVICE(0x178d, 0x02be), USB_DEVICE_DATA(&rt73usb_ops) },
2374         /* CNet */
2375         { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2376         { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2377         /* Conceptronic */
2378         { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
2379         /* Corega */
2380         { USB_DEVICE(0x07aa, 0x002e), USB_DEVICE_DATA(&rt73usb_ops) },
2381         /* D-Link */
2382         { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2383         { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
2384         { USB_DEVICE(0x07d1, 0x3c06), USB_DEVICE_DATA(&rt73usb_ops) },
2385         { USB_DEVICE(0x07d1, 0x3c07), USB_DEVICE_DATA(&rt73usb_ops) },
2386         /* Edimax */
2387         { USB_DEVICE(0x7392, 0x7318), USB_DEVICE_DATA(&rt73usb_ops) },
2388         { USB_DEVICE(0x7392, 0x7618), USB_DEVICE_DATA(&rt73usb_ops) },
2389         /* EnGenius */
2390         { USB_DEVICE(0x1740, 0x3701), USB_DEVICE_DATA(&rt73usb_ops) },
2391         /* Gemtek */
2392         { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2393         /* Gigabyte */
2394         { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2395         { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2396         /* Huawei-3Com */
2397         { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2398         /* Hercules */
2399         { USB_DEVICE(0x06f8, 0xe002), USB_DEVICE_DATA(&rt73usb_ops) },
2400         { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2401         { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2402         /* Linksys */
2403         { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2404         { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
2405         { USB_DEVICE(0x13b1, 0x0028), USB_DEVICE_DATA(&rt73usb_ops) },
2406         /* MSI */
2407         { USB_DEVICE(0x0db0, 0x4600), USB_DEVICE_DATA(&rt73usb_ops) },
2408         { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2409         { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2410         { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2411         { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
2412         /* Ovislink */
2413         { USB_DEVICE(0x1b75, 0x7318), USB_DEVICE_DATA(&rt73usb_ops) },
2414         /* Ralink */
2415         { USB_DEVICE(0x04bb, 0x093d), USB_DEVICE_DATA(&rt73usb_ops) },
2416         { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2417         { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2418         /* Qcom */
2419         { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2420         { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2421         { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
2422         /* Samsung */
2423         { USB_DEVICE(0x04e8, 0x4471), USB_DEVICE_DATA(&rt73usb_ops) },
2424         /* Senao */
2425         { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2426         /* Sitecom */
2427         { USB_DEVICE(0x0df6, 0x0024), USB_DEVICE_DATA(&rt73usb_ops) },
2428         { USB_DEVICE(0x0df6, 0x0027), USB_DEVICE_DATA(&rt73usb_ops) },
2429         { USB_DEVICE(0x0df6, 0x002f), USB_DEVICE_DATA(&rt73usb_ops) },
2430         { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
2431         { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
2432         /* Surecom */
2433         { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
2434         /* Tilgin */
2435         { USB_DEVICE(0x6933, 0x5001), USB_DEVICE_DATA(&rt73usb_ops) },
2436         /* Philips */
2437         { USB_DEVICE(0x0471, 0x200a), USB_DEVICE_DATA(&rt73usb_ops) },
2438         /* Planex */
2439         { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2440         { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
2441         /* WideTell */
2442         { USB_DEVICE(0x7167, 0x3840), USB_DEVICE_DATA(&rt73usb_ops) },
2443         /* Zcom */
2444         { USB_DEVICE(0x0cde, 0x001c), USB_DEVICE_DATA(&rt73usb_ops) },
2445         /* ZyXEL */
2446         { USB_DEVICE(0x0586, 0x3415), USB_DEVICE_DATA(&rt73usb_ops) },
2447         { 0, }
2448 };
2449
2450 MODULE_AUTHOR(DRV_PROJECT);
2451 MODULE_VERSION(DRV_VERSION);
2452 MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2453 MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2454 MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2455 MODULE_FIRMWARE(FIRMWARE_RT2571);
2456 MODULE_LICENSE("GPL");
2457
2458 static struct usb_driver rt73usb_driver = {
2459         .name           = KBUILD_MODNAME,
2460         .id_table       = rt73usb_device_table,
2461         .probe          = rt2x00usb_probe,
2462         .disconnect     = rt2x00usb_disconnect,
2463         .suspend        = rt2x00usb_suspend,
2464         .resume         = rt2x00usb_resume,
2465 };
2466
2467 static int __init rt73usb_init(void)
2468 {
2469         return usb_register(&rt73usb_driver);
2470 }
2471
2472 static void __exit rt73usb_exit(void)
2473 {
2474         usb_deregister(&rt73usb_driver);
2475 }
2476
2477 module_init(rt73usb_init);
2478 module_exit(rt73usb_exit);