Pileus Git - ~andy/linux/blob - drivers/net/wireless/rt2x00/rt61pci.c

   1 /*
   2         Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 /*
  20         Module: rt61pci
  21         Abstract: rt61pci device specific routines.
  22         Supported chipsets: RT2561, RT2561s, RT2661.
  23  */
  24
  25 #include <linux/crc-itu-t.h>
  26 #include <linux/delay.h>
  27 #include <linux/etherdevice.h>
  28 #include <linux/init.h>
  29 #include <linux/kernel.h>
  30 #include <linux/module.h>
  31 #include <linux/slab.h>
  32 #include <linux/pci.h>
  33 #include <linux/eeprom_93cx6.h>
  34
  35 #include "rt2x00.h"
  36 #include "rt2x00mmio.h"
  37 #include "rt2x00pci.h"
  38 #include "rt61pci.h"
  39
  40 /*
  41  * Allow hardware encryption to be disabled.
  42  */
  43 static bool modparam_nohwcrypt = false;
  44 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  45 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  46
  47 /*
  48  * Register access.
  49  * BBP and RF register require indirect register access,
  50  * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
  51  * These indirect registers work with busy bits,
  52  * and we will try maximal REGISTER_BUSY_COUNT times to access
  53  * the register while taking a REGISTER_BUSY_DELAY us delay
  54  * between each attempt. When the busy bit is still set at that time,
  55  * the access attempt is considered to have failed,
  56  * and we will print an error.
  57  */
  58 #define WAIT_FOR_BBP(__dev, __reg) \
  59         rt2x00mmio_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
  60 #define WAIT_FOR_RF(__dev, __reg) \
  61         rt2x00mmio_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
  62 #define WAIT_FOR_MCU(__dev, __reg) \
  63         rt2x00mmio_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  64                                 H2M_MAILBOX_CSR_OWNER, (__reg))
  65
  66 static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  67                               const unsigned int word, const u8 value)
  68 {
  69         u32 reg;
  70
  71         mutex_lock(&rt2x00dev->csr_mutex);
  72
  73         /*
  74          * Wait until the BBP becomes available, afterwards we
  75          * can safely write the new data into the register.
  76          */
  77         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  78                 reg = 0;
  79                 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
  80                 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
  81                 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
  82                 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
  83
  84                 rt2x00mmio_register_write(rt2x00dev, PHY_CSR3, reg);
  85         }
  86
  87         mutex_unlock(&rt2x00dev->csr_mutex);
  88 }
  89
  90 static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  91                              const unsigned int word, u8 *value)
  92 {
  93         u32 reg;
  94
  95         mutex_lock(&rt2x00dev->csr_mutex);
  96
  97         /*
  98          * Wait until the BBP becomes available, afterwards we
  99          * can safely write the read request into the register.
 100          * After the data has been written, we wait until hardware
 101          * returns the correct value, if at any time the register
 102          * doesn't become available in time, reg will be 0xffffffff
 103          * which means we return 0xff to the caller.
 104          */
 105         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 106                 reg = 0;
 107                 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
 108                 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
 109                 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
 110
 111                 rt2x00mmio_register_write(rt2x00dev, PHY_CSR3, reg);
 112
 113                 WAIT_FOR_BBP(rt2x00dev, &reg);
 114         }
 115
 116         *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
 117
 118         mutex_unlock(&rt2x00dev->csr_mutex);
 119 }
 120
 121 static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
 122                              const unsigned int word, const u32 value)
 123 {
 124         u32 reg;
 125
 126         mutex_lock(&rt2x00dev->csr_mutex);
 127
 128         /*
 129          * Wait until the RF becomes available, afterwards we
 130          * can safely write the new data into the register.
 131          */
 132         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 133                 reg = 0;
 134                 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
 135                 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
 136                 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
 137                 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
 138
 139                 rt2x00mmio_register_write(rt2x00dev, PHY_CSR4, reg);
 140                 rt2x00_rf_write(rt2x00dev, word, value);
 141         }
 142
 143         mutex_unlock(&rt2x00dev->csr_mutex);
 144 }
 145
 146 static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
 147                                 const u8 command, const u8 token,
 148                                 const u8 arg0, const u8 arg1)
 149 {
 150         u32 reg;
 151
 152         mutex_lock(&rt2x00dev->csr_mutex);
 153
 154         /*
 155          * Wait until the MCU becomes available, afterwards we
 156          * can safely write the new data into the register.
 157          */
 158         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 159                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 160                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 161                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 162                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 163                 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
 164
 165                 rt2x00mmio_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
 166                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 167                 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
 168                 rt2x00mmio_register_write(rt2x00dev, HOST_CMD_CSR, reg);
 169         }
 170
 171         mutex_unlock(&rt2x00dev->csr_mutex);
 172
 173 }
 174
 175 static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 176 {
 177         struct rt2x00_dev *rt2x00dev = eeprom->data;
 178         u32 reg;
 179
 180         rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, &reg);
 181
 182         eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
 183         eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
 184         eeprom->reg_data_clock =
 185             !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
 186         eeprom->reg_chip_select =
 187             !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
 188 }
 189
 190 static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 191 {
 192         struct rt2x00_dev *rt2x00dev = eeprom->data;
 193         u32 reg = 0;
 194
 195         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
 196         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
 197         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
 198                            !!eeprom->reg_data_clock);
 199         rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
 200                            !!eeprom->reg_chip_select);
 201
 202         rt2x00mmio_register_write(rt2x00dev, E2PROM_CSR, reg);
 203 }
 204
 205 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 206 static const struct rt2x00debug rt61pci_rt2x00debug = {
 207         .owner  = THIS_MODULE,
 208         .csr    = {
 209                 .read           = rt2x00mmio_register_read,
 210                 .write          = rt2x00mmio_register_write,
 211                 .flags          = RT2X00DEBUGFS_OFFSET,
 212                 .word_base      = CSR_REG_BASE,
 213                 .word_size      = sizeof(u32),
 214                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 215         },
 216         .eeprom = {
 217                 .read           = rt2x00_eeprom_read,
 218                 .write          = rt2x00_eeprom_write,
 219                 .word_base      = EEPROM_BASE,
 220                 .word_size      = sizeof(u16),
 221                 .word_count     = EEPROM_SIZE / sizeof(u16),
 222         },
 223         .bbp    = {
 224                 .read           = rt61pci_bbp_read,
 225                 .write          = rt61pci_bbp_write,
 226                 .word_base      = BBP_BASE,
 227                 .word_size      = sizeof(u8),
 228                 .word_count     = BBP_SIZE / sizeof(u8),
 229         },
 230         .rf     = {
 231                 .read           = rt2x00_rf_read,
 232                 .write          = rt61pci_rf_write,
 233                 .word_base      = RF_BASE,
 234                 .word_size      = sizeof(u32),
 235                 .word_count     = RF_SIZE / sizeof(u32),
 236         },
 237 };
 238 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 239
 240 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 241 {
 242         u32 reg;
 243
 244         rt2x00mmio_register_read(rt2x00dev, MAC_CSR13, &reg);
 245         return rt2x00_get_field32(reg, MAC_CSR13_VAL5);
 246 }
 247
 248 #ifdef CONFIG_RT2X00_LIB_LEDS
 249 static void rt61pci_brightness_set(struct led_classdev *led_cdev,
 250                                    enum led_brightness brightness)
 251 {
 252         struct rt2x00_led *led =
 253             container_of(led_cdev, struct rt2x00_led, led_dev);
 254         unsigned int enabled = brightness != LED_OFF;
 255         unsigned int a_mode =
 256             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
 257         unsigned int bg_mode =
 258             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 259
 260         if (led->type == LED_TYPE_RADIO) {
 261                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 262                                    MCU_LEDCS_RADIO_STATUS, enabled);
 263
 264                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
 265                                     (led->rt2x00dev->led_mcu_reg & 0xff),
 266                                     ((led->rt2x00dev->led_mcu_reg >> 8)));
 267         } else if (led->type == LED_TYPE_ASSOC) {
 268                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 269                                    MCU_LEDCS_LINK_BG_STATUS, bg_mode);
 270                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 271                                    MCU_LEDCS_LINK_A_STATUS, a_mode);
 272
 273                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
 274                                     (led->rt2x00dev->led_mcu_reg & 0xff),
 275                                     ((led->rt2x00dev->led_mcu_reg >> 8)));
 276         } else if (led->type == LED_TYPE_QUALITY) {
 277                 /*
 278                  * The brightness is divided into 6 levels (0 - 5),
 279                  * this means we need to convert the brightness
 280                  * argument into the matching level within that range.
 281                  */
 282                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 283                                     brightness / (LED_FULL / 6), 0);
 284         }
 285 }
 286
 287 static int rt61pci_blink_set(struct led_classdev *led_cdev,
 288                              unsigned long *delay_on,
 289                              unsigned long *delay_off)
 290 {
 291         struct rt2x00_led *led =
 292             container_of(led_cdev, struct rt2x00_led, led_dev);
 293         u32 reg;
 294
 295         rt2x00mmio_register_read(led->rt2x00dev, MAC_CSR14, &reg);
 296         rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
 297         rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
 298         rt2x00mmio_register_write(led->rt2x00dev, MAC_CSR14, reg);
 299
 300         return 0;
 301 }
 302
 303 static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev,
 304                              struct rt2x00_led *led,
 305                              enum led_type type)
 306 {
 307         led->rt2x00dev = rt2x00dev;
 308         led->type = type;
 309         led->led_dev.brightness_set = rt61pci_brightness_set;
 310         led->led_dev.blink_set = rt61pci_blink_set;
 311         led->flags = LED_INITIALIZED;
 312 }
 313 #endif /* CONFIG_RT2X00_LIB_LEDS */
 314
 315 /*
 316  * Configuration handlers.
 317  */
 318 static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
 319                                      struct rt2x00lib_crypto *crypto,
 320                                      struct ieee80211_key_conf *key)
 321 {
 322         struct hw_key_entry key_entry;
 323         struct rt2x00_field32 field;
 324         u32 mask;
 325         u32 reg;
 326
 327         if (crypto->cmd == SET_KEY) {
 328                 /*
 329                  * rt2x00lib can't determine the correct free
 330                  * key_idx for shared keys. We have 1 register
 331                  * with key valid bits. The goal is simple, read
 332                  * the register, if that is full we have no slots
 333                  * left.
 334                  * Note that each BSS is allowed to have up to 4
 335                  * shared keys, so put a mask over the allowed
 336                  * entries.
 337                  */
 338                 mask = (0xf << crypto->bssidx);
 339
 340                 rt2x00mmio_register_read(rt2x00dev, SEC_CSR0, &reg);
 341                 reg &= mask;
 342
 343                 if (reg && reg == mask)
 344                         return -ENOSPC;
 345
 346                 key->hw_key_idx += reg ? ffz(reg) : 0;
 347
 348                 /*
 349                  * Upload key to hardware
 350                  */
 351                 memcpy(key_entry.key, crypto->key,
 352                        sizeof(key_entry.key));
 353                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 354                        sizeof(key_entry.tx_mic));
 355                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 356                        sizeof(key_entry.rx_mic));
 357
 358                 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
 359                 rt2x00mmio_register_multiwrite(rt2x00dev, reg,
 360                                                &key_entry, sizeof(key_entry));
 361
 362                 /*
 363                  * The cipher types are stored over 2 registers.
 364                  * bssidx 0 and 1 keys are stored in SEC_CSR1 and
 365                  * bssidx 1 and 2 keys are stored in SEC_CSR5.
 366                  * Using the correct defines correctly will cause overhead,
 367                  * so just calculate the correct offset.
 368                  */
 369                 if (key->hw_key_idx < 8) {
 370                         field.bit_offset = (3 * key->hw_key_idx);
 371                         field.bit_mask = 0x7 << field.bit_offset;
 372
 373                         rt2x00mmio_register_read(rt2x00dev, SEC_CSR1, &reg);
 374                         rt2x00_set_field32(&reg, field, crypto->cipher);
 375                         rt2x00mmio_register_write(rt2x00dev, SEC_CSR1, reg);
 376                 } else {
 377                         field.bit_offset = (3 * (key->hw_key_idx - 8));
 378                         field.bit_mask = 0x7 << field.bit_offset;
 379
 380                         rt2x00mmio_register_read(rt2x00dev, SEC_CSR5, &reg);
 381                         rt2x00_set_field32(&reg, field, crypto->cipher);
 382                         rt2x00mmio_register_write(rt2x00dev, SEC_CSR5, reg);
 383                 }
 384
 385                 /*
 386                  * The driver does not support the IV/EIV generation
 387                  * in hardware. However it doesn't support the IV/EIV
 388                  * inside the ieee80211 frame either, but requires it
 389                  * to be provided separately for the descriptor.
 390                  * rt2x00lib will cut the IV/EIV data out of all frames
 391                  * given to us by mac80211, but we must tell mac80211
 392                  * to generate the IV/EIV data.
 393                  */
 394                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 395         }
 396
 397         /*
 398          * SEC_CSR0 contains only single-bit fields to indicate
 399          * a particular key is valid. Because using the FIELD32()
 400          * defines directly will cause a lot of overhead, we use
 401          * a calculation to determine the correct bit directly.
 402          */
 403         mask = 1 << key->hw_key_idx;
 404
 405         rt2x00mmio_register_read(rt2x00dev, SEC_CSR0, &reg);
 406         if (crypto->cmd == SET_KEY)
 407                 reg |= mask;
 408         else if (crypto->cmd == DISABLE_KEY)
 409                 reg &= ~mask;
 410         rt2x00mmio_register_write(rt2x00dev, SEC_CSR0, reg);
 411
 412         return 0;
 413 }
 414
 415 static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 416                                        struct rt2x00lib_crypto *crypto,
 417                                        struct ieee80211_key_conf *key)
 418 {
 419         struct hw_pairwise_ta_entry addr_entry;
 420         struct hw_key_entry key_entry;
 421         u32 mask;
 422         u32 reg;
 423
 424         if (crypto->cmd == SET_KEY) {
 425                 /*
 426                  * rt2x00lib can't determine the correct free
 427                  * key_idx for pairwise keys. We have 2 registers
 428                  * with key valid bits. The goal is simple: read
 429                  * the first register. If that is full, move to
 430                  * the next register.
 431                  * When both registers are full, we drop the key.
 432                  * Otherwise, we use the first invalid entry.
 433                  */
 434                 rt2x00mmio_register_read(rt2x00dev, SEC_CSR2, &reg);
 435                 if (reg && reg == ~0) {
 436                         key->hw_key_idx = 32;
 437                         rt2x00mmio_register_read(rt2x00dev, SEC_CSR3, &reg);
 438                         if (reg && reg == ~0)
 439                                 return -ENOSPC;
 440                 }
 441
 442                 key->hw_key_idx += reg ? ffz(reg) : 0;
 443
 444                 /*
 445                  * Upload key to hardware
 446                  */
 447                 memcpy(key_entry.key, crypto->key,
 448                        sizeof(key_entry.key));
 449                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 450                        sizeof(key_entry.tx_mic));
 451                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 452                        sizeof(key_entry.rx_mic));
 453
 454                 memset(&addr_entry, 0, sizeof(addr_entry));
 455                 memcpy(&addr_entry, crypto->address, ETH_ALEN);
 456                 addr_entry.cipher = crypto->cipher;
 457
 458                 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 459                 rt2x00mmio_register_multiwrite(rt2x00dev, reg,
 460                                                &key_entry, sizeof(key_entry));
 461
 462                 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
 463                 rt2x00mmio_register_multiwrite(rt2x00dev, reg,
 464                                                &addr_entry, sizeof(addr_entry));
 465
 466                 /*
 467                  * Enable pairwise lookup table for given BSS idx.
 468                  * Without this, received frames will not be decrypted
 469                  * by the hardware.
 470                  */
 471                 rt2x00mmio_register_read(rt2x00dev, SEC_CSR4, &reg);
 472                 reg |= (1 << crypto->bssidx);
 473                 rt2x00mmio_register_write(rt2x00dev, SEC_CSR4, reg);
 474
 475                 /*
 476                  * The driver does not support the IV/EIV generation
 477                  * in hardware. However it doesn't support the IV/EIV
 478                  * inside the ieee80211 frame either, but requires it
 479                  * to be provided separately for the descriptor.
 480                  * rt2x00lib will cut the IV/EIV data out of all frames
 481                  * given to us by mac80211, but we must tell mac80211
 482                  * to generate the IV/EIV data.
 483                  */
 484                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 485         }
 486
 487         /*
 488          * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
 489          * a particular key is valid. Because using the FIELD32()
 490          * defines directly will cause a lot of overhead, we use
 491          * a calculation to determine the correct bit directly.
 492          */
 493         if (key->hw_key_idx < 32) {
 494                 mask = 1 << key->hw_key_idx;
 495
 496                 rt2x00mmio_register_read(rt2x00dev, SEC_CSR2, &reg);
 497                 if (crypto->cmd == SET_KEY)
 498                         reg |= mask;
 499                 else if (crypto->cmd == DISABLE_KEY)
 500                         reg &= ~mask;
 501                 rt2x00mmio_register_write(rt2x00dev, SEC_CSR2, reg);
 502         } else {
 503                 mask = 1 << (key->hw_key_idx - 32);
 504
 505                 rt2x00mmio_register_read(rt2x00dev, SEC_CSR3, &reg);
 506                 if (crypto->cmd == SET_KEY)
 507                         reg |= mask;
 508                 else if (crypto->cmd == DISABLE_KEY)
 509                         reg &= ~mask;
 510                 rt2x00mmio_register_write(rt2x00dev, SEC_CSR3, reg);
 511         }
 512
 513         return 0;
 514 }
 515
 516 static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
 517                                   const unsigned int filter_flags)
 518 {
 519         u32 reg;
 520
 521         /*
 522          * Start configuration steps.
 523          * Note that the version error will always be dropped
 524          * and broadcast frames will always be accepted since
 525          * there is no filter for it at this time.
 526          */
 527         rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, &reg);
 528         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
 529                            !(filter_flags & FIF_FCSFAIL));
 530         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
 531                            !(filter_flags & FIF_PLCPFAIL));
 532         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
 533                            !(filter_flags & (FIF_CONTROL | FIF_PSPOLL)));
 534         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
 535                            !(filter_flags & FIF_PROMISC_IN_BSS));
 536         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
 537                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
 538                            !rt2x00dev->intf_ap_count);
 539         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
 540         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
 541                            !(filter_flags & FIF_ALLMULTI));
 542         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
 543         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
 544                            !(filter_flags & FIF_CONTROL));
 545         rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg);
 546 }
 547
 548 static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
 549                                 struct rt2x00_intf *intf,
 550                                 struct rt2x00intf_conf *conf,
 551                                 const unsigned int flags)
 552 {
 553         u32 reg;
 554
 555         if (flags & CONFIG_UPDATE_TYPE) {
 556                 /*
 557                  * Enable synchronisation.
 558                  */
 559                 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &reg);
 560                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
 561                 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
 562         }
 563
 564         if (flags & CONFIG_UPDATE_MAC) {
 565                 reg = le32_to_cpu(conf->mac[1]);
 566                 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
 567                 conf->mac[1] = cpu_to_le32(reg);
 568
 569                 rt2x00mmio_register_multiwrite(rt2x00dev, MAC_CSR2,
 570                                                conf->mac, sizeof(conf->mac));
 571         }
 572
 573         if (flags & CONFIG_UPDATE_BSSID) {
 574                 reg = le32_to_cpu(conf->bssid[1]);
 575                 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
 576                 conf->bssid[1] = cpu_to_le32(reg);
 577
 578                 rt2x00mmio_register_multiwrite(rt2x00dev, MAC_CSR4,
 579                                                conf->bssid,
 580                                                sizeof(conf->bssid));
 581         }
 582 }
 583
 584 static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
 585                                struct rt2x00lib_erp *erp,
 586                                u32 changed)
 587 {
 588         u32 reg;
 589
 590         rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, &reg);
 591         rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32);
 592         rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
 593         rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg);
 594
 595         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
 596                 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR4, &reg);
 597                 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
 598                 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
 599                                    !!erp->short_preamble);
 600                 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR4, reg);
 601         }
 602
 603         if (changed & BSS_CHANGED_BASIC_RATES)
 604                 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR5,
 605                                           erp->basic_rates);
 606
 607         if (changed & BSS_CHANGED_BEACON_INT) {
 608                 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &reg);
 609                 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
 610                                    erp->beacon_int * 16);
 611                 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
 612         }
 613
 614         if (changed & BSS_CHANGED_ERP_SLOT) {
 615                 rt2x00mmio_register_read(rt2x00dev, MAC_CSR9, &reg);
 616                 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
 617                 rt2x00mmio_register_write(rt2x00dev, MAC_CSR9, reg);
 618
 619                 rt2x00mmio_register_read(rt2x00dev, MAC_CSR8, &reg);
 620                 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
 621                 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
 622                 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
 623                 rt2x00mmio_register_write(rt2x00dev, MAC_CSR8, reg);
 624         }
 625 }
 626
 627 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
 628                                       struct antenna_setup *ant)
 629 {
 630         u8 r3;
 631         u8 r4;
 632         u8 r77;
 633
 634         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 635         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 636         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 637
 638         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF5325));
 639
 640         /*
 641          * Configure the RX antenna.
 642          */
 643         switch (ant->rx) {
 644         case ANTENNA_HW_DIVERSITY:
 645                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 646                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
 647                                   (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
 648                 break;
 649         case ANTENNA_A:
 650                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 651                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 652                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 653                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 654                 else
 655                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 656                 break;
 657         case ANTENNA_B:
 658         default:
 659                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 660                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 661                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 662                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 663                 else
 664                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 665                 break;
 666         }
 667
 668         rt61pci_bbp_write(rt2x00dev, 77, r77);
 669         rt61pci_bbp_write(rt2x00dev, 3, r3);
 670         rt61pci_bbp_write(rt2x00dev, 4, r4);
 671 }
 672
 673 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
 674                                       struct antenna_setup *ant)
 675 {
 676         u8 r3;
 677         u8 r4;
 678         u8 r77;
 679
 680         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 681         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 682         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 683
 684         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF2529));
 685         rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
 686                           !rt2x00_has_cap_frame_type(rt2x00dev));
 687
 688         /*
 689          * Configure the RX antenna.
 690          */
 691         switch (ant->rx) {
 692         case ANTENNA_HW_DIVERSITY:
 693                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 694                 break;
 695         case ANTENNA_A:
 696                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 697                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 698                 break;
 699         case ANTENNA_B:
 700         default:
 701                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 702                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 703                 break;
 704         }
 705
 706         rt61pci_bbp_write(rt2x00dev, 77, r77);
 707         rt61pci_bbp_write(rt2x00dev, 3, r3);
 708         rt61pci_bbp_write(rt2x00dev, 4, r4);
 709 }
 710
 711 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
 712                                            const int p1, const int p2)
 713 {
 714         u32 reg;
 715
 716         rt2x00mmio_register_read(rt2x00dev, MAC_CSR13, &reg);
 717
 718         rt2x00_set_field32(&reg, MAC_CSR13_DIR4, 0);
 719         rt2x00_set_field32(&reg, MAC_CSR13_VAL4, p1);
 720
 721         rt2x00_set_field32(&reg, MAC_CSR13_DIR3, 0);
 722         rt2x00_set_field32(&reg, MAC_CSR13_VAL3, !p2);
 723
 724         rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, reg);
 725 }
 726
 727 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
 728                                         struct antenna_setup *ant)
 729 {
 730         u8 r3;
 731         u8 r4;
 732         u8 r77;
 733
 734         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 735         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 736         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 737
 738         /*
 739          * Configure the RX antenna.
 740          */
 741         switch (ant->rx) {
 742         case ANTENNA_A:
 743                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 744                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 745                 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
 746                 break;
 747         case ANTENNA_HW_DIVERSITY:
 748                 /*
 749                  * FIXME: Antenna selection for the rf 2529 is very confusing
 750                  * in the legacy driver. Just default to antenna B until the
 751                  * legacy code can be properly translated into rt2x00 code.
 752                  */
 753         case ANTENNA_B:
 754         default:
 755                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 756                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 757                 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
 758                 break;
 759         }
 760
 761         rt61pci_bbp_write(rt2x00dev, 77, r77);
 762         rt61pci_bbp_write(rt2x00dev, 3, r3);
 763         rt61pci_bbp_write(rt2x00dev, 4, r4);
 764 }
 765
 766 struct antenna_sel {
 767         u8 word;
 768         /*
 769          * value[0] -> non-LNA
 770          * value[1] -> LNA
 771          */
 772         u8 value[2];
 773 };
 774
 775 static const struct antenna_sel antenna_sel_a[] = {
 776         { 96,  { 0x58, 0x78 } },
 777         { 104, { 0x38, 0x48 } },
 778         { 75,  { 0xfe, 0x80 } },
 779         { 86,  { 0xfe, 0x80 } },
 780         { 88,  { 0xfe, 0x80 } },
 781         { 35,  { 0x60, 0x60 } },
 782         { 97,  { 0x58, 0x58 } },
 783         { 98,  { 0x58, 0x58 } },
 784 };
 785
 786 static const struct antenna_sel antenna_sel_bg[] = {
 787         { 96,  { 0x48, 0x68 } },
 788         { 104, { 0x2c, 0x3c } },
 789         { 75,  { 0xfe, 0x80 } },
 790         { 86,  { 0xfe, 0x80 } },
 791         { 88,  { 0xfe, 0x80 } },
 792         { 35,  { 0x50, 0x50 } },
 793         { 97,  { 0x48, 0x48 } },
 794         { 98,  { 0x48, 0x48 } },
 795 };
 796
 797 static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev,
 798                                struct antenna_setup *ant)
 799 {
 800         const struct antenna_sel *sel;
 801         unsigned int lna;
 802         unsigned int i;
 803         u32 reg;
 804
 805         /*
 806          * We should never come here because rt2x00lib is supposed
 807          * to catch this and send us the correct antenna explicitely.
 808          */
 809         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 810                ant->tx == ANTENNA_SW_DIVERSITY);
 811
 812         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
 813                 sel = antenna_sel_a;
 814                 lna = rt2x00_has_cap_external_lna_a(rt2x00dev);
 815         } else {
 816                 sel = antenna_sel_bg;
 817                 lna = rt2x00_has_cap_external_lna_bg(rt2x00dev);
 818         }
 819
 820         for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
 821                 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
 822
 823         rt2x00mmio_register_read(rt2x00dev, PHY_CSR0, &reg);
 824
 825         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
 826                            rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 827         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
 828                            rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
 829
 830         rt2x00mmio_register_write(rt2x00dev, PHY_CSR0, reg);
 831
 832         if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325))
 833                 rt61pci_config_antenna_5x(rt2x00dev, ant);
 834         else if (rt2x00_rf(rt2x00dev, RF2527))
 835                 rt61pci_config_antenna_2x(rt2x00dev, ant);
 836         else if (rt2x00_rf(rt2x00dev, RF2529)) {
 837                 if (rt2x00_has_cap_double_antenna(rt2x00dev))
 838                         rt61pci_config_antenna_2x(rt2x00dev, ant);
 839                 else
 840                         rt61pci_config_antenna_2529(rt2x00dev, ant);
 841         }
 842 }
 843
 844 static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 845                                     struct rt2x00lib_conf *libconf)
 846 {
 847         u16 eeprom;
 848         short lna_gain = 0;
 849
 850         if (libconf->conf->chandef.chan->band == IEEE80211_BAND_2GHZ) {
 851                 if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
 852                         lna_gain += 14;
 853
 854                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
 855                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
 856         } else {
 857                 if (rt2x00_has_cap_external_lna_a(rt2x00dev))
 858                         lna_gain += 14;
 859
 860                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
 861                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
 862         }
 863
 864         rt2x00dev->lna_gain = lna_gain;
 865 }
 866
 867 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
 868                                    struct rf_channel *rf, const int txpower)
 869 {
 870         u8 r3;
 871         u8 r94;
 872         u8 smart;
 873
 874         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 875         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 876
 877         smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527));
 878
 879         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 880         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
 881         rt61pci_bbp_write(rt2x00dev, 3, r3);
 882
 883         r94 = 6;
 884         if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
 885                 r94 += txpower - MAX_TXPOWER;
 886         else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
 887                 r94 += txpower;
 888         rt61pci_bbp_write(rt2x00dev, 94, r94);
 889
 890         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 891         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 892         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 893         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 894
 895         udelay(200);
 896
 897         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 898         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 899         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 900         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 901
 902         udelay(200);
 903
 904         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 905         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 906         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 907         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 908
 909         msleep(1);
 910 }
 911
 912 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
 913                                    const int txpower)
 914 {
 915         struct rf_channel rf;
 916
 917         rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
 918         rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
 919         rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
 920         rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
 921
 922         rt61pci_config_channel(rt2x00dev, &rf, txpower);
 923 }
 924
 925 static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 926                                     struct rt2x00lib_conf *libconf)
 927 {
 928         u32 reg;
 929
 930         rt2x00mmio_register_read(rt2x00dev, TXRX_CSR4, &reg);
 931         rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1);
 932         rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_STEP, 0);
 933         rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0);
 934         rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
 935                            libconf->conf->long_frame_max_tx_count);
 936         rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
 937                            libconf->conf->short_frame_max_tx_count);
 938         rt2x00mmio_register_write(rt2x00dev, TXRX_CSR4, reg);
 939 }
 940
 941 static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev,
 942                                 struct rt2x00lib_conf *libconf)
 943 {
 944         enum dev_state state =
 945             (libconf->conf->flags & IEEE80211_CONF_PS) ?
 946                 STATE_SLEEP : STATE_AWAKE;
 947         u32 reg;
 948
 949         if (state == STATE_SLEEP) {
 950                 rt2x00mmio_register_read(rt2x00dev, MAC_CSR11, &reg);
 951                 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
 952                                    rt2x00dev->beacon_int - 10);
 953                 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
 954                                    libconf->conf->listen_interval - 1);
 955                 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
 956
 957                 /* We must first disable autowake before it can be enabled */
 958                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
 959                 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg);
 960
 961                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
 962                 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg);
 963
 964                 rt2x00mmio_register_write(rt2x00dev, SOFT_RESET_CSR,
 965                                           0x00000005);
 966                 rt2x00mmio_register_write(rt2x00dev, IO_CNTL_CSR, 0x0000001c);
 967                 rt2x00mmio_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000060);
 968
 969                 rt61pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0);
 970         } else {
 971                 rt2x00mmio_register_read(rt2x00dev, MAC_CSR11, &reg);
 972                 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
 973                 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
 974                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
 975                 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
 976                 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg);
 977
 978                 rt2x00mmio_register_write(rt2x00dev, SOFT_RESET_CSR,
 979                                           0x00000007);
 980                 rt2x00mmio_register_write(rt2x00dev, IO_CNTL_CSR, 0x00000018);
 981                 rt2x00mmio_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000020);
 982
 983                 rt61pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
 984         }
 985 }
 986
 987 static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
 988                            struct rt2x00lib_conf *libconf,
 989                            const unsigned int flags)
 990 {
 991         /* Always recalculate LNA gain before changing configuration */
 992         rt61pci_config_lna_gain(rt2x00dev, libconf);
 993
 994         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
 995                 rt61pci_config_channel(rt2x00dev, &libconf->rf,
 996                                        libconf->conf->power_level);
 997         if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
 998             !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
 999                 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
1000         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1001                 rt61pci_config_retry_limit(rt2x00dev, libconf);
1002         if (flags & IEEE80211_CONF_CHANGE_PS)
1003                 rt61pci_config_ps(rt2x00dev, libconf);
1004 }
1005
1006 /*
1007  * Link tuning
1008  */
1009 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
1010                                struct link_qual *qual)
1011 {
1012         u32 reg;
1013
1014         /*
1015          * Update FCS error count from register.
1016          */
1017         rt2x00mmio_register_read(rt2x00dev, STA_CSR0, &reg);
1018         qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
1019
1020         /*
1021          * Update False CCA count from register.
1022          */
1023         rt2x00mmio_register_read(rt2x00dev, STA_CSR1, &reg);
1024         qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
1025 }
1026
1027 static inline void rt61pci_set_vgc(struct rt2x00_dev *rt2x00dev,
1028                                    struct link_qual *qual, u8 vgc_level)
1029 {
1030         if (qual->vgc_level != vgc_level) {
1031                 rt61pci_bbp_write(rt2x00dev, 17, vgc_level);
1032                 qual->vgc_level = vgc_level;
1033                 qual->vgc_level_reg = vgc_level;
1034         }
1035 }
1036
1037 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
1038                                 struct link_qual *qual)
1039 {
1040         rt61pci_set_vgc(rt2x00dev, qual, 0x20);
1041 }
1042
1043 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev,
1044                                struct link_qual *qual, const u32 count)
1045 {
1046         u8 up_bound;
1047         u8 low_bound;
1048
1049         /*
1050          * Determine r17 bounds.
1051          */
1052         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1053                 low_bound = 0x28;
1054                 up_bound = 0x48;
1055                 if (rt2x00_has_cap_external_lna_a(rt2x00dev)) {
1056                         low_bound += 0x10;
1057                         up_bound += 0x10;
1058                 }
1059         } else {
1060                 low_bound = 0x20;
1061                 up_bound = 0x40;
1062                 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
1063                         low_bound += 0x10;
1064                         up_bound += 0x10;
1065                 }
1066         }
1067
1068         /*
1069          * If we are not associated, we should go straight to the
1070          * dynamic CCA tuning.
1071          */
1072         if (!rt2x00dev->intf_associated)
1073                 goto dynamic_cca_tune;
1074
1075         /*
1076          * Special big-R17 for very short distance
1077          */
1078         if (qual->rssi >= -35) {
1079                 rt61pci_set_vgc(rt2x00dev, qual, 0x60);
1080                 return;
1081         }
1082
1083         /*
1084          * Special big-R17 for short distance
1085          */
1086         if (qual->rssi >= -58) {
1087                 rt61pci_set_vgc(rt2x00dev, qual, up_bound);
1088                 return;
1089         }
1090
1091         /*
1092          * Special big-R17 for middle-short distance
1093          */
1094         if (qual->rssi >= -66) {
1095                 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x10);
1096                 return;
1097         }
1098
1099         /*
1100          * Special mid-R17 for middle distance
1101          */
1102         if (qual->rssi >= -74) {
1103                 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x08);
1104                 return;
1105         }
1106
1107         /*
1108          * Special case: Change up_bound based on the rssi.
1109          * Lower up_bound when rssi is weaker then -74 dBm.
1110          */
1111         up_bound -= 2 * (-74 - qual->rssi);
1112         if (low_bound > up_bound)
1113                 up_bound = low_bound;
1114
1115         if (qual->vgc_level > up_bound) {
1116                 rt61pci_set_vgc(rt2x00dev, qual, up_bound);
1117                 return;
1118         }
1119
1120 dynamic_cca_tune:
1121
1122         /*
1123          * r17 does not yet exceed upper limit, continue and base
1124          * the r17 tuning on the false CCA count.
1125          */
1126         if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
1127                 rt61pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
1128         else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
1129                 rt61pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
1130 }
1131
1132 /*
1133  * Queue handlers.
1134  */
1135 static void rt61pci_start_queue(struct data_queue *queue)
1136 {
1137         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1138         u32 reg;
1139
1140         switch (queue->qid) {
1141         case QID_RX:
1142                 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, &reg);
1143                 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1144                 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg);
1145                 break;
1146         case QID_BEACON:
1147                 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &reg);
1148                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1149                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1150                 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1151                 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
1152                 break;
1153         default:
1154                 break;
1155         }
1156 }
1157
1158 static void rt61pci_kick_queue(struct data_queue *queue)
1159 {
1160         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1161         u32 reg;
1162
1163         switch (queue->qid) {
1164         case QID_AC_VO:
1165                 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1166                 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, 1);
1167                 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1168                 break;
1169         case QID_AC_VI:
1170                 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1171                 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, 1);
1172                 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1173                 break;
1174         case QID_AC_BE:
1175                 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1176                 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, 1);
1177                 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1178                 break;
1179         case QID_AC_BK:
1180                 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1181                 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, 1);
1182                 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1183                 break;
1184         default:
1185                 break;
1186         }
1187 }
1188
1189 static void rt61pci_stop_queue(struct data_queue *queue)
1190 {
1191         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1192         u32 reg;
1193
1194         switch (queue->qid) {
1195         case QID_AC_VO:
1196                 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1197                 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1198                 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1199                 break;
1200         case QID_AC_VI:
1201                 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1202                 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1203                 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1204                 break;
1205         case QID_AC_BE:
1206                 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1207                 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1208                 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1209                 break;
1210         case QID_AC_BK:
1211                 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1212                 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1213                 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1214                 break;
1215         case QID_RX:
1216                 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, &reg);
1217                 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 1);
1218                 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg);
1219                 break;
1220         case QID_BEACON:
1221                 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &reg);
1222                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1223                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1224                 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1225                 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
1226
1227                 /*
1228                  * Wait for possibly running tbtt tasklets.
1229                  */
1230                 tasklet_kill(&rt2x00dev->tbtt_tasklet);
1231                 break;
1232         default:
1233                 break;
1234         }
1235 }
1236
1237 /*
1238  * Firmware functions
1239  */
1240 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1241 {
1242         u16 chip;
1243         char *fw_name;
1244
1245         pci_read_config_word(to_pci_dev(rt2x00dev->dev), PCI_DEVICE_ID, &chip);
1246         switch (chip) {
1247         case RT2561_PCI_ID:
1248                 fw_name = FIRMWARE_RT2561;
1249                 break;
1250         case RT2561s_PCI_ID:
1251                 fw_name = FIRMWARE_RT2561s;
1252                 break;
1253         case RT2661_PCI_ID:
1254                 fw_name = FIRMWARE_RT2661;
1255                 break;
1256         default:
1257                 fw_name = NULL;
1258                 break;
1259         }
1260
1261         return fw_name;
1262 }
1263
1264 static int rt61pci_check_firmware(struct rt2x00_dev *rt2x00dev,
1265                                   const u8 *data, const size_t len)
1266 {
1267         u16 fw_crc;
1268         u16 crc;
1269
1270         /*
1271          * Only support 8kb firmware files.
1272          */
1273         if (len != 8192)
1274                 return FW_BAD_LENGTH;
1275
1276         /*
1277          * The last 2 bytes in the firmware array are the crc checksum itself.
1278          * This means that we should never pass those 2 bytes to the crc
1279          * algorithm.
1280          */
1281         fw_crc = (data[len - 2] << 8 | data[len - 1]);
1282
1283         /*
1284          * Use the crc itu-t algorithm.
1285          */
1286         crc = crc_itu_t(0, data, len - 2);
1287         crc = crc_itu_t_byte(crc, 0);
1288         crc = crc_itu_t_byte(crc, 0);
1289
1290         return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
1291 }
1292
1293 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1294                                  const u8 *data, const size_t len)
1295 {
1296         int i;
1297         u32 reg;
1298
1299         /*
1300          * Wait for stable hardware.
1301          */
1302         for (i = 0; i < 100; i++) {
1303                 rt2x00mmio_register_read(rt2x00dev, MAC_CSR0, &reg);
1304                 if (reg)
1305                         break;
1306                 msleep(1);
1307         }
1308
1309         if (!reg) {
1310                 rt2x00_err(rt2x00dev, "Unstable hardware\n");
1311                 return -EBUSY;
1312         }
1313
1314         /*
1315          * Prepare MCU and mailbox for firmware loading.
1316          */
1317         reg = 0;
1318         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1319         rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1320         rt2x00mmio_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1321         rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1322         rt2x00mmio_register_write(rt2x00dev, HOST_CMD_CSR, 0);
1323
1324         /*
1325          * Write firmware to device.
1326          */
1327         reg = 0;
1328         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1329         rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
1330         rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1331
1332         rt2x00mmio_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1333                                        data, len);
1334
1335         rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
1336         rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1337
1338         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
1339         rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1340
1341         for (i = 0; i < 100; i++) {
1342                 rt2x00mmio_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
1343                 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
1344                         break;
1345                 msleep(1);
1346         }
1347
1348         if (i == 100) {
1349                 rt2x00_err(rt2x00dev, "MCU Control register not ready\n");
1350                 return -EBUSY;
1351         }
1352
1353         /*
1354          * Hardware needs another millisecond before it is ready.
1355          */
1356         msleep(1);
1357
1358         /*
1359          * Reset MAC and BBP registers.
1360          */
1361         reg = 0;
1362         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1363         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1364         rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg);
1365
1366         rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, &reg);
1367         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1368         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1369         rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg);
1370
1371         rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, &reg);
1372         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1373         rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg);
1374
1375         return 0;
1376 }
1377
1378 /*
1379  * Initialization functions.
1380  */
1381 static bool rt61pci_get_entry_state(struct queue_entry *entry)
1382 {
1383         struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
1384         u32 word;
1385
1386         if (entry->queue->qid == QID_RX) {
1387                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1388
1389                 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
1390         } else {
1391                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1392
1393                 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1394                         rt2x00_get_field32(word, TXD_W0_VALID));
1395         }
1396 }
1397
1398 static void rt61pci_clear_entry(struct queue_entry *entry)
1399 {
1400         struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
1401         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1402         u32 word;
1403
1404         if (entry->queue->qid == QID_RX) {
1405                 rt2x00_desc_read(entry_priv->desc, 5, &word);
1406                 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1407                                    skbdesc->skb_dma);
1408                 rt2x00_desc_write(entry_priv->desc, 5, word);
1409
1410                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1411                 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1412                 rt2x00_desc_write(entry_priv->desc, 0, word);
1413         } else {
1414                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1415                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1416                 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1417                 rt2x00_desc_write(entry_priv->desc, 0, word);
1418         }
1419 }
1420
1421 static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1422 {
1423         struct queue_entry_priv_mmio *entry_priv;
1424         u32 reg;
1425
1426         /*
1427          * Initialize registers.
1428          */
1429         rt2x00mmio_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1430         rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
1431                            rt2x00dev->tx[0].limit);
1432         rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
1433                            rt2x00dev->tx[1].limit);
1434         rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
1435                            rt2x00dev->tx[2].limit);
1436         rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
1437                            rt2x00dev->tx[3].limit);
1438         rt2x00mmio_register_write(rt2x00dev, TX_RING_CSR0, reg);
1439
1440         rt2x00mmio_register_read(rt2x00dev, TX_RING_CSR1, &reg);
1441         rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
1442                            rt2x00dev->tx[0].desc_size / 4);
1443         rt2x00mmio_register_write(rt2x00dev, TX_RING_CSR1, reg);
1444
1445         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1446         rt2x00mmio_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
1447         rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
1448                            entry_priv->desc_dma);
1449         rt2x00mmio_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1450
1451         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1452         rt2x00mmio_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
1453         rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
1454                            entry_priv->desc_dma);
1455         rt2x00mmio_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1456
1457         entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1458         rt2x00mmio_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
1459         rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
1460                            entry_priv->desc_dma);
1461         rt2x00mmio_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1462
1463         entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1464         rt2x00mmio_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
1465         rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
1466                            entry_priv->desc_dma);
1467         rt2x00mmio_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1468
1469         rt2x00mmio_register_read(rt2x00dev, RX_RING_CSR, &reg);
1470         rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
1471         rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1472                            rt2x00dev->rx->desc_size / 4);
1473         rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1474         rt2x00mmio_register_write(rt2x00dev, RX_RING_CSR, reg);
1475
1476         entry_priv = rt2x00dev->rx->entries[0].priv_data;
1477         rt2x00mmio_register_read(rt2x00dev, RX_BASE_CSR, &reg);
1478         rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
1479                            entry_priv->desc_dma);
1480         rt2x00mmio_register_write(rt2x00dev, RX_BASE_CSR, reg);
1481
1482         rt2x00mmio_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1483         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1484         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1485         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1486         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
1487         rt2x00mmio_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1488
1489         rt2x00mmio_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1490         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1491         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1492         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1493         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1494         rt2x00mmio_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1495
1496         rt2x00mmio_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1497         rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1498         rt2x00mmio_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1499
1500         return 0;
1501 }
1502
1503 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1504 {
1505         u32 reg;
1506
1507         rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, &reg);
1508         rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1509         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1510         rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1511         rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg);
1512
1513         rt2x00mmio_register_read(rt2x00dev, TXRX_CSR1, &reg);
1514         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1515         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1516         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1517         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1518         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1519         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1520         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1521         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1522         rt2x00mmio_register_write(rt2x00dev, TXRX_CSR1, reg);
1523
1524         /*
1525          * CCK TXD BBP registers
1526          */
1527         rt2x00mmio_register_read(rt2x00dev, TXRX_CSR2, &reg);
1528         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1529         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1530         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1531         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1532         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1533         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1534         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1535         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1536         rt2x00mmio_register_write(rt2x00dev, TXRX_CSR2, reg);
1537
1538         /*
1539          * OFDM TXD BBP registers
1540          */
1541         rt2x00mmio_register_read(rt2x00dev, TXRX_CSR3, &reg);
1542         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1543         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1544         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1545         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1546         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1547         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1548         rt2x00mmio_register_write(rt2x00dev, TXRX_CSR3, reg);
1549
1550         rt2x00mmio_register_read(rt2x00dev, TXRX_CSR7, &reg);
1551         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1552         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1553         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1554         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1555         rt2x00mmio_register_write(rt2x00dev, TXRX_CSR7, reg);
1556
1557         rt2x00mmio_register_read(rt2x00dev, TXRX_CSR8, &reg);
1558         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1559         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1560         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1561         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1562         rt2x00mmio_register_write(rt2x00dev, TXRX_CSR8, reg);
1563
1564         rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &reg);
1565         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1566         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1567         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1568         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1569         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1570         rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1571         rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
1572
1573         rt2x00mmio_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1574
1575         rt2x00mmio_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1576
1577         rt2x00mmio_register_read(rt2x00dev, MAC_CSR9, &reg);
1578         rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1579         rt2x00mmio_register_write(rt2x00dev, MAC_CSR9, reg);
1580
1581         rt2x00mmio_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1582
1583         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1584                 return -EBUSY;
1585
1586         rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1587
1588         /*
1589          * Invalidate all Shared Keys (SEC_CSR0),
1590          * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1591          */
1592         rt2x00mmio_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1593         rt2x00mmio_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1594         rt2x00mmio_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1595
1596         rt2x00mmio_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1597         rt2x00mmio_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1598         rt2x00mmio_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1599         rt2x00mmio_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1600
1601         rt2x00mmio_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1602
1603         rt2x00mmio_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1604
1605         rt2x00mmio_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1606
1607         /*
1608          * Clear all beacons
1609          * For the Beacon base registers we only need to clear
1610          * the first byte since that byte contains the VALID and OWNER
1611          * bits which (when set to 0) will invalidate the entire beacon.
1612          */
1613         rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1614         rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1615         rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1616         rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1617
1618         /*
1619          * We must clear the error counters.
1620          * These registers are cleared on read,
1621          * so we may pass a useless variable to store the value.
1622          */
1623         rt2x00mmio_register_read(rt2x00dev, STA_CSR0, &reg);
1624         rt2x00mmio_register_read(rt2x00dev, STA_CSR1, &reg);
1625         rt2x00mmio_register_read(rt2x00dev, STA_CSR2, &reg);
1626
1627         /*
1628          * Reset MAC and BBP registers.
1629          */
1630         rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, &reg);
1631         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1632         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1633         rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg);
1634
1635         rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, &reg);
1636         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1637         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1638         rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg);
1639
1640         rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, &reg);
1641         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1642         rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg);
1643
1644         return 0;
1645 }
1646
1647 static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1648 {
1649         unsigned int i;
1650         u8 value;
1651
1652         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1653                 rt61pci_bbp_read(rt2x00dev, 0, &value);
1654                 if ((value != 0xff) && (value != 0x00))
1655                         return 0;
1656                 udelay(REGISTER_BUSY_DELAY);
1657         }
1658
1659         rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
1660         return -EACCES;
1661 }
1662
1663 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1664 {
1665         unsigned int i;
1666         u16 eeprom;
1667         u8 reg_id;
1668         u8 value;
1669
1670         if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev)))
1671                 return -EACCES;
1672
1673         rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1674         rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1675         rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1676         rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1677         rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1678         rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1679         rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1680         rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1681         rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1682         rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1683         rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1684         rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1685         rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1686         rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1687         rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1688         rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1689         rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1690         rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1691         rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1692         rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1693         rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1694         rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1695         rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1696         rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1697
1698         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1699                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1700
1701                 if (eeprom != 0xffff && eeprom != 0x0000) {
1702                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1703                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1704                         rt61pci_bbp_write(rt2x00dev, reg_id, value);
1705                 }
1706         }
1707
1708         return 0;
1709 }
1710
1711 /*
1712  * Device state switch handlers.
1713  */
1714 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1715                                enum dev_state state)
1716 {
1717         int mask = (state == STATE_RADIO_IRQ_OFF);
1718         u32 reg;
1719         unsigned long flags;
1720
1721         /*
1722          * When interrupts are being enabled, the interrupt registers
1723          * should clear the register to assure a clean state.
1724          */
1725         if (state == STATE_RADIO_IRQ_ON) {
1726                 rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1727                 rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1728
1729                 rt2x00mmio_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1730                 rt2x00mmio_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1731         }
1732
1733         /*
1734          * Only toggle the interrupts bits we are going to use.
1735          * Non-checked interrupt bits are disabled by default.
1736          */
1737         spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
1738
1739         rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1740         rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1741         rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1742         rt2x00_set_field32(&reg, INT_MASK_CSR_BEACON_DONE, mask);
1743         rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1744         rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1745         rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
1746
1747         rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1748         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1749         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1750         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1751         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1752         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1753         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1754         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1755         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1756         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_TWAKEUP, mask);
1757         rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1758
1759         spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
1760
1761         if (state == STATE_RADIO_IRQ_OFF) {
1762                 /*
1763                  * Ensure that all tasklets are finished.
1764                  */
1765                 tasklet_kill(&rt2x00dev->txstatus_tasklet);
1766                 tasklet_kill(&rt2x00dev->rxdone_tasklet);
1767                 tasklet_kill(&rt2x00dev->autowake_tasklet);
1768                 tasklet_kill(&rt2x00dev->tbtt_tasklet);
1769         }
1770 }
1771
1772 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1773 {
1774         u32 reg;
1775
1776         /*
1777          * Initialize all registers.
1778          */
1779         if (unlikely(rt61pci_init_queues(rt2x00dev) ||
1780                      rt61pci_init_registers(rt2x00dev) ||
1781                      rt61pci_init_bbp(rt2x00dev)))
1782                 return -EIO;
1783
1784         /*
1785          * Enable RX.
1786          */
1787         rt2x00mmio_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1788         rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1789         rt2x00mmio_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1790
1791         return 0;
1792 }
1793
1794 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1795 {
1796         /*
1797          * Disable power
1798          */
1799         rt2x00mmio_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1800 }
1801
1802 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1803 {
1804         u32 reg, reg2;
1805         unsigned int i;
1806         char put_to_sleep;
1807
1808         put_to_sleep = (state != STATE_AWAKE);
1809
1810         rt2x00mmio_register_read(rt2x00dev, MAC_CSR12, &reg);
1811         rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1812         rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1813         rt2x00mmio_register_write(rt2x00dev, MAC_CSR12, reg);
1814
1815         /*
1816          * Device is not guaranteed to be in the requested state yet.
1817          * We must wait until the register indicates that the
1818          * device has entered the correct state.
1819          */
1820         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1821                 rt2x00mmio_register_read(rt2x00dev, MAC_CSR12, &reg2);
1822                 state = rt2x00_get_field32(reg2, MAC_CSR12_BBP_CURRENT_STATE);
1823                 if (state == !put_to_sleep)
1824                         return 0;
1825                 rt2x00mmio_register_write(rt2x00dev, MAC_CSR12, reg);
1826                 msleep(10);
1827         }
1828
1829         return -EBUSY;
1830 }
1831
1832 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1833                                     enum dev_state state)
1834 {
1835         int retval = 0;
1836
1837         switch (state) {
1838         case STATE_RADIO_ON:
1839                 retval = rt61pci_enable_radio(rt2x00dev);
1840                 break;
1841         case STATE_RADIO_OFF:
1842                 rt61pci_disable_radio(rt2x00dev);
1843                 break;
1844         case STATE_RADIO_IRQ_ON:
1845         case STATE_RADIO_IRQ_OFF:
1846                 rt61pci_toggle_irq(rt2x00dev, state);
1847                 break;
1848         case STATE_DEEP_SLEEP:
1849         case STATE_SLEEP:
1850         case STATE_STANDBY:
1851         case STATE_AWAKE:
1852                 retval = rt61pci_set_state(rt2x00dev, state);
1853                 break;
1854         default:
1855                 retval = -ENOTSUPP;
1856                 break;
1857         }
1858
1859         if (unlikely(retval))
1860                 rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
1861                            state, retval);
1862
1863         return retval;
1864 }
1865
1866 /*
1867  * TX descriptor initialization
1868  */
1869 static void rt61pci_write_tx_desc(struct queue_entry *entry,
1870                                   struct txentry_desc *txdesc)
1871 {
1872         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1873         struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
1874         __le32 *txd = entry_priv->desc;
1875         u32 word;
1876
1877         /*
1878          * Start writing the descriptor words.
1879          */
1880         rt2x00_desc_read(txd, 1, &word);
1881         rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, entry->queue->qid);
1882         rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->queue->aifs);
1883         rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min);
1884         rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max);
1885         rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1886         rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1887                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1888         rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1889         rt2x00_desc_write(txd, 1, word);
1890
1891         rt2x00_desc_read(txd, 2, &word);
1892         rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->u.plcp.signal);
1893         rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->u.plcp.service);
1894         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW,
1895                            txdesc->u.plcp.length_low);
1896         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH,
1897                            txdesc->u.plcp.length_high);
1898         rt2x00_desc_write(txd, 2, word);
1899
1900         if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1901                 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1902                 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
1903         }
1904
1905         rt2x00_desc_read(txd, 5, &word);
1906         rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid);
1907         rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
1908                            skbdesc->entry->entry_idx);
1909         rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1910                            TXPOWER_TO_DEV(entry->queue->rt2x00dev->tx_power));
1911         rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1912         rt2x00_desc_write(txd, 5, word);
1913
1914         if (entry->queue->qid != QID_BEACON) {
1915                 rt2x00_desc_read(txd, 6, &word);
1916                 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1917                                    skbdesc->skb_dma);
1918                 rt2x00_desc_write(txd, 6, word);
1919
1920                 rt2x00_desc_read(txd, 11, &word);
1921                 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0,
1922                                    txdesc->length);
1923                 rt2x00_desc_write(txd, 11, word);
1924         }
1925
1926         /*
1927          * Writing TXD word 0 must the last to prevent a race condition with
1928          * the device, whereby the device may take hold of the TXD before we
1929          * finished updating it.
1930          */
1931         rt2x00_desc_read(txd, 0, &word);
1932         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1933         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1934         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1935                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1936         rt2x00_set_field32(&word, TXD_W0_ACK,
1937                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1938         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1939                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1940         rt2x00_set_field32(&word, TXD_W0_OFDM,
1941                            (txdesc->rate_mode == RATE_MODE_OFDM));
1942         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
1943         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1944                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1945         rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1946                            test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1947         rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1948                            test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1949         rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1950         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
1951         rt2x00_set_field32(&word, TXD_W0_BURST,
1952                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1953         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1954         rt2x00_desc_write(txd, 0, word);
1955
1956         /*
1957          * Register descriptor details in skb frame descriptor.
1958          */
1959         skbdesc->desc = txd;
1960         skbdesc->desc_len = (entry->queue->qid == QID_BEACON) ? TXINFO_SIZE :
1961                             TXD_DESC_SIZE;
1962 }
1963
1964 /*
1965  * TX data initialization
1966  */
1967 static void rt61pci_write_beacon(struct queue_entry *entry,
1968                                  struct txentry_desc *txdesc)
1969 {
1970         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1971         struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
1972         unsigned int beacon_base;
1973         unsigned int padding_len;
1974         u32 orig_reg, reg;
1975
1976         /*
1977          * Disable beaconing while we are reloading the beacon data,
1978          * otherwise we might be sending out invalid data.
1979          */
1980         rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &reg);
1981         orig_reg = reg;
1982         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1983         rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
1984
1985         /*
1986          * Write the TX descriptor for the beacon.
1987          */
1988         rt61pci_write_tx_desc(entry, txdesc);
1989
1990         /*
1991          * Dump beacon to userspace through debugfs.
1992          */
1993         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1994
1995         /*
1996          * Write entire beacon with descriptor and padding to register.
1997          */
1998         padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
1999         if (padding_len && skb_pad(entry->skb, padding_len)) {
2000                 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
2001                 /* skb freed by skb_pad() on failure */
2002                 entry->skb = NULL;
2003                 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, orig_reg);
2004                 return;
2005         }
2006
2007         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
2008         rt2x00mmio_register_multiwrite(rt2x00dev, beacon_base,
2009                                        entry_priv->desc, TXINFO_SIZE);
2010         rt2x00mmio_register_multiwrite(rt2x00dev, beacon_base + TXINFO_SIZE,
2011                                        entry->skb->data,
2012                                        entry->skb->len + padding_len);
2013
2014         /*
2015          * Enable beaconing again.
2016          *
2017          * For Wi-Fi faily generated beacons between participating
2018          * stations. Set TBTT phase adaptive adjustment step to 8us.
2019          */
2020         rt2x00mmio_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
2021
2022         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
2023         rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
2024
2025         /*
2026          * Clean up beacon skb.
2027          */
2028         dev_kfree_skb_any(entry->skb);
2029         entry->skb = NULL;
2030 }
2031
2032 static void rt61pci_clear_beacon(struct queue_entry *entry)
2033 {
2034         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2035         u32 reg;
2036
2037         /*
2038          * Disable beaconing while we are reloading the beacon data,
2039          * otherwise we might be sending out invalid data.
2040          */
2041         rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &reg);
2042         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
2043         rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
2044
2045         /*
2046          * Clear beacon.
2047          */
2048         rt2x00mmio_register_write(rt2x00dev,
2049                                   HW_BEACON_OFFSET(entry->entry_idx), 0);
2050
2051         /*
2052          * Enable beaconing again.
2053          */
2054         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
2055         rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
2056 }
2057
2058 /*
2059  * RX control handlers
2060  */
2061 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
2062 {
2063         u8 offset = rt2x00dev->lna_gain;
2064         u8 lna;
2065
2066         lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
2067         switch (lna) {
2068         case 3:
2069                 offset += 90;
2070                 break;
2071         case 2:
2072                 offset += 74;
2073                 break;
2074         case 1:
2075                 offset += 64;
2076                 break;
2077         default:
2078                 return 0;
2079         }
2080
2081         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
2082                 if (lna == 3 || lna == 2)
2083                         offset += 10;
2084         }
2085
2086         return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
2087 }
2088
2089 static void rt61pci_fill_rxdone(struct queue_entry *entry,
2090                                 struct rxdone_entry_desc *rxdesc)
2091 {
2092         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2093         struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
2094         u32 word0;
2095         u32 word1;
2096
2097         rt2x00_desc_read(entry_priv->desc, 0, &word0);
2098         rt2x00_desc_read(entry_priv->desc, 1, &word1);
2099
2100         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
2101                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
2102
2103         rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
2104         rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
2105
2106         if (rxdesc->cipher != CIPHER_NONE) {
2107                 _rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv[0]);
2108                 _rt2x00_desc_read(entry_priv->desc, 3, &rxdesc->iv[1]);
2109                 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
2110
2111                 _rt2x00_desc_read(entry_priv->desc, 4, &rxdesc->icv);
2112                 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
2113
2114                 /*
2115                  * Hardware has stripped IV/EIV data from 802.11 frame during
2116                  * decryption. It has provided the data separately but rt2x00lib
2117                  * should decide if it should be reinserted.
2118                  */
2119                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2120
2121                 /*
2122                  * The hardware has already checked the Michael Mic and has
2123                  * stripped it from the frame. Signal this to mac80211.
2124                  */
2125                 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
2126
2127                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2128                         rxdesc->flags |= RX_FLAG_DECRYPTED;
2129                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2130                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2131         }
2132
2133         /*
2134          * Obtain the status about this packet.
2135          * When frame was received with an OFDM bitrate,
2136          * the signal is the PLCP value. If it was received with
2137          * a CCK bitrate the signal is the rate in 100kbit/s.
2138          */
2139         rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
2140         rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1);
2141         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
2142
2143         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
2144                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
2145         else
2146                 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
2147         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
2148                 rxdesc->dev_flags |= RXDONE_MY_BSS;
2149 }
2150
2151 /*
2152  * Interrupt functions.
2153  */
2154 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
2155 {
2156         struct data_queue *queue;
2157         struct queue_entry *entry;
2158         struct queue_entry *entry_done;
2159         struct queue_entry_priv_mmio *entry_priv;
2160         struct txdone_entry_desc txdesc;
2161         u32 word;
2162         u32 reg;
2163         int type;
2164         int index;
2165         int i;
2166
2167         /*
2168          * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
2169          * at most X times and also stop processing once the TX_STA_FIFO_VALID
2170          * flag is not set anymore.
2171          *
2172          * The legacy drivers use X=TX_RING_SIZE but state in a comment
2173          * that the TX_STA_FIFO stack has a size of 16. We stick to our
2174          * tx ring size for now.
2175          */
2176         for (i = 0; i < rt2x00dev->tx->limit; i++) {
2177                 rt2x00mmio_register_read(rt2x00dev, STA_CSR4, &reg);
2178                 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
2179                         break;
2180
2181                 /*
2182                  * Skip this entry when it contains an invalid
2183                  * queue identication number.
2184                  */
2185                 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
2186                 queue = rt2x00queue_get_tx_queue(rt2x00dev, type);
2187                 if (unlikely(!queue))
2188                         continue;
2189
2190                 /*
2191                  * Skip this entry when it contains an invalid
2192                  * index number.
2193                  */
2194                 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
2195                 if (unlikely(index >= queue->limit))
2196                         continue;
2197
2198                 entry = &queue->entries[index];
2199                 entry_priv = entry->priv_data;
2200                 rt2x00_desc_read(entry_priv->desc, 0, &word);
2201
2202                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
2203                     !rt2x00_get_field32(word, TXD_W0_VALID))
2204                         return;
2205
2206                 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2207                 while (entry != entry_done) {
2208                         /* Catch up.
2209                          * Just report any entries we missed as failed.
2210                          */
2211                         rt2x00_warn(rt2x00dev, "TX status report missed for entry %d\n",
2212                                     entry_done->entry_idx);
2213
2214                         rt2x00lib_txdone_noinfo(entry_done, TXDONE_UNKNOWN);
2215                         entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2216                 }
2217
2218                 /*
2219                  * Obtain the status about this packet.
2220                  */
2221                 txdesc.flags = 0;
2222                 switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) {
2223                 case 0: /* Success, maybe with retry */
2224                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2225                         break;
2226                 case 6: /* Failure, excessive retries */
2227                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
2228                         /* Don't break, this is a failed frame! */
2229                 default: /* Failure */
2230                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
2231                 }
2232                 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
2233
2234                 /*
2235                  * the frame was retried at least once
2236                  * -> hw used fallback rates
2237                  */
2238                 if (txdesc.retry)
2239                         __set_bit(TXDONE_FALLBACK, &txdesc.flags);
2240
2241                 rt2x00lib_txdone(entry, &txdesc);
2242         }
2243 }
2244
2245 static void rt61pci_wakeup(struct rt2x00_dev *rt2x00dev)
2246 {
2247         struct rt2x00lib_conf libconf = { .conf = &rt2x00dev->hw->conf };
2248
2249         rt61pci_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
2250 }
2251
2252 static inline void rt61pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
2253                                             struct rt2x00_field32 irq_field)
2254 {
2255         u32 reg;
2256
2257         /*
2258          * Enable a single interrupt. The interrupt mask register
2259          * access needs locking.
2260          */
2261         spin_lock_irq(&rt2x00dev->irqmask_lock);
2262
2263         rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, &reg);
2264         rt2x00_set_field32(&reg, irq_field, 0);
2265         rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
2266
2267         spin_unlock_irq(&rt2x00dev->irqmask_lock);
2268 }
2269
2270 static void rt61pci_enable_mcu_interrupt(struct rt2x00_dev *rt2x00dev,
2271                                          struct rt2x00_field32 irq_field)
2272 {
2273         u32 reg;
2274
2275         /*
2276          * Enable a single MCU interrupt. The interrupt mask register
2277          * access needs locking.
2278          */
2279         spin_lock_irq(&rt2x00dev->irqmask_lock);
2280
2281         rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
2282         rt2x00_set_field32(&reg, irq_field, 0);
2283         rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
2284
2285         spin_unlock_irq(&rt2x00dev->irqmask_lock);
2286 }
2287
2288 static void rt61pci_txstatus_tasklet(unsigned long data)
2289 {
2290         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
2291         rt61pci_txdone(rt2x00dev);
2292         if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2293                 rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TXDONE);
2294 }
2295
2296 static void rt61pci_tbtt_tasklet(unsigned long data)
2297 {
2298         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
2299         rt2x00lib_beacondone(rt2x00dev);
2300         if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2301                 rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_BEACON_DONE);
2302 }
2303
2304 static void rt61pci_rxdone_tasklet(unsigned long data)
2305 {
2306         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
2307         if (rt2x00mmio_rxdone(rt2x00dev))
2308                 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
2309         else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2310                 rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RXDONE);
2311 }
2312
2313 static void rt61pci_autowake_tasklet(unsigned long data)
2314 {
2315         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
2316         rt61pci_wakeup(rt2x00dev);
2317         rt2x00mmio_register_write(rt2x00dev,
2318                                   M2H_CMD_DONE_CSR, 0xffffffff);
2319         if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2320                 rt61pci_enable_mcu_interrupt(rt2x00dev, MCU_INT_MASK_CSR_TWAKEUP);
2321 }
2322
2323 static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
2324 {
2325         struct rt2x00_dev *rt2x00dev = dev_instance;
2326         u32 reg_mcu, mask_mcu;
2327         u32 reg, mask;
2328
2329         /*
2330          * Get the interrupt sources & saved to local variable.
2331          * Write register value back to clear pending interrupts.
2332          */
2333         rt2x00mmio_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
2334         rt2x00mmio_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
2335
2336         rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2337         rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2338
2339         if (!reg && !reg_mcu)
2340                 return IRQ_NONE;
2341
2342         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2343                 return IRQ_HANDLED;
2344
2345         /*
2346          * Schedule tasklets for interrupt handling.
2347          */
2348         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
2349                 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
2350
2351         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
2352                 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
2353
2354         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_BEACON_DONE))
2355                 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
2356
2357         if (rt2x00_get_field32(reg_mcu, MCU_INT_SOURCE_CSR_TWAKEUP))
2358                 tasklet_schedule(&rt2x00dev->autowake_tasklet);
2359
2360         /*
2361          * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
2362          * for interrupts and interrupt masks we can just use the value of
2363          * INT_SOURCE_CSR to create the interrupt mask.
2364          */
2365         mask = reg;
2366         mask_mcu = reg_mcu;
2367
2368         /*
2369          * Disable all interrupts for which a tasklet was scheduled right now,
2370          * the tasklet will reenable the appropriate interrupts.
2371          */
2372         spin_lock(&rt2x00dev->irqmask_lock);
2373
2374         rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, &reg);
2375         reg |= mask;
2376         rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
2377
2378         rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
2379         reg |= mask_mcu;
2380         rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
2381
2382         spin_unlock(&rt2x00dev->irqmask_lock);
2383
2384         return IRQ_HANDLED;
2385 }
2386
2387 /*
2388  * Device probe functions.
2389  */
2390 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2391 {
2392         struct eeprom_93cx6 eeprom;
2393         u32 reg;
2394         u16 word;
2395         u8 *mac;
2396         s8 value;
2397
2398         rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, &reg);
2399
2400         eeprom.data = rt2x00dev;
2401         eeprom.register_read = rt61pci_eepromregister_read;
2402         eeprom.register_write = rt61pci_eepromregister_write;
2403         eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
2404             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
2405         eeprom.reg_data_in = 0;
2406         eeprom.reg_data_out = 0;
2407         eeprom.reg_data_clock = 0;
2408         eeprom.reg_chip_select = 0;
2409
2410         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
2411                                EEPROM_SIZE / sizeof(u16));
2412
2413         /*
2414          * Start validation of the data that has been read.
2415          */
2416         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2417         if (!is_valid_ether_addr(mac)) {
2418                 eth_random_addr(mac);
2419                 rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac);
2420         }
2421
2422         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2423         if (word == 0xffff) {
2424                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
2425                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
2426                                    ANTENNA_B);
2427                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
2428                                    ANTENNA_B);
2429                 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
2430                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
2431                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
2432                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
2433                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2434                 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
2435         }
2436
2437         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2438         if (word == 0xffff) {
2439                 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
2440                 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
2441                 rt2x00_set_field16(&word, EEPROM_NIC_RX_FIXED, 0);
2442                 rt2x00_set_field16(&word, EEPROM_NIC_TX_FIXED, 0);
2443                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2444                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2445                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2446                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2447                 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
2448         }
2449
2450         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
2451         if (word == 0xffff) {
2452                 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
2453                                    LED_MODE_DEFAULT);
2454                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
2455                 rt2x00_eeprom_dbg(rt2x00dev, "Led: 0x%04x\n", word);
2456         }
2457
2458         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2459         if (word == 0xffff) {
2460                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2461                 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
2462                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2463                 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
2464         }
2465
2466         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
2467         if (word == 0xffff) {
2468                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2469                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2470                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2471                 rt2x00_eeprom_dbg(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2472         } else {
2473                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
2474                 if (value < -10 || value > 10)
2475                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2476                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
2477                 if (value < -10 || value > 10)
2478                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2479                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2480         }
2481
2482         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
2483         if (word == 0xffff) {
2484                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2485                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2486                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2487                 rt2x00_eeprom_dbg(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
2488         } else {
2489                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
2490                 if (value < -10 || value > 10)
2491                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2492                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
2493                 if (value < -10 || value > 10)
2494                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2495                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2496         }
2497
2498         return 0;
2499 }
2500
2501 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2502 {
2503         u32 reg;
2504         u16 value;
2505         u16 eeprom;
2506
2507         /*
2508          * Read EEPROM word for configuration.
2509          */
2510         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2511
2512         /*
2513          * Identify RF chipset.
2514          */
2515         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2516         rt2x00mmio_register_read(rt2x00dev, MAC_CSR0, &reg);
2517         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2518                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
2519
2520         if (!rt2x00_rf(rt2x00dev, RF5225) &&
2521             !rt2x00_rf(rt2x00dev, RF5325) &&
2522             !rt2x00_rf(rt2x00dev, RF2527) &&
2523             !rt2x00_rf(rt2x00dev, RF2529)) {
2524                 rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n");
2525                 return -ENODEV;
2526         }
2527
2528         /*
2529          * Determine number of antennas.
2530          */
2531         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
2532                 __set_bit(CAPABILITY_DOUBLE_ANTENNA, &rt2x00dev->cap_flags);
2533
2534         /*
2535          * Identify default antenna configuration.
2536          */
2537         rt2x00dev->default_ant.tx =
2538             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
2539         rt2x00dev->default_ant.rx =
2540             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
2541
2542         /*
2543          * Read the Frame type.
2544          */
2545         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
2546                 __set_bit(CAPABILITY_FRAME_TYPE, &rt2x00dev->cap_flags);
2547
2548         /*
2549          * Detect if this device has a hardware controlled radio.
2550          */
2551         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
2552                 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
2553
2554         /*
2555          * Read frequency offset and RF programming sequence.
2556          */
2557         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2558         if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2559                 __set_bit(CAPABILITY_RF_SEQUENCE, &rt2x00dev->cap_flags);
2560
2561         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2562
2563         /*
2564          * Read external LNA informations.
2565          */
2566         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2567
2568         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2569                 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
2570         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2571                 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
2572
2573         /*
2574          * When working with a RF2529 chip without double antenna,
2575          * the antenna settings should be gathered from the NIC
2576          * eeprom word.
2577          */
2578         if (rt2x00_rf(rt2x00dev, RF2529) &&
2579             !rt2x00_has_cap_double_antenna(rt2x00dev)) {
2580                 rt2x00dev->default_ant.rx =
2581                     ANTENNA_A + rt2x00_get_field16(eeprom, EEPROM_NIC_RX_FIXED);
2582                 rt2x00dev->default_ant.tx =
2583                     ANTENNA_B - rt2x00_get_field16(eeprom, EEPROM_NIC_TX_FIXED);
2584
2585                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2586                         rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2587                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2588                         rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2589         }
2590
2591         /*
2592          * Store led settings, for correct led behaviour.
2593          * If the eeprom value is invalid,
2594          * switch to default led mode.
2595          */
2596 #ifdef CONFIG_RT2X00_LIB_LEDS
2597         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2598         value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2599
2600         rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2601         rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2602         if (value == LED_MODE_SIGNAL_STRENGTH)
2603                 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
2604                                  LED_TYPE_QUALITY);
2605
2606         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2607         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
2608                            rt2x00_get_field16(eeprom,
2609                                               EEPROM_LED_POLARITY_GPIO_0));
2610         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
2611                            rt2x00_get_field16(eeprom,
2612                                               EEPROM_LED_POLARITY_GPIO_1));
2613         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
2614                            rt2x00_get_field16(eeprom,
2615                                               EEPROM_LED_POLARITY_GPIO_2));
2616         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
2617                            rt2x00_get_field16(eeprom,
2618                                               EEPROM_LED_POLARITY_GPIO_3));
2619         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
2620                            rt2x00_get_field16(eeprom,
2621                                               EEPROM_LED_POLARITY_GPIO_4));
2622         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
2623                            rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2624         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
2625                            rt2x00_get_field16(eeprom,
2626                                               EEPROM_LED_POLARITY_RDY_G));
2627         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
2628                            rt2x00_get_field16(eeprom,
2629                                               EEPROM_LED_POLARITY_RDY_A));
2630 #endif /* CONFIG_RT2X00_LIB_LEDS */
2631
2632         return 0;
2633 }
2634
2635 /*
2636  * RF value list for RF5225 & RF5325
2637  * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2638  */
2639 static const struct rf_channel rf_vals_noseq[] = {
2640         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2641         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2642         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2643         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2644         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2645         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2646         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2647         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2648         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2649         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2650         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2651         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2652         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2653         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2654
2655         /* 802.11 UNI / HyperLan 2 */
2656         { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2657         { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2658         { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2659         { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2660         { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2661         { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2662         { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2663         { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2664
2665         /* 802.11 HyperLan 2 */
2666         { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2667         { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2668         { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2669         { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2670         { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2671         { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2672         { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2673         { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2674         { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2675         { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2676
2677         /* 802.11 UNII */
2678         { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2679         { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2680         { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2681         { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2682         { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2683         { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2684
2685         /* MMAC(Japan)J52 ch 34,38,42,46 */
2686         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2687         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2688         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2689         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2690 };
2691
2692 /*
2693  * RF value list for RF5225 & RF5325
2694  * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2695  */
2696 static const struct rf_channel rf_vals_seq[] = {
2697         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2698         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2699         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2700         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2701         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2702         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2703         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2704         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2705         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2706         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2707         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2708         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2709         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2710         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2711
2712         /* 802.11 UNI / HyperLan 2 */
2713         { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2714         { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2715         { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2716         { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2717         { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2718         { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2719         { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2720         { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2721
2722         /* 802.11 HyperLan 2 */
2723         { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2724         { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2725         { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2726         { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2727         { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2728         { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2729         { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2730         { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2731         { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2732         { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2733
2734         /* 802.11 UNII */
2735         { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2736         { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2737         { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2738         { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2739         { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2740         { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2741
2742         /* MMAC(Japan)J52 ch 34,38,42,46 */
2743         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2744         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2745         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2746         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2747 };
2748
2749 static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2750 {
2751         struct hw_mode_spec *spec = &rt2x00dev->spec;
2752         struct channel_info *info;
2753         char *tx_power;
2754         unsigned int i;
2755
2756         /*
2757          * Disable powersaving as default.
2758          */
2759         rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2760
2761         /*
2762          * Initialize all hw fields.
2763          */
2764         rt2x00dev->hw->flags =
2765             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2766             IEEE80211_HW_SIGNAL_DBM |
2767             IEEE80211_HW_SUPPORTS_PS |
2768             IEEE80211_HW_PS_NULLFUNC_STACK;
2769
2770         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2771         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2772                                 rt2x00_eeprom_addr(rt2x00dev,
2773                                                    EEPROM_MAC_ADDR_0));
2774
2775         /*
2776          * As rt61 has a global fallback table we cannot specify
2777          * more then one tx rate per frame but since the hw will
2778          * try several rates (based on the fallback table) we should
2779          * initialize max_report_rates to the maximum number of rates
2780          * we are going to try. Otherwise mac80211 will truncate our
2781          * reported tx rates and the rc algortihm will end up with
2782          * incorrect data.
2783          */
2784         rt2x00dev->hw->max_rates = 1;
2785         rt2x00dev->hw->max_report_rates = 7;
2786         rt2x00dev->hw->max_rate_tries = 1;
2787
2788         /*
2789          * Initialize hw_mode information.
2790          */
2791         spec->supported_bands = SUPPORT_BAND_2GHZ;
2792         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2793
2794         if (!rt2x00_has_cap_rf_sequence(rt2x00dev)) {
2795                 spec->num_channels = 14;
2796                 spec->channels = rf_vals_noseq;
2797         } else {
2798                 spec->num_channels = 14;
2799                 spec->channels = rf_vals_seq;
2800         }
2801
2802         if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325)) {
2803                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2804                 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2805         }
2806
2807         /*
2808          * Create channel information array
2809          */
2810         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
2811         if (!info)
2812                 return -ENOMEM;
2813
2814         spec->channels_info = info;
2815
2816         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2817         for (i = 0; i < 14; i++) {
2818                 info[i].max_power = MAX_TXPOWER;
2819                 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2820         }
2821
2822         if (spec->num_channels > 14) {
2823                 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2824                 for (i = 14; i < spec->num_channels; i++) {
2825                         info[i].max_power = MAX_TXPOWER;
2826                         info[i].default_power1 =
2827                                         TXPOWER_FROM_DEV(tx_power[i - 14]);
2828                 }
2829         }
2830
2831         return 0;
2832 }
2833
2834 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2835 {
2836         int retval;
2837         u32 reg;
2838
2839         /*
2840          * Disable power saving.
2841          */
2842         rt2x00mmio_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
2843
2844         /*
2845          * Allocate eeprom data.
2846          */
2847         retval = rt61pci_validate_eeprom(rt2x00dev);
2848         if (retval)
2849                 return retval;
2850
2851         retval = rt61pci_init_eeprom(rt2x00dev);
2852         if (retval)
2853                 return retval;
2854
2855         /*
2856          * Enable rfkill polling by setting GPIO direction of the
2857          * rfkill switch GPIO pin correctly.
2858          */
2859         rt2x00mmio_register_read(rt2x00dev, MAC_CSR13, &reg);
2860         rt2x00_set_field32(&reg, MAC_CSR13_DIR5, 1);
2861         rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, reg);
2862
2863         /*
2864          * Initialize hw specifications.
2865          */
2866         retval = rt61pci_probe_hw_mode(rt2x00dev);
2867         if (retval)
2868                 return retval;
2869
2870         /*
2871          * This device has multiple filters for control frames,
2872          * but has no a separate filter for PS Poll frames.
2873          */
2874         __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
2875
2876         /*
2877          * This device requires firmware and DMA mapped skbs.
2878          */
2879         __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
2880         __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
2881         if (!modparam_nohwcrypt)
2882                 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
2883         __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
2884
2885         /*
2886          * Set the rssi offset.
2887          */
2888         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2889
2890         return 0;
2891 }
2892
2893 /*
2894  * IEEE80211 stack callback functions.
2895  */
2896 static int rt61pci_conf_tx(struct ieee80211_hw *hw,
2897                            struct ieee80211_vif *vif, u16 queue_idx,
2898                            const struct ieee80211_tx_queue_params *params)
2899 {
2900         struct rt2x00_dev *rt2x00dev = hw->priv;
2901         struct data_queue *queue;
2902         struct rt2x00_field32 field;
2903         int retval;
2904         u32 reg;
2905         u32 offset;
2906
2907         /*
2908          * First pass the configuration through rt2x00lib, that will
2909          * update the queue settings and validate the input. After that
2910          * we are free to update the registers based on the value
2911          * in the queue parameter.
2912          */
2913         retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
2914         if (retval)
2915                 return retval;
2916
2917         /*
2918          * We only need to perform additional register initialization
2919          * for WMM queues.
2920          */
2921         if (queue_idx >= 4)
2922                 return 0;
2923
2924         queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
2925
2926         /* Update WMM TXOP register */
2927         offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
2928         field.bit_offset = (queue_idx & 1) * 16;
2929         field.bit_mask = 0xffff << field.bit_offset;
2930
2931         rt2x00mmio_register_read(rt2x00dev, offset, &reg);
2932         rt2x00_set_field32(&reg, field, queue->txop);
2933         rt2x00mmio_register_write(rt2x00dev, offset, reg);
2934
2935         /* Update WMM registers */
2936         field.bit_offset = queue_idx * 4;
2937         field.bit_mask = 0xf << field.bit_offset;
2938
2939         rt2x00mmio_register_read(rt2x00dev, AIFSN_CSR, &reg);
2940         rt2x00_set_field32(&reg, field, queue->aifs);
2941         rt2x00mmio_register_write(rt2x00dev, AIFSN_CSR, reg);
2942
2943         rt2x00mmio_register_read(rt2x00dev, CWMIN_CSR, &reg);
2944         rt2x00_set_field32(&reg, field, queue->cw_min);
2945         rt2x00mmio_register_write(rt2x00dev, CWMIN_CSR, reg);
2946
2947         rt2x00mmio_register_read(rt2x00dev, CWMAX_CSR, &reg);
2948         rt2x00_set_field32(&reg, field, queue->cw_max);
2949         rt2x00mmio_register_write(rt2x00dev, CWMAX_CSR, reg);
2950
2951         return 0;
2952 }
2953
2954 static u64 rt61pci_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2955 {
2956         struct rt2x00_dev *rt2x00dev = hw->priv;
2957         u64 tsf;
2958         u32 reg;
2959
2960         rt2x00mmio_register_read(rt2x00dev, TXRX_CSR13, &reg);
2961         tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2962         rt2x00mmio_register_read(rt2x00dev, TXRX_CSR12, &reg);
2963         tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2964
2965         return tsf;
2966 }
2967
2968 static const struct ieee80211_ops rt61pci_mac80211_ops = {
2969         .tx                     = rt2x00mac_tx,
2970         .start                  = rt2x00mac_start,
2971         .stop                   = rt2x00mac_stop,
2972         .add_interface          = rt2x00mac_add_interface,
2973         .remove_interface       = rt2x00mac_remove_interface,
2974         .config                 = rt2x00mac_config,
2975         .configure_filter       = rt2x00mac_configure_filter,
2976         .set_key                = rt2x00mac_set_key,
2977         .sw_scan_start          = rt2x00mac_sw_scan_start,
2978         .sw_scan_complete       = rt2x00mac_sw_scan_complete,
2979         .get_stats              = rt2x00mac_get_stats,
2980         .bss_info_changed       = rt2x00mac_bss_info_changed,
2981         .conf_tx                = rt61pci_conf_tx,
2982         .get_tsf                = rt61pci_get_tsf,
2983         .rfkill_poll            = rt2x00mac_rfkill_poll,
2984         .flush                  = rt2x00mac_flush,
2985         .set_antenna            = rt2x00mac_set_antenna,
2986         .get_antenna            = rt2x00mac_get_antenna,
2987         .get_ringparam          = rt2x00mac_get_ringparam,
2988         .tx_frames_pending      = rt2x00mac_tx_frames_pending,
2989 };
2990
2991 static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2992         .irq_handler            = rt61pci_interrupt,
2993         .txstatus_tasklet       = rt61pci_txstatus_tasklet,
2994         .tbtt_tasklet           = rt61pci_tbtt_tasklet,
2995         .rxdone_tasklet         = rt61pci_rxdone_tasklet,
2996         .autowake_tasklet       = rt61pci_autowake_tasklet,
2997         .probe_hw               = rt61pci_probe_hw,
2998         .get_firmware_name      = rt61pci_get_firmware_name,
2999         .check_firmware         = rt61pci_check_firmware,
3000         .load_firmware          = rt61pci_load_firmware,
3001         .initialize             = rt2x00mmio_initialize,
3002         .uninitialize           = rt2x00mmio_uninitialize,
3003         .get_entry_state        = rt61pci_get_entry_state,
3004         .clear_entry            = rt61pci_clear_entry,
3005         .set_device_state       = rt61pci_set_device_state,
3006         .rfkill_poll            = rt61pci_rfkill_poll,
3007         .link_stats             = rt61pci_link_stats,
3008         .reset_tuner            = rt61pci_reset_tuner,
3009         .link_tuner             = rt61pci_link_tuner,
3010         .start_queue            = rt61pci_start_queue,
3011         .kick_queue             = rt61pci_kick_queue,
3012         .stop_queue             = rt61pci_stop_queue,
3013         .flush_queue            = rt2x00mmio_flush_queue,
3014         .write_tx_desc          = rt61pci_write_tx_desc,
3015         .write_beacon           = rt61pci_write_beacon,
3016         .clear_beacon           = rt61pci_clear_beacon,
3017         .fill_rxdone            = rt61pci_fill_rxdone,
3018         .config_shared_key      = rt61pci_config_shared_key,
3019         .config_pairwise_key    = rt61pci_config_pairwise_key,
3020         .config_filter          = rt61pci_config_filter,
3021         .config_intf            = rt61pci_config_intf,
3022         .config_erp             = rt61pci_config_erp,
3023         .config_ant             = rt61pci_config_ant,
3024         .config                 = rt61pci_config,
3025 };
3026
3027 static void rt61pci_queue_init(struct data_queue *queue)
3028 {
3029         switch (queue->qid) {
3030         case QID_RX:
3031                 queue->limit = 32;
3032                 queue->data_size = DATA_FRAME_SIZE;
3033                 queue->desc_size = RXD_DESC_SIZE;
3034                 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
3035                 break;
3036
3037         case QID_AC_VO:
3038         case QID_AC_VI:
3039         case QID_AC_BE:
3040         case QID_AC_BK:
3041                 queue->limit = 32;
3042                 queue->data_size = DATA_FRAME_SIZE;
3043                 queue->desc_size = TXD_DESC_SIZE;
3044                 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
3045                 break;
3046
3047         case QID_BEACON:
3048                 queue->limit = 4;
3049                 queue->data_size = 0; /* No DMA required for beacons */
3050                 queue->desc_size = TXINFO_SIZE;
3051                 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
3052                 break;
3053
3054         case QID_ATIM:
3055                 /* fallthrough */
3056         default:
3057                 BUG();
3058                 break;
3059         }
3060 }
3061
3062 static const struct rt2x00_ops rt61pci_ops = {
3063         .name                   = KBUILD_MODNAME,
3064         .max_ap_intf            = 4,
3065         .eeprom_size            = EEPROM_SIZE,
3066         .rf_size                = RF_SIZE,
3067         .tx_queues              = NUM_TX_QUEUES,
3068         .queue_init             = rt61pci_queue_init,
3069         .lib                    = &rt61pci_rt2x00_ops,
3070         .hw                     = &rt61pci_mac80211_ops,
3071 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
3072         .debugfs                = &rt61pci_rt2x00debug,
3073 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
3074 };
3075
3076 /*
3077  * RT61pci module information.
3078  */
3079 static DEFINE_PCI_DEVICE_TABLE(rt61pci_device_table) = {
3080         /* RT2561s */
3081         { PCI_DEVICE(0x1814, 0x0301) },
3082         /* RT2561 v2 */
3083         { PCI_DEVICE(0x1814, 0x0302) },
3084         /* RT2661 */
3085         { PCI_DEVICE(0x1814, 0x0401) },
3086         { 0, }
3087 };
3088
3089 MODULE_AUTHOR(DRV_PROJECT);
3090 MODULE_VERSION(DRV_VERSION);
3091 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
3092 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
3093                         "PCI & PCMCIA chipset based cards");
3094 MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
3095 MODULE_FIRMWARE(FIRMWARE_RT2561);
3096 MODULE_FIRMWARE(FIRMWARE_RT2561s);
3097 MODULE_FIRMWARE(FIRMWARE_RT2661);
3098 MODULE_LICENSE("GPL");
3099
3100 static int rt61pci_probe(struct pci_dev *pci_dev,
3101                          const struct pci_device_id *id)
3102 {
3103         return rt2x00pci_probe(pci_dev, &rt61pci_ops);
3104 }
3105
3106 static struct pci_driver rt61pci_driver = {
3107         .name           = KBUILD_MODNAME,
3108         .id_table       = rt61pci_device_table,
3109         .probe          = rt61pci_probe,
3110         .remove         = rt2x00pci_remove,
3111         .suspend        = rt2x00pci_suspend,
3112         .resume         = rt2x00pci_resume,
3113 };
3114
3115 module_pci_driver(rt61pci_driver);