Pileus Git - ~andy/linux/blob - drivers/net/wireless/rt2x00/rt2800lib.c

   1 /*
   2         Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
   3         Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
   4         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
   5         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
   6
   7         Based on the original rt2800pci.c and rt2800usb.c.
   8           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   9           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  10           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  11           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  12           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  13           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  14           <http://rt2x00.serialmonkey.com>
  15
  16         This program is free software; you can redistribute it and/or modify
  17         it under the terms of the GNU General Public License as published by
  18         the Free Software Foundation; either version 2 of the License, or
  19         (at your option) any later version.
  20
  21         This program is distributed in the hope that it will be useful,
  22         but WITHOUT ANY WARRANTY; without even the implied warranty of
  23         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24         GNU General Public License for more details.
  25
  26         You should have received a copy of the GNU General Public License
  27         along with this program; if not, write to the
  28         Free Software Foundation, Inc.,
  29         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  30  */
  31
  32 /*
  33         Module: rt2800lib
  34         Abstract: rt2800 generic device routines.
  35  */
  36
  37 #include <linux/crc-ccitt.h>
  38 #include <linux/kernel.h>
  39 #include <linux/module.h>
  40 #include <linux/slab.h>
  41
  42 #include "rt2x00.h"
  43 #include "rt2800lib.h"
  44 #include "rt2800.h"
  45
  46 /*
  47  * Register access.
  48  * All access to the CSR registers will go through the methods
  49  * rt2800_register_read and rt2800_register_write.
  50  * BBP and RF register require indirect register access,
  51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  52  * These indirect registers work with busy bits,
  53  * and we will try maximal REGISTER_BUSY_COUNT times to access
  54  * the register while taking a REGISTER_BUSY_DELAY us delay
  55  * between each attampt. When the busy bit is still set at that time,
  56  * the access attempt is considered to have failed,
  57  * and we will print an error.
  58  * The _lock versions must be used if you already hold the csr_mutex
  59  */
  60 #define WAIT_FOR_BBP(__dev, __reg) \
  61         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  62 #define WAIT_FOR_RFCSR(__dev, __reg) \
  63         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  64 #define WAIT_FOR_RF(__dev, __reg) \
  65         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  66 #define WAIT_FOR_MCU(__dev, __reg) \
  67         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  68                             H2M_MAILBOX_CSR_OWNER, (__reg))
  69
  70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
  71 {
  72         /* check for rt2872 on SoC */
  73         if (!rt2x00_is_soc(rt2x00dev) ||
  74             !rt2x00_rt(rt2x00dev, RT2872))
  75                 return false;
  76
  77         /* we know for sure that these rf chipsets are used on rt305x boards */
  78         if (rt2x00_rf(rt2x00dev, RF3020) ||
  79             rt2x00_rf(rt2x00dev, RF3021) ||
  80             rt2x00_rf(rt2x00dev, RF3022))
  81                 return true;
  82
  83         NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
  84         return false;
  85 }
  86
  87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  88                              const unsigned int word, const u8 value)
  89 {
  90         u32 reg;
  91
  92         mutex_lock(&rt2x00dev->csr_mutex);
  93
  94         /*
  95          * Wait until the BBP becomes available, afterwards we
  96          * can safely write the new data into the register.
  97          */
  98         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  99                 reg = 0;
 100                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
 101                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 102                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 103                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
 104                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 105
 106                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 107         }
 108
 109         mutex_unlock(&rt2x00dev->csr_mutex);
 110 }
 111
 112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 113                             const unsigned int word, u8 *value)
 114 {
 115         u32 reg;
 116
 117         mutex_lock(&rt2x00dev->csr_mutex);
 118
 119         /*
 120          * Wait until the BBP becomes available, afterwards we
 121          * can safely write the read request into the register.
 122          * After the data has been written, we wait until hardware
 123          * returns the correct value, if at any time the register
 124          * doesn't become available in time, reg will be 0xffffffff
 125          * which means we return 0xff to the caller.
 126          */
 127         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 128                 reg = 0;
 129                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 130                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 131                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 132                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 133
 134                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 135
 136                 WAIT_FOR_BBP(rt2x00dev, &reg);
 137         }
 138
 139         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 140
 141         mutex_unlock(&rt2x00dev->csr_mutex);
 142 }
 143
 144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 145                                const unsigned int word, const u8 value)
 146 {
 147         u32 reg;
 148
 149         mutex_lock(&rt2x00dev->csr_mutex);
 150
 151         /*
 152          * Wait until the RFCSR becomes available, afterwards we
 153          * can safely write the new data into the register.
 154          */
 155         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 156                 reg = 0;
 157                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 158                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 159                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 160                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 161
 162                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 163         }
 164
 165         mutex_unlock(&rt2x00dev->csr_mutex);
 166 }
 167
 168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 169                               const unsigned int word, u8 *value)
 170 {
 171         u32 reg;
 172
 173         mutex_lock(&rt2x00dev->csr_mutex);
 174
 175         /*
 176          * Wait until the RFCSR becomes available, afterwards we
 177          * can safely write the read request into the register.
 178          * After the data has been written, we wait until hardware
 179          * returns the correct value, if at any time the register
 180          * doesn't become available in time, reg will be 0xffffffff
 181          * which means we return 0xff to the caller.
 182          */
 183         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 184                 reg = 0;
 185                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 186                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 187                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 188
 189                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 190
 191                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 192         }
 193
 194         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 195
 196         mutex_unlock(&rt2x00dev->csr_mutex);
 197 }
 198
 199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 200                             const unsigned int word, const u32 value)
 201 {
 202         u32 reg;
 203
 204         mutex_lock(&rt2x00dev->csr_mutex);
 205
 206         /*
 207          * Wait until the RF becomes available, afterwards we
 208          * can safely write the new data into the register.
 209          */
 210         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 211                 reg = 0;
 212                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 213                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 214                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 215                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 216
 217                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 218                 rt2x00_rf_write(rt2x00dev, word, value);
 219         }
 220
 221         mutex_unlock(&rt2x00dev->csr_mutex);
 222 }
 223
 224 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 225                         const u8 command, const u8 token,
 226                         const u8 arg0, const u8 arg1)
 227 {
 228         u32 reg;
 229
 230         /*
 231          * SOC devices don't support MCU requests.
 232          */
 233         if (rt2x00_is_soc(rt2x00dev))
 234                 return;
 235
 236         mutex_lock(&rt2x00dev->csr_mutex);
 237
 238         /*
 239          * Wait until the MCU becomes available, afterwards we
 240          * can safely write the new data into the register.
 241          */
 242         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 243                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 244                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 245                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 246                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 247                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 248
 249                 reg = 0;
 250                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 251                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 252         }
 253
 254         mutex_unlock(&rt2x00dev->csr_mutex);
 255 }
 256 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
 257
 258 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
 259 {
 260         unsigned int i = 0;
 261         u32 reg;
 262
 263         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 264                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
 265                 if (reg && reg != ~0)
 266                         return 0;
 267                 msleep(1);
 268         }
 269
 270         ERROR(rt2x00dev, "Unstable hardware.\n");
 271         return -EBUSY;
 272 }
 273 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
 274
 275 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
 276 {
 277         unsigned int i;
 278         u32 reg;
 279
 280         /*
 281          * Some devices are really slow to respond here. Wait a whole second
 282          * before timing out.
 283          */
 284         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 285                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 286                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 287                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
 288                         return 0;
 289
 290                 msleep(10);
 291         }
 292
 293         ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
 294         return -EACCES;
 295 }
 296 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
 297
 298 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
 299 {
 300         u16 fw_crc;
 301         u16 crc;
 302
 303         /*
 304          * The last 2 bytes in the firmware array are the crc checksum itself,
 305          * this means that we should never pass those 2 bytes to the crc
 306          * algorithm.
 307          */
 308         fw_crc = (data[len - 2] << 8 | data[len - 1]);
 309
 310         /*
 311          * Use the crc ccitt algorithm.
 312          * This will return the same value as the legacy driver which
 313          * used bit ordering reversion on the both the firmware bytes
 314          * before input input as well as on the final output.
 315          * Obviously using crc ccitt directly is much more efficient.
 316          */
 317         crc = crc_ccitt(~0, data, len - 2);
 318
 319         /*
 320          * There is a small difference between the crc-itu-t + bitrev and
 321          * the crc-ccitt crc calculation. In the latter method the 2 bytes
 322          * will be swapped, use swab16 to convert the crc to the correct
 323          * value.
 324          */
 325         crc = swab16(crc);
 326
 327         return fw_crc == crc;
 328 }
 329
 330 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
 331                           const u8 *data, const size_t len)
 332 {
 333         size_t offset = 0;
 334         size_t fw_len;
 335         bool multiple;
 336
 337         /*
 338          * PCI(e) & SOC devices require firmware with a length
 339          * of 8kb. USB devices require firmware files with a length
 340          * of 4kb. Certain USB chipsets however require different firmware,
 341          * which Ralink only provides attached to the original firmware
 342          * file. Thus for USB devices, firmware files have a length
 343          * which is a multiple of 4kb.
 344          */
 345         if (rt2x00_is_usb(rt2x00dev)) {
 346                 fw_len = 4096;
 347                 multiple = true;
 348         } else {
 349                 fw_len = 8192;
 350                 multiple = true;
 351         }
 352
 353         /*
 354          * Validate the firmware length
 355          */
 356         if (len != fw_len && (!multiple || (len % fw_len) != 0))
 357                 return FW_BAD_LENGTH;
 358
 359         /*
 360          * Check if the chipset requires one of the upper parts
 361          * of the firmware.
 362          */
 363         if (rt2x00_is_usb(rt2x00dev) &&
 364             !rt2x00_rt(rt2x00dev, RT2860) &&
 365             !rt2x00_rt(rt2x00dev, RT2872) &&
 366             !rt2x00_rt(rt2x00dev, RT3070) &&
 367             ((len / fw_len) == 1))
 368                 return FW_BAD_VERSION;
 369
 370         /*
 371          * 8kb firmware files must be checked as if it were
 372          * 2 separate firmware files.
 373          */
 374         while (offset < len) {
 375                 if (!rt2800_check_firmware_crc(data + offset, fw_len))
 376                         return FW_BAD_CRC;
 377
 378                 offset += fw_len;
 379         }
 380
 381         return FW_OK;
 382 }
 383 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
 384
 385 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
 386                          const u8 *data, const size_t len)
 387 {
 388         unsigned int i;
 389         u32 reg;
 390
 391         /*
 392          * If driver doesn't wake up firmware here,
 393          * rt2800_load_firmware will hang forever when interface is up again.
 394          */
 395         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
 396
 397         /*
 398          * Wait for stable hardware.
 399          */
 400         if (rt2800_wait_csr_ready(rt2x00dev))
 401                 return -EBUSY;
 402
 403         if (rt2x00_is_pci(rt2x00dev)) {
 404                 if (rt2x00_rt(rt2x00dev, RT3572) ||
 405                     rt2x00_rt(rt2x00dev, RT5390)) {
 406                         rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
 407                         rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
 408                         rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
 409                         rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
 410                 }
 411                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
 412         }
 413
 414         /*
 415          * Write firmware to the device.
 416          */
 417         rt2800_drv_write_firmware(rt2x00dev, data, len);
 418
 419         /*
 420          * Wait for device to stabilize.
 421          */
 422         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 423                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
 424                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
 425                         break;
 426                 msleep(1);
 427         }
 428
 429         if (i == REGISTER_BUSY_COUNT) {
 430                 ERROR(rt2x00dev, "PBF system register not ready.\n");
 431                 return -EBUSY;
 432         }
 433
 434         /*
 435          * Disable DMA, will be reenabled later when enabling
 436          * the radio.
 437          */
 438         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 439         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 440         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 441         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 442
 443         /*
 444          * Initialize firmware.
 445          */
 446         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 447         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 448         if (rt2x00_is_usb(rt2x00dev))
 449                 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
 450         msleep(1);
 451
 452         return 0;
 453 }
 454 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
 455
 456 void rt2800_write_tx_data(struct queue_entry *entry,
 457                           struct txentry_desc *txdesc)
 458 {
 459         __le32 *txwi = rt2800_drv_get_txwi(entry);
 460         u32 word;
 461
 462         /*
 463          * Initialize TX Info descriptor
 464          */
 465         rt2x00_desc_read(txwi, 0, &word);
 466         rt2x00_set_field32(&word, TXWI_W0_FRAG,
 467                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 468         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
 469                            test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
 470         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
 471         rt2x00_set_field32(&word, TXWI_W0_TS,
 472                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
 473         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
 474                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
 475         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
 476                            txdesc->u.ht.mpdu_density);
 477         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
 478         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
 479         rt2x00_set_field32(&word, TXWI_W0_BW,
 480                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
 481         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
 482                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
 483         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
 484         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
 485         rt2x00_desc_write(txwi, 0, word);
 486
 487         rt2x00_desc_read(txwi, 1, &word);
 488         rt2x00_set_field32(&word, TXWI_W1_ACK,
 489                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
 490         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
 491                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
 492         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
 493         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
 494                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
 495                            txdesc->key_idx : txdesc->u.ht.wcid);
 496         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
 497                            txdesc->length);
 498         rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
 499         rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
 500         rt2x00_desc_write(txwi, 1, word);
 501
 502         /*
 503          * Always write 0 to IV/EIV fields, hardware will insert the IV
 504          * from the IVEIV register when TXD_W3_WIV is set to 0.
 505          * When TXD_W3_WIV is set to 1 it will use the IV data
 506          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
 507          * crypto entry in the registers should be used to encrypt the frame.
 508          */
 509         _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
 510         _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
 511 }
 512 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
 513
 514 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
 515 {
 516         s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
 517         s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
 518         s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
 519         u16 eeprom;
 520         u8 offset0;
 521         u8 offset1;
 522         u8 offset2;
 523
 524         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
 525                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
 526                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
 527                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
 528                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 529                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
 530         } else {
 531                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
 532                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
 533                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
 534                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 535                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
 536         }
 537
 538         /*
 539          * Convert the value from the descriptor into the RSSI value
 540          * If the value in the descriptor is 0, it is considered invalid
 541          * and the default (extremely low) rssi value is assumed
 542          */
 543         rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
 544         rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
 545         rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
 546
 547         /*
 548          * mac80211 only accepts a single RSSI value. Calculating the
 549          * average doesn't deliver a fair answer either since -60:-60 would
 550          * be considered equally good as -50:-70 while the second is the one
 551          * which gives less energy...
 552          */
 553         rssi0 = max(rssi0, rssi1);
 554         return (int)max(rssi0, rssi2);
 555 }
 556
 557 void rt2800_process_rxwi(struct queue_entry *entry,
 558                          struct rxdone_entry_desc *rxdesc)
 559 {
 560         __le32 *rxwi = (__le32 *) entry->skb->data;
 561         u32 word;
 562
 563         rt2x00_desc_read(rxwi, 0, &word);
 564
 565         rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
 566         rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
 567
 568         rt2x00_desc_read(rxwi, 1, &word);
 569
 570         if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
 571                 rxdesc->flags |= RX_FLAG_SHORT_GI;
 572
 573         if (rt2x00_get_field32(word, RXWI_W1_BW))
 574                 rxdesc->flags |= RX_FLAG_40MHZ;
 575
 576         /*
 577          * Detect RX rate, always use MCS as signal type.
 578          */
 579         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
 580         rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
 581         rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
 582
 583         /*
 584          * Mask of 0x8 bit to remove the short preamble flag.
 585          */
 586         if (rxdesc->rate_mode == RATE_MODE_CCK)
 587                 rxdesc->signal &= ~0x8;
 588
 589         rt2x00_desc_read(rxwi, 2, &word);
 590
 591         /*
 592          * Convert descriptor AGC value to RSSI value.
 593          */
 594         rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
 595
 596         /*
 597          * Remove RXWI descriptor from start of buffer.
 598          */
 599         skb_pull(entry->skb, RXWI_DESC_SIZE);
 600 }
 601 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
 602
 603 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
 604 {
 605         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 606         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 607         struct txdone_entry_desc txdesc;
 608         u32 word;
 609         u16 mcs, real_mcs;
 610         int aggr, ampdu;
 611
 612         /*
 613          * Obtain the status about this packet.
 614          */
 615         txdesc.flags = 0;
 616         rt2x00_desc_read(txwi, 0, &word);
 617
 618         mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
 619         ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
 620
 621         real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
 622         aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
 623
 624         /*
 625          * If a frame was meant to be sent as a single non-aggregated MPDU
 626          * but ended up in an aggregate the used tx rate doesn't correlate
 627          * with the one specified in the TXWI as the whole aggregate is sent
 628          * with the same rate.
 629          *
 630          * For example: two frames are sent to rt2x00, the first one sets
 631          * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
 632          * and requests MCS15. If the hw aggregates both frames into one
 633          * AMDPU the tx status for both frames will contain MCS7 although
 634          * the frame was sent successfully.
 635          *
 636          * Hence, replace the requested rate with the real tx rate to not
 637          * confuse the rate control algortihm by providing clearly wrong
 638          * data.
 639          */
 640         if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
 641                 skbdesc->tx_rate_idx = real_mcs;
 642                 mcs = real_mcs;
 643         }
 644
 645         if (aggr == 1 || ampdu == 1)
 646                 __set_bit(TXDONE_AMPDU, &txdesc.flags);
 647
 648         /*
 649          * Ralink has a retry mechanism using a global fallback
 650          * table. We setup this fallback table to try the immediate
 651          * lower rate for all rates. In the TX_STA_FIFO, the MCS field
 652          * always contains the MCS used for the last transmission, be
 653          * it successful or not.
 654          */
 655         if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
 656                 /*
 657                  * Transmission succeeded. The number of retries is
 658                  * mcs - real_mcs
 659                  */
 660                 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
 661                 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
 662         } else {
 663                 /*
 664                  * Transmission failed. The number of retries is
 665                  * always 7 in this case (for a total number of 8
 666                  * frames sent).
 667                  */
 668                 __set_bit(TXDONE_FAILURE, &txdesc.flags);
 669                 txdesc.retry = rt2x00dev->long_retry;
 670         }
 671
 672         /*
 673          * the frame was retried at least once
 674          * -> hw used fallback rates
 675          */
 676         if (txdesc.retry)
 677                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
 678
 679         rt2x00lib_txdone(entry, &txdesc);
 680 }
 681 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
 682
 683 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
 684 {
 685         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 686         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 687         unsigned int beacon_base;
 688         unsigned int padding_len;
 689         u32 orig_reg, reg;
 690
 691         /*
 692          * Disable beaconing while we are reloading the beacon data,
 693          * otherwise we might be sending out invalid data.
 694          */
 695         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 696         orig_reg = reg;
 697         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 698         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 699
 700         /*
 701          * Add space for the TXWI in front of the skb.
 702          */
 703         memset(skb_push(entry->skb, TXWI_DESC_SIZE), 0, TXWI_DESC_SIZE);
 704
 705         /*
 706          * Register descriptor details in skb frame descriptor.
 707          */
 708         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
 709         skbdesc->desc = entry->skb->data;
 710         skbdesc->desc_len = TXWI_DESC_SIZE;
 711
 712         /*
 713          * Add the TXWI for the beacon to the skb.
 714          */
 715         rt2800_write_tx_data(entry, txdesc);
 716
 717         /*
 718          * Dump beacon to userspace through debugfs.
 719          */
 720         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
 721
 722         /*
 723          * Write entire beacon with TXWI and padding to register.
 724          */
 725         padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
 726         if (padding_len && skb_pad(entry->skb, padding_len)) {
 727                 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
 728                 /* skb freed by skb_pad() on failure */
 729                 entry->skb = NULL;
 730                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
 731                 return;
 732         }
 733
 734         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
 735         rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
 736                                    entry->skb->len + padding_len);
 737
 738         /*
 739          * Enable beaconing again.
 740          */
 741         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 742         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 743
 744         /*
 745          * Clean up beacon skb.
 746          */
 747         dev_kfree_skb_any(entry->skb);
 748         entry->skb = NULL;
 749 }
 750 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
 751
 752 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
 753                                                 unsigned int beacon_base)
 754 {
 755         int i;
 756
 757         /*
 758          * For the Beacon base registers we only need to clear
 759          * the whole TXWI which (when set to 0) will invalidate
 760          * the entire beacon.
 761          */
 762         for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
 763                 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
 764 }
 765
 766 void rt2800_clear_beacon(struct queue_entry *entry)
 767 {
 768         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 769         u32 reg;
 770
 771         /*
 772          * Disable beaconing while we are reloading the beacon data,
 773          * otherwise we might be sending out invalid data.
 774          */
 775         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 776         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 777         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 778
 779         /*
 780          * Clear beacon.
 781          */
 782         rt2800_clear_beacon_register(rt2x00dev,
 783                                      HW_BEACON_OFFSET(entry->entry_idx));
 784
 785         /*
 786          * Enabled beaconing again.
 787          */
 788         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 789         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 790 }
 791 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
 792
 793 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 794 const struct rt2x00debug rt2800_rt2x00debug = {
 795         .owner  = THIS_MODULE,
 796         .csr    = {
 797                 .read           = rt2800_register_read,
 798                 .write          = rt2800_register_write,
 799                 .flags          = RT2X00DEBUGFS_OFFSET,
 800                 .word_base      = CSR_REG_BASE,
 801                 .word_size      = sizeof(u32),
 802                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 803         },
 804         .eeprom = {
 805                 .read           = rt2x00_eeprom_read,
 806                 .write          = rt2x00_eeprom_write,
 807                 .word_base      = EEPROM_BASE,
 808                 .word_size      = sizeof(u16),
 809                 .word_count     = EEPROM_SIZE / sizeof(u16),
 810         },
 811         .bbp    = {
 812                 .read           = rt2800_bbp_read,
 813                 .write          = rt2800_bbp_write,
 814                 .word_base      = BBP_BASE,
 815                 .word_size      = sizeof(u8),
 816                 .word_count     = BBP_SIZE / sizeof(u8),
 817         },
 818         .rf     = {
 819                 .read           = rt2x00_rf_read,
 820                 .write          = rt2800_rf_write,
 821                 .word_base      = RF_BASE,
 822                 .word_size      = sizeof(u32),
 823                 .word_count     = RF_SIZE / sizeof(u32),
 824         },
 825 };
 826 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
 827 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 828
 829 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 830 {
 831         u32 reg;
 832
 833         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 834         return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
 835 }
 836 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
 837
 838 #ifdef CONFIG_RT2X00_LIB_LEDS
 839 static void rt2800_brightness_set(struct led_classdev *led_cdev,
 840                                   enum led_brightness brightness)
 841 {
 842         struct rt2x00_led *led =
 843             container_of(led_cdev, struct rt2x00_led, led_dev);
 844         unsigned int enabled = brightness != LED_OFF;
 845         unsigned int bg_mode =
 846             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 847         unsigned int polarity =
 848                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 849                                    EEPROM_FREQ_LED_POLARITY);
 850         unsigned int ledmode =
 851                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 852                                    EEPROM_FREQ_LED_MODE);
 853         u32 reg;
 854
 855         /* Check for SoC (SOC devices don't support MCU requests) */
 856         if (rt2x00_is_soc(led->rt2x00dev)) {
 857                 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
 858
 859                 /* Set LED Polarity */
 860                 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
 861
 862                 /* Set LED Mode */
 863                 if (led->type == LED_TYPE_RADIO) {
 864                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
 865                                            enabled ? 3 : 0);
 866                 } else if (led->type == LED_TYPE_ASSOC) {
 867                         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
 868                                            enabled ? 3 : 0);
 869                 } else if (led->type == LED_TYPE_QUALITY) {
 870                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
 871                                            enabled ? 3 : 0);
 872                 }
 873
 874                 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
 875
 876         } else {
 877                 if (led->type == LED_TYPE_RADIO) {
 878                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 879                                               enabled ? 0x20 : 0);
 880                 } else if (led->type == LED_TYPE_ASSOC) {
 881                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 882                                               enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 883                 } else if (led->type == LED_TYPE_QUALITY) {
 884                         /*
 885                          * The brightness is divided into 6 levels (0 - 5),
 886                          * The specs tell us the following levels:
 887                          *      0, 1 ,3, 7, 15, 31
 888                          * to determine the level in a simple way we can simply
 889                          * work with bitshifting:
 890                          *      (1 << level) - 1
 891                          */
 892                         rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 893                                               (1 << brightness / (LED_FULL / 6)) - 1,
 894                                               polarity);
 895                 }
 896         }
 897 }
 898
 899 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
 900                      struct rt2x00_led *led, enum led_type type)
 901 {
 902         led->rt2x00dev = rt2x00dev;
 903         led->type = type;
 904         led->led_dev.brightness_set = rt2800_brightness_set;
 905         led->flags = LED_INITIALIZED;
 906 }
 907 #endif /* CONFIG_RT2X00_LIB_LEDS */
 908
 909 /*
 910  * Configuration handlers.
 911  */
 912 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
 913                                const u8 *address,
 914                                int wcid)
 915 {
 916         struct mac_wcid_entry wcid_entry;
 917         u32 offset;
 918
 919         offset = MAC_WCID_ENTRY(wcid);
 920
 921         memset(&wcid_entry, 0xff, sizeof(wcid_entry));
 922         if (address)
 923                 memcpy(wcid_entry.mac, address, ETH_ALEN);
 924
 925         rt2800_register_multiwrite(rt2x00dev, offset,
 926                                       &wcid_entry, sizeof(wcid_entry));
 927 }
 928
 929 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
 930 {
 931         u32 offset;
 932         offset = MAC_WCID_ATTR_ENTRY(wcid);
 933         rt2800_register_write(rt2x00dev, offset, 0);
 934 }
 935
 936 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
 937                                            int wcid, u32 bssidx)
 938 {
 939         u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
 940         u32 reg;
 941
 942         /*
 943          * The BSS Idx numbers is split in a main value of 3 bits,
 944          * and a extended field for adding one additional bit to the value.
 945          */
 946         rt2800_register_read(rt2x00dev, offset, &reg);
 947         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
 948         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
 949                            (bssidx & 0x8) >> 3);
 950         rt2800_register_write(rt2x00dev, offset, reg);
 951 }
 952
 953 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
 954                                            struct rt2x00lib_crypto *crypto,
 955                                            struct ieee80211_key_conf *key)
 956 {
 957         struct mac_iveiv_entry iveiv_entry;
 958         u32 offset;
 959         u32 reg;
 960
 961         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
 962
 963         if (crypto->cmd == SET_KEY) {
 964                 rt2800_register_read(rt2x00dev, offset, &reg);
 965                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
 966                                    !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
 967                 /*
 968                  * Both the cipher as the BSS Idx numbers are split in a main
 969                  * value of 3 bits, and a extended field for adding one additional
 970                  * bit to the value.
 971                  */
 972                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
 973                                    (crypto->cipher & 0x7));
 974                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
 975                                    (crypto->cipher & 0x8) >> 3);
 976                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
 977                 rt2800_register_write(rt2x00dev, offset, reg);
 978         } else {
 979                 /* Delete the cipher without touching the bssidx */
 980                 rt2800_register_read(rt2x00dev, offset, &reg);
 981                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
 982                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
 983                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
 984                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
 985                 rt2800_register_write(rt2x00dev, offset, reg);
 986         }
 987
 988         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
 989
 990         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
 991         if ((crypto->cipher == CIPHER_TKIP) ||
 992             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
 993             (crypto->cipher == CIPHER_AES))
 994                 iveiv_entry.iv[3] |= 0x20;
 995         iveiv_entry.iv[3] |= key->keyidx << 6;
 996         rt2800_register_multiwrite(rt2x00dev, offset,
 997                                       &iveiv_entry, sizeof(iveiv_entry));
 998 }
 999
1000 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1001                              struct rt2x00lib_crypto *crypto,
1002                              struct ieee80211_key_conf *key)
1003 {
1004         struct hw_key_entry key_entry;
1005         struct rt2x00_field32 field;
1006         u32 offset;
1007         u32 reg;
1008
1009         if (crypto->cmd == SET_KEY) {
1010                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1011
1012                 memcpy(key_entry.key, crypto->key,
1013                        sizeof(key_entry.key));
1014                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1015                        sizeof(key_entry.tx_mic));
1016                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1017                        sizeof(key_entry.rx_mic));
1018
1019                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1020                 rt2800_register_multiwrite(rt2x00dev, offset,
1021                                               &key_entry, sizeof(key_entry));
1022         }
1023
1024         /*
1025          * The cipher types are stored over multiple registers
1026          * starting with SHARED_KEY_MODE_BASE each word will have
1027          * 32 bits and contains the cipher types for 2 bssidx each.
1028          * Using the correct defines correctly will cause overhead,
1029          * so just calculate the correct offset.
1030          */
1031         field.bit_offset = 4 * (key->hw_key_idx % 8);
1032         field.bit_mask = 0x7 << field.bit_offset;
1033
1034         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1035
1036         rt2800_register_read(rt2x00dev, offset, &reg);
1037         rt2x00_set_field32(&reg, field,
1038                            (crypto->cmd == SET_KEY) * crypto->cipher);
1039         rt2800_register_write(rt2x00dev, offset, reg);
1040
1041         /*
1042          * Update WCID information
1043          */
1044         rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1045         rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1046                                        crypto->bssidx);
1047         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1048
1049         return 0;
1050 }
1051 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1052
1053 static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1054 {
1055         struct mac_wcid_entry wcid_entry;
1056         int idx;
1057         u32 offset;
1058
1059         /*
1060          * Search for the first free WCID entry and return the corresponding
1061          * index.
1062          *
1063          * Make sure the WCID starts _after_ the last possible shared key
1064          * entry (>32).
1065          *
1066          * Since parts of the pairwise key table might be shared with
1067          * the beacon frame buffers 6 & 7 we should only write into the
1068          * first 222 entries.
1069          */
1070         for (idx = 33; idx <= 222; idx++) {
1071                 offset = MAC_WCID_ENTRY(idx);
1072                 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1073                                           sizeof(wcid_entry));
1074                 if (is_broadcast_ether_addr(wcid_entry.mac))
1075                         return idx;
1076         }
1077
1078         /*
1079          * Use -1 to indicate that we don't have any more space in the WCID
1080          * table.
1081          */
1082         return -1;
1083 }
1084
1085 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1086                                struct rt2x00lib_crypto *crypto,
1087                                struct ieee80211_key_conf *key)
1088 {
1089         struct hw_key_entry key_entry;
1090         u32 offset;
1091
1092         if (crypto->cmd == SET_KEY) {
1093                 /*
1094                  * Allow key configuration only for STAs that are
1095                  * known by the hw.
1096                  */
1097                 if (crypto->wcid < 0)
1098                         return -ENOSPC;
1099                 key->hw_key_idx = crypto->wcid;
1100
1101                 memcpy(key_entry.key, crypto->key,
1102                        sizeof(key_entry.key));
1103                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1104                        sizeof(key_entry.tx_mic));
1105                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1106                        sizeof(key_entry.rx_mic));
1107
1108                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1109                 rt2800_register_multiwrite(rt2x00dev, offset,
1110                                               &key_entry, sizeof(key_entry));
1111         }
1112
1113         /*
1114          * Update WCID information
1115          */
1116         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1117
1118         return 0;
1119 }
1120 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1121
1122 int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1123                    struct ieee80211_sta *sta)
1124 {
1125         int wcid;
1126         struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1127
1128         /*
1129          * Find next free WCID.
1130          */
1131         wcid = rt2800_find_wcid(rt2x00dev);
1132
1133         /*
1134          * Store selected wcid even if it is invalid so that we can
1135          * later decide if the STA is uploaded into the hw.
1136          */
1137         sta_priv->wcid = wcid;
1138
1139         /*
1140          * No space left in the device, however, we can still communicate
1141          * with the STA -> No error.
1142          */
1143         if (wcid < 0)
1144                 return 0;
1145
1146         /*
1147          * Clean up WCID attributes and write STA address to the device.
1148          */
1149         rt2800_delete_wcid_attr(rt2x00dev, wcid);
1150         rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1151         rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1152                                        rt2x00lib_get_bssidx(rt2x00dev, vif));
1153         return 0;
1154 }
1155 EXPORT_SYMBOL_GPL(rt2800_sta_add);
1156
1157 int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1158 {
1159         /*
1160          * Remove WCID entry, no need to clean the attributes as they will
1161          * get renewed when the WCID is reused.
1162          */
1163         rt2800_config_wcid(rt2x00dev, NULL, wcid);
1164
1165         return 0;
1166 }
1167 EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1168
1169 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1170                           const unsigned int filter_flags)
1171 {
1172         u32 reg;
1173
1174         /*
1175          * Start configuration steps.
1176          * Note that the version error will always be dropped
1177          * and broadcast frames will always be accepted since
1178          * there is no filter for it at this time.
1179          */
1180         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1181         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1182                            !(filter_flags & FIF_FCSFAIL));
1183         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1184                            !(filter_flags & FIF_PLCPFAIL));
1185         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1186                            !(filter_flags & FIF_PROMISC_IN_BSS));
1187         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1188         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1189         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1190                            !(filter_flags & FIF_ALLMULTI));
1191         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1192         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1193         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1194                            !(filter_flags & FIF_CONTROL));
1195         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1196                            !(filter_flags & FIF_CONTROL));
1197         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1198                            !(filter_flags & FIF_CONTROL));
1199         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1200                            !(filter_flags & FIF_CONTROL));
1201         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1202                            !(filter_flags & FIF_CONTROL));
1203         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1204                            !(filter_flags & FIF_PSPOLL));
1205         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA,
1206                            !(filter_flags & FIF_CONTROL));
1207         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1208                            !(filter_flags & FIF_CONTROL));
1209         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1210                            !(filter_flags & FIF_CONTROL));
1211         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1212 }
1213 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1214
1215 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1216                         struct rt2x00intf_conf *conf, const unsigned int flags)
1217 {
1218         u32 reg;
1219         bool update_bssid = false;
1220
1221         if (flags & CONFIG_UPDATE_TYPE) {
1222                 /*
1223                  * Enable synchronisation.
1224                  */
1225                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1226                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1227                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1228
1229                 if (conf->sync == TSF_SYNC_AP_NONE) {
1230                         /*
1231                          * Tune beacon queue transmit parameters for AP mode
1232                          */
1233                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1234                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1235                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1236                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1237                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1238                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1239                 } else {
1240                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1241                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1242                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1243                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1244                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1245                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1246                 }
1247         }
1248
1249         if (flags & CONFIG_UPDATE_MAC) {
1250                 if (flags & CONFIG_UPDATE_TYPE &&
1251                     conf->sync == TSF_SYNC_AP_NONE) {
1252                         /*
1253                          * The BSSID register has to be set to our own mac
1254                          * address in AP mode.
1255                          */
1256                         memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1257                         update_bssid = true;
1258                 }
1259
1260                 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1261                         reg = le32_to_cpu(conf->mac[1]);
1262                         rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1263                         conf->mac[1] = cpu_to_le32(reg);
1264                 }
1265
1266                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1267                                               conf->mac, sizeof(conf->mac));
1268         }
1269
1270         if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1271                 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1272                         reg = le32_to_cpu(conf->bssid[1]);
1273                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1274                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1275                         conf->bssid[1] = cpu_to_le32(reg);
1276                 }
1277
1278                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1279                                               conf->bssid, sizeof(conf->bssid));
1280         }
1281 }
1282 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1283
1284 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1285                                     struct rt2x00lib_erp *erp)
1286 {
1287         bool any_sta_nongf = !!(erp->ht_opmode &
1288                                 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1289         u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1290         u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1291         u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1292         u32 reg;
1293
1294         /* default protection rate for HT20: OFDM 24M */
1295         mm20_rate = gf20_rate = 0x4004;
1296
1297         /* default protection rate for HT40: duplicate OFDM 24M */
1298         mm40_rate = gf40_rate = 0x4084;
1299
1300         switch (protection) {
1301         case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1302                 /*
1303                  * All STAs in this BSS are HT20/40 but there might be
1304                  * STAs not supporting greenfield mode.
1305                  * => Disable protection for HT transmissions.
1306                  */
1307                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1308
1309                 break;
1310         case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1311                 /*
1312                  * All STAs in this BSS are HT20 or HT20/40 but there
1313                  * might be STAs not supporting greenfield mode.
1314                  * => Protect all HT40 transmissions.
1315                  */
1316                 mm20_mode = gf20_mode = 0;
1317                 mm40_mode = gf40_mode = 2;
1318
1319                 break;
1320         case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1321                 /*
1322                  * Nonmember protection:
1323                  * According to 802.11n we _should_ protect all
1324                  * HT transmissions (but we don't have to).
1325                  *
1326                  * But if cts_protection is enabled we _shall_ protect
1327                  * all HT transmissions using a CCK rate.
1328                  *
1329                  * And if any station is non GF we _shall_ protect
1330                  * GF transmissions.
1331                  *
1332                  * We decide to protect everything
1333                  * -> fall through to mixed mode.
1334                  */
1335         case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1336                 /*
1337                  * Legacy STAs are present
1338                  * => Protect all HT transmissions.
1339                  */
1340                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1341
1342                 /*
1343                  * If erp protection is needed we have to protect HT
1344                  * transmissions with CCK 11M long preamble.
1345                  */
1346                 if (erp->cts_protection) {
1347                         /* don't duplicate RTS/CTS in CCK mode */
1348                         mm20_rate = mm40_rate = 0x0003;
1349                         gf20_rate = gf40_rate = 0x0003;
1350                 }
1351                 break;
1352         }
1353
1354         /* check for STAs not supporting greenfield mode */
1355         if (any_sta_nongf)
1356                 gf20_mode = gf40_mode = 2;
1357
1358         /* Update HT protection config */
1359         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1360         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1361         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1362         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1363
1364         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1365         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1366         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1367         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1368
1369         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1370         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1371         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1372         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1373
1374         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1375         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1376         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1377         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1378 }
1379
1380 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1381                        u32 changed)
1382 {
1383         u32 reg;
1384
1385         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1386                 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1387                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1388                                    !!erp->short_preamble);
1389                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1390                                    !!erp->short_preamble);
1391                 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1392         }
1393
1394         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1395                 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1396                 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1397                                    erp->cts_protection ? 2 : 0);
1398                 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1399         }
1400
1401         if (changed & BSS_CHANGED_BASIC_RATES) {
1402                 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1403                                          erp->basic_rates);
1404                 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1405         }
1406
1407         if (changed & BSS_CHANGED_ERP_SLOT) {
1408                 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1409                 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1410                                    erp->slot_time);
1411                 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1412
1413                 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1414                 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1415                 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1416         }
1417
1418         if (changed & BSS_CHANGED_BEACON_INT) {
1419                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1420                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1421                                    erp->beacon_int * 16);
1422                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1423         }
1424
1425         if (changed & BSS_CHANGED_HT)
1426                 rt2800_config_ht_opmode(rt2x00dev, erp);
1427 }
1428 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1429
1430 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1431 {
1432         u32 reg;
1433         u16 eeprom;
1434         u8 led_ctrl, led_g_mode, led_r_mode;
1435
1436         rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1437         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1438                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1439                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1440         } else {
1441                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1442                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1443         }
1444         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1445
1446         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1447         led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1448         led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1449         if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1450             led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1451                 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1452                 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1453                 if (led_ctrl == 0 || led_ctrl > 0x40) {
1454                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1455                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1456                         rt2800_register_write(rt2x00dev, LED_CFG, reg);
1457                 } else {
1458                         rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1459                                            (led_g_mode << 2) | led_r_mode, 1);
1460                 }
1461         }
1462 }
1463
1464 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1465                                      enum antenna ant)
1466 {
1467         u32 reg;
1468         u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1469         u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1470
1471         if (rt2x00_is_pci(rt2x00dev)) {
1472                 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1473                 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1474                 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1475         } else if (rt2x00_is_usb(rt2x00dev))
1476                 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1477                                    eesk_pin, 0);
1478
1479         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
1480         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
1481         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, gpio_bit3);
1482         rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1483 }
1484
1485 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1486 {
1487         u8 r1;
1488         u8 r3;
1489         u16 eeprom;
1490
1491         rt2800_bbp_read(rt2x00dev, 1, &r1);
1492         rt2800_bbp_read(rt2x00dev, 3, &r3);
1493
1494         if (rt2x00_rt(rt2x00dev, RT3572) &&
1495             test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1496                 rt2800_config_3572bt_ant(rt2x00dev);
1497
1498         /*
1499          * Configure the TX antenna.
1500          */
1501         switch (ant->tx_chain_num) {
1502         case 1:
1503                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1504                 break;
1505         case 2:
1506                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1507                     test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1508                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1509                 else
1510                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1511                 break;
1512         case 3:
1513                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1514                 break;
1515         }
1516
1517         /*
1518          * Configure the RX antenna.
1519          */
1520         switch (ant->rx_chain_num) {
1521         case 1:
1522                 if (rt2x00_rt(rt2x00dev, RT3070) ||
1523                     rt2x00_rt(rt2x00dev, RT3090) ||
1524                     rt2x00_rt(rt2x00dev, RT3390)) {
1525                         rt2x00_eeprom_read(rt2x00dev,
1526                                            EEPROM_NIC_CONF1, &eeprom);
1527                         if (rt2x00_get_field16(eeprom,
1528                                                 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1529                                 rt2800_set_ant_diversity(rt2x00dev,
1530                                                 rt2x00dev->default_ant.rx);
1531                 }
1532                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1533                 break;
1534         case 2:
1535                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1536                     test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1537                         rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1538                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1539                                 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1540                         rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1541                 } else {
1542                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1543                 }
1544                 break;
1545         case 3:
1546                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1547                 break;
1548         }
1549
1550         rt2800_bbp_write(rt2x00dev, 3, r3);
1551         rt2800_bbp_write(rt2x00dev, 1, r1);
1552 }
1553 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1554
1555 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1556                                    struct rt2x00lib_conf *libconf)
1557 {
1558         u16 eeprom;
1559         short lna_gain;
1560
1561         if (libconf->rf.channel <= 14) {
1562                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1563                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1564         } else if (libconf->rf.channel <= 64) {
1565                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1566                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1567         } else if (libconf->rf.channel <= 128) {
1568                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1569                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1570         } else {
1571                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1572                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1573         }
1574
1575         rt2x00dev->lna_gain = lna_gain;
1576 }
1577
1578 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1579                                          struct ieee80211_conf *conf,
1580                                          struct rf_channel *rf,
1581                                          struct channel_info *info)
1582 {
1583         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1584
1585         if (rt2x00dev->default_ant.tx_chain_num == 1)
1586                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1587
1588         if (rt2x00dev->default_ant.rx_chain_num == 1) {
1589                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1590                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1591         } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1592                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1593
1594         if (rf->channel > 14) {
1595                 /*
1596                  * When TX power is below 0, we should increase it by 7 to
1597                  * make it a positive value (Minimum value is -7).
1598                  * However this means that values between 0 and 7 have
1599                  * double meaning, and we should set a 7DBm boost flag.
1600                  */
1601                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1602                                    (info->default_power1 >= 0));
1603
1604                 if (info->default_power1 < 0)
1605                         info->default_power1 += 7;
1606
1607                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1608
1609                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1610                                    (info->default_power2 >= 0));
1611
1612                 if (info->default_power2 < 0)
1613                         info->default_power2 += 7;
1614
1615                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1616         } else {
1617                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1618                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1619         }
1620
1621         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1622
1623         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1624         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1625         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1626         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1627
1628         udelay(200);
1629
1630         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1631         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1632         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1633         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1634
1635         udelay(200);
1636
1637         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1638         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1639         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1640         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1641 }
1642
1643 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1644                                          struct ieee80211_conf *conf,
1645                                          struct rf_channel *rf,
1646                                          struct channel_info *info)
1647 {
1648         u8 rfcsr;
1649
1650         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1651         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1652
1653         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1654         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1655         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1656
1657         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1658         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
1659         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1660
1661         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1662         rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
1663         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1664
1665         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1666         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1667         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1668
1669         rt2800_rfcsr_write(rt2x00dev, 24,
1670                               rt2x00dev->calibration[conf_is_ht40(conf)]);
1671
1672         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1673         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1674         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1675 }
1676
1677 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
1678                                          struct ieee80211_conf *conf,
1679                                          struct rf_channel *rf,
1680                                          struct channel_info *info)
1681 {
1682         u8 rfcsr;
1683         u32 reg;
1684
1685         if (rf->channel <= 14) {
1686                 rt2800_bbp_write(rt2x00dev, 25, 0x15);
1687                 rt2800_bbp_write(rt2x00dev, 26, 0x85);
1688         } else {
1689                 rt2800_bbp_write(rt2x00dev, 25, 0x09);
1690                 rt2800_bbp_write(rt2x00dev, 26, 0xff);
1691         }
1692
1693         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1694         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1695
1696         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1697         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1698         if (rf->channel <= 14)
1699                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
1700         else
1701                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
1702         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1703
1704         rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
1705         if (rf->channel <= 14)
1706                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
1707         else
1708                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
1709         rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
1710
1711         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1712         if (rf->channel <= 14) {
1713                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
1714                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1715                                 (info->default_power1 & 0x3) |
1716                                 ((info->default_power1 & 0xC) << 1));
1717         } else {
1718                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
1719                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1720                                 (info->default_power1 & 0x3) |
1721                                 ((info->default_power1 & 0xC) << 1));
1722         }
1723         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1724
1725         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1726         if (rf->channel <= 14) {
1727                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
1728                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1729                                 (info->default_power2 & 0x3) |
1730                                 ((info->default_power2 & 0xC) << 1));
1731         } else {
1732                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
1733                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1734                                 (info->default_power2 & 0x3) |
1735                                 ((info->default_power2 & 0xC) << 1));
1736         }
1737         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1738
1739         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1740         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1741         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1742         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1743         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1744         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
1745         if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1746                 if (rf->channel <= 14) {
1747                         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1748                         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1749                 }
1750                 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1751                 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1752         } else {
1753                 switch (rt2x00dev->default_ant.tx_chain_num) {
1754                 case 1:
1755                         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1756                 case 2:
1757                         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1758                         break;
1759                 }
1760
1761                 switch (rt2x00dev->default_ant.rx_chain_num) {
1762                 case 1:
1763                         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1764                 case 2:
1765                         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1766                         break;
1767                 }
1768         }
1769         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1770
1771         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1772         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1773         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1774
1775         rt2800_rfcsr_write(rt2x00dev, 24,
1776                               rt2x00dev->calibration[conf_is_ht40(conf)]);
1777         rt2800_rfcsr_write(rt2x00dev, 31,
1778                               rt2x00dev->calibration[conf_is_ht40(conf)]);
1779
1780         if (rf->channel <= 14) {
1781                 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
1782                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
1783                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1784                 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
1785                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
1786                 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
1787                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1788                 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
1789                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
1790                 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
1791                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1792                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1793                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
1794         } else {
1795                 rt2800_rfcsr_write(rt2x00dev, 7, 0x14);
1796                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1797                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1798                 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
1799                 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
1800                 rt2800_rfcsr_write(rt2x00dev, 16, 0x7a);
1801                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1802                 if (rf->channel <= 64) {
1803                         rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
1804                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
1805                         rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1806                 } else if (rf->channel <= 128) {
1807                         rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
1808                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
1809                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1810                 } else {
1811                         rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
1812                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
1813                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1814                 }
1815                 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
1816                 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
1817                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
1818         }
1819
1820         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
1821         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT7, 0);
1822         if (rf->channel <= 14)
1823                 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT7, 1);
1824         else
1825                 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT7, 0);
1826         rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1827
1828         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1829         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1830         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1831 }
1832
1833 #define RT5390_POWER_BOUND     0x27
1834 #define RT5390_FREQ_OFFSET_BOUND       0x5f
1835
1836 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
1837                                          struct ieee80211_conf *conf,
1838                                          struct rf_channel *rf,
1839                                          struct channel_info *info)
1840 {
1841         u8 rfcsr;
1842
1843         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
1844         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
1845         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
1846         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
1847         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
1848
1849         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
1850         if (info->default_power1 > RT5390_POWER_BOUND)
1851                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, RT5390_POWER_BOUND);
1852         else
1853                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
1854         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
1855
1856         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1857         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1858         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
1859         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1860         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1861         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1862
1863         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1864         if (rt2x00dev->freq_offset > RT5390_FREQ_OFFSET_BOUND)
1865                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE,
1866                                   RT5390_FREQ_OFFSET_BOUND);
1867         else
1868                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
1869         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1870
1871         if (rf->channel <= 14) {
1872                 int idx = rf->channel-1;
1873
1874                 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1875                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1876                                 /* r55/r59 value array of channel 1~14 */
1877                                 static const char r55_bt_rev[] = {0x83, 0x83,
1878                                         0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
1879                                         0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
1880                                 static const char r59_bt_rev[] = {0x0e, 0x0e,
1881                                         0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
1882                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
1883
1884                                 rt2800_rfcsr_write(rt2x00dev, 55,
1885                                                    r55_bt_rev[idx]);
1886                                 rt2800_rfcsr_write(rt2x00dev, 59,
1887                                                    r59_bt_rev[idx]);
1888                         } else {
1889                                 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
1890                                         0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
1891                                         0x88, 0x88, 0x86, 0x85, 0x84};
1892
1893                                 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
1894                         }
1895                 } else {
1896                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1897                                 static const char r55_nonbt_rev[] = {0x23, 0x23,
1898                                         0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
1899                                         0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
1900                                 static const char r59_nonbt_rev[] = {0x07, 0x07,
1901                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
1902                                         0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
1903
1904                                 rt2800_rfcsr_write(rt2x00dev, 55,
1905                                                    r55_nonbt_rev[idx]);
1906                                 rt2800_rfcsr_write(rt2x00dev, 59,
1907                                                    r59_nonbt_rev[idx]);
1908                         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
1909                                 static const char r59_non_bt[] = {0x8f, 0x8f,
1910                                         0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
1911                                         0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
1912
1913                                 rt2800_rfcsr_write(rt2x00dev, 59,
1914                                                    r59_non_bt[idx]);
1915                         }
1916                 }
1917         }
1918
1919         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1920         rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
1921         rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
1922         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1923
1924         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1925         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1926         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
1927 }
1928
1929 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1930                                   struct ieee80211_conf *conf,
1931                                   struct rf_channel *rf,
1932                                   struct channel_info *info)
1933 {
1934         u32 reg;
1935         unsigned int tx_pin;
1936         u8 bbp;
1937
1938         if (rf->channel <= 14) {
1939                 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
1940                 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
1941         } else {
1942                 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
1943                 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
1944         }
1945
1946         switch (rt2x00dev->chip.rf) {
1947         case RF2020:
1948         case RF3020:
1949         case RF3021:
1950         case RF3022:
1951         case RF3320:
1952                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
1953                 break;
1954         case RF3052:
1955                 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
1956                 break;
1957         case RF5370:
1958         case RF5390:
1959                 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
1960                 break;
1961         default:
1962                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
1963         }
1964
1965         /*
1966          * Change BBP settings
1967          */
1968         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1969         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1970         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1971         rt2800_bbp_write(rt2x00dev, 86, 0);
1972
1973         if (rf->channel <= 14) {
1974                 if (!rt2x00_rt(rt2x00dev, RT5390)) {
1975                         if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
1976                                      &rt2x00dev->cap_flags)) {
1977                                 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1978                                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1979                         } else {
1980                                 rt2800_bbp_write(rt2x00dev, 82, 0x84);
1981                                 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1982                         }
1983                 }
1984         } else {
1985                 if (rt2x00_rt(rt2x00dev, RT3572))
1986                         rt2800_bbp_write(rt2x00dev, 82, 0x94);
1987                 else
1988                         rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1989
1990                 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
1991                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
1992                 else
1993                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
1994         }
1995
1996         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
1997         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
1998         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
1999         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
2000         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
2001
2002         if (rt2x00_rt(rt2x00dev, RT3572))
2003                 rt2800_rfcsr_write(rt2x00dev, 8, 0);
2004
2005         tx_pin = 0;
2006
2007         /* Turn on unused PA or LNA when not using 1T or 1R */
2008         if (rt2x00dev->default_ant.tx_chain_num == 2) {
2009                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
2010                                    rf->channel > 14);
2011                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
2012                                    rf->channel <= 14);
2013         }
2014
2015         /* Turn on unused PA or LNA when not using 1T or 1R */
2016         if (rt2x00dev->default_ant.rx_chain_num == 2) {
2017                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
2018                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
2019         }
2020
2021         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
2022         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
2023         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
2024         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
2025         if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
2026                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2027         else
2028                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
2029                                    rf->channel <= 14);
2030         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
2031
2032         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2033
2034         if (rt2x00_rt(rt2x00dev, RT3572))
2035                 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
2036
2037         rt2800_bbp_read(rt2x00dev, 4, &bbp);
2038         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
2039         rt2800_bbp_write(rt2x00dev, 4, bbp);
2040
2041         rt2800_bbp_read(rt2x00dev, 3, &bbp);
2042         rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
2043         rt2800_bbp_write(rt2x00dev, 3, bbp);
2044
2045         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2046                 if (conf_is_ht40(conf)) {
2047                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
2048                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2049                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
2050                 } else {
2051                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
2052                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
2053                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
2054                 }
2055         }
2056
2057         msleep(1);
2058
2059         /*
2060          * Clear channel statistic counters
2061          */
2062         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
2063         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
2064         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
2065 }
2066
2067 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
2068 {
2069         u8 tssi_bounds[9];
2070         u8 current_tssi;
2071         u16 eeprom;
2072         u8 step;
2073         int i;
2074
2075         /*
2076          * Read TSSI boundaries for temperature compensation from
2077          * the EEPROM.
2078          *
2079          * Array idx               0    1    2    3    4    5    6    7    8
2080          * Matching Delta value   -4   -3   -2   -1    0   +1   +2   +3   +4
2081          * Example TSSI bounds  0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
2082          */
2083         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2084                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
2085                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2086                                         EEPROM_TSSI_BOUND_BG1_MINUS4);
2087                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2088                                         EEPROM_TSSI_BOUND_BG1_MINUS3);
2089
2090                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
2091                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2092                                         EEPROM_TSSI_BOUND_BG2_MINUS2);
2093                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2094                                         EEPROM_TSSI_BOUND_BG2_MINUS1);
2095
2096                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
2097                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2098                                         EEPROM_TSSI_BOUND_BG3_REF);
2099                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2100                                         EEPROM_TSSI_BOUND_BG3_PLUS1);
2101
2102                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
2103                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2104                                         EEPROM_TSSI_BOUND_BG4_PLUS2);
2105                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2106                                         EEPROM_TSSI_BOUND_BG4_PLUS3);
2107
2108                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
2109                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2110                                         EEPROM_TSSI_BOUND_BG5_PLUS4);
2111
2112                 step = rt2x00_get_field16(eeprom,
2113                                           EEPROM_TSSI_BOUND_BG5_AGC_STEP);
2114         } else {
2115                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
2116                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2117                                         EEPROM_TSSI_BOUND_A1_MINUS4);
2118                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2119                                         EEPROM_TSSI_BOUND_A1_MINUS3);
2120
2121                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
2122                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2123                                         EEPROM_TSSI_BOUND_A2_MINUS2);
2124                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2125                                         EEPROM_TSSI_BOUND_A2_MINUS1);
2126
2127                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
2128                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2129                                         EEPROM_TSSI_BOUND_A3_REF);
2130                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2131                                         EEPROM_TSSI_BOUND_A3_PLUS1);
2132
2133                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
2134                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2135                                         EEPROM_TSSI_BOUND_A4_PLUS2);
2136                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2137                                         EEPROM_TSSI_BOUND_A4_PLUS3);
2138
2139                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
2140                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2141                                         EEPROM_TSSI_BOUND_A5_PLUS4);
2142
2143                 step = rt2x00_get_field16(eeprom,
2144                                           EEPROM_TSSI_BOUND_A5_AGC_STEP);
2145         }
2146
2147         /*
2148          * Check if temperature compensation is supported.
2149          */
2150         if (tssi_bounds[4] == 0xff)
2151                 return 0;
2152
2153         /*
2154          * Read current TSSI (BBP 49).
2155          */
2156         rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
2157
2158         /*
2159          * Compare TSSI value (BBP49) with the compensation boundaries
2160          * from the EEPROM and increase or decrease tx power.
2161          */
2162         for (i = 0; i <= 3; i++) {
2163                 if (current_tssi > tssi_bounds[i])
2164                         break;
2165         }
2166
2167         if (i == 4) {
2168                 for (i = 8; i >= 5; i--) {
2169                         if (current_tssi < tssi_bounds[i])
2170                                 break;
2171                 }
2172         }
2173
2174         return (i - 4) * step;
2175 }
2176
2177 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
2178                                       enum ieee80211_band band)
2179 {
2180         u16 eeprom;
2181         u8 comp_en;
2182         u8 comp_type;
2183         int comp_value = 0;
2184
2185         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
2186
2187         /*
2188          * HT40 compensation not required.
2189          */
2190         if (eeprom == 0xffff ||
2191             !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2192                 return 0;
2193
2194         if (band == IEEE80211_BAND_2GHZ) {
2195                 comp_en = rt2x00_get_field16(eeprom,
2196                                  EEPROM_TXPOWER_DELTA_ENABLE_2G);
2197                 if (comp_en) {
2198                         comp_type = rt2x00_get_field16(eeprom,
2199                                            EEPROM_TXPOWER_DELTA_TYPE_2G);
2200                         comp_value = rt2x00_get_field16(eeprom,
2201                                             EEPROM_TXPOWER_DELTA_VALUE_2G);
2202                         if (!comp_type)
2203                                 comp_value = -comp_value;
2204                 }
2205         } else {
2206                 comp_en = rt2x00_get_field16(eeprom,
2207                                  EEPROM_TXPOWER_DELTA_ENABLE_5G);
2208                 if (comp_en) {
2209                         comp_type = rt2x00_get_field16(eeprom,
2210                                            EEPROM_TXPOWER_DELTA_TYPE_5G);
2211                         comp_value = rt2x00_get_field16(eeprom,
2212                                             EEPROM_TXPOWER_DELTA_VALUE_5G);
2213                         if (!comp_type)
2214                                 comp_value = -comp_value;
2215                 }
2216         }
2217
2218         return comp_value;
2219 }
2220
2221 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
2222                                    enum ieee80211_band band, int power_level,
2223                                    u8 txpower, int delta)
2224 {
2225         u32 reg;
2226         u16 eeprom;
2227         u8 criterion;
2228         u8 eirp_txpower;
2229         u8 eirp_txpower_criterion;
2230         u8 reg_limit;
2231
2232         if (!((band == IEEE80211_BAND_5GHZ) && is_rate_b))
2233                 return txpower;
2234
2235         if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
2236                 /*
2237                  * Check if eirp txpower exceed txpower_limit.
2238                  * We use OFDM 6M as criterion and its eirp txpower
2239                  * is stored at EEPROM_EIRP_MAX_TX_POWER.
2240                  * .11b data rate need add additional 4dbm
2241                  * when calculating eirp txpower.
2242                  */
2243                 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
2244                 criterion = rt2x00_get_field32(reg, TX_PWR_CFG_0_6MBS);
2245
2246                 rt2x00_eeprom_read(rt2x00dev,
2247                                    EEPROM_EIRP_MAX_TX_POWER, &eeprom);
2248
2249                 if (band == IEEE80211_BAND_2GHZ)
2250                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2251                                                  EEPROM_EIRP_MAX_TX_POWER_2GHZ);
2252                 else
2253                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2254                                                  EEPROM_EIRP_MAX_TX_POWER_5GHZ);
2255
2256                 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2257                                (is_rate_b ? 4 : 0) + delta;
2258
2259                 reg_limit = (eirp_txpower > power_level) ?
2260                                         (eirp_txpower - power_level) : 0;
2261         } else
2262                 reg_limit = 0;
2263
2264         return txpower + delta - reg_limit;
2265 }
2266
2267 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
2268                                   enum ieee80211_band band,
2269                                   int power_level)
2270 {
2271         u8 txpower;
2272         u16 eeprom;
2273         int i, is_rate_b;
2274         u32 reg;
2275         u8 r1;
2276         u32 offset;
2277         int delta;
2278
2279         /*
2280          * Calculate HT40 compensation delta
2281          */
2282         delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
2283
2284         /*
2285          * calculate temperature compensation delta
2286          */
2287         delta += rt2800_get_gain_calibration_delta(rt2x00dev);
2288
2289         /*
2290          * set to normal bbp tx power control mode: +/- 0dBm
2291          */
2292         rt2800_bbp_read(rt2x00dev, 1, &r1);
2293         rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, 0);
2294         rt2800_bbp_write(rt2x00dev, 1, r1);
2295         offset = TX_PWR_CFG_0;
2296
2297         for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
2298                 /* just to be safe */
2299                 if (offset > TX_PWR_CFG_4)
2300                         break;
2301
2302                 rt2800_register_read(rt2x00dev, offset, &reg);
2303
2304                 /* read the next four txpower values */
2305                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
2306                                    &eeprom);
2307
2308                 is_rate_b = i ? 0 : 1;
2309                 /*
2310                  * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
2311                  * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
2312                  * TX_PWR_CFG_4: unknown
2313                  */
2314                 txpower = rt2x00_get_field16(eeprom,
2315                                              EEPROM_TXPOWER_BYRATE_RATE0);
2316                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2317                                              power_level, txpower, delta);
2318                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
2319
2320                 /*
2321                  * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
2322                  * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
2323                  * TX_PWR_CFG_4: unknown
2324                  */
2325                 txpower = rt2x00_get_field16(eeprom,
2326                                              EEPROM_TXPOWER_BYRATE_RATE1);
2327                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2328                                              power_level, txpower, delta);
2329                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
2330
2331                 /*
2332                  * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
2333                  * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
2334                  * TX_PWR_CFG_4: unknown
2335                  */
2336                 txpower = rt2x00_get_field16(eeprom,
2337                                              EEPROM_TXPOWER_BYRATE_RATE2);
2338                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2339                                              power_level, txpower, delta);
2340                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
2341
2342                 /*
2343                  * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
2344                  * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
2345                  * TX_PWR_CFG_4: unknown
2346                  */
2347                 txpower = rt2x00_get_field16(eeprom,
2348                                              EEPROM_TXPOWER_BYRATE_RATE3);
2349                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2350                                              power_level, txpower, delta);
2351                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
2352
2353                 /* read the next four txpower values */
2354                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
2355                                    &eeprom);
2356
2357                 is_rate_b = 0;
2358                 /*
2359                  * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
2360                  * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
2361                  * TX_PWR_CFG_4: unknown
2362                  */
2363                 txpower = rt2x00_get_field16(eeprom,
2364                                              EEPROM_TXPOWER_BYRATE_RATE0);
2365                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2366                                              power_level, txpower, delta);
2367                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
2368
2369                 /*
2370                  * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
2371                  * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
2372                  * TX_PWR_CFG_4: unknown
2373                  */
2374                 txpower = rt2x00_get_field16(eeprom,
2375                                              EEPROM_TXPOWER_BYRATE_RATE1);
2376                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2377                                              power_level, txpower, delta);
2378                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
2379
2380                 /*
2381                  * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
2382                  * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
2383                  * TX_PWR_CFG_4: unknown
2384                  */
2385                 txpower = rt2x00_get_field16(eeprom,
2386                                              EEPROM_TXPOWER_BYRATE_RATE2);
2387                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2388                                              power_level, txpower, delta);
2389                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
2390
2391                 /*
2392                  * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
2393                  * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
2394                  * TX_PWR_CFG_4: unknown
2395                  */
2396                 txpower = rt2x00_get_field16(eeprom,
2397                                              EEPROM_TXPOWER_BYRATE_RATE3);
2398                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2399                                              power_level, txpower, delta);
2400                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
2401
2402                 rt2800_register_write(rt2x00dev, offset, reg);
2403
2404                 /* next TX_PWR_CFG register */
2405                 offset += 4;
2406         }
2407 }
2408
2409 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
2410 {
2411         rt2800_config_txpower(rt2x00dev, rt2x00dev->curr_band,
2412                               rt2x00dev->tx_power);
2413 }
2414 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
2415
2416 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
2417                                       struct rt2x00lib_conf *libconf)
2418 {
2419         u32 reg;
2420
2421         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2422         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
2423                            libconf->conf->short_frame_max_tx_count);
2424         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
2425                            libconf->conf->long_frame_max_tx_count);
2426         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2427 }
2428
2429 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
2430                              struct rt2x00lib_conf *libconf)
2431 {
2432         enum dev_state state =
2433             (libconf->conf->flags & IEEE80211_CONF_PS) ?
2434                 STATE_SLEEP : STATE_AWAKE;
2435         u32 reg;
2436
2437         if (state == STATE_SLEEP) {
2438                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
2439
2440                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2441                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
2442                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
2443                                    libconf->conf->listen_interval - 1);
2444                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
2445                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2446
2447                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2448         } else {
2449                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2450                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
2451                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
2452                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
2453                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2454
2455                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2456         }
2457 }
2458
2459 void rt2800_config(struct rt2x00_dev *rt2x00dev,
2460                    struct rt2x00lib_conf *libconf,
2461                    const unsigned int flags)
2462 {
2463         /* Always recalculate LNA gain before changing configuration */
2464         rt2800_config_lna_gain(rt2x00dev, libconf);
2465
2466         if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
2467                 rt2800_config_channel(rt2x00dev, libconf->conf,
2468                                       &libconf->rf, &libconf->channel);
2469                 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2470                                       libconf->conf->power_level);
2471         }
2472         if (flags & IEEE80211_CONF_CHANGE_POWER)
2473                 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2474                                       libconf->conf->power_level);
2475         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2476                 rt2800_config_retry_limit(rt2x00dev, libconf);
2477         if (flags & IEEE80211_CONF_CHANGE_PS)
2478                 rt2800_config_ps(rt2x00dev, libconf);
2479 }
2480 EXPORT_SYMBOL_GPL(rt2800_config);
2481
2482 /*
2483  * Link tuning
2484  */
2485 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2486 {
2487         u32 reg;
2488
2489         /*
2490          * Update FCS error count from register.
2491          */
2492         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2493         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
2494 }
2495 EXPORT_SYMBOL_GPL(rt2800_link_stats);
2496
2497 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
2498 {
2499         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2500                 if (rt2x00_rt(rt2x00dev, RT3070) ||
2501                     rt2x00_rt(rt2x00dev, RT3071) ||
2502                     rt2x00_rt(rt2x00dev, RT3090) ||
2503                     rt2x00_rt(rt2x00dev, RT3390) ||
2504                     rt2x00_rt(rt2x00dev, RT5390))
2505                         return 0x1c + (2 * rt2x00dev->lna_gain);
2506                 else
2507                         return 0x2e + rt2x00dev->lna_gain;
2508         }
2509
2510         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2511                 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
2512         else
2513                 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
2514 }
2515
2516 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
2517                                   struct link_qual *qual, u8 vgc_level)
2518 {
2519         if (qual->vgc_level != vgc_level) {
2520                 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
2521                 qual->vgc_level = vgc_level;
2522                 qual->vgc_level_reg = vgc_level;
2523         }
2524 }
2525
2526 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2527 {
2528         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
2529 }
2530 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
2531
2532 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
2533                        const u32 count)
2534 {
2535         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
2536                 return;
2537
2538         /*
2539          * When RSSI is better then -80 increase VGC level with 0x10
2540          */
2541         rt2800_set_vgc(rt2x00dev, qual,
2542                        rt2800_get_default_vgc(rt2x00dev) +
2543                        ((qual->rssi > -80) * 0x10));
2544 }
2545 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
2546
2547 /*
2548  * Initialization functions.
2549  */
2550 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
2551 {
2552         u32 reg;
2553         u16 eeprom;
2554         unsigned int i;
2555         int ret;
2556
2557         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2558         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2559         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2560         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2561         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2562         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2563         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2564
2565         ret = rt2800_drv_init_registers(rt2x00dev);
2566         if (ret)
2567                 return ret;
2568
2569         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
2570         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
2571         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
2572         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
2573         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
2574         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
2575
2576         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
2577         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
2578         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
2579         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
2580         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
2581         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
2582
2583         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
2584         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
2585
2586         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
2587
2588         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2589         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
2590         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2591         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
2592         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2593         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2594         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
2595         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2596
2597         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
2598
2599         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
2600         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
2601         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
2602         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2603
2604         if (rt2x00_rt(rt2x00dev, RT3071) ||
2605             rt2x00_rt(rt2x00dev, RT3090) ||
2606             rt2x00_rt(rt2x00dev, RT3390)) {
2607                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2608                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2609                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2610                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2611                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
2612                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2613                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
2614                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2615                                                       0x0000002c);
2616                         else
2617                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2618                                                       0x0000000f);
2619                 } else {
2620                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2621                 }
2622         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
2623                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2624
2625                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2626                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2627                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
2628                 } else {
2629                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2630                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2631                 }
2632         } else if (rt2800_is_305x_soc(rt2x00dev)) {
2633                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2634                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2635                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
2636         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
2637                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2638                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2639         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2640                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
2641                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2642                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2643         } else {
2644                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
2645                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2646         }
2647
2648         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
2649         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
2650         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
2651         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
2652         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
2653         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
2654         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
2655         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
2656         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
2657         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
2658
2659         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
2660         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
2661         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
2662         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
2663         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
2664
2665         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
2666         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
2667         if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
2668             rt2x00_rt(rt2x00dev, RT2883) ||
2669             rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
2670                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
2671         else
2672                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
2673         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
2674         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
2675         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
2676
2677         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
2678         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
2679         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
2680         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
2681         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
2682         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
2683         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
2684         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
2685         rt2800_register_write(rt2x00dev, LED_CFG, reg);
2686
2687         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
2688
2689         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2690         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
2691         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
2692         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
2693         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
2694         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
2695         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
2696         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2697
2698         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
2699         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
2700         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
2701         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
2702         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
2703         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
2704         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
2705         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
2706         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2707
2708         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2709         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
2710         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
2711         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
2712         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2713         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2714         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2715         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2716         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2717         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2718         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
2719         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2720
2721         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2722         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
2723         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
2724         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
2725         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2726         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2727         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2728         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2729         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2730         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2731         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
2732         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2733
2734         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2735         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
2736         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
2737         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
2738         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2739         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2740         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2741         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2742         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2743         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2744         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
2745         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2746
2747         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2748         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
2749         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
2750         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
2751         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2752         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2753         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2754         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2755         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2756         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
2757         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
2758         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2759
2760         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2761         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
2762         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
2763         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
2764         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2765         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2766         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2767         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2768         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2769         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2770         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
2771         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2772
2773         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2774         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
2775         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
2776         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
2777         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2778         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2779         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2780         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2781         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2782         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
2783         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
2784         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2785
2786         if (rt2x00_is_usb(rt2x00dev)) {
2787                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
2788
2789                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2790                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2791                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2792                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2793                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2794                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
2795                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
2796                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
2797                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
2798                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
2799                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2800         }
2801
2802         /*
2803          * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
2804          * although it is reserved.
2805          */
2806         rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
2807         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
2808         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
2809         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
2810         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
2811         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
2812         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
2813         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
2814         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
2815         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
2816         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
2817         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
2818
2819         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
2820
2821         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2822         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
2823         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
2824                            IEEE80211_MAX_RTS_THRESHOLD);
2825         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
2826         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2827
2828         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
2829
2830         /*
2831          * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
2832          * time should be set to 16. However, the original Ralink driver uses
2833          * 16 for both and indeed using a value of 10 for CCK SIFS results in
2834          * connection problems with 11g + CTS protection. Hence, use the same
2835          * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
2836          */
2837         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
2838         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
2839         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
2840         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
2841         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
2842         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
2843         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
2844
2845         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
2846
2847         /*
2848          * ASIC will keep garbage value after boot, clear encryption keys.
2849          */
2850         for (i = 0; i < 4; i++)
2851                 rt2800_register_write(rt2x00dev,
2852                                          SHARED_KEY_MODE_ENTRY(i), 0);
2853
2854         for (i = 0; i < 256; i++) {
2855                 rt2800_config_wcid(rt2x00dev, NULL, i);
2856                 rt2800_delete_wcid_attr(rt2x00dev, i);
2857                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
2858         }
2859
2860         /*
2861          * Clear all beacons
2862          */
2863         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
2864         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
2865         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
2866         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
2867         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
2868         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
2869         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
2870         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
2871
2872         if (rt2x00_is_usb(rt2x00dev)) {
2873                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2874                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
2875                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
2876         } else if (rt2x00_is_pcie(rt2x00dev)) {
2877                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2878                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
2879                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
2880         }
2881
2882         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
2883         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
2884         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
2885         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
2886         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
2887         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
2888         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
2889         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
2890         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
2891         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
2892
2893         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
2894         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
2895         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
2896         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
2897         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
2898         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
2899         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
2900         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
2901         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
2902         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
2903
2904         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
2905         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
2906         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
2907         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
2908         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
2909         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
2910         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
2911         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
2912         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
2913         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
2914
2915         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
2916         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
2917         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
2918         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
2919         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
2920         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
2921
2922         /*
2923          * Do not force the BA window size, we use the TXWI to set it
2924          */
2925         rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
2926         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
2927         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
2928         rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
2929
2930         /*
2931          * We must clear the error counters.
2932          * These registers are cleared on read,
2933          * so we may pass a useless variable to store the value.
2934          */
2935         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2936         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
2937         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
2938         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
2939         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
2940         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
2941
2942         /*
2943          * Setup leadtime for pre tbtt interrupt to 6ms
2944          */
2945         rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
2946         rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
2947         rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
2948
2949         /*
2950          * Set up channel statistics timer
2951          */
2952         rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
2953         rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
2954         rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
2955         rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
2956         rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
2957         rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
2958         rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
2959
2960         return 0;
2961 }
2962
2963 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
2964 {
2965         unsigned int i;
2966         u32 reg;
2967
2968         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2969                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
2970                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
2971                         return 0;
2972
2973                 udelay(REGISTER_BUSY_DELAY);
2974         }
2975
2976         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
2977         return -EACCES;
2978 }
2979
2980 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
2981 {
2982         unsigned int i;
2983         u8 value;
2984
2985         /*
2986          * BBP was enabled after firmware was loaded,
2987          * but we need to reactivate it now.
2988          */
2989         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
2990         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
2991         msleep(1);
2992
2993         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2994                 rt2800_bbp_read(rt2x00dev, 0, &value);
2995                 if ((value != 0xff) && (value != 0x00))
2996                         return 0;
2997                 udelay(REGISTER_BUSY_DELAY);
2998         }
2999
3000         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
3001         return -EACCES;
3002 }
3003
3004 static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3005 {
3006         unsigned int i;
3007         u16 eeprom;
3008         u8 reg_id;
3009         u8 value;
3010
3011         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
3012                      rt2800_wait_bbp_ready(rt2x00dev)))
3013                 return -EACCES;
3014
3015         if (rt2x00_rt(rt2x00dev, RT5390)) {
3016                 rt2800_bbp_read(rt2x00dev, 4, &value);
3017                 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
3018                 rt2800_bbp_write(rt2x00dev, 4, value);
3019         }
3020
3021         if (rt2800_is_305x_soc(rt2x00dev) ||
3022             rt2x00_rt(rt2x00dev, RT3572) ||
3023             rt2x00_rt(rt2x00dev, RT5390))
3024                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3025
3026         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
3027         rt2800_bbp_write(rt2x00dev, 66, 0x38);
3028
3029         if (rt2x00_rt(rt2x00dev, RT5390))
3030                 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
3031
3032         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
3033                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
3034                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
3035         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
3036                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3037                 rt2800_bbp_write(rt2x00dev, 73, 0x13);
3038                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3039                 rt2800_bbp_write(rt2x00dev, 76, 0x28);
3040                 rt2800_bbp_write(rt2x00dev, 77, 0x59);
3041         } else {
3042                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3043                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
3044         }
3045
3046         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3047
3048         if (rt2x00_rt(rt2x00dev, RT3070) ||
3049             rt2x00_rt(rt2x00dev, RT3071) ||
3050             rt2x00_rt(rt2x00dev, RT3090) ||
3051             rt2x00_rt(rt2x00dev, RT3390) ||
3052             rt2x00_rt(rt2x00dev, RT3572) ||
3053             rt2x00_rt(rt2x00dev, RT5390)) {
3054                 rt2800_bbp_write(rt2x00dev, 79, 0x13);
3055                 rt2800_bbp_write(rt2x00dev, 80, 0x05);
3056                 rt2800_bbp_write(rt2x00dev, 81, 0x33);
3057         } else if (rt2800_is_305x_soc(rt2x00dev)) {
3058                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
3059                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
3060         } else {
3061                 rt2800_bbp_write(rt2x00dev, 81, 0x37);
3062         }
3063
3064         rt2800_bbp_write(rt2x00dev, 82, 0x62);
3065         if (rt2x00_rt(rt2x00dev, RT5390))
3066                 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3067         else
3068                 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3069
3070         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
3071                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
3072         else if (rt2x00_rt(rt2x00dev, RT5390))
3073                 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
3074         else
3075                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
3076
3077         if (rt2x00_rt(rt2x00dev, RT5390))
3078                 rt2800_bbp_write(rt2x00dev, 86, 0x38);
3079         else
3080                 rt2800_bbp_write(rt2x00dev, 86, 0x00);
3081
3082         rt2800_bbp_write(rt2x00dev, 91, 0x04);
3083
3084         if (rt2x00_rt(rt2x00dev, RT5390))
3085                 rt2800_bbp_write(rt2x00dev, 92, 0x02);
3086         else
3087                 rt2800_bbp_write(rt2x00dev, 92, 0x00);
3088
3089         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
3090             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
3091             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
3092             rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
3093             rt2x00_rt(rt2x00dev, RT3572) ||
3094             rt2x00_rt(rt2x00dev, RT5390) ||
3095             rt2800_is_305x_soc(rt2x00dev))
3096                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
3097         else
3098                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
3099
3100         if (rt2x00_rt(rt2x00dev, RT5390))
3101                 rt2800_bbp_write(rt2x00dev, 104, 0x92);
3102
3103         if (rt2800_is_305x_soc(rt2x00dev))
3104                 rt2800_bbp_write(rt2x00dev, 105, 0x01);
3105         else if (rt2x00_rt(rt2x00dev, RT5390))
3106                 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
3107         else
3108                 rt2800_bbp_write(rt2x00dev, 105, 0x05);
3109
3110         if (rt2x00_rt(rt2x00dev, RT5390))
3111                 rt2800_bbp_write(rt2x00dev, 106, 0x03);
3112         else
3113                 rt2800_bbp_write(rt2x00dev, 106, 0x35);
3114
3115         if (rt2x00_rt(rt2x00dev, RT5390))
3116                 rt2800_bbp_write(rt2x00dev, 128, 0x12);
3117
3118         if (rt2x00_rt(rt2x00dev, RT3071) ||
3119             rt2x00_rt(rt2x00dev, RT3090) ||
3120             rt2x00_rt(rt2x00dev, RT3390) ||
3121             rt2x00_rt(rt2x00dev, RT3572) ||
3122             rt2x00_rt(rt2x00dev, RT5390)) {
3123                 rt2800_bbp_read(rt2x00dev, 138, &value);
3124
3125                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3126                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
3127                         value |= 0x20;
3128                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
3129                         value &= ~0x02;
3130
3131                 rt2800_bbp_write(rt2x00dev, 138, value);
3132         }
3133
3134         if (rt2x00_rt(rt2x00dev, RT5390)) {
3135                 int ant, div_mode;
3136
3137                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3138                 div_mode = rt2x00_get_field16(eeprom,
3139                                               EEPROM_NIC_CONF1_ANT_DIVERSITY);
3140                 ant = (div_mode == 3) ? 1 : 0;
3141
3142                 /* check if this is a Bluetooth combo card */
3143                 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
3144                         u32 reg;
3145
3146                         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
3147                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
3148                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT6, 0);
3149                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 0);
3150                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 0);
3151                         if (ant == 0)
3152                                 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 1);
3153                         else if (ant == 1)
3154                                 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 1);
3155                         rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
3156                 }
3157
3158                 rt2800_bbp_read(rt2x00dev, 152, &value);
3159                 if (ant == 0)
3160                         rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
3161                 else
3162                         rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
3163                 rt2800_bbp_write(rt2x00dev, 152, value);
3164
3165                 /* Init frequency calibration */
3166                 rt2800_bbp_write(rt2x00dev, 142, 1);
3167                 rt2800_bbp_write(rt2x00dev, 143, 57);
3168         }
3169
3170         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
3171                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
3172
3173                 if (eeprom != 0xffff && eeprom != 0x0000) {
3174                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
3175                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
3176                         rt2800_bbp_write(rt2x00dev, reg_id, value);
3177                 }
3178         }
3179
3180         return 0;
3181 }
3182
3183 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
3184                                 bool bw40, u8 rfcsr24, u8 filter_target)
3185 {
3186         unsigned int i;
3187         u8 bbp;
3188         u8 rfcsr;
3189         u8 passband;
3190         u8 stopband;
3191         u8 overtuned = 0;
3192
3193         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3194
3195         rt2800_bbp_read(rt2x00dev, 4, &bbp);
3196         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
3197         rt2800_bbp_write(rt2x00dev, 4, bbp);
3198
3199         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
3200         rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
3201         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
3202
3203         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3204         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
3205         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3206
3207         /*
3208          * Set power & frequency of passband test tone
3209          */
3210         rt2800_bbp_write(rt2x00dev, 24, 0);
3211
3212         for (i = 0; i < 100; i++) {
3213                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3214                 msleep(1);
3215
3216                 rt2800_bbp_read(rt2x00dev, 55, &passband);
3217                 if (passband)
3218                         break;
3219         }
3220
3221         /*
3222          * Set power & frequency of stopband test tone
3223          */
3224         rt2800_bbp_write(rt2x00dev, 24, 0x06);
3225
3226         for (i = 0; i < 100; i++) {
3227                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3228                 msleep(1);
3229
3230                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
3231
3232                 if ((passband - stopband) <= filter_target) {
3233                         rfcsr24++;
3234                         overtuned += ((passband - stopband) == filter_target);
3235                 } else
3236                         break;
3237
3238                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3239         }
3240
3241         rfcsr24 -= !!overtuned;
3242
3243         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3244         return rfcsr24;
3245 }
3246
3247 static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
3248 {
3249         u8 rfcsr;
3250         u8 bbp;
3251         u32 reg;
3252         u16 eeprom;
3253
3254         if (!rt2x00_rt(rt2x00dev, RT3070) &&
3255             !rt2x00_rt(rt2x00dev, RT3071) &&
3256             !rt2x00_rt(rt2x00dev, RT3090) &&
3257             !rt2x00_rt(rt2x00dev, RT3390) &&
3258             !rt2x00_rt(rt2x00dev, RT3572) &&
3259             !rt2x00_rt(rt2x00dev, RT5390) &&
3260             !rt2800_is_305x_soc(rt2x00dev))
3261                 return 0;
3262
3263         /*
3264          * Init RF calibration.
3265          */
3266         if (rt2x00_rt(rt2x00dev, RT5390)) {
3267                 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
3268                 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
3269                 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3270                 msleep(1);
3271                 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
3272                 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3273         } else {
3274                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3275                 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
3276                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3277                 msleep(1);
3278                 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
3279                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3280         }
3281
3282         if (rt2x00_rt(rt2x00dev, RT3070) ||
3283             rt2x00_rt(rt2x00dev, RT3071) ||
3284             rt2x00_rt(rt2x00dev, RT3090)) {
3285                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3286                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3287                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3288                 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
3289                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3290                 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
3291                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3292                 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
3293                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3294                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3295                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3296                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3297                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3298                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3299                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3300                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3301                 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3302                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3303                 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
3304         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3305                 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
3306                 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
3307                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3308                 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
3309                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3310                 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
3311                 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
3312                 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
3313                 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
3314                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
3315                 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
3316                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3317                 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
3318                 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
3319                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3320                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3321                 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
3322                 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
3323                 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
3324                 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
3325                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
3326                 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
3327                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3328                 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
3329                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
3330                 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
3331                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3332                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3333                 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
3334                 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
3335                 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
3336                 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
3337         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3338                 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
3339                 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
3340                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3341                 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
3342                 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
3343                 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
3344                 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
3345                 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
3346                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
3347                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
3348                 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
3349                 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
3350                 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
3351                 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
3352                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3353                 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
3354                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
3355                 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
3356                 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
3357                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
3358                 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
3359                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3360                 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
3361                 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3362                 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
3363                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3364                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3365                 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3366                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
3367                 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
3368                 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
3369         } else if (rt2800_is_305x_soc(rt2x00dev)) {
3370                 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
3371                 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
3372                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
3373                 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
3374                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3375                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3376                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3377                 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
3378                 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
3379                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3380                 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
3381                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3382                 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
3383                 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
3384                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3385                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3386                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3387                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3388                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3389                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3390                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3391                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3392                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3393                 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
3394                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
3395                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3396                 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
3397                 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
3398                 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
3399                 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
3400                 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3401                 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
3402                 return 0;
3403         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
3404                 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
3405                 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
3406                 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
3407                 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
3408                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3409                         rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
3410                 else
3411                         rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
3412                 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
3413                 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3414                 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3415                 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
3416                 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3417                 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
3418                 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
3419                 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
3420                 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
3421                 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
3422
3423                 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
3424                 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
3425                 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
3426                 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
3427                 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
3428                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3429                         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3430                 else
3431                         rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
3432                 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
3433                 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3434                 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3435                 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3436
3437                 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3438                 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3439                 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3440                 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
3441                 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
3442                 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3443                 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3444                 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3445                 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3446                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3447
3448                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3449                         rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
3450                 else
3451                         rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
3452                 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3453                 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
3454                 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
3455                 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3456                 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3457                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3458                         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3459                 else
3460                         rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
3461                 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
3462                 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3463                 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
3464
3465                 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
3466                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3467                         rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
3468                 else
3469                         rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
3470                 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
3471                 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
3472                 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
3473                 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
3474                 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
3475                 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
3476
3477                 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3478                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3479                         rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
3480                 else
3481                         rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
3482                 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
3483                 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
3484         }
3485
3486         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
3487                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3488                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3489                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3490                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3491         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3492                    rt2x00_rt(rt2x00dev, RT3090)) {
3493                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
3494
3495                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3496                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3497                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3498
3499                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3500                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3501                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3502                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
3503                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3504                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
3505                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3506                         else
3507                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
3508                 }
3509                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3510
3511                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3512                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3513                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
3514         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3515                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3516                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3517                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
3518         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3519                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3520                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3521                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3522
3523                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3524                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3525                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3526                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3527                 msleep(1);
3528                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3529                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3530                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3531         }
3532
3533         /*
3534          * Set RX Filter calibration for 20MHz and 40MHz
3535          */
3536         if (rt2x00_rt(rt2x00dev, RT3070)) {
3537                 rt2x00dev->calibration[0] =
3538                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
3539                 rt2x00dev->calibration[1] =
3540                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
3541         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3542                    rt2x00_rt(rt2x00dev, RT3090) ||
3543                    rt2x00_rt(rt2x00dev, RT3390) ||
3544                    rt2x00_rt(rt2x00dev, RT3572)) {
3545                 rt2x00dev->calibration[0] =
3546                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
3547                 rt2x00dev->calibration[1] =
3548                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
3549         }
3550
3551         if (!rt2x00_rt(rt2x00dev, RT5390)) {
3552                 /*
3553                  * Set back to initial state
3554                  */
3555                 rt2800_bbp_write(rt2x00dev, 24, 0);
3556
3557                 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3558                 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
3559                 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3560
3561                 /*
3562                  * Set BBP back to BW20
3563                  */
3564                 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3565                 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
3566                 rt2800_bbp_write(rt2x00dev, 4, bbp);
3567         }
3568
3569         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
3570             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3571             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3572             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
3573                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
3574
3575         rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
3576         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
3577         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
3578
3579         if (!rt2x00_rt(rt2x00dev, RT5390)) {
3580                 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
3581                 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
3582                 if (rt2x00_rt(rt2x00dev, RT3070) ||
3583                     rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3584                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3585                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
3586                         if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG,
3587                                       &rt2x00dev->cap_flags))
3588                                 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
3589                 }
3590                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
3591                 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
3592                         rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
3593                                         rt2x00_get_field16(eeprom,
3594                                                 EEPROM_TXMIXER_GAIN_BG_VAL));
3595                 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3596         }
3597
3598         if (rt2x00_rt(rt2x00dev, RT3090)) {
3599                 rt2800_bbp_read(rt2x00dev, 138, &bbp);
3600
3601                 /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
3602                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3603                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
3604                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
3605                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
3606                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
3607
3608                 rt2800_bbp_write(rt2x00dev, 138, bbp);
3609         }
3610
3611         if (rt2x00_rt(rt2x00dev, RT3071) ||
3612             rt2x00_rt(rt2x00dev, RT3090) ||
3613             rt2x00_rt(rt2x00dev, RT3390)) {
3614                 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
3615                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3616                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
3617                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
3618                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3619                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3620                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3621
3622                 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
3623                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
3624                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
3625
3626                 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
3627                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
3628                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
3629
3630                 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
3631                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
3632                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3633         }
3634
3635         if (rt2x00_rt(rt2x00dev, RT3070)) {
3636                 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
3637                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
3638                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
3639                 else
3640                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
3641                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
3642                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
3643                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
3644                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
3645         }
3646
3647         if (rt2x00_rt(rt2x00dev, RT5390)) {
3648                 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
3649                 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
3650                 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
3651
3652                 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
3653                 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
3654                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3655
3656                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3657                 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
3658                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3659         }
3660
3661         return 0;
3662 }
3663
3664 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
3665 {
3666         u32 reg;
3667         u16 word;
3668
3669         /*
3670          * Initialize all registers.
3671          */
3672         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
3673                      rt2800_init_registers(rt2x00dev) ||
3674                      rt2800_init_bbp(rt2x00dev) ||
3675                      rt2800_init_rfcsr(rt2x00dev)))
3676                 return -EIO;
3677
3678         /*
3679          * Send signal to firmware during boot time.
3680          */
3681         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
3682
3683         if (rt2x00_is_usb(rt2x00dev) &&
3684             (rt2x00_rt(rt2x00dev, RT3070) ||
3685              rt2x00_rt(rt2x00dev, RT3071) ||
3686              rt2x00_rt(rt2x00dev, RT3572))) {
3687                 udelay(200);
3688                 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
3689                 udelay(10);
3690         }
3691
3692         /*
3693          * Enable RX.
3694          */
3695         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3696         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3697         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
3698         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3699
3700         udelay(50);
3701
3702         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3703         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
3704         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
3705         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
3706         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
3707         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3708
3709         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3710         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3711         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
3712         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3713
3714         /*
3715          * Initialize LED control
3716          */
3717         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
3718         rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
3719                            word & 0xff, (word >> 8) & 0xff);
3720
3721         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
3722         rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
3723                            word & 0xff, (word >> 8) & 0xff);
3724
3725         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
3726         rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
3727                            word & 0xff, (word >> 8) & 0xff);
3728
3729         return 0;
3730 }
3731 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
3732
3733 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
3734 {
3735         u32 reg;
3736
3737         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3738         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
3739         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
3740         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3741
3742         /* Wait for DMA, ignore error */
3743         rt2800_wait_wpdma_ready(rt2x00dev);
3744
3745         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3746         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
3747         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
3748         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3749 }
3750 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
3751
3752 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
3753 {
3754         u32 reg;
3755
3756         rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
3757
3758         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
3759 }
3760 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
3761
3762 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
3763 {
3764         u32 reg;
3765
3766         mutex_lock(&rt2x00dev->csr_mutex);
3767
3768         rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
3769         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
3770         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
3771         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
3772         rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
3773
3774         /* Wait until the EEPROM has been loaded */
3775         rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
3776
3777         /* Apparently the data is read from end to start */
3778         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3, &reg);
3779         /* The returned value is in CPU order, but eeprom is le */
3780         *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
3781         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2, &reg);
3782         *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
3783         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1, &reg);
3784         *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
3785         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0, &reg);
3786         *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
3787
3788         mutex_unlock(&rt2x00dev->csr_mutex);
3789 }
3790
3791 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
3792 {
3793         unsigned int i;
3794
3795         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
3796                 rt2800_efuse_read(rt2x00dev, i);
3797 }
3798 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
3799
3800 int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
3801 {
3802         u16 word;
3803         u8 *mac;
3804         u8 default_lna_gain;
3805
3806         /*
3807          * Start validation of the data that has been read.
3808          */
3809         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
3810         if (!is_valid_ether_addr(mac)) {
3811                 random_ether_addr(mac);
3812                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
3813         }
3814
3815         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
3816         if (word == 0xffff) {
3817                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3818                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
3819                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
3820                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
3821                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
3822         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
3823                    rt2x00_rt(rt2x00dev, RT2872)) {
3824                 /*
3825                  * There is a max of 2 RX streams for RT28x0 series
3826                  */
3827                 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
3828                         rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3829                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
3830         }
3831
3832         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
3833         if (word == 0xffff) {
3834                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
3835                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
3836                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
3837                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
3838                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
3839                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
3840                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
3841                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
3842                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
3843                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
3844                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
3845                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
3846                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
3847                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
3848                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
3849                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
3850                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
3851         }
3852
3853         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
3854         if ((word & 0x00ff) == 0x00ff) {
3855                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
3856                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
3857                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
3858         }
3859         if ((word & 0xff00) == 0xff00) {
3860                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
3861                                    LED_MODE_TXRX_ACTIVITY);
3862                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
3863                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
3864                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
3865                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
3866                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
3867                 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
3868         }
3869
3870         /*
3871          * During the LNA validation we are going to use
3872          * lna0 as correct value. Note that EEPROM_LNA
3873          * is never validated.
3874          */
3875         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
3876         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
3877
3878         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
3879         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
3880                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
3881         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
3882                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
3883         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
3884
3885         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
3886         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
3887                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
3888         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
3889             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
3890                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
3891                                    default_lna_gain);
3892         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
3893
3894         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
3895         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
3896                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
3897         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
3898                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
3899         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
3900
3901         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
3902         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
3903                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
3904         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
3905             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
3906                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
3907                                    default_lna_gain);
3908         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
3909
3910         return 0;
3911 }
3912 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
3913
3914 int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
3915 {
3916         u32 reg;
3917         u16 value;
3918         u16 eeprom;
3919
3920         /*
3921          * Read EEPROM word for configuration.
3922          */
3923         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3924
3925         /*
3926          * Identify RF chipset by EEPROM value
3927          * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
3928          * RT53xx: defined in "EEPROM_CHIP_ID" field
3929          */
3930         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
3931         if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390)
3932                 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
3933         else
3934                 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
3935
3936         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
3937                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
3938
3939         switch (rt2x00dev->chip.rt) {
3940         case RT2860:
3941         case RT2872:
3942         case RT2883:
3943         case RT3070:
3944         case RT3071:
3945         case RT3090:
3946         case RT3390:
3947         case RT3572:
3948         case RT5390:
3949                 break;
3950         default:
3951                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
3952                 return -ENODEV;
3953         }
3954
3955         switch (rt2x00dev->chip.rf) {
3956         case RF2820:
3957         case RF2850:
3958         case RF2720:
3959         case RF2750:
3960         case RF3020:
3961         case RF2020:
3962         case RF3021:
3963         case RF3022:
3964         case RF3052:
3965         case RF3320:
3966         case RF5370:
3967         case RF5390:
3968                 break;
3969         default:
3970                 ERROR(rt2x00dev, "Invalid RF chipset 0x%x detected.\n",
3971                       rt2x00dev->chip.rf);
3972                 return -ENODEV;
3973         }
3974
3975         /*
3976          * Identify default antenna configuration.
3977          */
3978         rt2x00dev->default_ant.tx_chain_num =
3979             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
3980         rt2x00dev->default_ant.rx_chain_num =
3981             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
3982
3983         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3984
3985         if (rt2x00_rt(rt2x00dev, RT3070) ||
3986             rt2x00_rt(rt2x00dev, RT3090) ||
3987             rt2x00_rt(rt2x00dev, RT3390)) {
3988                 value = rt2x00_get_field16(eeprom,
3989                                 EEPROM_NIC_CONF1_ANT_DIVERSITY);
3990                 switch (value) {
3991                 case 0:
3992                 case 1:
3993                 case 2:
3994                         rt2x00dev->default_ant.tx = ANTENNA_A;
3995                         rt2x00dev->default_ant.rx = ANTENNA_A;
3996                         break;
3997                 case 3:
3998                         rt2x00dev->default_ant.tx = ANTENNA_A;
3999                         rt2x00dev->default_ant.rx = ANTENNA_B;
4000                         break;
4001                 }
4002         } else {
4003                 rt2x00dev->default_ant.tx = ANTENNA_A;
4004                 rt2x00dev->default_ant.rx = ANTENNA_A;
4005         }
4006
4007         /*
4008          * Determine external LNA informations.
4009          */
4010         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
4011                 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
4012         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
4013                 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
4014
4015         /*
4016          * Detect if this device has an hardware controlled radio.
4017          */
4018         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
4019                 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
4020
4021         /*
4022          * Detect if this device has Bluetooth co-existence.
4023          */
4024         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
4025                 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
4026
4027         /*
4028          * Read frequency offset and RF programming sequence.
4029          */
4030         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
4031         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
4032
4033         /*
4034          * Store led settings, for correct led behaviour.
4035          */
4036 #ifdef CONFIG_RT2X00_LIB_LEDS
4037         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
4038         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
4039         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
4040
4041         rt2x00dev->led_mcu_reg = eeprom;
4042 #endif /* CONFIG_RT2X00_LIB_LEDS */
4043
4044         /*
4045          * Check if support EIRP tx power limit feature.
4046          */
4047         rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
4048
4049         if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
4050                                         EIRP_MAX_TX_POWER_LIMIT)
4051                 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
4052
4053         return 0;
4054 }
4055 EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
4056
4057 /*
4058  * RF value list for rt28xx
4059  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
4060  */
4061 static const struct rf_channel rf_vals[] = {
4062         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
4063         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
4064         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
4065         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
4066         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
4067         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
4068         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
4069         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
4070         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
4071         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
4072         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
4073         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
4074         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
4075         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
4076
4077         /* 802.11 UNI / HyperLan 2 */
4078         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
4079         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
4080         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
4081         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
4082         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
4083         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
4084         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
4085         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
4086         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
4087         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
4088         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
4089         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
4090
4091         /* 802.11 HyperLan 2 */
4092         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
4093         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
4094         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
4095         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
4096         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
4097         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
4098         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
4099         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
4100         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
4101         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
4102         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
4103         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
4104         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
4105         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
4106         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
4107         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
4108
4109         /* 802.11 UNII */
4110         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
4111         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
4112         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
4113         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
4114         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
4115         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
4116         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
4117         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
4118         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
4119         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
4120         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
4121
4122         /* 802.11 Japan */
4123         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
4124         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
4125         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
4126         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
4127         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
4128         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
4129         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
4130 };
4131
4132 /*
4133  * RF value list for rt3xxx
4134  * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4135  */
4136 static const struct rf_channel rf_vals_3x[] = {
4137         {1,  241, 2, 2 },
4138         {2,  241, 2, 7 },
4139         {3,  242, 2, 2 },
4140         {4,  242, 2, 7 },
4141         {5,  243, 2, 2 },
4142         {6,  243, 2, 7 },
4143         {7,  244, 2, 2 },
4144         {8,  244, 2, 7 },
4145         {9,  245, 2, 2 },
4146         {10, 245, 2, 7 },
4147         {11, 246, 2, 2 },
4148         {12, 246, 2, 7 },
4149         {13, 247, 2, 2 },
4150         {14, 248, 2, 4 },
4151
4152         /* 802.11 UNI / HyperLan 2 */
4153         {36, 0x56, 0, 4},
4154         {38, 0x56, 0, 6},
4155         {40, 0x56, 0, 8},
4156         {44, 0x57, 0, 0},
4157         {46, 0x57, 0, 2},
4158         {48, 0x57, 0, 4},
4159         {52, 0x57, 0, 8},
4160         {54, 0x57, 0, 10},
4161         {56, 0x58, 0, 0},
4162         {60, 0x58, 0, 4},
4163         {62, 0x58, 0, 6},
4164         {64, 0x58, 0, 8},
4165
4166         /* 802.11 HyperLan 2 */
4167         {100, 0x5b, 0, 8},
4168         {102, 0x5b, 0, 10},
4169         {104, 0x5c, 0, 0},
4170         {108, 0x5c, 0, 4},
4171         {110, 0x5c, 0, 6},
4172         {112, 0x5c, 0, 8},
4173         {116, 0x5d, 0, 0},
4174         {118, 0x5d, 0, 2},
4175         {120, 0x5d, 0, 4},
4176         {124, 0x5d, 0, 8},
4177         {126, 0x5d, 0, 10},
4178         {128, 0x5e, 0, 0},
4179         {132, 0x5e, 0, 4},
4180         {134, 0x5e, 0, 6},
4181         {136, 0x5e, 0, 8},
4182         {140, 0x5f, 0, 0},
4183
4184         /* 802.11 UNII */
4185         {149, 0x5f, 0, 9},
4186         {151, 0x5f, 0, 11},
4187         {153, 0x60, 0, 1},
4188         {157, 0x60, 0, 5},
4189         {159, 0x60, 0, 7},
4190         {161, 0x60, 0, 9},
4191         {165, 0x61, 0, 1},
4192         {167, 0x61, 0, 3},
4193         {169, 0x61, 0, 5},
4194         {171, 0x61, 0, 7},
4195         {173, 0x61, 0, 9},
4196 };
4197
4198 int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
4199 {
4200         struct hw_mode_spec *spec = &rt2x00dev->spec;
4201         struct channel_info *info;
4202         char *default_power1;
4203         char *default_power2;
4204         unsigned int i;
4205         u16 eeprom;
4206
4207         /*
4208          * Disable powersaving as default on PCI devices.
4209          */
4210         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
4211                 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
4212
4213         /*
4214          * Initialize all hw fields.
4215          */
4216         rt2x00dev->hw->flags =
4217             IEEE80211_HW_SIGNAL_DBM |
4218             IEEE80211_HW_SUPPORTS_PS |
4219             IEEE80211_HW_PS_NULLFUNC_STACK |
4220             IEEE80211_HW_AMPDU_AGGREGATION;
4221         /*
4222          * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
4223          * unless we are capable of sending the buffered frames out after the
4224          * DTIM transmission using rt2x00lib_beacondone. This will send out
4225          * multicast and broadcast traffic immediately instead of buffering it
4226          * infinitly and thus dropping it after some time.
4227          */
4228         if (!rt2x00_is_usb(rt2x00dev))
4229                 rt2x00dev->hw->flags |=
4230                         IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
4231
4232         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
4233         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
4234                                 rt2x00_eeprom_addr(rt2x00dev,
4235                                                    EEPROM_MAC_ADDR_0));
4236
4237         /*
4238          * As rt2800 has a global fallback table we cannot specify
4239          * more then one tx rate per frame but since the hw will
4240          * try several rates (based on the fallback table) we should
4241          * initialize max_report_rates to the maximum number of rates
4242          * we are going to try. Otherwise mac80211 will truncate our
4243          * reported tx rates and the rc algortihm will end up with
4244          * incorrect data.
4245          */
4246         rt2x00dev->hw->max_rates = 1;
4247         rt2x00dev->hw->max_report_rates = 7;
4248         rt2x00dev->hw->max_rate_tries = 1;
4249
4250         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4251
4252         /*
4253          * Initialize hw_mode information.
4254          */
4255         spec->supported_bands = SUPPORT_BAND_2GHZ;
4256         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
4257
4258         if (rt2x00_rf(rt2x00dev, RF2820) ||
4259             rt2x00_rf(rt2x00dev, RF2720)) {
4260                 spec->num_channels = 14;
4261                 spec->channels = rf_vals;
4262         } else if (rt2x00_rf(rt2x00dev, RF2850) ||
4263                    rt2x00_rf(rt2x00dev, RF2750)) {
4264                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
4265                 spec->num_channels = ARRAY_SIZE(rf_vals);
4266                 spec->channels = rf_vals;
4267         } else if (rt2x00_rf(rt2x00dev, RF3020) ||
4268                    rt2x00_rf(rt2x00dev, RF2020) ||
4269                    rt2x00_rf(rt2x00dev, RF3021) ||
4270                    rt2x00_rf(rt2x00dev, RF3022) ||
4271                    rt2x00_rf(rt2x00dev, RF3320) ||
4272                    rt2x00_rf(rt2x00dev, RF5370) ||
4273                    rt2x00_rf(rt2x00dev, RF5390)) {
4274                 spec->num_channels = 14;
4275                 spec->channels = rf_vals_3x;
4276         } else if (rt2x00_rf(rt2x00dev, RF3052)) {
4277                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
4278                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
4279                 spec->channels = rf_vals_3x;
4280         }
4281
4282         /*
4283          * Initialize HT information.
4284          */
4285         if (!rt2x00_rf(rt2x00dev, RF2020))
4286                 spec->ht.ht_supported = true;
4287         else
4288                 spec->ht.ht_supported = false;
4289
4290         spec->ht.cap =
4291             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4292             IEEE80211_HT_CAP_GRN_FLD |
4293             IEEE80211_HT_CAP_SGI_20 |
4294             IEEE80211_HT_CAP_SGI_40;
4295
4296         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
4297                 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
4298
4299         spec->ht.cap |=
4300             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
4301                 IEEE80211_HT_CAP_RX_STBC_SHIFT;
4302
4303         spec->ht.ampdu_factor = 3;
4304         spec->ht.ampdu_density = 4;
4305         spec->ht.mcs.tx_params =
4306             IEEE80211_HT_MCS_TX_DEFINED |
4307             IEEE80211_HT_MCS_TX_RX_DIFF |
4308             ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
4309                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
4310
4311         switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
4312         case 3:
4313                 spec->ht.mcs.rx_mask[2] = 0xff;
4314         case 2:
4315                 spec->ht.mcs.rx_mask[1] = 0xff;
4316         case 1:
4317                 spec->ht.mcs.rx_mask[0] = 0xff;
4318                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
4319                 break;
4320         }
4321
4322         /*
4323          * Create channel information array
4324          */
4325         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4326         if (!info)
4327                 return -ENOMEM;
4328
4329         spec->channels_info = info;
4330
4331         default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
4332         default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4333
4334         for (i = 0; i < 14; i++) {
4335                 info[i].default_power1 = default_power1[i];
4336                 info[i].default_power2 = default_power2[i];
4337         }
4338
4339         if (spec->num_channels > 14) {
4340                 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
4341                 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
4342
4343                 for (i = 14; i < spec->num_channels; i++) {
4344                         info[i].default_power1 = default_power1[i];
4345                         info[i].default_power2 = default_power2[i];
4346                 }
4347         }
4348
4349         return 0;
4350 }
4351 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
4352
4353 /*
4354  * IEEE80211 stack callback functions.
4355  */
4356 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
4357                          u16 *iv16)
4358 {
4359         struct rt2x00_dev *rt2x00dev = hw->priv;
4360         struct mac_iveiv_entry iveiv_entry;
4361         u32 offset;
4362
4363         offset = MAC_IVEIV_ENTRY(hw_key_idx);
4364         rt2800_register_multiread(rt2x00dev, offset,
4365                                       &iveiv_entry, sizeof(iveiv_entry));
4366
4367         memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
4368         memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
4369 }
4370 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
4371
4372 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
4373 {
4374         struct rt2x00_dev *rt2x00dev = hw->priv;
4375         u32 reg;
4376         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
4377
4378         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
4379         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
4380         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
4381
4382         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
4383         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
4384         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
4385
4386         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
4387         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
4388         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
4389
4390         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
4391         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
4392         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
4393
4394         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
4395         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
4396         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
4397
4398         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
4399         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
4400         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
4401
4402         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
4403         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
4404         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
4405
4406         return 0;
4407 }
4408 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
4409
4410 int rt2800_conf_tx(struct ieee80211_hw *hw,
4411                    struct ieee80211_vif *vif, u16 queue_idx,
4412                    const struct ieee80211_tx_queue_params *params)
4413 {
4414         struct rt2x00_dev *rt2x00dev = hw->priv;
4415         struct data_queue *queue;
4416         struct rt2x00_field32 field;
4417         int retval;
4418         u32 reg;
4419         u32 offset;
4420
4421         /*
4422          * First pass the configuration through rt2x00lib, that will
4423          * update the queue settings and validate the input. After that
4424          * we are free to update the registers based on the value
4425          * in the queue parameter.
4426          */
4427         retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
4428         if (retval)
4429                 return retval;
4430
4431         /*
4432          * We only need to perform additional register initialization
4433          * for WMM queues/
4434          */
4435         if (queue_idx >= 4)
4436                 return 0;
4437
4438         queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
4439
4440         /* Update WMM TXOP register */
4441         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
4442         field.bit_offset = (queue_idx & 1) * 16;
4443         field.bit_mask = 0xffff << field.bit_offset;
4444
4445         rt2800_register_read(rt2x00dev, offset, &reg);
4446         rt2x00_set_field32(&reg, field, queue->txop);
4447         rt2800_register_write(rt2x00dev, offset, reg);
4448
4449         /* Update WMM registers */
4450         field.bit_offset = queue_idx * 4;
4451         field.bit_mask = 0xf << field.bit_offset;
4452
4453         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
4454         rt2x00_set_field32(&reg, field, queue->aifs);
4455         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
4456
4457         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
4458         rt2x00_set_field32(&reg, field, queue->cw_min);
4459         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
4460
4461         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
4462         rt2x00_set_field32(&reg, field, queue->cw_max);
4463         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
4464
4465         /* Update EDCA registers */
4466         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
4467
4468         rt2800_register_read(rt2x00dev, offset, &reg);
4469         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
4470         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
4471         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
4472         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
4473         rt2800_register_write(rt2x00dev, offset, reg);
4474
4475         return 0;
4476 }
4477 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
4478
4479 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
4480 {
4481         struct rt2x00_dev *rt2x00dev = hw->priv;
4482         u64 tsf;
4483         u32 reg;
4484
4485         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
4486         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
4487         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
4488         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
4489
4490         return tsf;
4491 }
4492 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
4493
4494 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4495                         enum ieee80211_ampdu_mlme_action action,
4496                         struct ieee80211_sta *sta, u16 tid, u16 *ssn,
4497                         u8 buf_size)
4498 {
4499         struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
4500         int ret = 0;
4501
4502         /*
4503          * Don't allow aggregation for stations the hardware isn't aware
4504          * of because tx status reports for frames to an unknown station
4505          * always contain wcid=255 and thus we can't distinguish between
4506          * multiple stations which leads to unwanted situations when the
4507          * hw reorders frames due to aggregation.
4508          */
4509         if (sta_priv->wcid < 0)
4510                 return 1;
4511
4512         switch (action) {
4513         case IEEE80211_AMPDU_RX_START:
4514         case IEEE80211_AMPDU_RX_STOP:
4515                 /*
4516                  * The hw itself takes care of setting up BlockAck mechanisms.
4517                  * So, we only have to allow mac80211 to nagotiate a BlockAck
4518                  * agreement. Once that is done, the hw will BlockAck incoming
4519                  * AMPDUs without further setup.
4520                  */
4521                 break;
4522         case IEEE80211_AMPDU_TX_START:
4523                 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4524                 break;
4525         case IEEE80211_AMPDU_TX_STOP:
4526                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4527                 break;
4528         case IEEE80211_AMPDU_TX_OPERATIONAL:
4529                 break;
4530         default:
4531                 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
4532         }
4533
4534         return ret;
4535 }
4536 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
4537
4538 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
4539                       struct survey_info *survey)
4540 {
4541         struct rt2x00_dev *rt2x00dev = hw->priv;
4542         struct ieee80211_conf *conf = &hw->conf;
4543         u32 idle, busy, busy_ext;
4544
4545         if (idx != 0)
4546                 return -ENOENT;
4547
4548         survey->channel = conf->channel;
4549
4550         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
4551         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
4552         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
4553
4554         if (idle || busy) {
4555                 survey->filled = SURVEY_INFO_CHANNEL_TIME |
4556                                  SURVEY_INFO_CHANNEL_TIME_BUSY |
4557                                  SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
4558
4559                 survey->channel_time = (idle + busy) / 1000;
4560                 survey->channel_time_busy = busy / 1000;
4561                 survey->channel_time_ext_busy = busy_ext / 1000;
4562         }
4563
4564         if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
4565                 survey->filled |= SURVEY_INFO_IN_USE;
4566
4567         return 0;
4568
4569 }
4570 EXPORT_SYMBOL_GPL(rt2800_get_survey);
4571
4572 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
4573 MODULE_VERSION(DRV_VERSION);
4574 MODULE_DESCRIPTION("Ralink RT2800 library");
4575 MODULE_LICENSE("GPL");