Pileus Git - ~andy/linux/blob - drivers/net/wireless/p54/p54pci.c

   1
   2 /*
   3  * Linux device driver for PCI based Prism54
   4  *
   5  * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
   6  * Copyright (c) 2008, Christian Lamparter <chunkeey@web.de>
   7  *
   8  * Based on the islsm (softmac prism54) driver, which is:
   9  * Copyright 2004-2006 Jean-Baptiste Note <jean-baptiste.note@m4x.org>, et al.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/pci.h>
  18 #include <linux/firmware.h>
  19 #include <linux/etherdevice.h>
  20 #include <linux/delay.h>
  21 #include <linux/completion.h>
  22 #include <net/mac80211.h>
  23
  24 #include "p54.h"
  25 #include "lmac.h"
  26 #include "p54pci.h"
  27
  28 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
  29 MODULE_DESCRIPTION("Prism54 PCI wireless driver");
  30 MODULE_LICENSE("GPL");
  31 MODULE_ALIAS("prism54pci");
  32 MODULE_FIRMWARE("isl3886pci");
  33
  34 static struct pci_device_id p54p_table[] __devinitdata = {
  35         /* Intersil PRISM Duette/Prism GT Wireless LAN adapter */
  36         { PCI_DEVICE(0x1260, 0x3890) },
  37         /* 3COM 3CRWE154G72 Wireless LAN adapter */
  38         { PCI_DEVICE(0x10b7, 0x6001) },
  39         /* Intersil PRISM Indigo Wireless LAN adapter */
  40         { PCI_DEVICE(0x1260, 0x3877) },
  41         /* Intersil PRISM Javelin/Xbow Wireless LAN adapter */
  42         { PCI_DEVICE(0x1260, 0x3886) },
  43         { },
  44 };
  45
  46 MODULE_DEVICE_TABLE(pci, p54p_table);
  47
  48 static int p54p_upload_firmware(struct ieee80211_hw *dev)
  49 {
  50         struct p54p_priv *priv = dev->priv;
  51         __le32 reg;
  52         int err;
  53         __le32 *data;
  54         u32 remains, left, device_addr;
  55
  56         P54P_WRITE(int_enable, cpu_to_le32(0));
  57         P54P_READ(int_enable);
  58         udelay(10);
  59
  60         reg = P54P_READ(ctrl_stat);
  61         reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  62         reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RAMBOOT);
  63         P54P_WRITE(ctrl_stat, reg);
  64         P54P_READ(ctrl_stat);
  65         udelay(10);
  66
  67         reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
  68         P54P_WRITE(ctrl_stat, reg);
  69         wmb();
  70         udelay(10);
  71
  72         reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  73         P54P_WRITE(ctrl_stat, reg);
  74         wmb();
  75
  76         /* wait for the firmware to reset properly */
  77         mdelay(10);
  78
  79         err = p54_parse_firmware(dev, priv->firmware);
  80         if (err)
  81                 return err;
  82
  83         if (priv->common.fw_interface != FW_LM86) {
  84                 dev_err(&priv->pdev->dev, "wrong firmware, "
  85                         "please get a LM86(PCI) firmware a try again.\n");
  86                 return -EINVAL;
  87         }
  88
  89         data = (__le32 *) priv->firmware->data;
  90         remains = priv->firmware->size;
  91         device_addr = ISL38XX_DEV_FIRMWARE_ADDR;
  92         while (remains) {
  93                 u32 i = 0;
  94                 left = min((u32)0x1000, remains);
  95                 P54P_WRITE(direct_mem_base, cpu_to_le32(device_addr));
  96                 P54P_READ(int_enable);
  97
  98                 device_addr += 0x1000;
  99                 while (i < left) {
 100                         P54P_WRITE(direct_mem_win[i], *data++);
 101                         i += sizeof(u32);
 102                 }
 103
 104                 remains -= left;
 105                 P54P_READ(int_enable);
 106         }
 107
 108         reg = P54P_READ(ctrl_stat);
 109         reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_CLKRUN);
 110         reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
 111         reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RAMBOOT);
 112         P54P_WRITE(ctrl_stat, reg);
 113         P54P_READ(ctrl_stat);
 114         udelay(10);
 115
 116         reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
 117         P54P_WRITE(ctrl_stat, reg);
 118         wmb();
 119         udelay(10);
 120
 121         reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
 122         P54P_WRITE(ctrl_stat, reg);
 123         wmb();
 124         udelay(10);
 125
 126         /* wait for the firmware to boot properly */
 127         mdelay(100);
 128
 129         return 0;
 130 }
 131
 132 static void p54p_refill_rx_ring(struct ieee80211_hw *dev,
 133         int ring_index, struct p54p_desc *ring, u32 ring_limit,
 134         struct sk_buff **rx_buf)
 135 {
 136         struct p54p_priv *priv = dev->priv;
 137         struct p54p_ring_control *ring_control = priv->ring_control;
 138         u32 limit, idx, i;
 139
 140         idx = le32_to_cpu(ring_control->host_idx[ring_index]);
 141         limit = idx;
 142         limit -= le32_to_cpu(ring_control->device_idx[ring_index]);
 143         limit = ring_limit - limit;
 144
 145         i = idx % ring_limit;
 146         while (limit-- > 1) {
 147                 struct p54p_desc *desc = &ring[i];
 148
 149                 if (!desc->host_addr) {
 150                         struct sk_buff *skb;
 151                         dma_addr_t mapping;
 152                         skb = dev_alloc_skb(priv->common.rx_mtu + 32);
 153                         if (!skb)
 154                                 break;
 155
 156                         mapping = pci_map_single(priv->pdev,
 157                                                  skb_tail_pointer(skb),
 158                                                  priv->common.rx_mtu + 32,
 159                                                  PCI_DMA_FROMDEVICE);
 160
 161                         if (pci_dma_mapping_error(priv->pdev, mapping)) {
 162                                 dev_kfree_skb_any(skb);
 163                                 dev_err(&priv->pdev->dev,
 164                                         "RX DMA Mapping error\n");
 165                                 break;
 166                         }
 167
 168                         desc->host_addr = cpu_to_le32(mapping);
 169                         desc->device_addr = 0;  // FIXME: necessary?
 170                         desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
 171                         desc->flags = 0;
 172                         rx_buf[i] = skb;
 173                 }
 174
 175                 i++;
 176                 idx++;
 177                 i %= ring_limit;
 178         }
 179
 180         wmb();
 181         ring_control->host_idx[ring_index] = cpu_to_le32(idx);
 182 }
 183
 184 static void p54p_check_rx_ring(struct ieee80211_hw *dev, u32 *index,
 185         int ring_index, struct p54p_desc *ring, u32 ring_limit,
 186         struct sk_buff **rx_buf)
 187 {
 188         struct p54p_priv *priv = dev->priv;
 189         struct p54p_ring_control *ring_control = priv->ring_control;
 190         struct p54p_desc *desc;
 191         u32 idx, i;
 192
 193         i = (*index) % ring_limit;
 194         (*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
 195         idx %= ring_limit;
 196         while (i != idx) {
 197                 u16 len;
 198                 struct sk_buff *skb;
 199                 desc = &ring[i];
 200                 len = le16_to_cpu(desc->len);
 201                 skb = rx_buf[i];
 202
 203                 if (!skb) {
 204                         i++;
 205                         i %= ring_limit;
 206                         continue;
 207                 }
 208
 209                 if (unlikely(len > priv->common.rx_mtu)) {
 210                         if (net_ratelimit())
 211                                 dev_err(&priv->pdev->dev, "rx'd frame size "
 212                                         "exceeds length threshold.\n");
 213
 214                         len = priv->common.rx_mtu;
 215                 }
 216                 skb_put(skb, len);
 217
 218                 if (p54_rx(dev, skb)) {
 219                         pci_unmap_single(priv->pdev,
 220                                          le32_to_cpu(desc->host_addr),
 221                                          priv->common.rx_mtu + 32,
 222                                          PCI_DMA_FROMDEVICE);
 223                         rx_buf[i] = NULL;
 224                         desc->host_addr = 0;
 225                 } else {
 226                         skb_trim(skb, 0);
 227                         desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
 228                 }
 229
 230                 i++;
 231                 i %= ring_limit;
 232         }
 233
 234         p54p_refill_rx_ring(dev, ring_index, ring, ring_limit, rx_buf);
 235 }
 236
 237 static void p54p_check_tx_ring(struct ieee80211_hw *dev, u32 *index,
 238         int ring_index, struct p54p_desc *ring, u32 ring_limit,
 239         struct sk_buff **tx_buf)
 240 {
 241         unsigned long flags;
 242         struct p54p_priv *priv = dev->priv;
 243         struct p54p_ring_control *ring_control = priv->ring_control;
 244         struct p54p_desc *desc;
 245         struct sk_buff *skb;
 246         u32 idx, i;
 247
 248         i = (*index) % ring_limit;
 249         (*index) = idx = le32_to_cpu(ring_control->device_idx[1]);
 250         idx %= ring_limit;
 251
 252         spin_lock_irqsave(&priv->lock, flags);
 253         while (i != idx) {
 254                 desc = &ring[i];
 255
 256                 skb = tx_buf[i];
 257                 tx_buf[i] = NULL;
 258
 259                 pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr),
 260                                  le16_to_cpu(desc->len), PCI_DMA_TODEVICE);
 261
 262                 desc->host_addr = 0;
 263                 desc->device_addr = 0;
 264                 desc->len = 0;
 265                 desc->flags = 0;
 266
 267                 if (skb && FREE_AFTER_TX(skb)) {
 268                         spin_unlock_irqrestore(&priv->lock, flags);
 269                         p54_free_skb(dev, skb);
 270                         spin_lock_irqsave(&priv->lock, flags);
 271                 }
 272
 273                 i++;
 274                 i %= ring_limit;
 275         }
 276         spin_unlock_irqrestore(&priv->lock, flags);
 277 }
 278
 279 static void p54p_tasklet(unsigned long dev_id)
 280 {
 281         struct ieee80211_hw *dev = (struct ieee80211_hw *)dev_id;
 282         struct p54p_priv *priv = dev->priv;
 283         struct p54p_ring_control *ring_control = priv->ring_control;
 284
 285         p54p_check_tx_ring(dev, &priv->tx_idx_mgmt, 3, ring_control->tx_mgmt,
 286                            ARRAY_SIZE(ring_control->tx_mgmt),
 287                            priv->tx_buf_mgmt);
 288
 289         p54p_check_tx_ring(dev, &priv->tx_idx_data, 1, ring_control->tx_data,
 290                            ARRAY_SIZE(ring_control->tx_data),
 291                            priv->tx_buf_data);
 292
 293         p54p_check_rx_ring(dev, &priv->rx_idx_mgmt, 2, ring_control->rx_mgmt,
 294                 ARRAY_SIZE(ring_control->rx_mgmt), priv->rx_buf_mgmt);
 295
 296         p54p_check_rx_ring(dev, &priv->rx_idx_data, 0, ring_control->rx_data,
 297                 ARRAY_SIZE(ring_control->rx_data), priv->rx_buf_data);
 298
 299         wmb();
 300         P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
 301 }
 302
 303 static irqreturn_t p54p_interrupt(int irq, void *dev_id)
 304 {
 305         struct ieee80211_hw *dev = dev_id;
 306         struct p54p_priv *priv = dev->priv;
 307         __le32 reg;
 308
 309         spin_lock(&priv->lock);
 310         reg = P54P_READ(int_ident);
 311         if (unlikely(reg == cpu_to_le32(0xFFFFFFFF))) {
 312                 goto out;
 313         }
 314         P54P_WRITE(int_ack, reg);
 315
 316         reg &= P54P_READ(int_enable);
 317
 318         if (reg & cpu_to_le32(ISL38XX_INT_IDENT_UPDATE))
 319                 tasklet_schedule(&priv->tasklet);
 320         else if (reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT))
 321                 complete(&priv->boot_comp);
 322
 323 out:
 324         spin_unlock(&priv->lock);
 325         return reg ? IRQ_HANDLED : IRQ_NONE;
 326 }
 327
 328 static void p54p_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
 329 {
 330         struct p54p_priv *priv = dev->priv;
 331         struct p54p_ring_control *ring_control = priv->ring_control;
 332         unsigned long flags;
 333         struct p54p_desc *desc;
 334         dma_addr_t mapping;
 335         u32 device_idx, idx, i;
 336
 337         spin_lock_irqsave(&priv->lock, flags);
 338         device_idx = le32_to_cpu(ring_control->device_idx[1]);
 339         idx = le32_to_cpu(ring_control->host_idx[1]);
 340         i = idx % ARRAY_SIZE(ring_control->tx_data);
 341
 342         mapping = pci_map_single(priv->pdev, skb->data, skb->len,
 343                                  PCI_DMA_TODEVICE);
 344         if (pci_dma_mapping_error(priv->pdev, mapping)) {
 345                 spin_unlock_irqrestore(&priv->lock, flags);
 346                 p54_free_skb(dev, skb);
 347                 dev_err(&priv->pdev->dev, "TX DMA mapping error\n");
 348                 return ;
 349         }
 350         priv->tx_buf_data[i] = skb;
 351
 352         desc = &ring_control->tx_data[i];
 353         desc->host_addr = cpu_to_le32(mapping);
 354         desc->device_addr = ((struct p54_hdr *)skb->data)->req_id;
 355         desc->len = cpu_to_le16(skb->len);
 356         desc->flags = 0;
 357
 358         wmb();
 359         ring_control->host_idx[1] = cpu_to_le32(idx + 1);
 360         spin_unlock_irqrestore(&priv->lock, flags);
 361
 362         P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
 363         P54P_READ(dev_int);
 364 }
 365
 366 static void p54p_stop(struct ieee80211_hw *dev)
 367 {
 368         struct p54p_priv *priv = dev->priv;
 369         struct p54p_ring_control *ring_control = priv->ring_control;
 370         unsigned int i;
 371         struct p54p_desc *desc;
 372
 373         tasklet_kill(&priv->tasklet);
 374
 375         P54P_WRITE(int_enable, cpu_to_le32(0));
 376         P54P_READ(int_enable);
 377         udelay(10);
 378
 379         free_irq(priv->pdev->irq, dev);
 380
 381         P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
 382
 383         for (i = 0; i < ARRAY_SIZE(priv->rx_buf_data); i++) {
 384                 desc = &ring_control->rx_data[i];
 385                 if (desc->host_addr)
 386                         pci_unmap_single(priv->pdev,
 387                                          le32_to_cpu(desc->host_addr),
 388                                          priv->common.rx_mtu + 32,
 389                                          PCI_DMA_FROMDEVICE);
 390                 kfree_skb(priv->rx_buf_data[i]);
 391                 priv->rx_buf_data[i] = NULL;
 392         }
 393
 394         for (i = 0; i < ARRAY_SIZE(priv->rx_buf_mgmt); i++) {
 395                 desc = &ring_control->rx_mgmt[i];
 396                 if (desc->host_addr)
 397                         pci_unmap_single(priv->pdev,
 398                                          le32_to_cpu(desc->host_addr),
 399                                          priv->common.rx_mtu + 32,
 400                                          PCI_DMA_FROMDEVICE);
 401                 kfree_skb(priv->rx_buf_mgmt[i]);
 402                 priv->rx_buf_mgmt[i] = NULL;
 403         }
 404
 405         for (i = 0; i < ARRAY_SIZE(priv->tx_buf_data); i++) {
 406                 desc = &ring_control->tx_data[i];
 407                 if (desc->host_addr)
 408                         pci_unmap_single(priv->pdev,
 409                                          le32_to_cpu(desc->host_addr),
 410                                          le16_to_cpu(desc->len),
 411                                          PCI_DMA_TODEVICE);
 412
 413                 p54_free_skb(dev, priv->tx_buf_data[i]);
 414                 priv->tx_buf_data[i] = NULL;
 415         }
 416
 417         for (i = 0; i < ARRAY_SIZE(priv->tx_buf_mgmt); i++) {
 418                 desc = &ring_control->tx_mgmt[i];
 419                 if (desc->host_addr)
 420                         pci_unmap_single(priv->pdev,
 421                                          le32_to_cpu(desc->host_addr),
 422                                          le16_to_cpu(desc->len),
 423                                          PCI_DMA_TODEVICE);
 424
 425                 p54_free_skb(dev, priv->tx_buf_mgmt[i]);
 426                 priv->tx_buf_mgmt[i] = NULL;
 427         }
 428
 429         memset(ring_control, 0, sizeof(*ring_control));
 430 }
 431
 432 static int p54p_open(struct ieee80211_hw *dev)
 433 {
 434         struct p54p_priv *priv = dev->priv;
 435         int err;
 436
 437         init_completion(&priv->boot_comp);
 438         err = request_irq(priv->pdev->irq, p54p_interrupt,
 439                           IRQF_SHARED, "p54pci", dev);
 440         if (err) {
 441                 dev_err(&priv->pdev->dev, "failed to register IRQ handler\n");
 442                 return err;
 443         }
 444
 445         memset(priv->ring_control, 0, sizeof(*priv->ring_control));
 446         err = p54p_upload_firmware(dev);
 447         if (err) {
 448                 free_irq(priv->pdev->irq, dev);
 449                 return err;
 450         }
 451         priv->rx_idx_data = priv->tx_idx_data = 0;
 452         priv->rx_idx_mgmt = priv->tx_idx_mgmt = 0;
 453
 454         p54p_refill_rx_ring(dev, 0, priv->ring_control->rx_data,
 455                 ARRAY_SIZE(priv->ring_control->rx_data), priv->rx_buf_data);
 456
 457         p54p_refill_rx_ring(dev, 2, priv->ring_control->rx_mgmt,
 458                 ARRAY_SIZE(priv->ring_control->rx_mgmt), priv->rx_buf_mgmt);
 459
 460         P54P_WRITE(ring_control_base, cpu_to_le32(priv->ring_control_dma));
 461         P54P_READ(ring_control_base);
 462         wmb();
 463         udelay(10);
 464
 465         P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT));
 466         P54P_READ(int_enable);
 467         wmb();
 468         udelay(10);
 469
 470         P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
 471         P54P_READ(dev_int);
 472
 473         if (!wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ)) {
 474                 printk(KERN_ERR "%s: Cannot boot firmware!\n",
 475                        wiphy_name(dev->wiphy));
 476                 p54p_stop(dev);
 477                 return -ETIMEDOUT;
 478         }
 479
 480         P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE));
 481         P54P_READ(int_enable);
 482         wmb();
 483         udelay(10);
 484
 485         P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
 486         P54P_READ(dev_int);
 487         wmb();
 488         udelay(10);
 489
 490         return 0;
 491 }
 492
 493 static int __devinit p54p_probe(struct pci_dev *pdev,
 494                                 const struct pci_device_id *id)
 495 {
 496         struct p54p_priv *priv;
 497         struct ieee80211_hw *dev;
 498         unsigned long mem_addr, mem_len;
 499         int err;
 500
 501         err = pci_enable_device(pdev);
 502         if (err) {
 503                 dev_err(&pdev->dev, "Cannot enable new PCI device\n");
 504                 return err;
 505         }
 506
 507         mem_addr = pci_resource_start(pdev, 0);
 508         mem_len = pci_resource_len(pdev, 0);
 509         if (mem_len < sizeof(struct p54p_csr)) {
 510                 dev_err(&pdev->dev, "Too short PCI resources\n");
 511                 goto err_disable_dev;
 512         }
 513
 514         err = pci_request_regions(pdev, "p54pci");
 515         if (err) {
 516                 dev_err(&pdev->dev, "Cannot obtain PCI resources\n");
 517                 goto err_disable_dev;
 518         }
 519
 520         if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) ||
 521             pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
 522                 dev_err(&pdev->dev, "No suitable DMA available\n");
 523                 goto err_free_reg;
 524         }
 525
 526         pci_set_master(pdev);
 527         pci_try_set_mwi(pdev);
 528
 529         pci_write_config_byte(pdev, 0x40, 0);
 530         pci_write_config_byte(pdev, 0x41, 0);
 531
 532         dev = p54_init_common(sizeof(*priv));
 533         if (!dev) {
 534                 dev_err(&pdev->dev, "ieee80211 alloc failed\n");
 535                 err = -ENOMEM;
 536                 goto err_free_reg;
 537         }
 538
 539         priv = dev->priv;
 540         priv->pdev = pdev;
 541
 542         SET_IEEE80211_DEV(dev, &pdev->dev);
 543         pci_set_drvdata(pdev, dev);
 544
 545         priv->map = ioremap(mem_addr, mem_len);
 546         if (!priv->map) {
 547                 dev_err(&pdev->dev, "Cannot map device memory\n");
 548                 err = -ENOMEM;
 549                 goto err_free_dev;
 550         }
 551
 552         priv->ring_control = pci_alloc_consistent(pdev, sizeof(*priv->ring_control),
 553                                                   &priv->ring_control_dma);
 554         if (!priv->ring_control) {
 555                 dev_err(&pdev->dev, "Cannot allocate rings\n");
 556                 err = -ENOMEM;
 557                 goto err_iounmap;
 558         }
 559         priv->common.open = p54p_open;
 560         priv->common.stop = p54p_stop;
 561         priv->common.tx = p54p_tx;
 562
 563         spin_lock_init(&priv->lock);
 564         tasklet_init(&priv->tasklet, p54p_tasklet, (unsigned long)dev);
 565
 566         err = request_firmware(&priv->firmware, "isl3886pci",
 567                                &priv->pdev->dev);
 568         if (err) {
 569                 dev_err(&pdev->dev, "Cannot find firmware (isl3886pci)\n");
 570                 err = request_firmware(&priv->firmware, "isl3886",
 571                                        &priv->pdev->dev);
 572                 if (err)
 573                         goto err_free_common;
 574         }
 575
 576         err = p54p_open(dev);
 577         if (err)
 578                 goto err_free_common;
 579         err = p54_read_eeprom(dev);
 580         p54p_stop(dev);
 581         if (err)
 582                 goto err_free_common;
 583
 584         err = p54_register_common(dev, &pdev->dev);
 585         if (err)
 586                 goto err_free_common;
 587
 588         return 0;
 589
 590  err_free_common:
 591         release_firmware(priv->firmware);
 592         pci_free_consistent(pdev, sizeof(*priv->ring_control),
 593                             priv->ring_control, priv->ring_control_dma);
 594
 595  err_iounmap:
 596         iounmap(priv->map);
 597
 598  err_free_dev:
 599         pci_set_drvdata(pdev, NULL);
 600         p54_free_common(dev);
 601
 602  err_free_reg:
 603         pci_release_regions(pdev);
 604  err_disable_dev:
 605         pci_disable_device(pdev);
 606         return err;
 607 }
 608
 609 static void __devexit p54p_remove(struct pci_dev *pdev)
 610 {
 611         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
 612         struct p54p_priv *priv;
 613
 614         if (!dev)
 615                 return;
 616
 617         p54_unregister_common(dev);
 618         priv = dev->priv;
 619         release_firmware(priv->firmware);
 620         pci_free_consistent(pdev, sizeof(*priv->ring_control),
 621                             priv->ring_control, priv->ring_control_dma);
 622         iounmap(priv->map);
 623         pci_release_regions(pdev);
 624         pci_disable_device(pdev);
 625         p54_free_common(dev);
 626 }
 627
 628 #ifdef CONFIG_PM
 629 static int p54p_suspend(struct pci_dev *pdev, pm_message_t state)
 630 {
 631         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
 632         struct p54p_priv *priv = dev->priv;
 633
 634         if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
 635                 ieee80211_stop_queues(dev);
 636                 p54p_stop(dev);
 637         }
 638
 639         pci_save_state(pdev);
 640         pci_set_power_state(pdev, pci_choose_state(pdev, state));
 641         return 0;
 642 }
 643
 644 static int p54p_resume(struct pci_dev *pdev)
 645 {
 646         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
 647         struct p54p_priv *priv = dev->priv;
 648
 649         pci_set_power_state(pdev, PCI_D0);
 650         pci_restore_state(pdev);
 651
 652         if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
 653                 p54p_open(dev);
 654                 ieee80211_wake_queues(dev);
 655         }
 656
 657         return 0;
 658 }
 659 #endif /* CONFIG_PM */
 660
 661 static struct pci_driver p54p_driver = {
 662         .name           = "p54pci",
 663         .id_table       = p54p_table,
 664         .probe          = p54p_probe,
 665         .remove         = __devexit_p(p54p_remove),
 666 #ifdef CONFIG_PM
 667         .suspend        = p54p_suspend,
 668         .resume         = p54p_resume,
 669 #endif /* CONFIG_PM */
 670 };
 671
 672 static int __init p54p_init(void)
 673 {
 674         return pci_register_driver(&p54p_driver);
 675 }
 676
 677 static void __exit p54p_exit(void)
 678 {
 679         pci_unregister_driver(&p54p_driver);
 680 }
 681
 682 module_init(p54p_init);
 683 module_exit(p54p_exit);