Pileus Git - ~andy/linux/blob - drivers/net/wireless/iwlwifi/iwl-trans-pcie.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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  20  * along with this program; if not, write to the Free Software
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  27  * Contact Information:
  28  *  Intel Linux Wireless <ilw@linux.intel.com>
  29  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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  32  *
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  37  * modification, are permitted provided that the following conditions
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  41  *    notice, this list of conditions and the following disclaimer.
  42  *  * Redistributions in binary form must reproduce the above copyright
  43  *    notice, this list of conditions and the following disclaimer in
  44  *    the documentation and/or other materials provided with the
  45  *    distribution.
  46  *  * Neither the name Intel Corporation nor the names of its
  47  *    contributors may be used to endorse or promote products derived
  48  *    from this software without specific prior written permission.
  49  *
  50  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  55  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  56  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  57  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  58  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63 #include <linux/pci.h>
  64 #include <linux/pci-aspm.h>
  65 #include <linux/interrupt.h>
  66 #include <linux/debugfs.h>
  67 #include <linux/sched.h>
  68 #include <linux/bitops.h>
  69 #include <linux/gfp.h>
  70
  71 #include "iwl-trans.h"
  72 #include "iwl-trans-pcie-int.h"
  73 #include "iwl-csr.h"
  74 #include "iwl-prph.h"
  75 #include "iwl-shared.h"
  76 #include "iwl-eeprom.h"
  77 #include "iwl-agn-hw.h"
  78 #include "iwl-core.h"
  79
  80 static int iwl_trans_rx_alloc(struct iwl_trans *trans)
  81 {
  82         struct iwl_trans_pcie *trans_pcie =
  83                 IWL_TRANS_GET_PCIE_TRANS(trans);
  84         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
  85         struct device *dev = trans->dev;
  86
  87         memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
  88
  89         spin_lock_init(&rxq->lock);
  90
  91         if (WARN_ON(rxq->bd || rxq->rb_stts))
  92                 return -EINVAL;
  93
  94         /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
  95         rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
  96                                       &rxq->bd_dma, GFP_KERNEL);
  97         if (!rxq->bd)
  98                 goto err_bd;
  99
 100         /*Allocate the driver's pointer to receive buffer status */
 101         rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
 102                                            &rxq->rb_stts_dma, GFP_KERNEL);
 103         if (!rxq->rb_stts)
 104                 goto err_rb_stts;
 105
 106         return 0;
 107
 108 err_rb_stts:
 109         dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
 110                         rxq->bd, rxq->bd_dma);
 111         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 112         rxq->bd = NULL;
 113 err_bd:
 114         return -ENOMEM;
 115 }
 116
 117 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
 118 {
 119         struct iwl_trans_pcie *trans_pcie =
 120                 IWL_TRANS_GET_PCIE_TRANS(trans);
 121         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 122         int i;
 123
 124         /* Fill the rx_used queue with _all_ of the Rx buffers */
 125         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
 126                 /* In the reset function, these buffers may have been allocated
 127                  * to an SKB, so we need to unmap and free potential storage */
 128                 if (rxq->pool[i].page != NULL) {
 129                         dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
 130                                 PAGE_SIZE << hw_params(trans).rx_page_order,
 131                                 DMA_FROM_DEVICE);
 132                         __free_pages(rxq->pool[i].page,
 133                                      hw_params(trans).rx_page_order);
 134                         rxq->pool[i].page = NULL;
 135                 }
 136                 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
 137         }
 138 }
 139
 140 static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
 141                                  struct iwl_rx_queue *rxq)
 142 {
 143         u32 rb_size;
 144         const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
 145         u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */
 146
 147         if (iwlagn_mod_params.amsdu_size_8K)
 148                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
 149         else
 150                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 151
 152         /* Stop Rx DMA */
 153         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 154
 155         /* Reset driver's Rx queue write index */
 156         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 157
 158         /* Tell device where to find RBD circular buffer in DRAM */
 159         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 160                            (u32)(rxq->bd_dma >> 8));
 161
 162         /* Tell device where in DRAM to update its Rx status */
 163         iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
 164                            rxq->rb_stts_dma >> 4);
 165
 166         /* Enable Rx DMA
 167          * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
 168          *      the credit mechanism in 5000 HW RX FIFO
 169          * Direct rx interrupts to hosts
 170          * Rx buffer size 4 or 8k
 171          * RB timeout 0x10
 172          * 256 RBDs
 173          */
 174         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
 175                            FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
 176                            FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
 177                            FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
 178                            FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
 179                            rb_size|
 180                            (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
 181                            (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
 182
 183         /* Set interrupt coalescing timer to default (2048 usecs) */
 184         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 185 }
 186
 187 static int iwl_rx_init(struct iwl_trans *trans)
 188 {
 189         struct iwl_trans_pcie *trans_pcie =
 190                 IWL_TRANS_GET_PCIE_TRANS(trans);
 191         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 192
 193         int i, err;
 194         unsigned long flags;
 195
 196         if (!rxq->bd) {
 197                 err = iwl_trans_rx_alloc(trans);
 198                 if (err)
 199                         return err;
 200         }
 201
 202         spin_lock_irqsave(&rxq->lock, flags);
 203         INIT_LIST_HEAD(&rxq->rx_free);
 204         INIT_LIST_HEAD(&rxq->rx_used);
 205
 206         iwl_trans_rxq_free_rx_bufs(trans);
 207
 208         for (i = 0; i < RX_QUEUE_SIZE; i++)
 209                 rxq->queue[i] = NULL;
 210
 211         /* Set us so that we have processed and used all buffers, but have
 212          * not restocked the Rx queue with fresh buffers */
 213         rxq->read = rxq->write = 0;
 214         rxq->write_actual = 0;
 215         rxq->free_count = 0;
 216         spin_unlock_irqrestore(&rxq->lock, flags);
 217
 218         iwlagn_rx_replenish(trans);
 219
 220         iwl_trans_rx_hw_init(trans, rxq);
 221
 222         spin_lock_irqsave(&trans->shrd->lock, flags);
 223         rxq->need_update = 1;
 224         iwl_rx_queue_update_write_ptr(trans, rxq);
 225         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 226
 227         return 0;
 228 }
 229
 230 static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
 231 {
 232         struct iwl_trans_pcie *trans_pcie =
 233                 IWL_TRANS_GET_PCIE_TRANS(trans);
 234         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 235
 236         unsigned long flags;
 237
 238         /*if rxq->bd is NULL, it means that nothing has been allocated,
 239          * exit now */
 240         if (!rxq->bd) {
 241                 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
 242                 return;
 243         }
 244
 245         spin_lock_irqsave(&rxq->lock, flags);
 246         iwl_trans_rxq_free_rx_bufs(trans);
 247         spin_unlock_irqrestore(&rxq->lock, flags);
 248
 249         dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
 250                           rxq->bd, rxq->bd_dma);
 251         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 252         rxq->bd = NULL;
 253
 254         if (rxq->rb_stts)
 255                 dma_free_coherent(trans->dev,
 256                                   sizeof(struct iwl_rb_status),
 257                                   rxq->rb_stts, rxq->rb_stts_dma);
 258         else
 259                 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
 260         memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
 261         rxq->rb_stts = NULL;
 262 }
 263
 264 static int iwl_trans_rx_stop(struct iwl_trans *trans)
 265 {
 266
 267         /* stop Rx DMA */
 268         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 269         return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
 270                             FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
 271 }
 272
 273 static inline int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
 274                                     struct iwl_dma_ptr *ptr, size_t size)
 275 {
 276         if (WARN_ON(ptr->addr))
 277                 return -EINVAL;
 278
 279         ptr->addr = dma_alloc_coherent(trans->dev, size,
 280                                        &ptr->dma, GFP_KERNEL);
 281         if (!ptr->addr)
 282                 return -ENOMEM;
 283         ptr->size = size;
 284         return 0;
 285 }
 286
 287 static inline void iwlagn_free_dma_ptr(struct iwl_trans *trans,
 288                                     struct iwl_dma_ptr *ptr)
 289 {
 290         if (unlikely(!ptr->addr))
 291                 return;
 292
 293         dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
 294         memset(ptr, 0, sizeof(*ptr));
 295 }
 296
 297 static int iwl_trans_txq_alloc(struct iwl_trans *trans,
 298                                 struct iwl_tx_queue *txq, int slots_num,
 299                                 u32 txq_id)
 300 {
 301         size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
 302         int i;
 303
 304         if (WARN_ON(txq->meta || txq->cmd || txq->skbs || txq->tfds))
 305                 return -EINVAL;
 306
 307         txq->q.n_window = slots_num;
 308
 309         txq->meta = kcalloc(slots_num, sizeof(txq->meta[0]), GFP_KERNEL);
 310         txq->cmd = kcalloc(slots_num, sizeof(txq->cmd[0]), GFP_KERNEL);
 311
 312         if (!txq->meta || !txq->cmd)
 313                 goto error;
 314
 315         if (txq_id == trans->shrd->cmd_queue)
 316                 for (i = 0; i < slots_num; i++) {
 317                         txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd),
 318                                                 GFP_KERNEL);
 319                         if (!txq->cmd[i])
 320                                 goto error;
 321                 }
 322
 323         /* Alloc driver data array and TFD circular buffer */
 324         /* Driver private data, only for Tx (not command) queues,
 325          * not shared with device. */
 326         if (txq_id != trans->shrd->cmd_queue) {
 327                 txq->skbs = kcalloc(TFD_QUEUE_SIZE_MAX, sizeof(txq->skbs[0]),
 328                                     GFP_KERNEL);
 329                 if (!txq->skbs) {
 330                         IWL_ERR(trans, "kmalloc for auxiliary BD "
 331                                   "structures failed\n");
 332                         goto error;
 333                 }
 334         } else {
 335                 txq->skbs = NULL;
 336         }
 337
 338         /* Circular buffer of transmit frame descriptors (TFDs),
 339          * shared with device */
 340         txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
 341                                        &txq->q.dma_addr, GFP_KERNEL);
 342         if (!txq->tfds) {
 343                 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
 344                 goto error;
 345         }
 346         txq->q.id = txq_id;
 347
 348         return 0;
 349 error:
 350         kfree(txq->skbs);
 351         txq->skbs = NULL;
 352         /* since txq->cmd has been zeroed,
 353          * all non allocated cmd[i] will be NULL */
 354         if (txq->cmd && txq_id == trans->shrd->cmd_queue)
 355                 for (i = 0; i < slots_num; i++)
 356                         kfree(txq->cmd[i]);
 357         kfree(txq->meta);
 358         kfree(txq->cmd);
 359         txq->meta = NULL;
 360         txq->cmd = NULL;
 361
 362         return -ENOMEM;
 363
 364 }
 365
 366 static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
 367                       int slots_num, u32 txq_id)
 368 {
 369         int ret;
 370
 371         txq->need_update = 0;
 372         memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num);
 373
 374         /*
 375          * For the default queues 0-3, set up the swq_id
 376          * already -- all others need to get one later
 377          * (if they need one at all).
 378          */
 379         if (txq_id < 4)
 380                 iwl_set_swq_id(txq, txq_id, txq_id);
 381
 382         /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
 383          * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
 384         BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
 385
 386         /* Initialize queue's high/low-water marks, and head/tail indexes */
 387         ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
 388                         txq_id);
 389         if (ret)
 390                 return ret;
 391
 392         /*
 393          * Tell nic where to find circular buffer of Tx Frame Descriptors for
 394          * given Tx queue, and enable the DMA channel used for that queue.
 395          * Circular buffer (TFD queue in DRAM) physical base address */
 396         iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
 397                              txq->q.dma_addr >> 8);
 398
 399         return 0;
 400 }
 401
 402 /**
 403  * iwl_tx_queue_unmap -  Unmap any remaining DMA mappings and free skb's
 404  */
 405 static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
 406 {
 407         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 408         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 409         struct iwl_queue *q = &txq->q;
 410         enum dma_data_direction dma_dir;
 411         unsigned long flags;
 412         spinlock_t *lock;
 413
 414         if (!q->n_bd)
 415                 return;
 416
 417         /* In the command queue, all the TBs are mapped as BIDI
 418          * so unmap them as such.
 419          */
 420         if (txq_id == trans->shrd->cmd_queue) {
 421                 dma_dir = DMA_BIDIRECTIONAL;
 422                 lock = &trans->hcmd_lock;
 423         } else {
 424                 dma_dir = DMA_TO_DEVICE;
 425                 lock = &trans->shrd->sta_lock;
 426         }
 427
 428         spin_lock_irqsave(lock, flags);
 429         while (q->write_ptr != q->read_ptr) {
 430                 /* The read_ptr needs to bound by q->n_window */
 431                 iwlagn_txq_free_tfd(trans, txq, get_cmd_index(q, q->read_ptr),
 432                                     dma_dir);
 433                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
 434         }
 435         spin_unlock_irqrestore(lock, flags);
 436 }
 437
 438 /**
 439  * iwl_tx_queue_free - Deallocate DMA queue.
 440  * @txq: Transmit queue to deallocate.
 441  *
 442  * Empty queue by removing and destroying all BD's.
 443  * Free all buffers.
 444  * 0-fill, but do not free "txq" descriptor structure.
 445  */
 446 static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
 447 {
 448         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 449         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 450         struct device *dev = trans->dev;
 451         int i;
 452         if (WARN_ON(!txq))
 453                 return;
 454
 455         iwl_tx_queue_unmap(trans, txq_id);
 456
 457         /* De-alloc array of command/tx buffers */
 458
 459         if (txq_id == trans->shrd->cmd_queue)
 460                 for (i = 0; i < txq->q.n_window; i++)
 461                         kfree(txq->cmd[i]);
 462
 463         /* De-alloc circular buffer of TFDs */
 464         if (txq->q.n_bd) {
 465                 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
 466                                   txq->q.n_bd, txq->tfds, txq->q.dma_addr);
 467                 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
 468         }
 469
 470         /* De-alloc array of per-TFD driver data */
 471         kfree(txq->skbs);
 472         txq->skbs = NULL;
 473
 474         /* deallocate arrays */
 475         kfree(txq->cmd);
 476         kfree(txq->meta);
 477         txq->cmd = NULL;
 478         txq->meta = NULL;
 479
 480         /* 0-fill queue descriptor structure */
 481         memset(txq, 0, sizeof(*txq));
 482 }
 483
 484 /**
 485  * iwl_trans_tx_free - Free TXQ Context
 486  *
 487  * Destroy all TX DMA queues and structures
 488  */
 489 static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
 490 {
 491         int txq_id;
 492         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 493
 494         /* Tx queues */
 495         if (trans_pcie->txq) {
 496                 for (txq_id = 0;
 497                      txq_id < hw_params(trans).max_txq_num; txq_id++)
 498                         iwl_tx_queue_free(trans, txq_id);
 499         }
 500
 501         kfree(trans_pcie->txq);
 502         trans_pcie->txq = NULL;
 503
 504         iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
 505
 506         iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
 507 }
 508
 509 /**
 510  * iwl_trans_tx_alloc - allocate TX context
 511  * Allocate all Tx DMA structures and initialize them
 512  *
 513  * @param priv
 514  * @return error code
 515  */
 516 static int iwl_trans_tx_alloc(struct iwl_trans *trans)
 517 {
 518         int ret;
 519         int txq_id, slots_num;
 520         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 521
 522         u16 scd_bc_tbls_size = hw_params(trans).max_txq_num *
 523                         sizeof(struct iwlagn_scd_bc_tbl);
 524
 525         /*It is not allowed to alloc twice, so warn when this happens.
 526          * We cannot rely on the previous allocation, so free and fail */
 527         if (WARN_ON(trans_pcie->txq)) {
 528                 ret = -EINVAL;
 529                 goto error;
 530         }
 531
 532         ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
 533                                    scd_bc_tbls_size);
 534         if (ret) {
 535                 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
 536                 goto error;
 537         }
 538
 539         /* Alloc keep-warm buffer */
 540         ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
 541         if (ret) {
 542                 IWL_ERR(trans, "Keep Warm allocation failed\n");
 543                 goto error;
 544         }
 545
 546         trans_pcie->txq = kcalloc(hw_params(trans).max_txq_num,
 547                                   sizeof(struct iwl_tx_queue), GFP_KERNEL);
 548         if (!trans_pcie->txq) {
 549                 IWL_ERR(trans, "Not enough memory for txq\n");
 550                 ret = ENOMEM;
 551                 goto error;
 552         }
 553
 554         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 555         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
 556                 slots_num = (txq_id == trans->shrd->cmd_queue) ?
 557                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 558                 ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id],
 559                                           slots_num, txq_id);
 560                 if (ret) {
 561                         IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
 562                         goto error;
 563                 }
 564         }
 565
 566         return 0;
 567
 568 error:
 569         iwl_trans_pcie_tx_free(trans);
 570
 571         return ret;
 572 }
 573 static int iwl_tx_init(struct iwl_trans *trans)
 574 {
 575         int ret;
 576         int txq_id, slots_num;
 577         unsigned long flags;
 578         bool alloc = false;
 579         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 580
 581         if (!trans_pcie->txq) {
 582                 ret = iwl_trans_tx_alloc(trans);
 583                 if (ret)
 584                         goto error;
 585                 alloc = true;
 586         }
 587
 588         spin_lock_irqsave(&trans->shrd->lock, flags);
 589
 590         /* Turn off all Tx DMA fifos */
 591         iwl_write_prph(trans, SCD_TXFACT, 0);
 592
 593         /* Tell NIC where to find the "keep warm" buffer */
 594         iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
 595                            trans_pcie->kw.dma >> 4);
 596
 597         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 598
 599         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 600         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
 601                 slots_num = (txq_id == trans->shrd->cmd_queue) ?
 602                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 603                 ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id],
 604                                          slots_num, txq_id);
 605                 if (ret) {
 606                         IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
 607                         goto error;
 608                 }
 609         }
 610
 611         return 0;
 612 error:
 613         /*Upon error, free only if we allocated something */
 614         if (alloc)
 615                 iwl_trans_pcie_tx_free(trans);
 616         return ret;
 617 }
 618
 619 static void iwl_set_pwr_vmain(struct iwl_trans *trans)
 620 {
 621 /*
 622  * (for documentation purposes)
 623  * to set power to V_AUX, do:
 624
 625                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
 626                         iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 627                                                APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 628                                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 629  */
 630
 631         iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 632                                APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 633                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 634 }
 635
 636 /*
 637  * Start up NIC's basic functionality after it has been reset
 638  * (e.g. after platform boot, or shutdown via iwl_apm_stop())
 639  * NOTE:  This does not load uCode nor start the embedded processor
 640  */
 641 static int iwl_apm_init(struct iwl_trans *trans)
 642 {
 643         int ret = 0;
 644         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 645
 646         /*
 647          * Use "set_bit" below rather than "write", to preserve any hardware
 648          * bits already set by default after reset.
 649          */
 650
 651         /* Disable L0S exit timer (platform NMI Work/Around) */
 652         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 653                           CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 654
 655         /*
 656          * Disable L0s without affecting L1;
 657          *  don't wait for ICH L0s (ICH bug W/A)
 658          */
 659         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 660                           CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 661
 662         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 663         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 664
 665         /*
 666          * Enable HAP INTA (interrupt from management bus) to
 667          * wake device's PCI Express link L1a -> L0s
 668          */
 669         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 670                                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 671
 672         bus_apm_config(bus(trans));
 673
 674         /* Configure analog phase-lock-loop before activating to D0A */
 675         if (cfg(trans)->base_params->pll_cfg_val)
 676                 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
 677                             cfg(trans)->base_params->pll_cfg_val);
 678
 679         /*
 680          * Set "initialization complete" bit to move adapter from
 681          * D0U* --> D0A* (powered-up active) state.
 682          */
 683         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 684
 685         /*
 686          * Wait for clock stabilization; once stabilized, access to
 687          * device-internal resources is supported, e.g. iwl_write_prph()
 688          * and accesses to uCode SRAM.
 689          */
 690         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 691                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 692                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 693         if (ret < 0) {
 694                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 695                 goto out;
 696         }
 697
 698         /*
 699          * Enable DMA clock and wait for it to stabilize.
 700          *
 701          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
 702          * do not disable clocks.  This preserves any hardware bits already
 703          * set by default in "CLK_CTRL_REG" after reset.
 704          */
 705         iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 706         udelay(20);
 707
 708         /* Disable L1-Active */
 709         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 710                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 711
 712         set_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status);
 713
 714 out:
 715         return ret;
 716 }
 717
 718 static int iwl_apm_stop_master(struct iwl_trans *trans)
 719 {
 720         int ret = 0;
 721
 722         /* stop device's busmaster DMA activity */
 723         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 724
 725         ret = iwl_poll_bit(trans, CSR_RESET,
 726                         CSR_RESET_REG_FLAG_MASTER_DISABLED,
 727                         CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 728         if (ret)
 729                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 730
 731         IWL_DEBUG_INFO(trans, "stop master\n");
 732
 733         return ret;
 734 }
 735
 736 static void iwl_apm_stop(struct iwl_trans *trans)
 737 {
 738         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 739
 740         clear_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status);
 741
 742         /* Stop device's DMA activity */
 743         iwl_apm_stop_master(trans);
 744
 745         /* Reset the entire device */
 746         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 747
 748         udelay(10);
 749
 750         /*
 751          * Clear "initialization complete" bit to move adapter from
 752          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 753          */
 754         iwl_clear_bit(trans, CSR_GP_CNTRL,
 755                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 756 }
 757
 758 static int iwl_nic_init(struct iwl_trans *trans)
 759 {
 760         unsigned long flags;
 761
 762         /* nic_init */
 763         spin_lock_irqsave(&trans->shrd->lock, flags);
 764         iwl_apm_init(trans);
 765
 766         /* Set interrupt coalescing calibration timer to default (512 usecs) */
 767         iwl_write8(trans, CSR_INT_COALESCING,
 768                 IWL_HOST_INT_CALIB_TIMEOUT_DEF);
 769
 770         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 771
 772         iwl_set_pwr_vmain(trans);
 773
 774         iwl_nic_config(priv(trans));
 775
 776 #ifndef CONFIG_IWLWIFI_IDI
 777         /* Allocate the RX queue, or reset if it is already allocated */
 778         iwl_rx_init(trans);
 779 #endif
 780
 781         /* Allocate or reset and init all Tx and Command queues */
 782         if (iwl_tx_init(trans))
 783                 return -ENOMEM;
 784
 785         if (hw_params(trans).shadow_reg_enable) {
 786                 /* enable shadow regs in HW */
 787                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL,
 788                         0x800FFFFF);
 789         }
 790
 791         set_bit(STATUS_INIT, &trans->shrd->status);
 792
 793         return 0;
 794 }
 795
 796 #define HW_READY_TIMEOUT (50)
 797
 798 /* Note: returns poll_bit return value, which is >= 0 if success */
 799 static int iwl_set_hw_ready(struct iwl_trans *trans)
 800 {
 801         int ret;
 802
 803         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 804                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 805
 806         /* See if we got it */
 807         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 808                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 809                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 810                                 HW_READY_TIMEOUT);
 811
 812         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 813         return ret;
 814 }
 815
 816 /* Note: returns standard 0/-ERROR code */
 817 static int iwl_prepare_card_hw(struct iwl_trans *trans)
 818 {
 819         int ret;
 820
 821         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 822
 823         ret = iwl_set_hw_ready(trans);
 824         /* If the card is ready, exit 0 */
 825         if (ret >= 0)
 826                 return 0;
 827
 828         /* If HW is not ready, prepare the conditions to check again */
 829         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 830                         CSR_HW_IF_CONFIG_REG_PREPARE);
 831
 832         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 833                         ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
 834                         CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
 835
 836         if (ret < 0)
 837                 return ret;
 838
 839         /* HW should be ready by now, check again. */
 840         ret = iwl_set_hw_ready(trans);
 841         if (ret >= 0)
 842                 return 0;
 843         return ret;
 844 }
 845
 846 #define IWL_AC_UNSET -1
 847
 848 struct queue_to_fifo_ac {
 849         s8 fifo, ac;
 850 };
 851
 852 static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = {
 853         { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
 854         { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
 855         { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
 856         { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
 857         { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
 858         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 859         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 860         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 861         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 862         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 863         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 864 };
 865
 866 static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = {
 867         { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
 868         { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
 869         { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
 870         { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
 871         { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, },
 872         { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, },
 873         { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, },
 874         { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, },
 875         { IWL_TX_FIFO_BE_IPAN, 2, },
 876         { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
 877         { IWL_TX_FIFO_AUX, IWL_AC_UNSET, },
 878 };
 879
 880 static const u8 iwlagn_bss_ac_to_fifo[] = {
 881         IWL_TX_FIFO_VO,
 882         IWL_TX_FIFO_VI,
 883         IWL_TX_FIFO_BE,
 884         IWL_TX_FIFO_BK,
 885 };
 886 static const u8 iwlagn_bss_ac_to_queue[] = {
 887         0, 1, 2, 3,
 888 };
 889 static const u8 iwlagn_pan_ac_to_fifo[] = {
 890         IWL_TX_FIFO_VO_IPAN,
 891         IWL_TX_FIFO_VI_IPAN,
 892         IWL_TX_FIFO_BE_IPAN,
 893         IWL_TX_FIFO_BK_IPAN,
 894 };
 895 static const u8 iwlagn_pan_ac_to_queue[] = {
 896         7, 6, 5, 4,
 897 };
 898
 899 /*
 900  * ucode
 901  */
 902 static int iwl_load_section(struct iwl_trans *trans, const char *name,
 903                                 struct fw_desc *image, u32 dst_addr)
 904 {
 905         dma_addr_t phy_addr = image->p_addr;
 906         u32 byte_cnt = image->len;
 907         int ret;
 908
 909         trans->ucode_write_complete = 0;
 910
 911         iwl_write_direct32(trans,
 912                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 913                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 914
 915         iwl_write_direct32(trans,
 916                 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
 917
 918         iwl_write_direct32(trans,
 919                 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 920                 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 921
 922         iwl_write_direct32(trans,
 923                 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 924                 (iwl_get_dma_hi_addr(phy_addr)
 925                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 926
 927         iwl_write_direct32(trans,
 928                 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 929                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 930                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 931                 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 932
 933         iwl_write_direct32(trans,
 934                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 935                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE       |
 936                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE    |
 937                 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 938
 939         IWL_DEBUG_FW(trans, "%s uCode section being loaded...\n", name);
 940         ret = wait_event_timeout(trans->shrd->wait_command_queue,
 941                                  trans->ucode_write_complete, 5 * HZ);
 942         if (!ret) {
 943                 IWL_ERR(trans, "Could not load the %s uCode section\n",
 944                         name);
 945                 return -ETIMEDOUT;
 946         }
 947
 948         return 0;
 949 }
 950
 951 static int iwl_load_given_ucode(struct iwl_trans *trans, struct fw_img *image)
 952 {
 953         int ret = 0;
 954
 955         ret = iwl_load_section(trans, "INST", &image->code,
 956                                    IWLAGN_RTC_INST_LOWER_BOUND);
 957         if (ret)
 958                 return ret;
 959
 960         ret = iwl_load_section(trans, "DATA", &image->data,
 961                                     IWLAGN_RTC_DATA_LOWER_BOUND);
 962         if (ret)
 963                 return ret;
 964
 965         /* Remove all resets to allow NIC to operate */
 966         iwl_write32(trans, CSR_RESET, 0);
 967
 968         return 0;
 969 }
 970
 971 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, struct fw_img *fw)
 972 {
 973         int ret;
 974         struct iwl_trans_pcie *trans_pcie =
 975                 IWL_TRANS_GET_PCIE_TRANS(trans);
 976
 977         trans->shrd->ucode_owner = IWL_OWNERSHIP_DRIVER;
 978         trans_pcie->ac_to_queue[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_queue;
 979         trans_pcie->ac_to_queue[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_queue;
 980
 981         trans_pcie->ac_to_fifo[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_fifo;
 982         trans_pcie->ac_to_fifo[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_fifo;
 983
 984         trans_pcie->mcast_queue[IWL_RXON_CTX_BSS] = 0;
 985         trans_pcie->mcast_queue[IWL_RXON_CTX_PAN] = IWL_IPAN_MCAST_QUEUE;
 986
 987         if ((hw_params(trans).sku & EEPROM_SKU_CAP_AMT_ENABLE) &&
 988              iwl_prepare_card_hw(trans)) {
 989                 IWL_WARN(trans, "Exit HW not ready\n");
 990                 return -EIO;
 991         }
 992
 993         /* If platform's RF_KILL switch is NOT set to KILL */
 994         if (iwl_read32(trans, CSR_GP_CNTRL) &
 995                         CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
 996                 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
 997         else
 998                 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
 999
1000         if (iwl_is_rfkill(trans->shrd)) {
1001                 iwl_set_hw_rfkill_state(priv(trans), true);
1002                 iwl_enable_interrupts(trans);
1003                 return -ERFKILL;
1004         }
1005
1006         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1007
1008         ret = iwl_nic_init(trans);
1009         if (ret) {
1010                 IWL_ERR(trans, "Unable to init nic\n");
1011                 return ret;
1012         }
1013
1014         /* make sure rfkill handshake bits are cleared */
1015         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1016         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1017                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1018
1019         /* clear (again), then enable host interrupts */
1020         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1021         iwl_enable_interrupts(trans);
1022
1023         /* really make sure rfkill handshake bits are cleared */
1024         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1025         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1026
1027         /* Load the given image to the HW */
1028         iwl_load_given_ucode(trans, fw);
1029
1030         return 0;
1031 }
1032
1033 /*
1034  * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1035  * must be called under priv->shrd->lock and mac access
1036  */
1037 static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
1038 {
1039         iwl_write_prph(trans, SCD_TXFACT, mask);
1040 }
1041
1042 static void iwl_tx_start(struct iwl_trans *trans)
1043 {
1044         const struct queue_to_fifo_ac *queue_to_fifo;
1045         struct iwl_trans_pcie *trans_pcie =
1046                 IWL_TRANS_GET_PCIE_TRANS(trans);
1047         u32 a;
1048         unsigned long flags;
1049         int i, chan;
1050         u32 reg_val;
1051
1052         spin_lock_irqsave(&trans->shrd->lock, flags);
1053
1054         trans_pcie->scd_base_addr =
1055                 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
1056         a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
1057         /* reset conext data memory */
1058         for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
1059                 a += 4)
1060                 iwl_write_targ_mem(trans, a, 0);
1061         /* reset tx status memory */
1062         for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
1063                 a += 4)
1064                 iwl_write_targ_mem(trans, a, 0);
1065         for (; a < trans_pcie->scd_base_addr +
1066                SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(trans).max_txq_num);
1067                a += 4)
1068                 iwl_write_targ_mem(trans, a, 0);
1069
1070         iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
1071                        trans_pcie->scd_bc_tbls.dma >> 10);
1072
1073         /* Enable DMA channel */
1074         for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
1075                 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
1076                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1077                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
1078
1079         /* Update FH chicken bits */
1080         reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
1081         iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
1082                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
1083
1084         iwl_write_prph(trans, SCD_QUEUECHAIN_SEL,
1085                 SCD_QUEUECHAIN_SEL_ALL(trans));
1086         iwl_write_prph(trans, SCD_AGGR_SEL, 0);
1087
1088         /* initiate the queues */
1089         for (i = 0; i < hw_params(trans).max_txq_num; i++) {
1090                 iwl_write_prph(trans, SCD_QUEUE_RDPTR(i), 0);
1091                 iwl_write_direct32(trans, HBUS_TARG_WRPTR, 0 | (i << 8));
1092                 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
1093                                 SCD_CONTEXT_QUEUE_OFFSET(i), 0);
1094                 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
1095                                 SCD_CONTEXT_QUEUE_OFFSET(i) +
1096                                 sizeof(u32),
1097                                 ((SCD_WIN_SIZE <<
1098                                 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1099                                 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1100                                 ((SCD_FRAME_LIMIT <<
1101                                 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1102                                 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1103         }
1104
1105         iwl_write_prph(trans, SCD_INTERRUPT_MASK,
1106                         IWL_MASK(0, hw_params(trans).max_txq_num));
1107
1108         /* Activate all Tx DMA/FIFO channels */
1109         iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
1110
1111         /* map queues to FIFOs */
1112         if (trans->shrd->valid_contexts != BIT(IWL_RXON_CTX_BSS))
1113                 queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo;
1114         else
1115                 queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
1116
1117         iwl_trans_set_wr_ptrs(trans, trans->shrd->cmd_queue, 0);
1118
1119         /* make sure all queue are not stopped */
1120         memset(&trans_pcie->queue_stopped[0], 0,
1121                 sizeof(trans_pcie->queue_stopped));
1122         for (i = 0; i < 4; i++)
1123                 atomic_set(&trans_pcie->queue_stop_count[i], 0);
1124
1125         /* reset to 0 to enable all the queue first */
1126         trans_pcie->txq_ctx_active_msk = 0;
1127
1128         BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) <
1129                                                 IWLAGN_FIRST_AMPDU_QUEUE);
1130         BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) <
1131                                                 IWLAGN_FIRST_AMPDU_QUEUE);
1132
1133         for (i = 0; i < IWLAGN_FIRST_AMPDU_QUEUE; i++) {
1134                 int fifo = queue_to_fifo[i].fifo;
1135                 int ac = queue_to_fifo[i].ac;
1136
1137                 iwl_txq_ctx_activate(trans_pcie, i);
1138
1139                 if (fifo == IWL_TX_FIFO_UNUSED)
1140                         continue;
1141
1142                 if (ac != IWL_AC_UNSET)
1143                         iwl_set_swq_id(&trans_pcie->txq[i], ac, i);
1144                 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[i],
1145                                               fifo, 0);
1146         }
1147
1148         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1149
1150         /* Enable L1-Active */
1151         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
1152                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1153 }
1154
1155 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans)
1156 {
1157         iwl_reset_ict(trans);
1158         iwl_tx_start(trans);
1159 }
1160
1161 /**
1162  * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
1163  */
1164 static int iwl_trans_tx_stop(struct iwl_trans *trans)
1165 {
1166         int ch, txq_id;
1167         unsigned long flags;
1168         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1169
1170         /* Turn off all Tx DMA fifos */
1171         spin_lock_irqsave(&trans->shrd->lock, flags);
1172
1173         iwl_trans_txq_set_sched(trans, 0);
1174
1175         /* Stop each Tx DMA channel, and wait for it to be idle */
1176         for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
1177                 iwl_write_direct32(trans,
1178                                    FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
1179                 if (iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG,
1180                                     FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
1181                                     1000))
1182                         IWL_ERR(trans, "Failing on timeout while stopping"
1183                             " DMA channel %d [0x%08x]", ch,
1184                             iwl_read_direct32(trans,
1185                                               FH_TSSR_TX_STATUS_REG));
1186         }
1187         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1188
1189         if (!trans_pcie->txq) {
1190                 IWL_WARN(trans, "Stopping tx queues that aren't allocated...");
1191                 return 0;
1192         }
1193
1194         /* Unmap DMA from host system and free skb's */
1195         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++)
1196                 iwl_tx_queue_unmap(trans, txq_id);
1197
1198         return 0;
1199 }
1200
1201 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1202 {
1203         unsigned long flags;
1204         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1205
1206         /* tell the device to stop sending interrupts */
1207         spin_lock_irqsave(&trans->shrd->lock, flags);
1208         iwl_disable_interrupts(trans);
1209         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1210
1211         /* device going down, Stop using ICT table */
1212         iwl_disable_ict(trans);
1213
1214         /*
1215          * If a HW restart happens during firmware loading,
1216          * then the firmware loading might call this function
1217          * and later it might be called again due to the
1218          * restart. So don't process again if the device is
1219          * already dead.
1220          */
1221         if (test_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status)) {
1222                 iwl_trans_tx_stop(trans);
1223 #ifndef CONFIG_IWLWIFI_IDI
1224                 iwl_trans_rx_stop(trans);
1225 #endif
1226                 /* Power-down device's busmaster DMA clocks */
1227                 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1228                                APMG_CLK_VAL_DMA_CLK_RQT);
1229                 udelay(5);
1230         }
1231
1232         /* Make sure (redundant) we've released our request to stay awake */
1233         iwl_clear_bit(trans, CSR_GP_CNTRL,
1234                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1235
1236         /* Stop the device, and put it in low power state */
1237         iwl_apm_stop(trans);
1238
1239         /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1240          * Clean again the interrupt here
1241          */
1242         spin_lock_irqsave(&trans->shrd->lock, flags);
1243         iwl_disable_interrupts(trans);
1244         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1245
1246         /* wait to make sure we flush pending tasklet*/
1247         synchronize_irq(trans->irq);
1248         tasklet_kill(&trans_pcie->irq_tasklet);
1249
1250         /* stop and reset the on-board processor */
1251         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1252 }
1253
1254 static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1255                 struct iwl_device_cmd *dev_cmd, enum iwl_rxon_context_id ctx,
1256                 u8 sta_id, u8 tid)
1257 {
1258         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1259         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1260         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1261         struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload;
1262         struct iwl_cmd_meta *out_meta;
1263         struct iwl_tx_queue *txq;
1264         struct iwl_queue *q;
1265
1266         dma_addr_t phys_addr = 0;
1267         dma_addr_t txcmd_phys;
1268         dma_addr_t scratch_phys;
1269         u16 len, firstlen, secondlen;
1270         u8 wait_write_ptr = 0;
1271         u8 txq_id;
1272         bool is_agg = false;
1273         __le16 fc = hdr->frame_control;
1274         u8 hdr_len = ieee80211_hdrlen(fc);
1275         u16 __maybe_unused wifi_seq;
1276
1277         /*
1278          * Send this frame after DTIM -- there's a special queue
1279          * reserved for this for contexts that support AP mode.
1280          */
1281         if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1282                 txq_id = trans_pcie->mcast_queue[ctx];
1283
1284                 /*
1285                  * The microcode will clear the more data
1286                  * bit in the last frame it transmits.
1287                  */
1288                 hdr->frame_control |=
1289                         cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1290         } else if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)
1291                 txq_id = IWL_AUX_QUEUE;
1292         else
1293                 txq_id =
1294                     trans_pcie->ac_to_queue[ctx][skb_get_queue_mapping(skb)];
1295
1296         /* aggregation is on for this <sta,tid> */
1297         if (info->flags & IEEE80211_TX_CTL_AMPDU) {
1298                 WARN_ON(tid >= IWL_MAX_TID_COUNT);
1299                 txq_id = trans_pcie->agg_txq[sta_id][tid];
1300                 is_agg = true;
1301         }
1302
1303         txq = &trans_pcie->txq[txq_id];
1304         q = &txq->q;
1305
1306         /* In AGG mode, the index in the ring must correspond to the WiFi
1307          * sequence number. This is a HW requirements to help the SCD to parse
1308          * the BA.
1309          * Check here that the packets are in the right place on the ring.
1310          */
1311 #ifdef CONFIG_IWLWIFI_DEBUG
1312         wifi_seq = SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1313         WARN_ONCE(is_agg && ((wifi_seq & 0xff) != q->write_ptr),
1314                   "Q: %d WiFi Seq %d tfdNum %d",
1315                   txq_id, wifi_seq, q->write_ptr);
1316 #endif
1317
1318         /* Set up driver data for this TFD */
1319         txq->skbs[q->write_ptr] = skb;
1320         txq->cmd[q->write_ptr] = dev_cmd;
1321
1322         dev_cmd->hdr.cmd = REPLY_TX;
1323         dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1324                                 INDEX_TO_SEQ(q->write_ptr)));
1325
1326         /* Set up first empty entry in queue's array of Tx/cmd buffers */
1327         out_meta = &txq->meta[q->write_ptr];
1328
1329         /*
1330          * Use the first empty entry in this queue's command buffer array
1331          * to contain the Tx command and MAC header concatenated together
1332          * (payload data will be in another buffer).
1333          * Size of this varies, due to varying MAC header length.
1334          * If end is not dword aligned, we'll have 2 extra bytes at the end
1335          * of the MAC header (device reads on dword boundaries).
1336          * We'll tell device about this padding later.
1337          */
1338         len = sizeof(struct iwl_tx_cmd) +
1339                 sizeof(struct iwl_cmd_header) + hdr_len;
1340         firstlen = (len + 3) & ~3;
1341
1342         /* Tell NIC about any 2-byte padding after MAC header */
1343         if (firstlen != len)
1344                 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1345
1346         /* Physical address of this Tx command's header (not MAC header!),
1347          * within command buffer array. */
1348         txcmd_phys = dma_map_single(trans->dev,
1349                                     &dev_cmd->hdr, firstlen,
1350                                     DMA_BIDIRECTIONAL);
1351         if (unlikely(dma_mapping_error(trans->dev, txcmd_phys)))
1352                 return -1;
1353         dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1354         dma_unmap_len_set(out_meta, len, firstlen);
1355
1356         if (!ieee80211_has_morefrags(fc)) {
1357                 txq->need_update = 1;
1358         } else {
1359                 wait_write_ptr = 1;
1360                 txq->need_update = 0;
1361         }
1362
1363         /* Set up TFD's 2nd entry to point directly to remainder of skb,
1364          * if any (802.11 null frames have no payload). */
1365         secondlen = skb->len - hdr_len;
1366         if (secondlen > 0) {
1367                 phys_addr = dma_map_single(trans->dev, skb->data + hdr_len,
1368                                            secondlen, DMA_TO_DEVICE);
1369                 if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
1370                         dma_unmap_single(trans->dev,
1371                                          dma_unmap_addr(out_meta, mapping),
1372                                          dma_unmap_len(out_meta, len),
1373                                          DMA_BIDIRECTIONAL);
1374                         return -1;
1375                 }
1376         }
1377
1378         /* Attach buffers to TFD */
1379         iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1);
1380         if (secondlen > 0)
1381                 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
1382                                              secondlen, 0);
1383
1384         scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1385                                 offsetof(struct iwl_tx_cmd, scratch);
1386
1387         /* take back ownership of DMA buffer to enable update */
1388         dma_sync_single_for_cpu(trans->dev, txcmd_phys, firstlen,
1389                         DMA_BIDIRECTIONAL);
1390         tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1391         tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1392
1393         IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
1394                      le16_to_cpu(dev_cmd->hdr.sequence));
1395         IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1396         iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
1397         iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
1398
1399         /* Set up entry for this TFD in Tx byte-count array */
1400         iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1401
1402         dma_sync_single_for_device(trans->dev, txcmd_phys, firstlen,
1403                         DMA_BIDIRECTIONAL);
1404
1405         trace_iwlwifi_dev_tx(priv(trans),
1406                              &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
1407                              sizeof(struct iwl_tfd),
1408                              &dev_cmd->hdr, firstlen,
1409                              skb->data + hdr_len, secondlen);
1410
1411         /* Tell device the write index *just past* this latest filled TFD */
1412         q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1413         iwl_txq_update_write_ptr(trans, txq);
1414
1415         /*
1416          * At this point the frame is "transmitted" successfully
1417          * and we will get a TX status notification eventually,
1418          * regardless of the value of ret. "ret" only indicates
1419          * whether or not we should update the write pointer.
1420          */
1421         if (iwl_queue_space(q) < q->high_mark) {
1422                 if (wait_write_ptr) {
1423                         txq->need_update = 1;
1424                         iwl_txq_update_write_ptr(trans, txq);
1425                 } else {
1426                         iwl_stop_queue(trans, txq, "Queue is full");
1427                 }
1428         }
1429         return 0;
1430 }
1431
1432 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1433 {
1434         struct iwl_trans_pcie *trans_pcie =
1435                 IWL_TRANS_GET_PCIE_TRANS(trans);
1436         int err;
1437
1438         trans_pcie->inta_mask = CSR_INI_SET_MASK;
1439
1440         if (!trans_pcie->irq_requested) {
1441                 tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1442                         iwl_irq_tasklet, (unsigned long)trans);
1443
1444                 iwl_alloc_isr_ict(trans);
1445
1446                 err = request_irq(trans->irq, iwl_isr_ict, IRQF_SHARED,
1447                         DRV_NAME, trans);
1448                 if (err) {
1449                         IWL_ERR(trans, "Error allocating IRQ %d\n",
1450                                 trans->irq);
1451                         goto error;
1452                 }
1453
1454                 INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1455                 trans_pcie->irq_requested = true;
1456         }
1457
1458         err = iwl_prepare_card_hw(trans);
1459         if (err) {
1460                 IWL_ERR(trans, "Error while preparing HW: %d", err);
1461                 goto error;
1462         }
1463
1464         iwl_apm_init(trans);
1465
1466         /* If platform's RF_KILL switch is NOT set to KILL */
1467         if (iwl_read32(trans,
1468                         CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
1469                 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1470         else
1471                 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1472
1473         iwl_set_hw_rfkill_state(priv(trans),
1474                                 test_bit(STATUS_RF_KILL_HW,
1475                                          &trans->shrd->status));
1476
1477         return err;
1478
1479 error:
1480         iwl_free_isr_ict(trans);
1481         tasklet_kill(&trans_pcie->irq_tasklet);
1482         return err;
1483 }
1484
1485 static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans)
1486 {
1487         iwl_apm_stop(trans);
1488
1489         /* Even if we stop the HW, we still want the RF kill interrupt */
1490         IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n");
1491         iwl_write32(trans, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
1492 }
1493
1494 static int iwl_trans_pcie_reclaim(struct iwl_trans *trans, int sta_id, int tid,
1495                       int txq_id, int ssn, u32 status,
1496                       struct sk_buff_head *skbs)
1497 {
1498         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1499         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1500         /* n_bd is usually 256 => n_bd - 1 = 0xff */
1501         int tfd_num = ssn & (txq->q.n_bd - 1);
1502         int freed = 0;
1503
1504         txq->time_stamp = jiffies;
1505
1506         if (unlikely(txq_id >= IWLAGN_FIRST_AMPDU_QUEUE &&
1507                      txq_id != trans_pcie->agg_txq[sta_id][tid])) {
1508                 /*
1509                  * FIXME: this is a uCode bug which need to be addressed,
1510                  * log the information and return for now.
1511                  * Since it is can possibly happen very often and in order
1512                  * not to fill the syslog, don't use IWL_ERR or IWL_WARN
1513                  */
1514                 IWL_DEBUG_TX_QUEUES(trans, "Bad queue mapping txq_id %d, "
1515                         "agg_txq[sta_id[tid] %d", txq_id,
1516                         trans_pcie->agg_txq[sta_id][tid]);
1517                 return 1;
1518         }
1519
1520         if (txq->q.read_ptr != tfd_num) {
1521                 IWL_DEBUG_TX_REPLY(trans, "[Q %d | AC %d] %d -> %d (%d)\n",
1522                                 txq_id, iwl_get_queue_ac(txq), txq->q.read_ptr,
1523                                 tfd_num, ssn);
1524                 freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
1525                 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
1526                    (!txq->sched_retry ||
1527                    status != TX_STATUS_FAIL_PASSIVE_NO_RX))
1528                         iwl_wake_queue(trans, txq, "Packets reclaimed");
1529         }
1530         return 0;
1531 }
1532
1533 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1534 {
1535         iowrite8(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1536 }
1537
1538 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1539 {
1540         iowrite32(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1541 }
1542
1543 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1544 {
1545         u32 val = ioread32(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1546         return val;
1547 }
1548
1549 static void iwl_trans_pcie_free(struct iwl_trans *trans)
1550 {
1551         struct iwl_trans_pcie *trans_pcie =
1552                 IWL_TRANS_GET_PCIE_TRANS(trans);
1553
1554         iwl_calib_free_results(trans);
1555         iwl_trans_pcie_tx_free(trans);
1556 #ifndef CONFIG_IWLWIFI_IDI
1557         iwl_trans_pcie_rx_free(trans);
1558 #endif
1559         if (trans_pcie->irq_requested == true) {
1560                 free_irq(trans->irq, trans);
1561                 iwl_free_isr_ict(trans);
1562         }
1563
1564         pci_disable_msi(trans_pcie->pci_dev);
1565         pci_iounmap(trans_pcie->pci_dev, trans_pcie->hw_base);
1566         pci_release_regions(trans_pcie->pci_dev);
1567         pci_disable_device(trans_pcie->pci_dev);
1568
1569         trans->shrd->trans = NULL;
1570         kfree(trans);
1571 }
1572
1573 #ifdef CONFIG_PM_SLEEP
1574 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1575 {
1576         /*
1577          * This function is called when system goes into suspend state
1578          * mac80211 will call iwlagn_mac_stop() from the mac80211 suspend
1579          * function first but since iwlagn_mac_stop() has no knowledge of
1580          * who the caller is,
1581          * it will not call apm_ops.stop() to stop the DMA operation.
1582          * Calling apm_ops.stop here to make sure we stop the DMA.
1583          *
1584          * But of course ... if we have configured WoWLAN then we did other
1585          * things already :-)
1586          */
1587         if (!trans->shrd->wowlan) {
1588                 iwl_apm_stop(trans);
1589         } else {
1590                 iwl_disable_interrupts(trans);
1591                 iwl_clear_bit(trans, CSR_GP_CNTRL,
1592                               CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1593         }
1594
1595         return 0;
1596 }
1597
1598 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1599 {
1600         bool hw_rfkill = false;
1601
1602         iwl_enable_interrupts(trans);
1603
1604         if (!(iwl_read32(trans, CSR_GP_CNTRL) &
1605                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1606                 hw_rfkill = true;
1607
1608         if (hw_rfkill)
1609                 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1610         else
1611                 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1612
1613         iwl_set_hw_rfkill_state(priv(trans), hw_rfkill);
1614
1615         return 0;
1616 }
1617 #endif /* CONFIG_PM_SLEEP */
1618
1619 static void iwl_trans_pcie_wake_any_queue(struct iwl_trans *trans,
1620                                           enum iwl_rxon_context_id ctx,
1621                                           const char *msg)
1622 {
1623         u8 ac, txq_id;
1624         struct iwl_trans_pcie *trans_pcie =
1625                 IWL_TRANS_GET_PCIE_TRANS(trans);
1626
1627         for (ac = 0; ac < AC_NUM; ac++) {
1628                 txq_id = trans_pcie->ac_to_queue[ctx][ac];
1629                 IWL_DEBUG_TX_QUEUES(trans, "Queue Status: Q[%d] %s\n",
1630                         ac,
1631                         (atomic_read(&trans_pcie->queue_stop_count[ac]) > 0)
1632                               ? "stopped" : "awake");
1633                 iwl_wake_queue(trans, &trans_pcie->txq[txq_id], msg);
1634         }
1635 }
1636
1637 static void iwl_trans_pcie_stop_queue(struct iwl_trans *trans, int txq_id,
1638                                       const char *msg)
1639 {
1640         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1641
1642         iwl_stop_queue(trans, &trans_pcie->txq[txq_id], msg);
1643 }
1644
1645 #define IWL_FLUSH_WAIT_MS       2000
1646
1647 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
1648 {
1649         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1650         struct iwl_tx_queue *txq;
1651         struct iwl_queue *q;
1652         int cnt;
1653         unsigned long now = jiffies;
1654         int ret = 0;
1655
1656         /* waiting for all the tx frames complete might take a while */
1657         for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1658                 if (cnt == trans->shrd->cmd_queue)
1659                         continue;
1660                 txq = &trans_pcie->txq[cnt];
1661                 q = &txq->q;
1662                 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1663                        now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1664                         msleep(1);
1665
1666                 if (q->read_ptr != q->write_ptr) {
1667                         IWL_ERR(trans, "fail to flush all tx fifo queues\n");
1668                         ret = -ETIMEDOUT;
1669                         break;
1670                 }
1671         }
1672         return ret;
1673 }
1674
1675 /*
1676  * On every watchdog tick we check (latest) time stamp. If it does not
1677  * change during timeout period and queue is not empty we reset firmware.
1678  */
1679 static int iwl_trans_pcie_check_stuck_queue(struct iwl_trans *trans, int cnt)
1680 {
1681         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1682         struct iwl_tx_queue *txq = &trans_pcie->txq[cnt];
1683         struct iwl_queue *q = &txq->q;
1684         unsigned long timeout;
1685
1686         if (q->read_ptr == q->write_ptr) {
1687                 txq->time_stamp = jiffies;
1688                 return 0;
1689         }
1690
1691         timeout = txq->time_stamp +
1692                   msecs_to_jiffies(hw_params(trans).wd_timeout);
1693
1694         if (time_after(jiffies, timeout)) {
1695                 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", q->id,
1696                         hw_params(trans).wd_timeout);
1697                 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1698                         q->read_ptr, q->write_ptr);
1699                 IWL_ERR(trans, "Current HW read_ptr %d write_ptr %d\n",
1700                         iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt))
1701                                 & (TFD_QUEUE_SIZE_MAX - 1),
1702                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1703                 return 1;
1704         }
1705
1706         return 0;
1707 }
1708
1709 static const char *get_fh_string(int cmd)
1710 {
1711         switch (cmd) {
1712         IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1713         IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1714         IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1715         IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1716         IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1717         IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1718         IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1719         IWL_CMD(FH_TSSR_TX_STATUS_REG);
1720         IWL_CMD(FH_TSSR_TX_ERROR_REG);
1721         default:
1722                 return "UNKNOWN";
1723         }
1724 }
1725
1726 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1727 {
1728         int i;
1729 #ifdef CONFIG_IWLWIFI_DEBUG
1730         int pos = 0;
1731         size_t bufsz = 0;
1732 #endif
1733         static const u32 fh_tbl[] = {
1734                 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1735                 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1736                 FH_RSCSR_CHNL0_WPTR,
1737                 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1738                 FH_MEM_RSSR_SHARED_CTRL_REG,
1739                 FH_MEM_RSSR_RX_STATUS_REG,
1740                 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1741                 FH_TSSR_TX_STATUS_REG,
1742                 FH_TSSR_TX_ERROR_REG
1743         };
1744 #ifdef CONFIG_IWLWIFI_DEBUG
1745         if (display) {
1746                 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1747                 *buf = kmalloc(bufsz, GFP_KERNEL);
1748                 if (!*buf)
1749                         return -ENOMEM;
1750                 pos += scnprintf(*buf + pos, bufsz - pos,
1751                                 "FH register values:\n");
1752                 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1753                         pos += scnprintf(*buf + pos, bufsz - pos,
1754                                 "  %34s: 0X%08x\n",
1755                                 get_fh_string(fh_tbl[i]),
1756                                 iwl_read_direct32(trans, fh_tbl[i]));
1757                 }
1758                 return pos;
1759         }
1760 #endif
1761         IWL_ERR(trans, "FH register values:\n");
1762         for (i = 0; i <  ARRAY_SIZE(fh_tbl); i++) {
1763                 IWL_ERR(trans, "  %34s: 0X%08x\n",
1764                         get_fh_string(fh_tbl[i]),
1765                         iwl_read_direct32(trans, fh_tbl[i]));
1766         }
1767         return 0;
1768 }
1769
1770 static const char *get_csr_string(int cmd)
1771 {
1772         switch (cmd) {
1773         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1774         IWL_CMD(CSR_INT_COALESCING);
1775         IWL_CMD(CSR_INT);
1776         IWL_CMD(CSR_INT_MASK);
1777         IWL_CMD(CSR_FH_INT_STATUS);
1778         IWL_CMD(CSR_GPIO_IN);
1779         IWL_CMD(CSR_RESET);
1780         IWL_CMD(CSR_GP_CNTRL);
1781         IWL_CMD(CSR_HW_REV);
1782         IWL_CMD(CSR_EEPROM_REG);
1783         IWL_CMD(CSR_EEPROM_GP);
1784         IWL_CMD(CSR_OTP_GP_REG);
1785         IWL_CMD(CSR_GIO_REG);
1786         IWL_CMD(CSR_GP_UCODE_REG);
1787         IWL_CMD(CSR_GP_DRIVER_REG);
1788         IWL_CMD(CSR_UCODE_DRV_GP1);
1789         IWL_CMD(CSR_UCODE_DRV_GP2);
1790         IWL_CMD(CSR_LED_REG);
1791         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1792         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1793         IWL_CMD(CSR_ANA_PLL_CFG);
1794         IWL_CMD(CSR_HW_REV_WA_REG);
1795         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1796         default:
1797                 return "UNKNOWN";
1798         }
1799 }
1800
1801 void iwl_dump_csr(struct iwl_trans *trans)
1802 {
1803         int i;
1804         static const u32 csr_tbl[] = {
1805                 CSR_HW_IF_CONFIG_REG,
1806                 CSR_INT_COALESCING,
1807                 CSR_INT,
1808                 CSR_INT_MASK,
1809                 CSR_FH_INT_STATUS,
1810                 CSR_GPIO_IN,
1811                 CSR_RESET,
1812                 CSR_GP_CNTRL,
1813                 CSR_HW_REV,
1814                 CSR_EEPROM_REG,
1815                 CSR_EEPROM_GP,
1816                 CSR_OTP_GP_REG,
1817                 CSR_GIO_REG,
1818                 CSR_GP_UCODE_REG,
1819                 CSR_GP_DRIVER_REG,
1820                 CSR_UCODE_DRV_GP1,
1821                 CSR_UCODE_DRV_GP2,
1822                 CSR_LED_REG,
1823                 CSR_DRAM_INT_TBL_REG,
1824                 CSR_GIO_CHICKEN_BITS,
1825                 CSR_ANA_PLL_CFG,
1826                 CSR_HW_REV_WA_REG,
1827                 CSR_DBG_HPET_MEM_REG
1828         };
1829         IWL_ERR(trans, "CSR values:\n");
1830         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1831                 "CSR_INT_PERIODIC_REG)\n");
1832         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1833                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1834                         get_csr_string(csr_tbl[i]),
1835                         iwl_read32(trans, csr_tbl[i]));
1836         }
1837 }
1838
1839 #ifdef CONFIG_IWLWIFI_DEBUGFS
1840 /* create and remove of files */
1841 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1842         if (!debugfs_create_file(#name, mode, parent, trans,            \
1843                                  &iwl_dbgfs_##name##_ops))              \
1844                 return -ENOMEM;                                         \
1845 } while (0)
1846
1847 /* file operation */
1848 #define DEBUGFS_READ_FUNC(name)                                         \
1849 static ssize_t iwl_dbgfs_##name##_read(struct file *file,               \
1850                                         char __user *user_buf,          \
1851                                         size_t count, loff_t *ppos);
1852
1853 #define DEBUGFS_WRITE_FUNC(name)                                        \
1854 static ssize_t iwl_dbgfs_##name##_write(struct file *file,              \
1855                                         const char __user *user_buf,    \
1856                                         size_t count, loff_t *ppos);
1857
1858
1859 static int iwl_dbgfs_open_file_generic(struct inode *inode, struct file *file)
1860 {
1861         file->private_data = inode->i_private;
1862         return 0;
1863 }
1864
1865 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1866         DEBUGFS_READ_FUNC(name);                                        \
1867 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1868         .read = iwl_dbgfs_##name##_read,                                \
1869         .open = iwl_dbgfs_open_file_generic,                            \
1870         .llseek = generic_file_llseek,                                  \
1871 };
1872
1873 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1874         DEBUGFS_WRITE_FUNC(name);                                       \
1875 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1876         .write = iwl_dbgfs_##name##_write,                              \
1877         .open = iwl_dbgfs_open_file_generic,                            \
1878         .llseek = generic_file_llseek,                                  \
1879 };
1880
1881 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1882         DEBUGFS_READ_FUNC(name);                                        \
1883         DEBUGFS_WRITE_FUNC(name);                                       \
1884 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1885         .write = iwl_dbgfs_##name##_write,                              \
1886         .read = iwl_dbgfs_##name##_read,                                \
1887         .open = iwl_dbgfs_open_file_generic,                            \
1888         .llseek = generic_file_llseek,                                  \
1889 };
1890
1891 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1892                                                 char __user *user_buf,
1893                                                 size_t count, loff_t *ppos)
1894 {
1895         struct iwl_trans *trans = file->private_data;
1896         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1897         struct iwl_tx_queue *txq;
1898         struct iwl_queue *q;
1899         char *buf;
1900         int pos = 0;
1901         int cnt;
1902         int ret;
1903         const size_t bufsz = sizeof(char) * 64 * hw_params(trans).max_txq_num;
1904
1905         if (!trans_pcie->txq) {
1906                 IWL_ERR(trans, "txq not ready\n");
1907                 return -EAGAIN;
1908         }
1909         buf = kzalloc(bufsz, GFP_KERNEL);
1910         if (!buf)
1911                 return -ENOMEM;
1912
1913         for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1914                 txq = &trans_pcie->txq[cnt];
1915                 q = &txq->q;
1916                 pos += scnprintf(buf + pos, bufsz - pos,
1917                                 "hwq %.2d: read=%u write=%u stop=%d"
1918                                 " swq_id=%#.2x (ac %d/hwq %d)\n",
1919                                 cnt, q->read_ptr, q->write_ptr,
1920                                 !!test_bit(cnt, trans_pcie->queue_stopped),
1921                                 txq->swq_id, txq->swq_id & 3,
1922                                 (txq->swq_id >> 2) & 0x1f);
1923                 if (cnt >= 4)
1924                         continue;
1925                 /* for the ACs, display the stop count too */
1926                 pos += scnprintf(buf + pos, bufsz - pos,
1927                         "        stop-count: %d\n",
1928                         atomic_read(&trans_pcie->queue_stop_count[cnt]));
1929         }
1930         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1931         kfree(buf);
1932         return ret;
1933 }
1934
1935 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1936                                                 char __user *user_buf,
1937                                                 size_t count, loff_t *ppos) {
1938         struct iwl_trans *trans = file->private_data;
1939         struct iwl_trans_pcie *trans_pcie =
1940                 IWL_TRANS_GET_PCIE_TRANS(trans);
1941         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
1942         char buf[256];
1943         int pos = 0;
1944         const size_t bufsz = sizeof(buf);
1945
1946         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1947                                                 rxq->read);
1948         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1949                                                 rxq->write);
1950         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1951                                                 rxq->free_count);
1952         if (rxq->rb_stts) {
1953                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1954                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
1955         } else {
1956                 pos += scnprintf(buf + pos, bufsz - pos,
1957                                         "closed_rb_num: Not Allocated\n");
1958         }
1959         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1960 }
1961
1962 static ssize_t iwl_dbgfs_log_event_read(struct file *file,
1963                                          char __user *user_buf,
1964                                          size_t count, loff_t *ppos)
1965 {
1966         struct iwl_trans *trans = file->private_data;
1967         char *buf;
1968         int pos = 0;
1969         ssize_t ret = -ENOMEM;
1970
1971         ret = pos = iwl_dump_nic_event_log(trans, true, &buf, true);
1972         if (buf) {
1973                 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1974                 kfree(buf);
1975         }
1976         return ret;
1977 }
1978
1979 static ssize_t iwl_dbgfs_log_event_write(struct file *file,
1980                                         const char __user *user_buf,
1981                                         size_t count, loff_t *ppos)
1982 {
1983         struct iwl_trans *trans = file->private_data;
1984         u32 event_log_flag;
1985         char buf[8];
1986         int buf_size;
1987
1988         memset(buf, 0, sizeof(buf));
1989         buf_size = min(count, sizeof(buf) -  1);
1990         if (copy_from_user(buf, user_buf, buf_size))
1991                 return -EFAULT;
1992         if (sscanf(buf, "%d", &event_log_flag) != 1)
1993                 return -EFAULT;
1994         if (event_log_flag == 1)
1995                 iwl_dump_nic_event_log(trans, true, NULL, false);
1996
1997         return count;
1998 }
1999
2000 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2001                                         char __user *user_buf,
2002                                         size_t count, loff_t *ppos) {
2003
2004         struct iwl_trans *trans = file->private_data;
2005         struct iwl_trans_pcie *trans_pcie =
2006                 IWL_TRANS_GET_PCIE_TRANS(trans);
2007         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2008
2009         int pos = 0;
2010         char *buf;
2011         int bufsz = 24 * 64; /* 24 items * 64 char per item */
2012         ssize_t ret;
2013
2014         buf = kzalloc(bufsz, GFP_KERNEL);
2015         if (!buf) {
2016                 IWL_ERR(trans, "Can not allocate Buffer\n");
2017                 return -ENOMEM;
2018         }
2019
2020         pos += scnprintf(buf + pos, bufsz - pos,
2021                         "Interrupt Statistics Report:\n");
2022
2023         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2024                 isr_stats->hw);
2025         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2026                 isr_stats->sw);
2027         if (isr_stats->sw || isr_stats->hw) {
2028                 pos += scnprintf(buf + pos, bufsz - pos,
2029                         "\tLast Restarting Code:  0x%X\n",
2030                         isr_stats->err_code);
2031         }
2032 #ifdef CONFIG_IWLWIFI_DEBUG
2033         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2034                 isr_stats->sch);
2035         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2036                 isr_stats->alive);
2037 #endif
2038         pos += scnprintf(buf + pos, bufsz - pos,
2039                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2040
2041         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2042                 isr_stats->ctkill);
2043
2044         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2045                 isr_stats->wakeup);
2046
2047         pos += scnprintf(buf + pos, bufsz - pos,
2048                 "Rx command responses:\t\t %u\n", isr_stats->rx);
2049
2050         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2051                 isr_stats->tx);
2052
2053         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2054                 isr_stats->unhandled);
2055
2056         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2057         kfree(buf);
2058         return ret;
2059 }
2060
2061 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2062                                          const char __user *user_buf,
2063                                          size_t count, loff_t *ppos)
2064 {
2065         struct iwl_trans *trans = file->private_data;
2066         struct iwl_trans_pcie *trans_pcie =
2067                 IWL_TRANS_GET_PCIE_TRANS(trans);
2068         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2069
2070         char buf[8];
2071         int buf_size;
2072         u32 reset_flag;
2073
2074         memset(buf, 0, sizeof(buf));
2075         buf_size = min(count, sizeof(buf) -  1);
2076         if (copy_from_user(buf, user_buf, buf_size))
2077                 return -EFAULT;
2078         if (sscanf(buf, "%x", &reset_flag) != 1)
2079                 return -EFAULT;
2080         if (reset_flag == 0)
2081                 memset(isr_stats, 0, sizeof(*isr_stats));
2082
2083         return count;
2084 }
2085
2086 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2087                                          const char __user *user_buf,
2088                                          size_t count, loff_t *ppos)
2089 {
2090         struct iwl_trans *trans = file->private_data;
2091         char buf[8];
2092         int buf_size;
2093         int csr;
2094
2095         memset(buf, 0, sizeof(buf));
2096         buf_size = min(count, sizeof(buf) -  1);
2097         if (copy_from_user(buf, user_buf, buf_size))
2098                 return -EFAULT;
2099         if (sscanf(buf, "%d", &csr) != 1)
2100                 return -EFAULT;
2101
2102         iwl_dump_csr(trans);
2103
2104         return count;
2105 }
2106
2107 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2108                                          char __user *user_buf,
2109                                          size_t count, loff_t *ppos)
2110 {
2111         struct iwl_trans *trans = file->private_data;
2112         char *buf;
2113         int pos = 0;
2114         ssize_t ret = -EFAULT;
2115
2116         ret = pos = iwl_dump_fh(trans, &buf, true);
2117         if (buf) {
2118                 ret = simple_read_from_buffer(user_buf,
2119                                               count, ppos, buf, pos);
2120                 kfree(buf);
2121         }
2122
2123         return ret;
2124 }
2125
2126 DEBUGFS_READ_WRITE_FILE_OPS(log_event);
2127 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2128 DEBUGFS_READ_FILE_OPS(fh_reg);
2129 DEBUGFS_READ_FILE_OPS(rx_queue);
2130 DEBUGFS_READ_FILE_OPS(tx_queue);
2131 DEBUGFS_WRITE_FILE_OPS(csr);
2132
2133 /*
2134  * Create the debugfs files and directories
2135  *
2136  */
2137 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2138                                         struct dentry *dir)
2139 {
2140         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2141         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2142         DEBUGFS_ADD_FILE(log_event, dir, S_IWUSR | S_IRUSR);
2143         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2144         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2145         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2146         return 0;
2147 }
2148 #else
2149 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2150                                         struct dentry *dir)
2151 { return 0; }
2152
2153 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2154
2155 const struct iwl_trans_ops trans_ops_pcie = {
2156         .start_hw = iwl_trans_pcie_start_hw,
2157         .stop_hw = iwl_trans_pcie_stop_hw,
2158         .fw_alive = iwl_trans_pcie_fw_alive,
2159         .start_fw = iwl_trans_pcie_start_fw,
2160         .stop_device = iwl_trans_pcie_stop_device,
2161
2162         .wake_any_queue = iwl_trans_pcie_wake_any_queue,
2163
2164         .send_cmd = iwl_trans_pcie_send_cmd,
2165
2166         .tx = iwl_trans_pcie_tx,
2167         .reclaim = iwl_trans_pcie_reclaim,
2168
2169         .tx_agg_disable = iwl_trans_pcie_tx_agg_disable,
2170         .tx_agg_alloc = iwl_trans_pcie_tx_agg_alloc,
2171         .tx_agg_setup = iwl_trans_pcie_tx_agg_setup,
2172
2173         .free = iwl_trans_pcie_free,
2174         .stop_queue = iwl_trans_pcie_stop_queue,
2175
2176         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2177
2178         .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty,
2179         .check_stuck_queue = iwl_trans_pcie_check_stuck_queue,
2180
2181 #ifdef CONFIG_PM_SLEEP
2182         .suspend = iwl_trans_pcie_suspend,
2183         .resume = iwl_trans_pcie_resume,
2184 #endif
2185         .write8 = iwl_trans_pcie_write8,
2186         .write32 = iwl_trans_pcie_write32,
2187         .read32 = iwl_trans_pcie_read32,
2188 };
2189
2190 /* PCI registers */
2191 #define PCI_CFG_RETRY_TIMEOUT   0x041
2192
2193 struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd,
2194                                        struct pci_dev *pdev,
2195                                        const struct pci_device_id *ent)
2196 {
2197         struct iwl_trans_pcie *trans_pcie;
2198         struct iwl_trans *trans;
2199         u16 pci_cmd;
2200         int err;
2201
2202         trans = kzalloc(sizeof(struct iwl_trans) +
2203                              sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2204
2205         if (WARN_ON(!trans))
2206                 return NULL;
2207
2208         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2209
2210         trans->ops = &trans_ops_pcie;
2211         trans->shrd = shrd;
2212         trans_pcie->trans = trans;
2213         spin_lock_init(&trans->hcmd_lock);
2214
2215         /* W/A - seems to solve weird behavior. We need to remove this if we
2216          * don't want to stay in L1 all the time. This wastes a lot of power */
2217         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
2218                                 PCIE_LINK_STATE_CLKPM);
2219
2220         if (pci_enable_device(pdev)) {
2221                 err = -ENODEV;
2222                 goto out_no_pci;
2223         }
2224
2225         pci_set_master(pdev);
2226
2227         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2228         if (!err)
2229                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2230         if (err) {
2231                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2232                 if (!err)
2233                         err = pci_set_consistent_dma_mask(pdev,
2234                                                         DMA_BIT_MASK(32));
2235                 /* both attempts failed: */
2236                 if (err) {
2237                         dev_printk(KERN_ERR, &pdev->dev,
2238                                    "No suitable DMA available.\n");
2239                         goto out_pci_disable_device;
2240                 }
2241         }
2242
2243         err = pci_request_regions(pdev, DRV_NAME);
2244         if (err) {
2245                 dev_printk(KERN_ERR, &pdev->dev, "pci_request_regions failed");
2246                 goto out_pci_disable_device;
2247         }
2248
2249         trans_pcie->hw_base = pci_iomap(pdev, 0, 0);
2250         if (!trans_pcie->hw_base) {
2251                 dev_printk(KERN_ERR, &pdev->dev, "pci_iomap failed");
2252                 err = -ENODEV;
2253                 goto out_pci_release_regions;
2254         }
2255
2256         dev_printk(KERN_INFO, &pdev->dev,
2257                 "pci_resource_len = 0x%08llx\n",
2258                 (unsigned long long) pci_resource_len(pdev, 0));
2259         dev_printk(KERN_INFO, &pdev->dev,
2260                 "pci_resource_base = %p\n", trans_pcie->hw_base);
2261
2262         dev_printk(KERN_INFO, &pdev->dev,
2263                 "HW Revision ID = 0x%X\n", pdev->revision);
2264
2265         /* We disable the RETRY_TIMEOUT register (0x41) to keep
2266          * PCI Tx retries from interfering with C3 CPU state */
2267         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2268
2269         err = pci_enable_msi(pdev);
2270         if (err)
2271                 dev_printk(KERN_ERR, &pdev->dev,
2272                         "pci_enable_msi failed(0X%x)", err);
2273
2274         trans->dev = &pdev->dev;
2275         trans->irq = pdev->irq;
2276         trans_pcie->pci_dev = pdev;
2277
2278         /* TODO: Move this away, not needed if not MSI */
2279         /* enable rfkill interrupt: hw bug w/a */
2280         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2281         if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2282                 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2283                 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2284         }
2285
2286         return trans;
2287
2288 out_pci_release_regions:
2289         pci_release_regions(pdev);
2290 out_pci_disable_device:
2291         pci_disable_device(pdev);
2292 out_no_pci:
2293         kfree(trans);
2294         return NULL;
2295 }
2296