Pileus Git - ~andy/linux/blob - drivers/net/wireless/iwlwifi/iwl-trans-pcie.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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  20  * along with this program; if not, write to the Free Software
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  27  * Contact Information:
  28  *  Intel Linux Wireless <ilw@linux.intel.com>
  29  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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  32  *
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  37  * modification, are permitted provided that the following conditions
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  41  *    notice, this list of conditions and the following disclaimer.
  42  *  * Redistributions in binary form must reproduce the above copyright
  43  *    notice, this list of conditions and the following disclaimer in
  44  *    the documentation and/or other materials provided with the
  45  *    distribution.
  46  *  * Neither the name Intel Corporation nor the names of its
  47  *    contributors may be used to endorse or promote products derived
  48  *    from this software without specific prior written permission.
  49  *
  50  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  55  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  56  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  57  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  58  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63 #include <linux/pci.h>
  64 #include <linux/pci-aspm.h>
  65 #include <linux/interrupt.h>
  66 #include <linux/debugfs.h>
  67 #include <linux/sched.h>
  68 #include <linux/bitops.h>
  69 #include <linux/gfp.h>
  70
  71 #include "iwl-trans.h"
  72 #include "iwl-trans-pcie-int.h"
  73 #include "iwl-csr.h"
  74 #include "iwl-prph.h"
  75 #include "iwl-shared.h"
  76 #include "iwl-eeprom.h"
  77 #include "iwl-agn-hw.h"
  78 #include "iwl-core.h"
  79
  80 static int iwl_trans_rx_alloc(struct iwl_trans *trans)
  81 {
  82         struct iwl_trans_pcie *trans_pcie =
  83                 IWL_TRANS_GET_PCIE_TRANS(trans);
  84         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
  85         struct device *dev = trans->dev;
  86
  87         memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
  88
  89         spin_lock_init(&rxq->lock);
  90
  91         if (WARN_ON(rxq->bd || rxq->rb_stts))
  92                 return -EINVAL;
  93
  94         /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
  95         rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
  96                                       &rxq->bd_dma, GFP_KERNEL);
  97         if (!rxq->bd)
  98                 goto err_bd;
  99
 100         /*Allocate the driver's pointer to receive buffer status */
 101         rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
 102                                            &rxq->rb_stts_dma, GFP_KERNEL);
 103         if (!rxq->rb_stts)
 104                 goto err_rb_stts;
 105
 106         return 0;
 107
 108 err_rb_stts:
 109         dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
 110                         rxq->bd, rxq->bd_dma);
 111         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 112         rxq->bd = NULL;
 113 err_bd:
 114         return -ENOMEM;
 115 }
 116
 117 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
 118 {
 119         struct iwl_trans_pcie *trans_pcie =
 120                 IWL_TRANS_GET_PCIE_TRANS(trans);
 121         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 122         int i;
 123
 124         /* Fill the rx_used queue with _all_ of the Rx buffers */
 125         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
 126                 /* In the reset function, these buffers may have been allocated
 127                  * to an SKB, so we need to unmap and free potential storage */
 128                 if (rxq->pool[i].page != NULL) {
 129                         dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
 130                                 PAGE_SIZE << hw_params(trans).rx_page_order,
 131                                 DMA_FROM_DEVICE);
 132                         __free_pages(rxq->pool[i].page,
 133                                      hw_params(trans).rx_page_order);
 134                         rxq->pool[i].page = NULL;
 135                 }
 136                 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
 137         }
 138 }
 139
 140 static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
 141                                  struct iwl_rx_queue *rxq)
 142 {
 143         u32 rb_size;
 144         const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
 145         u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */
 146
 147         if (iwlagn_mod_params.amsdu_size_8K)
 148                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
 149         else
 150                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 151
 152         /* Stop Rx DMA */
 153         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 154
 155         /* Reset driver's Rx queue write index */
 156         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 157
 158         /* Tell device where to find RBD circular buffer in DRAM */
 159         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 160                            (u32)(rxq->bd_dma >> 8));
 161
 162         /* Tell device where in DRAM to update its Rx status */
 163         iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
 164                            rxq->rb_stts_dma >> 4);
 165
 166         /* Enable Rx DMA
 167          * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
 168          *      the credit mechanism in 5000 HW RX FIFO
 169          * Direct rx interrupts to hosts
 170          * Rx buffer size 4 or 8k
 171          * RB timeout 0x10
 172          * 256 RBDs
 173          */
 174         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
 175                            FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
 176                            FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
 177                            FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
 178                            FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
 179                            rb_size|
 180                            (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
 181                            (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
 182
 183         /* Set interrupt coalescing timer to default (2048 usecs) */
 184         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 185 }
 186
 187 static int iwl_rx_init(struct iwl_trans *trans)
 188 {
 189         struct iwl_trans_pcie *trans_pcie =
 190                 IWL_TRANS_GET_PCIE_TRANS(trans);
 191         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 192
 193         int i, err;
 194         unsigned long flags;
 195
 196         if (!rxq->bd) {
 197                 err = iwl_trans_rx_alloc(trans);
 198                 if (err)
 199                         return err;
 200         }
 201
 202         spin_lock_irqsave(&rxq->lock, flags);
 203         INIT_LIST_HEAD(&rxq->rx_free);
 204         INIT_LIST_HEAD(&rxq->rx_used);
 205
 206         iwl_trans_rxq_free_rx_bufs(trans);
 207
 208         for (i = 0; i < RX_QUEUE_SIZE; i++)
 209                 rxq->queue[i] = NULL;
 210
 211         /* Set us so that we have processed and used all buffers, but have
 212          * not restocked the Rx queue with fresh buffers */
 213         rxq->read = rxq->write = 0;
 214         rxq->write_actual = 0;
 215         rxq->free_count = 0;
 216         spin_unlock_irqrestore(&rxq->lock, flags);
 217
 218         iwlagn_rx_replenish(trans);
 219
 220         iwl_trans_rx_hw_init(trans, rxq);
 221
 222         spin_lock_irqsave(&trans->shrd->lock, flags);
 223         rxq->need_update = 1;
 224         iwl_rx_queue_update_write_ptr(trans, rxq);
 225         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 226
 227         return 0;
 228 }
 229
 230 static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
 231 {
 232         struct iwl_trans_pcie *trans_pcie =
 233                 IWL_TRANS_GET_PCIE_TRANS(trans);
 234         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 235
 236         unsigned long flags;
 237
 238         /*if rxq->bd is NULL, it means that nothing has been allocated,
 239          * exit now */
 240         if (!rxq->bd) {
 241                 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
 242                 return;
 243         }
 244
 245         spin_lock_irqsave(&rxq->lock, flags);
 246         iwl_trans_rxq_free_rx_bufs(trans);
 247         spin_unlock_irqrestore(&rxq->lock, flags);
 248
 249         dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
 250                           rxq->bd, rxq->bd_dma);
 251         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 252         rxq->bd = NULL;
 253
 254         if (rxq->rb_stts)
 255                 dma_free_coherent(trans->dev,
 256                                   sizeof(struct iwl_rb_status),
 257                                   rxq->rb_stts, rxq->rb_stts_dma);
 258         else
 259                 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
 260         memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
 261         rxq->rb_stts = NULL;
 262 }
 263
 264 static int iwl_trans_rx_stop(struct iwl_trans *trans)
 265 {
 266
 267         /* stop Rx DMA */
 268         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 269         return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
 270                             FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
 271 }
 272
 273 static inline int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
 274                                     struct iwl_dma_ptr *ptr, size_t size)
 275 {
 276         if (WARN_ON(ptr->addr))
 277                 return -EINVAL;
 278
 279         ptr->addr = dma_alloc_coherent(trans->dev, size,
 280                                        &ptr->dma, GFP_KERNEL);
 281         if (!ptr->addr)
 282                 return -ENOMEM;
 283         ptr->size = size;
 284         return 0;
 285 }
 286
 287 static inline void iwlagn_free_dma_ptr(struct iwl_trans *trans,
 288                                     struct iwl_dma_ptr *ptr)
 289 {
 290         if (unlikely(!ptr->addr))
 291                 return;
 292
 293         dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
 294         memset(ptr, 0, sizeof(*ptr));
 295 }
 296
 297 static int iwl_trans_txq_alloc(struct iwl_trans *trans,
 298                                 struct iwl_tx_queue *txq, int slots_num,
 299                                 u32 txq_id)
 300 {
 301         size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
 302         int i;
 303
 304         if (WARN_ON(txq->meta || txq->cmd || txq->skbs || txq->tfds))
 305                 return -EINVAL;
 306
 307         txq->q.n_window = slots_num;
 308
 309         txq->meta = kcalloc(slots_num, sizeof(txq->meta[0]), GFP_KERNEL);
 310         txq->cmd = kcalloc(slots_num, sizeof(txq->cmd[0]), GFP_KERNEL);
 311
 312         if (!txq->meta || !txq->cmd)
 313                 goto error;
 314
 315         if (txq_id == trans->shrd->cmd_queue)
 316                 for (i = 0; i < slots_num; i++) {
 317                         txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd),
 318                                                 GFP_KERNEL);
 319                         if (!txq->cmd[i])
 320                                 goto error;
 321                 }
 322
 323         /* Alloc driver data array and TFD circular buffer */
 324         /* Driver private data, only for Tx (not command) queues,
 325          * not shared with device. */
 326         if (txq_id != trans->shrd->cmd_queue) {
 327                 txq->skbs = kcalloc(TFD_QUEUE_SIZE_MAX, sizeof(txq->skbs[0]),
 328                                     GFP_KERNEL);
 329                 if (!txq->skbs) {
 330                         IWL_ERR(trans, "kmalloc for auxiliary BD "
 331                                   "structures failed\n");
 332                         goto error;
 333                 }
 334         } else {
 335                 txq->skbs = NULL;
 336         }
 337
 338         /* Circular buffer of transmit frame descriptors (TFDs),
 339          * shared with device */
 340         txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
 341                                        &txq->q.dma_addr, GFP_KERNEL);
 342         if (!txq->tfds) {
 343                 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
 344                 goto error;
 345         }
 346         txq->q.id = txq_id;
 347
 348         return 0;
 349 error:
 350         kfree(txq->skbs);
 351         txq->skbs = NULL;
 352         /* since txq->cmd has been zeroed,
 353          * all non allocated cmd[i] will be NULL */
 354         if (txq->cmd && txq_id == trans->shrd->cmd_queue)
 355                 for (i = 0; i < slots_num; i++)
 356                         kfree(txq->cmd[i]);
 357         kfree(txq->meta);
 358         kfree(txq->cmd);
 359         txq->meta = NULL;
 360         txq->cmd = NULL;
 361
 362         return -ENOMEM;
 363
 364 }
 365
 366 static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
 367                       int slots_num, u32 txq_id)
 368 {
 369         int ret;
 370
 371         txq->need_update = 0;
 372         memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num);
 373
 374         /*
 375          * For the default queues 0-3, set up the swq_id
 376          * already -- all others need to get one later
 377          * (if they need one at all).
 378          */
 379         if (txq_id < 4)
 380                 iwl_set_swq_id(txq, txq_id, txq_id);
 381
 382         /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
 383          * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
 384         BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
 385
 386         /* Initialize queue's high/low-water marks, and head/tail indexes */
 387         ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
 388                         txq_id);
 389         if (ret)
 390                 return ret;
 391
 392         /*
 393          * Tell nic where to find circular buffer of Tx Frame Descriptors for
 394          * given Tx queue, and enable the DMA channel used for that queue.
 395          * Circular buffer (TFD queue in DRAM) physical base address */
 396         iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
 397                              txq->q.dma_addr >> 8);
 398
 399         return 0;
 400 }
 401
 402 /**
 403  * iwl_tx_queue_unmap -  Unmap any remaining DMA mappings and free skb's
 404  */
 405 static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
 406 {
 407         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 408         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 409         struct iwl_queue *q = &txq->q;
 410         enum dma_data_direction dma_dir;
 411         unsigned long flags;
 412         spinlock_t *lock;
 413
 414         if (!q->n_bd)
 415                 return;
 416
 417         /* In the command queue, all the TBs are mapped as BIDI
 418          * so unmap them as such.
 419          */
 420         if (txq_id == trans->shrd->cmd_queue) {
 421                 dma_dir = DMA_BIDIRECTIONAL;
 422                 lock = &trans->hcmd_lock;
 423         } else {
 424                 dma_dir = DMA_TO_DEVICE;
 425                 lock = &trans->shrd->sta_lock;
 426         }
 427
 428         spin_lock_irqsave(lock, flags);
 429         while (q->write_ptr != q->read_ptr) {
 430                 /* The read_ptr needs to bound by q->n_window */
 431                 iwlagn_txq_free_tfd(trans, txq, get_cmd_index(q, q->read_ptr),
 432                                     dma_dir);
 433                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
 434         }
 435         spin_unlock_irqrestore(lock, flags);
 436 }
 437
 438 /**
 439  * iwl_tx_queue_free - Deallocate DMA queue.
 440  * @txq: Transmit queue to deallocate.
 441  *
 442  * Empty queue by removing and destroying all BD's.
 443  * Free all buffers.
 444  * 0-fill, but do not free "txq" descriptor structure.
 445  */
 446 static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
 447 {
 448         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 449         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 450         struct device *dev = trans->dev;
 451         int i;
 452         if (WARN_ON(!txq))
 453                 return;
 454
 455         iwl_tx_queue_unmap(trans, txq_id);
 456
 457         /* De-alloc array of command/tx buffers */
 458
 459         if (txq_id == trans->shrd->cmd_queue)
 460                 for (i = 0; i < txq->q.n_window; i++)
 461                         kfree(txq->cmd[i]);
 462
 463         /* De-alloc circular buffer of TFDs */
 464         if (txq->q.n_bd) {
 465                 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
 466                                   txq->q.n_bd, txq->tfds, txq->q.dma_addr);
 467                 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
 468         }
 469
 470         /* De-alloc array of per-TFD driver data */
 471         kfree(txq->skbs);
 472         txq->skbs = NULL;
 473
 474         /* deallocate arrays */
 475         kfree(txq->cmd);
 476         kfree(txq->meta);
 477         txq->cmd = NULL;
 478         txq->meta = NULL;
 479
 480         /* 0-fill queue descriptor structure */
 481         memset(txq, 0, sizeof(*txq));
 482 }
 483
 484 /**
 485  * iwl_trans_tx_free - Free TXQ Context
 486  *
 487  * Destroy all TX DMA queues and structures
 488  */
 489 static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
 490 {
 491         int txq_id;
 492         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 493
 494         /* Tx queues */
 495         if (trans_pcie->txq) {
 496                 for (txq_id = 0;
 497                      txq_id < hw_params(trans).max_txq_num; txq_id++)
 498                         iwl_tx_queue_free(trans, txq_id);
 499         }
 500
 501         kfree(trans_pcie->txq);
 502         trans_pcie->txq = NULL;
 503
 504         iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
 505
 506         iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
 507 }
 508
 509 /**
 510  * iwl_trans_tx_alloc - allocate TX context
 511  * Allocate all Tx DMA structures and initialize them
 512  *
 513  * @param priv
 514  * @return error code
 515  */
 516 static int iwl_trans_tx_alloc(struct iwl_trans *trans)
 517 {
 518         int ret;
 519         int txq_id, slots_num;
 520         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 521
 522         u16 scd_bc_tbls_size = hw_params(trans).max_txq_num *
 523                         sizeof(struct iwlagn_scd_bc_tbl);
 524
 525         /*It is not allowed to alloc twice, so warn when this happens.
 526          * We cannot rely on the previous allocation, so free and fail */
 527         if (WARN_ON(trans_pcie->txq)) {
 528                 ret = -EINVAL;
 529                 goto error;
 530         }
 531
 532         ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
 533                                    scd_bc_tbls_size);
 534         if (ret) {
 535                 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
 536                 goto error;
 537         }
 538
 539         /* Alloc keep-warm buffer */
 540         ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
 541         if (ret) {
 542                 IWL_ERR(trans, "Keep Warm allocation failed\n");
 543                 goto error;
 544         }
 545
 546         trans_pcie->txq = kcalloc(hw_params(trans).max_txq_num,
 547                                   sizeof(struct iwl_tx_queue), GFP_KERNEL);
 548         if (!trans_pcie->txq) {
 549                 IWL_ERR(trans, "Not enough memory for txq\n");
 550                 ret = ENOMEM;
 551                 goto error;
 552         }
 553
 554         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 555         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
 556                 slots_num = (txq_id == trans->shrd->cmd_queue) ?
 557                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 558                 ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id],
 559                                           slots_num, txq_id);
 560                 if (ret) {
 561                         IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
 562                         goto error;
 563                 }
 564         }
 565
 566         return 0;
 567
 568 error:
 569         iwl_trans_pcie_tx_free(trans);
 570
 571         return ret;
 572 }
 573 static int iwl_tx_init(struct iwl_trans *trans)
 574 {
 575         int ret;
 576         int txq_id, slots_num;
 577         unsigned long flags;
 578         bool alloc = false;
 579         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 580
 581         if (!trans_pcie->txq) {
 582                 ret = iwl_trans_tx_alloc(trans);
 583                 if (ret)
 584                         goto error;
 585                 alloc = true;
 586         }
 587
 588         spin_lock_irqsave(&trans->shrd->lock, flags);
 589
 590         /* Turn off all Tx DMA fifos */
 591         iwl_write_prph(trans, SCD_TXFACT, 0);
 592
 593         /* Tell NIC where to find the "keep warm" buffer */
 594         iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
 595                            trans_pcie->kw.dma >> 4);
 596
 597         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 598
 599         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 600         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
 601                 slots_num = (txq_id == trans->shrd->cmd_queue) ?
 602                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 603                 ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id],
 604                                          slots_num, txq_id);
 605                 if (ret) {
 606                         IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
 607                         goto error;
 608                 }
 609         }
 610
 611         return 0;
 612 error:
 613         /*Upon error, free only if we allocated something */
 614         if (alloc)
 615                 iwl_trans_pcie_tx_free(trans);
 616         return ret;
 617 }
 618
 619 static void iwl_set_pwr_vmain(struct iwl_trans *trans)
 620 {
 621 /*
 622  * (for documentation purposes)
 623  * to set power to V_AUX, do:
 624
 625                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
 626                         iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 627                                                APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 628                                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 629  */
 630
 631         iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 632                                APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 633                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 634 }
 635
 636 /* PCI registers */
 637 #define PCI_CFG_RETRY_TIMEOUT   0x041
 638 #define PCI_CFG_LINK_CTRL_VAL_L0S_EN    0x01
 639 #define PCI_CFG_LINK_CTRL_VAL_L1_EN     0x02
 640
 641 static u16 iwl_pciexp_link_ctrl(struct iwl_trans *trans)
 642 {
 643         int pos;
 644         u16 pci_lnk_ctl;
 645         struct iwl_trans_pcie *trans_pcie =
 646                 IWL_TRANS_GET_PCIE_TRANS(trans);
 647
 648         struct pci_dev *pci_dev = trans_pcie->pci_dev;
 649
 650         pos = pci_pcie_cap(pci_dev);
 651         pci_read_config_word(pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
 652         return pci_lnk_ctl;
 653 }
 654
 655 static void iwl_apm_config(struct iwl_trans *trans)
 656 {
 657         /*
 658          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 659          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 660          * If so (likely), disable L0S, so device moves directly L0->L1;
 661          *    costs negligible amount of power savings.
 662          * If not (unlikely), enable L0S, so there is at least some
 663          *    power savings, even without L1.
 664          */
 665         u16 lctl = iwl_pciexp_link_ctrl(trans);
 666
 667         if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
 668                                 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
 669                 /* L1-ASPM enabled; disable(!) L0S */
 670                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 671                 dev_printk(KERN_INFO, trans->dev,
 672                            "L1 Enabled; Disabling L0S\n");
 673         } else {
 674                 /* L1-ASPM disabled; enable(!) L0S */
 675                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 676                 dev_printk(KERN_INFO, trans->dev,
 677                            "L1 Disabled; Enabling L0S\n");
 678         }
 679 }
 680
 681 /*
 682  * Start up NIC's basic functionality after it has been reset
 683  * (e.g. after platform boot, or shutdown via iwl_apm_stop())
 684  * NOTE:  This does not load uCode nor start the embedded processor
 685  */
 686 static int iwl_apm_init(struct iwl_trans *trans)
 687 {
 688         int ret = 0;
 689         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 690
 691         /*
 692          * Use "set_bit" below rather than "write", to preserve any hardware
 693          * bits already set by default after reset.
 694          */
 695
 696         /* Disable L0S exit timer (platform NMI Work/Around) */
 697         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 698                           CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 699
 700         /*
 701          * Disable L0s without affecting L1;
 702          *  don't wait for ICH L0s (ICH bug W/A)
 703          */
 704         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 705                           CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 706
 707         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 708         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 709
 710         /*
 711          * Enable HAP INTA (interrupt from management bus) to
 712          * wake device's PCI Express link L1a -> L0s
 713          */
 714         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 715                                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 716
 717         iwl_apm_config(trans);
 718
 719         /* Configure analog phase-lock-loop before activating to D0A */
 720         if (cfg(trans)->base_params->pll_cfg_val)
 721                 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
 722                             cfg(trans)->base_params->pll_cfg_val);
 723
 724         /*
 725          * Set "initialization complete" bit to move adapter from
 726          * D0U* --> D0A* (powered-up active) state.
 727          */
 728         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 729
 730         /*
 731          * Wait for clock stabilization; once stabilized, access to
 732          * device-internal resources is supported, e.g. iwl_write_prph()
 733          * and accesses to uCode SRAM.
 734          */
 735         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 736                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 737                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 738         if (ret < 0) {
 739                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 740                 goto out;
 741         }
 742
 743         /*
 744          * Enable DMA clock and wait for it to stabilize.
 745          *
 746          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
 747          * do not disable clocks.  This preserves any hardware bits already
 748          * set by default in "CLK_CTRL_REG" after reset.
 749          */
 750         iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 751         udelay(20);
 752
 753         /* Disable L1-Active */
 754         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 755                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 756
 757         set_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status);
 758
 759 out:
 760         return ret;
 761 }
 762
 763 static int iwl_apm_stop_master(struct iwl_trans *trans)
 764 {
 765         int ret = 0;
 766
 767         /* stop device's busmaster DMA activity */
 768         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 769
 770         ret = iwl_poll_bit(trans, CSR_RESET,
 771                         CSR_RESET_REG_FLAG_MASTER_DISABLED,
 772                         CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 773         if (ret)
 774                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 775
 776         IWL_DEBUG_INFO(trans, "stop master\n");
 777
 778         return ret;
 779 }
 780
 781 static void iwl_apm_stop(struct iwl_trans *trans)
 782 {
 783         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 784
 785         clear_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status);
 786
 787         /* Stop device's DMA activity */
 788         iwl_apm_stop_master(trans);
 789
 790         /* Reset the entire device */
 791         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 792
 793         udelay(10);
 794
 795         /*
 796          * Clear "initialization complete" bit to move adapter from
 797          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 798          */
 799         iwl_clear_bit(trans, CSR_GP_CNTRL,
 800                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 801 }
 802
 803 static int iwl_nic_init(struct iwl_trans *trans)
 804 {
 805         unsigned long flags;
 806
 807         /* nic_init */
 808         spin_lock_irqsave(&trans->shrd->lock, flags);
 809         iwl_apm_init(trans);
 810
 811         /* Set interrupt coalescing calibration timer to default (512 usecs) */
 812         iwl_write8(trans, CSR_INT_COALESCING,
 813                 IWL_HOST_INT_CALIB_TIMEOUT_DEF);
 814
 815         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 816
 817         iwl_set_pwr_vmain(trans);
 818
 819         iwl_nic_config(priv(trans));
 820
 821 #ifndef CONFIG_IWLWIFI_IDI
 822         /* Allocate the RX queue, or reset if it is already allocated */
 823         iwl_rx_init(trans);
 824 #endif
 825
 826         /* Allocate or reset and init all Tx and Command queues */
 827         if (iwl_tx_init(trans))
 828                 return -ENOMEM;
 829
 830         if (hw_params(trans).shadow_reg_enable) {
 831                 /* enable shadow regs in HW */
 832                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL,
 833                         0x800FFFFF);
 834         }
 835
 836         set_bit(STATUS_INIT, &trans->shrd->status);
 837
 838         return 0;
 839 }
 840
 841 #define HW_READY_TIMEOUT (50)
 842
 843 /* Note: returns poll_bit return value, which is >= 0 if success */
 844 static int iwl_set_hw_ready(struct iwl_trans *trans)
 845 {
 846         int ret;
 847
 848         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 849                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 850
 851         /* See if we got it */
 852         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 853                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 854                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 855                                 HW_READY_TIMEOUT);
 856
 857         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 858         return ret;
 859 }
 860
 861 /* Note: returns standard 0/-ERROR code */
 862 static int iwl_prepare_card_hw(struct iwl_trans *trans)
 863 {
 864         int ret;
 865
 866         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 867
 868         ret = iwl_set_hw_ready(trans);
 869         /* If the card is ready, exit 0 */
 870         if (ret >= 0)
 871                 return 0;
 872
 873         /* If HW is not ready, prepare the conditions to check again */
 874         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 875                         CSR_HW_IF_CONFIG_REG_PREPARE);
 876
 877         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 878                         ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
 879                         CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
 880
 881         if (ret < 0)
 882                 return ret;
 883
 884         /* HW should be ready by now, check again. */
 885         ret = iwl_set_hw_ready(trans);
 886         if (ret >= 0)
 887                 return 0;
 888         return ret;
 889 }
 890
 891 #define IWL_AC_UNSET -1
 892
 893 struct queue_to_fifo_ac {
 894         s8 fifo, ac;
 895 };
 896
 897 static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = {
 898         { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
 899         { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
 900         { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
 901         { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
 902         { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
 903         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 904         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 905         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 906         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 907         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 908         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 909 };
 910
 911 static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = {
 912         { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
 913         { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
 914         { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
 915         { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
 916         { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, },
 917         { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, },
 918         { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, },
 919         { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, },
 920         { IWL_TX_FIFO_BE_IPAN, 2, },
 921         { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
 922         { IWL_TX_FIFO_AUX, IWL_AC_UNSET, },
 923 };
 924
 925 static const u8 iwlagn_bss_ac_to_fifo[] = {
 926         IWL_TX_FIFO_VO,
 927         IWL_TX_FIFO_VI,
 928         IWL_TX_FIFO_BE,
 929         IWL_TX_FIFO_BK,
 930 };
 931 static const u8 iwlagn_bss_ac_to_queue[] = {
 932         0, 1, 2, 3,
 933 };
 934 static const u8 iwlagn_pan_ac_to_fifo[] = {
 935         IWL_TX_FIFO_VO_IPAN,
 936         IWL_TX_FIFO_VI_IPAN,
 937         IWL_TX_FIFO_BE_IPAN,
 938         IWL_TX_FIFO_BK_IPAN,
 939 };
 940 static const u8 iwlagn_pan_ac_to_queue[] = {
 941         7, 6, 5, 4,
 942 };
 943
 944 /*
 945  * ucode
 946  */
 947 static int iwl_load_section(struct iwl_trans *trans, const char *name,
 948                                 struct fw_desc *image, u32 dst_addr)
 949 {
 950         dma_addr_t phy_addr = image->p_addr;
 951         u32 byte_cnt = image->len;
 952         int ret;
 953
 954         trans->ucode_write_complete = 0;
 955
 956         iwl_write_direct32(trans,
 957                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 958                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 959
 960         iwl_write_direct32(trans,
 961                 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
 962
 963         iwl_write_direct32(trans,
 964                 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 965                 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 966
 967         iwl_write_direct32(trans,
 968                 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 969                 (iwl_get_dma_hi_addr(phy_addr)
 970                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 971
 972         iwl_write_direct32(trans,
 973                 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 974                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 975                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 976                 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 977
 978         iwl_write_direct32(trans,
 979                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 980                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE       |
 981                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE    |
 982                 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 983
 984         IWL_DEBUG_FW(trans, "%s uCode section being loaded...\n", name);
 985         ret = wait_event_timeout(trans->shrd->wait_command_queue,
 986                                  trans->ucode_write_complete, 5 * HZ);
 987         if (!ret) {
 988                 IWL_ERR(trans, "Could not load the %s uCode section\n",
 989                         name);
 990                 return -ETIMEDOUT;
 991         }
 992
 993         return 0;
 994 }
 995
 996 static int iwl_load_given_ucode(struct iwl_trans *trans, struct fw_img *image)
 997 {
 998         int ret = 0;
 999
1000         ret = iwl_load_section(trans, "INST", &image->code,
1001                                    IWLAGN_RTC_INST_LOWER_BOUND);
1002         if (ret)
1003                 return ret;
1004
1005         ret = iwl_load_section(trans, "DATA", &image->data,
1006                                     IWLAGN_RTC_DATA_LOWER_BOUND);
1007         if (ret)
1008                 return ret;
1009
1010         /* Remove all resets to allow NIC to operate */
1011         iwl_write32(trans, CSR_RESET, 0);
1012
1013         return 0;
1014 }
1015
1016 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, struct fw_img *fw)
1017 {
1018         int ret;
1019         struct iwl_trans_pcie *trans_pcie =
1020                 IWL_TRANS_GET_PCIE_TRANS(trans);
1021
1022         trans->shrd->ucode_owner = IWL_OWNERSHIP_DRIVER;
1023         trans_pcie->ac_to_queue[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_queue;
1024         trans_pcie->ac_to_queue[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_queue;
1025
1026         trans_pcie->ac_to_fifo[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_fifo;
1027         trans_pcie->ac_to_fifo[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_fifo;
1028
1029         trans_pcie->mcast_queue[IWL_RXON_CTX_BSS] = 0;
1030         trans_pcie->mcast_queue[IWL_RXON_CTX_PAN] = IWL_IPAN_MCAST_QUEUE;
1031
1032         if ((hw_params(trans).sku & EEPROM_SKU_CAP_AMT_ENABLE) &&
1033              iwl_prepare_card_hw(trans)) {
1034                 IWL_WARN(trans, "Exit HW not ready\n");
1035                 return -EIO;
1036         }
1037
1038         /* If platform's RF_KILL switch is NOT set to KILL */
1039         if (iwl_read32(trans, CSR_GP_CNTRL) &
1040                         CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
1041                 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1042         else
1043                 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1044
1045         if (iwl_is_rfkill(trans->shrd)) {
1046                 iwl_set_hw_rfkill_state(priv(trans), true);
1047                 iwl_enable_interrupts(trans);
1048                 return -ERFKILL;
1049         }
1050
1051         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1052
1053         ret = iwl_nic_init(trans);
1054         if (ret) {
1055                 IWL_ERR(trans, "Unable to init nic\n");
1056                 return ret;
1057         }
1058
1059         /* make sure rfkill handshake bits are cleared */
1060         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1061         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1062                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1063
1064         /* clear (again), then enable host interrupts */
1065         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1066         iwl_enable_interrupts(trans);
1067
1068         /* really make sure rfkill handshake bits are cleared */
1069         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1070         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1071
1072         /* Load the given image to the HW */
1073         iwl_load_given_ucode(trans, fw);
1074
1075         return 0;
1076 }
1077
1078 /*
1079  * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1080  * must be called under priv->shrd->lock and mac access
1081  */
1082 static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
1083 {
1084         iwl_write_prph(trans, SCD_TXFACT, mask);
1085 }
1086
1087 static void iwl_tx_start(struct iwl_trans *trans)
1088 {
1089         const struct queue_to_fifo_ac *queue_to_fifo;
1090         struct iwl_trans_pcie *trans_pcie =
1091                 IWL_TRANS_GET_PCIE_TRANS(trans);
1092         u32 a;
1093         unsigned long flags;
1094         int i, chan;
1095         u32 reg_val;
1096
1097         spin_lock_irqsave(&trans->shrd->lock, flags);
1098
1099         trans_pcie->scd_base_addr =
1100                 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
1101         a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
1102         /* reset conext data memory */
1103         for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
1104                 a += 4)
1105                 iwl_write_targ_mem(trans, a, 0);
1106         /* reset tx status memory */
1107         for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
1108                 a += 4)
1109                 iwl_write_targ_mem(trans, a, 0);
1110         for (; a < trans_pcie->scd_base_addr +
1111                SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(trans).max_txq_num);
1112                a += 4)
1113                 iwl_write_targ_mem(trans, a, 0);
1114
1115         iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
1116                        trans_pcie->scd_bc_tbls.dma >> 10);
1117
1118         /* Enable DMA channel */
1119         for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
1120                 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
1121                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1122                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
1123
1124         /* Update FH chicken bits */
1125         reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
1126         iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
1127                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
1128
1129         iwl_write_prph(trans, SCD_QUEUECHAIN_SEL,
1130                 SCD_QUEUECHAIN_SEL_ALL(trans));
1131         iwl_write_prph(trans, SCD_AGGR_SEL, 0);
1132
1133         /* initiate the queues */
1134         for (i = 0; i < hw_params(trans).max_txq_num; i++) {
1135                 iwl_write_prph(trans, SCD_QUEUE_RDPTR(i), 0);
1136                 iwl_write_direct32(trans, HBUS_TARG_WRPTR, 0 | (i << 8));
1137                 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
1138                                 SCD_CONTEXT_QUEUE_OFFSET(i), 0);
1139                 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
1140                                 SCD_CONTEXT_QUEUE_OFFSET(i) +
1141                                 sizeof(u32),
1142                                 ((SCD_WIN_SIZE <<
1143                                 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1144                                 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1145                                 ((SCD_FRAME_LIMIT <<
1146                                 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1147                                 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1148         }
1149
1150         iwl_write_prph(trans, SCD_INTERRUPT_MASK,
1151                         IWL_MASK(0, hw_params(trans).max_txq_num));
1152
1153         /* Activate all Tx DMA/FIFO channels */
1154         iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
1155
1156         /* map queues to FIFOs */
1157         if (trans->shrd->valid_contexts != BIT(IWL_RXON_CTX_BSS))
1158                 queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo;
1159         else
1160                 queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
1161
1162         iwl_trans_set_wr_ptrs(trans, trans->shrd->cmd_queue, 0);
1163
1164         /* make sure all queue are not stopped */
1165         memset(&trans_pcie->queue_stopped[0], 0,
1166                 sizeof(trans_pcie->queue_stopped));
1167         for (i = 0; i < 4; i++)
1168                 atomic_set(&trans_pcie->queue_stop_count[i], 0);
1169
1170         /* reset to 0 to enable all the queue first */
1171         trans_pcie->txq_ctx_active_msk = 0;
1172
1173         BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) <
1174                                                 IWLAGN_FIRST_AMPDU_QUEUE);
1175         BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) <
1176                                                 IWLAGN_FIRST_AMPDU_QUEUE);
1177
1178         for (i = 0; i < IWLAGN_FIRST_AMPDU_QUEUE; i++) {
1179                 int fifo = queue_to_fifo[i].fifo;
1180                 int ac = queue_to_fifo[i].ac;
1181
1182                 iwl_txq_ctx_activate(trans_pcie, i);
1183
1184                 if (fifo == IWL_TX_FIFO_UNUSED)
1185                         continue;
1186
1187                 if (ac != IWL_AC_UNSET)
1188                         iwl_set_swq_id(&trans_pcie->txq[i], ac, i);
1189                 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[i],
1190                                               fifo, 0);
1191         }
1192
1193         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1194
1195         /* Enable L1-Active */
1196         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
1197                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1198 }
1199
1200 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans)
1201 {
1202         iwl_reset_ict(trans);
1203         iwl_tx_start(trans);
1204 }
1205
1206 /**
1207  * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
1208  */
1209 static int iwl_trans_tx_stop(struct iwl_trans *trans)
1210 {
1211         int ch, txq_id;
1212         unsigned long flags;
1213         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1214
1215         /* Turn off all Tx DMA fifos */
1216         spin_lock_irqsave(&trans->shrd->lock, flags);
1217
1218         iwl_trans_txq_set_sched(trans, 0);
1219
1220         /* Stop each Tx DMA channel, and wait for it to be idle */
1221         for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
1222                 iwl_write_direct32(trans,
1223                                    FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
1224                 if (iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG,
1225                                     FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
1226                                     1000))
1227                         IWL_ERR(trans, "Failing on timeout while stopping"
1228                             " DMA channel %d [0x%08x]", ch,
1229                             iwl_read_direct32(trans,
1230                                               FH_TSSR_TX_STATUS_REG));
1231         }
1232         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1233
1234         if (!trans_pcie->txq) {
1235                 IWL_WARN(trans, "Stopping tx queues that aren't allocated...");
1236                 return 0;
1237         }
1238
1239         /* Unmap DMA from host system and free skb's */
1240         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++)
1241                 iwl_tx_queue_unmap(trans, txq_id);
1242
1243         return 0;
1244 }
1245
1246 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1247 {
1248         unsigned long flags;
1249         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1250
1251         /* tell the device to stop sending interrupts */
1252         spin_lock_irqsave(&trans->shrd->lock, flags);
1253         iwl_disable_interrupts(trans);
1254         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1255
1256         /* device going down, Stop using ICT table */
1257         iwl_disable_ict(trans);
1258
1259         /*
1260          * If a HW restart happens during firmware loading,
1261          * then the firmware loading might call this function
1262          * and later it might be called again due to the
1263          * restart. So don't process again if the device is
1264          * already dead.
1265          */
1266         if (test_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status)) {
1267                 iwl_trans_tx_stop(trans);
1268 #ifndef CONFIG_IWLWIFI_IDI
1269                 iwl_trans_rx_stop(trans);
1270 #endif
1271                 /* Power-down device's busmaster DMA clocks */
1272                 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1273                                APMG_CLK_VAL_DMA_CLK_RQT);
1274                 udelay(5);
1275         }
1276
1277         /* Make sure (redundant) we've released our request to stay awake */
1278         iwl_clear_bit(trans, CSR_GP_CNTRL,
1279                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1280
1281         /* Stop the device, and put it in low power state */
1282         iwl_apm_stop(trans);
1283
1284         /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1285          * Clean again the interrupt here
1286          */
1287         spin_lock_irqsave(&trans->shrd->lock, flags);
1288         iwl_disable_interrupts(trans);
1289         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1290
1291         /* wait to make sure we flush pending tasklet*/
1292         synchronize_irq(trans->irq);
1293         tasklet_kill(&trans_pcie->irq_tasklet);
1294
1295         /* stop and reset the on-board processor */
1296         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1297 }
1298
1299 static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1300                 struct iwl_device_cmd *dev_cmd, enum iwl_rxon_context_id ctx,
1301                 u8 sta_id, u8 tid)
1302 {
1303         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1304         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1305         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1306         struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload;
1307         struct iwl_cmd_meta *out_meta;
1308         struct iwl_tx_queue *txq;
1309         struct iwl_queue *q;
1310
1311         dma_addr_t phys_addr = 0;
1312         dma_addr_t txcmd_phys;
1313         dma_addr_t scratch_phys;
1314         u16 len, firstlen, secondlen;
1315         u8 wait_write_ptr = 0;
1316         u8 txq_id;
1317         bool is_agg = false;
1318         __le16 fc = hdr->frame_control;
1319         u8 hdr_len = ieee80211_hdrlen(fc);
1320         u16 __maybe_unused wifi_seq;
1321
1322         /*
1323          * Send this frame after DTIM -- there's a special queue
1324          * reserved for this for contexts that support AP mode.
1325          */
1326         if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1327                 txq_id = trans_pcie->mcast_queue[ctx];
1328
1329                 /*
1330                  * The microcode will clear the more data
1331                  * bit in the last frame it transmits.
1332                  */
1333                 hdr->frame_control |=
1334                         cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1335         } else if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)
1336                 txq_id = IWL_AUX_QUEUE;
1337         else
1338                 txq_id =
1339                     trans_pcie->ac_to_queue[ctx][skb_get_queue_mapping(skb)];
1340
1341         /* aggregation is on for this <sta,tid> */
1342         if (info->flags & IEEE80211_TX_CTL_AMPDU) {
1343                 WARN_ON(tid >= IWL_MAX_TID_COUNT);
1344                 txq_id = trans_pcie->agg_txq[sta_id][tid];
1345                 is_agg = true;
1346         }
1347
1348         txq = &trans_pcie->txq[txq_id];
1349         q = &txq->q;
1350
1351         /* In AGG mode, the index in the ring must correspond to the WiFi
1352          * sequence number. This is a HW requirements to help the SCD to parse
1353          * the BA.
1354          * Check here that the packets are in the right place on the ring.
1355          */
1356 #ifdef CONFIG_IWLWIFI_DEBUG
1357         wifi_seq = SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1358         WARN_ONCE(is_agg && ((wifi_seq & 0xff) != q->write_ptr),
1359                   "Q: %d WiFi Seq %d tfdNum %d",
1360                   txq_id, wifi_seq, q->write_ptr);
1361 #endif
1362
1363         /* Set up driver data for this TFD */
1364         txq->skbs[q->write_ptr] = skb;
1365         txq->cmd[q->write_ptr] = dev_cmd;
1366
1367         dev_cmd->hdr.cmd = REPLY_TX;
1368         dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1369                                 INDEX_TO_SEQ(q->write_ptr)));
1370
1371         /* Set up first empty entry in queue's array of Tx/cmd buffers */
1372         out_meta = &txq->meta[q->write_ptr];
1373
1374         /*
1375          * Use the first empty entry in this queue's command buffer array
1376          * to contain the Tx command and MAC header concatenated together
1377          * (payload data will be in another buffer).
1378          * Size of this varies, due to varying MAC header length.
1379          * If end is not dword aligned, we'll have 2 extra bytes at the end
1380          * of the MAC header (device reads on dword boundaries).
1381          * We'll tell device about this padding later.
1382          */
1383         len = sizeof(struct iwl_tx_cmd) +
1384                 sizeof(struct iwl_cmd_header) + hdr_len;
1385         firstlen = (len + 3) & ~3;
1386
1387         /* Tell NIC about any 2-byte padding after MAC header */
1388         if (firstlen != len)
1389                 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1390
1391         /* Physical address of this Tx command's header (not MAC header!),
1392          * within command buffer array. */
1393         txcmd_phys = dma_map_single(trans->dev,
1394                                     &dev_cmd->hdr, firstlen,
1395                                     DMA_BIDIRECTIONAL);
1396         if (unlikely(dma_mapping_error(trans->dev, txcmd_phys)))
1397                 return -1;
1398         dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1399         dma_unmap_len_set(out_meta, len, firstlen);
1400
1401         if (!ieee80211_has_morefrags(fc)) {
1402                 txq->need_update = 1;
1403         } else {
1404                 wait_write_ptr = 1;
1405                 txq->need_update = 0;
1406         }
1407
1408         /* Set up TFD's 2nd entry to point directly to remainder of skb,
1409          * if any (802.11 null frames have no payload). */
1410         secondlen = skb->len - hdr_len;
1411         if (secondlen > 0) {
1412                 phys_addr = dma_map_single(trans->dev, skb->data + hdr_len,
1413                                            secondlen, DMA_TO_DEVICE);
1414                 if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
1415                         dma_unmap_single(trans->dev,
1416                                          dma_unmap_addr(out_meta, mapping),
1417                                          dma_unmap_len(out_meta, len),
1418                                          DMA_BIDIRECTIONAL);
1419                         return -1;
1420                 }
1421         }
1422
1423         /* Attach buffers to TFD */
1424         iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1);
1425         if (secondlen > 0)
1426                 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
1427                                              secondlen, 0);
1428
1429         scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1430                                 offsetof(struct iwl_tx_cmd, scratch);
1431
1432         /* take back ownership of DMA buffer to enable update */
1433         dma_sync_single_for_cpu(trans->dev, txcmd_phys, firstlen,
1434                         DMA_BIDIRECTIONAL);
1435         tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1436         tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1437
1438         IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
1439                      le16_to_cpu(dev_cmd->hdr.sequence));
1440         IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1441         iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
1442         iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
1443
1444         /* Set up entry for this TFD in Tx byte-count array */
1445         iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1446
1447         dma_sync_single_for_device(trans->dev, txcmd_phys, firstlen,
1448                         DMA_BIDIRECTIONAL);
1449
1450         trace_iwlwifi_dev_tx(priv(trans),
1451                              &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
1452                              sizeof(struct iwl_tfd),
1453                              &dev_cmd->hdr, firstlen,
1454                              skb->data + hdr_len, secondlen);
1455
1456         /* Tell device the write index *just past* this latest filled TFD */
1457         q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1458         iwl_txq_update_write_ptr(trans, txq);
1459
1460         /*
1461          * At this point the frame is "transmitted" successfully
1462          * and we will get a TX status notification eventually,
1463          * regardless of the value of ret. "ret" only indicates
1464          * whether or not we should update the write pointer.
1465          */
1466         if (iwl_queue_space(q) < q->high_mark) {
1467                 if (wait_write_ptr) {
1468                         txq->need_update = 1;
1469                         iwl_txq_update_write_ptr(trans, txq);
1470                 } else {
1471                         iwl_stop_queue(trans, txq, "Queue is full");
1472                 }
1473         }
1474         return 0;
1475 }
1476
1477 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1478 {
1479         struct iwl_trans_pcie *trans_pcie =
1480                 IWL_TRANS_GET_PCIE_TRANS(trans);
1481         int err;
1482
1483         trans_pcie->inta_mask = CSR_INI_SET_MASK;
1484
1485         if (!trans_pcie->irq_requested) {
1486                 tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1487                         iwl_irq_tasklet, (unsigned long)trans);
1488
1489                 iwl_alloc_isr_ict(trans);
1490
1491                 err = request_irq(trans->irq, iwl_isr_ict, IRQF_SHARED,
1492                         DRV_NAME, trans);
1493                 if (err) {
1494                         IWL_ERR(trans, "Error allocating IRQ %d\n",
1495                                 trans->irq);
1496                         goto error;
1497                 }
1498
1499                 INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1500                 trans_pcie->irq_requested = true;
1501         }
1502
1503         err = iwl_prepare_card_hw(trans);
1504         if (err) {
1505                 IWL_ERR(trans, "Error while preparing HW: %d", err);
1506                 goto error;
1507         }
1508
1509         iwl_apm_init(trans);
1510
1511         /* If platform's RF_KILL switch is NOT set to KILL */
1512         if (iwl_read32(trans,
1513                         CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
1514                 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1515         else
1516                 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1517
1518         iwl_set_hw_rfkill_state(priv(trans),
1519                                 test_bit(STATUS_RF_KILL_HW,
1520                                          &trans->shrd->status));
1521
1522         return err;
1523
1524 error:
1525         iwl_free_isr_ict(trans);
1526         tasklet_kill(&trans_pcie->irq_tasklet);
1527         return err;
1528 }
1529
1530 static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans)
1531 {
1532         iwl_apm_stop(trans);
1533
1534         /* Even if we stop the HW, we still want the RF kill interrupt */
1535         IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n");
1536         iwl_write32(trans, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
1537 }
1538
1539 static int iwl_trans_pcie_reclaim(struct iwl_trans *trans, int sta_id, int tid,
1540                       int txq_id, int ssn, u32 status,
1541                       struct sk_buff_head *skbs)
1542 {
1543         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1544         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1545         /* n_bd is usually 256 => n_bd - 1 = 0xff */
1546         int tfd_num = ssn & (txq->q.n_bd - 1);
1547         int freed = 0;
1548
1549         txq->time_stamp = jiffies;
1550
1551         if (unlikely(txq_id >= IWLAGN_FIRST_AMPDU_QUEUE &&
1552                      txq_id != trans_pcie->agg_txq[sta_id][tid])) {
1553                 /*
1554                  * FIXME: this is a uCode bug which need to be addressed,
1555                  * log the information and return for now.
1556                  * Since it is can possibly happen very often and in order
1557                  * not to fill the syslog, don't use IWL_ERR or IWL_WARN
1558                  */
1559                 IWL_DEBUG_TX_QUEUES(trans, "Bad queue mapping txq_id %d, "
1560                         "agg_txq[sta_id[tid] %d", txq_id,
1561                         trans_pcie->agg_txq[sta_id][tid]);
1562                 return 1;
1563         }
1564
1565         if (txq->q.read_ptr != tfd_num) {
1566                 IWL_DEBUG_TX_REPLY(trans, "[Q %d | AC %d] %d -> %d (%d)\n",
1567                                 txq_id, iwl_get_queue_ac(txq), txq->q.read_ptr,
1568                                 tfd_num, ssn);
1569                 freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
1570                 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
1571                    (!txq->sched_retry ||
1572                    status != TX_STATUS_FAIL_PASSIVE_NO_RX))
1573                         iwl_wake_queue(trans, txq, "Packets reclaimed");
1574         }
1575         return 0;
1576 }
1577
1578 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1579 {
1580         iowrite8(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1581 }
1582
1583 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1584 {
1585         iowrite32(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1586 }
1587
1588 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1589 {
1590         u32 val = ioread32(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1591         return val;
1592 }
1593
1594 static void iwl_trans_pcie_free(struct iwl_trans *trans)
1595 {
1596         struct iwl_trans_pcie *trans_pcie =
1597                 IWL_TRANS_GET_PCIE_TRANS(trans);
1598
1599         iwl_calib_free_results(trans);
1600         iwl_trans_pcie_tx_free(trans);
1601 #ifndef CONFIG_IWLWIFI_IDI
1602         iwl_trans_pcie_rx_free(trans);
1603 #endif
1604         if (trans_pcie->irq_requested == true) {
1605                 free_irq(trans->irq, trans);
1606                 iwl_free_isr_ict(trans);
1607         }
1608
1609         pci_disable_msi(trans_pcie->pci_dev);
1610         pci_iounmap(trans_pcie->pci_dev, trans_pcie->hw_base);
1611         pci_release_regions(trans_pcie->pci_dev);
1612         pci_disable_device(trans_pcie->pci_dev);
1613
1614         trans->shrd->trans = NULL;
1615         kfree(trans);
1616 }
1617
1618 #ifdef CONFIG_PM_SLEEP
1619 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1620 {
1621         /*
1622          * This function is called when system goes into suspend state
1623          * mac80211 will call iwlagn_mac_stop() from the mac80211 suspend
1624          * function first but since iwlagn_mac_stop() has no knowledge of
1625          * who the caller is,
1626          * it will not call apm_ops.stop() to stop the DMA operation.
1627          * Calling apm_ops.stop here to make sure we stop the DMA.
1628          *
1629          * But of course ... if we have configured WoWLAN then we did other
1630          * things already :-)
1631          */
1632         if (!trans->shrd->wowlan) {
1633                 iwl_apm_stop(trans);
1634         } else {
1635                 iwl_disable_interrupts(trans);
1636                 iwl_clear_bit(trans, CSR_GP_CNTRL,
1637                               CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1638         }
1639
1640         return 0;
1641 }
1642
1643 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1644 {
1645         bool hw_rfkill = false;
1646
1647         iwl_enable_interrupts(trans);
1648
1649         if (!(iwl_read32(trans, CSR_GP_CNTRL) &
1650                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1651                 hw_rfkill = true;
1652
1653         if (hw_rfkill)
1654                 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1655         else
1656                 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1657
1658         iwl_set_hw_rfkill_state(priv(trans), hw_rfkill);
1659
1660         return 0;
1661 }
1662 #endif /* CONFIG_PM_SLEEP */
1663
1664 static void iwl_trans_pcie_wake_any_queue(struct iwl_trans *trans,
1665                                           enum iwl_rxon_context_id ctx,
1666                                           const char *msg)
1667 {
1668         u8 ac, txq_id;
1669         struct iwl_trans_pcie *trans_pcie =
1670                 IWL_TRANS_GET_PCIE_TRANS(trans);
1671
1672         for (ac = 0; ac < AC_NUM; ac++) {
1673                 txq_id = trans_pcie->ac_to_queue[ctx][ac];
1674                 IWL_DEBUG_TX_QUEUES(trans, "Queue Status: Q[%d] %s\n",
1675                         ac,
1676                         (atomic_read(&trans_pcie->queue_stop_count[ac]) > 0)
1677                               ? "stopped" : "awake");
1678                 iwl_wake_queue(trans, &trans_pcie->txq[txq_id], msg);
1679         }
1680 }
1681
1682 static void iwl_trans_pcie_stop_queue(struct iwl_trans *trans, int txq_id,
1683                                       const char *msg)
1684 {
1685         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1686
1687         iwl_stop_queue(trans, &trans_pcie->txq[txq_id], msg);
1688 }
1689
1690 #define IWL_FLUSH_WAIT_MS       2000
1691
1692 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
1693 {
1694         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1695         struct iwl_tx_queue *txq;
1696         struct iwl_queue *q;
1697         int cnt;
1698         unsigned long now = jiffies;
1699         int ret = 0;
1700
1701         /* waiting for all the tx frames complete might take a while */
1702         for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1703                 if (cnt == trans->shrd->cmd_queue)
1704                         continue;
1705                 txq = &trans_pcie->txq[cnt];
1706                 q = &txq->q;
1707                 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1708                        now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1709                         msleep(1);
1710
1711                 if (q->read_ptr != q->write_ptr) {
1712                         IWL_ERR(trans, "fail to flush all tx fifo queues\n");
1713                         ret = -ETIMEDOUT;
1714                         break;
1715                 }
1716         }
1717         return ret;
1718 }
1719
1720 /*
1721  * On every watchdog tick we check (latest) time stamp. If it does not
1722  * change during timeout period and queue is not empty we reset firmware.
1723  */
1724 static int iwl_trans_pcie_check_stuck_queue(struct iwl_trans *trans, int cnt)
1725 {
1726         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1727         struct iwl_tx_queue *txq = &trans_pcie->txq[cnt];
1728         struct iwl_queue *q = &txq->q;
1729         unsigned long timeout;
1730
1731         if (q->read_ptr == q->write_ptr) {
1732                 txq->time_stamp = jiffies;
1733                 return 0;
1734         }
1735
1736         timeout = txq->time_stamp +
1737                   msecs_to_jiffies(hw_params(trans).wd_timeout);
1738
1739         if (time_after(jiffies, timeout)) {
1740                 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", q->id,
1741                         hw_params(trans).wd_timeout);
1742                 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1743                         q->read_ptr, q->write_ptr);
1744                 IWL_ERR(trans, "Current HW read_ptr %d write_ptr %d\n",
1745                         iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt))
1746                                 & (TFD_QUEUE_SIZE_MAX - 1),
1747                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1748                 return 1;
1749         }
1750
1751         return 0;
1752 }
1753
1754 static const char *get_fh_string(int cmd)
1755 {
1756         switch (cmd) {
1757         IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1758         IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1759         IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1760         IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1761         IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1762         IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1763         IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1764         IWL_CMD(FH_TSSR_TX_STATUS_REG);
1765         IWL_CMD(FH_TSSR_TX_ERROR_REG);
1766         default:
1767                 return "UNKNOWN";
1768         }
1769 }
1770
1771 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1772 {
1773         int i;
1774 #ifdef CONFIG_IWLWIFI_DEBUG
1775         int pos = 0;
1776         size_t bufsz = 0;
1777 #endif
1778         static const u32 fh_tbl[] = {
1779                 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1780                 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1781                 FH_RSCSR_CHNL0_WPTR,
1782                 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1783                 FH_MEM_RSSR_SHARED_CTRL_REG,
1784                 FH_MEM_RSSR_RX_STATUS_REG,
1785                 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1786                 FH_TSSR_TX_STATUS_REG,
1787                 FH_TSSR_TX_ERROR_REG
1788         };
1789 #ifdef CONFIG_IWLWIFI_DEBUG
1790         if (display) {
1791                 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1792                 *buf = kmalloc(bufsz, GFP_KERNEL);
1793                 if (!*buf)
1794                         return -ENOMEM;
1795                 pos += scnprintf(*buf + pos, bufsz - pos,
1796                                 "FH register values:\n");
1797                 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1798                         pos += scnprintf(*buf + pos, bufsz - pos,
1799                                 "  %34s: 0X%08x\n",
1800                                 get_fh_string(fh_tbl[i]),
1801                                 iwl_read_direct32(trans, fh_tbl[i]));
1802                 }
1803                 return pos;
1804         }
1805 #endif
1806         IWL_ERR(trans, "FH register values:\n");
1807         for (i = 0; i <  ARRAY_SIZE(fh_tbl); i++) {
1808                 IWL_ERR(trans, "  %34s: 0X%08x\n",
1809                         get_fh_string(fh_tbl[i]),
1810                         iwl_read_direct32(trans, fh_tbl[i]));
1811         }
1812         return 0;
1813 }
1814
1815 static const char *get_csr_string(int cmd)
1816 {
1817         switch (cmd) {
1818         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1819         IWL_CMD(CSR_INT_COALESCING);
1820         IWL_CMD(CSR_INT);
1821         IWL_CMD(CSR_INT_MASK);
1822         IWL_CMD(CSR_FH_INT_STATUS);
1823         IWL_CMD(CSR_GPIO_IN);
1824         IWL_CMD(CSR_RESET);
1825         IWL_CMD(CSR_GP_CNTRL);
1826         IWL_CMD(CSR_HW_REV);
1827         IWL_CMD(CSR_EEPROM_REG);
1828         IWL_CMD(CSR_EEPROM_GP);
1829         IWL_CMD(CSR_OTP_GP_REG);
1830         IWL_CMD(CSR_GIO_REG);
1831         IWL_CMD(CSR_GP_UCODE_REG);
1832         IWL_CMD(CSR_GP_DRIVER_REG);
1833         IWL_CMD(CSR_UCODE_DRV_GP1);
1834         IWL_CMD(CSR_UCODE_DRV_GP2);
1835         IWL_CMD(CSR_LED_REG);
1836         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1837         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1838         IWL_CMD(CSR_ANA_PLL_CFG);
1839         IWL_CMD(CSR_HW_REV_WA_REG);
1840         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1841         default:
1842                 return "UNKNOWN";
1843         }
1844 }
1845
1846 void iwl_dump_csr(struct iwl_trans *trans)
1847 {
1848         int i;
1849         static const u32 csr_tbl[] = {
1850                 CSR_HW_IF_CONFIG_REG,
1851                 CSR_INT_COALESCING,
1852                 CSR_INT,
1853                 CSR_INT_MASK,
1854                 CSR_FH_INT_STATUS,
1855                 CSR_GPIO_IN,
1856                 CSR_RESET,
1857                 CSR_GP_CNTRL,
1858                 CSR_HW_REV,
1859                 CSR_EEPROM_REG,
1860                 CSR_EEPROM_GP,
1861                 CSR_OTP_GP_REG,
1862                 CSR_GIO_REG,
1863                 CSR_GP_UCODE_REG,
1864                 CSR_GP_DRIVER_REG,
1865                 CSR_UCODE_DRV_GP1,
1866                 CSR_UCODE_DRV_GP2,
1867                 CSR_LED_REG,
1868                 CSR_DRAM_INT_TBL_REG,
1869                 CSR_GIO_CHICKEN_BITS,
1870                 CSR_ANA_PLL_CFG,
1871                 CSR_HW_REV_WA_REG,
1872                 CSR_DBG_HPET_MEM_REG
1873         };
1874         IWL_ERR(trans, "CSR values:\n");
1875         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1876                 "CSR_INT_PERIODIC_REG)\n");
1877         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1878                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1879                         get_csr_string(csr_tbl[i]),
1880                         iwl_read32(trans, csr_tbl[i]));
1881         }
1882 }
1883
1884 #ifdef CONFIG_IWLWIFI_DEBUGFS
1885 /* create and remove of files */
1886 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1887         if (!debugfs_create_file(#name, mode, parent, trans,            \
1888                                  &iwl_dbgfs_##name##_ops))              \
1889                 return -ENOMEM;                                         \
1890 } while (0)
1891
1892 /* file operation */
1893 #define DEBUGFS_READ_FUNC(name)                                         \
1894 static ssize_t iwl_dbgfs_##name##_read(struct file *file,               \
1895                                         char __user *user_buf,          \
1896                                         size_t count, loff_t *ppos);
1897
1898 #define DEBUGFS_WRITE_FUNC(name)                                        \
1899 static ssize_t iwl_dbgfs_##name##_write(struct file *file,              \
1900                                         const char __user *user_buf,    \
1901                                         size_t count, loff_t *ppos);
1902
1903
1904 static int iwl_dbgfs_open_file_generic(struct inode *inode, struct file *file)
1905 {
1906         file->private_data = inode->i_private;
1907         return 0;
1908 }
1909
1910 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1911         DEBUGFS_READ_FUNC(name);                                        \
1912 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1913         .read = iwl_dbgfs_##name##_read,                                \
1914         .open = iwl_dbgfs_open_file_generic,                            \
1915         .llseek = generic_file_llseek,                                  \
1916 };
1917
1918 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1919         DEBUGFS_WRITE_FUNC(name);                                       \
1920 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1921         .write = iwl_dbgfs_##name##_write,                              \
1922         .open = iwl_dbgfs_open_file_generic,                            \
1923         .llseek = generic_file_llseek,                                  \
1924 };
1925
1926 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1927         DEBUGFS_READ_FUNC(name);                                        \
1928         DEBUGFS_WRITE_FUNC(name);                                       \
1929 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1930         .write = iwl_dbgfs_##name##_write,                              \
1931         .read = iwl_dbgfs_##name##_read,                                \
1932         .open = iwl_dbgfs_open_file_generic,                            \
1933         .llseek = generic_file_llseek,                                  \
1934 };
1935
1936 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1937                                                 char __user *user_buf,
1938                                                 size_t count, loff_t *ppos)
1939 {
1940         struct iwl_trans *trans = file->private_data;
1941         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1942         struct iwl_tx_queue *txq;
1943         struct iwl_queue *q;
1944         char *buf;
1945         int pos = 0;
1946         int cnt;
1947         int ret;
1948         const size_t bufsz = sizeof(char) * 64 * hw_params(trans).max_txq_num;
1949
1950         if (!trans_pcie->txq) {
1951                 IWL_ERR(trans, "txq not ready\n");
1952                 return -EAGAIN;
1953         }
1954         buf = kzalloc(bufsz, GFP_KERNEL);
1955         if (!buf)
1956                 return -ENOMEM;
1957
1958         for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1959                 txq = &trans_pcie->txq[cnt];
1960                 q = &txq->q;
1961                 pos += scnprintf(buf + pos, bufsz - pos,
1962                                 "hwq %.2d: read=%u write=%u stop=%d"
1963                                 " swq_id=%#.2x (ac %d/hwq %d)\n",
1964                                 cnt, q->read_ptr, q->write_ptr,
1965                                 !!test_bit(cnt, trans_pcie->queue_stopped),
1966                                 txq->swq_id, txq->swq_id & 3,
1967                                 (txq->swq_id >> 2) & 0x1f);
1968                 if (cnt >= 4)
1969                         continue;
1970                 /* for the ACs, display the stop count too */
1971                 pos += scnprintf(buf + pos, bufsz - pos,
1972                         "        stop-count: %d\n",
1973                         atomic_read(&trans_pcie->queue_stop_count[cnt]));
1974         }
1975         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1976         kfree(buf);
1977         return ret;
1978 }
1979
1980 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1981                                                 char __user *user_buf,
1982                                                 size_t count, loff_t *ppos) {
1983         struct iwl_trans *trans = file->private_data;
1984         struct iwl_trans_pcie *trans_pcie =
1985                 IWL_TRANS_GET_PCIE_TRANS(trans);
1986         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
1987         char buf[256];
1988         int pos = 0;
1989         const size_t bufsz = sizeof(buf);
1990
1991         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1992                                                 rxq->read);
1993         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1994                                                 rxq->write);
1995         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1996                                                 rxq->free_count);
1997         if (rxq->rb_stts) {
1998                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1999                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
2000         } else {
2001                 pos += scnprintf(buf + pos, bufsz - pos,
2002                                         "closed_rb_num: Not Allocated\n");
2003         }
2004         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2005 }
2006
2007 static ssize_t iwl_dbgfs_log_event_read(struct file *file,
2008                                          char __user *user_buf,
2009                                          size_t count, loff_t *ppos)
2010 {
2011         struct iwl_trans *trans = file->private_data;
2012         char *buf;
2013         int pos = 0;
2014         ssize_t ret = -ENOMEM;
2015
2016         ret = pos = iwl_dump_nic_event_log(trans, true, &buf, true);
2017         if (buf) {
2018                 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2019                 kfree(buf);
2020         }
2021         return ret;
2022 }
2023
2024 static ssize_t iwl_dbgfs_log_event_write(struct file *file,
2025                                         const char __user *user_buf,
2026                                         size_t count, loff_t *ppos)
2027 {
2028         struct iwl_trans *trans = file->private_data;
2029         u32 event_log_flag;
2030         char buf[8];
2031         int buf_size;
2032
2033         memset(buf, 0, sizeof(buf));
2034         buf_size = min(count, sizeof(buf) -  1);
2035         if (copy_from_user(buf, user_buf, buf_size))
2036                 return -EFAULT;
2037         if (sscanf(buf, "%d", &event_log_flag) != 1)
2038                 return -EFAULT;
2039         if (event_log_flag == 1)
2040                 iwl_dump_nic_event_log(trans, true, NULL, false);
2041
2042         return count;
2043 }
2044
2045 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2046                                         char __user *user_buf,
2047                                         size_t count, loff_t *ppos) {
2048
2049         struct iwl_trans *trans = file->private_data;
2050         struct iwl_trans_pcie *trans_pcie =
2051                 IWL_TRANS_GET_PCIE_TRANS(trans);
2052         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2053
2054         int pos = 0;
2055         char *buf;
2056         int bufsz = 24 * 64; /* 24 items * 64 char per item */
2057         ssize_t ret;
2058
2059         buf = kzalloc(bufsz, GFP_KERNEL);
2060         if (!buf) {
2061                 IWL_ERR(trans, "Can not allocate Buffer\n");
2062                 return -ENOMEM;
2063         }
2064
2065         pos += scnprintf(buf + pos, bufsz - pos,
2066                         "Interrupt Statistics Report:\n");
2067
2068         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2069                 isr_stats->hw);
2070         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2071                 isr_stats->sw);
2072         if (isr_stats->sw || isr_stats->hw) {
2073                 pos += scnprintf(buf + pos, bufsz - pos,
2074                         "\tLast Restarting Code:  0x%X\n",
2075                         isr_stats->err_code);
2076         }
2077 #ifdef CONFIG_IWLWIFI_DEBUG
2078         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2079                 isr_stats->sch);
2080         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2081                 isr_stats->alive);
2082 #endif
2083         pos += scnprintf(buf + pos, bufsz - pos,
2084                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2085
2086         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2087                 isr_stats->ctkill);
2088
2089         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2090                 isr_stats->wakeup);
2091
2092         pos += scnprintf(buf + pos, bufsz - pos,
2093                 "Rx command responses:\t\t %u\n", isr_stats->rx);
2094
2095         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2096                 isr_stats->tx);
2097
2098         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2099                 isr_stats->unhandled);
2100
2101         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2102         kfree(buf);
2103         return ret;
2104 }
2105
2106 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2107                                          const char __user *user_buf,
2108                                          size_t count, loff_t *ppos)
2109 {
2110         struct iwl_trans *trans = file->private_data;
2111         struct iwl_trans_pcie *trans_pcie =
2112                 IWL_TRANS_GET_PCIE_TRANS(trans);
2113         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2114
2115         char buf[8];
2116         int buf_size;
2117         u32 reset_flag;
2118
2119         memset(buf, 0, sizeof(buf));
2120         buf_size = min(count, sizeof(buf) -  1);
2121         if (copy_from_user(buf, user_buf, buf_size))
2122                 return -EFAULT;
2123         if (sscanf(buf, "%x", &reset_flag) != 1)
2124                 return -EFAULT;
2125         if (reset_flag == 0)
2126                 memset(isr_stats, 0, sizeof(*isr_stats));
2127
2128         return count;
2129 }
2130
2131 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2132                                          const char __user *user_buf,
2133                                          size_t count, loff_t *ppos)
2134 {
2135         struct iwl_trans *trans = file->private_data;
2136         char buf[8];
2137         int buf_size;
2138         int csr;
2139
2140         memset(buf, 0, sizeof(buf));
2141         buf_size = min(count, sizeof(buf) -  1);
2142         if (copy_from_user(buf, user_buf, buf_size))
2143                 return -EFAULT;
2144         if (sscanf(buf, "%d", &csr) != 1)
2145                 return -EFAULT;
2146
2147         iwl_dump_csr(trans);
2148
2149         return count;
2150 }
2151
2152 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2153                                          char __user *user_buf,
2154                                          size_t count, loff_t *ppos)
2155 {
2156         struct iwl_trans *trans = file->private_data;
2157         char *buf;
2158         int pos = 0;
2159         ssize_t ret = -EFAULT;
2160
2161         ret = pos = iwl_dump_fh(trans, &buf, true);
2162         if (buf) {
2163                 ret = simple_read_from_buffer(user_buf,
2164                                               count, ppos, buf, pos);
2165                 kfree(buf);
2166         }
2167
2168         return ret;
2169 }
2170
2171 DEBUGFS_READ_WRITE_FILE_OPS(log_event);
2172 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2173 DEBUGFS_READ_FILE_OPS(fh_reg);
2174 DEBUGFS_READ_FILE_OPS(rx_queue);
2175 DEBUGFS_READ_FILE_OPS(tx_queue);
2176 DEBUGFS_WRITE_FILE_OPS(csr);
2177
2178 /*
2179  * Create the debugfs files and directories
2180  *
2181  */
2182 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2183                                         struct dentry *dir)
2184 {
2185         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2186         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2187         DEBUGFS_ADD_FILE(log_event, dir, S_IWUSR | S_IRUSR);
2188         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2189         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2190         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2191         return 0;
2192 }
2193 #else
2194 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2195                                         struct dentry *dir)
2196 { return 0; }
2197
2198 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2199
2200 const struct iwl_trans_ops trans_ops_pcie = {
2201         .start_hw = iwl_trans_pcie_start_hw,
2202         .stop_hw = iwl_trans_pcie_stop_hw,
2203         .fw_alive = iwl_trans_pcie_fw_alive,
2204         .start_fw = iwl_trans_pcie_start_fw,
2205         .stop_device = iwl_trans_pcie_stop_device,
2206
2207         .wake_any_queue = iwl_trans_pcie_wake_any_queue,
2208
2209         .send_cmd = iwl_trans_pcie_send_cmd,
2210
2211         .tx = iwl_trans_pcie_tx,
2212         .reclaim = iwl_trans_pcie_reclaim,
2213
2214         .tx_agg_disable = iwl_trans_pcie_tx_agg_disable,
2215         .tx_agg_alloc = iwl_trans_pcie_tx_agg_alloc,
2216         .tx_agg_setup = iwl_trans_pcie_tx_agg_setup,
2217
2218         .free = iwl_trans_pcie_free,
2219         .stop_queue = iwl_trans_pcie_stop_queue,
2220
2221         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2222
2223         .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty,
2224         .check_stuck_queue = iwl_trans_pcie_check_stuck_queue,
2225
2226 #ifdef CONFIG_PM_SLEEP
2227         .suspend = iwl_trans_pcie_suspend,
2228         .resume = iwl_trans_pcie_resume,
2229 #endif
2230         .write8 = iwl_trans_pcie_write8,
2231         .write32 = iwl_trans_pcie_write32,
2232         .read32 = iwl_trans_pcie_read32,
2233 };
2234
2235 struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd,
2236                                        struct pci_dev *pdev,
2237                                        const struct pci_device_id *ent)
2238 {
2239         struct iwl_trans_pcie *trans_pcie;
2240         struct iwl_trans *trans;
2241         u16 pci_cmd;
2242         int err;
2243
2244         trans = kzalloc(sizeof(struct iwl_trans) +
2245                              sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2246
2247         if (WARN_ON(!trans))
2248                 return NULL;
2249
2250         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2251
2252         trans->ops = &trans_ops_pcie;
2253         trans->shrd = shrd;
2254         trans_pcie->trans = trans;
2255         spin_lock_init(&trans->hcmd_lock);
2256
2257         /* W/A - seems to solve weird behavior. We need to remove this if we
2258          * don't want to stay in L1 all the time. This wastes a lot of power */
2259         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
2260                                 PCIE_LINK_STATE_CLKPM);
2261
2262         if (pci_enable_device(pdev)) {
2263                 err = -ENODEV;
2264                 goto out_no_pci;
2265         }
2266
2267         pci_set_master(pdev);
2268
2269         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2270         if (!err)
2271                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2272         if (err) {
2273                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2274                 if (!err)
2275                         err = pci_set_consistent_dma_mask(pdev,
2276                                                         DMA_BIT_MASK(32));
2277                 /* both attempts failed: */
2278                 if (err) {
2279                         dev_printk(KERN_ERR, &pdev->dev,
2280                                    "No suitable DMA available.\n");
2281                         goto out_pci_disable_device;
2282                 }
2283         }
2284
2285         err = pci_request_regions(pdev, DRV_NAME);
2286         if (err) {
2287                 dev_printk(KERN_ERR, &pdev->dev, "pci_request_regions failed");
2288                 goto out_pci_disable_device;
2289         }
2290
2291         trans_pcie->hw_base = pci_iomap(pdev, 0, 0);
2292         if (!trans_pcie->hw_base) {
2293                 dev_printk(KERN_ERR, &pdev->dev, "pci_iomap failed");
2294                 err = -ENODEV;
2295                 goto out_pci_release_regions;
2296         }
2297
2298         dev_printk(KERN_INFO, &pdev->dev,
2299                 "pci_resource_len = 0x%08llx\n",
2300                 (unsigned long long) pci_resource_len(pdev, 0));
2301         dev_printk(KERN_INFO, &pdev->dev,
2302                 "pci_resource_base = %p\n", trans_pcie->hw_base);
2303
2304         dev_printk(KERN_INFO, &pdev->dev,
2305                 "HW Revision ID = 0x%X\n", pdev->revision);
2306
2307         /* We disable the RETRY_TIMEOUT register (0x41) to keep
2308          * PCI Tx retries from interfering with C3 CPU state */
2309         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2310
2311         err = pci_enable_msi(pdev);
2312         if (err)
2313                 dev_printk(KERN_ERR, &pdev->dev,
2314                         "pci_enable_msi failed(0X%x)", err);
2315
2316         trans->dev = &pdev->dev;
2317         trans->irq = pdev->irq;
2318         trans_pcie->pci_dev = pdev;
2319
2320         /* TODO: Move this away, not needed if not MSI */
2321         /* enable rfkill interrupt: hw bug w/a */
2322         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2323         if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2324                 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2325                 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2326         }
2327
2328         return trans;
2329
2330 out_pci_release_regions:
2331         pci_release_regions(pdev);
2332 out_pci_disable_device:
2333         pci_disable_device(pdev);
2334 out_no_pci:
2335         kfree(trans);
2336         return NULL;
2337 }
2338