Pileus Git - ~andy/linux/blob - drivers/net/wireless/iwlwifi/iwl-trans-pcie.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  22  * USA
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  25  * in the file called LICENSE.GPL.
  26  *
  27  * Contact Information:
  28  *  Intel Linux Wireless <ilw@linux.intel.com>
  29  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  30  *
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  32  *
  33  * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
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  37  * modification, are permitted provided that the following conditions
  38  * are met:
  39  *
  40  *  * Redistributions of source code must retain the above copyright
  41  *    notice, this list of conditions and the following disclaimer.
  42  *  * Redistributions in binary form must reproduce the above copyright
  43  *    notice, this list of conditions and the following disclaimer in
  44  *    the documentation and/or other materials provided with the
  45  *    distribution.
  46  *  * Neither the name Intel Corporation nor the names of its
  47  *    contributors may be used to endorse or promote products derived
  48  *    from this software without specific prior written permission.
  49  *
  50  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  55  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  56  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  57  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  58  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63 #include <linux/pci.h>
  64 #include <linux/pci-aspm.h>
  65 #include <linux/interrupt.h>
  66 #include <linux/debugfs.h>
  67 #include <linux/bitops.h>
  68 #include <linux/gfp.h>
  69
  70 #include "iwl-trans.h"
  71 #include "iwl-trans-pcie-int.h"
  72 #include "iwl-csr.h"
  73 #include "iwl-prph.h"
  74 #include "iwl-shared.h"
  75 #include "iwl-eeprom.h"
  76 #include "iwl-agn-hw.h"
  77 #include "iwl-core.h"
  78
  79 static int iwl_trans_rx_alloc(struct iwl_trans *trans)
  80 {
  81         struct iwl_trans_pcie *trans_pcie =
  82                 IWL_TRANS_GET_PCIE_TRANS(trans);
  83         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
  84         struct device *dev = trans->dev;
  85
  86         memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
  87
  88         spin_lock_init(&rxq->lock);
  89
  90         if (WARN_ON(rxq->bd || rxq->rb_stts))
  91                 return -EINVAL;
  92
  93         /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
  94         rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
  95                                       &rxq->bd_dma, GFP_KERNEL);
  96         if (!rxq->bd)
  97                 goto err_bd;
  98
  99         /*Allocate the driver's pointer to receive buffer status */
 100         rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
 101                                            &rxq->rb_stts_dma, GFP_KERNEL);
 102         if (!rxq->rb_stts)
 103                 goto err_rb_stts;
 104
 105         return 0;
 106
 107 err_rb_stts:
 108         dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
 109                         rxq->bd, rxq->bd_dma);
 110         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 111         rxq->bd = NULL;
 112 err_bd:
 113         return -ENOMEM;
 114 }
 115
 116 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
 117 {
 118         struct iwl_trans_pcie *trans_pcie =
 119                 IWL_TRANS_GET_PCIE_TRANS(trans);
 120         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 121         int i;
 122
 123         /* Fill the rx_used queue with _all_ of the Rx buffers */
 124         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
 125                 /* In the reset function, these buffers may have been allocated
 126                  * to an SKB, so we need to unmap and free potential storage */
 127                 if (rxq->pool[i].page != NULL) {
 128                         dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
 129                                 PAGE_SIZE << hw_params(trans).rx_page_order,
 130                                 DMA_FROM_DEVICE);
 131                         __free_pages(rxq->pool[i].page,
 132                                      hw_params(trans).rx_page_order);
 133                         rxq->pool[i].page = NULL;
 134                 }
 135                 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
 136         }
 137 }
 138
 139 static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
 140                                  struct iwl_rx_queue *rxq)
 141 {
 142         u32 rb_size;
 143         const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
 144         u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */
 145
 146         if (iwlagn_mod_params.amsdu_size_8K)
 147                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
 148         else
 149                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 150
 151         /* Stop Rx DMA */
 152         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 153
 154         /* Reset driver's Rx queue write index */
 155         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 156
 157         /* Tell device where to find RBD circular buffer in DRAM */
 158         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 159                            (u32)(rxq->bd_dma >> 8));
 160
 161         /* Tell device where in DRAM to update its Rx status */
 162         iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
 163                            rxq->rb_stts_dma >> 4);
 164
 165         /* Enable Rx DMA
 166          * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
 167          *      the credit mechanism in 5000 HW RX FIFO
 168          * Direct rx interrupts to hosts
 169          * Rx buffer size 4 or 8k
 170          * RB timeout 0x10
 171          * 256 RBDs
 172          */
 173         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
 174                            FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
 175                            FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
 176                            FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
 177                            FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
 178                            rb_size|
 179                            (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
 180                            (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
 181
 182         /* Set interrupt coalescing timer to default (2048 usecs) */
 183         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 184 }
 185
 186 static int iwl_rx_init(struct iwl_trans *trans)
 187 {
 188         struct iwl_trans_pcie *trans_pcie =
 189                 IWL_TRANS_GET_PCIE_TRANS(trans);
 190         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 191
 192         int i, err;
 193         unsigned long flags;
 194
 195         if (!rxq->bd) {
 196                 err = iwl_trans_rx_alloc(trans);
 197                 if (err)
 198                         return err;
 199         }
 200
 201         spin_lock_irqsave(&rxq->lock, flags);
 202         INIT_LIST_HEAD(&rxq->rx_free);
 203         INIT_LIST_HEAD(&rxq->rx_used);
 204
 205         iwl_trans_rxq_free_rx_bufs(trans);
 206
 207         for (i = 0; i < RX_QUEUE_SIZE; i++)
 208                 rxq->queue[i] = NULL;
 209
 210         /* Set us so that we have processed and used all buffers, but have
 211          * not restocked the Rx queue with fresh buffers */
 212         rxq->read = rxq->write = 0;
 213         rxq->write_actual = 0;
 214         rxq->free_count = 0;
 215         spin_unlock_irqrestore(&rxq->lock, flags);
 216
 217         iwlagn_rx_replenish(trans);
 218
 219         iwl_trans_rx_hw_init(trans, rxq);
 220
 221         spin_lock_irqsave(&trans->shrd->lock, flags);
 222         rxq->need_update = 1;
 223         iwl_rx_queue_update_write_ptr(trans, rxq);
 224         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 225
 226         return 0;
 227 }
 228
 229 static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
 230 {
 231         struct iwl_trans_pcie *trans_pcie =
 232                 IWL_TRANS_GET_PCIE_TRANS(trans);
 233         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 234
 235         unsigned long flags;
 236
 237         /*if rxq->bd is NULL, it means that nothing has been allocated,
 238          * exit now */
 239         if (!rxq->bd) {
 240                 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
 241                 return;
 242         }
 243
 244         spin_lock_irqsave(&rxq->lock, flags);
 245         iwl_trans_rxq_free_rx_bufs(trans);
 246         spin_unlock_irqrestore(&rxq->lock, flags);
 247
 248         dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
 249                           rxq->bd, rxq->bd_dma);
 250         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 251         rxq->bd = NULL;
 252
 253         if (rxq->rb_stts)
 254                 dma_free_coherent(trans->dev,
 255                                   sizeof(struct iwl_rb_status),
 256                                   rxq->rb_stts, rxq->rb_stts_dma);
 257         else
 258                 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
 259         memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
 260         rxq->rb_stts = NULL;
 261 }
 262
 263 static int iwl_trans_rx_stop(struct iwl_trans *trans)
 264 {
 265
 266         /* stop Rx DMA */
 267         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 268         return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
 269                             FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
 270 }
 271
 272 static inline int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
 273                                     struct iwl_dma_ptr *ptr, size_t size)
 274 {
 275         if (WARN_ON(ptr->addr))
 276                 return -EINVAL;
 277
 278         ptr->addr = dma_alloc_coherent(trans->dev, size,
 279                                        &ptr->dma, GFP_KERNEL);
 280         if (!ptr->addr)
 281                 return -ENOMEM;
 282         ptr->size = size;
 283         return 0;
 284 }
 285
 286 static inline void iwlagn_free_dma_ptr(struct iwl_trans *trans,
 287                                     struct iwl_dma_ptr *ptr)
 288 {
 289         if (unlikely(!ptr->addr))
 290                 return;
 291
 292         dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
 293         memset(ptr, 0, sizeof(*ptr));
 294 }
 295
 296 static int iwl_trans_txq_alloc(struct iwl_trans *trans,
 297                                 struct iwl_tx_queue *txq, int slots_num,
 298                                 u32 txq_id)
 299 {
 300         size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
 301         int i;
 302
 303         if (WARN_ON(txq->meta || txq->cmd || txq->skbs || txq->tfds))
 304                 return -EINVAL;
 305
 306         txq->q.n_window = slots_num;
 307
 308         txq->meta = kcalloc(slots_num, sizeof(txq->meta[0]), GFP_KERNEL);
 309         txq->cmd = kcalloc(slots_num, sizeof(txq->cmd[0]), GFP_KERNEL);
 310
 311         if (!txq->meta || !txq->cmd)
 312                 goto error;
 313
 314         if (txq_id == trans->shrd->cmd_queue)
 315                 for (i = 0; i < slots_num; i++) {
 316                         txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd),
 317                                                 GFP_KERNEL);
 318                         if (!txq->cmd[i])
 319                                 goto error;
 320                 }
 321
 322         /* Alloc driver data array and TFD circular buffer */
 323         /* Driver private data, only for Tx (not command) queues,
 324          * not shared with device. */
 325         if (txq_id != trans->shrd->cmd_queue) {
 326                 txq->skbs = kcalloc(TFD_QUEUE_SIZE_MAX, sizeof(txq->skbs[0]),
 327                                     GFP_KERNEL);
 328                 if (!txq->skbs) {
 329                         IWL_ERR(trans, "kmalloc for auxiliary BD "
 330                                   "structures failed\n");
 331                         goto error;
 332                 }
 333         } else {
 334                 txq->skbs = NULL;
 335         }
 336
 337         /* Circular buffer of transmit frame descriptors (TFDs),
 338          * shared with device */
 339         txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
 340                                        &txq->q.dma_addr, GFP_KERNEL);
 341         if (!txq->tfds) {
 342                 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
 343                 goto error;
 344         }
 345         txq->q.id = txq_id;
 346
 347         return 0;
 348 error:
 349         kfree(txq->skbs);
 350         txq->skbs = NULL;
 351         /* since txq->cmd has been zeroed,
 352          * all non allocated cmd[i] will be NULL */
 353         if (txq->cmd && txq_id == trans->shrd->cmd_queue)
 354                 for (i = 0; i < slots_num; i++)
 355                         kfree(txq->cmd[i]);
 356         kfree(txq->meta);
 357         kfree(txq->cmd);
 358         txq->meta = NULL;
 359         txq->cmd = NULL;
 360
 361         return -ENOMEM;
 362
 363 }
 364
 365 static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
 366                       int slots_num, u32 txq_id)
 367 {
 368         int ret;
 369
 370         txq->need_update = 0;
 371         memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num);
 372
 373         /*
 374          * For the default queues 0-3, set up the swq_id
 375          * already -- all others need to get one later
 376          * (if they need one at all).
 377          */
 378         if (txq_id < 4)
 379                 iwl_set_swq_id(txq, txq_id, txq_id);
 380
 381         /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
 382          * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
 383         BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
 384
 385         /* Initialize queue's high/low-water marks, and head/tail indexes */
 386         ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
 387                         txq_id);
 388         if (ret)
 389                 return ret;
 390
 391         /*
 392          * Tell nic where to find circular buffer of Tx Frame Descriptors for
 393          * given Tx queue, and enable the DMA channel used for that queue.
 394          * Circular buffer (TFD queue in DRAM) physical base address */
 395         iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
 396                              txq->q.dma_addr >> 8);
 397
 398         return 0;
 399 }
 400
 401 /**
 402  * iwl_tx_queue_unmap -  Unmap any remaining DMA mappings and free skb's
 403  */
 404 static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
 405 {
 406         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 407         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 408         struct iwl_queue *q = &txq->q;
 409         enum dma_data_direction dma_dir;
 410         unsigned long flags;
 411         spinlock_t *lock;
 412
 413         if (!q->n_bd)
 414                 return;
 415
 416         /* In the command queue, all the TBs are mapped as BIDI
 417          * so unmap them as such.
 418          */
 419         if (txq_id == trans->shrd->cmd_queue) {
 420                 dma_dir = DMA_BIDIRECTIONAL;
 421                 lock = &trans->hcmd_lock;
 422         } else {
 423                 dma_dir = DMA_TO_DEVICE;
 424                 lock = &trans->shrd->sta_lock;
 425         }
 426
 427         spin_lock_irqsave(lock, flags);
 428         while (q->write_ptr != q->read_ptr) {
 429                 /* The read_ptr needs to bound by q->n_window */
 430                 iwlagn_txq_free_tfd(trans, txq, get_cmd_index(q, q->read_ptr),
 431                                     dma_dir);
 432                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
 433         }
 434         spin_unlock_irqrestore(lock, flags);
 435 }
 436
 437 /**
 438  * iwl_tx_queue_free - Deallocate DMA queue.
 439  * @txq: Transmit queue to deallocate.
 440  *
 441  * Empty queue by removing and destroying all BD's.
 442  * Free all buffers.
 443  * 0-fill, but do not free "txq" descriptor structure.
 444  */
 445 static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
 446 {
 447         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 448         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 449         struct device *dev = trans->dev;
 450         int i;
 451         if (WARN_ON(!txq))
 452                 return;
 453
 454         iwl_tx_queue_unmap(trans, txq_id);
 455
 456         /* De-alloc array of command/tx buffers */
 457
 458         if (txq_id == trans->shrd->cmd_queue)
 459                 for (i = 0; i < txq->q.n_window; i++)
 460                         kfree(txq->cmd[i]);
 461
 462         /* De-alloc circular buffer of TFDs */
 463         if (txq->q.n_bd) {
 464                 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
 465                                   txq->q.n_bd, txq->tfds, txq->q.dma_addr);
 466                 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
 467         }
 468
 469         /* De-alloc array of per-TFD driver data */
 470         kfree(txq->skbs);
 471         txq->skbs = NULL;
 472
 473         /* deallocate arrays */
 474         kfree(txq->cmd);
 475         kfree(txq->meta);
 476         txq->cmd = NULL;
 477         txq->meta = NULL;
 478
 479         /* 0-fill queue descriptor structure */
 480         memset(txq, 0, sizeof(*txq));
 481 }
 482
 483 /**
 484  * iwl_trans_tx_free - Free TXQ Context
 485  *
 486  * Destroy all TX DMA queues and structures
 487  */
 488 static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
 489 {
 490         int txq_id;
 491         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 492
 493         /* Tx queues */
 494         if (trans_pcie->txq) {
 495                 for (txq_id = 0;
 496                      txq_id < hw_params(trans).max_txq_num; txq_id++)
 497                         iwl_tx_queue_free(trans, txq_id);
 498         }
 499
 500         kfree(trans_pcie->txq);
 501         trans_pcie->txq = NULL;
 502
 503         iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
 504
 505         iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
 506 }
 507
 508 /**
 509  * iwl_trans_tx_alloc - allocate TX context
 510  * Allocate all Tx DMA structures and initialize them
 511  *
 512  * @param priv
 513  * @return error code
 514  */
 515 static int iwl_trans_tx_alloc(struct iwl_trans *trans)
 516 {
 517         int ret;
 518         int txq_id, slots_num;
 519         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 520
 521         u16 scd_bc_tbls_size = hw_params(trans).max_txq_num *
 522                         sizeof(struct iwlagn_scd_bc_tbl);
 523
 524         /*It is not allowed to alloc twice, so warn when this happens.
 525          * We cannot rely on the previous allocation, so free and fail */
 526         if (WARN_ON(trans_pcie->txq)) {
 527                 ret = -EINVAL;
 528                 goto error;
 529         }
 530
 531         ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
 532                                    scd_bc_tbls_size);
 533         if (ret) {
 534                 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
 535                 goto error;
 536         }
 537
 538         /* Alloc keep-warm buffer */
 539         ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
 540         if (ret) {
 541                 IWL_ERR(trans, "Keep Warm allocation failed\n");
 542                 goto error;
 543         }
 544
 545         trans_pcie->txq = kcalloc(hw_params(trans).max_txq_num,
 546                                   sizeof(struct iwl_tx_queue), GFP_KERNEL);
 547         if (!trans_pcie->txq) {
 548                 IWL_ERR(trans, "Not enough memory for txq\n");
 549                 ret = ENOMEM;
 550                 goto error;
 551         }
 552
 553         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 554         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
 555                 slots_num = (txq_id == trans->shrd->cmd_queue) ?
 556                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 557                 ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id],
 558                                           slots_num, txq_id);
 559                 if (ret) {
 560                         IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
 561                         goto error;
 562                 }
 563         }
 564
 565         return 0;
 566
 567 error:
 568         iwl_trans_pcie_tx_free(trans);
 569
 570         return ret;
 571 }
 572 static int iwl_tx_init(struct iwl_trans *trans)
 573 {
 574         int ret;
 575         int txq_id, slots_num;
 576         unsigned long flags;
 577         bool alloc = false;
 578         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 579
 580         if (!trans_pcie->txq) {
 581                 ret = iwl_trans_tx_alloc(trans);
 582                 if (ret)
 583                         goto error;
 584                 alloc = true;
 585         }
 586
 587         spin_lock_irqsave(&trans->shrd->lock, flags);
 588
 589         /* Turn off all Tx DMA fifos */
 590         iwl_write_prph(trans, SCD_TXFACT, 0);
 591
 592         /* Tell NIC where to find the "keep warm" buffer */
 593         iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
 594                            trans_pcie->kw.dma >> 4);
 595
 596         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 597
 598         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 599         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
 600                 slots_num = (txq_id == trans->shrd->cmd_queue) ?
 601                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 602                 ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id],
 603                                          slots_num, txq_id);
 604                 if (ret) {
 605                         IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
 606                         goto error;
 607                 }
 608         }
 609
 610         return 0;
 611 error:
 612         /*Upon error, free only if we allocated something */
 613         if (alloc)
 614                 iwl_trans_pcie_tx_free(trans);
 615         return ret;
 616 }
 617
 618 static void iwl_set_pwr_vmain(struct iwl_trans *trans)
 619 {
 620 /*
 621  * (for documentation purposes)
 622  * to set power to V_AUX, do:
 623
 624                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
 625                         iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 626                                                APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 627                                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 628  */
 629
 630         iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 631                                APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 632                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 633 }
 634
 635 /*
 636  * Start up NIC's basic functionality after it has been reset
 637  * (e.g. after platform boot, or shutdown via iwl_apm_stop())
 638  * NOTE:  This does not load uCode nor start the embedded processor
 639  */
 640 static int iwl_apm_init(struct iwl_trans *trans)
 641 {
 642         int ret = 0;
 643         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 644
 645         /*
 646          * Use "set_bit" below rather than "write", to preserve any hardware
 647          * bits already set by default after reset.
 648          */
 649
 650         /* Disable L0S exit timer (platform NMI Work/Around) */
 651         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 652                           CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 653
 654         /*
 655          * Disable L0s without affecting L1;
 656          *  don't wait for ICH L0s (ICH bug W/A)
 657          */
 658         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 659                           CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 660
 661         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 662         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 663
 664         /*
 665          * Enable HAP INTA (interrupt from management bus) to
 666          * wake device's PCI Express link L1a -> L0s
 667          */
 668         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 669                                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 670
 671         bus_apm_config(bus(trans));
 672
 673         /* Configure analog phase-lock-loop before activating to D0A */
 674         if (cfg(trans)->base_params->pll_cfg_val)
 675                 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
 676                             cfg(trans)->base_params->pll_cfg_val);
 677
 678         /*
 679          * Set "initialization complete" bit to move adapter from
 680          * D0U* --> D0A* (powered-up active) state.
 681          */
 682         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 683
 684         /*
 685          * Wait for clock stabilization; once stabilized, access to
 686          * device-internal resources is supported, e.g. iwl_write_prph()
 687          * and accesses to uCode SRAM.
 688          */
 689         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 690                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 691                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 692         if (ret < 0) {
 693                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 694                 goto out;
 695         }
 696
 697         /*
 698          * Enable DMA clock and wait for it to stabilize.
 699          *
 700          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
 701          * do not disable clocks.  This preserves any hardware bits already
 702          * set by default in "CLK_CTRL_REG" after reset.
 703          */
 704         iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 705         udelay(20);
 706
 707         /* Disable L1-Active */
 708         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 709                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 710
 711         set_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status);
 712
 713 out:
 714         return ret;
 715 }
 716
 717 static int iwl_apm_stop_master(struct iwl_trans *trans)
 718 {
 719         int ret = 0;
 720
 721         /* stop device's busmaster DMA activity */
 722         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 723
 724         ret = iwl_poll_bit(trans, CSR_RESET,
 725                         CSR_RESET_REG_FLAG_MASTER_DISABLED,
 726                         CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 727         if (ret)
 728                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 729
 730         IWL_DEBUG_INFO(trans, "stop master\n");
 731
 732         return ret;
 733 }
 734
 735 static void iwl_apm_stop(struct iwl_trans *trans)
 736 {
 737         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 738
 739         clear_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status);
 740
 741         /* Stop device's DMA activity */
 742         iwl_apm_stop_master(trans);
 743
 744         /* Reset the entire device */
 745         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 746
 747         udelay(10);
 748
 749         /*
 750          * Clear "initialization complete" bit to move adapter from
 751          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 752          */
 753         iwl_clear_bit(trans, CSR_GP_CNTRL,
 754                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 755 }
 756
 757 static int iwl_nic_init(struct iwl_trans *trans)
 758 {
 759         unsigned long flags;
 760
 761         /* nic_init */
 762         spin_lock_irqsave(&trans->shrd->lock, flags);
 763         iwl_apm_init(trans);
 764
 765         /* Set interrupt coalescing calibration timer to default (512 usecs) */
 766         iwl_write8(trans, CSR_INT_COALESCING,
 767                 IWL_HOST_INT_CALIB_TIMEOUT_DEF);
 768
 769         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 770
 771         iwl_set_pwr_vmain(trans);
 772
 773         iwl_nic_config(priv(trans));
 774
 775 #ifndef CONFIG_IWLWIFI_IDI
 776         /* Allocate the RX queue, or reset if it is already allocated */
 777         iwl_rx_init(trans);
 778 #endif
 779
 780         /* Allocate or reset and init all Tx and Command queues */
 781         if (iwl_tx_init(trans))
 782                 return -ENOMEM;
 783
 784         if (hw_params(trans).shadow_reg_enable) {
 785                 /* enable shadow regs in HW */
 786                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL,
 787                         0x800FFFFF);
 788         }
 789
 790         set_bit(STATUS_INIT, &trans->shrd->status);
 791
 792         return 0;
 793 }
 794
 795 #define HW_READY_TIMEOUT (50)
 796
 797 /* Note: returns poll_bit return value, which is >= 0 if success */
 798 static int iwl_set_hw_ready(struct iwl_trans *trans)
 799 {
 800         int ret;
 801
 802         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 803                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 804
 805         /* See if we got it */
 806         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 807                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 808                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 809                                 HW_READY_TIMEOUT);
 810
 811         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 812         return ret;
 813 }
 814
 815 /* Note: returns standard 0/-ERROR code */
 816 static int iwl_prepare_card_hw(struct iwl_trans *trans)
 817 {
 818         int ret;
 819
 820         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 821
 822         ret = iwl_set_hw_ready(trans);
 823         /* If the card is ready, exit 0 */
 824         if (ret >= 0)
 825                 return 0;
 826
 827         /* If HW is not ready, prepare the conditions to check again */
 828         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 829                         CSR_HW_IF_CONFIG_REG_PREPARE);
 830
 831         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 832                         ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
 833                         CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
 834
 835         if (ret < 0)
 836                 return ret;
 837
 838         /* HW should be ready by now, check again. */
 839         ret = iwl_set_hw_ready(trans);
 840         if (ret >= 0)
 841                 return 0;
 842         return ret;
 843 }
 844
 845 #define IWL_AC_UNSET -1
 846
 847 struct queue_to_fifo_ac {
 848         s8 fifo, ac;
 849 };
 850
 851 static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = {
 852         { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
 853         { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
 854         { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
 855         { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
 856         { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
 857         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 858         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 859         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 860         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 861         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 862         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 863 };
 864
 865 static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = {
 866         { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
 867         { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
 868         { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
 869         { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
 870         { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, },
 871         { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, },
 872         { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, },
 873         { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, },
 874         { IWL_TX_FIFO_BE_IPAN, 2, },
 875         { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
 876         { IWL_TX_FIFO_AUX, IWL_AC_UNSET, },
 877 };
 878
 879 static const u8 iwlagn_bss_ac_to_fifo[] = {
 880         IWL_TX_FIFO_VO,
 881         IWL_TX_FIFO_VI,
 882         IWL_TX_FIFO_BE,
 883         IWL_TX_FIFO_BK,
 884 };
 885 static const u8 iwlagn_bss_ac_to_queue[] = {
 886         0, 1, 2, 3,
 887 };
 888 static const u8 iwlagn_pan_ac_to_fifo[] = {
 889         IWL_TX_FIFO_VO_IPAN,
 890         IWL_TX_FIFO_VI_IPAN,
 891         IWL_TX_FIFO_BE_IPAN,
 892         IWL_TX_FIFO_BK_IPAN,
 893 };
 894 static const u8 iwlagn_pan_ac_to_queue[] = {
 895         7, 6, 5, 4,
 896 };
 897
 898 static int iwl_trans_pcie_start_device(struct iwl_trans *trans)
 899 {
 900         int ret;
 901         struct iwl_trans_pcie *trans_pcie =
 902                 IWL_TRANS_GET_PCIE_TRANS(trans);
 903
 904         trans->shrd->ucode_owner = IWL_OWNERSHIP_DRIVER;
 905         trans_pcie->ac_to_queue[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_queue;
 906         trans_pcie->ac_to_queue[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_queue;
 907
 908         trans_pcie->ac_to_fifo[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_fifo;
 909         trans_pcie->ac_to_fifo[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_fifo;
 910
 911         trans_pcie->mcast_queue[IWL_RXON_CTX_BSS] = 0;
 912         trans_pcie->mcast_queue[IWL_RXON_CTX_PAN] = IWL_IPAN_MCAST_QUEUE;
 913
 914         if ((hw_params(trans).sku & EEPROM_SKU_CAP_AMT_ENABLE) &&
 915              iwl_prepare_card_hw(trans)) {
 916                 IWL_WARN(trans, "Exit HW not ready\n");
 917                 return -EIO;
 918         }
 919
 920         /* If platform's RF_KILL switch is NOT set to KILL */
 921         if (iwl_read32(trans, CSR_GP_CNTRL) &
 922                         CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
 923                 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
 924         else
 925                 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
 926
 927         if (iwl_is_rfkill(trans->shrd)) {
 928                 iwl_set_hw_rfkill_state(priv(trans), true);
 929                 iwl_enable_interrupts(trans);
 930                 return -ERFKILL;
 931         }
 932
 933         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
 934
 935         ret = iwl_nic_init(trans);
 936         if (ret) {
 937                 IWL_ERR(trans, "Unable to init nic\n");
 938                 return ret;
 939         }
 940
 941         /* make sure rfkill handshake bits are cleared */
 942         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 943         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
 944                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 945
 946         /* clear (again), then enable host interrupts */
 947         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
 948         iwl_enable_interrupts(trans);
 949
 950         /* really make sure rfkill handshake bits are cleared */
 951         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 952         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 953
 954         return 0;
 955 }
 956
 957 /*
 958  * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
 959  * must be called under priv->shrd->lock and mac access
 960  */
 961 static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
 962 {
 963         iwl_write_prph(trans, SCD_TXFACT, mask);
 964 }
 965
 966 static void iwl_tx_start(struct iwl_trans *trans)
 967 {
 968         const struct queue_to_fifo_ac *queue_to_fifo;
 969         struct iwl_trans_pcie *trans_pcie =
 970                 IWL_TRANS_GET_PCIE_TRANS(trans);
 971         u32 a;
 972         unsigned long flags;
 973         int i, chan;
 974         u32 reg_val;
 975
 976         spin_lock_irqsave(&trans->shrd->lock, flags);
 977
 978         trans_pcie->scd_base_addr =
 979                 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
 980         a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
 981         /* reset conext data memory */
 982         for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
 983                 a += 4)
 984                 iwl_write_targ_mem(trans, a, 0);
 985         /* reset tx status memory */
 986         for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
 987                 a += 4)
 988                 iwl_write_targ_mem(trans, a, 0);
 989         for (; a < trans_pcie->scd_base_addr +
 990                SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(trans).max_txq_num);
 991                a += 4)
 992                 iwl_write_targ_mem(trans, a, 0);
 993
 994         iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
 995                        trans_pcie->scd_bc_tbls.dma >> 10);
 996
 997         /* Enable DMA channel */
 998         for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
 999                 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
1000                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1001                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
1002
1003         /* Update FH chicken bits */
1004         reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
1005         iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
1006                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
1007
1008         iwl_write_prph(trans, SCD_QUEUECHAIN_SEL,
1009                 SCD_QUEUECHAIN_SEL_ALL(trans));
1010         iwl_write_prph(trans, SCD_AGGR_SEL, 0);
1011
1012         /* initiate the queues */
1013         for (i = 0; i < hw_params(trans).max_txq_num; i++) {
1014                 iwl_write_prph(trans, SCD_QUEUE_RDPTR(i), 0);
1015                 iwl_write_direct32(trans, HBUS_TARG_WRPTR, 0 | (i << 8));
1016                 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
1017                                 SCD_CONTEXT_QUEUE_OFFSET(i), 0);
1018                 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
1019                                 SCD_CONTEXT_QUEUE_OFFSET(i) +
1020                                 sizeof(u32),
1021                                 ((SCD_WIN_SIZE <<
1022                                 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1023                                 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1024                                 ((SCD_FRAME_LIMIT <<
1025                                 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1026                                 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1027         }
1028
1029         iwl_write_prph(trans, SCD_INTERRUPT_MASK,
1030                         IWL_MASK(0, hw_params(trans).max_txq_num));
1031
1032         /* Activate all Tx DMA/FIFO channels */
1033         iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
1034
1035         /* map queues to FIFOs */
1036         if (trans->shrd->valid_contexts != BIT(IWL_RXON_CTX_BSS))
1037                 queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo;
1038         else
1039                 queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
1040
1041         iwl_trans_set_wr_ptrs(trans, trans->shrd->cmd_queue, 0);
1042
1043         /* make sure all queue are not stopped */
1044         memset(&trans_pcie->queue_stopped[0], 0,
1045                 sizeof(trans_pcie->queue_stopped));
1046         for (i = 0; i < 4; i++)
1047                 atomic_set(&trans_pcie->queue_stop_count[i], 0);
1048
1049         /* reset to 0 to enable all the queue first */
1050         trans_pcie->txq_ctx_active_msk = 0;
1051
1052         BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) <
1053                                                 IWLAGN_FIRST_AMPDU_QUEUE);
1054         BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) <
1055                                                 IWLAGN_FIRST_AMPDU_QUEUE);
1056
1057         for (i = 0; i < IWLAGN_FIRST_AMPDU_QUEUE; i++) {
1058                 int fifo = queue_to_fifo[i].fifo;
1059                 int ac = queue_to_fifo[i].ac;
1060
1061                 iwl_txq_ctx_activate(trans_pcie, i);
1062
1063                 if (fifo == IWL_TX_FIFO_UNUSED)
1064                         continue;
1065
1066                 if (ac != IWL_AC_UNSET)
1067                         iwl_set_swq_id(&trans_pcie->txq[i], ac, i);
1068                 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[i],
1069                                               fifo, 0);
1070         }
1071
1072         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1073
1074         /* Enable L1-Active */
1075         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
1076                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1077 }
1078
1079 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans)
1080 {
1081         iwl_reset_ict(trans);
1082         iwl_tx_start(trans);
1083 }
1084
1085 /**
1086  * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
1087  */
1088 static int iwl_trans_tx_stop(struct iwl_trans *trans)
1089 {
1090         int ch, txq_id;
1091         unsigned long flags;
1092         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1093
1094         /* Turn off all Tx DMA fifos */
1095         spin_lock_irqsave(&trans->shrd->lock, flags);
1096
1097         iwl_trans_txq_set_sched(trans, 0);
1098
1099         /* Stop each Tx DMA channel, and wait for it to be idle */
1100         for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
1101                 iwl_write_direct32(trans,
1102                                    FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
1103                 if (iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG,
1104                                     FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
1105                                     1000))
1106                         IWL_ERR(trans, "Failing on timeout while stopping"
1107                             " DMA channel %d [0x%08x]", ch,
1108                             iwl_read_direct32(trans,
1109                                               FH_TSSR_TX_STATUS_REG));
1110         }
1111         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1112
1113         if (!trans_pcie->txq) {
1114                 IWL_WARN(trans, "Stopping tx queues that aren't allocated...");
1115                 return 0;
1116         }
1117
1118         /* Unmap DMA from host system and free skb's */
1119         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++)
1120                 iwl_tx_queue_unmap(trans, txq_id);
1121
1122         return 0;
1123 }
1124
1125 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1126 {
1127         unsigned long flags;
1128         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1129
1130         /* tell the device to stop sending interrupts */
1131         spin_lock_irqsave(&trans->shrd->lock, flags);
1132         iwl_disable_interrupts(trans);
1133         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1134
1135         /* device going down, Stop using ICT table */
1136         iwl_disable_ict(trans);
1137
1138         /*
1139          * If a HW restart happens during firmware loading,
1140          * then the firmware loading might call this function
1141          * and later it might be called again due to the
1142          * restart. So don't process again if the device is
1143          * already dead.
1144          */
1145         if (test_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status)) {
1146                 iwl_trans_tx_stop(trans);
1147 #ifndef CONFIG_IWLWIFI_IDI
1148                 iwl_trans_rx_stop(trans);
1149 #endif
1150                 /* Power-down device's busmaster DMA clocks */
1151                 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1152                                APMG_CLK_VAL_DMA_CLK_RQT);
1153                 udelay(5);
1154         }
1155
1156         /* Make sure (redundant) we've released our request to stay awake */
1157         iwl_clear_bit(trans, CSR_GP_CNTRL,
1158                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1159
1160         /* Stop the device, and put it in low power state */
1161         iwl_apm_stop(trans);
1162
1163         /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1164          * Clean again the interrupt here
1165          */
1166         spin_lock_irqsave(&trans->shrd->lock, flags);
1167         iwl_disable_interrupts(trans);
1168         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1169
1170         /* wait to make sure we flush pending tasklet*/
1171         synchronize_irq(trans->irq);
1172         tasklet_kill(&trans_pcie->irq_tasklet);
1173
1174         /* stop and reset the on-board processor */
1175         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1176 }
1177
1178 static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1179                 struct iwl_device_cmd *dev_cmd, enum iwl_rxon_context_id ctx,
1180                 u8 sta_id, u8 tid)
1181 {
1182         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1183         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1184         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1185         struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload;
1186         struct iwl_cmd_meta *out_meta;
1187         struct iwl_tx_queue *txq;
1188         struct iwl_queue *q;
1189
1190         dma_addr_t phys_addr = 0;
1191         dma_addr_t txcmd_phys;
1192         dma_addr_t scratch_phys;
1193         u16 len, firstlen, secondlen;
1194         u8 wait_write_ptr = 0;
1195         u8 txq_id;
1196         bool is_agg = false;
1197         __le16 fc = hdr->frame_control;
1198         u8 hdr_len = ieee80211_hdrlen(fc);
1199         u16 __maybe_unused wifi_seq;
1200
1201         /*
1202          * Send this frame after DTIM -- there's a special queue
1203          * reserved for this for contexts that support AP mode.
1204          */
1205         if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1206                 txq_id = trans_pcie->mcast_queue[ctx];
1207
1208                 /*
1209                  * The microcode will clear the more data
1210                  * bit in the last frame it transmits.
1211                  */
1212                 hdr->frame_control |=
1213                         cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1214         } else if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)
1215                 txq_id = IWL_AUX_QUEUE;
1216         else
1217                 txq_id =
1218                     trans_pcie->ac_to_queue[ctx][skb_get_queue_mapping(skb)];
1219
1220         /* aggregation is on for this <sta,tid> */
1221         if (info->flags & IEEE80211_TX_CTL_AMPDU) {
1222                 WARN_ON(tid >= IWL_MAX_TID_COUNT);
1223                 txq_id = trans_pcie->agg_txq[sta_id][tid];
1224                 is_agg = true;
1225         }
1226
1227         txq = &trans_pcie->txq[txq_id];
1228         q = &txq->q;
1229
1230         /* In AGG mode, the index in the ring must correspond to the WiFi
1231          * sequence number. This is a HW requirements to help the SCD to parse
1232          * the BA.
1233          * Check here that the packets are in the right place on the ring.
1234          */
1235 #ifdef CONFIG_IWLWIFI_DEBUG
1236         wifi_seq = SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1237         WARN_ONCE(is_agg && ((wifi_seq & 0xff) != q->write_ptr),
1238                   "Q: %d WiFi Seq %d tfdNum %d",
1239                   txq_id, wifi_seq, q->write_ptr);
1240 #endif
1241
1242         /* Set up driver data for this TFD */
1243         txq->skbs[q->write_ptr] = skb;
1244         txq->cmd[q->write_ptr] = dev_cmd;
1245
1246         dev_cmd->hdr.cmd = REPLY_TX;
1247         dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1248                                 INDEX_TO_SEQ(q->write_ptr)));
1249
1250         /* Set up first empty entry in queue's array of Tx/cmd buffers */
1251         out_meta = &txq->meta[q->write_ptr];
1252
1253         /*
1254          * Use the first empty entry in this queue's command buffer array
1255          * to contain the Tx command and MAC header concatenated together
1256          * (payload data will be in another buffer).
1257          * Size of this varies, due to varying MAC header length.
1258          * If end is not dword aligned, we'll have 2 extra bytes at the end
1259          * of the MAC header (device reads on dword boundaries).
1260          * We'll tell device about this padding later.
1261          */
1262         len = sizeof(struct iwl_tx_cmd) +
1263                 sizeof(struct iwl_cmd_header) + hdr_len;
1264         firstlen = (len + 3) & ~3;
1265
1266         /* Tell NIC about any 2-byte padding after MAC header */
1267         if (firstlen != len)
1268                 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1269
1270         /* Physical address of this Tx command's header (not MAC header!),
1271          * within command buffer array. */
1272         txcmd_phys = dma_map_single(trans->dev,
1273                                     &dev_cmd->hdr, firstlen,
1274                                     DMA_BIDIRECTIONAL);
1275         if (unlikely(dma_mapping_error(trans->dev, txcmd_phys)))
1276                 return -1;
1277         dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1278         dma_unmap_len_set(out_meta, len, firstlen);
1279
1280         if (!ieee80211_has_morefrags(fc)) {
1281                 txq->need_update = 1;
1282         } else {
1283                 wait_write_ptr = 1;
1284                 txq->need_update = 0;
1285         }
1286
1287         /* Set up TFD's 2nd entry to point directly to remainder of skb,
1288          * if any (802.11 null frames have no payload). */
1289         secondlen = skb->len - hdr_len;
1290         if (secondlen > 0) {
1291                 phys_addr = dma_map_single(trans->dev, skb->data + hdr_len,
1292                                            secondlen, DMA_TO_DEVICE);
1293                 if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
1294                         dma_unmap_single(trans->dev,
1295                                          dma_unmap_addr(out_meta, mapping),
1296                                          dma_unmap_len(out_meta, len),
1297                                          DMA_BIDIRECTIONAL);
1298                         return -1;
1299                 }
1300         }
1301
1302         /* Attach buffers to TFD */
1303         iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1);
1304         if (secondlen > 0)
1305                 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
1306                                              secondlen, 0);
1307
1308         scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1309                                 offsetof(struct iwl_tx_cmd, scratch);
1310
1311         /* take back ownership of DMA buffer to enable update */
1312         dma_sync_single_for_cpu(trans->dev, txcmd_phys, firstlen,
1313                         DMA_BIDIRECTIONAL);
1314         tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1315         tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1316
1317         IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
1318                      le16_to_cpu(dev_cmd->hdr.sequence));
1319         IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1320         iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
1321         iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
1322
1323         /* Set up entry for this TFD in Tx byte-count array */
1324         iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1325
1326         dma_sync_single_for_device(trans->dev, txcmd_phys, firstlen,
1327                         DMA_BIDIRECTIONAL);
1328
1329         trace_iwlwifi_dev_tx(priv(trans),
1330                              &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
1331                              sizeof(struct iwl_tfd),
1332                              &dev_cmd->hdr, firstlen,
1333                              skb->data + hdr_len, secondlen);
1334
1335         /* Tell device the write index *just past* this latest filled TFD */
1336         q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1337         iwl_txq_update_write_ptr(trans, txq);
1338
1339         /*
1340          * At this point the frame is "transmitted" successfully
1341          * and we will get a TX status notification eventually,
1342          * regardless of the value of ret. "ret" only indicates
1343          * whether or not we should update the write pointer.
1344          */
1345         if (iwl_queue_space(q) < q->high_mark) {
1346                 if (wait_write_ptr) {
1347                         txq->need_update = 1;
1348                         iwl_txq_update_write_ptr(trans, txq);
1349                 } else {
1350                         iwl_stop_queue(trans, txq, "Queue is full");
1351                 }
1352         }
1353         return 0;
1354 }
1355
1356 static void iwl_trans_pcie_kick_nic(struct iwl_trans *trans)
1357 {
1358         /* Remove all resets to allow NIC to operate */
1359         iwl_write32(trans, CSR_RESET, 0);
1360 }
1361
1362 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1363 {
1364         struct iwl_trans_pcie *trans_pcie =
1365                 IWL_TRANS_GET_PCIE_TRANS(trans);
1366         int err;
1367
1368         trans_pcie->inta_mask = CSR_INI_SET_MASK;
1369
1370         if (!trans_pcie->irq_requested) {
1371                 tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1372                         iwl_irq_tasklet, (unsigned long)trans);
1373
1374                 iwl_alloc_isr_ict(trans);
1375
1376                 err = request_irq(trans->irq, iwl_isr_ict, IRQF_SHARED,
1377                         DRV_NAME, trans);
1378                 if (err) {
1379                         IWL_ERR(trans, "Error allocating IRQ %d\n",
1380                                 trans->irq);
1381                         goto error;
1382                 }
1383
1384                 INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1385                 trans_pcie->irq_requested = true;
1386         }
1387
1388         err = iwl_prepare_card_hw(trans);
1389         if (err) {
1390                 IWL_ERR(trans, "Error while preparing HW: %d", err);
1391                 goto error;
1392         }
1393
1394         iwl_apm_init(trans);
1395
1396         /* If platform's RF_KILL switch is NOT set to KILL */
1397         if (iwl_read32(trans,
1398                         CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
1399                 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1400         else
1401                 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1402
1403         iwl_set_hw_rfkill_state(priv(trans),
1404                                 test_bit(STATUS_RF_KILL_HW,
1405                                          &trans->shrd->status));
1406
1407         return err;
1408
1409 error:
1410         iwl_free_isr_ict(trans);
1411         tasklet_kill(&trans_pcie->irq_tasklet);
1412         return err;
1413 }
1414
1415 static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans)
1416 {
1417         iwl_apm_stop(trans);
1418
1419         /* Even if we stop the HW, we still want the RF kill interrupt */
1420         IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n");
1421         iwl_write32(trans, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
1422 }
1423
1424 static int iwl_trans_pcie_reclaim(struct iwl_trans *trans, int sta_id, int tid,
1425                       int txq_id, int ssn, u32 status,
1426                       struct sk_buff_head *skbs)
1427 {
1428         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1429         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1430         /* n_bd is usually 256 => n_bd - 1 = 0xff */
1431         int tfd_num = ssn & (txq->q.n_bd - 1);
1432         int freed = 0;
1433
1434         txq->time_stamp = jiffies;
1435
1436         if (unlikely(txq_id >= IWLAGN_FIRST_AMPDU_QUEUE &&
1437                      txq_id != trans_pcie->agg_txq[sta_id][tid])) {
1438                 /*
1439                  * FIXME: this is a uCode bug which need to be addressed,
1440                  * log the information and return for now.
1441                  * Since it is can possibly happen very often and in order
1442                  * not to fill the syslog, don't use IWL_ERR or IWL_WARN
1443                  */
1444                 IWL_DEBUG_TX_QUEUES(trans, "Bad queue mapping txq_id %d, "
1445                         "agg_txq[sta_id[tid] %d", txq_id,
1446                         trans_pcie->agg_txq[sta_id][tid]);
1447                 return 1;
1448         }
1449
1450         if (txq->q.read_ptr != tfd_num) {
1451                 IWL_DEBUG_TX_REPLY(trans, "[Q %d | AC %d] %d -> %d (%d)\n",
1452                                 txq_id, iwl_get_queue_ac(txq), txq->q.read_ptr,
1453                                 tfd_num, ssn);
1454                 freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
1455                 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
1456                    (!txq->sched_retry ||
1457                    status != TX_STATUS_FAIL_PASSIVE_NO_RX))
1458                         iwl_wake_queue(trans, txq, "Packets reclaimed");
1459         }
1460         return 0;
1461 }
1462
1463 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1464 {
1465         iowrite8(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1466 }
1467
1468 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1469 {
1470         iowrite32(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1471 }
1472
1473 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1474 {
1475         u32 val = ioread32(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1476         return val;
1477 }
1478
1479 static void iwl_trans_pcie_free(struct iwl_trans *trans)
1480 {
1481         struct iwl_trans_pcie *trans_pcie =
1482                 IWL_TRANS_GET_PCIE_TRANS(trans);
1483
1484         iwl_calib_free_results(trans);
1485         iwl_trans_pcie_tx_free(trans);
1486 #ifndef CONFIG_IWLWIFI_IDI
1487         iwl_trans_pcie_rx_free(trans);
1488 #endif
1489         if (trans_pcie->irq_requested == true) {
1490                 free_irq(trans->irq, trans);
1491                 iwl_free_isr_ict(trans);
1492         }
1493
1494         pci_disable_msi(trans_pcie->pci_dev);
1495         pci_iounmap(trans_pcie->pci_dev, trans_pcie->hw_base);
1496         pci_release_regions(trans_pcie->pci_dev);
1497         pci_disable_device(trans_pcie->pci_dev);
1498
1499         trans->shrd->trans = NULL;
1500         kfree(trans);
1501 }
1502
1503 #ifdef CONFIG_PM_SLEEP
1504 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1505 {
1506         /*
1507          * This function is called when system goes into suspend state
1508          * mac80211 will call iwlagn_mac_stop() from the mac80211 suspend
1509          * function first but since iwlagn_mac_stop() has no knowledge of
1510          * who the caller is,
1511          * it will not call apm_ops.stop() to stop the DMA operation.
1512          * Calling apm_ops.stop here to make sure we stop the DMA.
1513          *
1514          * But of course ... if we have configured WoWLAN then we did other
1515          * things already :-)
1516          */
1517         if (!trans->shrd->wowlan) {
1518                 iwl_apm_stop(trans);
1519         } else {
1520                 iwl_disable_interrupts(trans);
1521                 iwl_clear_bit(trans, CSR_GP_CNTRL,
1522                               CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1523         }
1524
1525         return 0;
1526 }
1527
1528 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1529 {
1530         bool hw_rfkill = false;
1531
1532         iwl_enable_interrupts(trans);
1533
1534         if (!(iwl_read32(trans, CSR_GP_CNTRL) &
1535                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1536                 hw_rfkill = true;
1537
1538         if (hw_rfkill)
1539                 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1540         else
1541                 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1542
1543         iwl_set_hw_rfkill_state(priv(trans), hw_rfkill);
1544
1545         return 0;
1546 }
1547 #endif /* CONFIG_PM_SLEEP */
1548
1549 static void iwl_trans_pcie_wake_any_queue(struct iwl_trans *trans,
1550                                           enum iwl_rxon_context_id ctx,
1551                                           const char *msg)
1552 {
1553         u8 ac, txq_id;
1554         struct iwl_trans_pcie *trans_pcie =
1555                 IWL_TRANS_GET_PCIE_TRANS(trans);
1556
1557         for (ac = 0; ac < AC_NUM; ac++) {
1558                 txq_id = trans_pcie->ac_to_queue[ctx][ac];
1559                 IWL_DEBUG_TX_QUEUES(trans, "Queue Status: Q[%d] %s\n",
1560                         ac,
1561                         (atomic_read(&trans_pcie->queue_stop_count[ac]) > 0)
1562                               ? "stopped" : "awake");
1563                 iwl_wake_queue(trans, &trans_pcie->txq[txq_id], msg);
1564         }
1565 }
1566
1567 static void iwl_trans_pcie_stop_queue(struct iwl_trans *trans, int txq_id,
1568                                       const char *msg)
1569 {
1570         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1571
1572         iwl_stop_queue(trans, &trans_pcie->txq[txq_id], msg);
1573 }
1574
1575 #define IWL_FLUSH_WAIT_MS       2000
1576
1577 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
1578 {
1579         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1580         struct iwl_tx_queue *txq;
1581         struct iwl_queue *q;
1582         int cnt;
1583         unsigned long now = jiffies;
1584         int ret = 0;
1585
1586         /* waiting for all the tx frames complete might take a while */
1587         for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1588                 if (cnt == trans->shrd->cmd_queue)
1589                         continue;
1590                 txq = &trans_pcie->txq[cnt];
1591                 q = &txq->q;
1592                 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1593                        now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1594                         msleep(1);
1595
1596                 if (q->read_ptr != q->write_ptr) {
1597                         IWL_ERR(trans, "fail to flush all tx fifo queues\n");
1598                         ret = -ETIMEDOUT;
1599                         break;
1600                 }
1601         }
1602         return ret;
1603 }
1604
1605 /*
1606  * On every watchdog tick we check (latest) time stamp. If it does not
1607  * change during timeout period and queue is not empty we reset firmware.
1608  */
1609 static int iwl_trans_pcie_check_stuck_queue(struct iwl_trans *trans, int cnt)
1610 {
1611         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1612         struct iwl_tx_queue *txq = &trans_pcie->txq[cnt];
1613         struct iwl_queue *q = &txq->q;
1614         unsigned long timeout;
1615
1616         if (q->read_ptr == q->write_ptr) {
1617                 txq->time_stamp = jiffies;
1618                 return 0;
1619         }
1620
1621         timeout = txq->time_stamp +
1622                   msecs_to_jiffies(hw_params(trans).wd_timeout);
1623
1624         if (time_after(jiffies, timeout)) {
1625                 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", q->id,
1626                         hw_params(trans).wd_timeout);
1627                 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1628                         q->read_ptr, q->write_ptr);
1629                 IWL_ERR(trans, "Current HW read_ptr %d write_ptr %d\n",
1630                         iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt))
1631                                 & (TFD_QUEUE_SIZE_MAX - 1),
1632                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1633                 return 1;
1634         }
1635
1636         return 0;
1637 }
1638
1639 static const char *get_fh_string(int cmd)
1640 {
1641         switch (cmd) {
1642         IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1643         IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1644         IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1645         IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1646         IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1647         IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1648         IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1649         IWL_CMD(FH_TSSR_TX_STATUS_REG);
1650         IWL_CMD(FH_TSSR_TX_ERROR_REG);
1651         default:
1652                 return "UNKNOWN";
1653         }
1654 }
1655
1656 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1657 {
1658         int i;
1659 #ifdef CONFIG_IWLWIFI_DEBUG
1660         int pos = 0;
1661         size_t bufsz = 0;
1662 #endif
1663         static const u32 fh_tbl[] = {
1664                 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1665                 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1666                 FH_RSCSR_CHNL0_WPTR,
1667                 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1668                 FH_MEM_RSSR_SHARED_CTRL_REG,
1669                 FH_MEM_RSSR_RX_STATUS_REG,
1670                 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1671                 FH_TSSR_TX_STATUS_REG,
1672                 FH_TSSR_TX_ERROR_REG
1673         };
1674 #ifdef CONFIG_IWLWIFI_DEBUG
1675         if (display) {
1676                 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1677                 *buf = kmalloc(bufsz, GFP_KERNEL);
1678                 if (!*buf)
1679                         return -ENOMEM;
1680                 pos += scnprintf(*buf + pos, bufsz - pos,
1681                                 "FH register values:\n");
1682                 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1683                         pos += scnprintf(*buf + pos, bufsz - pos,
1684                                 "  %34s: 0X%08x\n",
1685                                 get_fh_string(fh_tbl[i]),
1686                                 iwl_read_direct32(trans, fh_tbl[i]));
1687                 }
1688                 return pos;
1689         }
1690 #endif
1691         IWL_ERR(trans, "FH register values:\n");
1692         for (i = 0; i <  ARRAY_SIZE(fh_tbl); i++) {
1693                 IWL_ERR(trans, "  %34s: 0X%08x\n",
1694                         get_fh_string(fh_tbl[i]),
1695                         iwl_read_direct32(trans, fh_tbl[i]));
1696         }
1697         return 0;
1698 }
1699
1700 static const char *get_csr_string(int cmd)
1701 {
1702         switch (cmd) {
1703         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1704         IWL_CMD(CSR_INT_COALESCING);
1705         IWL_CMD(CSR_INT);
1706         IWL_CMD(CSR_INT_MASK);
1707         IWL_CMD(CSR_FH_INT_STATUS);
1708         IWL_CMD(CSR_GPIO_IN);
1709         IWL_CMD(CSR_RESET);
1710         IWL_CMD(CSR_GP_CNTRL);
1711         IWL_CMD(CSR_HW_REV);
1712         IWL_CMD(CSR_EEPROM_REG);
1713         IWL_CMD(CSR_EEPROM_GP);
1714         IWL_CMD(CSR_OTP_GP_REG);
1715         IWL_CMD(CSR_GIO_REG);
1716         IWL_CMD(CSR_GP_UCODE_REG);
1717         IWL_CMD(CSR_GP_DRIVER_REG);
1718         IWL_CMD(CSR_UCODE_DRV_GP1);
1719         IWL_CMD(CSR_UCODE_DRV_GP2);
1720         IWL_CMD(CSR_LED_REG);
1721         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1722         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1723         IWL_CMD(CSR_ANA_PLL_CFG);
1724         IWL_CMD(CSR_HW_REV_WA_REG);
1725         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1726         default:
1727                 return "UNKNOWN";
1728         }
1729 }
1730
1731 void iwl_dump_csr(struct iwl_trans *trans)
1732 {
1733         int i;
1734         static const u32 csr_tbl[] = {
1735                 CSR_HW_IF_CONFIG_REG,
1736                 CSR_INT_COALESCING,
1737                 CSR_INT,
1738                 CSR_INT_MASK,
1739                 CSR_FH_INT_STATUS,
1740                 CSR_GPIO_IN,
1741                 CSR_RESET,
1742                 CSR_GP_CNTRL,
1743                 CSR_HW_REV,
1744                 CSR_EEPROM_REG,
1745                 CSR_EEPROM_GP,
1746                 CSR_OTP_GP_REG,
1747                 CSR_GIO_REG,
1748                 CSR_GP_UCODE_REG,
1749                 CSR_GP_DRIVER_REG,
1750                 CSR_UCODE_DRV_GP1,
1751                 CSR_UCODE_DRV_GP2,
1752                 CSR_LED_REG,
1753                 CSR_DRAM_INT_TBL_REG,
1754                 CSR_GIO_CHICKEN_BITS,
1755                 CSR_ANA_PLL_CFG,
1756                 CSR_HW_REV_WA_REG,
1757                 CSR_DBG_HPET_MEM_REG
1758         };
1759         IWL_ERR(trans, "CSR values:\n");
1760         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1761                 "CSR_INT_PERIODIC_REG)\n");
1762         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1763                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1764                         get_csr_string(csr_tbl[i]),
1765                         iwl_read32(trans, csr_tbl[i]));
1766         }
1767 }
1768
1769 #ifdef CONFIG_IWLWIFI_DEBUGFS
1770 /* create and remove of files */
1771 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1772         if (!debugfs_create_file(#name, mode, parent, trans,            \
1773                                  &iwl_dbgfs_##name##_ops))              \
1774                 return -ENOMEM;                                         \
1775 } while (0)
1776
1777 /* file operation */
1778 #define DEBUGFS_READ_FUNC(name)                                         \
1779 static ssize_t iwl_dbgfs_##name##_read(struct file *file,               \
1780                                         char __user *user_buf,          \
1781                                         size_t count, loff_t *ppos);
1782
1783 #define DEBUGFS_WRITE_FUNC(name)                                        \
1784 static ssize_t iwl_dbgfs_##name##_write(struct file *file,              \
1785                                         const char __user *user_buf,    \
1786                                         size_t count, loff_t *ppos);
1787
1788
1789 static int iwl_dbgfs_open_file_generic(struct inode *inode, struct file *file)
1790 {
1791         file->private_data = inode->i_private;
1792         return 0;
1793 }
1794
1795 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1796         DEBUGFS_READ_FUNC(name);                                        \
1797 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1798         .read = iwl_dbgfs_##name##_read,                                \
1799         .open = iwl_dbgfs_open_file_generic,                            \
1800         .llseek = generic_file_llseek,                                  \
1801 };
1802
1803 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1804         DEBUGFS_WRITE_FUNC(name);                                       \
1805 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1806         .write = iwl_dbgfs_##name##_write,                              \
1807         .open = iwl_dbgfs_open_file_generic,                            \
1808         .llseek = generic_file_llseek,                                  \
1809 };
1810
1811 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1812         DEBUGFS_READ_FUNC(name);                                        \
1813         DEBUGFS_WRITE_FUNC(name);                                       \
1814 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1815         .write = iwl_dbgfs_##name##_write,                              \
1816         .read = iwl_dbgfs_##name##_read,                                \
1817         .open = iwl_dbgfs_open_file_generic,                            \
1818         .llseek = generic_file_llseek,                                  \
1819 };
1820
1821 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1822                                                 char __user *user_buf,
1823                                                 size_t count, loff_t *ppos)
1824 {
1825         struct iwl_trans *trans = file->private_data;
1826         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1827         struct iwl_tx_queue *txq;
1828         struct iwl_queue *q;
1829         char *buf;
1830         int pos = 0;
1831         int cnt;
1832         int ret;
1833         const size_t bufsz = sizeof(char) * 64 * hw_params(trans).max_txq_num;
1834
1835         if (!trans_pcie->txq) {
1836                 IWL_ERR(trans, "txq not ready\n");
1837                 return -EAGAIN;
1838         }
1839         buf = kzalloc(bufsz, GFP_KERNEL);
1840         if (!buf)
1841                 return -ENOMEM;
1842
1843         for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1844                 txq = &trans_pcie->txq[cnt];
1845                 q = &txq->q;
1846                 pos += scnprintf(buf + pos, bufsz - pos,
1847                                 "hwq %.2d: read=%u write=%u stop=%d"
1848                                 " swq_id=%#.2x (ac %d/hwq %d)\n",
1849                                 cnt, q->read_ptr, q->write_ptr,
1850                                 !!test_bit(cnt, trans_pcie->queue_stopped),
1851                                 txq->swq_id, txq->swq_id & 3,
1852                                 (txq->swq_id >> 2) & 0x1f);
1853                 if (cnt >= 4)
1854                         continue;
1855                 /* for the ACs, display the stop count too */
1856                 pos += scnprintf(buf + pos, bufsz - pos,
1857                         "        stop-count: %d\n",
1858                         atomic_read(&trans_pcie->queue_stop_count[cnt]));
1859         }
1860         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1861         kfree(buf);
1862         return ret;
1863 }
1864
1865 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1866                                                 char __user *user_buf,
1867                                                 size_t count, loff_t *ppos) {
1868         struct iwl_trans *trans = file->private_data;
1869         struct iwl_trans_pcie *trans_pcie =
1870                 IWL_TRANS_GET_PCIE_TRANS(trans);
1871         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
1872         char buf[256];
1873         int pos = 0;
1874         const size_t bufsz = sizeof(buf);
1875
1876         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1877                                                 rxq->read);
1878         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1879                                                 rxq->write);
1880         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1881                                                 rxq->free_count);
1882         if (rxq->rb_stts) {
1883                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1884                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
1885         } else {
1886                 pos += scnprintf(buf + pos, bufsz - pos,
1887                                         "closed_rb_num: Not Allocated\n");
1888         }
1889         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1890 }
1891
1892 static ssize_t iwl_dbgfs_log_event_read(struct file *file,
1893                                          char __user *user_buf,
1894                                          size_t count, loff_t *ppos)
1895 {
1896         struct iwl_trans *trans = file->private_data;
1897         char *buf;
1898         int pos = 0;
1899         ssize_t ret = -ENOMEM;
1900
1901         ret = pos = iwl_dump_nic_event_log(trans, true, &buf, true);
1902         if (buf) {
1903                 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1904                 kfree(buf);
1905         }
1906         return ret;
1907 }
1908
1909 static ssize_t iwl_dbgfs_log_event_write(struct file *file,
1910                                         const char __user *user_buf,
1911                                         size_t count, loff_t *ppos)
1912 {
1913         struct iwl_trans *trans = file->private_data;
1914         u32 event_log_flag;
1915         char buf[8];
1916         int buf_size;
1917
1918         memset(buf, 0, sizeof(buf));
1919         buf_size = min(count, sizeof(buf) -  1);
1920         if (copy_from_user(buf, user_buf, buf_size))
1921                 return -EFAULT;
1922         if (sscanf(buf, "%d", &event_log_flag) != 1)
1923                 return -EFAULT;
1924         if (event_log_flag == 1)
1925                 iwl_dump_nic_event_log(trans, true, NULL, false);
1926
1927         return count;
1928 }
1929
1930 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1931                                         char __user *user_buf,
1932                                         size_t count, loff_t *ppos) {
1933
1934         struct iwl_trans *trans = file->private_data;
1935         struct iwl_trans_pcie *trans_pcie =
1936                 IWL_TRANS_GET_PCIE_TRANS(trans);
1937         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1938
1939         int pos = 0;
1940         char *buf;
1941         int bufsz = 24 * 64; /* 24 items * 64 char per item */
1942         ssize_t ret;
1943
1944         buf = kzalloc(bufsz, GFP_KERNEL);
1945         if (!buf) {
1946                 IWL_ERR(trans, "Can not allocate Buffer\n");
1947                 return -ENOMEM;
1948         }
1949
1950         pos += scnprintf(buf + pos, bufsz - pos,
1951                         "Interrupt Statistics Report:\n");
1952
1953         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1954                 isr_stats->hw);
1955         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1956                 isr_stats->sw);
1957         if (isr_stats->sw || isr_stats->hw) {
1958                 pos += scnprintf(buf + pos, bufsz - pos,
1959                         "\tLast Restarting Code:  0x%X\n",
1960                         isr_stats->err_code);
1961         }
1962 #ifdef CONFIG_IWLWIFI_DEBUG
1963         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1964                 isr_stats->sch);
1965         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1966                 isr_stats->alive);
1967 #endif
1968         pos += scnprintf(buf + pos, bufsz - pos,
1969                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1970
1971         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1972                 isr_stats->ctkill);
1973
1974         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1975                 isr_stats->wakeup);
1976
1977         pos += scnprintf(buf + pos, bufsz - pos,
1978                 "Rx command responses:\t\t %u\n", isr_stats->rx);
1979
1980         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1981                 isr_stats->tx);
1982
1983         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1984                 isr_stats->unhandled);
1985
1986         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1987         kfree(buf);
1988         return ret;
1989 }
1990
1991 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1992                                          const char __user *user_buf,
1993                                          size_t count, loff_t *ppos)
1994 {
1995         struct iwl_trans *trans = file->private_data;
1996         struct iwl_trans_pcie *trans_pcie =
1997                 IWL_TRANS_GET_PCIE_TRANS(trans);
1998         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1999
2000         char buf[8];
2001         int buf_size;
2002         u32 reset_flag;
2003
2004         memset(buf, 0, sizeof(buf));
2005         buf_size = min(count, sizeof(buf) -  1);
2006         if (copy_from_user(buf, user_buf, buf_size))
2007                 return -EFAULT;
2008         if (sscanf(buf, "%x", &reset_flag) != 1)
2009                 return -EFAULT;
2010         if (reset_flag == 0)
2011                 memset(isr_stats, 0, sizeof(*isr_stats));
2012
2013         return count;
2014 }
2015
2016 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2017                                          const char __user *user_buf,
2018                                          size_t count, loff_t *ppos)
2019 {
2020         struct iwl_trans *trans = file->private_data;
2021         char buf[8];
2022         int buf_size;
2023         int csr;
2024
2025         memset(buf, 0, sizeof(buf));
2026         buf_size = min(count, sizeof(buf) -  1);
2027         if (copy_from_user(buf, user_buf, buf_size))
2028                 return -EFAULT;
2029         if (sscanf(buf, "%d", &csr) != 1)
2030                 return -EFAULT;
2031
2032         iwl_dump_csr(trans);
2033
2034         return count;
2035 }
2036
2037 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2038                                          char __user *user_buf,
2039                                          size_t count, loff_t *ppos)
2040 {
2041         struct iwl_trans *trans = file->private_data;
2042         char *buf;
2043         int pos = 0;
2044         ssize_t ret = -EFAULT;
2045
2046         ret = pos = iwl_dump_fh(trans, &buf, true);
2047         if (buf) {
2048                 ret = simple_read_from_buffer(user_buf,
2049                                               count, ppos, buf, pos);
2050                 kfree(buf);
2051         }
2052
2053         return ret;
2054 }
2055
2056 DEBUGFS_READ_WRITE_FILE_OPS(log_event);
2057 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2058 DEBUGFS_READ_FILE_OPS(fh_reg);
2059 DEBUGFS_READ_FILE_OPS(rx_queue);
2060 DEBUGFS_READ_FILE_OPS(tx_queue);
2061 DEBUGFS_WRITE_FILE_OPS(csr);
2062
2063 /*
2064  * Create the debugfs files and directories
2065  *
2066  */
2067 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2068                                         struct dentry *dir)
2069 {
2070         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2071         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2072         DEBUGFS_ADD_FILE(log_event, dir, S_IWUSR | S_IRUSR);
2073         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2074         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2075         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2076         return 0;
2077 }
2078 #else
2079 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2080                                         struct dentry *dir)
2081 { return 0; }
2082
2083 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2084
2085 const struct iwl_trans_ops trans_ops_pcie = {
2086         .start_hw = iwl_trans_pcie_start_hw,
2087         .stop_hw = iwl_trans_pcie_stop_hw,
2088         .fw_alive = iwl_trans_pcie_fw_alive,
2089         .start_device = iwl_trans_pcie_start_device,
2090         .stop_device = iwl_trans_pcie_stop_device,
2091
2092         .wake_any_queue = iwl_trans_pcie_wake_any_queue,
2093
2094         .send_cmd = iwl_trans_pcie_send_cmd,
2095
2096         .tx = iwl_trans_pcie_tx,
2097         .reclaim = iwl_trans_pcie_reclaim,
2098
2099         .tx_agg_disable = iwl_trans_pcie_tx_agg_disable,
2100         .tx_agg_alloc = iwl_trans_pcie_tx_agg_alloc,
2101         .tx_agg_setup = iwl_trans_pcie_tx_agg_setup,
2102
2103         .kick_nic = iwl_trans_pcie_kick_nic,
2104
2105         .free = iwl_trans_pcie_free,
2106         .stop_queue = iwl_trans_pcie_stop_queue,
2107
2108         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2109
2110         .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty,
2111         .check_stuck_queue = iwl_trans_pcie_check_stuck_queue,
2112
2113 #ifdef CONFIG_PM_SLEEP
2114         .suspend = iwl_trans_pcie_suspend,
2115         .resume = iwl_trans_pcie_resume,
2116 #endif
2117         .write8 = iwl_trans_pcie_write8,
2118         .write32 = iwl_trans_pcie_write32,
2119         .read32 = iwl_trans_pcie_read32,
2120 };
2121
2122 /* PCI registers */
2123 #define PCI_CFG_RETRY_TIMEOUT   0x041
2124
2125 struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd,
2126                                        struct pci_dev *pdev,
2127                                        const struct pci_device_id *ent)
2128 {
2129         struct iwl_trans_pcie *trans_pcie;
2130         struct iwl_trans *trans;
2131         u16 pci_cmd;
2132         int err;
2133
2134         trans = kzalloc(sizeof(struct iwl_trans) +
2135                              sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2136
2137         if (WARN_ON(!trans))
2138                 return NULL;
2139
2140         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2141
2142         trans->ops = &trans_ops_pcie;
2143         trans->shrd = shrd;
2144         trans_pcie->trans = trans;
2145         spin_lock_init(&trans->hcmd_lock);
2146
2147         /* W/A - seems to solve weird behavior. We need to remove this if we
2148          * don't want to stay in L1 all the time. This wastes a lot of power */
2149         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
2150                                 PCIE_LINK_STATE_CLKPM);
2151
2152         if (pci_enable_device(pdev)) {
2153                 err = -ENODEV;
2154                 goto out_no_pci;
2155         }
2156
2157         pci_set_master(pdev);
2158
2159         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2160         if (!err)
2161                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2162         if (err) {
2163                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2164                 if (!err)
2165                         err = pci_set_consistent_dma_mask(pdev,
2166                                                         DMA_BIT_MASK(32));
2167                 /* both attempts failed: */
2168                 if (err) {
2169                         dev_printk(KERN_ERR, &pdev->dev,
2170                                    "No suitable DMA available.\n");
2171                         goto out_pci_disable_device;
2172                 }
2173         }
2174
2175         err = pci_request_regions(pdev, DRV_NAME);
2176         if (err) {
2177                 dev_printk(KERN_ERR, &pdev->dev, "pci_request_regions failed");
2178                 goto out_pci_disable_device;
2179         }
2180
2181         trans_pcie->hw_base = pci_iomap(pdev, 0, 0);
2182         if (!trans_pcie->hw_base) {
2183                 dev_printk(KERN_ERR, &pdev->dev, "pci_iomap failed");
2184                 err = -ENODEV;
2185                 goto out_pci_release_regions;
2186         }
2187
2188         dev_printk(KERN_INFO, &pdev->dev,
2189                 "pci_resource_len = 0x%08llx\n",
2190                 (unsigned long long) pci_resource_len(pdev, 0));
2191         dev_printk(KERN_INFO, &pdev->dev,
2192                 "pci_resource_base = %p\n", trans_pcie->hw_base);
2193
2194         dev_printk(KERN_INFO, &pdev->dev,
2195                 "HW Revision ID = 0x%X\n", pdev->revision);
2196
2197         /* We disable the RETRY_TIMEOUT register (0x41) to keep
2198          * PCI Tx retries from interfering with C3 CPU state */
2199         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2200
2201         err = pci_enable_msi(pdev);
2202         if (err)
2203                 dev_printk(KERN_ERR, &pdev->dev,
2204                         "pci_enable_msi failed(0X%x)", err);
2205
2206         trans->dev = &pdev->dev;
2207         trans->irq = pdev->irq;
2208         trans_pcie->pci_dev = pdev;
2209
2210         /* TODO: Move this away, not needed if not MSI */
2211         /* enable rfkill interrupt: hw bug w/a */
2212         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2213         if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2214                 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2215                 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2216         }
2217
2218         return trans;
2219
2220 out_pci_release_regions:
2221         pci_release_regions(pdev);
2222 out_pci_disable_device:
2223         pci_disable_device(pdev);
2224 out_no_pci:
2225         kfree(trans);
2226         return NULL;
2227 }
2228