Pileus Git - ~andy/linux/blob - drivers/net/wireless/iwlwifi/iwl-pci.c

   1 /******************************************************************************
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   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
   9  *
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  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
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  28  *  Intel Linux Wireless <ilw@linux.intel.com>
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  41  *    notice, this list of conditions and the following disclaimer.
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  43  *    notice, this list of conditions and the following disclaimer in
  44  *    the documentation and/or other materials provided with the
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  47  *    contributors may be used to endorse or promote products derived
  48  *    from this software without specific prior written permission.
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  50  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  55  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  56  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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  58  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63 #include <linux/pci.h>
  64 #include <linux/pci-aspm.h>
  65
  66 #include "iwl-pci.h"
  67 #include "iwl-agn.h"
  68 #include "iwl-core.h"
  69 #include "iwl-io.h"
  70 #include "iwl-trans.h"
  71
  72 /* PCI registers */
  73 #define PCI_CFG_RETRY_TIMEOUT   0x041
  74 #define PCI_CFG_LINK_CTRL_VAL_L0S_EN    0x01
  75 #define PCI_CFG_LINK_CTRL_VAL_L1_EN     0x02
  76
  77 struct iwl_pci_bus {
  78         /* basic pci-network driver stuff */
  79         struct pci_dev *pci_dev;
  80
  81         /* pci hardware address support */
  82         void __iomem *hw_base;
  83 };
  84
  85 #define IWL_BUS_GET_PCI_BUS(_iwl_bus) \
  86                         ((struct iwl_pci_bus *) ((_iwl_bus)->bus_specific))
  87
  88 #define IWL_BUS_GET_PCI_DEV(_iwl_bus) \
  89                         ((IWL_BUS_GET_PCI_BUS(_iwl_bus))->pci_dev)
  90
  91 static u16 iwl_pciexp_link_ctrl(struct iwl_bus *bus)
  92 {
  93         int pos;
  94         u16 pci_lnk_ctl;
  95         struct pci_dev *pci_dev = IWL_BUS_GET_PCI_DEV(bus);
  96
  97         pos = pci_pcie_cap(pci_dev);
  98         pci_read_config_word(pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
  99         return pci_lnk_ctl;
 100 }
 101
 102 static bool iwl_pci_is_pm_supported(struct iwl_bus *bus)
 103 {
 104         u16 lctl = iwl_pciexp_link_ctrl(bus);
 105
 106         return !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
 107 }
 108
 109 static void iwl_pci_apm_config(struct iwl_bus *bus)
 110 {
 111         /*
 112          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 113          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 114          * If so (likely), disable L0S, so device moves directly L0->L1;
 115          *    costs negligible amount of power savings.
 116          * If not (unlikely), enable L0S, so there is at least some
 117          *    power savings, even without L1.
 118          */
 119         u16 lctl = iwl_pciexp_link_ctrl(bus);
 120
 121         if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
 122                                 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
 123                 /* L1-ASPM enabled; disable(!) L0S */
 124                 iwl_set_bit(bus->priv, CSR_GIO_REG,
 125                                 CSR_GIO_REG_VAL_L0S_ENABLED);
 126                 IWL_DEBUG_POWER(bus->priv, "L1 Enabled; Disabling L0S\n");
 127         } else {
 128                 /* L1-ASPM disabled; enable(!) L0S */
 129                 iwl_clear_bit(bus->priv, CSR_GIO_REG,
 130                                 CSR_GIO_REG_VAL_L0S_ENABLED);
 131                 IWL_DEBUG_POWER(bus->priv, "L1 Disabled; Enabling L0S\n");
 132         }
 133 }
 134
 135 static void iwl_pci_set_drv_data(struct iwl_bus *bus, void *drv_priv)
 136 {
 137         pci_set_drvdata(IWL_BUS_GET_PCI_DEV(bus), drv_priv);
 138 }
 139
 140 static struct device *iwl_pci_get_dev(const struct iwl_bus *bus)
 141 {
 142         return &(IWL_BUS_GET_PCI_DEV(bus)->dev);
 143 }
 144
 145 static unsigned int iwl_pci_get_irq(const struct iwl_bus *bus)
 146 {
 147         return IWL_BUS_GET_PCI_DEV(bus)->irq;
 148 }
 149
 150 static void iwl_pci_get_hw_id(struct iwl_bus *bus, char buf[],
 151                               int buf_len)
 152 {
 153         struct pci_dev *pci_dev = IWL_BUS_GET_PCI_DEV(bus);
 154
 155         snprintf(buf, buf_len, "PCI ID: 0x%04X:0x%04X", pci_dev->device,
 156                  pci_dev->subsystem_device);
 157 }
 158
 159 static void iwl_pci_write8(struct iwl_bus *bus, u32 ofs, u8 val)
 160 {
 161         iowrite8(val, IWL_BUS_GET_PCI_BUS(bus)->hw_base + ofs);
 162 }
 163
 164 static void iwl_pci_write32(struct iwl_bus *bus, u32 ofs, u32 val)
 165 {
 166         iowrite32(val, IWL_BUS_GET_PCI_BUS(bus)->hw_base + ofs);
 167 }
 168
 169 static u32 iwl_pci_read32(struct iwl_bus *bus, u32 ofs)
 170 {
 171         u32 val = ioread32(IWL_BUS_GET_PCI_BUS(bus)->hw_base + ofs);
 172         return val;
 173 }
 174
 175 static struct iwl_bus_ops pci_ops = {
 176         .get_pm_support = iwl_pci_is_pm_supported,
 177         .apm_config = iwl_pci_apm_config,
 178         .set_drv_data = iwl_pci_set_drv_data,
 179         .get_dev = iwl_pci_get_dev,
 180         .get_irq = iwl_pci_get_irq,
 181         .get_hw_id = iwl_pci_get_hw_id,
 182         .write8 = iwl_pci_write8,
 183         .write32 = iwl_pci_write32,
 184         .read32 = iwl_pci_read32,
 185 };
 186
 187 #define IWL_PCI_DEVICE(dev, subdev, cfg) \
 188         .vendor = PCI_VENDOR_ID_INTEL,  .device = (dev), \
 189         .subvendor = PCI_ANY_ID, .subdevice = (subdev), \
 190         .driver_data = (kernel_ulong_t)&(cfg)
 191
 192 /* Hardware specific file defines the PCI IDs table for that hardware module */
 193 static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
 194         {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
 195         {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
 196         {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
 197         {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
 198         {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
 199         {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
 200         {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
 201         {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
 202         {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
 203         {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
 204         {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
 205         {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
 206         {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
 207         {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
 208         {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
 209         {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
 210         {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
 211         {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
 212         {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
 213         {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
 214         {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
 215         {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
 216         {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
 217         {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
 218
 219 /* 5300 Series WiFi */
 220         {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
 221         {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
 222         {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
 223         {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
 224         {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
 225         {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
 226         {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
 227         {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
 228         {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
 229         {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
 230         {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
 231         {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
 232
 233 /* 5350 Series WiFi/WiMax */
 234         {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
 235         {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
 236         {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
 237
 238 /* 5150 Series Wifi/WiMax */
 239         {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
 240         {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
 241         {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
 242         {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
 243         {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
 244         {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
 245
 246         {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
 247         {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
 248         {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
 249         {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
 250
 251 /* 6x00 Series */
 252         {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
 253         {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
 254         {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
 255         {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
 256         {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
 257         {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
 258         {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
 259         {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
 260         {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
 261         {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
 262
 263 /* 6x05 Series */
 264         {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6005_2agn_cfg)},
 265         {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6005_2abg_cfg)},
 266         {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6005_2bg_cfg)},
 267         {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6005_2agn_cfg)},
 268         {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6005_2abg_cfg)},
 269         {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6005_2agn_cfg)},
 270         {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6005_2abg_cfg)},
 271
 272 /* 6x30 Series */
 273         {IWL_PCI_DEVICE(0x008A, 0x5305, iwl1030_bgn_cfg)},
 274         {IWL_PCI_DEVICE(0x008A, 0x5307, iwl1030_bg_cfg)},
 275         {IWL_PCI_DEVICE(0x008A, 0x5325, iwl1030_bgn_cfg)},
 276         {IWL_PCI_DEVICE(0x008A, 0x5327, iwl1030_bg_cfg)},
 277         {IWL_PCI_DEVICE(0x008B, 0x5315, iwl1030_bgn_cfg)},
 278         {IWL_PCI_DEVICE(0x008B, 0x5317, iwl1030_bg_cfg)},
 279         {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6030_2agn_cfg)},
 280         {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6030_2bgn_cfg)},
 281         {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6030_2abg_cfg)},
 282         {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6030_2agn_cfg)},
 283         {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6030_2bgn_cfg)},
 284         {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6030_2abg_cfg)},
 285         {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6030_2bg_cfg)},
 286         {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6030_2agn_cfg)},
 287         {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6030_2bgn_cfg)},
 288         {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6030_2abg_cfg)},
 289
 290 /* 6x50 WiFi/WiMax Series */
 291         {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
 292         {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
 293         {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
 294         {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
 295         {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
 296         {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
 297
 298 /* 6150 WiFi/WiMax Series */
 299         {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6150_bgn_cfg)},
 300         {IWL_PCI_DEVICE(0x0885, 0x1307, iwl6150_bg_cfg)},
 301         {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6150_bgn_cfg)},
 302         {IWL_PCI_DEVICE(0x0885, 0x1327, iwl6150_bg_cfg)},
 303         {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6150_bgn_cfg)},
 304         {IWL_PCI_DEVICE(0x0886, 0x1317, iwl6150_bg_cfg)},
 305
 306 /* 1000 Series WiFi */
 307         {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
 308         {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
 309         {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
 310         {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
 311         {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
 312         {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
 313         {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
 314         {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
 315         {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
 316         {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
 317         {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
 318         {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
 319
 320 /* 100 Series WiFi */
 321         {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
 322         {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
 323         {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
 324         {IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg)},
 325         {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
 326         {IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg)},
 327
 328 /* 130 Series WiFi */
 329         {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)},
 330         {IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)},
 331         {IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)},
 332         {IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)},
 333         {IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)},
 334         {IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)},
 335
 336 /* 2x00 Series */
 337         {IWL_PCI_DEVICE(0x0890, 0x4022, iwl2000_2bgn_cfg)},
 338         {IWL_PCI_DEVICE(0x0891, 0x4222, iwl2000_2bgn_cfg)},
 339         {IWL_PCI_DEVICE(0x0890, 0x4422, iwl2000_2bgn_cfg)},
 340         {IWL_PCI_DEVICE(0x0890, 0x4026, iwl2000_2bg_cfg)},
 341         {IWL_PCI_DEVICE(0x0891, 0x4226, iwl2000_2bg_cfg)},
 342         {IWL_PCI_DEVICE(0x0890, 0x4426, iwl2000_2bg_cfg)},
 343
 344 /* 2x30 Series */
 345         {IWL_PCI_DEVICE(0x0887, 0x4062, iwl2030_2bgn_cfg)},
 346         {IWL_PCI_DEVICE(0x0888, 0x4262, iwl2030_2bgn_cfg)},
 347         {IWL_PCI_DEVICE(0x0887, 0x4462, iwl2030_2bgn_cfg)},
 348         {IWL_PCI_DEVICE(0x0887, 0x4066, iwl2030_2bg_cfg)},
 349         {IWL_PCI_DEVICE(0x0888, 0x4266, iwl2030_2bg_cfg)},
 350         {IWL_PCI_DEVICE(0x0887, 0x4466, iwl2030_2bg_cfg)},
 351
 352 /* 6x35 Series */
 353         {IWL_PCI_DEVICE(0x088E, 0x4060, iwl6035_2agn_cfg)},
 354         {IWL_PCI_DEVICE(0x088F, 0x4260, iwl6035_2agn_cfg)},
 355         {IWL_PCI_DEVICE(0x088E, 0x4460, iwl6035_2agn_cfg)},
 356         {IWL_PCI_DEVICE(0x088E, 0x4064, iwl6035_2abg_cfg)},
 357         {IWL_PCI_DEVICE(0x088F, 0x4264, iwl6035_2abg_cfg)},
 358         {IWL_PCI_DEVICE(0x088E, 0x4464, iwl6035_2abg_cfg)},
 359         {IWL_PCI_DEVICE(0x088E, 0x4066, iwl6035_2bg_cfg)},
 360         {IWL_PCI_DEVICE(0x088F, 0x4266, iwl6035_2bg_cfg)},
 361         {IWL_PCI_DEVICE(0x088E, 0x4466, iwl6035_2bg_cfg)},
 362
 363 /* 105 Series */
 364         {IWL_PCI_DEVICE(0x0894, 0x0022, iwl105_bgn_cfg)},
 365         {IWL_PCI_DEVICE(0x0895, 0x0222, iwl105_bgn_cfg)},
 366         {IWL_PCI_DEVICE(0x0894, 0x0422, iwl105_bgn_cfg)},
 367         {IWL_PCI_DEVICE(0x0894, 0x0026, iwl105_bg_cfg)},
 368         {IWL_PCI_DEVICE(0x0895, 0x0226, iwl105_bg_cfg)},
 369         {IWL_PCI_DEVICE(0x0894, 0x0426, iwl105_bg_cfg)},
 370
 371 /* 135 Series */
 372         {IWL_PCI_DEVICE(0x0892, 0x0062, iwl135_bgn_cfg)},
 373         {IWL_PCI_DEVICE(0x0893, 0x0262, iwl135_bgn_cfg)},
 374         {IWL_PCI_DEVICE(0x0892, 0x0462, iwl135_bgn_cfg)},
 375         {IWL_PCI_DEVICE(0x0892, 0x0066, iwl135_bg_cfg)},
 376         {IWL_PCI_DEVICE(0x0893, 0x0266, iwl135_bg_cfg)},
 377         {IWL_PCI_DEVICE(0x0892, 0x0466, iwl135_bg_cfg)},
 378
 379         {0}
 380 };
 381 MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
 382
 383 static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 384 {
 385         struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
 386         struct iwl_pci_bus *bus;
 387         u16 pci_cmd;
 388         int err;
 389
 390         bus = kzalloc(sizeof(*bus), GFP_KERNEL);
 391         if (!bus) {
 392                 pr_err("Couldn't allocate iwl_pci_bus");
 393                 err = -ENOMEM;
 394                 goto out_no_pci;
 395         }
 396
 397         bus->pci_dev = pdev;
 398
 399         /* W/A - seems to solve weird behavior. We need to remove this if we
 400          * don't want to stay in L1 all the time. This wastes a lot of power */
 401         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
 402                                 PCIE_LINK_STATE_CLKPM);
 403
 404         if (pci_enable_device(pdev)) {
 405                 err = -ENODEV;
 406                 goto out_no_pci;
 407         }
 408
 409         pci_set_master(pdev);
 410
 411         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
 412         if (!err)
 413                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
 414         if (err) {
 415                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
 416                 if (!err)
 417                         err = pci_set_consistent_dma_mask(pdev,
 418                                                         DMA_BIT_MASK(32));
 419                 /* both attempts failed: */
 420                 if (err) {
 421                         pr_err("No suitable DMA available.\n");
 422                         goto out_pci_disable_device;
 423                 }
 424         }
 425
 426         err = pci_request_regions(pdev, DRV_NAME);
 427         if (err) {
 428                 pr_err("pci_request_regions failed");
 429                 goto out_pci_disable_device;
 430         }
 431
 432         bus->hw_base = pci_iomap(pdev, 0, 0);
 433         if (!bus->hw_base) {
 434                 pr_err("pci_iomap failed");
 435                 err = -ENODEV;
 436                 goto out_pci_release_regions;
 437         }
 438
 439         pr_info("pci_resource_len = 0x%08llx\n",
 440                 (unsigned long long) pci_resource_len(pdev, 0));
 441         pr_info("pci_resource_base = %p\n", bus->hw_base);
 442
 443         pr_info("HW Revision ID = 0x%X\n", pdev->revision);
 444
 445         /* We disable the RETRY_TIMEOUT register (0x41) to keep
 446          * PCI Tx retries from interfering with C3 CPU state */
 447         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
 448
 449         err = pci_enable_msi(pdev);
 450         if (err) {
 451                 pr_err("pci_enable_msi failed");
 452                 goto out_iounmap;
 453         }
 454
 455         /* TODO: Move this away, not needed if not MSI */
 456         /* enable rfkill interrupt: hw bug w/a */
 457         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
 458         if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
 459                 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
 460                 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
 461         }
 462
 463         err = iwl_probe((void *) bus, &pci_ops, cfg);
 464         if (err)
 465                 goto out_disable_msi;
 466         return 0;
 467
 468 out_disable_msi:
 469         pci_disable_msi(pdev);
 470 out_iounmap:
 471         pci_iounmap(pdev, bus->hw_base);
 472 out_pci_release_regions:
 473         pci_set_drvdata(pdev, NULL);
 474         pci_release_regions(pdev);
 475 out_pci_disable_device:
 476         pci_disable_device(pdev);
 477 out_no_pci:
 478         kfree(bus);
 479         return err;
 480 }
 481
 482 static void iwl_pci_down(void *bus)
 483 {
 484         struct iwl_pci_bus *pci_bus = (struct iwl_pci_bus *) bus;
 485
 486         pci_disable_msi(pci_bus->pci_dev);
 487         pci_iounmap(pci_bus->pci_dev, pci_bus->hw_base);
 488         pci_release_regions(pci_bus->pci_dev);
 489         pci_disable_device(pci_bus->pci_dev);
 490         pci_set_drvdata(pci_bus->pci_dev, NULL);
 491
 492         kfree(pci_bus);
 493 }
 494
 495 static void __devexit iwl_pci_remove(struct pci_dev *pdev)
 496 {
 497         struct iwl_priv *priv = pci_get_drvdata(pdev);
 498         void *bus_specific = priv->bus.bus_specific;
 499
 500         iwl_remove(priv);
 501
 502         iwl_pci_down(bus_specific);
 503 }
 504
 505 #ifdef CONFIG_PM
 506
 507 static int iwl_pci_suspend(struct device *device)
 508 {
 509         struct pci_dev *pdev = to_pci_dev(device);
 510         struct iwl_priv *priv = pci_get_drvdata(pdev);
 511
 512         return iwl_suspend(priv);
 513 }
 514
 515 static int iwl_pci_resume(struct device *device)
 516 {
 517         struct pci_dev *pdev = to_pci_dev(device);
 518         struct iwl_priv *priv = pci_get_drvdata(pdev);
 519
 520         /*
 521          * We disable the RETRY_TIMEOUT register (0x41) to keep
 522          * PCI Tx retries from interfering with C3 CPU state.
 523          */
 524         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
 525
 526         return iwl_resume(priv);
 527 }
 528
 529 static SIMPLE_DEV_PM_OPS(iwl_dev_pm_ops, iwl_pci_suspend, iwl_pci_resume);
 530
 531 #define IWL_PM_OPS      (&iwl_dev_pm_ops)
 532
 533 #else
 534
 535 #define IWL_PM_OPS      NULL
 536
 537 #endif
 538
 539 static struct pci_driver iwl_pci_driver = {
 540         .name = DRV_NAME,
 541         .id_table = iwl_hw_card_ids,
 542         .probe = iwl_pci_probe,
 543         .remove = __devexit_p(iwl_pci_remove),
 544         .driver.pm = IWL_PM_OPS,
 545 };
 546
 547 int __must_check iwl_pci_register_driver(void)
 548 {
 549         int ret;
 550         ret = pci_register_driver(&iwl_pci_driver);
 551         if (ret)
 552                 pr_err("Unable to initialize PCI module\n");
 553
 554         return ret;
 555 }
 556
 557 void iwl_pci_unregister_driver(void)
 558 {
 559         pci_unregister_driver(&iwl_pci_driver);
 560 }