Pileus Git - ~andy/linux/blob - drivers/net/wireless/iwlwifi/iwl-agn.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29
  30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  31
  32 #include <linux/kernel.h>
  33 #include <linux/module.h>
  34 #include <linux/init.h>
  35 #include <linux/pci.h>
  36 #include <linux/pci-aspm.h>
  37 #include <linux/slab.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/delay.h>
  40 #include <linux/sched.h>
  41 #include <linux/skbuff.h>
  42 #include <linux/netdevice.h>
  43 #include <linux/wireless.h>
  44 #include <linux/firmware.h>
  45 #include <linux/etherdevice.h>
  46 #include <linux/if_arp.h>
  47
  48 #include <net/mac80211.h>
  49
  50 #include <asm/div64.h>
  51
  52 #define DRV_NAME        "iwlagn"
  53
  54 #include "iwl-eeprom.h"
  55 #include "iwl-dev.h"
  56 #include "iwl-core.h"
  57 #include "iwl-io.h"
  58 #include "iwl-helpers.h"
  59 #include "iwl-sta.h"
  60 #include "iwl-agn-calib.h"
  61 #include "iwl-agn.h"
  62 #include "iwl-agn-led.h"
  63
  64
  65 /******************************************************************************
  66  *
  67  * module boiler plate
  68  *
  69  ******************************************************************************/
  70
  71 /*
  72  * module name, copyright, version, etc.
  73  */
  74 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  75
  76 #ifdef CONFIG_IWLWIFI_DEBUG
  77 #define VD "d"
  78 #else
  79 #define VD
  80 #endif
  81
  82 #define DRV_VERSION     IWLWIFI_VERSION VD
  83
  84
  85 MODULE_DESCRIPTION(DRV_DESCRIPTION);
  86 MODULE_VERSION(DRV_VERSION);
  87 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  88 MODULE_LICENSE("GPL");
  89 MODULE_ALIAS("iwl4965");
  90
  91 static int iwlagn_ant_coupling;
  92 static bool iwlagn_bt_ch_announce = 1;
  93
  94 void iwl_update_chain_flags(struct iwl_priv *priv)
  95 {
  96         struct iwl_rxon_context *ctx;
  97
  98         if (priv->cfg->ops->hcmd->set_rxon_chain) {
  99                 for_each_context(priv, ctx) {
 100                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
 101                         if (ctx->active.rx_chain != ctx->staging.rx_chain)
 102                                 iwlcore_commit_rxon(priv, ctx);
 103                 }
 104         }
 105 }
 106
 107 static void iwl_clear_free_frames(struct iwl_priv *priv)
 108 {
 109         struct list_head *element;
 110
 111         IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
 112                        priv->frames_count);
 113
 114         while (!list_empty(&priv->free_frames)) {
 115                 element = priv->free_frames.next;
 116                 list_del(element);
 117                 kfree(list_entry(element, struct iwl_frame, list));
 118                 priv->frames_count--;
 119         }
 120
 121         if (priv->frames_count) {
 122                 IWL_WARN(priv, "%d frames still in use.  Did we lose one?\n",
 123                             priv->frames_count);
 124                 priv->frames_count = 0;
 125         }
 126 }
 127
 128 static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
 129 {
 130         struct iwl_frame *frame;
 131         struct list_head *element;
 132         if (list_empty(&priv->free_frames)) {
 133                 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
 134                 if (!frame) {
 135                         IWL_ERR(priv, "Could not allocate frame!\n");
 136                         return NULL;
 137                 }
 138
 139                 priv->frames_count++;
 140                 return frame;
 141         }
 142
 143         element = priv->free_frames.next;
 144         list_del(element);
 145         return list_entry(element, struct iwl_frame, list);
 146 }
 147
 148 static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
 149 {
 150         memset(frame, 0, sizeof(*frame));
 151         list_add(&frame->list, &priv->free_frames);
 152 }
 153
 154 static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
 155                                  struct ieee80211_hdr *hdr,
 156                                  int left)
 157 {
 158         lockdep_assert_held(&priv->mutex);
 159
 160         if (!priv->beacon_skb)
 161                 return 0;
 162
 163         if (priv->beacon_skb->len > left)
 164                 return 0;
 165
 166         memcpy(hdr, priv->beacon_skb->data, priv->beacon_skb->len);
 167
 168         return priv->beacon_skb->len;
 169 }
 170
 171 /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
 172 static void iwl_set_beacon_tim(struct iwl_priv *priv,
 173                                struct iwl_tx_beacon_cmd *tx_beacon_cmd,
 174                                u8 *beacon, u32 frame_size)
 175 {
 176         u16 tim_idx;
 177         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
 178
 179         /*
 180          * The index is relative to frame start but we start looking at the
 181          * variable-length part of the beacon.
 182          */
 183         tim_idx = mgmt->u.beacon.variable - beacon;
 184
 185         /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
 186         while ((tim_idx < (frame_size - 2)) &&
 187                         (beacon[tim_idx] != WLAN_EID_TIM))
 188                 tim_idx += beacon[tim_idx+1] + 2;
 189
 190         /* If TIM field was found, set variables */
 191         if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
 192                 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
 193                 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
 194         } else
 195                 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
 196 }
 197
 198 static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
 199                                        struct iwl_frame *frame)
 200 {
 201         struct iwl_tx_beacon_cmd *tx_beacon_cmd;
 202         u32 frame_size;
 203         u32 rate_flags;
 204         u32 rate;
 205         /*
 206          * We have to set up the TX command, the TX Beacon command, and the
 207          * beacon contents.
 208          */
 209
 210         lockdep_assert_held(&priv->mutex);
 211
 212         if (!priv->beacon_ctx) {
 213                 IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
 214                 return 0;
 215         }
 216
 217         /* Initialize memory */
 218         tx_beacon_cmd = &frame->u.beacon;
 219         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
 220
 221         /* Set up TX beacon contents */
 222         frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
 223                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
 224         if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
 225                 return 0;
 226         if (!frame_size)
 227                 return 0;
 228
 229         /* Set up TX command fields */
 230         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
 231         tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
 232         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
 233         tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
 234                 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
 235
 236         /* Set up TX beacon command fields */
 237         iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
 238                            frame_size);
 239
 240         /* Set up packet rate and flags */
 241         rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx);
 242         priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
 243                                               priv->hw_params.valid_tx_ant);
 244         rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
 245         if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
 246                 rate_flags |= RATE_MCS_CCK_MSK;
 247         tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
 248                         rate_flags);
 249
 250         return sizeof(*tx_beacon_cmd) + frame_size;
 251 }
 252
 253 int iwlagn_send_beacon_cmd(struct iwl_priv *priv)
 254 {
 255         struct iwl_frame *frame;
 256         unsigned int frame_size;
 257         int rc;
 258
 259         frame = iwl_get_free_frame(priv);
 260         if (!frame) {
 261                 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
 262                           "command.\n");
 263                 return -ENOMEM;
 264         }
 265
 266         frame_size = iwl_hw_get_beacon_cmd(priv, frame);
 267         if (!frame_size) {
 268                 IWL_ERR(priv, "Error configuring the beacon command\n");
 269                 iwl_free_frame(priv, frame);
 270                 return -EINVAL;
 271         }
 272
 273         rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
 274                               &frame->u.cmd[0]);
 275
 276         iwl_free_frame(priv, frame);
 277
 278         return rc;
 279 }
 280
 281 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
 282 {
 283         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 284
 285         dma_addr_t addr = get_unaligned_le32(&tb->lo);
 286         if (sizeof(dma_addr_t) > sizeof(u32))
 287                 addr |=
 288                 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
 289
 290         return addr;
 291 }
 292
 293 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
 294 {
 295         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 296
 297         return le16_to_cpu(tb->hi_n_len) >> 4;
 298 }
 299
 300 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
 301                                   dma_addr_t addr, u16 len)
 302 {
 303         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 304         u16 hi_n_len = len << 4;
 305
 306         put_unaligned_le32(addr, &tb->lo);
 307         if (sizeof(dma_addr_t) > sizeof(u32))
 308                 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
 309
 310         tb->hi_n_len = cpu_to_le16(hi_n_len);
 311
 312         tfd->num_tbs = idx + 1;
 313 }
 314
 315 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
 316 {
 317         return tfd->num_tbs & 0x1f;
 318 }
 319
 320 /**
 321  * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
 322  * @priv - driver private data
 323  * @txq - tx queue
 324  *
 325  * Does NOT advance any TFD circular buffer read/write indexes
 326  * Does NOT free the TFD itself (which is within circular buffer)
 327  */
 328 void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
 329 {
 330         struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
 331         struct iwl_tfd *tfd;
 332         struct pci_dev *dev = priv->pci_dev;
 333         int index = txq->q.read_ptr;
 334         int i;
 335         int num_tbs;
 336
 337         tfd = &tfd_tmp[index];
 338
 339         /* Sanity check on number of chunks */
 340         num_tbs = iwl_tfd_get_num_tbs(tfd);
 341
 342         if (num_tbs >= IWL_NUM_OF_TBS) {
 343                 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
 344                 /* @todo issue fatal error, it is quite serious situation */
 345                 return;
 346         }
 347
 348         /* Unmap tx_cmd */
 349         if (num_tbs)
 350                 pci_unmap_single(dev,
 351                                 dma_unmap_addr(&txq->meta[index], mapping),
 352                                 dma_unmap_len(&txq->meta[index], len),
 353                                 PCI_DMA_BIDIRECTIONAL);
 354
 355         /* Unmap chunks, if any. */
 356         for (i = 1; i < num_tbs; i++)
 357                 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
 358                                 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
 359
 360         /* free SKB */
 361         if (txq->txb) {
 362                 struct sk_buff *skb;
 363
 364                 skb = txq->txb[txq->q.read_ptr].skb;
 365
 366                 /* can be called from irqs-disabled context */
 367                 if (skb) {
 368                         dev_kfree_skb_any(skb);
 369                         txq->txb[txq->q.read_ptr].skb = NULL;
 370                 }
 371         }
 372 }
 373
 374 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
 375                                  struct iwl_tx_queue *txq,
 376                                  dma_addr_t addr, u16 len,
 377                                  u8 reset, u8 pad)
 378 {
 379         struct iwl_queue *q;
 380         struct iwl_tfd *tfd, *tfd_tmp;
 381         u32 num_tbs;
 382
 383         q = &txq->q;
 384         tfd_tmp = (struct iwl_tfd *)txq->tfds;
 385         tfd = &tfd_tmp[q->write_ptr];
 386
 387         if (reset)
 388                 memset(tfd, 0, sizeof(*tfd));
 389
 390         num_tbs = iwl_tfd_get_num_tbs(tfd);
 391
 392         /* Each TFD can point to a maximum 20 Tx buffers */
 393         if (num_tbs >= IWL_NUM_OF_TBS) {
 394                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
 395                           IWL_NUM_OF_TBS);
 396                 return -EINVAL;
 397         }
 398
 399         BUG_ON(addr & ~DMA_BIT_MASK(36));
 400         if (unlikely(addr & ~IWL_TX_DMA_MASK))
 401                 IWL_ERR(priv, "Unaligned address = %llx\n",
 402                           (unsigned long long)addr);
 403
 404         iwl_tfd_set_tb(tfd, num_tbs, addr, len);
 405
 406         return 0;
 407 }
 408
 409 /*
 410  * Tell nic where to find circular buffer of Tx Frame Descriptors for
 411  * given Tx queue, and enable the DMA channel used for that queue.
 412  *
 413  * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
 414  * channels supported in hardware.
 415  */
 416 int iwl_hw_tx_queue_init(struct iwl_priv *priv,
 417                          struct iwl_tx_queue *txq)
 418 {
 419         int txq_id = txq->q.id;
 420
 421         /* Circular buffer (TFD queue in DRAM) physical base address */
 422         iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
 423                              txq->q.dma_addr >> 8);
 424
 425         return 0;
 426 }
 427
 428 /******************************************************************************
 429  *
 430  * Generic RX handler implementations
 431  *
 432  ******************************************************************************/
 433 static void iwl_rx_reply_alive(struct iwl_priv *priv,
 434                                 struct iwl_rx_mem_buffer *rxb)
 435 {
 436         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 437         struct iwl_alive_resp *palive;
 438         struct delayed_work *pwork;
 439
 440         palive = &pkt->u.alive_frame;
 441
 442         IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
 443                        "0x%01X 0x%01X\n",
 444                        palive->is_valid, palive->ver_type,
 445                        palive->ver_subtype);
 446
 447         if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
 448                 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
 449                 memcpy(&priv->card_alive_init,
 450                        &pkt->u.alive_frame,
 451                        sizeof(struct iwl_init_alive_resp));
 452                 pwork = &priv->init_alive_start;
 453         } else {
 454                 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
 455                 memcpy(&priv->card_alive, &pkt->u.alive_frame,
 456                        sizeof(struct iwl_alive_resp));
 457                 pwork = &priv->alive_start;
 458         }
 459
 460         /* We delay the ALIVE response by 5ms to
 461          * give the HW RF Kill time to activate... */
 462         if (palive->is_valid == UCODE_VALID_OK)
 463                 queue_delayed_work(priv->workqueue, pwork,
 464                                    msecs_to_jiffies(5));
 465         else {
 466                 IWL_WARN(priv, "%s uCode did not respond OK.\n",
 467                         (palive->ver_subtype == INITIALIZE_SUBTYPE) ?
 468                         "init" : "runtime");
 469                 queue_work(priv->workqueue, &priv->restart);
 470         }
 471 }
 472
 473 static void iwl_bg_beacon_update(struct work_struct *work)
 474 {
 475         struct iwl_priv *priv =
 476                 container_of(work, struct iwl_priv, beacon_update);
 477         struct sk_buff *beacon;
 478
 479         mutex_lock(&priv->mutex);
 480         if (!priv->beacon_ctx) {
 481                 IWL_ERR(priv, "updating beacon w/o beacon context!\n");
 482                 goto out;
 483         }
 484
 485         if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) {
 486                 /*
 487                  * The ucode will send beacon notifications even in
 488                  * IBSS mode, but we don't want to process them. But
 489                  * we need to defer the type check to here due to
 490                  * requiring locking around the beacon_ctx access.
 491                  */
 492                 goto out;
 493         }
 494
 495         /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
 496         beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif);
 497         if (!beacon) {
 498                 IWL_ERR(priv, "update beacon failed -- keeping old\n");
 499                 goto out;
 500         }
 501
 502         /* new beacon skb is allocated every time; dispose previous.*/
 503         dev_kfree_skb(priv->beacon_skb);
 504
 505         priv->beacon_skb = beacon;
 506
 507         iwlagn_send_beacon_cmd(priv);
 508  out:
 509         mutex_unlock(&priv->mutex);
 510 }
 511
 512 static void iwl_bg_bt_runtime_config(struct work_struct *work)
 513 {
 514         struct iwl_priv *priv =
 515                 container_of(work, struct iwl_priv, bt_runtime_config);
 516
 517         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 518                 return;
 519
 520         /* dont send host command if rf-kill is on */
 521         if (!iwl_is_ready_rf(priv))
 522                 return;
 523         priv->cfg->ops->hcmd->send_bt_config(priv);
 524 }
 525
 526 static void iwl_bg_bt_full_concurrency(struct work_struct *work)
 527 {
 528         struct iwl_priv *priv =
 529                 container_of(work, struct iwl_priv, bt_full_concurrency);
 530         struct iwl_rxon_context *ctx;
 531
 532         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 533                 return;
 534
 535         /* dont send host command if rf-kill is on */
 536         if (!iwl_is_ready_rf(priv))
 537                 return;
 538
 539         IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
 540                        priv->bt_full_concurrent ?
 541                        "full concurrency" : "3-wire");
 542
 543         /*
 544          * LQ & RXON updated cmds must be sent before BT Config cmd
 545          * to avoid 3-wire collisions
 546          */
 547         mutex_lock(&priv->mutex);
 548         for_each_context(priv, ctx) {
 549                 if (priv->cfg->ops->hcmd->set_rxon_chain)
 550                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
 551                 iwlcore_commit_rxon(priv, ctx);
 552         }
 553         mutex_unlock(&priv->mutex);
 554
 555         priv->cfg->ops->hcmd->send_bt_config(priv);
 556 }
 557
 558 /**
 559  * iwl_bg_statistics_periodic - Timer callback to queue statistics
 560  *
 561  * This callback is provided in order to send a statistics request.
 562  *
 563  * This timer function is continually reset to execute within
 564  * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
 565  * was received.  We need to ensure we receive the statistics in order
 566  * to update the temperature used for calibrating the TXPOWER.
 567  */
 568 static void iwl_bg_statistics_periodic(unsigned long data)
 569 {
 570         struct iwl_priv *priv = (struct iwl_priv *)data;
 571
 572         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 573                 return;
 574
 575         /* dont send host command if rf-kill is on */
 576         if (!iwl_is_ready_rf(priv))
 577                 return;
 578
 579         iwl_send_statistics_request(priv, CMD_ASYNC, false);
 580 }
 581
 582
 583 static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
 584                                         u32 start_idx, u32 num_events,
 585                                         u32 mode)
 586 {
 587         u32 i;
 588         u32 ptr;        /* SRAM byte address of log data */
 589         u32 ev, time, data; /* event log data */
 590         unsigned long reg_flags;
 591
 592         if (mode == 0)
 593                 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
 594         else
 595                 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
 596
 597         /* Make sure device is powered up for SRAM reads */
 598         spin_lock_irqsave(&priv->reg_lock, reg_flags);
 599         if (iwl_grab_nic_access(priv)) {
 600                 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
 601                 return;
 602         }
 603
 604         /* Set starting address; reads will auto-increment */
 605         _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
 606         rmb();
 607
 608         /*
 609          * "time" is actually "data" for mode 0 (no timestamp).
 610          * place event id # at far right for easier visual parsing.
 611          */
 612         for (i = 0; i < num_events; i++) {
 613                 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 614                 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 615                 if (mode == 0) {
 616                         trace_iwlwifi_dev_ucode_cont_event(priv,
 617                                                         0, time, ev);
 618                 } else {
 619                         data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 620                         trace_iwlwifi_dev_ucode_cont_event(priv,
 621                                                 time, data, ev);
 622                 }
 623         }
 624         /* Allow device to power down */
 625         iwl_release_nic_access(priv);
 626         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
 627 }
 628
 629 static void iwl_continuous_event_trace(struct iwl_priv *priv)
 630 {
 631         u32 capacity;   /* event log capacity in # entries */
 632         u32 base;       /* SRAM byte address of event log header */
 633         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
 634         u32 num_wraps;  /* # times uCode wrapped to top of log */
 635         u32 next_entry; /* index of next entry to be written by uCode */
 636
 637         if (priv->ucode_type == UCODE_INIT)
 638                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
 639         else
 640                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
 641         if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
 642                 capacity = iwl_read_targ_mem(priv, base);
 643                 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
 644                 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
 645                 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
 646         } else
 647                 return;
 648
 649         if (num_wraps == priv->event_log.num_wraps) {
 650                 iwl_print_cont_event_trace(priv,
 651                                        base, priv->event_log.next_entry,
 652                                        next_entry - priv->event_log.next_entry,
 653                                        mode);
 654                 priv->event_log.non_wraps_count++;
 655         } else {
 656                 if ((num_wraps - priv->event_log.num_wraps) > 1)
 657                         priv->event_log.wraps_more_count++;
 658                 else
 659                         priv->event_log.wraps_once_count++;
 660                 trace_iwlwifi_dev_ucode_wrap_event(priv,
 661                                 num_wraps - priv->event_log.num_wraps,
 662                                 next_entry, priv->event_log.next_entry);
 663                 if (next_entry < priv->event_log.next_entry) {
 664                         iwl_print_cont_event_trace(priv, base,
 665                                priv->event_log.next_entry,
 666                                capacity - priv->event_log.next_entry,
 667                                mode);
 668
 669                         iwl_print_cont_event_trace(priv, base, 0,
 670                                 next_entry, mode);
 671                 } else {
 672                         iwl_print_cont_event_trace(priv, base,
 673                                next_entry, capacity - next_entry,
 674                                mode);
 675
 676                         iwl_print_cont_event_trace(priv, base, 0,
 677                                 next_entry, mode);
 678                 }
 679         }
 680         priv->event_log.num_wraps = num_wraps;
 681         priv->event_log.next_entry = next_entry;
 682 }
 683
 684 /**
 685  * iwl_bg_ucode_trace - Timer callback to log ucode event
 686  *
 687  * The timer is continually set to execute every
 688  * UCODE_TRACE_PERIOD milliseconds after the last timer expired
 689  * this function is to perform continuous uCode event logging operation
 690  * if enabled
 691  */
 692 static void iwl_bg_ucode_trace(unsigned long data)
 693 {
 694         struct iwl_priv *priv = (struct iwl_priv *)data;
 695
 696         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 697                 return;
 698
 699         if (priv->event_log.ucode_trace) {
 700                 iwl_continuous_event_trace(priv);
 701                 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
 702                 mod_timer(&priv->ucode_trace,
 703                          jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
 704         }
 705 }
 706
 707 static void iwlagn_rx_beacon_notif(struct iwl_priv *priv,
 708                                    struct iwl_rx_mem_buffer *rxb)
 709 {
 710         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 711         struct iwlagn_beacon_notif *beacon = (void *)pkt->u.raw;
 712 #ifdef CONFIG_IWLWIFI_DEBUG
 713         u16 status = le16_to_cpu(beacon->beacon_notify_hdr.status.status);
 714         u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
 715
 716         IWL_DEBUG_RX(priv, "beacon status %#x, retries:%d ibssmgr:%d "
 717                 "tsf:0x%.8x%.8x rate:%d\n",
 718                 status & TX_STATUS_MSK,
 719                 beacon->beacon_notify_hdr.failure_frame,
 720                 le32_to_cpu(beacon->ibss_mgr_status),
 721                 le32_to_cpu(beacon->high_tsf),
 722                 le32_to_cpu(beacon->low_tsf), rate);
 723 #endif
 724
 725         priv->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
 726
 727         if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
 728                 queue_work(priv->workqueue, &priv->beacon_update);
 729 }
 730
 731 /* Handle notification from uCode that card's power state is changing
 732  * due to software, hardware, or critical temperature RFKILL */
 733 static void iwl_rx_card_state_notif(struct iwl_priv *priv,
 734                                     struct iwl_rx_mem_buffer *rxb)
 735 {
 736         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 737         u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
 738         unsigned long status = priv->status;
 739
 740         IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
 741                           (flags & HW_CARD_DISABLED) ? "Kill" : "On",
 742                           (flags & SW_CARD_DISABLED) ? "Kill" : "On",
 743                           (flags & CT_CARD_DISABLED) ?
 744                           "Reached" : "Not reached");
 745
 746         if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
 747                      CT_CARD_DISABLED)) {
 748
 749                 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
 750                             CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 751
 752                 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
 753                                         HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
 754
 755                 if (!(flags & RXON_CARD_DISABLED)) {
 756                         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
 757                                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 758                         iwl_write_direct32(priv, HBUS_TARG_MBX_C,
 759                                         HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
 760                 }
 761                 if (flags & CT_CARD_DISABLED)
 762                         iwl_tt_enter_ct_kill(priv);
 763         }
 764         if (!(flags & CT_CARD_DISABLED))
 765                 iwl_tt_exit_ct_kill(priv);
 766
 767         if (flags & HW_CARD_DISABLED)
 768                 set_bit(STATUS_RF_KILL_HW, &priv->status);
 769         else
 770                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
 771
 772
 773         if (!(flags & RXON_CARD_DISABLED))
 774                 iwl_scan_cancel(priv);
 775
 776         if ((test_bit(STATUS_RF_KILL_HW, &status) !=
 777              test_bit(STATUS_RF_KILL_HW, &priv->status)))
 778                 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
 779                         test_bit(STATUS_RF_KILL_HW, &priv->status));
 780         else
 781                 wake_up_interruptible(&priv->wait_command_queue);
 782 }
 783
 784 static void iwl_bg_tx_flush(struct work_struct *work)
 785 {
 786         struct iwl_priv *priv =
 787                 container_of(work, struct iwl_priv, tx_flush);
 788
 789         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 790                 return;
 791
 792         /* do nothing if rf-kill is on */
 793         if (!iwl_is_ready_rf(priv))
 794                 return;
 795
 796         if (priv->cfg->ops->lib->txfifo_flush) {
 797                 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
 798                 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
 799         }
 800 }
 801
 802 /**
 803  * iwl_setup_rx_handlers - Initialize Rx handler callbacks
 804  *
 805  * Setup the RX handlers for each of the reply types sent from the uCode
 806  * to the host.
 807  *
 808  * This function chains into the hardware specific files for them to setup
 809  * any hardware specific handlers as well.
 810  */
 811 static void iwl_setup_rx_handlers(struct iwl_priv *priv)
 812 {
 813         priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
 814         priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
 815         priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
 816         priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
 817                         iwl_rx_spectrum_measure_notif;
 818         priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
 819         priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
 820             iwl_rx_pm_debug_statistics_notif;
 821         priv->rx_handlers[BEACON_NOTIFICATION] = iwlagn_rx_beacon_notif;
 822
 823         /*
 824          * The same handler is used for both the REPLY to a discrete
 825          * statistics request from the host as well as for the periodic
 826          * statistics notifications (after received beacons) from the uCode.
 827          */
 828         priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
 829         priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
 830
 831         iwl_setup_rx_scan_handlers(priv);
 832
 833         /* status change handler */
 834         priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
 835
 836         priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
 837             iwl_rx_missed_beacon_notif;
 838         /* Rx handlers */
 839         priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
 840         priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
 841         /* block ack */
 842         priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
 843         /* Set up hardware specific Rx handlers */
 844         priv->cfg->ops->lib->rx_handler_setup(priv);
 845 }
 846
 847 /**
 848  * iwl_rx_handle - Main entry function for receiving responses from uCode
 849  *
 850  * Uses the priv->rx_handlers callback function array to invoke
 851  * the appropriate handlers, including command responses,
 852  * frame-received notifications, and other notifications.
 853  */
 854 static void iwl_rx_handle(struct iwl_priv *priv)
 855 {
 856         struct iwl_rx_mem_buffer *rxb;
 857         struct iwl_rx_packet *pkt;
 858         struct iwl_rx_queue *rxq = &priv->rxq;
 859         u32 r, i;
 860         int reclaim;
 861         unsigned long flags;
 862         u8 fill_rx = 0;
 863         u32 count = 8;
 864         int total_empty;
 865
 866         /* uCode's read index (stored in shared DRAM) indicates the last Rx
 867          * buffer that the driver may process (last buffer filled by ucode). */
 868         r = le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF;
 869         i = rxq->read;
 870
 871         /* Rx interrupt, but nothing sent from uCode */
 872         if (i == r)
 873                 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
 874
 875         /* calculate total frames need to be restock after handling RX */
 876         total_empty = r - rxq->write_actual;
 877         if (total_empty < 0)
 878                 total_empty += RX_QUEUE_SIZE;
 879
 880         if (total_empty > (RX_QUEUE_SIZE / 2))
 881                 fill_rx = 1;
 882
 883         while (i != r) {
 884                 int len;
 885
 886                 rxb = rxq->queue[i];
 887
 888                 /* If an RXB doesn't have a Rx queue slot associated with it,
 889                  * then a bug has been introduced in the queue refilling
 890                  * routines -- catch it here */
 891                 BUG_ON(rxb == NULL);
 892
 893                 rxq->queue[i] = NULL;
 894
 895                 pci_unmap_page(priv->pci_dev, rxb->page_dma,
 896                                PAGE_SIZE << priv->hw_params.rx_page_order,
 897                                PCI_DMA_FROMDEVICE);
 898                 pkt = rxb_addr(rxb);
 899
 900                 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
 901                 len += sizeof(u32); /* account for status word */
 902                 trace_iwlwifi_dev_rx(priv, pkt, len);
 903
 904                 /* Reclaim a command buffer only if this packet is a response
 905                  *   to a (driver-originated) command.
 906                  * If the packet (e.g. Rx frame) originated from uCode,
 907                  *   there is no command buffer to reclaim.
 908                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
 909                  *   but apparently a few don't get set; catch them here. */
 910                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
 911                         (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
 912                         (pkt->hdr.cmd != REPLY_RX) &&
 913                         (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
 914                         (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
 915                         (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
 916                         (pkt->hdr.cmd != REPLY_TX);
 917
 918                 /*
 919                  * Do the notification wait before RX handlers so
 920                  * even if the RX handler consumes the RXB we have
 921                  * access to it in the notification wait entry.
 922                  */
 923                 if (!list_empty(&priv->_agn.notif_waits)) {
 924                         struct iwl_notification_wait *w;
 925
 926                         spin_lock(&priv->_agn.notif_wait_lock);
 927                         list_for_each_entry(w, &priv->_agn.notif_waits, list) {
 928                                 if (w->cmd == pkt->hdr.cmd) {
 929                                         w->triggered = true;
 930                                         if (w->fn)
 931                                                 w->fn(priv, pkt);
 932                                 }
 933                         }
 934                         spin_unlock(&priv->_agn.notif_wait_lock);
 935
 936                         wake_up_all(&priv->_agn.notif_waitq);
 937                 }
 938
 939                 /* Based on type of command response or notification,
 940                  *   handle those that need handling via function in
 941                  *   rx_handlers table.  See iwl_setup_rx_handlers() */
 942                 if (priv->rx_handlers[pkt->hdr.cmd]) {
 943                         IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
 944                                 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
 945                         priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
 946                         priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
 947                 } else {
 948                         /* No handling needed */
 949                         IWL_DEBUG_RX(priv,
 950                                 "r %d i %d No handler needed for %s, 0x%02x\n",
 951                                 r, i, get_cmd_string(pkt->hdr.cmd),
 952                                 pkt->hdr.cmd);
 953                 }
 954
 955                 /*
 956                  * XXX: After here, we should always check rxb->page
 957                  * against NULL before touching it or its virtual
 958                  * memory (pkt). Because some rx_handler might have
 959                  * already taken or freed the pages.
 960                  */
 961
 962                 if (reclaim) {
 963                         /* Invoke any callbacks, transfer the buffer to caller,
 964                          * and fire off the (possibly) blocking iwl_send_cmd()
 965                          * as we reclaim the driver command queue */
 966                         if (rxb->page)
 967                                 iwl_tx_cmd_complete(priv, rxb);
 968                         else
 969                                 IWL_WARN(priv, "Claim null rxb?\n");
 970                 }
 971
 972                 /* Reuse the page if possible. For notification packets and
 973                  * SKBs that fail to Rx correctly, add them back into the
 974                  * rx_free list for reuse later. */
 975                 spin_lock_irqsave(&rxq->lock, flags);
 976                 if (rxb->page != NULL) {
 977                         rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
 978                                 0, PAGE_SIZE << priv->hw_params.rx_page_order,
 979                                 PCI_DMA_FROMDEVICE);
 980                         list_add_tail(&rxb->list, &rxq->rx_free);
 981                         rxq->free_count++;
 982                 } else
 983                         list_add_tail(&rxb->list, &rxq->rx_used);
 984
 985                 spin_unlock_irqrestore(&rxq->lock, flags);
 986
 987                 i = (i + 1) & RX_QUEUE_MASK;
 988                 /* If there are a lot of unused frames,
 989                  * restock the Rx queue so ucode wont assert. */
 990                 if (fill_rx) {
 991                         count++;
 992                         if (count >= 8) {
 993                                 rxq->read = i;
 994                                 iwlagn_rx_replenish_now(priv);
 995                                 count = 0;
 996                         }
 997                 }
 998         }
 999
1000         /* Backtrack one entry */
1001         rxq->read = i;
1002         if (fill_rx)
1003                 iwlagn_rx_replenish_now(priv);
1004         else
1005                 iwlagn_rx_queue_restock(priv);
1006 }
1007
1008 /* call this function to flush any scheduled tasklet */
1009 static inline void iwl_synchronize_irq(struct iwl_priv *priv)
1010 {
1011         /* wait to make sure we flush pending tasklet*/
1012         synchronize_irq(priv->pci_dev->irq);
1013         tasklet_kill(&priv->irq_tasklet);
1014 }
1015
1016 static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
1017 {
1018         u32 inta, handled = 0;
1019         u32 inta_fh;
1020         unsigned long flags;
1021         u32 i;
1022 #ifdef CONFIG_IWLWIFI_DEBUG
1023         u32 inta_mask;
1024 #endif
1025
1026         spin_lock_irqsave(&priv->lock, flags);
1027
1028         /* Ack/clear/reset pending uCode interrupts.
1029          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1030          *  and will clear only when CSR_FH_INT_STATUS gets cleared. */
1031         inta = iwl_read32(priv, CSR_INT);
1032         iwl_write32(priv, CSR_INT, inta);
1033
1034         /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1035          * Any new interrupts that happen after this, either while we're
1036          * in this tasklet, or later, will show up in next ISR/tasklet. */
1037         inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1038         iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
1039
1040 #ifdef CONFIG_IWLWIFI_DEBUG
1041         if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1042                 /* just for debug */
1043                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1044                 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
1045                               inta, inta_mask, inta_fh);
1046         }
1047 #endif
1048
1049         spin_unlock_irqrestore(&priv->lock, flags);
1050
1051         /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1052          * atomic, make sure that inta covers all the interrupts that
1053          * we've discovered, even if FH interrupt came in just after
1054          * reading CSR_INT. */
1055         if (inta_fh & CSR49_FH_INT_RX_MASK)
1056                 inta |= CSR_INT_BIT_FH_RX;
1057         if (inta_fh & CSR49_FH_INT_TX_MASK)
1058                 inta |= CSR_INT_BIT_FH_TX;
1059
1060         /* Now service all interrupt bits discovered above. */
1061         if (inta & CSR_INT_BIT_HW_ERR) {
1062                 IWL_ERR(priv, "Hardware error detected.  Restarting.\n");
1063
1064                 /* Tell the device to stop sending interrupts */
1065                 iwl_disable_interrupts(priv);
1066
1067                 priv->isr_stats.hw++;
1068                 iwl_irq_handle_error(priv);
1069
1070                 handled |= CSR_INT_BIT_HW_ERR;
1071
1072                 return;
1073         }
1074
1075 #ifdef CONFIG_IWLWIFI_DEBUG
1076         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1077                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1078                 if (inta & CSR_INT_BIT_SCD) {
1079                         IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1080                                       "the frame/frames.\n");
1081                         priv->isr_stats.sch++;
1082                 }
1083
1084                 /* Alive notification via Rx interrupt will do the real work */
1085                 if (inta & CSR_INT_BIT_ALIVE) {
1086                         IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1087                         priv->isr_stats.alive++;
1088                 }
1089         }
1090 #endif
1091         /* Safely ignore these bits for debug checks below */
1092         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1093
1094         /* HW RF KILL switch toggled */
1095         if (inta & CSR_INT_BIT_RF_KILL) {
1096                 int hw_rf_kill = 0;
1097                 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1098                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1099                         hw_rf_kill = 1;
1100
1101                 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1102                                 hw_rf_kill ? "disable radio" : "enable radio");
1103
1104                 priv->isr_stats.rfkill++;
1105
1106                 /* driver only loads ucode once setting the interface up.
1107                  * the driver allows loading the ucode even if the radio
1108                  * is killed. Hence update the killswitch state here. The
1109                  * rfkill handler will care about restarting if needed.
1110                  */
1111                 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1112                         if (hw_rf_kill)
1113                                 set_bit(STATUS_RF_KILL_HW, &priv->status);
1114                         else
1115                                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1116                         wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1117                 }
1118
1119                 handled |= CSR_INT_BIT_RF_KILL;
1120         }
1121
1122         /* Chip got too hot and stopped itself */
1123         if (inta & CSR_INT_BIT_CT_KILL) {
1124                 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1125                 priv->isr_stats.ctkill++;
1126                 handled |= CSR_INT_BIT_CT_KILL;
1127         }
1128
1129         /* Error detected by uCode */
1130         if (inta & CSR_INT_BIT_SW_ERR) {
1131                 IWL_ERR(priv, "Microcode SW error detected. "
1132                         " Restarting 0x%X.\n", inta);
1133                 priv->isr_stats.sw++;
1134                 iwl_irq_handle_error(priv);
1135                 handled |= CSR_INT_BIT_SW_ERR;
1136         }
1137
1138         /*
1139          * uCode wakes up after power-down sleep.
1140          * Tell device about any new tx or host commands enqueued,
1141          * and about any Rx buffers made available while asleep.
1142          */
1143         if (inta & CSR_INT_BIT_WAKEUP) {
1144                 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1145                 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1146                 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1147                         iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1148                 priv->isr_stats.wakeup++;
1149                 handled |= CSR_INT_BIT_WAKEUP;
1150         }
1151
1152         /* All uCode command responses, including Tx command responses,
1153          * Rx "responses" (frame-received notification), and other
1154          * notifications from uCode come through here*/
1155         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1156                 iwl_rx_handle(priv);
1157                 priv->isr_stats.rx++;
1158                 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1159         }
1160
1161         /* This "Tx" DMA channel is used only for loading uCode */
1162         if (inta & CSR_INT_BIT_FH_TX) {
1163                 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1164                 priv->isr_stats.tx++;
1165                 handled |= CSR_INT_BIT_FH_TX;
1166                 /* Wake up uCode load routine, now that load is complete */
1167                 priv->ucode_write_complete = 1;
1168                 wake_up_interruptible(&priv->wait_command_queue);
1169         }
1170
1171         if (inta & ~handled) {
1172                 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1173                 priv->isr_stats.unhandled++;
1174         }
1175
1176         if (inta & ~(priv->inta_mask)) {
1177                 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1178                          inta & ~priv->inta_mask);
1179                 IWL_WARN(priv, "   with FH_INT = 0x%08x\n", inta_fh);
1180         }
1181
1182         /* Re-enable all interrupts */
1183         /* only Re-enable if disabled by irq */
1184         if (test_bit(STATUS_INT_ENABLED, &priv->status))
1185                 iwl_enable_interrupts(priv);
1186
1187 #ifdef CONFIG_IWLWIFI_DEBUG
1188         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1189                 inta = iwl_read32(priv, CSR_INT);
1190                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1191                 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1192                 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
1193                         "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1194         }
1195 #endif
1196 }
1197
1198 /* tasklet for iwlagn interrupt */
1199 static void iwl_irq_tasklet(struct iwl_priv *priv)
1200 {
1201         u32 inta = 0;
1202         u32 handled = 0;
1203         unsigned long flags;
1204         u32 i;
1205 #ifdef CONFIG_IWLWIFI_DEBUG
1206         u32 inta_mask;
1207 #endif
1208
1209         spin_lock_irqsave(&priv->lock, flags);
1210
1211         /* Ack/clear/reset pending uCode interrupts.
1212          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1213          */
1214         /* There is a hardware bug in the interrupt mask function that some
1215          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1216          * they are disabled in the CSR_INT_MASK register. Furthermore the
1217          * ICT interrupt handling mechanism has another bug that might cause
1218          * these unmasked interrupts fail to be detected. We workaround the
1219          * hardware bugs here by ACKing all the possible interrupts so that
1220          * interrupt coalescing can still be achieved.
1221          */
1222         iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
1223
1224         inta = priv->_agn.inta;
1225
1226 #ifdef CONFIG_IWLWIFI_DEBUG
1227         if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1228                 /* just for debug */
1229                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1230                 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1231                                 inta, inta_mask);
1232         }
1233 #endif
1234
1235         spin_unlock_irqrestore(&priv->lock, flags);
1236
1237         /* saved interrupt in inta variable now we can reset priv->_agn.inta */
1238         priv->_agn.inta = 0;
1239
1240         /* Now service all interrupt bits discovered above. */
1241         if (inta & CSR_INT_BIT_HW_ERR) {
1242                 IWL_ERR(priv, "Hardware error detected.  Restarting.\n");
1243
1244                 /* Tell the device to stop sending interrupts */
1245                 iwl_disable_interrupts(priv);
1246
1247                 priv->isr_stats.hw++;
1248                 iwl_irq_handle_error(priv);
1249
1250                 handled |= CSR_INT_BIT_HW_ERR;
1251
1252                 return;
1253         }
1254
1255 #ifdef CONFIG_IWLWIFI_DEBUG
1256         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1257                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1258                 if (inta & CSR_INT_BIT_SCD) {
1259                         IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1260                                       "the frame/frames.\n");
1261                         priv->isr_stats.sch++;
1262                 }
1263
1264                 /* Alive notification via Rx interrupt will do the real work */
1265                 if (inta & CSR_INT_BIT_ALIVE) {
1266                         IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1267                         priv->isr_stats.alive++;
1268                 }
1269         }
1270 #endif
1271         /* Safely ignore these bits for debug checks below */
1272         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1273
1274         /* HW RF KILL switch toggled */
1275         if (inta & CSR_INT_BIT_RF_KILL) {
1276                 int hw_rf_kill = 0;
1277                 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1278                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1279                         hw_rf_kill = 1;
1280
1281                 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1282                                 hw_rf_kill ? "disable radio" : "enable radio");
1283
1284                 priv->isr_stats.rfkill++;
1285
1286                 /* driver only loads ucode once setting the interface up.
1287                  * the driver allows loading the ucode even if the radio
1288                  * is killed. Hence update the killswitch state here. The
1289                  * rfkill handler will care about restarting if needed.
1290                  */
1291                 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1292                         if (hw_rf_kill)
1293                                 set_bit(STATUS_RF_KILL_HW, &priv->status);
1294                         else
1295                                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1296                         wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1297                 }
1298
1299                 handled |= CSR_INT_BIT_RF_KILL;
1300         }
1301
1302         /* Chip got too hot and stopped itself */
1303         if (inta & CSR_INT_BIT_CT_KILL) {
1304                 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1305                 priv->isr_stats.ctkill++;
1306                 handled |= CSR_INT_BIT_CT_KILL;
1307         }
1308
1309         /* Error detected by uCode */
1310         if (inta & CSR_INT_BIT_SW_ERR) {
1311                 IWL_ERR(priv, "Microcode SW error detected. "
1312                         " Restarting 0x%X.\n", inta);
1313                 priv->isr_stats.sw++;
1314                 iwl_irq_handle_error(priv);
1315                 handled |= CSR_INT_BIT_SW_ERR;
1316         }
1317
1318         /* uCode wakes up after power-down sleep */
1319         if (inta & CSR_INT_BIT_WAKEUP) {
1320                 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1321                 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1322                 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1323                         iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1324
1325                 priv->isr_stats.wakeup++;
1326
1327                 handled |= CSR_INT_BIT_WAKEUP;
1328         }
1329
1330         /* All uCode command responses, including Tx command responses,
1331          * Rx "responses" (frame-received notification), and other
1332          * notifications from uCode come through here*/
1333         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1334                         CSR_INT_BIT_RX_PERIODIC)) {
1335                 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
1336                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1337                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1338                         iwl_write32(priv, CSR_FH_INT_STATUS,
1339                                         CSR49_FH_INT_RX_MASK);
1340                 }
1341                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1342                         handled |= CSR_INT_BIT_RX_PERIODIC;
1343                         iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1344                 }
1345                 /* Sending RX interrupt require many steps to be done in the
1346                  * the device:
1347                  * 1- write interrupt to current index in ICT table.
1348                  * 2- dma RX frame.
1349                  * 3- update RX shared data to indicate last write index.
1350                  * 4- send interrupt.
1351                  * This could lead to RX race, driver could receive RX interrupt
1352                  * but the shared data changes does not reflect this;
1353                  * periodic interrupt will detect any dangling Rx activity.
1354                  */
1355
1356                 /* Disable periodic interrupt; we use it as just a one-shot. */
1357                 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1358                             CSR_INT_PERIODIC_DIS);
1359                 iwl_rx_handle(priv);
1360
1361                 /*
1362                  * Enable periodic interrupt in 8 msec only if we received
1363                  * real RX interrupt (instead of just periodic int), to catch
1364                  * any dangling Rx interrupt.  If it was just the periodic
1365                  * interrupt, there was no dangling Rx activity, and no need
1366                  * to extend the periodic interrupt; one-shot is enough.
1367                  */
1368                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1369                         iwl_write8(priv, CSR_INT_PERIODIC_REG,
1370                                     CSR_INT_PERIODIC_ENA);
1371
1372                 priv->isr_stats.rx++;
1373         }
1374
1375         /* This "Tx" DMA channel is used only for loading uCode */
1376         if (inta & CSR_INT_BIT_FH_TX) {
1377                 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
1378                 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1379                 priv->isr_stats.tx++;
1380                 handled |= CSR_INT_BIT_FH_TX;
1381                 /* Wake up uCode load routine, now that load is complete */
1382                 priv->ucode_write_complete = 1;
1383                 wake_up_interruptible(&priv->wait_command_queue);
1384         }
1385
1386         if (inta & ~handled) {
1387                 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1388                 priv->isr_stats.unhandled++;
1389         }
1390
1391         if (inta & ~(priv->inta_mask)) {
1392                 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1393                          inta & ~priv->inta_mask);
1394         }
1395
1396         /* Re-enable all interrupts */
1397         /* only Re-enable if disabled by irq */
1398         if (test_bit(STATUS_INT_ENABLED, &priv->status))
1399                 iwl_enable_interrupts(priv);
1400 }
1401
1402 /* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
1403 #define ACK_CNT_RATIO (50)
1404 #define BA_TIMEOUT_CNT (5)
1405 #define BA_TIMEOUT_MAX (16)
1406
1407 /**
1408  * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
1409  *
1410  * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding
1411  * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
1412  * operation state.
1413  */
1414 bool iwl_good_ack_health(struct iwl_priv *priv,
1415                                 struct iwl_rx_packet *pkt)
1416 {
1417         bool rc = true;
1418         int actual_ack_cnt_delta, expected_ack_cnt_delta;
1419         int ba_timeout_delta;
1420
1421         actual_ack_cnt_delta =
1422                 le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) -
1423                 le32_to_cpu(priv->_agn.statistics.tx.actual_ack_cnt);
1424         expected_ack_cnt_delta =
1425                 le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) -
1426                 le32_to_cpu(priv->_agn.statistics.tx.expected_ack_cnt);
1427         ba_timeout_delta =
1428                 le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) -
1429                 le32_to_cpu(priv->_agn.statistics.tx.agg.ba_timeout);
1430         if ((priv->_agn.agg_tids_count > 0) &&
1431             (expected_ack_cnt_delta > 0) &&
1432             (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta)
1433                 < ACK_CNT_RATIO) &&
1434             (ba_timeout_delta > BA_TIMEOUT_CNT)) {
1435                 IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d,"
1436                                 " expected_ack_cnt = %d\n",
1437                                 actual_ack_cnt_delta, expected_ack_cnt_delta);
1438
1439 #ifdef CONFIG_IWLWIFI_DEBUGFS
1440                 /*
1441                  * This is ifdef'ed on DEBUGFS because otherwise the
1442                  * statistics aren't available. If DEBUGFS is set but
1443                  * DEBUG is not, these will just compile out.
1444                  */
1445                 IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n",
1446                                 priv->_agn.delta_statistics.tx.rx_detected_cnt);
1447                 IWL_DEBUG_RADIO(priv,
1448                                 "ack_or_ba_timeout_collision delta = %d\n",
1449                                 priv->_agn.delta_statistics.tx.
1450                                 ack_or_ba_timeout_collision);
1451 #endif
1452                 IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n",
1453                                 ba_timeout_delta);
1454                 if (!actual_ack_cnt_delta &&
1455                     (ba_timeout_delta >= BA_TIMEOUT_MAX))
1456                         rc = false;
1457         }
1458         return rc;
1459 }
1460
1461
1462 /*****************************************************************************
1463  *
1464  * sysfs attributes
1465  *
1466  *****************************************************************************/
1467
1468 #ifdef CONFIG_IWLWIFI_DEBUG
1469
1470 /*
1471  * The following adds a new attribute to the sysfs representation
1472  * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1473  * used for controlling the debug level.
1474  *
1475  * See the level definitions in iwl for details.
1476  *
1477  * The debug_level being managed using sysfs below is a per device debug
1478  * level that is used instead of the global debug level if it (the per
1479  * device debug level) is set.
1480  */
1481 static ssize_t show_debug_level(struct device *d,
1482                                 struct device_attribute *attr, char *buf)
1483 {
1484         struct iwl_priv *priv = dev_get_drvdata(d);
1485         return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1486 }
1487 static ssize_t store_debug_level(struct device *d,
1488                                 struct device_attribute *attr,
1489                                  const char *buf, size_t count)
1490 {
1491         struct iwl_priv *priv = dev_get_drvdata(d);
1492         unsigned long val;
1493         int ret;
1494
1495         ret = strict_strtoul(buf, 0, &val);
1496         if (ret)
1497                 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1498         else {
1499                 priv->debug_level = val;
1500                 if (iwl_alloc_traffic_mem(priv))
1501                         IWL_ERR(priv,
1502                                 "Not enough memory to generate traffic log\n");
1503         }
1504         return strnlen(buf, count);
1505 }
1506
1507 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1508                         show_debug_level, store_debug_level);
1509
1510
1511 #endif /* CONFIG_IWLWIFI_DEBUG */
1512
1513
1514 static ssize_t show_temperature(struct device *d,
1515                                 struct device_attribute *attr, char *buf)
1516 {
1517         struct iwl_priv *priv = dev_get_drvdata(d);
1518
1519         if (!iwl_is_alive(priv))
1520                 return -EAGAIN;
1521
1522         return sprintf(buf, "%d\n", priv->temperature);
1523 }
1524
1525 static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1526
1527 static ssize_t show_tx_power(struct device *d,
1528                              struct device_attribute *attr, char *buf)
1529 {
1530         struct iwl_priv *priv = dev_get_drvdata(d);
1531
1532         if (!iwl_is_ready_rf(priv))
1533                 return sprintf(buf, "off\n");
1534         else
1535                 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1536 }
1537
1538 static ssize_t store_tx_power(struct device *d,
1539                               struct device_attribute *attr,
1540                               const char *buf, size_t count)
1541 {
1542         struct iwl_priv *priv = dev_get_drvdata(d);
1543         unsigned long val;
1544         int ret;
1545
1546         ret = strict_strtoul(buf, 10, &val);
1547         if (ret)
1548                 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1549         else {
1550                 ret = iwl_set_tx_power(priv, val, false);
1551                 if (ret)
1552                         IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1553                                 ret);
1554                 else
1555                         ret = count;
1556         }
1557         return ret;
1558 }
1559
1560 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1561
1562 static struct attribute *iwl_sysfs_entries[] = {
1563         &dev_attr_temperature.attr,
1564         &dev_attr_tx_power.attr,
1565 #ifdef CONFIG_IWLWIFI_DEBUG
1566         &dev_attr_debug_level.attr,
1567 #endif
1568         NULL
1569 };
1570
1571 static struct attribute_group iwl_attribute_group = {
1572         .name = NULL,           /* put in device directory */
1573         .attrs = iwl_sysfs_entries,
1574 };
1575
1576 /******************************************************************************
1577  *
1578  * uCode download functions
1579  *
1580  ******************************************************************************/
1581
1582 static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
1583 {
1584         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1585         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1586         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1587         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1588         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1589         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
1590 }
1591
1592 static void iwl_nic_start(struct iwl_priv *priv)
1593 {
1594         /* Remove all resets to allow NIC to operate */
1595         iwl_write32(priv, CSR_RESET, 0);
1596 }
1597
1598 struct iwlagn_ucode_capabilities {
1599         u32 max_probe_length;
1600         u32 standard_phy_calibration_size;
1601         bool pan;
1602 };
1603
1604 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
1605 static int iwl_mac_setup_register(struct iwl_priv *priv,
1606                                   struct iwlagn_ucode_capabilities *capa);
1607
1608 #define UCODE_EXPERIMENTAL_INDEX        100
1609 #define UCODE_EXPERIMENTAL_TAG          "exp"
1610
1611 static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1612 {
1613         const char *name_pre = priv->cfg->fw_name_pre;
1614         char tag[8];
1615
1616         if (first) {
1617 #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1618                 priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1619                 strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1620         } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1621 #endif
1622                 priv->fw_index = priv->cfg->ucode_api_max;
1623                 sprintf(tag, "%d", priv->fw_index);
1624         } else {
1625                 priv->fw_index--;
1626                 sprintf(tag, "%d", priv->fw_index);
1627         }
1628
1629         if (priv->fw_index < priv->cfg->ucode_api_min) {
1630                 IWL_ERR(priv, "no suitable firmware found!\n");
1631                 return -ENOENT;
1632         }
1633
1634         sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
1635
1636         IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1637                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1638                                 ? "EXPERIMENTAL " : "",
1639                        priv->firmware_name);
1640
1641         return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1642                                        &priv->pci_dev->dev, GFP_KERNEL, priv,
1643                                        iwl_ucode_callback);
1644 }
1645
1646 struct iwlagn_firmware_pieces {
1647         const void *inst, *data, *init, *init_data, *boot;
1648         size_t inst_size, data_size, init_size, init_data_size, boot_size;
1649
1650         u32 build;
1651
1652         u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1653         u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
1654 };
1655
1656 static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1657                                        const struct firmware *ucode_raw,
1658                                        struct iwlagn_firmware_pieces *pieces)
1659 {
1660         struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1661         u32 api_ver, hdr_size;
1662         const u8 *src;
1663
1664         priv->ucode_ver = le32_to_cpu(ucode->ver);
1665         api_ver = IWL_UCODE_API(priv->ucode_ver);
1666
1667         switch (api_ver) {
1668         default:
1669                 /*
1670                  * 4965 doesn't revision the firmware file format
1671                  * along with the API version, it always uses v1
1672                  * file format.
1673                  */
1674                 if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) !=
1675                                 CSR_HW_REV_TYPE_4965) {
1676                         hdr_size = 28;
1677                         if (ucode_raw->size < hdr_size) {
1678                                 IWL_ERR(priv, "File size too small!\n");
1679                                 return -EINVAL;
1680                         }
1681                         pieces->build = le32_to_cpu(ucode->u.v2.build);
1682                         pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1683                         pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1684                         pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1685                         pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1686                         pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
1687                         src = ucode->u.v2.data;
1688                         break;
1689                 }
1690                 /* fall through for 4965 */
1691         case 0:
1692         case 1:
1693         case 2:
1694                 hdr_size = 24;
1695                 if (ucode_raw->size < hdr_size) {
1696                         IWL_ERR(priv, "File size too small!\n");
1697                         return -EINVAL;
1698                 }
1699                 pieces->build = 0;
1700                 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1701                 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1702                 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1703                 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1704                 pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
1705                 src = ucode->u.v1.data;
1706                 break;
1707         }
1708
1709         /* Verify size of file vs. image size info in file's header */
1710         if (ucode_raw->size != hdr_size + pieces->inst_size +
1711                                 pieces->data_size + pieces->init_size +
1712                                 pieces->init_data_size + pieces->boot_size) {
1713
1714                 IWL_ERR(priv,
1715                         "uCode file size %d does not match expected size\n",
1716                         (int)ucode_raw->size);
1717                 return -EINVAL;
1718         }
1719
1720         pieces->inst = src;
1721         src += pieces->inst_size;
1722         pieces->data = src;
1723         src += pieces->data_size;
1724         pieces->init = src;
1725         src += pieces->init_size;
1726         pieces->init_data = src;
1727         src += pieces->init_data_size;
1728         pieces->boot = src;
1729         src += pieces->boot_size;
1730
1731         return 0;
1732 }
1733
1734 static int iwlagn_wanted_ucode_alternative = 1;
1735
1736 static int iwlagn_load_firmware(struct iwl_priv *priv,
1737                                 const struct firmware *ucode_raw,
1738                                 struct iwlagn_firmware_pieces *pieces,
1739                                 struct iwlagn_ucode_capabilities *capa)
1740 {
1741         struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1742         struct iwl_ucode_tlv *tlv;
1743         size_t len = ucode_raw->size;
1744         const u8 *data;
1745         int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1746         u64 alternatives;
1747         u32 tlv_len;
1748         enum iwl_ucode_tlv_type tlv_type;
1749         const u8 *tlv_data;
1750
1751         if (len < sizeof(*ucode)) {
1752                 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
1753                 return -EINVAL;
1754         }
1755
1756         if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1757                 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1758                         le32_to_cpu(ucode->magic));
1759                 return -EINVAL;
1760         }
1761
1762         /*
1763          * Check which alternatives are present, and "downgrade"
1764          * when the chosen alternative is not present, warning
1765          * the user when that happens. Some files may not have
1766          * any alternatives, so don't warn in that case.
1767          */
1768         alternatives = le64_to_cpu(ucode->alternatives);
1769         tmp = wanted_alternative;
1770         if (wanted_alternative > 63)
1771                 wanted_alternative = 63;
1772         while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1773                 wanted_alternative--;
1774         if (wanted_alternative && wanted_alternative != tmp)
1775                 IWL_WARN(priv,
1776                          "uCode alternative %d not available, choosing %d\n",
1777                          tmp, wanted_alternative);
1778
1779         priv->ucode_ver = le32_to_cpu(ucode->ver);
1780         pieces->build = le32_to_cpu(ucode->build);
1781         data = ucode->data;
1782
1783         len -= sizeof(*ucode);
1784
1785         while (len >= sizeof(*tlv)) {
1786                 u16 tlv_alt;
1787
1788                 len -= sizeof(*tlv);
1789                 tlv = (void *)data;
1790
1791                 tlv_len = le32_to_cpu(tlv->length);
1792                 tlv_type = le16_to_cpu(tlv->type);
1793                 tlv_alt = le16_to_cpu(tlv->alternative);
1794                 tlv_data = tlv->data;
1795
1796                 if (len < tlv_len) {
1797                         IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1798                                 len, tlv_len);
1799                         return -EINVAL;
1800                 }
1801                 len -= ALIGN(tlv_len, 4);
1802                 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1803
1804                 /*
1805                  * Alternative 0 is always valid.
1806                  *
1807                  * Skip alternative TLVs that are not selected.
1808                  */
1809                 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1810                         continue;
1811
1812                 switch (tlv_type) {
1813                 case IWL_UCODE_TLV_INST:
1814                         pieces->inst = tlv_data;
1815                         pieces->inst_size = tlv_len;
1816                         break;
1817                 case IWL_UCODE_TLV_DATA:
1818                         pieces->data = tlv_data;
1819                         pieces->data_size = tlv_len;
1820                         break;
1821                 case IWL_UCODE_TLV_INIT:
1822                         pieces->init = tlv_data;
1823                         pieces->init_size = tlv_len;
1824                         break;
1825                 case IWL_UCODE_TLV_INIT_DATA:
1826                         pieces->init_data = tlv_data;
1827                         pieces->init_data_size = tlv_len;
1828                         break;
1829                 case IWL_UCODE_TLV_BOOT:
1830                         pieces->boot = tlv_data;
1831                         pieces->boot_size = tlv_len;
1832                         break;
1833                 case IWL_UCODE_TLV_PROBE_MAX_LEN:
1834                         if (tlv_len != sizeof(u32))
1835                                 goto invalid_tlv_len;
1836                         capa->max_probe_length =
1837                                         le32_to_cpup((__le32 *)tlv_data);
1838                         break;
1839                 case IWL_UCODE_TLV_PAN:
1840                         if (tlv_len)
1841                                 goto invalid_tlv_len;
1842                         capa->pan = true;
1843                         break;
1844                 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
1845                         if (tlv_len != sizeof(u32))
1846                                 goto invalid_tlv_len;
1847                         pieces->init_evtlog_ptr =
1848                                         le32_to_cpup((__le32 *)tlv_data);
1849                         break;
1850                 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
1851                         if (tlv_len != sizeof(u32))
1852                                 goto invalid_tlv_len;
1853                         pieces->init_evtlog_size =
1854                                         le32_to_cpup((__le32 *)tlv_data);
1855                         break;
1856                 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
1857                         if (tlv_len != sizeof(u32))
1858                                 goto invalid_tlv_len;
1859                         pieces->init_errlog_ptr =
1860                                         le32_to_cpup((__le32 *)tlv_data);
1861                         break;
1862                 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
1863                         if (tlv_len != sizeof(u32))
1864                                 goto invalid_tlv_len;
1865                         pieces->inst_evtlog_ptr =
1866                                         le32_to_cpup((__le32 *)tlv_data);
1867                         break;
1868                 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
1869                         if (tlv_len != sizeof(u32))
1870                                 goto invalid_tlv_len;
1871                         pieces->inst_evtlog_size =
1872                                         le32_to_cpup((__le32 *)tlv_data);
1873                         break;
1874                 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
1875                         if (tlv_len != sizeof(u32))
1876                                 goto invalid_tlv_len;
1877                         pieces->inst_errlog_ptr =
1878                                         le32_to_cpup((__le32 *)tlv_data);
1879                         break;
1880                 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
1881                         if (tlv_len)
1882                                 goto invalid_tlv_len;
1883                         priv->enhance_sensitivity_table = true;
1884                         break;
1885                 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
1886                         if (tlv_len != sizeof(u32))
1887                                 goto invalid_tlv_len;
1888                         capa->standard_phy_calibration_size =
1889                                         le32_to_cpup((__le32 *)tlv_data);
1890                         break;
1891                 default:
1892                         IWL_WARN(priv, "unknown TLV: %d\n", tlv_type);
1893                         break;
1894                 }
1895         }
1896
1897         if (len) {
1898                 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
1899                 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
1900                 return -EINVAL;
1901         }
1902
1903         return 0;
1904
1905  invalid_tlv_len:
1906         IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
1907         iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
1908
1909         return -EINVAL;
1910 }
1911
1912 /**
1913  * iwl_ucode_callback - callback when firmware was loaded
1914  *
1915  * If loaded successfully, copies the firmware into buffers
1916  * for the card to fetch (via DMA).
1917  */
1918 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
1919 {
1920         struct iwl_priv *priv = context;
1921         struct iwl_ucode_header *ucode;
1922         int err;
1923         struct iwlagn_firmware_pieces pieces;
1924         const unsigned int api_max = priv->cfg->ucode_api_max;
1925         const unsigned int api_min = priv->cfg->ucode_api_min;
1926         u32 api_ver;
1927         char buildstr[25];
1928         u32 build;
1929         struct iwlagn_ucode_capabilities ucode_capa = {
1930                 .max_probe_length = 200,
1931                 .standard_phy_calibration_size =
1932                         IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE,
1933         };
1934
1935         memset(&pieces, 0, sizeof(pieces));
1936
1937         if (!ucode_raw) {
1938                 if (priv->fw_index <= priv->cfg->ucode_api_max)
1939                         IWL_ERR(priv,
1940                                 "request for firmware file '%s' failed.\n",
1941                                 priv->firmware_name);
1942                 goto try_again;
1943         }
1944
1945         IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
1946                        priv->firmware_name, ucode_raw->size);
1947
1948         /* Make sure that we got at least the API version number */
1949         if (ucode_raw->size < 4) {
1950                 IWL_ERR(priv, "File size way too small!\n");
1951                 goto try_again;
1952         }
1953
1954         /* Data from ucode file:  header followed by uCode images */
1955         ucode = (struct iwl_ucode_header *)ucode_raw->data;
1956
1957         if (ucode->ver)
1958                 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
1959         else
1960                 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
1961                                            &ucode_capa);
1962
1963         if (err)
1964                 goto try_again;
1965
1966         api_ver = IWL_UCODE_API(priv->ucode_ver);
1967         build = pieces.build;
1968
1969         /*
1970          * api_ver should match the api version forming part of the
1971          * firmware filename ... but we don't check for that and only rely
1972          * on the API version read from firmware header from here on forward
1973          */
1974         /* no api version check required for experimental uCode */
1975         if (priv->fw_index != UCODE_EXPERIMENTAL_INDEX) {
1976                 if (api_ver < api_min || api_ver > api_max) {
1977                         IWL_ERR(priv,
1978                                 "Driver unable to support your firmware API. "
1979                                 "Driver supports v%u, firmware is v%u.\n",
1980                                 api_max, api_ver);
1981                         goto try_again;
1982                 }
1983
1984                 if (api_ver != api_max)
1985                         IWL_ERR(priv,
1986                                 "Firmware has old API version. Expected v%u, "
1987                                 "got v%u. New firmware can be obtained "
1988                                 "from http://www.intellinuxwireless.org.\n",
1989                                 api_max, api_ver);
1990         }
1991
1992         if (build)
1993                 sprintf(buildstr, " build %u%s", build,
1994                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1995                                 ? " (EXP)" : "");
1996         else
1997                 buildstr[0] = '\0';
1998
1999         IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
2000                  IWL_UCODE_MAJOR(priv->ucode_ver),
2001                  IWL_UCODE_MINOR(priv->ucode_ver),
2002                  IWL_UCODE_API(priv->ucode_ver),
2003                  IWL_UCODE_SERIAL(priv->ucode_ver),
2004                  buildstr);
2005
2006         snprintf(priv->hw->wiphy->fw_version,
2007                  sizeof(priv->hw->wiphy->fw_version),
2008                  "%u.%u.%u.%u%s",
2009                  IWL_UCODE_MAJOR(priv->ucode_ver),
2010                  IWL_UCODE_MINOR(priv->ucode_ver),
2011                  IWL_UCODE_API(priv->ucode_ver),
2012                  IWL_UCODE_SERIAL(priv->ucode_ver),
2013                  buildstr);
2014
2015         /*
2016          * For any of the failures below (before allocating pci memory)
2017          * we will try to load a version with a smaller API -- maybe the
2018          * user just got a corrupted version of the latest API.
2019          */
2020
2021         IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
2022                        priv->ucode_ver);
2023         IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
2024                        pieces.inst_size);
2025         IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
2026                        pieces.data_size);
2027         IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
2028                        pieces.init_size);
2029         IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
2030                        pieces.init_data_size);
2031         IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
2032                        pieces.boot_size);
2033
2034         /* Verify that uCode images will fit in card's SRAM */
2035         if (pieces.inst_size > priv->hw_params.max_inst_size) {
2036                 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
2037                         pieces.inst_size);
2038                 goto try_again;
2039         }
2040
2041         if (pieces.data_size > priv->hw_params.max_data_size) {
2042                 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
2043                         pieces.data_size);
2044                 goto try_again;
2045         }
2046
2047         if (pieces.init_size > priv->hw_params.max_inst_size) {
2048                 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
2049                         pieces.init_size);
2050                 goto try_again;
2051         }
2052
2053         if (pieces.init_data_size > priv->hw_params.max_data_size) {
2054                 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
2055                         pieces.init_data_size);
2056                 goto try_again;
2057         }
2058
2059         if (pieces.boot_size > priv->hw_params.max_bsm_size) {
2060                 IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
2061                         pieces.boot_size);
2062                 goto try_again;
2063         }
2064
2065         /* Allocate ucode buffers for card's bus-master loading ... */
2066
2067         /* Runtime instructions and 2 copies of data:
2068          * 1) unmodified from disk
2069          * 2) backup cache for save/restore during power-downs */
2070         priv->ucode_code.len = pieces.inst_size;
2071         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
2072
2073         priv->ucode_data.len = pieces.data_size;
2074         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
2075
2076         priv->ucode_data_backup.len = pieces.data_size;
2077         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
2078
2079         if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2080             !priv->ucode_data_backup.v_addr)
2081                 goto err_pci_alloc;
2082
2083         /* Initialization instructions and data */
2084         if (pieces.init_size && pieces.init_data_size) {
2085                 priv->ucode_init.len = pieces.init_size;
2086                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
2087
2088                 priv->ucode_init_data.len = pieces.init_data_size;
2089                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
2090
2091                 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2092                         goto err_pci_alloc;
2093         }
2094
2095         /* Bootstrap (instructions only, no data) */
2096         if (pieces.boot_size) {
2097                 priv->ucode_boot.len = pieces.boot_size;
2098                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
2099
2100                 if (!priv->ucode_boot.v_addr)
2101                         goto err_pci_alloc;
2102         }
2103
2104         /* Now that we can no longer fail, copy information */
2105
2106         /*
2107          * The (size - 16) / 12 formula is based on the information recorded
2108          * for each event, which is of mode 1 (including timestamp) for all
2109          * new microcodes that include this information.
2110          */
2111         priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
2112         if (pieces.init_evtlog_size)
2113                 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
2114         else
2115                 priv->_agn.init_evtlog_size =
2116                         priv->cfg->base_params->max_event_log_size;
2117         priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
2118         priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
2119         if (pieces.inst_evtlog_size)
2120                 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
2121         else
2122                 priv->_agn.inst_evtlog_size =
2123                         priv->cfg->base_params->max_event_log_size;
2124         priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
2125
2126         if (ucode_capa.pan) {
2127                 priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
2128                 priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
2129         } else
2130                 priv->sta_key_max_num = STA_KEY_MAX_NUM;
2131
2132         /* Copy images into buffers for card's bus-master reads ... */
2133
2134         /* Runtime instructions (first block of data in file) */
2135         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
2136                         pieces.inst_size);
2137         memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
2138
2139         IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
2140                 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2141
2142         /*
2143          * Runtime data
2144          * NOTE:  Copy into backup buffer will be done in iwl_up()
2145          */
2146         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
2147                         pieces.data_size);
2148         memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
2149         memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
2150
2151         /* Initialization instructions */
2152         if (pieces.init_size) {
2153                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
2154                                 pieces.init_size);
2155                 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
2156         }
2157
2158         /* Initialization data */
2159         if (pieces.init_data_size) {
2160                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
2161                                pieces.init_data_size);
2162                 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
2163                        pieces.init_data_size);
2164         }
2165
2166         /* Bootstrap instructions */
2167         IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
2168                         pieces.boot_size);
2169         memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
2170
2171         /*
2172          * figure out the offset of chain noise reset and gain commands
2173          * base on the size of standard phy calibration commands table size
2174          */
2175         if (ucode_capa.standard_phy_calibration_size >
2176             IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
2177                 ucode_capa.standard_phy_calibration_size =
2178                         IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
2179
2180         priv->_agn.phy_calib_chain_noise_reset_cmd =
2181                 ucode_capa.standard_phy_calibration_size;
2182         priv->_agn.phy_calib_chain_noise_gain_cmd =
2183                 ucode_capa.standard_phy_calibration_size + 1;
2184
2185         /**************************************************
2186          * This is still part of probe() in a sense...
2187          *
2188          * 9. Setup and register with mac80211 and debugfs
2189          **************************************************/
2190         err = iwl_mac_setup_register(priv, &ucode_capa);
2191         if (err)
2192                 goto out_unbind;
2193
2194         err = iwl_dbgfs_register(priv, DRV_NAME);
2195         if (err)
2196                 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
2197
2198         err = sysfs_create_group(&priv->pci_dev->dev.kobj,
2199                                         &iwl_attribute_group);
2200         if (err) {
2201                 IWL_ERR(priv, "failed to create sysfs device attributes\n");
2202                 goto out_unbind;
2203         }
2204
2205         /* We have our copies now, allow OS release its copies */
2206         release_firmware(ucode_raw);
2207         complete(&priv->_agn.firmware_loading_complete);
2208         return;
2209
2210  try_again:
2211         /* try next, if any */
2212         if (iwl_request_firmware(priv, false))
2213                 goto out_unbind;
2214         release_firmware(ucode_raw);
2215         return;
2216
2217  err_pci_alloc:
2218         IWL_ERR(priv, "failed to allocate pci memory\n");
2219         iwl_dealloc_ucode_pci(priv);
2220  out_unbind:
2221         complete(&priv->_agn.firmware_loading_complete);
2222         device_release_driver(&priv->pci_dev->dev);
2223         release_firmware(ucode_raw);
2224 }
2225
2226 static const char *desc_lookup_text[] = {
2227         "OK",
2228         "FAIL",
2229         "BAD_PARAM",
2230         "BAD_CHECKSUM",
2231         "NMI_INTERRUPT_WDG",
2232         "SYSASSERT",
2233         "FATAL_ERROR",
2234         "BAD_COMMAND",
2235         "HW_ERROR_TUNE_LOCK",
2236         "HW_ERROR_TEMPERATURE",
2237         "ILLEGAL_CHAN_FREQ",
2238         "VCC_NOT_STABLE",
2239         "FH_ERROR",
2240         "NMI_INTERRUPT_HOST",
2241         "NMI_INTERRUPT_ACTION_PT",
2242         "NMI_INTERRUPT_UNKNOWN",
2243         "UCODE_VERSION_MISMATCH",
2244         "HW_ERROR_ABS_LOCK",
2245         "HW_ERROR_CAL_LOCK_FAIL",
2246         "NMI_INTERRUPT_INST_ACTION_PT",
2247         "NMI_INTERRUPT_DATA_ACTION_PT",
2248         "NMI_TRM_HW_ER",
2249         "NMI_INTERRUPT_TRM",
2250         "NMI_INTERRUPT_BREAK_POINT"
2251         "DEBUG_0",
2252         "DEBUG_1",
2253         "DEBUG_2",
2254         "DEBUG_3",
2255 };
2256
2257 static struct { char *name; u8 num; } advanced_lookup[] = {
2258         { "NMI_INTERRUPT_WDG", 0x34 },
2259         { "SYSASSERT", 0x35 },
2260         { "UCODE_VERSION_MISMATCH", 0x37 },
2261         { "BAD_COMMAND", 0x38 },
2262         { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
2263         { "FATAL_ERROR", 0x3D },
2264         { "NMI_TRM_HW_ERR", 0x46 },
2265         { "NMI_INTERRUPT_TRM", 0x4C },
2266         { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
2267         { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
2268         { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
2269         { "NMI_INTERRUPT_HOST", 0x66 },
2270         { "NMI_INTERRUPT_ACTION_PT", 0x7C },
2271         { "NMI_INTERRUPT_UNKNOWN", 0x84 },
2272         { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
2273         { "ADVANCED_SYSASSERT", 0 },
2274 };
2275
2276 static const char *desc_lookup(u32 num)
2277 {
2278         int i;
2279         int max = ARRAY_SIZE(desc_lookup_text);
2280
2281         if (num < max)
2282                 return desc_lookup_text[num];
2283
2284         max = ARRAY_SIZE(advanced_lookup) - 1;
2285         for (i = 0; i < max; i++) {
2286                 if (advanced_lookup[i].num == num)
2287                         break;;
2288         }
2289         return advanced_lookup[i].name;
2290 }
2291
2292 #define ERROR_START_OFFSET  (1 * sizeof(u32))
2293 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
2294
2295 void iwl_dump_nic_error_log(struct iwl_priv *priv)
2296 {
2297         u32 data2, line;
2298         u32 desc, time, count, base, data1;
2299         u32 blink1, blink2, ilink1, ilink2;
2300         u32 pc, hcmd;
2301
2302         if (priv->ucode_type == UCODE_INIT) {
2303                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
2304                 if (!base)
2305                         base = priv->_agn.init_errlog_ptr;
2306         } else {
2307                 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
2308                 if (!base)
2309                         base = priv->_agn.inst_errlog_ptr;
2310         }
2311
2312         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2313                 IWL_ERR(priv,
2314                         "Not valid error log pointer 0x%08X for %s uCode\n",
2315                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2316                 return;
2317         }
2318
2319         count = iwl_read_targ_mem(priv, base);
2320
2321         if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
2322                 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
2323                 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
2324                         priv->status, count);
2325         }
2326
2327         desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
2328         priv->isr_stats.err_code = desc;
2329         pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
2330         blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
2331         blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
2332         ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
2333         ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
2334         data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
2335         data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
2336         line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
2337         time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
2338         hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
2339
2340         trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
2341                                       blink1, blink2, ilink1, ilink2);
2342
2343         IWL_ERR(priv, "Desc                                  Time       "
2344                 "data1      data2      line\n");
2345         IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
2346                 desc_lookup(desc), desc, time, data1, data2, line);
2347         IWL_ERR(priv, "pc      blink1  blink2  ilink1  ilink2  hcmd\n");
2348         IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
2349                 pc, blink1, blink2, ilink1, ilink2, hcmd);
2350 }
2351
2352 #define EVENT_START_OFFSET  (4 * sizeof(u32))
2353
2354 /**
2355  * iwl_print_event_log - Dump error event log to syslog
2356  *
2357  */
2358 static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
2359                                u32 num_events, u32 mode,
2360                                int pos, char **buf, size_t bufsz)
2361 {
2362         u32 i;
2363         u32 base;       /* SRAM byte address of event log header */
2364         u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
2365         u32 ptr;        /* SRAM byte address of log data */
2366         u32 ev, time, data; /* event log data */
2367         unsigned long reg_flags;
2368
2369         if (num_events == 0)
2370                 return pos;
2371
2372         if (priv->ucode_type == UCODE_INIT) {
2373                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2374                 if (!base)
2375                         base = priv->_agn.init_evtlog_ptr;
2376         } else {
2377                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2378                 if (!base)
2379                         base = priv->_agn.inst_evtlog_ptr;
2380         }
2381
2382         if (mode == 0)
2383                 event_size = 2 * sizeof(u32);
2384         else
2385                 event_size = 3 * sizeof(u32);
2386
2387         ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
2388
2389         /* Make sure device is powered up for SRAM reads */
2390         spin_lock_irqsave(&priv->reg_lock, reg_flags);
2391         iwl_grab_nic_access(priv);
2392
2393         /* Set starting address; reads will auto-increment */
2394         _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
2395         rmb();
2396
2397         /* "time" is actually "data" for mode 0 (no timestamp).
2398         * place event id # at far right for easier visual parsing. */
2399         for (i = 0; i < num_events; i++) {
2400                 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2401                 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2402                 if (mode == 0) {
2403                         /* data, ev */
2404                         if (bufsz) {
2405                                 pos += scnprintf(*buf + pos, bufsz - pos,
2406                                                 "EVT_LOG:0x%08x:%04u\n",
2407                                                 time, ev);
2408                         } else {
2409                                 trace_iwlwifi_dev_ucode_event(priv, 0,
2410                                         time, ev);
2411                                 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
2412                                         time, ev);
2413                         }
2414                 } else {
2415                         data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2416                         if (bufsz) {
2417                                 pos += scnprintf(*buf + pos, bufsz - pos,
2418                                                 "EVT_LOGT:%010u:0x%08x:%04u\n",
2419                                                  time, data, ev);
2420                         } else {
2421                                 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
2422                                         time, data, ev);
2423                                 trace_iwlwifi_dev_ucode_event(priv, time,
2424                                         data, ev);
2425                         }
2426                 }
2427         }
2428
2429         /* Allow device to power down */
2430         iwl_release_nic_access(priv);
2431         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
2432         return pos;
2433 }
2434
2435 /**
2436  * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2437  */
2438 static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2439                                     u32 num_wraps, u32 next_entry,
2440                                     u32 size, u32 mode,
2441                                     int pos, char **buf, size_t bufsz)
2442 {
2443         /*
2444          * display the newest DEFAULT_LOG_ENTRIES entries
2445          * i.e the entries just before the next ont that uCode would fill.
2446          */
2447         if (num_wraps) {
2448                 if (next_entry < size) {
2449                         pos = iwl_print_event_log(priv,
2450                                                 capacity - (size - next_entry),
2451                                                 size - next_entry, mode,
2452                                                 pos, buf, bufsz);
2453                         pos = iwl_print_event_log(priv, 0,
2454                                                   next_entry, mode,
2455                                                   pos, buf, bufsz);
2456                 } else
2457                         pos = iwl_print_event_log(priv, next_entry - size,
2458                                                   size, mode, pos, buf, bufsz);
2459         } else {
2460                 if (next_entry < size) {
2461                         pos = iwl_print_event_log(priv, 0, next_entry,
2462                                                   mode, pos, buf, bufsz);
2463                 } else {
2464                         pos = iwl_print_event_log(priv, next_entry - size,
2465                                                   size, mode, pos, buf, bufsz);
2466                 }
2467         }
2468         return pos;
2469 }
2470
2471 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2472
2473 int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2474                             char **buf, bool display)
2475 {
2476         u32 base;       /* SRAM byte address of event log header */
2477         u32 capacity;   /* event log capacity in # entries */
2478         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
2479         u32 num_wraps;  /* # times uCode wrapped to top of log */
2480         u32 next_entry; /* index of next entry to be written by uCode */
2481         u32 size;       /* # entries that we'll print */
2482         u32 logsize;
2483         int pos = 0;
2484         size_t bufsz = 0;
2485
2486         if (priv->ucode_type == UCODE_INIT) {
2487                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2488                 logsize = priv->_agn.init_evtlog_size;
2489                 if (!base)
2490                         base = priv->_agn.init_evtlog_ptr;
2491         } else {
2492                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2493                 logsize = priv->_agn.inst_evtlog_size;
2494                 if (!base)
2495                         base = priv->_agn.inst_evtlog_ptr;
2496         }
2497
2498         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2499                 IWL_ERR(priv,
2500                         "Invalid event log pointer 0x%08X for %s uCode\n",
2501                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2502                 return -EINVAL;
2503         }
2504
2505         /* event log header */
2506         capacity = iwl_read_targ_mem(priv, base);
2507         mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2508         num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2509         next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2510
2511         if (capacity > logsize) {
2512                 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
2513                         capacity, logsize);
2514                 capacity = logsize;
2515         }
2516
2517         if (next_entry > logsize) {
2518                 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
2519                         next_entry, logsize);
2520                 next_entry = logsize;
2521         }
2522
2523         size = num_wraps ? capacity : next_entry;
2524
2525         /* bail out if nothing in log */
2526         if (size == 0) {
2527                 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
2528                 return pos;
2529         }
2530
2531         /* enable/disable bt channel inhibition */
2532         priv->bt_ch_announce = iwlagn_bt_ch_announce;
2533
2534 #ifdef CONFIG_IWLWIFI_DEBUG
2535         if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
2536                 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2537                         ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2538 #else
2539         size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2540                 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2541 #endif
2542         IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2543                 size);
2544
2545 #ifdef CONFIG_IWLWIFI_DEBUG
2546         if (display) {
2547                 if (full_log)
2548                         bufsz = capacity * 48;
2549                 else
2550                         bufsz = size * 48;
2551                 *buf = kmalloc(bufsz, GFP_KERNEL);
2552                 if (!*buf)
2553                         return -ENOMEM;
2554         }
2555         if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2556                 /*
2557                  * if uCode has wrapped back to top of log,
2558                  * start at the oldest entry,
2559                  * i.e the next one that uCode would fill.
2560                  */
2561                 if (num_wraps)
2562                         pos = iwl_print_event_log(priv, next_entry,
2563                                                 capacity - next_entry, mode,
2564                                                 pos, buf, bufsz);
2565                 /* (then/else) start at top of log */
2566                 pos = iwl_print_event_log(priv, 0,
2567                                           next_entry, mode, pos, buf, bufsz);
2568         } else
2569                 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2570                                                 next_entry, size, mode,
2571                                                 pos, buf, bufsz);
2572 #else
2573         pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2574                                         next_entry, size, mode,
2575                                         pos, buf, bufsz);
2576 #endif
2577         return pos;
2578 }
2579
2580 static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2581 {
2582         struct iwl_ct_kill_config cmd;
2583         struct iwl_ct_kill_throttling_config adv_cmd;
2584         unsigned long flags;
2585         int ret = 0;
2586
2587         spin_lock_irqsave(&priv->lock, flags);
2588         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2589                     CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2590         spin_unlock_irqrestore(&priv->lock, flags);
2591         priv->thermal_throttle.ct_kill_toggle = false;
2592
2593         if (priv->cfg->base_params->support_ct_kill_exit) {
2594                 adv_cmd.critical_temperature_enter =
2595                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2596                 adv_cmd.critical_temperature_exit =
2597                         cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2598
2599                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2600                                        sizeof(adv_cmd), &adv_cmd);
2601                 if (ret)
2602                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2603                 else
2604                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2605                                         "succeeded, "
2606                                         "critical temperature enter is %d,"
2607                                         "exit is %d\n",
2608                                        priv->hw_params.ct_kill_threshold,
2609                                        priv->hw_params.ct_kill_exit_threshold);
2610         } else {
2611                 cmd.critical_temperature_R =
2612                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2613
2614                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2615                                        sizeof(cmd), &cmd);
2616                 if (ret)
2617                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2618                 else
2619                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2620                                         "succeeded, "
2621                                         "critical temperature is %d\n",
2622                                         priv->hw_params.ct_kill_threshold);
2623         }
2624 }
2625
2626 static int iwlagn_send_calib_cfg_rt(struct iwl_priv *priv, u32 cfg)
2627 {
2628         struct iwl_calib_cfg_cmd calib_cfg_cmd;
2629         struct iwl_host_cmd cmd = {
2630                 .id = CALIBRATION_CFG_CMD,
2631                 .len = sizeof(struct iwl_calib_cfg_cmd),
2632                 .data = &calib_cfg_cmd,
2633         };
2634
2635         memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
2636         calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
2637         calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg);
2638
2639         return iwl_send_cmd(priv, &cmd);
2640 }
2641
2642
2643 /**
2644  * iwl_alive_start - called after REPLY_ALIVE notification received
2645  *                   from protocol/runtime uCode (initialization uCode's
2646  *                   Alive gets handled by iwl_init_alive_start()).
2647  */
2648 static void iwl_alive_start(struct iwl_priv *priv)
2649 {
2650         int ret = 0;
2651         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2652
2653         IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
2654
2655         /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2656          * This is a paranoid check, because we would not have gotten the
2657          * "runtime" alive if code weren't properly loaded.  */
2658         if (iwl_verify_ucode(priv)) {
2659                 /* Runtime instruction load was bad;
2660                  * take it all the way back down so we can try again */
2661                 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
2662                 goto restart;
2663         }
2664
2665         ret = priv->cfg->ops->lib->alive_notify(priv);
2666         if (ret) {
2667                 IWL_WARN(priv,
2668                         "Could not complete ALIVE transition [ntf]: %d\n", ret);
2669                 goto restart;
2670         }
2671
2672
2673         /* After the ALIVE response, we can send host commands to the uCode */
2674         set_bit(STATUS_ALIVE, &priv->status);
2675
2676         /* Enable watchdog to monitor the driver tx queues */
2677         iwl_setup_watchdog(priv);
2678
2679         if (iwl_is_rfkill(priv))
2680                 return;
2681
2682         /* download priority table before any calibration request */
2683         if (priv->cfg->bt_params &&
2684             priv->cfg->bt_params->advanced_bt_coexist) {
2685                 /* Configure Bluetooth device coexistence support */
2686                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
2687                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
2688                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
2689                 priv->cfg->ops->hcmd->send_bt_config(priv);
2690                 priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS;
2691                 iwlagn_send_prio_tbl(priv);
2692
2693                 /* FIXME: w/a to force change uCode BT state machine */
2694                 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
2695                         BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2696                 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE,
2697                         BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2698         }
2699         if (priv->hw_params.calib_rt_cfg)
2700                 iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg);
2701
2702         ieee80211_wake_queues(priv->hw);
2703
2704         priv->active_rate = IWL_RATES_MASK;
2705
2706         /* Configure Tx antenna selection based on H/W config */
2707         if (priv->cfg->ops->hcmd->set_tx_ant)
2708                 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2709
2710         if (iwl_is_associated_ctx(ctx)) {
2711                 struct iwl_rxon_cmd *active_rxon =
2712                                 (struct iwl_rxon_cmd *)&ctx->active;
2713                 /* apply any changes in staging */
2714                 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2715                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2716         } else {
2717                 struct iwl_rxon_context *tmp;
2718                 /* Initialize our rx_config data */
2719                 for_each_context(priv, tmp)
2720                         iwl_connection_init_rx_config(priv, tmp);
2721
2722                 if (priv->cfg->ops->hcmd->set_rxon_chain)
2723                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
2724         }
2725
2726         if (priv->cfg->bt_params &&
2727             !priv->cfg->bt_params->advanced_bt_coexist) {
2728                 /* Configure Bluetooth device coexistence support */
2729                 priv->cfg->ops->hcmd->send_bt_config(priv);
2730         }
2731
2732         iwl_reset_run_time_calib(priv);
2733
2734         set_bit(STATUS_READY, &priv->status);
2735
2736         /* Configure the adapter for unassociated operation */
2737         iwlcore_commit_rxon(priv, ctx);
2738
2739         /* At this point, the NIC is initialized and operational */
2740         iwl_rf_kill_ct_config(priv);
2741
2742         IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
2743         wake_up_interruptible(&priv->wait_command_queue);
2744
2745         iwl_power_update_mode(priv, true);
2746         IWL_DEBUG_INFO(priv, "Updated power mode\n");
2747
2748
2749         return;
2750
2751  restart:
2752         queue_work(priv->workqueue, &priv->restart);
2753 }
2754
2755 static void iwl_cancel_deferred_work(struct iwl_priv *priv);
2756
2757 static void __iwl_down(struct iwl_priv *priv)
2758 {
2759         unsigned long flags;
2760         int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
2761
2762         IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
2763
2764         iwl_scan_cancel_timeout(priv, 200);
2765
2766         exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
2767
2768         /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2769          * to prevent rearm timer */
2770         del_timer_sync(&priv->watchdog);
2771
2772         iwl_clear_ucode_stations(priv, NULL);
2773         iwl_dealloc_bcast_stations(priv);
2774         iwl_clear_driver_stations(priv);
2775
2776         /* reset BT coex data */
2777         priv->bt_status = 0;
2778         if (priv->cfg->bt_params)
2779                 priv->bt_traffic_load =
2780                          priv->cfg->bt_params->bt_init_traffic_load;
2781         else
2782                 priv->bt_traffic_load = 0;
2783         priv->bt_full_concurrent = false;
2784         priv->bt_ci_compliance = 0;
2785
2786         /* Unblock any waiting calls */
2787         wake_up_interruptible_all(&priv->wait_command_queue);
2788
2789         /* Wipe out the EXIT_PENDING status bit if we are not actually
2790          * exiting the module */
2791         if (!exit_pending)
2792                 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2793
2794         /* stop and reset the on-board processor */
2795         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2796
2797         /* tell the device to stop sending interrupts */
2798         spin_lock_irqsave(&priv->lock, flags);
2799         iwl_disable_interrupts(priv);
2800         spin_unlock_irqrestore(&priv->lock, flags);
2801         iwl_synchronize_irq(priv);
2802
2803         if (priv->mac80211_registered)
2804                 ieee80211_stop_queues(priv->hw);
2805
2806         /* If we have not previously called iwl_init() then
2807          * clear all bits but the RF Kill bit and return */
2808         if (!iwl_is_init(priv)) {
2809                 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2810                                         STATUS_RF_KILL_HW |
2811                                test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2812                                         STATUS_GEO_CONFIGURED |
2813                                test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2814                                         STATUS_EXIT_PENDING;
2815                 goto exit;
2816         }
2817
2818         /* ...otherwise clear out all the status bits but the RF Kill
2819          * bit and continue taking the NIC down. */
2820         priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2821                                 STATUS_RF_KILL_HW |
2822                         test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2823                                 STATUS_GEO_CONFIGURED |
2824                         test_bit(STATUS_FW_ERROR, &priv->status) <<
2825                                 STATUS_FW_ERROR |
2826                        test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2827                                 STATUS_EXIT_PENDING;
2828
2829         /* device going down, Stop using ICT table */
2830         if (priv->cfg->ops->lib->isr_ops.disable)
2831                 priv->cfg->ops->lib->isr_ops.disable(priv);
2832
2833         iwlagn_txq_ctx_stop(priv);
2834         iwlagn_rxq_stop(priv);
2835
2836         /* Power-down device's busmaster DMA clocks */
2837         iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2838         udelay(5);
2839
2840         /* Make sure (redundant) we've released our request to stay awake */
2841         iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2842
2843         /* Stop the device, and put it in low power state */
2844         iwl_apm_stop(priv);
2845
2846  exit:
2847         memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
2848
2849         dev_kfree_skb(priv->beacon_skb);
2850         priv->beacon_skb = NULL;
2851
2852         /* clear out any free frames */
2853         iwl_clear_free_frames(priv);
2854 }
2855
2856 static void iwl_down(struct iwl_priv *priv)
2857 {
2858         mutex_lock(&priv->mutex);
2859         __iwl_down(priv);
2860         mutex_unlock(&priv->mutex);
2861
2862         iwl_cancel_deferred_work(priv);
2863 }
2864
2865 #define HW_READY_TIMEOUT (50)
2866
2867 static int iwl_set_hw_ready(struct iwl_priv *priv)
2868 {
2869         int ret = 0;
2870
2871         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2872                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2873
2874         /* See if we got it */
2875         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2876                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2877                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2878                                 HW_READY_TIMEOUT);
2879         if (ret != -ETIMEDOUT)
2880                 priv->hw_ready = true;
2881         else
2882                 priv->hw_ready = false;
2883
2884         IWL_DEBUG_INFO(priv, "hardware %s\n",
2885                       (priv->hw_ready == 1) ? "ready" : "not ready");
2886         return ret;
2887 }
2888
2889 static int iwl_prepare_card_hw(struct iwl_priv *priv)
2890 {
2891         int ret = 0;
2892
2893         IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
2894
2895         ret = iwl_set_hw_ready(priv);
2896         if (priv->hw_ready)
2897                 return ret;
2898
2899         /* If HW is not ready, prepare the conditions to check again */
2900         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2901                         CSR_HW_IF_CONFIG_REG_PREPARE);
2902
2903         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2904                         ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2905                         CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2906
2907         /* HW should be ready by now, check again. */
2908         if (ret != -ETIMEDOUT)
2909                 iwl_set_hw_ready(priv);
2910
2911         return ret;
2912 }
2913
2914 #define MAX_HW_RESTARTS 5
2915
2916 static int __iwl_up(struct iwl_priv *priv)
2917 {
2918         struct iwl_rxon_context *ctx;
2919         int i;
2920         int ret;
2921
2922         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2923                 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
2924                 return -EIO;
2925         }
2926
2927         if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
2928                 IWL_ERR(priv, "ucode not available for device bringup\n");
2929                 return -EIO;
2930         }
2931
2932         for_each_context(priv, ctx) {
2933                 ret = iwlagn_alloc_bcast_station(priv, ctx);
2934                 if (ret) {
2935                         iwl_dealloc_bcast_stations(priv);
2936                         return ret;
2937                 }
2938         }
2939
2940         iwl_prepare_card_hw(priv);
2941
2942         if (!priv->hw_ready) {
2943                 IWL_WARN(priv, "Exit HW not ready\n");
2944                 return -EIO;
2945         }
2946
2947         /* If platform's RF_KILL switch is NOT set to KILL */
2948         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2949                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2950         else
2951                 set_bit(STATUS_RF_KILL_HW, &priv->status);
2952
2953         if (iwl_is_rfkill(priv)) {
2954                 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2955
2956                 iwl_enable_interrupts(priv);
2957                 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
2958                 return 0;
2959         }
2960
2961         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2962
2963         /* must be initialised before iwl_hw_nic_init */
2964         if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
2965                 priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
2966         else
2967                 priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
2968
2969         ret = iwlagn_hw_nic_init(priv);
2970         if (ret) {
2971                 IWL_ERR(priv, "Unable to init nic\n");
2972                 return ret;
2973         }
2974
2975         /* make sure rfkill handshake bits are cleared */
2976         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2977         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2978                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2979
2980         /* clear (again), then enable host interrupts */
2981         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2982         iwl_enable_interrupts(priv);
2983
2984         /* really make sure rfkill handshake bits are cleared */
2985         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2986         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2987
2988         /* Copy original ucode data image from disk into backup cache.
2989          * This will be used to initialize the on-board processor's
2990          * data SRAM for a clean start when the runtime program first loads. */
2991         memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
2992                priv->ucode_data.len);
2993
2994         for (i = 0; i < MAX_HW_RESTARTS; i++) {
2995
2996                 /* load bootstrap state machine,
2997                  * load bootstrap program into processor's memory,
2998                  * prepare to load the "initialize" uCode */
2999                 ret = priv->cfg->ops->lib->load_ucode(priv);
3000
3001                 if (ret) {
3002                         IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
3003                                 ret);
3004                         continue;
3005                 }
3006
3007                 /* start card; "initialize" will load runtime ucode */
3008                 iwl_nic_start(priv);
3009
3010                 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
3011
3012                 return 0;
3013         }
3014
3015         set_bit(STATUS_EXIT_PENDING, &priv->status);
3016         __iwl_down(priv);
3017         clear_bit(STATUS_EXIT_PENDING, &priv->status);
3018
3019         /* tried to restart and config the device for as long as our
3020          * patience could withstand */
3021         IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
3022         return -EIO;
3023 }
3024
3025
3026 /*****************************************************************************
3027  *
3028  * Workqueue callbacks
3029  *
3030  *****************************************************************************/
3031
3032 static void iwl_bg_init_alive_start(struct work_struct *data)
3033 {
3034         struct iwl_priv *priv =
3035             container_of(data, struct iwl_priv, init_alive_start.work);
3036
3037         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3038                 return;
3039
3040         mutex_lock(&priv->mutex);
3041         priv->cfg->ops->lib->init_alive_start(priv);
3042         mutex_unlock(&priv->mutex);
3043 }
3044
3045 static void iwl_bg_alive_start(struct work_struct *data)
3046 {
3047         struct iwl_priv *priv =
3048             container_of(data, struct iwl_priv, alive_start.work);
3049
3050         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3051                 return;
3052
3053         /* enable dram interrupt */
3054         if (priv->cfg->ops->lib->isr_ops.reset)
3055                 priv->cfg->ops->lib->isr_ops.reset(priv);
3056
3057         mutex_lock(&priv->mutex);
3058         iwl_alive_start(priv);
3059         mutex_unlock(&priv->mutex);
3060 }
3061
3062 static void iwl_bg_run_time_calib_work(struct work_struct *work)
3063 {
3064         struct iwl_priv *priv = container_of(work, struct iwl_priv,
3065                         run_time_calib_work);
3066
3067         mutex_lock(&priv->mutex);
3068
3069         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3070             test_bit(STATUS_SCANNING, &priv->status)) {
3071                 mutex_unlock(&priv->mutex);
3072                 return;
3073         }
3074
3075         if (priv->start_calib) {
3076                 if (iwl_bt_statistics(priv)) {
3077                         iwl_chain_noise_calibration(priv,
3078                                         (void *)&priv->_agn.statistics_bt);
3079                         iwl_sensitivity_calibration(priv,
3080                                         (void *)&priv->_agn.statistics_bt);
3081                 } else {
3082                         iwl_chain_noise_calibration(priv,
3083                                         (void *)&priv->_agn.statistics);
3084                         iwl_sensitivity_calibration(priv,
3085                                         (void *)&priv->_agn.statistics);
3086                 }
3087         }
3088
3089         mutex_unlock(&priv->mutex);
3090 }
3091
3092 static void iwl_bg_restart(struct work_struct *data)
3093 {
3094         struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
3095
3096         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3097                 return;
3098
3099         if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
3100                 struct iwl_rxon_context *ctx;
3101                 bool bt_full_concurrent;
3102                 u8 bt_ci_compliance;
3103                 u8 bt_load;
3104                 u8 bt_status;
3105
3106                 mutex_lock(&priv->mutex);
3107                 for_each_context(priv, ctx)
3108                         ctx->vif = NULL;
3109                 priv->is_open = 0;
3110
3111                 /*
3112                  * __iwl_down() will clear the BT status variables,
3113                  * which is correct, but when we restart we really
3114                  * want to keep them so restore them afterwards.
3115                  *
3116                  * The restart process will later pick them up and
3117                  * re-configure the hw when we reconfigure the BT
3118                  * command.
3119                  */
3120                 bt_full_concurrent = priv->bt_full_concurrent;
3121                 bt_ci_compliance = priv->bt_ci_compliance;
3122                 bt_load = priv->bt_traffic_load;
3123                 bt_status = priv->bt_status;
3124
3125                 __iwl_down(priv);
3126
3127                 priv->bt_full_concurrent = bt_full_concurrent;
3128                 priv->bt_ci_compliance = bt_ci_compliance;
3129                 priv->bt_traffic_load = bt_load;
3130                 priv->bt_status = bt_status;
3131
3132                 mutex_unlock(&priv->mutex);
3133                 iwl_cancel_deferred_work(priv);
3134                 ieee80211_restart_hw(priv->hw);
3135         } else {
3136                 iwl_down(priv);
3137
3138                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3139                         return;
3140
3141                 mutex_lock(&priv->mutex);
3142                 __iwl_up(priv);
3143                 mutex_unlock(&priv->mutex);
3144         }
3145 }
3146
3147 static void iwl_bg_rx_replenish(struct work_struct *data)
3148 {
3149         struct iwl_priv *priv =
3150             container_of(data, struct iwl_priv, rx_replenish);
3151
3152         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3153                 return;
3154
3155         mutex_lock(&priv->mutex);
3156         iwlagn_rx_replenish(priv);
3157         mutex_unlock(&priv->mutex);
3158 }
3159
3160 /*****************************************************************************
3161  *
3162  * mac80211 entry point functions
3163  *
3164  *****************************************************************************/
3165
3166 #define UCODE_READY_TIMEOUT     (4 * HZ)
3167
3168 /*
3169  * Not a mac80211 entry point function, but it fits in with all the
3170  * other mac80211 functions grouped here.
3171  */
3172 static int iwl_mac_setup_register(struct iwl_priv *priv,
3173                                   struct iwlagn_ucode_capabilities *capa)
3174 {
3175         int ret;
3176         struct ieee80211_hw *hw = priv->hw;
3177         struct iwl_rxon_context *ctx;
3178
3179         hw->rate_control_algorithm = "iwl-agn-rs";
3180
3181         /* Tell mac80211 our characteristics */
3182         hw->flags = IEEE80211_HW_SIGNAL_DBM |
3183                     IEEE80211_HW_AMPDU_AGGREGATION |
3184                     IEEE80211_HW_NEED_DTIM_PERIOD |
3185                     IEEE80211_HW_SPECTRUM_MGMT |
3186                     IEEE80211_HW_REPORTS_TX_ACK_STATUS;
3187
3188         hw->max_tx_aggregation_subframes = LINK_QUAL_AGG_FRAME_LIMIT_DEF;
3189
3190         if (!priv->cfg->base_params->broken_powersave)
3191                 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
3192                              IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
3193
3194         if (priv->cfg->sku & IWL_SKU_N)
3195                 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
3196                              IEEE80211_HW_SUPPORTS_STATIC_SMPS;
3197
3198         hw->sta_data_size = sizeof(struct iwl_station_priv);
3199         hw->vif_data_size = sizeof(struct iwl_vif_priv);
3200
3201         for_each_context(priv, ctx) {
3202                 hw->wiphy->interface_modes |= ctx->interface_modes;
3203                 hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
3204         }
3205
3206         hw->wiphy->max_remain_on_channel_duration = 1000;
3207
3208         hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
3209                             WIPHY_FLAG_DISABLE_BEACON_HINTS |
3210                             WIPHY_FLAG_IBSS_RSN;
3211
3212         /*
3213          * For now, disable PS by default because it affects
3214          * RX performance significantly.
3215          */
3216         hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3217
3218         hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
3219         /* we create the 802.11 header and a zero-length SSID element */
3220         hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
3221
3222         /* Default value; 4 EDCA QOS priorities */
3223         hw->queues = 4;
3224
3225         hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
3226
3227         if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3228                 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3229                         &priv->bands[IEEE80211_BAND_2GHZ];
3230         if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3231                 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3232                         &priv->bands[IEEE80211_BAND_5GHZ];
3233
3234         iwl_leds_init(priv);
3235
3236         ret = ieee80211_register_hw(priv->hw);
3237         if (ret) {
3238                 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3239                 return ret;
3240         }
3241         priv->mac80211_registered = 1;
3242
3243         return 0;
3244 }
3245
3246
3247 int iwlagn_mac_start(struct ieee80211_hw *hw)
3248 {
3249         struct iwl_priv *priv = hw->priv;
3250         int ret;
3251
3252         IWL_DEBUG_MAC80211(priv, "enter\n");
3253
3254         /* we should be verifying the device is ready to be opened */
3255         mutex_lock(&priv->mutex);
3256         ret = __iwl_up(priv);
3257         mutex_unlock(&priv->mutex);
3258
3259         if (ret)
3260                 return ret;
3261
3262         if (iwl_is_rfkill(priv))
3263                 goto out;
3264
3265         IWL_DEBUG_INFO(priv, "Start UP work done.\n");
3266
3267         /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
3268          * mac80211 will not be run successfully. */
3269         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3270                         test_bit(STATUS_READY, &priv->status),
3271                         UCODE_READY_TIMEOUT);
3272         if (!ret) {
3273                 if (!test_bit(STATUS_READY, &priv->status)) {
3274                         IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
3275                                 jiffies_to_msecs(UCODE_READY_TIMEOUT));
3276                         return -ETIMEDOUT;
3277                 }
3278         }
3279
3280         iwlagn_led_enable(priv);
3281
3282 out:
3283         priv->is_open = 1;
3284         IWL_DEBUG_MAC80211(priv, "leave\n");
3285         return 0;
3286 }
3287
3288 void iwlagn_mac_stop(struct ieee80211_hw *hw)
3289 {
3290         struct iwl_priv *priv = hw->priv;
3291
3292         IWL_DEBUG_MAC80211(priv, "enter\n");
3293
3294         if (!priv->is_open)
3295                 return;
3296
3297         priv->is_open = 0;
3298
3299         iwl_down(priv);
3300
3301         flush_workqueue(priv->workqueue);
3302
3303         /* User space software may expect getting rfkill changes
3304          * even if interface is down */
3305         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3306         iwl_enable_rfkill_int(priv);
3307
3308         IWL_DEBUG_MAC80211(priv, "leave\n");
3309 }
3310
3311 int iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
3312 {
3313         struct iwl_priv *priv = hw->priv;
3314
3315         IWL_DEBUG_MACDUMP(priv, "enter\n");
3316
3317         IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
3318                      ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
3319
3320         if (iwlagn_tx_skb(priv, skb))
3321                 dev_kfree_skb_any(skb);
3322
3323         IWL_DEBUG_MACDUMP(priv, "leave\n");
3324         return NETDEV_TX_OK;
3325 }
3326
3327 void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw,
3328                                 struct ieee80211_vif *vif,
3329                                 struct ieee80211_key_conf *keyconf,
3330                                 struct ieee80211_sta *sta,
3331                                 u32 iv32, u16 *phase1key)
3332 {
3333         struct iwl_priv *priv = hw->priv;
3334         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3335
3336         IWL_DEBUG_MAC80211(priv, "enter\n");
3337
3338         iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
3339                             iv32, phase1key);
3340
3341         IWL_DEBUG_MAC80211(priv, "leave\n");
3342 }
3343
3344 int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3345                        struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3346                        struct ieee80211_key_conf *key)
3347 {
3348         struct iwl_priv *priv = hw->priv;
3349         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3350         struct iwl_rxon_context *ctx = vif_priv->ctx;
3351         int ret;
3352         u8 sta_id;
3353         bool is_default_wep_key = false;
3354
3355         IWL_DEBUG_MAC80211(priv, "enter\n");
3356
3357         if (priv->cfg->mod_params->sw_crypto) {
3358                 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
3359                 return -EOPNOTSUPP;
3360         }
3361
3362         /*
3363          * To support IBSS RSN, don't program group keys in IBSS, the
3364          * hardware will then not attempt to decrypt the frames.
3365          */
3366         if (vif->type == NL80211_IFTYPE_ADHOC &&
3367             !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
3368                 return -EOPNOTSUPP;
3369
3370         sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
3371         if (sta_id == IWL_INVALID_STATION)
3372                 return -EINVAL;
3373
3374         mutex_lock(&priv->mutex);
3375         iwl_scan_cancel_timeout(priv, 100);
3376
3377         /*
3378          * If we are getting WEP group key and we didn't receive any key mapping
3379          * so far, we are in legacy wep mode (group key only), otherwise we are
3380          * in 1X mode.
3381          * In legacy wep mode, we use another host command to the uCode.
3382          */
3383         if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
3384              key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
3385             !sta) {
3386                 if (cmd == SET_KEY)
3387                         is_default_wep_key = !ctx->key_mapping_keys;
3388                 else
3389                         is_default_wep_key =
3390                                         (key->hw_key_idx == HW_KEY_DEFAULT);
3391         }
3392
3393         switch (cmd) {
3394         case SET_KEY:
3395                 if (is_default_wep_key)
3396                         ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
3397                 else
3398                         ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
3399                                                   key, sta_id);
3400
3401                 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
3402                 break;
3403         case DISABLE_KEY:
3404                 if (is_default_wep_key)
3405                         ret = iwl_remove_default_wep_key(priv, ctx, key);
3406                 else
3407                         ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
3408
3409                 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
3410                 break;
3411         default:
3412                 ret = -EINVAL;
3413         }
3414
3415         mutex_unlock(&priv->mutex);
3416         IWL_DEBUG_MAC80211(priv, "leave\n");
3417
3418         return ret;
3419 }
3420
3421 int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw,
3422                             struct ieee80211_vif *vif,
3423                             enum ieee80211_ampdu_mlme_action action,
3424                             struct ieee80211_sta *sta, u16 tid, u16 *ssn,
3425                             u8 buf_size)
3426 {
3427         struct iwl_priv *priv = hw->priv;
3428         int ret = -EINVAL;
3429         struct iwl_station_priv *sta_priv = (void *) sta->drv_priv;
3430
3431         IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
3432                      sta->addr, tid);
3433
3434         if (!(priv->cfg->sku & IWL_SKU_N))
3435                 return -EACCES;
3436
3437         mutex_lock(&priv->mutex);
3438
3439         switch (action) {
3440         case IEEE80211_AMPDU_RX_START:
3441                 IWL_DEBUG_HT(priv, "start Rx\n");
3442                 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
3443                 break;
3444         case IEEE80211_AMPDU_RX_STOP:
3445                 IWL_DEBUG_HT(priv, "stop Rx\n");
3446                 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
3447                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3448                         ret = 0;
3449                 break;
3450         case IEEE80211_AMPDU_TX_START:
3451                 IWL_DEBUG_HT(priv, "start Tx\n");
3452                 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
3453                 if (ret == 0) {
3454                         priv->_agn.agg_tids_count++;
3455                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3456                                      priv->_agn.agg_tids_count);
3457                 }
3458                 break;
3459         case IEEE80211_AMPDU_TX_STOP:
3460                 IWL_DEBUG_HT(priv, "stop Tx\n");
3461                 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
3462                 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3463                         priv->_agn.agg_tids_count--;
3464                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3465                                      priv->_agn.agg_tids_count);
3466                 }
3467                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3468                         ret = 0;
3469                 if (priv->cfg->ht_params &&
3470                     priv->cfg->ht_params->use_rts_for_aggregation) {
3471                         struct iwl_station_priv *sta_priv =
3472                                 (void *) sta->drv_priv;
3473                         /*
3474                          * switch off RTS/CTS if it was previously enabled
3475                          */
3476
3477                         sta_priv->lq_sta.lq.general_params.flags &=
3478                                 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3479                         iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3480                                         &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3481                 }
3482                 break;
3483         case IEEE80211_AMPDU_TX_OPERATIONAL:
3484                 /*
3485                  * If the limit is 0, then it wasn't initialised yet,
3486                  * use the default. We can do that since we take the
3487                  * minimum below, and we don't want to go above our
3488                  * default due to hardware restrictions.
3489                  */
3490                 if (sta_priv->max_agg_bufsize == 0)
3491                         sta_priv->max_agg_bufsize =
3492                                 LINK_QUAL_AGG_FRAME_LIMIT_DEF;
3493
3494                 /*
3495                  * Even though in theory the peer could have different
3496                  * aggregation reorder buffer sizes for different sessions,
3497                  * our ucode doesn't allow for that and has a global limit
3498                  * for each station. Therefore, use the minimum of all the
3499                  * aggregation sessions and our default value.
3500                  */
3501                 sta_priv->max_agg_bufsize =
3502                         min(sta_priv->max_agg_bufsize, buf_size);
3503
3504                 if (priv->cfg->ht_params &&
3505                     priv->cfg->ht_params->use_rts_for_aggregation) {
3506                         /*
3507                          * switch to RTS/CTS if it is the prefer protection
3508                          * method for HT traffic
3509                          */
3510
3511                         sta_priv->lq_sta.lq.general_params.flags |=
3512                                 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3513                 }
3514
3515                 sta_priv->lq_sta.lq.agg_params.agg_frame_cnt_limit =
3516                         sta_priv->max_agg_bufsize;
3517
3518                 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3519                                 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3520                 ret = 0;
3521                 break;
3522         }
3523         mutex_unlock(&priv->mutex);
3524
3525         return ret;
3526 }
3527
3528 int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3529                        struct ieee80211_vif *vif,
3530                        struct ieee80211_sta *sta)
3531 {
3532         struct iwl_priv *priv = hw->priv;
3533         struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3534         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3535         bool is_ap = vif->type == NL80211_IFTYPE_STATION;
3536         int ret;
3537         u8 sta_id;
3538
3539         IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3540                         sta->addr);
3541         mutex_lock(&priv->mutex);
3542         IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3543                         sta->addr);
3544         sta_priv->common.sta_id = IWL_INVALID_STATION;
3545
3546         atomic_set(&sta_priv->pending_frames, 0);
3547         if (vif->type == NL80211_IFTYPE_AP)
3548                 sta_priv->client = true;
3549
3550         ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
3551                                      is_ap, sta, &sta_id);
3552         if (ret) {
3553                 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3554                         sta->addr, ret);
3555                 /* Should we return success if return code is EEXIST ? */
3556                 mutex_unlock(&priv->mutex);
3557                 return ret;
3558         }
3559
3560         sta_priv->common.sta_id = sta_id;
3561
3562         /* Initialize rate scaling */
3563         IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
3564                        sta->addr);
3565         iwl_rs_rate_init(priv, sta, sta_id);
3566         mutex_unlock(&priv->mutex);
3567
3568         return 0;
3569 }
3570
3571 void iwlagn_mac_channel_switch(struct ieee80211_hw *hw,
3572                                struct ieee80211_channel_switch *ch_switch)
3573 {
3574         struct iwl_priv *priv = hw->priv;
3575         const struct iwl_channel_info *ch_info;
3576         struct ieee80211_conf *conf = &hw->conf;
3577         struct ieee80211_channel *channel = ch_switch->channel;
3578         struct iwl_ht_config *ht_conf = &priv->current_ht_config;
3579         /*
3580          * MULTI-FIXME
3581          * When we add support for multiple interfaces, we need to
3582          * revisit this. The channel switch command in the device
3583          * only affects the BSS context, but what does that really
3584          * mean? And what if we get a CSA on the second interface?
3585          * This needs a lot of work.
3586          */
3587         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
3588         u16 ch;
3589         unsigned long flags = 0;
3590
3591         IWL_DEBUG_MAC80211(priv, "enter\n");
3592
3593         if (iwl_is_rfkill(priv))
3594                 goto out_exit;
3595
3596         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3597             test_bit(STATUS_SCANNING, &priv->status))
3598                 goto out_exit;
3599
3600         if (!iwl_is_associated_ctx(ctx))
3601                 goto out_exit;
3602
3603         /* channel switch in progress */
3604         if (priv->switch_rxon.switch_in_progress == true)
3605                 goto out_exit;
3606
3607         mutex_lock(&priv->mutex);
3608         if (priv->cfg->ops->lib->set_channel_switch) {
3609
3610                 ch = channel->hw_value;
3611                 if (le16_to_cpu(ctx->active.channel) != ch) {
3612                         ch_info = iwl_get_channel_info(priv,
3613                                                        channel->band,
3614                                                        ch);
3615                         if (!is_channel_valid(ch_info)) {
3616                                 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3617                                 goto out;
3618                         }
3619                         spin_lock_irqsave(&priv->lock, flags);
3620
3621                         priv->current_ht_config.smps = conf->smps_mode;
3622
3623                         /* Configure HT40 channels */
3624                         ctx->ht.enabled = conf_is_ht(conf);
3625                         if (ctx->ht.enabled) {
3626                                 if (conf_is_ht40_minus(conf)) {
3627                                         ctx->ht.extension_chan_offset =
3628                                                 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
3629                                         ctx->ht.is_40mhz = true;
3630                                 } else if (conf_is_ht40_plus(conf)) {
3631                                         ctx->ht.extension_chan_offset =
3632                                                 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
3633                                         ctx->ht.is_40mhz = true;
3634                                 } else {
3635                                         ctx->ht.extension_chan_offset =
3636                                                 IEEE80211_HT_PARAM_CHA_SEC_NONE;
3637                                         ctx->ht.is_40mhz = false;
3638                                 }
3639                         } else
3640                                 ctx->ht.is_40mhz = false;
3641
3642                         if ((le16_to_cpu(ctx->staging.channel) != ch))
3643                                 ctx->staging.flags = 0;
3644
3645                         iwl_set_rxon_channel(priv, channel, ctx);
3646                         iwl_set_rxon_ht(priv, ht_conf);
3647                         iwl_set_flags_for_band(priv, ctx, channel->band,
3648                                                ctx->vif);
3649                         spin_unlock_irqrestore(&priv->lock, flags);
3650
3651                         iwl_set_rate(priv);
3652                         /*
3653                          * at this point, staging_rxon has the
3654                          * configuration for channel switch
3655                          */
3656                         if (priv->cfg->ops->lib->set_channel_switch(priv,
3657                                                                     ch_switch))
3658                                 priv->switch_rxon.switch_in_progress = false;
3659                 }
3660         }
3661 out:
3662         mutex_unlock(&priv->mutex);
3663 out_exit:
3664         if (!priv->switch_rxon.switch_in_progress)
3665                 ieee80211_chswitch_done(ctx->vif, false);
3666         IWL_DEBUG_MAC80211(priv, "leave\n");
3667 }
3668
3669 void iwlagn_configure_filter(struct ieee80211_hw *hw,
3670                              unsigned int changed_flags,
3671                              unsigned int *total_flags,
3672                              u64 multicast)
3673 {
3674         struct iwl_priv *priv = hw->priv;
3675         __le32 filter_or = 0, filter_nand = 0;
3676         struct iwl_rxon_context *ctx;
3677
3678 #define CHK(test, flag) do { \
3679         if (*total_flags & (test))              \
3680                 filter_or |= (flag);            \
3681         else                                    \
3682                 filter_nand |= (flag);          \
3683         } while (0)
3684
3685         IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3686                         changed_flags, *total_flags);
3687
3688         CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3689         /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
3690         CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
3691         CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3692
3693 #undef CHK
3694
3695         mutex_lock(&priv->mutex);
3696
3697         for_each_context(priv, ctx) {
3698                 ctx->staging.filter_flags &= ~filter_nand;
3699                 ctx->staging.filter_flags |= filter_or;
3700
3701                 /*
3702                  * Not committing directly because hardware can perform a scan,
3703                  * but we'll eventually commit the filter flags change anyway.
3704                  */
3705         }
3706
3707         mutex_unlock(&priv->mutex);
3708
3709         /*
3710          * Receiving all multicast frames is always enabled by the
3711          * default flags setup in iwl_connection_init_rx_config()
3712          * since we currently do not support programming multicast
3713          * filters into the device.
3714          */
3715         *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3716                         FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3717 }
3718
3719 void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop)
3720 {
3721         struct iwl_priv *priv = hw->priv;
3722
3723         mutex_lock(&priv->mutex);
3724         IWL_DEBUG_MAC80211(priv, "enter\n");
3725
3726         /* do not support "flush" */
3727         if (!priv->cfg->ops->lib->txfifo_flush)
3728                 goto done;
3729
3730         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3731                 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
3732                 goto done;
3733         }
3734         if (iwl_is_rfkill(priv)) {
3735                 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
3736                 goto done;
3737         }
3738
3739         /*
3740          * mac80211 will not push any more frames for transmit
3741          * until the flush is completed
3742          */
3743         if (drop) {
3744                 IWL_DEBUG_MAC80211(priv, "send flush command\n");
3745                 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
3746                         IWL_ERR(priv, "flush request fail\n");
3747                         goto done;
3748                 }
3749         }
3750         IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
3751         iwlagn_wait_tx_queue_empty(priv);
3752 done:
3753         mutex_unlock(&priv->mutex);
3754         IWL_DEBUG_MAC80211(priv, "leave\n");
3755 }
3756
3757 static void iwlagn_disable_roc(struct iwl_priv *priv)
3758 {
3759         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_PAN];
3760         struct ieee80211_channel *chan = ACCESS_ONCE(priv->hw->conf.channel);
3761
3762         lockdep_assert_held(&priv->mutex);
3763
3764         if (!ctx->is_active)
3765                 return;
3766
3767         ctx->staging.dev_type = RXON_DEV_TYPE_2STA;
3768         ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3769         iwl_set_rxon_channel(priv, chan, ctx);
3770         iwl_set_flags_for_band(priv, ctx, chan->band, NULL);
3771
3772         priv->_agn.hw_roc_channel = NULL;
3773
3774         iwlcore_commit_rxon(priv, ctx);
3775
3776         ctx->is_active = false;
3777 }
3778
3779 static void iwlagn_bg_roc_done(struct work_struct *work)
3780 {
3781         struct iwl_priv *priv = container_of(work, struct iwl_priv,
3782                                              _agn.hw_roc_work.work);
3783
3784         mutex_lock(&priv->mutex);
3785         ieee80211_remain_on_channel_expired(priv->hw);
3786         iwlagn_disable_roc(priv);
3787         mutex_unlock(&priv->mutex);
3788 }
3789
3790 #ifdef CONFIG_IWL5000
3791 static int iwl_mac_remain_on_channel(struct ieee80211_hw *hw,
3792                                      struct ieee80211_channel *channel,
3793                                      enum nl80211_channel_type channel_type,
3794                                      int duration)
3795 {
3796         struct iwl_priv *priv = hw->priv;
3797         int err = 0;
3798
3799         if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3800                 return -EOPNOTSUPP;
3801
3802         if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
3803                                         BIT(NL80211_IFTYPE_P2P_CLIENT)))
3804                 return -EOPNOTSUPP;
3805
3806         mutex_lock(&priv->mutex);
3807
3808         if (priv->contexts[IWL_RXON_CTX_PAN].is_active ||
3809             test_bit(STATUS_SCAN_HW, &priv->status)) {
3810                 err = -EBUSY;
3811                 goto out;
3812         }
3813
3814         priv->contexts[IWL_RXON_CTX_PAN].is_active = true;
3815         priv->_agn.hw_roc_channel = channel;
3816         priv->_agn.hw_roc_chantype = channel_type;
3817         priv->_agn.hw_roc_duration = DIV_ROUND_UP(duration * 1000, 1024);
3818         iwlcore_commit_rxon(priv, &priv->contexts[IWL_RXON_CTX_PAN]);
3819         queue_delayed_work(priv->workqueue, &priv->_agn.hw_roc_work,
3820                            msecs_to_jiffies(duration + 20));
3821
3822         msleep(IWL_MIN_SLOT_TIME); /* TU is almost ms */
3823         ieee80211_ready_on_channel(priv->hw);
3824
3825  out:
3826         mutex_unlock(&priv->mutex);
3827
3828         return err;
3829 }
3830
3831 static int iwl_mac_cancel_remain_on_channel(struct ieee80211_hw *hw)
3832 {
3833         struct iwl_priv *priv = hw->priv;
3834
3835         if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3836                 return -EOPNOTSUPP;
3837
3838         cancel_delayed_work_sync(&priv->_agn.hw_roc_work);
3839
3840         mutex_lock(&priv->mutex);
3841         iwlagn_disable_roc(priv);
3842         mutex_unlock(&priv->mutex);
3843
3844         return 0;
3845 }
3846 #endif
3847
3848 /*****************************************************************************
3849  *
3850  * driver setup and teardown
3851  *
3852  *****************************************************************************/
3853
3854 static void iwl_setup_deferred_work(struct iwl_priv *priv)
3855 {
3856         priv->workqueue = create_singlethread_workqueue(DRV_NAME);
3857
3858         init_waitqueue_head(&priv->wait_command_queue);
3859
3860         INIT_WORK(&priv->restart, iwl_bg_restart);
3861         INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
3862         INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
3863         INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
3864         INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
3865         INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
3866         INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
3867         INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3868         INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
3869         INIT_DELAYED_WORK(&priv->_agn.hw_roc_work, iwlagn_bg_roc_done);
3870
3871         iwl_setup_scan_deferred_work(priv);
3872
3873         if (priv->cfg->ops->lib->setup_deferred_work)
3874                 priv->cfg->ops->lib->setup_deferred_work(priv);
3875
3876         init_timer(&priv->statistics_periodic);
3877         priv->statistics_periodic.data = (unsigned long)priv;
3878         priv->statistics_periodic.function = iwl_bg_statistics_periodic;
3879
3880         init_timer(&priv->ucode_trace);
3881         priv->ucode_trace.data = (unsigned long)priv;
3882         priv->ucode_trace.function = iwl_bg_ucode_trace;
3883
3884         init_timer(&priv->watchdog);
3885         priv->watchdog.data = (unsigned long)priv;
3886         priv->watchdog.function = iwl_bg_watchdog;
3887
3888         if (!priv->cfg->base_params->use_isr_legacy)
3889                 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3890                         iwl_irq_tasklet, (unsigned long)priv);
3891         else
3892                 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3893                         iwl_irq_tasklet_legacy, (unsigned long)priv);
3894 }
3895
3896 static void iwl_cancel_deferred_work(struct iwl_priv *priv)
3897 {
3898         if (priv->cfg->ops->lib->cancel_deferred_work)
3899                 priv->cfg->ops->lib->cancel_deferred_work(priv);
3900
3901         cancel_delayed_work_sync(&priv->init_alive_start);
3902         cancel_delayed_work(&priv->alive_start);
3903         cancel_work_sync(&priv->run_time_calib_work);
3904         cancel_work_sync(&priv->beacon_update);
3905
3906         iwl_cancel_scan_deferred_work(priv);
3907
3908         cancel_work_sync(&priv->bt_full_concurrency);
3909         cancel_work_sync(&priv->bt_runtime_config);
3910
3911         del_timer_sync(&priv->statistics_periodic);
3912         del_timer_sync(&priv->ucode_trace);
3913 }
3914
3915 static void iwl_init_hw_rates(struct iwl_priv *priv,
3916                               struct ieee80211_rate *rates)
3917 {
3918         int i;
3919
3920         for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3921                 rates[i].bitrate = iwl_rates[i].ieee * 5;
3922                 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3923                 rates[i].hw_value_short = i;
3924                 rates[i].flags = 0;
3925                 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3926                         /*
3927                          * If CCK != 1M then set short preamble rate flag.
3928                          */
3929                         rates[i].flags |=
3930                                 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3931                                         0 : IEEE80211_RATE_SHORT_PREAMBLE;
3932                 }
3933         }
3934 }
3935
3936 static int iwl_init_drv(struct iwl_priv *priv)
3937 {
3938         int ret;
3939
3940         spin_lock_init(&priv->sta_lock);
3941         spin_lock_init(&priv->hcmd_lock);
3942
3943         INIT_LIST_HEAD(&priv->free_frames);
3944
3945         mutex_init(&priv->mutex);
3946         mutex_init(&priv->sync_cmd_mutex);
3947
3948         priv->ieee_channels = NULL;
3949         priv->ieee_rates = NULL;
3950         priv->band = IEEE80211_BAND_2GHZ;
3951
3952         priv->iw_mode = NL80211_IFTYPE_STATION;
3953         priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
3954         priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
3955         priv->_agn.agg_tids_count = 0;
3956
3957         /* initialize force reset */
3958         priv->force_reset[IWL_RF_RESET].reset_duration =
3959                 IWL_DELAY_NEXT_FORCE_RF_RESET;
3960         priv->force_reset[IWL_FW_RESET].reset_duration =
3961                 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
3962
3963         /* Choose which receivers/antennas to use */
3964         if (priv->cfg->ops->hcmd->set_rxon_chain)
3965                 priv->cfg->ops->hcmd->set_rxon_chain(priv,
3966                                         &priv->contexts[IWL_RXON_CTX_BSS]);
3967
3968         iwl_init_scan_params(priv);
3969
3970         /* init bt coex */
3971         if (priv->cfg->bt_params &&
3972             priv->cfg->bt_params->advanced_bt_coexist) {
3973                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
3974                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
3975                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
3976                 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
3977                 priv->bt_duration = BT_DURATION_LIMIT_DEF;
3978                 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
3979         }
3980
3981         /* Set the tx_power_user_lmt to the lowest power level
3982          * this value will get overwritten by channel max power avg
3983          * from eeprom */
3984         priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3985         priv->tx_power_next = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3986
3987         ret = iwl_init_channel_map(priv);
3988         if (ret) {
3989                 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3990                 goto err;
3991         }
3992
3993         ret = iwlcore_init_geos(priv);
3994         if (ret) {
3995                 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3996                 goto err_free_channel_map;
3997         }
3998         iwl_init_hw_rates(priv, priv->ieee_rates);
3999
4000         return 0;
4001
4002 err_free_channel_map:
4003         iwl_free_channel_map(priv);
4004 err:
4005         return ret;
4006 }
4007
4008 static void iwl_uninit_drv(struct iwl_priv *priv)
4009 {
4010         iwl_calib_free_results(priv);
4011         iwlcore_free_geos(priv);
4012         iwl_free_channel_map(priv);
4013         kfree(priv->scan_cmd);
4014 }
4015
4016 #ifdef CONFIG_IWL5000
4017 struct ieee80211_ops iwlagn_hw_ops = {
4018         .tx = iwlagn_mac_tx,
4019         .start = iwlagn_mac_start,
4020         .stop = iwlagn_mac_stop,
4021         .add_interface = iwl_mac_add_interface,
4022         .remove_interface = iwl_mac_remove_interface,
4023         .change_interface = iwl_mac_change_interface,
4024         .config = iwlagn_mac_config,
4025         .configure_filter = iwlagn_configure_filter,
4026         .set_key = iwlagn_mac_set_key,
4027         .update_tkip_key = iwlagn_mac_update_tkip_key,
4028         .conf_tx = iwl_mac_conf_tx,
4029         .bss_info_changed = iwlagn_bss_info_changed,
4030         .ampdu_action = iwlagn_mac_ampdu_action,
4031         .hw_scan = iwl_mac_hw_scan,
4032         .sta_notify = iwlagn_mac_sta_notify,
4033         .sta_add = iwlagn_mac_sta_add,
4034         .sta_remove = iwl_mac_sta_remove,
4035         .channel_switch = iwlagn_mac_channel_switch,
4036         .flush = iwlagn_mac_flush,
4037         .tx_last_beacon = iwl_mac_tx_last_beacon,
4038         .remain_on_channel = iwl_mac_remain_on_channel,
4039         .cancel_remain_on_channel = iwl_mac_cancel_remain_on_channel,
4040 };
4041 #endif
4042
4043 static void iwl_hw_detect(struct iwl_priv *priv)
4044 {
4045         priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
4046         priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
4047         pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
4048         IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", priv->rev_id);
4049 }
4050
4051 static int iwl_set_hw_params(struct iwl_priv *priv)
4052 {
4053         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
4054         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
4055         if (priv->cfg->mod_params->amsdu_size_8K)
4056                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
4057         else
4058                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
4059
4060         priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
4061
4062         if (priv->cfg->mod_params->disable_11n)
4063                 priv->cfg->sku &= ~IWL_SKU_N;
4064
4065         /* Device-specific setup */
4066         return priv->cfg->ops->lib->set_hw_params(priv);
4067 }
4068
4069 static const u8 iwlagn_bss_ac_to_fifo[] = {
4070         IWL_TX_FIFO_VO,
4071         IWL_TX_FIFO_VI,
4072         IWL_TX_FIFO_BE,
4073         IWL_TX_FIFO_BK,
4074 };
4075
4076 static const u8 iwlagn_bss_ac_to_queue[] = {
4077         0, 1, 2, 3,
4078 };
4079
4080 static const u8 iwlagn_pan_ac_to_fifo[] = {
4081         IWL_TX_FIFO_VO_IPAN,
4082         IWL_TX_FIFO_VI_IPAN,
4083         IWL_TX_FIFO_BE_IPAN,
4084         IWL_TX_FIFO_BK_IPAN,
4085 };
4086
4087 static const u8 iwlagn_pan_ac_to_queue[] = {
4088         7, 6, 5, 4,
4089 };
4090
4091 static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
4092 {
4093         int err = 0, i;
4094         struct iwl_priv *priv;
4095         struct ieee80211_hw *hw;
4096         struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
4097         unsigned long flags;
4098         u16 pci_cmd, num_mac;
4099
4100         /************************
4101          * 1. Allocating HW data
4102          ************************/
4103
4104         /* Disabling hardware scan means that mac80211 will perform scans
4105          * "the hard way", rather than using device's scan. */
4106         if (cfg->mod_params->disable_hw_scan) {
4107                 dev_printk(KERN_DEBUG, &(pdev->dev),
4108                         "sw scan support is deprecated\n");
4109 #ifdef CONFIG_IWL5000
4110                 iwlagn_hw_ops.hw_scan = NULL;
4111 #endif
4112 #ifdef CONFIG_IWL4965
4113                 iwl4965_hw_ops.hw_scan = NULL;
4114 #endif
4115         }
4116
4117         hw = iwl_alloc_all(cfg);
4118         if (!hw) {
4119                 err = -ENOMEM;
4120                 goto out;
4121         }
4122         priv = hw->priv;
4123         /* At this point both hw and priv are allocated. */
4124
4125         /*
4126          * The default context is always valid,
4127          * more may be discovered when firmware
4128          * is loaded.
4129          */
4130         priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
4131
4132         for (i = 0; i < NUM_IWL_RXON_CTX; i++)
4133                 priv->contexts[i].ctxid = i;
4134
4135         priv->contexts[IWL_RXON_CTX_BSS].always_active = true;
4136         priv->contexts[IWL_RXON_CTX_BSS].is_active = true;
4137         priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
4138         priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
4139         priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
4140         priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
4141         priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
4142         priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
4143         priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
4144         priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
4145         priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
4146                 BIT(NL80211_IFTYPE_ADHOC);
4147         priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
4148                 BIT(NL80211_IFTYPE_STATION);
4149         priv->contexts[IWL_RXON_CTX_BSS].ap_devtype = RXON_DEV_TYPE_AP;
4150         priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
4151         priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
4152         priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
4153
4154         priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
4155         priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING;
4156         priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC;
4157         priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
4158         priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
4159         priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
4160         priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
4161         priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
4162         priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
4163         priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
4164         priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
4165         priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
4166                 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
4167 #ifdef CONFIG_IWL_P2P
4168         priv->contexts[IWL_RXON_CTX_PAN].interface_modes |=
4169                 BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT(NL80211_IFTYPE_P2P_GO);
4170 #endif
4171         priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP;
4172         priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA;
4173         priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P;
4174
4175         BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
4176
4177         SET_IEEE80211_DEV(hw, &pdev->dev);
4178
4179         IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
4180         priv->cfg = cfg;
4181         priv->pci_dev = pdev;
4182         priv->inta_mask = CSR_INI_SET_MASK;
4183
4184         /* is antenna coupling more than 35dB ? */
4185         priv->bt_ant_couple_ok =
4186                 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
4187                 true : false;
4188
4189         /* enable/disable bt channel inhibition */
4190         priv->bt_ch_announce = iwlagn_bt_ch_announce;
4191         IWL_DEBUG_INFO(priv, "BT channel inhibition is %s\n",
4192                        (priv->bt_ch_announce) ? "On" : "Off");
4193
4194         if (iwl_alloc_traffic_mem(priv))
4195                 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
4196
4197         /**************************
4198          * 2. Initializing PCI bus
4199          **************************/
4200         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
4201                                 PCIE_LINK_STATE_CLKPM);
4202
4203         if (pci_enable_device(pdev)) {
4204                 err = -ENODEV;
4205                 goto out_ieee80211_free_hw;
4206         }
4207
4208         pci_set_master(pdev);
4209
4210         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
4211         if (!err)
4212                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
4213         if (err) {
4214                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4215                 if (!err)
4216                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4217                 /* both attempts failed: */
4218                 if (err) {
4219                         IWL_WARN(priv, "No suitable DMA available.\n");
4220                         goto out_pci_disable_device;
4221                 }
4222         }
4223
4224         err = pci_request_regions(pdev, DRV_NAME);
4225         if (err)
4226                 goto out_pci_disable_device;
4227
4228         pci_set_drvdata(pdev, priv);
4229
4230
4231         /***********************
4232          * 3. Read REV register
4233          ***********************/
4234         priv->hw_base = pci_iomap(pdev, 0, 0);
4235         if (!priv->hw_base) {
4236                 err = -ENODEV;
4237                 goto out_pci_release_regions;
4238         }
4239
4240         IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
4241                 (unsigned long long) pci_resource_len(pdev, 0));
4242         IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
4243
4244         /* these spin locks will be used in apm_ops.init and EEPROM access
4245          * we should init now
4246          */
4247         spin_lock_init(&priv->reg_lock);
4248         spin_lock_init(&priv->lock);
4249
4250         /*
4251          * stop and reset the on-board processor just in case it is in a
4252          * strange state ... like being left stranded by a primary kernel
4253          * and this is now the kdump kernel trying to start up
4254          */
4255         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4256
4257         iwl_hw_detect(priv);
4258         IWL_INFO(priv, "Detected %s, REV=0x%X\n",
4259                 priv->cfg->name, priv->hw_rev);
4260
4261         /* We disable the RETRY_TIMEOUT register (0x41) to keep
4262          * PCI Tx retries from interfering with C3 CPU state */
4263         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
4264
4265         iwl_prepare_card_hw(priv);
4266         if (!priv->hw_ready) {
4267                 IWL_WARN(priv, "Failed, HW not ready\n");
4268                 goto out_iounmap;
4269         }
4270
4271         /*****************
4272          * 4. Read EEPROM
4273          *****************/
4274         /* Read the EEPROM */
4275         err = iwl_eeprom_init(priv);
4276         if (err) {
4277                 IWL_ERR(priv, "Unable to init EEPROM\n");
4278                 goto out_iounmap;
4279         }
4280         err = iwl_eeprom_check_version(priv);
4281         if (err)
4282                 goto out_free_eeprom;
4283
4284         err = iwl_eeprom_check_sku(priv);
4285         if (err)
4286                 goto out_free_eeprom;
4287
4288         /* extract MAC Address */
4289         iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
4290         IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
4291         priv->hw->wiphy->addresses = priv->addresses;
4292         priv->hw->wiphy->n_addresses = 1;
4293         num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
4294         if (num_mac > 1) {
4295                 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
4296                        ETH_ALEN);
4297                 priv->addresses[1].addr[5]++;
4298                 priv->hw->wiphy->n_addresses++;
4299         }
4300
4301         /************************
4302          * 5. Setup HW constants
4303          ************************/
4304         if (iwl_set_hw_params(priv)) {
4305                 IWL_ERR(priv, "failed to set hw parameters\n");
4306                 goto out_free_eeprom;
4307         }
4308
4309         /*******************
4310          * 6. Setup priv
4311          *******************/
4312
4313         err = iwl_init_drv(priv);
4314         if (err)
4315                 goto out_free_eeprom;
4316         /* At this point both hw and priv are initialized. */
4317
4318         /********************
4319          * 7. Setup services
4320          ********************/
4321         spin_lock_irqsave(&priv->lock, flags);
4322         iwl_disable_interrupts(priv);
4323         spin_unlock_irqrestore(&priv->lock, flags);
4324
4325         pci_enable_msi(priv->pci_dev);
4326
4327         if (priv->cfg->ops->lib->isr_ops.alloc)
4328                 priv->cfg->ops->lib->isr_ops.alloc(priv);
4329
4330         err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr_ops.isr,
4331                           IRQF_SHARED, DRV_NAME, priv);
4332         if (err) {
4333                 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4334                 goto out_disable_msi;
4335         }
4336
4337         iwl_setup_deferred_work(priv);
4338         iwl_setup_rx_handlers(priv);
4339
4340         /*********************************************
4341          * 8. Enable interrupts and read RFKILL state
4342          *********************************************/
4343
4344         /* enable rfkill interrupt: hw bug w/a */
4345         pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
4346         if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
4347                 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
4348                 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
4349         }
4350
4351         iwl_enable_rfkill_int(priv);
4352
4353         /* If platform's RF_KILL switch is NOT set to KILL */
4354         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
4355                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
4356         else
4357                 set_bit(STATUS_RF_KILL_HW, &priv->status);
4358
4359         wiphy_rfkill_set_hw_state(priv->hw->wiphy,
4360                 test_bit(STATUS_RF_KILL_HW, &priv->status));
4361
4362         iwl_power_initialize(priv);
4363         iwl_tt_initialize(priv);
4364
4365         init_completion(&priv->_agn.firmware_loading_complete);
4366
4367         err = iwl_request_firmware(priv, true);
4368         if (err)
4369                 goto out_destroy_workqueue;
4370
4371         return 0;
4372
4373  out_destroy_workqueue:
4374         destroy_workqueue(priv->workqueue);
4375         priv->workqueue = NULL;
4376         free_irq(priv->pci_dev->irq, priv);
4377         if (priv->cfg->ops->lib->isr_ops.free)
4378                 priv->cfg->ops->lib->isr_ops.free(priv);
4379  out_disable_msi:
4380         pci_disable_msi(priv->pci_dev);
4381         iwl_uninit_drv(priv);
4382  out_free_eeprom:
4383         iwl_eeprom_free(priv);
4384  out_iounmap:
4385         pci_iounmap(pdev, priv->hw_base);
4386  out_pci_release_regions:
4387         pci_set_drvdata(pdev, NULL);
4388         pci_release_regions(pdev);
4389  out_pci_disable_device:
4390         pci_disable_device(pdev);
4391  out_ieee80211_free_hw:
4392         iwl_free_traffic_mem(priv);
4393         ieee80211_free_hw(priv->hw);
4394  out:
4395         return err;
4396 }
4397
4398 static void __devexit iwl_pci_remove(struct pci_dev *pdev)
4399 {
4400         struct iwl_priv *priv = pci_get_drvdata(pdev);
4401         unsigned long flags;
4402
4403         if (!priv)
4404                 return;
4405
4406         wait_for_completion(&priv->_agn.firmware_loading_complete);
4407
4408         IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
4409
4410         iwl_dbgfs_unregister(priv);
4411         sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
4412
4413         /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
4414          * to be called and iwl_down since we are removing the device
4415          * we need to set STATUS_EXIT_PENDING bit.
4416          */
4417         set_bit(STATUS_EXIT_PENDING, &priv->status);
4418
4419         iwl_leds_exit(priv);
4420
4421         if (priv->mac80211_registered) {
4422                 ieee80211_unregister_hw(priv->hw);
4423                 priv->mac80211_registered = 0;
4424         } else {
4425                 iwl_down(priv);
4426         }
4427
4428         /*
4429          * Make sure device is reset to low power before unloading driver.
4430          * This may be redundant with iwl_down(), but there are paths to
4431          * run iwl_down() without calling apm_ops.stop(), and there are
4432          * paths to avoid running iwl_down() at all before leaving driver.
4433          * This (inexpensive) call *makes sure* device is reset.
4434          */
4435         iwl_apm_stop(priv);
4436
4437         iwl_tt_exit(priv);
4438
4439         /* make sure we flush any pending irq or
4440          * tasklet for the driver
4441          */
4442         spin_lock_irqsave(&priv->lock, flags);
4443         iwl_disable_interrupts(priv);
4444         spin_unlock_irqrestore(&priv->lock, flags);
4445
4446         iwl_synchronize_irq(priv);
4447
4448         iwl_dealloc_ucode_pci(priv);
4449
4450         if (priv->rxq.bd)
4451                 iwlagn_rx_queue_free(priv, &priv->rxq);
4452         iwlagn_hw_txq_ctx_free(priv);
4453
4454         iwl_eeprom_free(priv);
4455
4456
4457         /*netif_stop_queue(dev); */
4458         flush_workqueue(priv->workqueue);
4459
4460         /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
4461          * priv->workqueue... so we can't take down the workqueue
4462          * until now... */
4463         destroy_workqueue(priv->workqueue);
4464         priv->workqueue = NULL;
4465         iwl_free_traffic_mem(priv);
4466
4467         free_irq(priv->pci_dev->irq, priv);
4468         pci_disable_msi(priv->pci_dev);
4469         pci_iounmap(pdev, priv->hw_base);
4470         pci_release_regions(pdev);
4471         pci_disable_device(pdev);
4472         pci_set_drvdata(pdev, NULL);
4473
4474         iwl_uninit_drv(priv);
4475
4476         if (priv->cfg->ops->lib->isr_ops.free)
4477                 priv->cfg->ops->lib->isr_ops.free(priv);
4478
4479         dev_kfree_skb(priv->beacon_skb);
4480
4481         ieee80211_free_hw(priv->hw);
4482 }
4483
4484
4485 /*****************************************************************************
4486  *
4487  * driver and module entry point
4488  *
4489  *****************************************************************************/
4490
4491 /* Hardware specific file defines the PCI IDs table for that hardware module */
4492 static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4493 #ifdef CONFIG_IWL4965
4494         {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
4495         {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4496 #endif /* CONFIG_IWL4965 */
4497 #ifdef CONFIG_IWL5000
4498 /* 5100 Series WiFi */
4499         {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
4500         {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
4501         {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
4502         {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
4503         {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
4504         {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
4505         {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
4506         {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
4507         {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
4508         {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
4509         {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
4510         {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
4511         {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
4512         {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
4513         {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
4514         {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
4515         {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
4516         {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
4517         {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
4518         {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
4519         {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
4520         {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
4521         {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
4522         {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
4523
4524 /* 5300 Series WiFi */
4525         {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
4526         {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
4527         {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
4528         {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
4529         {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
4530         {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
4531         {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
4532         {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
4533         {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
4534         {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
4535         {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
4536         {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
4537
4538 /* 5350 Series WiFi/WiMax */
4539         {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4540         {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4541         {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4542
4543 /* 5150 Series Wifi/WiMax */
4544         {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4545         {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4546         {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4547         {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4548         {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4549         {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4550
4551         {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4552         {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4553         {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4554         {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
4555
4556 /* 6x00 Series */
4557         {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4558         {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4559         {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4560         {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4561         {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4562         {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4563         {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4564         {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4565         {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4566         {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4567
4568 /* 6x05 Series */
4569         {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6005_2agn_cfg)},
4570         {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6005_2abg_cfg)},
4571         {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6005_2bg_cfg)},
4572         {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6005_2agn_cfg)},
4573         {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6005_2abg_cfg)},
4574         {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6005_2agn_cfg)},
4575         {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6005_2abg_cfg)},
4576
4577 /* 6x30 Series */
4578         {IWL_PCI_DEVICE(0x008A, 0x5305, iwl1030_bgn_cfg)},
4579         {IWL_PCI_DEVICE(0x008A, 0x5307, iwl1030_bg_cfg)},
4580         {IWL_PCI_DEVICE(0x008A, 0x5325, iwl1030_bgn_cfg)},
4581         {IWL_PCI_DEVICE(0x008A, 0x5327, iwl1030_bg_cfg)},
4582         {IWL_PCI_DEVICE(0x008B, 0x5315, iwl1030_bgn_cfg)},
4583         {IWL_PCI_DEVICE(0x008B, 0x5317, iwl1030_bg_cfg)},
4584         {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6030_2agn_cfg)},
4585         {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6030_2bgn_cfg)},
4586         {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6030_2abg_cfg)},
4587         {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6030_2agn_cfg)},
4588         {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6030_2bgn_cfg)},
4589         {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6030_2abg_cfg)},
4590         {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6030_2bg_cfg)},
4591         {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6030_2agn_cfg)},
4592         {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6030_2bgn_cfg)},
4593         {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6030_2abg_cfg)},
4594
4595 /* 6x50 WiFi/WiMax Series */
4596         {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4597         {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4598         {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4599         {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
4600         {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4601         {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4602
4603 /* 6150 WiFi/WiMax Series */
4604         {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6150_bgn_cfg)},
4605         {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6150_bgn_cfg)},
4606         {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6150_bgn_cfg)},
4607         {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6150_bgn_cfg)},
4608         {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6150_bgn_cfg)},
4609         {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6150_bgn_cfg)},
4610
4611 /* 1000 Series WiFi */
4612         {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4613         {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4614         {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4615         {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4616         {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4617         {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4618         {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4619         {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4620         {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4621         {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4622         {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4623         {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
4624
4625 /* 100 Series WiFi */
4626         {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
4627         {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
4628         {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
4629         {IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg)},
4630         {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
4631         {IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg)},
4632
4633 /* 130 Series WiFi */
4634         {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)},
4635         {IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)},
4636         {IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)},
4637         {IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)},
4638         {IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)},
4639         {IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)},
4640
4641 /* 2x00 Series */
4642         {IWL_PCI_DEVICE(0x0890, 0x4022, iwl2000_2bgn_cfg)},
4643         {IWL_PCI_DEVICE(0x0891, 0x4222, iwl2000_2bgn_cfg)},
4644         {IWL_PCI_DEVICE(0x0890, 0x4422, iwl2000_2bgn_cfg)},
4645         {IWL_PCI_DEVICE(0x0890, 0x4026, iwl2000_2bg_cfg)},
4646         {IWL_PCI_DEVICE(0x0891, 0x4226, iwl2000_2bg_cfg)},
4647         {IWL_PCI_DEVICE(0x0890, 0x4426, iwl2000_2bg_cfg)},
4648
4649 /* 2x30 Series */
4650         {IWL_PCI_DEVICE(0x0887, 0x4062, iwl2030_2bgn_cfg)},
4651         {IWL_PCI_DEVICE(0x0888, 0x4262, iwl2030_2bgn_cfg)},
4652         {IWL_PCI_DEVICE(0x0887, 0x4462, iwl2030_2bgn_cfg)},
4653         {IWL_PCI_DEVICE(0x0887, 0x4066, iwl2030_2bg_cfg)},
4654         {IWL_PCI_DEVICE(0x0888, 0x4266, iwl2030_2bg_cfg)},
4655         {IWL_PCI_DEVICE(0x0887, 0x4466, iwl2030_2bg_cfg)},
4656
4657 /* 6x35 Series */
4658         {IWL_PCI_DEVICE(0x088E, 0x4060, iwl6035_2agn_cfg)},
4659         {IWL_PCI_DEVICE(0x088F, 0x4260, iwl6035_2agn_cfg)},
4660         {IWL_PCI_DEVICE(0x088E, 0x4460, iwl6035_2agn_cfg)},
4661         {IWL_PCI_DEVICE(0x088E, 0x4064, iwl6035_2abg_cfg)},
4662         {IWL_PCI_DEVICE(0x088F, 0x4264, iwl6035_2abg_cfg)},
4663         {IWL_PCI_DEVICE(0x088E, 0x4464, iwl6035_2abg_cfg)},
4664         {IWL_PCI_DEVICE(0x088E, 0x4066, iwl6035_2bg_cfg)},
4665         {IWL_PCI_DEVICE(0x088F, 0x4266, iwl6035_2bg_cfg)},
4666         {IWL_PCI_DEVICE(0x088E, 0x4466, iwl6035_2bg_cfg)},
4667
4668 /* 200 Series */
4669         {IWL_PCI_DEVICE(0x0894, 0x0022, iwl200_bgn_cfg)},
4670         {IWL_PCI_DEVICE(0x0895, 0x0222, iwl200_bgn_cfg)},
4671         {IWL_PCI_DEVICE(0x0894, 0x0422, iwl200_bgn_cfg)},
4672         {IWL_PCI_DEVICE(0x0894, 0x0026, iwl200_bg_cfg)},
4673         {IWL_PCI_DEVICE(0x0895, 0x0226, iwl200_bg_cfg)},
4674         {IWL_PCI_DEVICE(0x0894, 0x0426, iwl200_bg_cfg)},
4675
4676 /* 230 Series */
4677         {IWL_PCI_DEVICE(0x0892, 0x0062, iwl230_bgn_cfg)},
4678         {IWL_PCI_DEVICE(0x0893, 0x0262, iwl230_bgn_cfg)},
4679         {IWL_PCI_DEVICE(0x0892, 0x0462, iwl230_bgn_cfg)},
4680         {IWL_PCI_DEVICE(0x0892, 0x0066, iwl230_bg_cfg)},
4681         {IWL_PCI_DEVICE(0x0893, 0x0266, iwl230_bg_cfg)},
4682         {IWL_PCI_DEVICE(0x0892, 0x0466, iwl230_bg_cfg)},
4683
4684 #endif /* CONFIG_IWL5000 */
4685
4686         {0}
4687 };
4688 MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4689
4690 static struct pci_driver iwl_driver = {
4691         .name = DRV_NAME,
4692         .id_table = iwl_hw_card_ids,
4693         .probe = iwl_pci_probe,
4694         .remove = __devexit_p(iwl_pci_remove),
4695         .driver.pm = IWL_PM_OPS,
4696 };
4697
4698 static int __init iwl_init(void)
4699 {
4700
4701         int ret;
4702         pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4703         pr_info(DRV_COPYRIGHT "\n");
4704
4705         ret = iwlagn_rate_control_register();
4706         if (ret) {
4707                 pr_err("Unable to register rate control algorithm: %d\n", ret);
4708                 return ret;
4709         }
4710
4711         ret = pci_register_driver(&iwl_driver);
4712         if (ret) {
4713                 pr_err("Unable to initialize PCI module\n");
4714                 goto error_register;
4715         }
4716
4717         return ret;
4718
4719 error_register:
4720         iwlagn_rate_control_unregister();
4721         return ret;
4722 }
4723
4724 static void __exit iwl_exit(void)
4725 {
4726         pci_unregister_driver(&iwl_driver);
4727         iwlagn_rate_control_unregister();
4728 }
4729
4730 module_exit(iwl_exit);
4731 module_init(iwl_init);
4732
4733 #ifdef CONFIG_IWLWIFI_DEBUG
4734 module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
4735 MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4736 module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
4737 MODULE_PARM_DESC(debug, "debug output mask");
4738 #endif
4739
4740 module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
4741 MODULE_PARM_DESC(swcrypto50,
4742                  "using crypto in software (default 0 [hardware]) (deprecated)");
4743 module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4744 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4745 module_param_named(queues_num50,
4746                    iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4747 MODULE_PARM_DESC(queues_num50,
4748                  "number of hw queues in 50xx series (deprecated)");
4749 module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4750 MODULE_PARM_DESC(queues_num, "number of hw queues.");
4751 module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4752 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
4753 module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4754 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4755 module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
4756                    int, S_IRUGO);
4757 MODULE_PARM_DESC(amsdu_size_8K50,
4758                  "enable 8K amsdu size in 50XX series (deprecated)");
4759 module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4760                    int, S_IRUGO);
4761 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4762 module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4763 MODULE_PARM_DESC(fw_restart50,
4764                  "restart firmware in case of error (deprecated)");
4765 module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4766 MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4767 module_param_named(
4768         disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
4769 MODULE_PARM_DESC(disable_hw_scan,
4770                  "disable hardware scanning (default 0) (deprecated)");
4771
4772 module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4773                    S_IRUGO);
4774 MODULE_PARM_DESC(ucode_alternative,
4775                  "specify ucode alternative to use from ucode file");
4776
4777 module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
4778 MODULE_PARM_DESC(antenna_coupling,
4779                  "specify antenna coupling in dB (defualt: 0 dB)");
4780
4781 module_param_named(bt_ch_inhibition, iwlagn_bt_ch_announce, bool, S_IRUGO);
4782 MODULE_PARM_DESC(bt_ch_inhibition,
4783                  "Disable BT channel inhibition (default: enable)");