Pileus Git - ~andy/linux/blob - drivers/net/wireless/iwlwifi/iwl-agn.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29
  30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  31
  32 #include <linux/kernel.h>
  33 #include <linux/module.h>
  34 #include <linux/init.h>
  35 #include <linux/pci.h>
  36 #include <linux/pci-aspm.h>
  37 #include <linux/slab.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/delay.h>
  40 #include <linux/sched.h>
  41 #include <linux/skbuff.h>
  42 #include <linux/netdevice.h>
  43 #include <linux/wireless.h>
  44 #include <linux/firmware.h>
  45 #include <linux/etherdevice.h>
  46 #include <linux/if_arp.h>
  47
  48 #include <net/mac80211.h>
  49
  50 #include <asm/div64.h>
  51
  52 #define DRV_NAME        "iwlagn"
  53
  54 #include "iwl-eeprom.h"
  55 #include "iwl-dev.h"
  56 #include "iwl-core.h"
  57 #include "iwl-io.h"
  58 #include "iwl-helpers.h"
  59 #include "iwl-sta.h"
  60 #include "iwl-agn-calib.h"
  61 #include "iwl-agn.h"
  62 #include "iwl-agn-led.h"
  63
  64
  65 /******************************************************************************
  66  *
  67  * module boiler plate
  68  *
  69  ******************************************************************************/
  70
  71 /*
  72  * module name, copyright, version, etc.
  73  */
  74 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  75
  76 #ifdef CONFIG_IWLWIFI_DEBUG
  77 #define VD "d"
  78 #else
  79 #define VD
  80 #endif
  81
  82 #define DRV_VERSION     IWLWIFI_VERSION VD
  83
  84
  85 MODULE_DESCRIPTION(DRV_DESCRIPTION);
  86 MODULE_VERSION(DRV_VERSION);
  87 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  88 MODULE_LICENSE("GPL");
  89 MODULE_ALIAS("iwl4965");
  90
  91 static int iwlagn_ant_coupling;
  92 static bool iwlagn_bt_ch_announce = 1;
  93
  94 void iwl_update_chain_flags(struct iwl_priv *priv)
  95 {
  96         struct iwl_rxon_context *ctx;
  97
  98         if (priv->cfg->ops->hcmd->set_rxon_chain) {
  99                 for_each_context(priv, ctx) {
 100                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
 101                         if (ctx->active.rx_chain != ctx->staging.rx_chain)
 102                                 iwlcore_commit_rxon(priv, ctx);
 103                 }
 104         }
 105 }
 106
 107 static void iwl_clear_free_frames(struct iwl_priv *priv)
 108 {
 109         struct list_head *element;
 110
 111         IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
 112                        priv->frames_count);
 113
 114         while (!list_empty(&priv->free_frames)) {
 115                 element = priv->free_frames.next;
 116                 list_del(element);
 117                 kfree(list_entry(element, struct iwl_frame, list));
 118                 priv->frames_count--;
 119         }
 120
 121         if (priv->frames_count) {
 122                 IWL_WARN(priv, "%d frames still in use.  Did we lose one?\n",
 123                             priv->frames_count);
 124                 priv->frames_count = 0;
 125         }
 126 }
 127
 128 static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
 129 {
 130         struct iwl_frame *frame;
 131         struct list_head *element;
 132         if (list_empty(&priv->free_frames)) {
 133                 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
 134                 if (!frame) {
 135                         IWL_ERR(priv, "Could not allocate frame!\n");
 136                         return NULL;
 137                 }
 138
 139                 priv->frames_count++;
 140                 return frame;
 141         }
 142
 143         element = priv->free_frames.next;
 144         list_del(element);
 145         return list_entry(element, struct iwl_frame, list);
 146 }
 147
 148 static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
 149 {
 150         memset(frame, 0, sizeof(*frame));
 151         list_add(&frame->list, &priv->free_frames);
 152 }
 153
 154 static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
 155                                  struct ieee80211_hdr *hdr,
 156                                  int left)
 157 {
 158         lockdep_assert_held(&priv->mutex);
 159
 160         if (!priv->beacon_skb)
 161                 return 0;
 162
 163         if (priv->beacon_skb->len > left)
 164                 return 0;
 165
 166         memcpy(hdr, priv->beacon_skb->data, priv->beacon_skb->len);
 167
 168         return priv->beacon_skb->len;
 169 }
 170
 171 /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
 172 static void iwl_set_beacon_tim(struct iwl_priv *priv,
 173                                struct iwl_tx_beacon_cmd *tx_beacon_cmd,
 174                                u8 *beacon, u32 frame_size)
 175 {
 176         u16 tim_idx;
 177         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
 178
 179         /*
 180          * The index is relative to frame start but we start looking at the
 181          * variable-length part of the beacon.
 182          */
 183         tim_idx = mgmt->u.beacon.variable - beacon;
 184
 185         /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
 186         while ((tim_idx < (frame_size - 2)) &&
 187                         (beacon[tim_idx] != WLAN_EID_TIM))
 188                 tim_idx += beacon[tim_idx+1] + 2;
 189
 190         /* If TIM field was found, set variables */
 191         if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
 192                 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
 193                 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
 194         } else
 195                 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
 196 }
 197
 198 static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
 199                                        struct iwl_frame *frame)
 200 {
 201         struct iwl_tx_beacon_cmd *tx_beacon_cmd;
 202         u32 frame_size;
 203         u32 rate_flags;
 204         u32 rate;
 205         /*
 206          * We have to set up the TX command, the TX Beacon command, and the
 207          * beacon contents.
 208          */
 209
 210         lockdep_assert_held(&priv->mutex);
 211
 212         if (!priv->beacon_ctx) {
 213                 IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
 214                 return 0;
 215         }
 216
 217         /* Initialize memory */
 218         tx_beacon_cmd = &frame->u.beacon;
 219         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
 220
 221         /* Set up TX beacon contents */
 222         frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
 223                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
 224         if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
 225                 return 0;
 226         if (!frame_size)
 227                 return 0;
 228
 229         /* Set up TX command fields */
 230         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
 231         tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
 232         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
 233         tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
 234                 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
 235
 236         /* Set up TX beacon command fields */
 237         iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
 238                            frame_size);
 239
 240         /* Set up packet rate and flags */
 241         rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx);
 242         priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
 243                                               priv->hw_params.valid_tx_ant);
 244         rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
 245         if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
 246                 rate_flags |= RATE_MCS_CCK_MSK;
 247         tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
 248                         rate_flags);
 249
 250         return sizeof(*tx_beacon_cmd) + frame_size;
 251 }
 252
 253 int iwlagn_send_beacon_cmd(struct iwl_priv *priv)
 254 {
 255         struct iwl_frame *frame;
 256         unsigned int frame_size;
 257         int rc;
 258
 259         frame = iwl_get_free_frame(priv);
 260         if (!frame) {
 261                 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
 262                           "command.\n");
 263                 return -ENOMEM;
 264         }
 265
 266         frame_size = iwl_hw_get_beacon_cmd(priv, frame);
 267         if (!frame_size) {
 268                 IWL_ERR(priv, "Error configuring the beacon command\n");
 269                 iwl_free_frame(priv, frame);
 270                 return -EINVAL;
 271         }
 272
 273         rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
 274                               &frame->u.cmd[0]);
 275
 276         iwl_free_frame(priv, frame);
 277
 278         return rc;
 279 }
 280
 281 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
 282 {
 283         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 284
 285         dma_addr_t addr = get_unaligned_le32(&tb->lo);
 286         if (sizeof(dma_addr_t) > sizeof(u32))
 287                 addr |=
 288                 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
 289
 290         return addr;
 291 }
 292
 293 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
 294 {
 295         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 296
 297         return le16_to_cpu(tb->hi_n_len) >> 4;
 298 }
 299
 300 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
 301                                   dma_addr_t addr, u16 len)
 302 {
 303         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 304         u16 hi_n_len = len << 4;
 305
 306         put_unaligned_le32(addr, &tb->lo);
 307         if (sizeof(dma_addr_t) > sizeof(u32))
 308                 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
 309
 310         tb->hi_n_len = cpu_to_le16(hi_n_len);
 311
 312         tfd->num_tbs = idx + 1;
 313 }
 314
 315 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
 316 {
 317         return tfd->num_tbs & 0x1f;
 318 }
 319
 320 /**
 321  * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
 322  * @priv - driver private data
 323  * @txq - tx queue
 324  *
 325  * Does NOT advance any TFD circular buffer read/write indexes
 326  * Does NOT free the TFD itself (which is within circular buffer)
 327  */
 328 void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
 329 {
 330         struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
 331         struct iwl_tfd *tfd;
 332         struct pci_dev *dev = priv->pci_dev;
 333         int index = txq->q.read_ptr;
 334         int i;
 335         int num_tbs;
 336
 337         tfd = &tfd_tmp[index];
 338
 339         /* Sanity check on number of chunks */
 340         num_tbs = iwl_tfd_get_num_tbs(tfd);
 341
 342         if (num_tbs >= IWL_NUM_OF_TBS) {
 343                 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
 344                 /* @todo issue fatal error, it is quite serious situation */
 345                 return;
 346         }
 347
 348         /* Unmap tx_cmd */
 349         if (num_tbs)
 350                 pci_unmap_single(dev,
 351                                 dma_unmap_addr(&txq->meta[index], mapping),
 352                                 dma_unmap_len(&txq->meta[index], len),
 353                                 PCI_DMA_BIDIRECTIONAL);
 354
 355         /* Unmap chunks, if any. */
 356         for (i = 1; i < num_tbs; i++)
 357                 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
 358                                 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
 359
 360         /* free SKB */
 361         if (txq->txb) {
 362                 struct sk_buff *skb;
 363
 364                 skb = txq->txb[txq->q.read_ptr].skb;
 365
 366                 /* can be called from irqs-disabled context */
 367                 if (skb) {
 368                         dev_kfree_skb_any(skb);
 369                         txq->txb[txq->q.read_ptr].skb = NULL;
 370                 }
 371         }
 372 }
 373
 374 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
 375                                  struct iwl_tx_queue *txq,
 376                                  dma_addr_t addr, u16 len,
 377                                  u8 reset, u8 pad)
 378 {
 379         struct iwl_queue *q;
 380         struct iwl_tfd *tfd, *tfd_tmp;
 381         u32 num_tbs;
 382
 383         q = &txq->q;
 384         tfd_tmp = (struct iwl_tfd *)txq->tfds;
 385         tfd = &tfd_tmp[q->write_ptr];
 386
 387         if (reset)
 388                 memset(tfd, 0, sizeof(*tfd));
 389
 390         num_tbs = iwl_tfd_get_num_tbs(tfd);
 391
 392         /* Each TFD can point to a maximum 20 Tx buffers */
 393         if (num_tbs >= IWL_NUM_OF_TBS) {
 394                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
 395                           IWL_NUM_OF_TBS);
 396                 return -EINVAL;
 397         }
 398
 399         BUG_ON(addr & ~DMA_BIT_MASK(36));
 400         if (unlikely(addr & ~IWL_TX_DMA_MASK))
 401                 IWL_ERR(priv, "Unaligned address = %llx\n",
 402                           (unsigned long long)addr);
 403
 404         iwl_tfd_set_tb(tfd, num_tbs, addr, len);
 405
 406         return 0;
 407 }
 408
 409 /*
 410  * Tell nic where to find circular buffer of Tx Frame Descriptors for
 411  * given Tx queue, and enable the DMA channel used for that queue.
 412  *
 413  * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
 414  * channels supported in hardware.
 415  */
 416 int iwl_hw_tx_queue_init(struct iwl_priv *priv,
 417                          struct iwl_tx_queue *txq)
 418 {
 419         int txq_id = txq->q.id;
 420
 421         /* Circular buffer (TFD queue in DRAM) physical base address */
 422         iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
 423                              txq->q.dma_addr >> 8);
 424
 425         return 0;
 426 }
 427
 428 /******************************************************************************
 429  *
 430  * Generic RX handler implementations
 431  *
 432  ******************************************************************************/
 433 static void iwl_rx_reply_alive(struct iwl_priv *priv,
 434                                 struct iwl_rx_mem_buffer *rxb)
 435 {
 436         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 437         struct iwl_alive_resp *palive;
 438         struct delayed_work *pwork;
 439
 440         palive = &pkt->u.alive_frame;
 441
 442         IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
 443                        "0x%01X 0x%01X\n",
 444                        palive->is_valid, palive->ver_type,
 445                        palive->ver_subtype);
 446
 447         if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
 448                 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
 449                 memcpy(&priv->card_alive_init,
 450                        &pkt->u.alive_frame,
 451                        sizeof(struct iwl_init_alive_resp));
 452                 pwork = &priv->init_alive_start;
 453         } else {
 454                 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
 455                 memcpy(&priv->card_alive, &pkt->u.alive_frame,
 456                        sizeof(struct iwl_alive_resp));
 457                 pwork = &priv->alive_start;
 458         }
 459
 460         /* We delay the ALIVE response by 5ms to
 461          * give the HW RF Kill time to activate... */
 462         if (palive->is_valid == UCODE_VALID_OK)
 463                 queue_delayed_work(priv->workqueue, pwork,
 464                                    msecs_to_jiffies(5));
 465         else {
 466                 IWL_WARN(priv, "%s uCode did not respond OK.\n",
 467                         (palive->ver_subtype == INITIALIZE_SUBTYPE) ?
 468                         "init" : "runtime");
 469                 /*
 470                  * If fail to load init uCode,
 471                  * let's try to load the init uCode again.
 472                  * We should not get into this situation, but if it
 473                  * does happen, we should not move on and loading "runtime"
 474                  * without proper calibrate the device.
 475                  */
 476                 if (palive->ver_subtype == INITIALIZE_SUBTYPE)
 477                         priv->ucode_type = UCODE_NONE;
 478                 queue_work(priv->workqueue, &priv->restart);
 479         }
 480 }
 481
 482 static void iwl_bg_beacon_update(struct work_struct *work)
 483 {
 484         struct iwl_priv *priv =
 485                 container_of(work, struct iwl_priv, beacon_update);
 486         struct sk_buff *beacon;
 487
 488         mutex_lock(&priv->mutex);
 489         if (!priv->beacon_ctx) {
 490                 IWL_ERR(priv, "updating beacon w/o beacon context!\n");
 491                 goto out;
 492         }
 493
 494         if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) {
 495                 /*
 496                  * The ucode will send beacon notifications even in
 497                  * IBSS mode, but we don't want to process them. But
 498                  * we need to defer the type check to here due to
 499                  * requiring locking around the beacon_ctx access.
 500                  */
 501                 goto out;
 502         }
 503
 504         /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
 505         beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif);
 506         if (!beacon) {
 507                 IWL_ERR(priv, "update beacon failed -- keeping old\n");
 508                 goto out;
 509         }
 510
 511         /* new beacon skb is allocated every time; dispose previous.*/
 512         dev_kfree_skb(priv->beacon_skb);
 513
 514         priv->beacon_skb = beacon;
 515
 516         iwlagn_send_beacon_cmd(priv);
 517  out:
 518         mutex_unlock(&priv->mutex);
 519 }
 520
 521 static void iwl_bg_bt_runtime_config(struct work_struct *work)
 522 {
 523         struct iwl_priv *priv =
 524                 container_of(work, struct iwl_priv, bt_runtime_config);
 525
 526         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 527                 return;
 528
 529         /* dont send host command if rf-kill is on */
 530         if (!iwl_is_ready_rf(priv))
 531                 return;
 532         priv->cfg->ops->hcmd->send_bt_config(priv);
 533 }
 534
 535 static void iwl_bg_bt_full_concurrency(struct work_struct *work)
 536 {
 537         struct iwl_priv *priv =
 538                 container_of(work, struct iwl_priv, bt_full_concurrency);
 539         struct iwl_rxon_context *ctx;
 540
 541         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 542                 return;
 543
 544         /* dont send host command if rf-kill is on */
 545         if (!iwl_is_ready_rf(priv))
 546                 return;
 547
 548         IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
 549                        priv->bt_full_concurrent ?
 550                        "full concurrency" : "3-wire");
 551
 552         /*
 553          * LQ & RXON updated cmds must be sent before BT Config cmd
 554          * to avoid 3-wire collisions
 555          */
 556         mutex_lock(&priv->mutex);
 557         for_each_context(priv, ctx) {
 558                 if (priv->cfg->ops->hcmd->set_rxon_chain)
 559                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
 560                 iwlcore_commit_rxon(priv, ctx);
 561         }
 562         mutex_unlock(&priv->mutex);
 563
 564         priv->cfg->ops->hcmd->send_bt_config(priv);
 565 }
 566
 567 /**
 568  * iwl_bg_statistics_periodic - Timer callback to queue statistics
 569  *
 570  * This callback is provided in order to send a statistics request.
 571  *
 572  * This timer function is continually reset to execute within
 573  * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
 574  * was received.  We need to ensure we receive the statistics in order
 575  * to update the temperature used for calibrating the TXPOWER.
 576  */
 577 static void iwl_bg_statistics_periodic(unsigned long data)
 578 {
 579         struct iwl_priv *priv = (struct iwl_priv *)data;
 580
 581         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 582                 return;
 583
 584         /* dont send host command if rf-kill is on */
 585         if (!iwl_is_ready_rf(priv))
 586                 return;
 587
 588         iwl_send_statistics_request(priv, CMD_ASYNC, false);
 589 }
 590
 591
 592 static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
 593                                         u32 start_idx, u32 num_events,
 594                                         u32 mode)
 595 {
 596         u32 i;
 597         u32 ptr;        /* SRAM byte address of log data */
 598         u32 ev, time, data; /* event log data */
 599         unsigned long reg_flags;
 600
 601         if (mode == 0)
 602                 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
 603         else
 604                 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
 605
 606         /* Make sure device is powered up for SRAM reads */
 607         spin_lock_irqsave(&priv->reg_lock, reg_flags);
 608         if (iwl_grab_nic_access(priv)) {
 609                 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
 610                 return;
 611         }
 612
 613         /* Set starting address; reads will auto-increment */
 614         _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
 615         rmb();
 616
 617         /*
 618          * "time" is actually "data" for mode 0 (no timestamp).
 619          * place event id # at far right for easier visual parsing.
 620          */
 621         for (i = 0; i < num_events; i++) {
 622                 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 623                 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 624                 if (mode == 0) {
 625                         trace_iwlwifi_dev_ucode_cont_event(priv,
 626                                                         0, time, ev);
 627                 } else {
 628                         data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 629                         trace_iwlwifi_dev_ucode_cont_event(priv,
 630                                                 time, data, ev);
 631                 }
 632         }
 633         /* Allow device to power down */
 634         iwl_release_nic_access(priv);
 635         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
 636 }
 637
 638 static void iwl_continuous_event_trace(struct iwl_priv *priv)
 639 {
 640         u32 capacity;   /* event log capacity in # entries */
 641         u32 base;       /* SRAM byte address of event log header */
 642         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
 643         u32 num_wraps;  /* # times uCode wrapped to top of log */
 644         u32 next_entry; /* index of next entry to be written by uCode */
 645
 646         if (priv->ucode_type == UCODE_INIT)
 647                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
 648         else
 649                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
 650         if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
 651                 capacity = iwl_read_targ_mem(priv, base);
 652                 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
 653                 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
 654                 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
 655         } else
 656                 return;
 657
 658         if (num_wraps == priv->event_log.num_wraps) {
 659                 iwl_print_cont_event_trace(priv,
 660                                        base, priv->event_log.next_entry,
 661                                        next_entry - priv->event_log.next_entry,
 662                                        mode);
 663                 priv->event_log.non_wraps_count++;
 664         } else {
 665                 if ((num_wraps - priv->event_log.num_wraps) > 1)
 666                         priv->event_log.wraps_more_count++;
 667                 else
 668                         priv->event_log.wraps_once_count++;
 669                 trace_iwlwifi_dev_ucode_wrap_event(priv,
 670                                 num_wraps - priv->event_log.num_wraps,
 671                                 next_entry, priv->event_log.next_entry);
 672                 if (next_entry < priv->event_log.next_entry) {
 673                         iwl_print_cont_event_trace(priv, base,
 674                                priv->event_log.next_entry,
 675                                capacity - priv->event_log.next_entry,
 676                                mode);
 677
 678                         iwl_print_cont_event_trace(priv, base, 0,
 679                                 next_entry, mode);
 680                 } else {
 681                         iwl_print_cont_event_trace(priv, base,
 682                                next_entry, capacity - next_entry,
 683                                mode);
 684
 685                         iwl_print_cont_event_trace(priv, base, 0,
 686                                 next_entry, mode);
 687                 }
 688         }
 689         priv->event_log.num_wraps = num_wraps;
 690         priv->event_log.next_entry = next_entry;
 691 }
 692
 693 /**
 694  * iwl_bg_ucode_trace - Timer callback to log ucode event
 695  *
 696  * The timer is continually set to execute every
 697  * UCODE_TRACE_PERIOD milliseconds after the last timer expired
 698  * this function is to perform continuous uCode event logging operation
 699  * if enabled
 700  */
 701 static void iwl_bg_ucode_trace(unsigned long data)
 702 {
 703         struct iwl_priv *priv = (struct iwl_priv *)data;
 704
 705         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 706                 return;
 707
 708         if (priv->event_log.ucode_trace) {
 709                 iwl_continuous_event_trace(priv);
 710                 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
 711                 mod_timer(&priv->ucode_trace,
 712                          jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
 713         }
 714 }
 715
 716 static void iwlagn_rx_beacon_notif(struct iwl_priv *priv,
 717                                    struct iwl_rx_mem_buffer *rxb)
 718 {
 719         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 720         struct iwlagn_beacon_notif *beacon = (void *)pkt->u.raw;
 721 #ifdef CONFIG_IWLWIFI_DEBUG
 722         u16 status = le16_to_cpu(beacon->beacon_notify_hdr.status.status);
 723         u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
 724
 725         IWL_DEBUG_RX(priv, "beacon status %#x, retries:%d ibssmgr:%d "
 726                 "tsf:0x%.8x%.8x rate:%d\n",
 727                 status & TX_STATUS_MSK,
 728                 beacon->beacon_notify_hdr.failure_frame,
 729                 le32_to_cpu(beacon->ibss_mgr_status),
 730                 le32_to_cpu(beacon->high_tsf),
 731                 le32_to_cpu(beacon->low_tsf), rate);
 732 #endif
 733
 734         priv->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
 735
 736         if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
 737                 queue_work(priv->workqueue, &priv->beacon_update);
 738 }
 739
 740 /* Handle notification from uCode that card's power state is changing
 741  * due to software, hardware, or critical temperature RFKILL */
 742 static void iwl_rx_card_state_notif(struct iwl_priv *priv,
 743                                     struct iwl_rx_mem_buffer *rxb)
 744 {
 745         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 746         u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
 747         unsigned long status = priv->status;
 748
 749         IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
 750                           (flags & HW_CARD_DISABLED) ? "Kill" : "On",
 751                           (flags & SW_CARD_DISABLED) ? "Kill" : "On",
 752                           (flags & CT_CARD_DISABLED) ?
 753                           "Reached" : "Not reached");
 754
 755         if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
 756                      CT_CARD_DISABLED)) {
 757
 758                 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
 759                             CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 760
 761                 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
 762                                         HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
 763
 764                 if (!(flags & RXON_CARD_DISABLED)) {
 765                         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
 766                                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 767                         iwl_write_direct32(priv, HBUS_TARG_MBX_C,
 768                                         HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
 769                 }
 770                 if (flags & CT_CARD_DISABLED)
 771                         iwl_tt_enter_ct_kill(priv);
 772         }
 773         if (!(flags & CT_CARD_DISABLED))
 774                 iwl_tt_exit_ct_kill(priv);
 775
 776         if (flags & HW_CARD_DISABLED)
 777                 set_bit(STATUS_RF_KILL_HW, &priv->status);
 778         else
 779                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
 780
 781
 782         if (!(flags & RXON_CARD_DISABLED))
 783                 iwl_scan_cancel(priv);
 784
 785         if ((test_bit(STATUS_RF_KILL_HW, &status) !=
 786              test_bit(STATUS_RF_KILL_HW, &priv->status)))
 787                 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
 788                         test_bit(STATUS_RF_KILL_HW, &priv->status));
 789         else
 790                 wake_up_interruptible(&priv->wait_command_queue);
 791 }
 792
 793 static void iwl_bg_tx_flush(struct work_struct *work)
 794 {
 795         struct iwl_priv *priv =
 796                 container_of(work, struct iwl_priv, tx_flush);
 797
 798         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 799                 return;
 800
 801         /* do nothing if rf-kill is on */
 802         if (!iwl_is_ready_rf(priv))
 803                 return;
 804
 805         if (priv->cfg->ops->lib->txfifo_flush) {
 806                 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
 807                 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
 808         }
 809 }
 810
 811 /**
 812  * iwl_setup_rx_handlers - Initialize Rx handler callbacks
 813  *
 814  * Setup the RX handlers for each of the reply types sent from the uCode
 815  * to the host.
 816  *
 817  * This function chains into the hardware specific files for them to setup
 818  * any hardware specific handlers as well.
 819  */
 820 static void iwl_setup_rx_handlers(struct iwl_priv *priv)
 821 {
 822         priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
 823         priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
 824         priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
 825         priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
 826                         iwl_rx_spectrum_measure_notif;
 827         priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
 828         priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
 829             iwl_rx_pm_debug_statistics_notif;
 830         priv->rx_handlers[BEACON_NOTIFICATION] = iwlagn_rx_beacon_notif;
 831
 832         /*
 833          * The same handler is used for both the REPLY to a discrete
 834          * statistics request from the host as well as for the periodic
 835          * statistics notifications (after received beacons) from the uCode.
 836          */
 837         priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
 838         priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
 839
 840         iwl_setup_rx_scan_handlers(priv);
 841
 842         /* status change handler */
 843         priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
 844
 845         priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
 846             iwl_rx_missed_beacon_notif;
 847         /* Rx handlers */
 848         priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
 849         priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
 850         /* block ack */
 851         priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
 852         /* Set up hardware specific Rx handlers */
 853         priv->cfg->ops->lib->rx_handler_setup(priv);
 854 }
 855
 856 /**
 857  * iwl_rx_handle - Main entry function for receiving responses from uCode
 858  *
 859  * Uses the priv->rx_handlers callback function array to invoke
 860  * the appropriate handlers, including command responses,
 861  * frame-received notifications, and other notifications.
 862  */
 863 static void iwl_rx_handle(struct iwl_priv *priv)
 864 {
 865         struct iwl_rx_mem_buffer *rxb;
 866         struct iwl_rx_packet *pkt;
 867         struct iwl_rx_queue *rxq = &priv->rxq;
 868         u32 r, i;
 869         int reclaim;
 870         unsigned long flags;
 871         u8 fill_rx = 0;
 872         u32 count = 8;
 873         int total_empty;
 874
 875         /* uCode's read index (stored in shared DRAM) indicates the last Rx
 876          * buffer that the driver may process (last buffer filled by ucode). */
 877         r = le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF;
 878         i = rxq->read;
 879
 880         /* Rx interrupt, but nothing sent from uCode */
 881         if (i == r)
 882                 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
 883
 884         /* calculate total frames need to be restock after handling RX */
 885         total_empty = r - rxq->write_actual;
 886         if (total_empty < 0)
 887                 total_empty += RX_QUEUE_SIZE;
 888
 889         if (total_empty > (RX_QUEUE_SIZE / 2))
 890                 fill_rx = 1;
 891
 892         while (i != r) {
 893                 int len;
 894
 895                 rxb = rxq->queue[i];
 896
 897                 /* If an RXB doesn't have a Rx queue slot associated with it,
 898                  * then a bug has been introduced in the queue refilling
 899                  * routines -- catch it here */
 900                 BUG_ON(rxb == NULL);
 901
 902                 rxq->queue[i] = NULL;
 903
 904                 pci_unmap_page(priv->pci_dev, rxb->page_dma,
 905                                PAGE_SIZE << priv->hw_params.rx_page_order,
 906                                PCI_DMA_FROMDEVICE);
 907                 pkt = rxb_addr(rxb);
 908
 909                 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
 910                 len += sizeof(u32); /* account for status word */
 911                 trace_iwlwifi_dev_rx(priv, pkt, len);
 912
 913                 /* Reclaim a command buffer only if this packet is a response
 914                  *   to a (driver-originated) command.
 915                  * If the packet (e.g. Rx frame) originated from uCode,
 916                  *   there is no command buffer to reclaim.
 917                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
 918                  *   but apparently a few don't get set; catch them here. */
 919                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
 920                         (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
 921                         (pkt->hdr.cmd != REPLY_RX) &&
 922                         (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
 923                         (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
 924                         (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
 925                         (pkt->hdr.cmd != REPLY_TX);
 926
 927                 /*
 928                  * Do the notification wait before RX handlers so
 929                  * even if the RX handler consumes the RXB we have
 930                  * access to it in the notification wait entry.
 931                  */
 932                 if (!list_empty(&priv->_agn.notif_waits)) {
 933                         struct iwl_notification_wait *w;
 934
 935                         spin_lock(&priv->_agn.notif_wait_lock);
 936                         list_for_each_entry(w, &priv->_agn.notif_waits, list) {
 937                                 if (w->cmd == pkt->hdr.cmd) {
 938                                         w->triggered = true;
 939                                         if (w->fn)
 940                                                 w->fn(priv, pkt);
 941                                 }
 942                         }
 943                         spin_unlock(&priv->_agn.notif_wait_lock);
 944
 945                         wake_up_all(&priv->_agn.notif_waitq);
 946                 }
 947
 948                 /* Based on type of command response or notification,
 949                  *   handle those that need handling via function in
 950                  *   rx_handlers table.  See iwl_setup_rx_handlers() */
 951                 if (priv->rx_handlers[pkt->hdr.cmd]) {
 952                         IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
 953                                 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
 954                         priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
 955                         priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
 956                 } else {
 957                         /* No handling needed */
 958                         IWL_DEBUG_RX(priv,
 959                                 "r %d i %d No handler needed for %s, 0x%02x\n",
 960                                 r, i, get_cmd_string(pkt->hdr.cmd),
 961                                 pkt->hdr.cmd);
 962                 }
 963
 964                 /*
 965                  * XXX: After here, we should always check rxb->page
 966                  * against NULL before touching it or its virtual
 967                  * memory (pkt). Because some rx_handler might have
 968                  * already taken or freed the pages.
 969                  */
 970
 971                 if (reclaim) {
 972                         /* Invoke any callbacks, transfer the buffer to caller,
 973                          * and fire off the (possibly) blocking iwl_send_cmd()
 974                          * as we reclaim the driver command queue */
 975                         if (rxb->page)
 976                                 iwl_tx_cmd_complete(priv, rxb);
 977                         else
 978                                 IWL_WARN(priv, "Claim null rxb?\n");
 979                 }
 980
 981                 /* Reuse the page if possible. For notification packets and
 982                  * SKBs that fail to Rx correctly, add them back into the
 983                  * rx_free list for reuse later. */
 984                 spin_lock_irqsave(&rxq->lock, flags);
 985                 if (rxb->page != NULL) {
 986                         rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
 987                                 0, PAGE_SIZE << priv->hw_params.rx_page_order,
 988                                 PCI_DMA_FROMDEVICE);
 989                         list_add_tail(&rxb->list, &rxq->rx_free);
 990                         rxq->free_count++;
 991                 } else
 992                         list_add_tail(&rxb->list, &rxq->rx_used);
 993
 994                 spin_unlock_irqrestore(&rxq->lock, flags);
 995
 996                 i = (i + 1) & RX_QUEUE_MASK;
 997                 /* If there are a lot of unused frames,
 998                  * restock the Rx queue so ucode wont assert. */
 999                 if (fill_rx) {
1000                         count++;
1001                         if (count >= 8) {
1002                                 rxq->read = i;
1003                                 iwlagn_rx_replenish_now(priv);
1004                                 count = 0;
1005                         }
1006                 }
1007         }
1008
1009         /* Backtrack one entry */
1010         rxq->read = i;
1011         if (fill_rx)
1012                 iwlagn_rx_replenish_now(priv);
1013         else
1014                 iwlagn_rx_queue_restock(priv);
1015 }
1016
1017 /* call this function to flush any scheduled tasklet */
1018 static inline void iwl_synchronize_irq(struct iwl_priv *priv)
1019 {
1020         /* wait to make sure we flush pending tasklet*/
1021         synchronize_irq(priv->pci_dev->irq);
1022         tasklet_kill(&priv->irq_tasklet);
1023 }
1024
1025 static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
1026 {
1027         u32 inta, handled = 0;
1028         u32 inta_fh;
1029         unsigned long flags;
1030         u32 i;
1031 #ifdef CONFIG_IWLWIFI_DEBUG
1032         u32 inta_mask;
1033 #endif
1034
1035         spin_lock_irqsave(&priv->lock, flags);
1036
1037         /* Ack/clear/reset pending uCode interrupts.
1038          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1039          *  and will clear only when CSR_FH_INT_STATUS gets cleared. */
1040         inta = iwl_read32(priv, CSR_INT);
1041         iwl_write32(priv, CSR_INT, inta);
1042
1043         /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1044          * Any new interrupts that happen after this, either while we're
1045          * in this tasklet, or later, will show up in next ISR/tasklet. */
1046         inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1047         iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
1048
1049 #ifdef CONFIG_IWLWIFI_DEBUG
1050         if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1051                 /* just for debug */
1052                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1053                 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
1054                               inta, inta_mask, inta_fh);
1055         }
1056 #endif
1057
1058         spin_unlock_irqrestore(&priv->lock, flags);
1059
1060         /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1061          * atomic, make sure that inta covers all the interrupts that
1062          * we've discovered, even if FH interrupt came in just after
1063          * reading CSR_INT. */
1064         if (inta_fh & CSR49_FH_INT_RX_MASK)
1065                 inta |= CSR_INT_BIT_FH_RX;
1066         if (inta_fh & CSR49_FH_INT_TX_MASK)
1067                 inta |= CSR_INT_BIT_FH_TX;
1068
1069         /* Now service all interrupt bits discovered above. */
1070         if (inta & CSR_INT_BIT_HW_ERR) {
1071                 IWL_ERR(priv, "Hardware error detected.  Restarting.\n");
1072
1073                 /* Tell the device to stop sending interrupts */
1074                 iwl_disable_interrupts(priv);
1075
1076                 priv->isr_stats.hw++;
1077                 iwl_irq_handle_error(priv);
1078
1079                 handled |= CSR_INT_BIT_HW_ERR;
1080
1081                 return;
1082         }
1083
1084 #ifdef CONFIG_IWLWIFI_DEBUG
1085         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1086                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1087                 if (inta & CSR_INT_BIT_SCD) {
1088                         IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1089                                       "the frame/frames.\n");
1090                         priv->isr_stats.sch++;
1091                 }
1092
1093                 /* Alive notification via Rx interrupt will do the real work */
1094                 if (inta & CSR_INT_BIT_ALIVE) {
1095                         IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1096                         priv->isr_stats.alive++;
1097                 }
1098         }
1099 #endif
1100         /* Safely ignore these bits for debug checks below */
1101         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1102
1103         /* HW RF KILL switch toggled */
1104         if (inta & CSR_INT_BIT_RF_KILL) {
1105                 int hw_rf_kill = 0;
1106                 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1107                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1108                         hw_rf_kill = 1;
1109
1110                 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1111                                 hw_rf_kill ? "disable radio" : "enable radio");
1112
1113                 priv->isr_stats.rfkill++;
1114
1115                 /* driver only loads ucode once setting the interface up.
1116                  * the driver allows loading the ucode even if the radio
1117                  * is killed. Hence update the killswitch state here. The
1118                  * rfkill handler will care about restarting if needed.
1119                  */
1120                 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1121                         if (hw_rf_kill)
1122                                 set_bit(STATUS_RF_KILL_HW, &priv->status);
1123                         else
1124                                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1125                         wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1126                 }
1127
1128                 handled |= CSR_INT_BIT_RF_KILL;
1129         }
1130
1131         /* Chip got too hot and stopped itself */
1132         if (inta & CSR_INT_BIT_CT_KILL) {
1133                 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1134                 priv->isr_stats.ctkill++;
1135                 handled |= CSR_INT_BIT_CT_KILL;
1136         }
1137
1138         /* Error detected by uCode */
1139         if (inta & CSR_INT_BIT_SW_ERR) {
1140                 IWL_ERR(priv, "Microcode SW error detected. "
1141                         " Restarting 0x%X.\n", inta);
1142                 priv->isr_stats.sw++;
1143                 iwl_irq_handle_error(priv);
1144                 handled |= CSR_INT_BIT_SW_ERR;
1145         }
1146
1147         /*
1148          * uCode wakes up after power-down sleep.
1149          * Tell device about any new tx or host commands enqueued,
1150          * and about any Rx buffers made available while asleep.
1151          */
1152         if (inta & CSR_INT_BIT_WAKEUP) {
1153                 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1154                 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1155                 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1156                         iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1157                 priv->isr_stats.wakeup++;
1158                 handled |= CSR_INT_BIT_WAKEUP;
1159         }
1160
1161         /* All uCode command responses, including Tx command responses,
1162          * Rx "responses" (frame-received notification), and other
1163          * notifications from uCode come through here*/
1164         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1165                 iwl_rx_handle(priv);
1166                 priv->isr_stats.rx++;
1167                 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1168         }
1169
1170         /* This "Tx" DMA channel is used only for loading uCode */
1171         if (inta & CSR_INT_BIT_FH_TX) {
1172                 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1173                 priv->isr_stats.tx++;
1174                 handled |= CSR_INT_BIT_FH_TX;
1175                 /* Wake up uCode load routine, now that load is complete */
1176                 priv->ucode_write_complete = 1;
1177                 wake_up_interruptible(&priv->wait_command_queue);
1178         }
1179
1180         if (inta & ~handled) {
1181                 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1182                 priv->isr_stats.unhandled++;
1183         }
1184
1185         if (inta & ~(priv->inta_mask)) {
1186                 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1187                          inta & ~priv->inta_mask);
1188                 IWL_WARN(priv, "   with FH_INT = 0x%08x\n", inta_fh);
1189         }
1190
1191         /* Re-enable all interrupts */
1192         /* only Re-enable if disabled by irq */
1193         if (test_bit(STATUS_INT_ENABLED, &priv->status))
1194                 iwl_enable_interrupts(priv);
1195         /* Re-enable RF_KILL if it occurred */
1196         else if (handled & CSR_INT_BIT_RF_KILL)
1197                 iwl_enable_rfkill_int(priv);
1198
1199 #ifdef CONFIG_IWLWIFI_DEBUG
1200         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1201                 inta = iwl_read32(priv, CSR_INT);
1202                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1203                 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1204                 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
1205                         "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1206         }
1207 #endif
1208 }
1209
1210 /* tasklet for iwlagn interrupt */
1211 static void iwl_irq_tasklet(struct iwl_priv *priv)
1212 {
1213         u32 inta = 0;
1214         u32 handled = 0;
1215         unsigned long flags;
1216         u32 i;
1217 #ifdef CONFIG_IWLWIFI_DEBUG
1218         u32 inta_mask;
1219 #endif
1220
1221         spin_lock_irqsave(&priv->lock, flags);
1222
1223         /* Ack/clear/reset pending uCode interrupts.
1224          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1225          */
1226         /* There is a hardware bug in the interrupt mask function that some
1227          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1228          * they are disabled in the CSR_INT_MASK register. Furthermore the
1229          * ICT interrupt handling mechanism has another bug that might cause
1230          * these unmasked interrupts fail to be detected. We workaround the
1231          * hardware bugs here by ACKing all the possible interrupts so that
1232          * interrupt coalescing can still be achieved.
1233          */
1234         iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
1235
1236         inta = priv->_agn.inta;
1237
1238 #ifdef CONFIG_IWLWIFI_DEBUG
1239         if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1240                 /* just for debug */
1241                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1242                 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1243                                 inta, inta_mask);
1244         }
1245 #endif
1246
1247         spin_unlock_irqrestore(&priv->lock, flags);
1248
1249         /* saved interrupt in inta variable now we can reset priv->_agn.inta */
1250         priv->_agn.inta = 0;
1251
1252         /* Now service all interrupt bits discovered above. */
1253         if (inta & CSR_INT_BIT_HW_ERR) {
1254                 IWL_ERR(priv, "Hardware error detected.  Restarting.\n");
1255
1256                 /* Tell the device to stop sending interrupts */
1257                 iwl_disable_interrupts(priv);
1258
1259                 priv->isr_stats.hw++;
1260                 iwl_irq_handle_error(priv);
1261
1262                 handled |= CSR_INT_BIT_HW_ERR;
1263
1264                 return;
1265         }
1266
1267 #ifdef CONFIG_IWLWIFI_DEBUG
1268         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1269                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1270                 if (inta & CSR_INT_BIT_SCD) {
1271                         IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1272                                       "the frame/frames.\n");
1273                         priv->isr_stats.sch++;
1274                 }
1275
1276                 /* Alive notification via Rx interrupt will do the real work */
1277                 if (inta & CSR_INT_BIT_ALIVE) {
1278                         IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1279                         priv->isr_stats.alive++;
1280                 }
1281         }
1282 #endif
1283         /* Safely ignore these bits for debug checks below */
1284         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1285
1286         /* HW RF KILL switch toggled */
1287         if (inta & CSR_INT_BIT_RF_KILL) {
1288                 int hw_rf_kill = 0;
1289                 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1290                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1291                         hw_rf_kill = 1;
1292
1293                 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1294                                 hw_rf_kill ? "disable radio" : "enable radio");
1295
1296                 priv->isr_stats.rfkill++;
1297
1298                 /* driver only loads ucode once setting the interface up.
1299                  * the driver allows loading the ucode even if the radio
1300                  * is killed. Hence update the killswitch state here. The
1301                  * rfkill handler will care about restarting if needed.
1302                  */
1303                 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1304                         if (hw_rf_kill)
1305                                 set_bit(STATUS_RF_KILL_HW, &priv->status);
1306                         else
1307                                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1308                         wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1309                 }
1310
1311                 handled |= CSR_INT_BIT_RF_KILL;
1312         }
1313
1314         /* Chip got too hot and stopped itself */
1315         if (inta & CSR_INT_BIT_CT_KILL) {
1316                 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1317                 priv->isr_stats.ctkill++;
1318                 handled |= CSR_INT_BIT_CT_KILL;
1319         }
1320
1321         /* Error detected by uCode */
1322         if (inta & CSR_INT_BIT_SW_ERR) {
1323                 IWL_ERR(priv, "Microcode SW error detected. "
1324                         " Restarting 0x%X.\n", inta);
1325                 priv->isr_stats.sw++;
1326                 iwl_irq_handle_error(priv);
1327                 handled |= CSR_INT_BIT_SW_ERR;
1328         }
1329
1330         /* uCode wakes up after power-down sleep */
1331         if (inta & CSR_INT_BIT_WAKEUP) {
1332                 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1333                 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1334                 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1335                         iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1336
1337                 priv->isr_stats.wakeup++;
1338
1339                 handled |= CSR_INT_BIT_WAKEUP;
1340         }
1341
1342         /* All uCode command responses, including Tx command responses,
1343          * Rx "responses" (frame-received notification), and other
1344          * notifications from uCode come through here*/
1345         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1346                         CSR_INT_BIT_RX_PERIODIC)) {
1347                 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
1348                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1349                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1350                         iwl_write32(priv, CSR_FH_INT_STATUS,
1351                                         CSR49_FH_INT_RX_MASK);
1352                 }
1353                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1354                         handled |= CSR_INT_BIT_RX_PERIODIC;
1355                         iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1356                 }
1357                 /* Sending RX interrupt require many steps to be done in the
1358                  * the device:
1359                  * 1- write interrupt to current index in ICT table.
1360                  * 2- dma RX frame.
1361                  * 3- update RX shared data to indicate last write index.
1362                  * 4- send interrupt.
1363                  * This could lead to RX race, driver could receive RX interrupt
1364                  * but the shared data changes does not reflect this;
1365                  * periodic interrupt will detect any dangling Rx activity.
1366                  */
1367
1368                 /* Disable periodic interrupt; we use it as just a one-shot. */
1369                 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1370                             CSR_INT_PERIODIC_DIS);
1371                 iwl_rx_handle(priv);
1372
1373                 /*
1374                  * Enable periodic interrupt in 8 msec only if we received
1375                  * real RX interrupt (instead of just periodic int), to catch
1376                  * any dangling Rx interrupt.  If it was just the periodic
1377                  * interrupt, there was no dangling Rx activity, and no need
1378                  * to extend the periodic interrupt; one-shot is enough.
1379                  */
1380                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1381                         iwl_write8(priv, CSR_INT_PERIODIC_REG,
1382                                     CSR_INT_PERIODIC_ENA);
1383
1384                 priv->isr_stats.rx++;
1385         }
1386
1387         /* This "Tx" DMA channel is used only for loading uCode */
1388         if (inta & CSR_INT_BIT_FH_TX) {
1389                 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
1390                 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1391                 priv->isr_stats.tx++;
1392                 handled |= CSR_INT_BIT_FH_TX;
1393                 /* Wake up uCode load routine, now that load is complete */
1394                 priv->ucode_write_complete = 1;
1395                 wake_up_interruptible(&priv->wait_command_queue);
1396         }
1397
1398         if (inta & ~handled) {
1399                 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1400                 priv->isr_stats.unhandled++;
1401         }
1402
1403         if (inta & ~(priv->inta_mask)) {
1404                 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1405                          inta & ~priv->inta_mask);
1406         }
1407
1408         /* Re-enable all interrupts */
1409         /* only Re-enable if disabled by irq */
1410         if (test_bit(STATUS_INT_ENABLED, &priv->status))
1411                 iwl_enable_interrupts(priv);
1412         /* Re-enable RF_KILL if it occurred */
1413         else if (handled & CSR_INT_BIT_RF_KILL)
1414                 iwl_enable_rfkill_int(priv);
1415 }
1416
1417 /* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
1418 #define ACK_CNT_RATIO (50)
1419 #define BA_TIMEOUT_CNT (5)
1420 #define BA_TIMEOUT_MAX (16)
1421
1422 /**
1423  * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
1424  *
1425  * When the ACK count ratio is low and aggregated BA timeout retries exceeding
1426  * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
1427  * operation state.
1428  */
1429 bool iwl_good_ack_health(struct iwl_priv *priv, struct iwl_rx_packet *pkt)
1430 {
1431         int actual_delta, expected_delta, ba_timeout_delta;
1432         struct statistics_tx *cur, *old;
1433
1434         if (priv->_agn.agg_tids_count)
1435                 return true;
1436
1437         if (iwl_bt_statistics(priv)) {
1438                 cur = &pkt->u.stats_bt.tx;
1439                 old = &priv->_agn.statistics_bt.tx;
1440         } else {
1441                 cur = &pkt->u.stats.tx;
1442                 old = &priv->_agn.statistics.tx;
1443         }
1444
1445         actual_delta = le32_to_cpu(cur->actual_ack_cnt) -
1446                        le32_to_cpu(old->actual_ack_cnt);
1447         expected_delta = le32_to_cpu(cur->expected_ack_cnt) -
1448                          le32_to_cpu(old->expected_ack_cnt);
1449
1450         /* Values should not be negative, but we do not trust the firmware */
1451         if (actual_delta <= 0 || expected_delta <= 0)
1452                 return true;
1453
1454         ba_timeout_delta = le32_to_cpu(cur->agg.ba_timeout) -
1455                            le32_to_cpu(old->agg.ba_timeout);
1456
1457         if ((actual_delta * 100 / expected_delta) < ACK_CNT_RATIO &&
1458             ba_timeout_delta > BA_TIMEOUT_CNT) {
1459                 IWL_DEBUG_RADIO(priv, "deltas: actual %d expected %d ba_timeout %d\n",
1460                                 actual_delta, expected_delta, ba_timeout_delta);
1461
1462 #ifdef CONFIG_IWLWIFI_DEBUGFS
1463                 /*
1464                  * This is ifdef'ed on DEBUGFS because otherwise the
1465                  * statistics aren't available. If DEBUGFS is set but
1466                  * DEBUG is not, these will just compile out.
1467                  */
1468                 IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta %d\n",
1469                                 priv->_agn.delta_statistics.tx.rx_detected_cnt);
1470                 IWL_DEBUG_RADIO(priv,
1471                                 "ack_or_ba_timeout_collision delta %d\n",
1472                                 priv->_agn.delta_statistics.tx.ack_or_ba_timeout_collision);
1473 #endif
1474
1475                 if (ba_timeout_delta >= BA_TIMEOUT_MAX)
1476                         return false;
1477         }
1478
1479         return true;
1480 }
1481
1482
1483 /*****************************************************************************
1484  *
1485  * sysfs attributes
1486  *
1487  *****************************************************************************/
1488
1489 #ifdef CONFIG_IWLWIFI_DEBUG
1490
1491 /*
1492  * The following adds a new attribute to the sysfs representation
1493  * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1494  * used for controlling the debug level.
1495  *
1496  * See the level definitions in iwl for details.
1497  *
1498  * The debug_level being managed using sysfs below is a per device debug
1499  * level that is used instead of the global debug level if it (the per
1500  * device debug level) is set.
1501  */
1502 static ssize_t show_debug_level(struct device *d,
1503                                 struct device_attribute *attr, char *buf)
1504 {
1505         struct iwl_priv *priv = dev_get_drvdata(d);
1506         return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1507 }
1508 static ssize_t store_debug_level(struct device *d,
1509                                 struct device_attribute *attr,
1510                                  const char *buf, size_t count)
1511 {
1512         struct iwl_priv *priv = dev_get_drvdata(d);
1513         unsigned long val;
1514         int ret;
1515
1516         ret = strict_strtoul(buf, 0, &val);
1517         if (ret)
1518                 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1519         else {
1520                 priv->debug_level = val;
1521                 if (iwl_alloc_traffic_mem(priv))
1522                         IWL_ERR(priv,
1523                                 "Not enough memory to generate traffic log\n");
1524         }
1525         return strnlen(buf, count);
1526 }
1527
1528 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1529                         show_debug_level, store_debug_level);
1530
1531
1532 #endif /* CONFIG_IWLWIFI_DEBUG */
1533
1534
1535 static ssize_t show_temperature(struct device *d,
1536                                 struct device_attribute *attr, char *buf)
1537 {
1538         struct iwl_priv *priv = dev_get_drvdata(d);
1539
1540         if (!iwl_is_alive(priv))
1541                 return -EAGAIN;
1542
1543         return sprintf(buf, "%d\n", priv->temperature);
1544 }
1545
1546 static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1547
1548 static ssize_t show_tx_power(struct device *d,
1549                              struct device_attribute *attr, char *buf)
1550 {
1551         struct iwl_priv *priv = dev_get_drvdata(d);
1552
1553         if (!iwl_is_ready_rf(priv))
1554                 return sprintf(buf, "off\n");
1555         else
1556                 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1557 }
1558
1559 static ssize_t store_tx_power(struct device *d,
1560                               struct device_attribute *attr,
1561                               const char *buf, size_t count)
1562 {
1563         struct iwl_priv *priv = dev_get_drvdata(d);
1564         unsigned long val;
1565         int ret;
1566
1567         ret = strict_strtoul(buf, 10, &val);
1568         if (ret)
1569                 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1570         else {
1571                 ret = iwl_set_tx_power(priv, val, false);
1572                 if (ret)
1573                         IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1574                                 ret);
1575                 else
1576                         ret = count;
1577         }
1578         return ret;
1579 }
1580
1581 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1582
1583 static struct attribute *iwl_sysfs_entries[] = {
1584         &dev_attr_temperature.attr,
1585         &dev_attr_tx_power.attr,
1586 #ifdef CONFIG_IWLWIFI_DEBUG
1587         &dev_attr_debug_level.attr,
1588 #endif
1589         NULL
1590 };
1591
1592 static struct attribute_group iwl_attribute_group = {
1593         .name = NULL,           /* put in device directory */
1594         .attrs = iwl_sysfs_entries,
1595 };
1596
1597 /******************************************************************************
1598  *
1599  * uCode download functions
1600  *
1601  ******************************************************************************/
1602
1603 static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
1604 {
1605         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1606         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1607         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1608         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1609         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1610         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
1611 }
1612
1613 static void iwl_nic_start(struct iwl_priv *priv)
1614 {
1615         /* Remove all resets to allow NIC to operate */
1616         iwl_write32(priv, CSR_RESET, 0);
1617 }
1618
1619 struct iwlagn_ucode_capabilities {
1620         u32 max_probe_length;
1621         u32 standard_phy_calibration_size;
1622         bool pan;
1623 };
1624
1625 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
1626 static int iwl_mac_setup_register(struct iwl_priv *priv,
1627                                   struct iwlagn_ucode_capabilities *capa);
1628
1629 #define UCODE_EXPERIMENTAL_INDEX        100
1630 #define UCODE_EXPERIMENTAL_TAG          "exp"
1631
1632 static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1633 {
1634         const char *name_pre = priv->cfg->fw_name_pre;
1635         char tag[8];
1636
1637         if (first) {
1638 #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1639                 priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1640                 strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1641         } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1642 #endif
1643                 priv->fw_index = priv->cfg->ucode_api_max;
1644                 sprintf(tag, "%d", priv->fw_index);
1645         } else {
1646                 priv->fw_index--;
1647                 sprintf(tag, "%d", priv->fw_index);
1648         }
1649
1650         if (priv->fw_index < priv->cfg->ucode_api_min) {
1651                 IWL_ERR(priv, "no suitable firmware found!\n");
1652                 return -ENOENT;
1653         }
1654
1655         sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
1656
1657         IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1658                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1659                                 ? "EXPERIMENTAL " : "",
1660                        priv->firmware_name);
1661
1662         return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1663                                        &priv->pci_dev->dev, GFP_KERNEL, priv,
1664                                        iwl_ucode_callback);
1665 }
1666
1667 struct iwlagn_firmware_pieces {
1668         const void *inst, *data, *init, *init_data, *boot;
1669         size_t inst_size, data_size, init_size, init_data_size, boot_size;
1670
1671         u32 build;
1672
1673         u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1674         u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
1675 };
1676
1677 static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1678                                        const struct firmware *ucode_raw,
1679                                        struct iwlagn_firmware_pieces *pieces)
1680 {
1681         struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1682         u32 api_ver, hdr_size;
1683         const u8 *src;
1684
1685         priv->ucode_ver = le32_to_cpu(ucode->ver);
1686         api_ver = IWL_UCODE_API(priv->ucode_ver);
1687
1688         switch (api_ver) {
1689         default:
1690                 /*
1691                  * 4965 doesn't revision the firmware file format
1692                  * along with the API version, it always uses v1
1693                  * file format.
1694                  */
1695                 if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) !=
1696                                 CSR_HW_REV_TYPE_4965) {
1697                         hdr_size = 28;
1698                         if (ucode_raw->size < hdr_size) {
1699                                 IWL_ERR(priv, "File size too small!\n");
1700                                 return -EINVAL;
1701                         }
1702                         pieces->build = le32_to_cpu(ucode->u.v2.build);
1703                         pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1704                         pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1705                         pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1706                         pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1707                         pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
1708                         src = ucode->u.v2.data;
1709                         break;
1710                 }
1711                 /* fall through for 4965 */
1712         case 0:
1713         case 1:
1714         case 2:
1715                 hdr_size = 24;
1716                 if (ucode_raw->size < hdr_size) {
1717                         IWL_ERR(priv, "File size too small!\n");
1718                         return -EINVAL;
1719                 }
1720                 pieces->build = 0;
1721                 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1722                 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1723                 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1724                 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1725                 pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
1726                 src = ucode->u.v1.data;
1727                 break;
1728         }
1729
1730         /* Verify size of file vs. image size info in file's header */
1731         if (ucode_raw->size != hdr_size + pieces->inst_size +
1732                                 pieces->data_size + pieces->init_size +
1733                                 pieces->init_data_size + pieces->boot_size) {
1734
1735                 IWL_ERR(priv,
1736                         "uCode file size %d does not match expected size\n",
1737                         (int)ucode_raw->size);
1738                 return -EINVAL;
1739         }
1740
1741         pieces->inst = src;
1742         src += pieces->inst_size;
1743         pieces->data = src;
1744         src += pieces->data_size;
1745         pieces->init = src;
1746         src += pieces->init_size;
1747         pieces->init_data = src;
1748         src += pieces->init_data_size;
1749         pieces->boot = src;
1750         src += pieces->boot_size;
1751
1752         return 0;
1753 }
1754
1755 static int iwlagn_wanted_ucode_alternative = 1;
1756
1757 static int iwlagn_load_firmware(struct iwl_priv *priv,
1758                                 const struct firmware *ucode_raw,
1759                                 struct iwlagn_firmware_pieces *pieces,
1760                                 struct iwlagn_ucode_capabilities *capa)
1761 {
1762         struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1763         struct iwl_ucode_tlv *tlv;
1764         size_t len = ucode_raw->size;
1765         const u8 *data;
1766         int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1767         u64 alternatives;
1768         u32 tlv_len;
1769         enum iwl_ucode_tlv_type tlv_type;
1770         const u8 *tlv_data;
1771
1772         if (len < sizeof(*ucode)) {
1773                 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
1774                 return -EINVAL;
1775         }
1776
1777         if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1778                 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1779                         le32_to_cpu(ucode->magic));
1780                 return -EINVAL;
1781         }
1782
1783         /*
1784          * Check which alternatives are present, and "downgrade"
1785          * when the chosen alternative is not present, warning
1786          * the user when that happens. Some files may not have
1787          * any alternatives, so don't warn in that case.
1788          */
1789         alternatives = le64_to_cpu(ucode->alternatives);
1790         tmp = wanted_alternative;
1791         if (wanted_alternative > 63)
1792                 wanted_alternative = 63;
1793         while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1794                 wanted_alternative--;
1795         if (wanted_alternative && wanted_alternative != tmp)
1796                 IWL_WARN(priv,
1797                          "uCode alternative %d not available, choosing %d\n",
1798                          tmp, wanted_alternative);
1799
1800         priv->ucode_ver = le32_to_cpu(ucode->ver);
1801         pieces->build = le32_to_cpu(ucode->build);
1802         data = ucode->data;
1803
1804         len -= sizeof(*ucode);
1805
1806         while (len >= sizeof(*tlv)) {
1807                 u16 tlv_alt;
1808
1809                 len -= sizeof(*tlv);
1810                 tlv = (void *)data;
1811
1812                 tlv_len = le32_to_cpu(tlv->length);
1813                 tlv_type = le16_to_cpu(tlv->type);
1814                 tlv_alt = le16_to_cpu(tlv->alternative);
1815                 tlv_data = tlv->data;
1816
1817                 if (len < tlv_len) {
1818                         IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1819                                 len, tlv_len);
1820                         return -EINVAL;
1821                 }
1822                 len -= ALIGN(tlv_len, 4);
1823                 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1824
1825                 /*
1826                  * Alternative 0 is always valid.
1827                  *
1828                  * Skip alternative TLVs that are not selected.
1829                  */
1830                 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1831                         continue;
1832
1833                 switch (tlv_type) {
1834                 case IWL_UCODE_TLV_INST:
1835                         pieces->inst = tlv_data;
1836                         pieces->inst_size = tlv_len;
1837                         break;
1838                 case IWL_UCODE_TLV_DATA:
1839                         pieces->data = tlv_data;
1840                         pieces->data_size = tlv_len;
1841                         break;
1842                 case IWL_UCODE_TLV_INIT:
1843                         pieces->init = tlv_data;
1844                         pieces->init_size = tlv_len;
1845                         break;
1846                 case IWL_UCODE_TLV_INIT_DATA:
1847                         pieces->init_data = tlv_data;
1848                         pieces->init_data_size = tlv_len;
1849                         break;
1850                 case IWL_UCODE_TLV_BOOT:
1851                         pieces->boot = tlv_data;
1852                         pieces->boot_size = tlv_len;
1853                         break;
1854                 case IWL_UCODE_TLV_PROBE_MAX_LEN:
1855                         if (tlv_len != sizeof(u32))
1856                                 goto invalid_tlv_len;
1857                         capa->max_probe_length =
1858                                         le32_to_cpup((__le32 *)tlv_data);
1859                         break;
1860                 case IWL_UCODE_TLV_PAN:
1861                         if (tlv_len)
1862                                 goto invalid_tlv_len;
1863                         capa->pan = true;
1864                         break;
1865                 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
1866                         if (tlv_len != sizeof(u32))
1867                                 goto invalid_tlv_len;
1868                         pieces->init_evtlog_ptr =
1869                                         le32_to_cpup((__le32 *)tlv_data);
1870                         break;
1871                 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
1872                         if (tlv_len != sizeof(u32))
1873                                 goto invalid_tlv_len;
1874                         pieces->init_evtlog_size =
1875                                         le32_to_cpup((__le32 *)tlv_data);
1876                         break;
1877                 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
1878                         if (tlv_len != sizeof(u32))
1879                                 goto invalid_tlv_len;
1880                         pieces->init_errlog_ptr =
1881                                         le32_to_cpup((__le32 *)tlv_data);
1882                         break;
1883                 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
1884                         if (tlv_len != sizeof(u32))
1885                                 goto invalid_tlv_len;
1886                         pieces->inst_evtlog_ptr =
1887                                         le32_to_cpup((__le32 *)tlv_data);
1888                         break;
1889                 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
1890                         if (tlv_len != sizeof(u32))
1891                                 goto invalid_tlv_len;
1892                         pieces->inst_evtlog_size =
1893                                         le32_to_cpup((__le32 *)tlv_data);
1894                         break;
1895                 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
1896                         if (tlv_len != sizeof(u32))
1897                                 goto invalid_tlv_len;
1898                         pieces->inst_errlog_ptr =
1899                                         le32_to_cpup((__le32 *)tlv_data);
1900                         break;
1901                 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
1902                         if (tlv_len)
1903                                 goto invalid_tlv_len;
1904                         priv->enhance_sensitivity_table = true;
1905                         break;
1906                 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
1907                         if (tlv_len != sizeof(u32))
1908                                 goto invalid_tlv_len;
1909                         capa->standard_phy_calibration_size =
1910                                         le32_to_cpup((__le32 *)tlv_data);
1911                         break;
1912                 default:
1913                         IWL_WARN(priv, "unknown TLV: %d\n", tlv_type);
1914                         break;
1915                 }
1916         }
1917
1918         if (len) {
1919                 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
1920                 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
1921                 return -EINVAL;
1922         }
1923
1924         return 0;
1925
1926  invalid_tlv_len:
1927         IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
1928         iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
1929
1930         return -EINVAL;
1931 }
1932
1933 /**
1934  * iwl_ucode_callback - callback when firmware was loaded
1935  *
1936  * If loaded successfully, copies the firmware into buffers
1937  * for the card to fetch (via DMA).
1938  */
1939 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
1940 {
1941         struct iwl_priv *priv = context;
1942         struct iwl_ucode_header *ucode;
1943         int err;
1944         struct iwlagn_firmware_pieces pieces;
1945         const unsigned int api_max = priv->cfg->ucode_api_max;
1946         const unsigned int api_min = priv->cfg->ucode_api_min;
1947         u32 api_ver;
1948         char buildstr[25];
1949         u32 build;
1950         struct iwlagn_ucode_capabilities ucode_capa = {
1951                 .max_probe_length = 200,
1952                 .standard_phy_calibration_size =
1953                         IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE,
1954         };
1955
1956         memset(&pieces, 0, sizeof(pieces));
1957
1958         if (!ucode_raw) {
1959                 if (priv->fw_index <= priv->cfg->ucode_api_max)
1960                         IWL_ERR(priv,
1961                                 "request for firmware file '%s' failed.\n",
1962                                 priv->firmware_name);
1963                 goto try_again;
1964         }
1965
1966         IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
1967                        priv->firmware_name, ucode_raw->size);
1968
1969         /* Make sure that we got at least the API version number */
1970         if (ucode_raw->size < 4) {
1971                 IWL_ERR(priv, "File size way too small!\n");
1972                 goto try_again;
1973         }
1974
1975         /* Data from ucode file:  header followed by uCode images */
1976         ucode = (struct iwl_ucode_header *)ucode_raw->data;
1977
1978         if (ucode->ver)
1979                 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
1980         else
1981                 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
1982                                            &ucode_capa);
1983
1984         if (err)
1985                 goto try_again;
1986
1987         api_ver = IWL_UCODE_API(priv->ucode_ver);
1988         build = pieces.build;
1989
1990         /*
1991          * api_ver should match the api version forming part of the
1992          * firmware filename ... but we don't check for that and only rely
1993          * on the API version read from firmware header from here on forward
1994          */
1995         /* no api version check required for experimental uCode */
1996         if (priv->fw_index != UCODE_EXPERIMENTAL_INDEX) {
1997                 if (api_ver < api_min || api_ver > api_max) {
1998                         IWL_ERR(priv,
1999                                 "Driver unable to support your firmware API. "
2000                                 "Driver supports v%u, firmware is v%u.\n",
2001                                 api_max, api_ver);
2002                         goto try_again;
2003                 }
2004
2005                 if (api_ver != api_max)
2006                         IWL_ERR(priv,
2007                                 "Firmware has old API version. Expected v%u, "
2008                                 "got v%u. New firmware can be obtained "
2009                                 "from http://www.intellinuxwireless.org.\n",
2010                                 api_max, api_ver);
2011         }
2012
2013         if (build)
2014                 sprintf(buildstr, " build %u%s", build,
2015                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
2016                                 ? " (EXP)" : "");
2017         else
2018                 buildstr[0] = '\0';
2019
2020         IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
2021                  IWL_UCODE_MAJOR(priv->ucode_ver),
2022                  IWL_UCODE_MINOR(priv->ucode_ver),
2023                  IWL_UCODE_API(priv->ucode_ver),
2024                  IWL_UCODE_SERIAL(priv->ucode_ver),
2025                  buildstr);
2026
2027         snprintf(priv->hw->wiphy->fw_version,
2028                  sizeof(priv->hw->wiphy->fw_version),
2029                  "%u.%u.%u.%u%s",
2030                  IWL_UCODE_MAJOR(priv->ucode_ver),
2031                  IWL_UCODE_MINOR(priv->ucode_ver),
2032                  IWL_UCODE_API(priv->ucode_ver),
2033                  IWL_UCODE_SERIAL(priv->ucode_ver),
2034                  buildstr);
2035
2036         /*
2037          * For any of the failures below (before allocating pci memory)
2038          * we will try to load a version with a smaller API -- maybe the
2039          * user just got a corrupted version of the latest API.
2040          */
2041
2042         IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
2043                        priv->ucode_ver);
2044         IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
2045                        pieces.inst_size);
2046         IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
2047                        pieces.data_size);
2048         IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
2049                        pieces.init_size);
2050         IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
2051                        pieces.init_data_size);
2052         IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
2053                        pieces.boot_size);
2054
2055         /* Verify that uCode images will fit in card's SRAM */
2056         if (pieces.inst_size > priv->hw_params.max_inst_size) {
2057                 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
2058                         pieces.inst_size);
2059                 goto try_again;
2060         }
2061
2062         if (pieces.data_size > priv->hw_params.max_data_size) {
2063                 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
2064                         pieces.data_size);
2065                 goto try_again;
2066         }
2067
2068         if (pieces.init_size > priv->hw_params.max_inst_size) {
2069                 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
2070                         pieces.init_size);
2071                 goto try_again;
2072         }
2073
2074         if (pieces.init_data_size > priv->hw_params.max_data_size) {
2075                 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
2076                         pieces.init_data_size);
2077                 goto try_again;
2078         }
2079
2080         if (pieces.boot_size > priv->hw_params.max_bsm_size) {
2081                 IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
2082                         pieces.boot_size);
2083                 goto try_again;
2084         }
2085
2086         /* Allocate ucode buffers for card's bus-master loading ... */
2087
2088         /* Runtime instructions and 2 copies of data:
2089          * 1) unmodified from disk
2090          * 2) backup cache for save/restore during power-downs */
2091         priv->ucode_code.len = pieces.inst_size;
2092         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
2093
2094         priv->ucode_data.len = pieces.data_size;
2095         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
2096
2097         priv->ucode_data_backup.len = pieces.data_size;
2098         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
2099
2100         if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2101             !priv->ucode_data_backup.v_addr)
2102                 goto err_pci_alloc;
2103
2104         /* Initialization instructions and data */
2105         if (pieces.init_size && pieces.init_data_size) {
2106                 priv->ucode_init.len = pieces.init_size;
2107                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
2108
2109                 priv->ucode_init_data.len = pieces.init_data_size;
2110                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
2111
2112                 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2113                         goto err_pci_alloc;
2114         }
2115
2116         /* Bootstrap (instructions only, no data) */
2117         if (pieces.boot_size) {
2118                 priv->ucode_boot.len = pieces.boot_size;
2119                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
2120
2121                 if (!priv->ucode_boot.v_addr)
2122                         goto err_pci_alloc;
2123         }
2124
2125         /* Now that we can no longer fail, copy information */
2126
2127         /*
2128          * The (size - 16) / 12 formula is based on the information recorded
2129          * for each event, which is of mode 1 (including timestamp) for all
2130          * new microcodes that include this information.
2131          */
2132         priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
2133         if (pieces.init_evtlog_size)
2134                 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
2135         else
2136                 priv->_agn.init_evtlog_size =
2137                         priv->cfg->base_params->max_event_log_size;
2138         priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
2139         priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
2140         if (pieces.inst_evtlog_size)
2141                 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
2142         else
2143                 priv->_agn.inst_evtlog_size =
2144                         priv->cfg->base_params->max_event_log_size;
2145         priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
2146
2147         if (ucode_capa.pan) {
2148                 priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
2149                 priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
2150         } else
2151                 priv->sta_key_max_num = STA_KEY_MAX_NUM;
2152
2153         /* Copy images into buffers for card's bus-master reads ... */
2154
2155         /* Runtime instructions (first block of data in file) */
2156         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
2157                         pieces.inst_size);
2158         memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
2159
2160         IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
2161                 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2162
2163         /*
2164          * Runtime data
2165          * NOTE:  Copy into backup buffer will be done in iwl_up()
2166          */
2167         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
2168                         pieces.data_size);
2169         memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
2170         memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
2171
2172         /* Initialization instructions */
2173         if (pieces.init_size) {
2174                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
2175                                 pieces.init_size);
2176                 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
2177         }
2178
2179         /* Initialization data */
2180         if (pieces.init_data_size) {
2181                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
2182                                pieces.init_data_size);
2183                 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
2184                        pieces.init_data_size);
2185         }
2186
2187         /* Bootstrap instructions */
2188         IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
2189                         pieces.boot_size);
2190         memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
2191
2192         /*
2193          * figure out the offset of chain noise reset and gain commands
2194          * base on the size of standard phy calibration commands table size
2195          */
2196         if (ucode_capa.standard_phy_calibration_size >
2197             IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
2198                 ucode_capa.standard_phy_calibration_size =
2199                         IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
2200
2201         priv->_agn.phy_calib_chain_noise_reset_cmd =
2202                 ucode_capa.standard_phy_calibration_size;
2203         priv->_agn.phy_calib_chain_noise_gain_cmd =
2204                 ucode_capa.standard_phy_calibration_size + 1;
2205
2206         /**************************************************
2207          * This is still part of probe() in a sense...
2208          *
2209          * 9. Setup and register with mac80211 and debugfs
2210          **************************************************/
2211         err = iwl_mac_setup_register(priv, &ucode_capa);
2212         if (err)
2213                 goto out_unbind;
2214
2215         err = iwl_dbgfs_register(priv, DRV_NAME);
2216         if (err)
2217                 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
2218
2219         err = sysfs_create_group(&priv->pci_dev->dev.kobj,
2220                                         &iwl_attribute_group);
2221         if (err) {
2222                 IWL_ERR(priv, "failed to create sysfs device attributes\n");
2223                 goto out_unbind;
2224         }
2225
2226         /* We have our copies now, allow OS release its copies */
2227         release_firmware(ucode_raw);
2228         complete(&priv->_agn.firmware_loading_complete);
2229         return;
2230
2231  try_again:
2232         /* try next, if any */
2233         if (iwl_request_firmware(priv, false))
2234                 goto out_unbind;
2235         release_firmware(ucode_raw);
2236         return;
2237
2238  err_pci_alloc:
2239         IWL_ERR(priv, "failed to allocate pci memory\n");
2240         iwl_dealloc_ucode_pci(priv);
2241  out_unbind:
2242         complete(&priv->_agn.firmware_loading_complete);
2243         device_release_driver(&priv->pci_dev->dev);
2244         release_firmware(ucode_raw);
2245 }
2246
2247 static const char *desc_lookup_text[] = {
2248         "OK",
2249         "FAIL",
2250         "BAD_PARAM",
2251         "BAD_CHECKSUM",
2252         "NMI_INTERRUPT_WDG",
2253         "SYSASSERT",
2254         "FATAL_ERROR",
2255         "BAD_COMMAND",
2256         "HW_ERROR_TUNE_LOCK",
2257         "HW_ERROR_TEMPERATURE",
2258         "ILLEGAL_CHAN_FREQ",
2259         "VCC_NOT_STABLE",
2260         "FH_ERROR",
2261         "NMI_INTERRUPT_HOST",
2262         "NMI_INTERRUPT_ACTION_PT",
2263         "NMI_INTERRUPT_UNKNOWN",
2264         "UCODE_VERSION_MISMATCH",
2265         "HW_ERROR_ABS_LOCK",
2266         "HW_ERROR_CAL_LOCK_FAIL",
2267         "NMI_INTERRUPT_INST_ACTION_PT",
2268         "NMI_INTERRUPT_DATA_ACTION_PT",
2269         "NMI_TRM_HW_ER",
2270         "NMI_INTERRUPT_TRM",
2271         "NMI_INTERRUPT_BREAK_POINT"
2272         "DEBUG_0",
2273         "DEBUG_1",
2274         "DEBUG_2",
2275         "DEBUG_3",
2276 };
2277
2278 static struct { char *name; u8 num; } advanced_lookup[] = {
2279         { "NMI_INTERRUPT_WDG", 0x34 },
2280         { "SYSASSERT", 0x35 },
2281         { "UCODE_VERSION_MISMATCH", 0x37 },
2282         { "BAD_COMMAND", 0x38 },
2283         { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
2284         { "FATAL_ERROR", 0x3D },
2285         { "NMI_TRM_HW_ERR", 0x46 },
2286         { "NMI_INTERRUPT_TRM", 0x4C },
2287         { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
2288         { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
2289         { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
2290         { "NMI_INTERRUPT_HOST", 0x66 },
2291         { "NMI_INTERRUPT_ACTION_PT", 0x7C },
2292         { "NMI_INTERRUPT_UNKNOWN", 0x84 },
2293         { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
2294         { "ADVANCED_SYSASSERT", 0 },
2295 };
2296
2297 static const char *desc_lookup(u32 num)
2298 {
2299         int i;
2300         int max = ARRAY_SIZE(desc_lookup_text);
2301
2302         if (num < max)
2303                 return desc_lookup_text[num];
2304
2305         max = ARRAY_SIZE(advanced_lookup) - 1;
2306         for (i = 0; i < max; i++) {
2307                 if (advanced_lookup[i].num == num)
2308                         break;;
2309         }
2310         return advanced_lookup[i].name;
2311 }
2312
2313 #define ERROR_START_OFFSET  (1 * sizeof(u32))
2314 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
2315
2316 void iwl_dump_nic_error_log(struct iwl_priv *priv)
2317 {
2318         u32 data2, line;
2319         u32 desc, time, count, base, data1;
2320         u32 blink1, blink2, ilink1, ilink2;
2321         u32 pc, hcmd;
2322
2323         if (priv->ucode_type == UCODE_INIT) {
2324                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
2325                 if (!base)
2326                         base = priv->_agn.init_errlog_ptr;
2327         } else {
2328                 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
2329                 if (!base)
2330                         base = priv->_agn.inst_errlog_ptr;
2331         }
2332
2333         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2334                 IWL_ERR(priv,
2335                         "Not valid error log pointer 0x%08X for %s uCode\n",
2336                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2337                 return;
2338         }
2339
2340         count = iwl_read_targ_mem(priv, base);
2341
2342         if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
2343                 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
2344                 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
2345                         priv->status, count);
2346         }
2347
2348         desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
2349         priv->isr_stats.err_code = desc;
2350         pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
2351         blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
2352         blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
2353         ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
2354         ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
2355         data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
2356         data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
2357         line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
2358         time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
2359         hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
2360
2361         trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
2362                                       blink1, blink2, ilink1, ilink2);
2363
2364         IWL_ERR(priv, "Desc                                  Time       "
2365                 "data1      data2      line\n");
2366         IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
2367                 desc_lookup(desc), desc, time, data1, data2, line);
2368         IWL_ERR(priv, "pc      blink1  blink2  ilink1  ilink2  hcmd\n");
2369         IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
2370                 pc, blink1, blink2, ilink1, ilink2, hcmd);
2371 }
2372
2373 #define EVENT_START_OFFSET  (4 * sizeof(u32))
2374
2375 /**
2376  * iwl_print_event_log - Dump error event log to syslog
2377  *
2378  */
2379 static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
2380                                u32 num_events, u32 mode,
2381                                int pos, char **buf, size_t bufsz)
2382 {
2383         u32 i;
2384         u32 base;       /* SRAM byte address of event log header */
2385         u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
2386         u32 ptr;        /* SRAM byte address of log data */
2387         u32 ev, time, data; /* event log data */
2388         unsigned long reg_flags;
2389
2390         if (num_events == 0)
2391                 return pos;
2392
2393         if (priv->ucode_type == UCODE_INIT) {
2394                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2395                 if (!base)
2396                         base = priv->_agn.init_evtlog_ptr;
2397         } else {
2398                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2399                 if (!base)
2400                         base = priv->_agn.inst_evtlog_ptr;
2401         }
2402
2403         if (mode == 0)
2404                 event_size = 2 * sizeof(u32);
2405         else
2406                 event_size = 3 * sizeof(u32);
2407
2408         ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
2409
2410         /* Make sure device is powered up for SRAM reads */
2411         spin_lock_irqsave(&priv->reg_lock, reg_flags);
2412         iwl_grab_nic_access(priv);
2413
2414         /* Set starting address; reads will auto-increment */
2415         _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
2416         rmb();
2417
2418         /* "time" is actually "data" for mode 0 (no timestamp).
2419         * place event id # at far right for easier visual parsing. */
2420         for (i = 0; i < num_events; i++) {
2421                 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2422                 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2423                 if (mode == 0) {
2424                         /* data, ev */
2425                         if (bufsz) {
2426                                 pos += scnprintf(*buf + pos, bufsz - pos,
2427                                                 "EVT_LOG:0x%08x:%04u\n",
2428                                                 time, ev);
2429                         } else {
2430                                 trace_iwlwifi_dev_ucode_event(priv, 0,
2431                                         time, ev);
2432                                 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
2433                                         time, ev);
2434                         }
2435                 } else {
2436                         data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2437                         if (bufsz) {
2438                                 pos += scnprintf(*buf + pos, bufsz - pos,
2439                                                 "EVT_LOGT:%010u:0x%08x:%04u\n",
2440                                                  time, data, ev);
2441                         } else {
2442                                 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
2443                                         time, data, ev);
2444                                 trace_iwlwifi_dev_ucode_event(priv, time,
2445                                         data, ev);
2446                         }
2447                 }
2448         }
2449
2450         /* Allow device to power down */
2451         iwl_release_nic_access(priv);
2452         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
2453         return pos;
2454 }
2455
2456 /**
2457  * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2458  */
2459 static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2460                                     u32 num_wraps, u32 next_entry,
2461                                     u32 size, u32 mode,
2462                                     int pos, char **buf, size_t bufsz)
2463 {
2464         /*
2465          * display the newest DEFAULT_LOG_ENTRIES entries
2466          * i.e the entries just before the next ont that uCode would fill.
2467          */
2468         if (num_wraps) {
2469                 if (next_entry < size) {
2470                         pos = iwl_print_event_log(priv,
2471                                                 capacity - (size - next_entry),
2472                                                 size - next_entry, mode,
2473                                                 pos, buf, bufsz);
2474                         pos = iwl_print_event_log(priv, 0,
2475                                                   next_entry, mode,
2476                                                   pos, buf, bufsz);
2477                 } else
2478                         pos = iwl_print_event_log(priv, next_entry - size,
2479                                                   size, mode, pos, buf, bufsz);
2480         } else {
2481                 if (next_entry < size) {
2482                         pos = iwl_print_event_log(priv, 0, next_entry,
2483                                                   mode, pos, buf, bufsz);
2484                 } else {
2485                         pos = iwl_print_event_log(priv, next_entry - size,
2486                                                   size, mode, pos, buf, bufsz);
2487                 }
2488         }
2489         return pos;
2490 }
2491
2492 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2493
2494 int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2495                             char **buf, bool display)
2496 {
2497         u32 base;       /* SRAM byte address of event log header */
2498         u32 capacity;   /* event log capacity in # entries */
2499         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
2500         u32 num_wraps;  /* # times uCode wrapped to top of log */
2501         u32 next_entry; /* index of next entry to be written by uCode */
2502         u32 size;       /* # entries that we'll print */
2503         u32 logsize;
2504         int pos = 0;
2505         size_t bufsz = 0;
2506
2507         if (priv->ucode_type == UCODE_INIT) {
2508                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2509                 logsize = priv->_agn.init_evtlog_size;
2510                 if (!base)
2511                         base = priv->_agn.init_evtlog_ptr;
2512         } else {
2513                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2514                 logsize = priv->_agn.inst_evtlog_size;
2515                 if (!base)
2516                         base = priv->_agn.inst_evtlog_ptr;
2517         }
2518
2519         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2520                 IWL_ERR(priv,
2521                         "Invalid event log pointer 0x%08X for %s uCode\n",
2522                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2523                 return -EINVAL;
2524         }
2525
2526         /* event log header */
2527         capacity = iwl_read_targ_mem(priv, base);
2528         mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2529         num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2530         next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2531
2532         if (capacity > logsize) {
2533                 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
2534                         capacity, logsize);
2535                 capacity = logsize;
2536         }
2537
2538         if (next_entry > logsize) {
2539                 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
2540                         next_entry, logsize);
2541                 next_entry = logsize;
2542         }
2543
2544         size = num_wraps ? capacity : next_entry;
2545
2546         /* bail out if nothing in log */
2547         if (size == 0) {
2548                 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
2549                 return pos;
2550         }
2551
2552         /* enable/disable bt channel inhibition */
2553         priv->bt_ch_announce = iwlagn_bt_ch_announce;
2554
2555 #ifdef CONFIG_IWLWIFI_DEBUG
2556         if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
2557                 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2558                         ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2559 #else
2560         size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2561                 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2562 #endif
2563         IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2564                 size);
2565
2566 #ifdef CONFIG_IWLWIFI_DEBUG
2567         if (display) {
2568                 if (full_log)
2569                         bufsz = capacity * 48;
2570                 else
2571                         bufsz = size * 48;
2572                 *buf = kmalloc(bufsz, GFP_KERNEL);
2573                 if (!*buf)
2574                         return -ENOMEM;
2575         }
2576         if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2577                 /*
2578                  * if uCode has wrapped back to top of log,
2579                  * start at the oldest entry,
2580                  * i.e the next one that uCode would fill.
2581                  */
2582                 if (num_wraps)
2583                         pos = iwl_print_event_log(priv, next_entry,
2584                                                 capacity - next_entry, mode,
2585                                                 pos, buf, bufsz);
2586                 /* (then/else) start at top of log */
2587                 pos = iwl_print_event_log(priv, 0,
2588                                           next_entry, mode, pos, buf, bufsz);
2589         } else
2590                 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2591                                                 next_entry, size, mode,
2592                                                 pos, buf, bufsz);
2593 #else
2594         pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2595                                         next_entry, size, mode,
2596                                         pos, buf, bufsz);
2597 #endif
2598         return pos;
2599 }
2600
2601 static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2602 {
2603         struct iwl_ct_kill_config cmd;
2604         struct iwl_ct_kill_throttling_config adv_cmd;
2605         unsigned long flags;
2606         int ret = 0;
2607
2608         spin_lock_irqsave(&priv->lock, flags);
2609         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2610                     CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2611         spin_unlock_irqrestore(&priv->lock, flags);
2612         priv->thermal_throttle.ct_kill_toggle = false;
2613
2614         if (priv->cfg->base_params->support_ct_kill_exit) {
2615                 adv_cmd.critical_temperature_enter =
2616                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2617                 adv_cmd.critical_temperature_exit =
2618                         cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2619
2620                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2621                                        sizeof(adv_cmd), &adv_cmd);
2622                 if (ret)
2623                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2624                 else
2625                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2626                                         "succeeded, "
2627                                         "critical temperature enter is %d,"
2628                                         "exit is %d\n",
2629                                        priv->hw_params.ct_kill_threshold,
2630                                        priv->hw_params.ct_kill_exit_threshold);
2631         } else {
2632                 cmd.critical_temperature_R =
2633                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2634
2635                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2636                                        sizeof(cmd), &cmd);
2637                 if (ret)
2638                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2639                 else
2640                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2641                                         "succeeded, "
2642                                         "critical temperature is %d\n",
2643                                         priv->hw_params.ct_kill_threshold);
2644         }
2645 }
2646
2647 static int iwlagn_send_calib_cfg_rt(struct iwl_priv *priv, u32 cfg)
2648 {
2649         struct iwl_calib_cfg_cmd calib_cfg_cmd;
2650         struct iwl_host_cmd cmd = {
2651                 .id = CALIBRATION_CFG_CMD,
2652                 .len = sizeof(struct iwl_calib_cfg_cmd),
2653                 .data = &calib_cfg_cmd,
2654         };
2655
2656         memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
2657         calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
2658         calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg);
2659
2660         return iwl_send_cmd(priv, &cmd);
2661 }
2662
2663
2664 /**
2665  * iwl_alive_start - called after REPLY_ALIVE notification received
2666  *                   from protocol/runtime uCode (initialization uCode's
2667  *                   Alive gets handled by iwl_init_alive_start()).
2668  */
2669 static void iwl_alive_start(struct iwl_priv *priv)
2670 {
2671         int ret = 0;
2672         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2673
2674         IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
2675
2676         /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2677          * This is a paranoid check, because we would not have gotten the
2678          * "runtime" alive if code weren't properly loaded.  */
2679         if (iwl_verify_ucode(priv)) {
2680                 /* Runtime instruction load was bad;
2681                  * take it all the way back down so we can try again */
2682                 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
2683                 goto restart;
2684         }
2685
2686         ret = priv->cfg->ops->lib->alive_notify(priv);
2687         if (ret) {
2688                 IWL_WARN(priv,
2689                         "Could not complete ALIVE transition [ntf]: %d\n", ret);
2690                 goto restart;
2691         }
2692
2693
2694         /* After the ALIVE response, we can send host commands to the uCode */
2695         set_bit(STATUS_ALIVE, &priv->status);
2696
2697         /* Enable watchdog to monitor the driver tx queues */
2698         iwl_setup_watchdog(priv);
2699
2700         if (iwl_is_rfkill(priv))
2701                 return;
2702
2703         /* download priority table before any calibration request */
2704         if (priv->cfg->bt_params &&
2705             priv->cfg->bt_params->advanced_bt_coexist) {
2706                 /* Configure Bluetooth device coexistence support */
2707                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
2708                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
2709                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
2710                 priv->cfg->ops->hcmd->send_bt_config(priv);
2711                 priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS;
2712                 iwlagn_send_prio_tbl(priv);
2713
2714                 /* FIXME: w/a to force change uCode BT state machine */
2715                 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
2716                         BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2717                 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE,
2718                         BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2719         }
2720         if (priv->hw_params.calib_rt_cfg)
2721                 iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg);
2722
2723         ieee80211_wake_queues(priv->hw);
2724
2725         priv->active_rate = IWL_RATES_MASK;
2726
2727         /* Configure Tx antenna selection based on H/W config */
2728         if (priv->cfg->ops->hcmd->set_tx_ant)
2729                 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2730
2731         if (iwl_is_associated_ctx(ctx)) {
2732                 struct iwl_rxon_cmd *active_rxon =
2733                                 (struct iwl_rxon_cmd *)&ctx->active;
2734                 /* apply any changes in staging */
2735                 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2736                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2737         } else {
2738                 struct iwl_rxon_context *tmp;
2739                 /* Initialize our rx_config data */
2740                 for_each_context(priv, tmp)
2741                         iwl_connection_init_rx_config(priv, tmp);
2742
2743                 if (priv->cfg->ops->hcmd->set_rxon_chain)
2744                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
2745         }
2746
2747         if (!priv->cfg->bt_params || (priv->cfg->bt_params &&
2748             !priv->cfg->bt_params->advanced_bt_coexist)) {
2749                 /*
2750                  * default is 2-wire BT coexexistence support
2751                  */
2752                 priv->cfg->ops->hcmd->send_bt_config(priv);
2753         }
2754
2755         iwl_reset_run_time_calib(priv);
2756
2757         set_bit(STATUS_READY, &priv->status);
2758
2759         /* Configure the adapter for unassociated operation */
2760         iwlcore_commit_rxon(priv, ctx);
2761
2762         /* At this point, the NIC is initialized and operational */
2763         iwl_rf_kill_ct_config(priv);
2764
2765         IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
2766         wake_up_interruptible(&priv->wait_command_queue);
2767
2768         iwl_power_update_mode(priv, true);
2769         IWL_DEBUG_INFO(priv, "Updated power mode\n");
2770
2771
2772         return;
2773
2774  restart:
2775         queue_work(priv->workqueue, &priv->restart);
2776 }
2777
2778 static void iwl_cancel_deferred_work(struct iwl_priv *priv);
2779
2780 static void __iwl_down(struct iwl_priv *priv)
2781 {
2782         unsigned long flags;
2783         int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
2784
2785         IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
2786
2787         iwl_scan_cancel_timeout(priv, 200);
2788
2789         exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
2790
2791         /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2792          * to prevent rearm timer */
2793         del_timer_sync(&priv->watchdog);
2794
2795         iwl_clear_ucode_stations(priv, NULL);
2796         iwl_dealloc_bcast_stations(priv);
2797         iwl_clear_driver_stations(priv);
2798
2799         /* reset BT coex data */
2800         priv->bt_status = 0;
2801         if (priv->cfg->bt_params)
2802                 priv->bt_traffic_load =
2803                          priv->cfg->bt_params->bt_init_traffic_load;
2804         else
2805                 priv->bt_traffic_load = 0;
2806         priv->bt_full_concurrent = false;
2807         priv->bt_ci_compliance = 0;
2808
2809         /* Unblock any waiting calls */
2810         wake_up_interruptible_all(&priv->wait_command_queue);
2811
2812         /* Wipe out the EXIT_PENDING status bit if we are not actually
2813          * exiting the module */
2814         if (!exit_pending)
2815                 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2816
2817         /* stop and reset the on-board processor */
2818         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2819
2820         /* tell the device to stop sending interrupts */
2821         spin_lock_irqsave(&priv->lock, flags);
2822         iwl_disable_interrupts(priv);
2823         spin_unlock_irqrestore(&priv->lock, flags);
2824         iwl_synchronize_irq(priv);
2825
2826         if (priv->mac80211_registered)
2827                 ieee80211_stop_queues(priv->hw);
2828
2829         /* If we have not previously called iwl_init() then
2830          * clear all bits but the RF Kill bit and return */
2831         if (!iwl_is_init(priv)) {
2832                 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2833                                         STATUS_RF_KILL_HW |
2834                                test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2835                                         STATUS_GEO_CONFIGURED |
2836                                test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2837                                         STATUS_EXIT_PENDING;
2838                 goto exit;
2839         }
2840
2841         /* ...otherwise clear out all the status bits but the RF Kill
2842          * bit and continue taking the NIC down. */
2843         priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2844                                 STATUS_RF_KILL_HW |
2845                         test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2846                                 STATUS_GEO_CONFIGURED |
2847                         test_bit(STATUS_FW_ERROR, &priv->status) <<
2848                                 STATUS_FW_ERROR |
2849                        test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2850                                 STATUS_EXIT_PENDING;
2851
2852         /* device going down, Stop using ICT table */
2853         if (priv->cfg->ops->lib->isr_ops.disable)
2854                 priv->cfg->ops->lib->isr_ops.disable(priv);
2855
2856         iwlagn_txq_ctx_stop(priv);
2857         iwlagn_rxq_stop(priv);
2858
2859         /* Power-down device's busmaster DMA clocks */
2860         iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2861         udelay(5);
2862
2863         /* Make sure (redundant) we've released our request to stay awake */
2864         iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2865
2866         /* Stop the device, and put it in low power state */
2867         iwl_apm_stop(priv);
2868
2869  exit:
2870         memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
2871
2872         dev_kfree_skb(priv->beacon_skb);
2873         priv->beacon_skb = NULL;
2874
2875         /* clear out any free frames */
2876         iwl_clear_free_frames(priv);
2877 }
2878
2879 static void iwl_down(struct iwl_priv *priv)
2880 {
2881         mutex_lock(&priv->mutex);
2882         __iwl_down(priv);
2883         mutex_unlock(&priv->mutex);
2884
2885         iwl_cancel_deferred_work(priv);
2886 }
2887
2888 #define HW_READY_TIMEOUT (50)
2889
2890 static int iwl_set_hw_ready(struct iwl_priv *priv)
2891 {
2892         int ret = 0;
2893
2894         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2895                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2896
2897         /* See if we got it */
2898         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2899                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2900                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2901                                 HW_READY_TIMEOUT);
2902         if (ret != -ETIMEDOUT)
2903                 priv->hw_ready = true;
2904         else
2905                 priv->hw_ready = false;
2906
2907         IWL_DEBUG_INFO(priv, "hardware %s\n",
2908                       (priv->hw_ready == 1) ? "ready" : "not ready");
2909         return ret;
2910 }
2911
2912 static int iwl_prepare_card_hw(struct iwl_priv *priv)
2913 {
2914         int ret = 0;
2915
2916         IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
2917
2918         ret = iwl_set_hw_ready(priv);
2919         if (priv->hw_ready)
2920                 return ret;
2921
2922         /* If HW is not ready, prepare the conditions to check again */
2923         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2924                         CSR_HW_IF_CONFIG_REG_PREPARE);
2925
2926         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2927                         ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2928                         CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2929
2930         /* HW should be ready by now, check again. */
2931         if (ret != -ETIMEDOUT)
2932                 iwl_set_hw_ready(priv);
2933
2934         return ret;
2935 }
2936
2937 #define MAX_HW_RESTARTS 5
2938
2939 static int __iwl_up(struct iwl_priv *priv)
2940 {
2941         struct iwl_rxon_context *ctx;
2942         int i;
2943         int ret;
2944
2945         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2946                 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
2947                 return -EIO;
2948         }
2949
2950         if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
2951                 IWL_ERR(priv, "ucode not available for device bringup\n");
2952                 return -EIO;
2953         }
2954
2955         for_each_context(priv, ctx) {
2956                 ret = iwlagn_alloc_bcast_station(priv, ctx);
2957                 if (ret) {
2958                         iwl_dealloc_bcast_stations(priv);
2959                         return ret;
2960                 }
2961         }
2962
2963         iwl_prepare_card_hw(priv);
2964
2965         if (!priv->hw_ready) {
2966                 IWL_WARN(priv, "Exit HW not ready\n");
2967                 return -EIO;
2968         }
2969
2970         /* If platform's RF_KILL switch is NOT set to KILL */
2971         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2972                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2973         else
2974                 set_bit(STATUS_RF_KILL_HW, &priv->status);
2975
2976         if (iwl_is_rfkill(priv)) {
2977                 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2978
2979                 iwl_enable_interrupts(priv);
2980                 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
2981                 return 0;
2982         }
2983
2984         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2985
2986         /* must be initialised before iwl_hw_nic_init */
2987         if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
2988                 priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
2989         else
2990                 priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
2991
2992         ret = iwlagn_hw_nic_init(priv);
2993         if (ret) {
2994                 IWL_ERR(priv, "Unable to init nic\n");
2995                 return ret;
2996         }
2997
2998         /* make sure rfkill handshake bits are cleared */
2999         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
3000         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
3001                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3002
3003         /* clear (again), then enable host interrupts */
3004         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3005         iwl_enable_interrupts(priv);
3006
3007         /* really make sure rfkill handshake bits are cleared */
3008         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
3009         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
3010
3011         /* Copy original ucode data image from disk into backup cache.
3012          * This will be used to initialize the on-board processor's
3013          * data SRAM for a clean start when the runtime program first loads. */
3014         memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
3015                priv->ucode_data.len);
3016
3017         for (i = 0; i < MAX_HW_RESTARTS; i++) {
3018
3019                 /* load bootstrap state machine,
3020                  * load bootstrap program into processor's memory,
3021                  * prepare to load the "initialize" uCode */
3022                 ret = priv->cfg->ops->lib->load_ucode(priv);
3023
3024                 if (ret) {
3025                         IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
3026                                 ret);
3027                         continue;
3028                 }
3029
3030                 /* start card; "initialize" will load runtime ucode */
3031                 iwl_nic_start(priv);
3032
3033                 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
3034
3035                 return 0;
3036         }
3037
3038         set_bit(STATUS_EXIT_PENDING, &priv->status);
3039         __iwl_down(priv);
3040         clear_bit(STATUS_EXIT_PENDING, &priv->status);
3041
3042         /* tried to restart and config the device for as long as our
3043          * patience could withstand */
3044         IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
3045         return -EIO;
3046 }
3047
3048
3049 /*****************************************************************************
3050  *
3051  * Workqueue callbacks
3052  *
3053  *****************************************************************************/
3054
3055 static void iwl_bg_init_alive_start(struct work_struct *data)
3056 {
3057         struct iwl_priv *priv =
3058             container_of(data, struct iwl_priv, init_alive_start.work);
3059
3060         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3061                 return;
3062
3063         mutex_lock(&priv->mutex);
3064         priv->cfg->ops->lib->init_alive_start(priv);
3065         mutex_unlock(&priv->mutex);
3066 }
3067
3068 static void iwl_bg_alive_start(struct work_struct *data)
3069 {
3070         struct iwl_priv *priv =
3071             container_of(data, struct iwl_priv, alive_start.work);
3072
3073         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3074                 return;
3075
3076         /* enable dram interrupt */
3077         if (priv->cfg->ops->lib->isr_ops.reset)
3078                 priv->cfg->ops->lib->isr_ops.reset(priv);
3079
3080         mutex_lock(&priv->mutex);
3081         iwl_alive_start(priv);
3082         mutex_unlock(&priv->mutex);
3083 }
3084
3085 static void iwl_bg_run_time_calib_work(struct work_struct *work)
3086 {
3087         struct iwl_priv *priv = container_of(work, struct iwl_priv,
3088                         run_time_calib_work);
3089
3090         mutex_lock(&priv->mutex);
3091
3092         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3093             test_bit(STATUS_SCANNING, &priv->status)) {
3094                 mutex_unlock(&priv->mutex);
3095                 return;
3096         }
3097
3098         if (priv->start_calib) {
3099                 if (iwl_bt_statistics(priv)) {
3100                         iwl_chain_noise_calibration(priv,
3101                                         (void *)&priv->_agn.statistics_bt);
3102                         iwl_sensitivity_calibration(priv,
3103                                         (void *)&priv->_agn.statistics_bt);
3104                 } else {
3105                         iwl_chain_noise_calibration(priv,
3106                                         (void *)&priv->_agn.statistics);
3107                         iwl_sensitivity_calibration(priv,
3108                                         (void *)&priv->_agn.statistics);
3109                 }
3110         }
3111
3112         mutex_unlock(&priv->mutex);
3113 }
3114
3115 static void iwl_bg_restart(struct work_struct *data)
3116 {
3117         struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
3118
3119         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3120                 return;
3121
3122         if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
3123                 struct iwl_rxon_context *ctx;
3124                 bool bt_full_concurrent;
3125                 u8 bt_ci_compliance;
3126                 u8 bt_load;
3127                 u8 bt_status;
3128
3129                 mutex_lock(&priv->mutex);
3130                 for_each_context(priv, ctx)
3131                         ctx->vif = NULL;
3132                 priv->is_open = 0;
3133
3134                 /*
3135                  * __iwl_down() will clear the BT status variables,
3136                  * which is correct, but when we restart we really
3137                  * want to keep them so restore them afterwards.
3138                  *
3139                  * The restart process will later pick them up and
3140                  * re-configure the hw when we reconfigure the BT
3141                  * command.
3142                  */
3143                 bt_full_concurrent = priv->bt_full_concurrent;
3144                 bt_ci_compliance = priv->bt_ci_compliance;
3145                 bt_load = priv->bt_traffic_load;
3146                 bt_status = priv->bt_status;
3147
3148                 __iwl_down(priv);
3149
3150                 priv->bt_full_concurrent = bt_full_concurrent;
3151                 priv->bt_ci_compliance = bt_ci_compliance;
3152                 priv->bt_traffic_load = bt_load;
3153                 priv->bt_status = bt_status;
3154
3155                 mutex_unlock(&priv->mutex);
3156                 iwl_cancel_deferred_work(priv);
3157                 ieee80211_restart_hw(priv->hw);
3158         } else {
3159                 iwl_down(priv);
3160
3161                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3162                         return;
3163
3164                 mutex_lock(&priv->mutex);
3165                 __iwl_up(priv);
3166                 mutex_unlock(&priv->mutex);
3167         }
3168 }
3169
3170 static void iwl_bg_rx_replenish(struct work_struct *data)
3171 {
3172         struct iwl_priv *priv =
3173             container_of(data, struct iwl_priv, rx_replenish);
3174
3175         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3176                 return;
3177
3178         mutex_lock(&priv->mutex);
3179         iwlagn_rx_replenish(priv);
3180         mutex_unlock(&priv->mutex);
3181 }
3182
3183 /*****************************************************************************
3184  *
3185  * mac80211 entry point functions
3186  *
3187  *****************************************************************************/
3188
3189 #define UCODE_READY_TIMEOUT     (4 * HZ)
3190
3191 /*
3192  * Not a mac80211 entry point function, but it fits in with all the
3193  * other mac80211 functions grouped here.
3194  */
3195 static int iwl_mac_setup_register(struct iwl_priv *priv,
3196                                   struct iwlagn_ucode_capabilities *capa)
3197 {
3198         int ret;
3199         struct ieee80211_hw *hw = priv->hw;
3200         struct iwl_rxon_context *ctx;
3201
3202         hw->rate_control_algorithm = "iwl-agn-rs";
3203
3204         /* Tell mac80211 our characteristics */
3205         hw->flags = IEEE80211_HW_SIGNAL_DBM |
3206                     IEEE80211_HW_AMPDU_AGGREGATION |
3207                     IEEE80211_HW_NEED_DTIM_PERIOD |
3208                     IEEE80211_HW_SPECTRUM_MGMT |
3209                     IEEE80211_HW_REPORTS_TX_ACK_STATUS;
3210
3211         hw->max_tx_aggregation_subframes = LINK_QUAL_AGG_FRAME_LIMIT_DEF;
3212
3213         if (!priv->cfg->base_params->broken_powersave)
3214                 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
3215                              IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
3216
3217         if (priv->cfg->sku & IWL_SKU_N)
3218                 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
3219                              IEEE80211_HW_SUPPORTS_STATIC_SMPS;
3220
3221         hw->sta_data_size = sizeof(struct iwl_station_priv);
3222         hw->vif_data_size = sizeof(struct iwl_vif_priv);
3223
3224         for_each_context(priv, ctx) {
3225                 hw->wiphy->interface_modes |= ctx->interface_modes;
3226                 hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
3227         }
3228
3229         hw->wiphy->max_remain_on_channel_duration = 1000;
3230
3231         hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
3232                             WIPHY_FLAG_DISABLE_BEACON_HINTS |
3233                             WIPHY_FLAG_IBSS_RSN;
3234
3235         /*
3236          * For now, disable PS by default because it affects
3237          * RX performance significantly.
3238          */
3239         hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3240
3241         hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
3242         /* we create the 802.11 header and a zero-length SSID element */
3243         hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
3244
3245         /* Default value; 4 EDCA QOS priorities */
3246         hw->queues = 4;
3247
3248         hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
3249
3250         if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3251                 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3252                         &priv->bands[IEEE80211_BAND_2GHZ];
3253         if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3254                 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3255                         &priv->bands[IEEE80211_BAND_5GHZ];
3256
3257         iwl_leds_init(priv);
3258
3259         ret = ieee80211_register_hw(priv->hw);
3260         if (ret) {
3261                 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3262                 return ret;
3263         }
3264         priv->mac80211_registered = 1;
3265
3266         return 0;
3267 }
3268
3269
3270 int iwlagn_mac_start(struct ieee80211_hw *hw)
3271 {
3272         struct iwl_priv *priv = hw->priv;
3273         int ret;
3274
3275         IWL_DEBUG_MAC80211(priv, "enter\n");
3276
3277         /* we should be verifying the device is ready to be opened */
3278         mutex_lock(&priv->mutex);
3279         ret = __iwl_up(priv);
3280         mutex_unlock(&priv->mutex);
3281
3282         if (ret)
3283                 return ret;
3284
3285         if (iwl_is_rfkill(priv))
3286                 goto out;
3287
3288         IWL_DEBUG_INFO(priv, "Start UP work done.\n");
3289
3290         /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
3291          * mac80211 will not be run successfully. */
3292         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3293                         test_bit(STATUS_READY, &priv->status),
3294                         UCODE_READY_TIMEOUT);
3295         if (!ret) {
3296                 if (!test_bit(STATUS_READY, &priv->status)) {
3297                         IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
3298                                 jiffies_to_msecs(UCODE_READY_TIMEOUT));
3299                         return -ETIMEDOUT;
3300                 }
3301         }
3302
3303         iwlagn_led_enable(priv);
3304
3305 out:
3306         priv->is_open = 1;
3307         IWL_DEBUG_MAC80211(priv, "leave\n");
3308         return 0;
3309 }
3310
3311 void iwlagn_mac_stop(struct ieee80211_hw *hw)
3312 {
3313         struct iwl_priv *priv = hw->priv;
3314
3315         IWL_DEBUG_MAC80211(priv, "enter\n");
3316
3317         if (!priv->is_open)
3318                 return;
3319
3320         priv->is_open = 0;
3321
3322         iwl_down(priv);
3323
3324         flush_workqueue(priv->workqueue);
3325
3326         /* User space software may expect getting rfkill changes
3327          * even if interface is down */
3328         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3329         iwl_enable_rfkill_int(priv);
3330
3331         IWL_DEBUG_MAC80211(priv, "leave\n");
3332 }
3333
3334 int iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
3335 {
3336         struct iwl_priv *priv = hw->priv;
3337
3338         IWL_DEBUG_MACDUMP(priv, "enter\n");
3339
3340         IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
3341                      ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
3342
3343         if (iwlagn_tx_skb(priv, skb))
3344                 dev_kfree_skb_any(skb);
3345
3346         IWL_DEBUG_MACDUMP(priv, "leave\n");
3347         return NETDEV_TX_OK;
3348 }
3349
3350 void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw,
3351                                 struct ieee80211_vif *vif,
3352                                 struct ieee80211_key_conf *keyconf,
3353                                 struct ieee80211_sta *sta,
3354                                 u32 iv32, u16 *phase1key)
3355 {
3356         struct iwl_priv *priv = hw->priv;
3357         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3358
3359         IWL_DEBUG_MAC80211(priv, "enter\n");
3360
3361         iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
3362                             iv32, phase1key);
3363
3364         IWL_DEBUG_MAC80211(priv, "leave\n");
3365 }
3366
3367 int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3368                        struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3369                        struct ieee80211_key_conf *key)
3370 {
3371         struct iwl_priv *priv = hw->priv;
3372         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3373         struct iwl_rxon_context *ctx = vif_priv->ctx;
3374         int ret;
3375         u8 sta_id;
3376         bool is_default_wep_key = false;
3377
3378         IWL_DEBUG_MAC80211(priv, "enter\n");
3379
3380         if (priv->cfg->mod_params->sw_crypto) {
3381                 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
3382                 return -EOPNOTSUPP;
3383         }
3384
3385         /*
3386          * To support IBSS RSN, don't program group keys in IBSS, the
3387          * hardware will then not attempt to decrypt the frames.
3388          */
3389         if (vif->type == NL80211_IFTYPE_ADHOC &&
3390             !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
3391                 return -EOPNOTSUPP;
3392
3393         sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
3394         if (sta_id == IWL_INVALID_STATION)
3395                 return -EINVAL;
3396
3397         mutex_lock(&priv->mutex);
3398         iwl_scan_cancel_timeout(priv, 100);
3399
3400         /*
3401          * If we are getting WEP group key and we didn't receive any key mapping
3402          * so far, we are in legacy wep mode (group key only), otherwise we are
3403          * in 1X mode.
3404          * In legacy wep mode, we use another host command to the uCode.
3405          */
3406         if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
3407              key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
3408             !sta) {
3409                 if (cmd == SET_KEY)
3410                         is_default_wep_key = !ctx->key_mapping_keys;
3411                 else
3412                         is_default_wep_key =
3413                                         (key->hw_key_idx == HW_KEY_DEFAULT);
3414         }
3415
3416         switch (cmd) {
3417         case SET_KEY:
3418                 if (is_default_wep_key)
3419                         ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
3420                 else
3421                         ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
3422                                                   key, sta_id);
3423
3424                 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
3425                 break;
3426         case DISABLE_KEY:
3427                 if (is_default_wep_key)
3428                         ret = iwl_remove_default_wep_key(priv, ctx, key);
3429                 else
3430                         ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
3431
3432                 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
3433                 break;
3434         default:
3435                 ret = -EINVAL;
3436         }
3437
3438         mutex_unlock(&priv->mutex);
3439         IWL_DEBUG_MAC80211(priv, "leave\n");
3440
3441         return ret;
3442 }
3443
3444 int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw,
3445                             struct ieee80211_vif *vif,
3446                             enum ieee80211_ampdu_mlme_action action,
3447                             struct ieee80211_sta *sta, u16 tid, u16 *ssn,
3448                             u8 buf_size)
3449 {
3450         struct iwl_priv *priv = hw->priv;
3451         int ret = -EINVAL;
3452         struct iwl_station_priv *sta_priv = (void *) sta->drv_priv;
3453
3454         IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
3455                      sta->addr, tid);
3456
3457         if (!(priv->cfg->sku & IWL_SKU_N))
3458                 return -EACCES;
3459
3460         mutex_lock(&priv->mutex);
3461
3462         switch (action) {
3463         case IEEE80211_AMPDU_RX_START:
3464                 IWL_DEBUG_HT(priv, "start Rx\n");
3465                 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
3466                 break;
3467         case IEEE80211_AMPDU_RX_STOP:
3468                 IWL_DEBUG_HT(priv, "stop Rx\n");
3469                 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
3470                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3471                         ret = 0;
3472                 break;
3473         case IEEE80211_AMPDU_TX_START:
3474                 IWL_DEBUG_HT(priv, "start Tx\n");
3475                 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
3476                 if (ret == 0) {
3477                         priv->_agn.agg_tids_count++;
3478                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3479                                      priv->_agn.agg_tids_count);
3480                 }
3481                 break;
3482         case IEEE80211_AMPDU_TX_STOP:
3483                 IWL_DEBUG_HT(priv, "stop Tx\n");
3484                 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
3485                 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3486                         priv->_agn.agg_tids_count--;
3487                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3488                                      priv->_agn.agg_tids_count);
3489                 }
3490                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3491                         ret = 0;
3492                 if (priv->cfg->ht_params &&
3493                     priv->cfg->ht_params->use_rts_for_aggregation) {
3494                         struct iwl_station_priv *sta_priv =
3495                                 (void *) sta->drv_priv;
3496                         /*
3497                          * switch off RTS/CTS if it was previously enabled
3498                          */
3499
3500                         sta_priv->lq_sta.lq.general_params.flags &=
3501                                 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3502                         iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3503                                         &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3504                 }
3505                 break;
3506         case IEEE80211_AMPDU_TX_OPERATIONAL:
3507                 /*
3508                  * If the limit is 0, then it wasn't initialised yet,
3509                  * use the default. We can do that since we take the
3510                  * minimum below, and we don't want to go above our
3511                  * default due to hardware restrictions.
3512                  */
3513                 if (sta_priv->max_agg_bufsize == 0)
3514                         sta_priv->max_agg_bufsize =
3515                                 LINK_QUAL_AGG_FRAME_LIMIT_DEF;
3516
3517                 /*
3518                  * Even though in theory the peer could have different
3519                  * aggregation reorder buffer sizes for different sessions,
3520                  * our ucode doesn't allow for that and has a global limit
3521                  * for each station. Therefore, use the minimum of all the
3522                  * aggregation sessions and our default value.
3523                  */
3524                 sta_priv->max_agg_bufsize =
3525                         min(sta_priv->max_agg_bufsize, buf_size);
3526
3527                 if (priv->cfg->ht_params &&
3528                     priv->cfg->ht_params->use_rts_for_aggregation) {
3529                         /*
3530                          * switch to RTS/CTS if it is the prefer protection
3531                          * method for HT traffic
3532                          */
3533
3534                         sta_priv->lq_sta.lq.general_params.flags |=
3535                                 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3536                 }
3537
3538                 sta_priv->lq_sta.lq.agg_params.agg_frame_cnt_limit =
3539                         sta_priv->max_agg_bufsize;
3540
3541                 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3542                                 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3543                 ret = 0;
3544                 break;
3545         }
3546         mutex_unlock(&priv->mutex);
3547
3548         return ret;
3549 }
3550
3551 int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3552                        struct ieee80211_vif *vif,
3553                        struct ieee80211_sta *sta)
3554 {
3555         struct iwl_priv *priv = hw->priv;
3556         struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3557         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3558         bool is_ap = vif->type == NL80211_IFTYPE_STATION;
3559         int ret;
3560         u8 sta_id;
3561
3562         IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3563                         sta->addr);
3564         mutex_lock(&priv->mutex);
3565         IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3566                         sta->addr);
3567         sta_priv->common.sta_id = IWL_INVALID_STATION;
3568
3569         atomic_set(&sta_priv->pending_frames, 0);
3570         if (vif->type == NL80211_IFTYPE_AP)
3571                 sta_priv->client = true;
3572
3573         ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
3574                                      is_ap, sta, &sta_id);
3575         if (ret) {
3576                 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3577                         sta->addr, ret);
3578                 /* Should we return success if return code is EEXIST ? */
3579                 mutex_unlock(&priv->mutex);
3580                 return ret;
3581         }
3582
3583         sta_priv->common.sta_id = sta_id;
3584
3585         /* Initialize rate scaling */
3586         IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
3587                        sta->addr);
3588         iwl_rs_rate_init(priv, sta, sta_id);
3589         mutex_unlock(&priv->mutex);
3590
3591         return 0;
3592 }
3593
3594 void iwlagn_mac_channel_switch(struct ieee80211_hw *hw,
3595                                struct ieee80211_channel_switch *ch_switch)
3596 {
3597         struct iwl_priv *priv = hw->priv;
3598         const struct iwl_channel_info *ch_info;
3599         struct ieee80211_conf *conf = &hw->conf;
3600         struct ieee80211_channel *channel = ch_switch->channel;
3601         struct iwl_ht_config *ht_conf = &priv->current_ht_config;
3602         /*
3603          * MULTI-FIXME
3604          * When we add support for multiple interfaces, we need to
3605          * revisit this. The channel switch command in the device
3606          * only affects the BSS context, but what does that really
3607          * mean? And what if we get a CSA on the second interface?
3608          * This needs a lot of work.
3609          */
3610         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
3611         u16 ch;
3612         unsigned long flags = 0;
3613
3614         IWL_DEBUG_MAC80211(priv, "enter\n");
3615
3616         if (iwl_is_rfkill(priv))
3617                 goto out_exit;
3618
3619         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3620             test_bit(STATUS_SCANNING, &priv->status))
3621                 goto out_exit;
3622
3623         if (!iwl_is_associated_ctx(ctx))
3624                 goto out_exit;
3625
3626         /* channel switch in progress */
3627         if (priv->switch_rxon.switch_in_progress == true)
3628                 goto out_exit;
3629
3630         mutex_lock(&priv->mutex);
3631         if (priv->cfg->ops->lib->set_channel_switch) {
3632
3633                 ch = channel->hw_value;
3634                 if (le16_to_cpu(ctx->active.channel) != ch) {
3635                         ch_info = iwl_get_channel_info(priv,
3636                                                        channel->band,
3637                                                        ch);
3638                         if (!is_channel_valid(ch_info)) {
3639                                 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3640                                 goto out;
3641                         }
3642                         spin_lock_irqsave(&priv->lock, flags);
3643
3644                         priv->current_ht_config.smps = conf->smps_mode;
3645
3646                         /* Configure HT40 channels */
3647                         ctx->ht.enabled = conf_is_ht(conf);
3648                         if (ctx->ht.enabled) {
3649                                 if (conf_is_ht40_minus(conf)) {
3650                                         ctx->ht.extension_chan_offset =
3651                                                 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
3652                                         ctx->ht.is_40mhz = true;
3653                                 } else if (conf_is_ht40_plus(conf)) {
3654                                         ctx->ht.extension_chan_offset =
3655                                                 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
3656                                         ctx->ht.is_40mhz = true;
3657                                 } else {
3658                                         ctx->ht.extension_chan_offset =
3659                                                 IEEE80211_HT_PARAM_CHA_SEC_NONE;
3660                                         ctx->ht.is_40mhz = false;
3661                                 }
3662                         } else
3663                                 ctx->ht.is_40mhz = false;
3664
3665                         if ((le16_to_cpu(ctx->staging.channel) != ch))
3666                                 ctx->staging.flags = 0;
3667
3668                         iwl_set_rxon_channel(priv, channel, ctx);
3669                         iwl_set_rxon_ht(priv, ht_conf);
3670                         iwl_set_flags_for_band(priv, ctx, channel->band,
3671                                                ctx->vif);
3672                         spin_unlock_irqrestore(&priv->lock, flags);
3673
3674                         iwl_set_rate(priv);
3675                         /*
3676                          * at this point, staging_rxon has the
3677                          * configuration for channel switch
3678                          */
3679                         if (priv->cfg->ops->lib->set_channel_switch(priv,
3680                                                                     ch_switch))
3681                                 priv->switch_rxon.switch_in_progress = false;
3682                 }
3683         }
3684 out:
3685         mutex_unlock(&priv->mutex);
3686 out_exit:
3687         if (!priv->switch_rxon.switch_in_progress)
3688                 ieee80211_chswitch_done(ctx->vif, false);
3689         IWL_DEBUG_MAC80211(priv, "leave\n");
3690 }
3691
3692 void iwlagn_configure_filter(struct ieee80211_hw *hw,
3693                              unsigned int changed_flags,
3694                              unsigned int *total_flags,
3695                              u64 multicast)
3696 {
3697         struct iwl_priv *priv = hw->priv;
3698         __le32 filter_or = 0, filter_nand = 0;
3699         struct iwl_rxon_context *ctx;
3700
3701 #define CHK(test, flag) do { \
3702         if (*total_flags & (test))              \
3703                 filter_or |= (flag);            \
3704         else                                    \
3705                 filter_nand |= (flag);          \
3706         } while (0)
3707
3708         IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3709                         changed_flags, *total_flags);
3710
3711         CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3712         /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
3713         CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
3714         CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3715
3716 #undef CHK
3717
3718         mutex_lock(&priv->mutex);
3719
3720         for_each_context(priv, ctx) {
3721                 ctx->staging.filter_flags &= ~filter_nand;
3722                 ctx->staging.filter_flags |= filter_or;
3723
3724                 /*
3725                  * Not committing directly because hardware can perform a scan,
3726                  * but we'll eventually commit the filter flags change anyway.
3727                  */
3728         }
3729
3730         mutex_unlock(&priv->mutex);
3731
3732         /*
3733          * Receiving all multicast frames is always enabled by the
3734          * default flags setup in iwl_connection_init_rx_config()
3735          * since we currently do not support programming multicast
3736          * filters into the device.
3737          */
3738         *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3739                         FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3740 }
3741
3742 void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop)
3743 {
3744         struct iwl_priv *priv = hw->priv;
3745
3746         mutex_lock(&priv->mutex);
3747         IWL_DEBUG_MAC80211(priv, "enter\n");
3748
3749         /* do not support "flush" */
3750         if (!priv->cfg->ops->lib->txfifo_flush)
3751                 goto done;
3752
3753         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3754                 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
3755                 goto done;
3756         }
3757         if (iwl_is_rfkill(priv)) {
3758                 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
3759                 goto done;
3760         }
3761
3762         /*
3763          * mac80211 will not push any more frames for transmit
3764          * until the flush is completed
3765          */
3766         if (drop) {
3767                 IWL_DEBUG_MAC80211(priv, "send flush command\n");
3768                 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
3769                         IWL_ERR(priv, "flush request fail\n");
3770                         goto done;
3771                 }
3772         }
3773         IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
3774         iwlagn_wait_tx_queue_empty(priv);
3775 done:
3776         mutex_unlock(&priv->mutex);
3777         IWL_DEBUG_MAC80211(priv, "leave\n");
3778 }
3779
3780 static void iwlagn_disable_roc(struct iwl_priv *priv)
3781 {
3782         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_PAN];
3783         struct ieee80211_channel *chan = ACCESS_ONCE(priv->hw->conf.channel);
3784
3785         lockdep_assert_held(&priv->mutex);
3786
3787         if (!ctx->is_active)
3788                 return;
3789
3790         ctx->staging.dev_type = RXON_DEV_TYPE_2STA;
3791         ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3792         iwl_set_rxon_channel(priv, chan, ctx);
3793         iwl_set_flags_for_band(priv, ctx, chan->band, NULL);
3794
3795         priv->_agn.hw_roc_channel = NULL;
3796
3797         iwlcore_commit_rxon(priv, ctx);
3798
3799         ctx->is_active = false;
3800 }
3801
3802 static void iwlagn_bg_roc_done(struct work_struct *work)
3803 {
3804         struct iwl_priv *priv = container_of(work, struct iwl_priv,
3805                                              _agn.hw_roc_work.work);
3806
3807         mutex_lock(&priv->mutex);
3808         ieee80211_remain_on_channel_expired(priv->hw);
3809         iwlagn_disable_roc(priv);
3810         mutex_unlock(&priv->mutex);
3811 }
3812
3813 #ifdef CONFIG_IWL5000
3814 static int iwl_mac_remain_on_channel(struct ieee80211_hw *hw,
3815                                      struct ieee80211_channel *channel,
3816                                      enum nl80211_channel_type channel_type,
3817                                      int duration)
3818 {
3819         struct iwl_priv *priv = hw->priv;
3820         int err = 0;
3821
3822         if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3823                 return -EOPNOTSUPP;
3824
3825         if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
3826                                         BIT(NL80211_IFTYPE_P2P_CLIENT)))
3827                 return -EOPNOTSUPP;
3828
3829         mutex_lock(&priv->mutex);
3830
3831         if (priv->contexts[IWL_RXON_CTX_PAN].is_active ||
3832             test_bit(STATUS_SCAN_HW, &priv->status)) {
3833                 err = -EBUSY;
3834                 goto out;
3835         }
3836
3837         priv->contexts[IWL_RXON_CTX_PAN].is_active = true;
3838         priv->_agn.hw_roc_channel = channel;
3839         priv->_agn.hw_roc_chantype = channel_type;
3840         priv->_agn.hw_roc_duration = DIV_ROUND_UP(duration * 1000, 1024);
3841         iwlcore_commit_rxon(priv, &priv->contexts[IWL_RXON_CTX_PAN]);
3842         queue_delayed_work(priv->workqueue, &priv->_agn.hw_roc_work,
3843                            msecs_to_jiffies(duration + 20));
3844
3845         msleep(IWL_MIN_SLOT_TIME); /* TU is almost ms */
3846         ieee80211_ready_on_channel(priv->hw);
3847
3848  out:
3849         mutex_unlock(&priv->mutex);
3850
3851         return err;
3852 }
3853
3854 static int iwl_mac_cancel_remain_on_channel(struct ieee80211_hw *hw)
3855 {
3856         struct iwl_priv *priv = hw->priv;
3857
3858         if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3859                 return -EOPNOTSUPP;
3860
3861         cancel_delayed_work_sync(&priv->_agn.hw_roc_work);
3862
3863         mutex_lock(&priv->mutex);
3864         iwlagn_disable_roc(priv);
3865         mutex_unlock(&priv->mutex);
3866
3867         return 0;
3868 }
3869 #endif
3870
3871 /*****************************************************************************
3872  *
3873  * driver setup and teardown
3874  *
3875  *****************************************************************************/
3876
3877 static void iwl_setup_deferred_work(struct iwl_priv *priv)
3878 {
3879         priv->workqueue = create_singlethread_workqueue(DRV_NAME);
3880
3881         init_waitqueue_head(&priv->wait_command_queue);
3882
3883         INIT_WORK(&priv->restart, iwl_bg_restart);
3884         INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
3885         INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
3886         INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
3887         INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
3888         INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
3889         INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
3890         INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3891         INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
3892         INIT_DELAYED_WORK(&priv->_agn.hw_roc_work, iwlagn_bg_roc_done);
3893
3894         iwl_setup_scan_deferred_work(priv);
3895
3896         if (priv->cfg->ops->lib->setup_deferred_work)
3897                 priv->cfg->ops->lib->setup_deferred_work(priv);
3898
3899         init_timer(&priv->statistics_periodic);
3900         priv->statistics_periodic.data = (unsigned long)priv;
3901         priv->statistics_periodic.function = iwl_bg_statistics_periodic;
3902
3903         init_timer(&priv->ucode_trace);
3904         priv->ucode_trace.data = (unsigned long)priv;
3905         priv->ucode_trace.function = iwl_bg_ucode_trace;
3906
3907         init_timer(&priv->watchdog);
3908         priv->watchdog.data = (unsigned long)priv;
3909         priv->watchdog.function = iwl_bg_watchdog;
3910
3911         if (!priv->cfg->base_params->use_isr_legacy)
3912                 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3913                         iwl_irq_tasklet, (unsigned long)priv);
3914         else
3915                 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3916                         iwl_irq_tasklet_legacy, (unsigned long)priv);
3917 }
3918
3919 static void iwl_cancel_deferred_work(struct iwl_priv *priv)
3920 {
3921         if (priv->cfg->ops->lib->cancel_deferred_work)
3922                 priv->cfg->ops->lib->cancel_deferred_work(priv);
3923
3924         cancel_delayed_work_sync(&priv->init_alive_start);
3925         cancel_delayed_work(&priv->alive_start);
3926         cancel_work_sync(&priv->run_time_calib_work);
3927         cancel_work_sync(&priv->beacon_update);
3928
3929         iwl_cancel_scan_deferred_work(priv);
3930
3931         cancel_work_sync(&priv->bt_full_concurrency);
3932         cancel_work_sync(&priv->bt_runtime_config);
3933
3934         del_timer_sync(&priv->statistics_periodic);
3935         del_timer_sync(&priv->ucode_trace);
3936 }
3937
3938 static void iwl_init_hw_rates(struct iwl_priv *priv,
3939                               struct ieee80211_rate *rates)
3940 {
3941         int i;
3942
3943         for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3944                 rates[i].bitrate = iwl_rates[i].ieee * 5;
3945                 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3946                 rates[i].hw_value_short = i;
3947                 rates[i].flags = 0;
3948                 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3949                         /*
3950                          * If CCK != 1M then set short preamble rate flag.
3951                          */
3952                         rates[i].flags |=
3953                                 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3954                                         0 : IEEE80211_RATE_SHORT_PREAMBLE;
3955                 }
3956         }
3957 }
3958
3959 static int iwl_init_drv(struct iwl_priv *priv)
3960 {
3961         int ret;
3962
3963         spin_lock_init(&priv->sta_lock);
3964         spin_lock_init(&priv->hcmd_lock);
3965
3966         INIT_LIST_HEAD(&priv->free_frames);
3967
3968         mutex_init(&priv->mutex);
3969         mutex_init(&priv->sync_cmd_mutex);
3970
3971         priv->ieee_channels = NULL;
3972         priv->ieee_rates = NULL;
3973         priv->band = IEEE80211_BAND_2GHZ;
3974
3975         priv->iw_mode = NL80211_IFTYPE_STATION;
3976         priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
3977         priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
3978         priv->_agn.agg_tids_count = 0;
3979
3980         /* initialize force reset */
3981         priv->force_reset[IWL_RF_RESET].reset_duration =
3982                 IWL_DELAY_NEXT_FORCE_RF_RESET;
3983         priv->force_reset[IWL_FW_RESET].reset_duration =
3984                 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
3985
3986         /* Choose which receivers/antennas to use */
3987         if (priv->cfg->ops->hcmd->set_rxon_chain)
3988                 priv->cfg->ops->hcmd->set_rxon_chain(priv,
3989                                         &priv->contexts[IWL_RXON_CTX_BSS]);
3990
3991         iwl_init_scan_params(priv);
3992
3993         /* init bt coex */
3994         if (priv->cfg->bt_params &&
3995             priv->cfg->bt_params->advanced_bt_coexist) {
3996                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
3997                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
3998                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
3999                 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
4000                 priv->bt_duration = BT_DURATION_LIMIT_DEF;
4001                 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
4002         }
4003
4004         /* Set the tx_power_user_lmt to the lowest power level
4005          * this value will get overwritten by channel max power avg
4006          * from eeprom */
4007         priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
4008         priv->tx_power_next = IWLAGN_TX_POWER_TARGET_POWER_MIN;
4009
4010         ret = iwl_init_channel_map(priv);
4011         if (ret) {
4012                 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
4013                 goto err;
4014         }
4015
4016         ret = iwlcore_init_geos(priv);
4017         if (ret) {
4018                 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
4019                 goto err_free_channel_map;
4020         }
4021         iwl_init_hw_rates(priv, priv->ieee_rates);
4022
4023         return 0;
4024
4025 err_free_channel_map:
4026         iwl_free_channel_map(priv);
4027 err:
4028         return ret;
4029 }
4030
4031 static void iwl_uninit_drv(struct iwl_priv *priv)
4032 {
4033         iwl_calib_free_results(priv);
4034         iwlcore_free_geos(priv);
4035         iwl_free_channel_map(priv);
4036         kfree(priv->scan_cmd);
4037 }
4038
4039 #ifdef CONFIG_IWL5000
4040 struct ieee80211_ops iwlagn_hw_ops = {
4041         .tx = iwlagn_mac_tx,
4042         .start = iwlagn_mac_start,
4043         .stop = iwlagn_mac_stop,
4044         .add_interface = iwl_mac_add_interface,
4045         .remove_interface = iwl_mac_remove_interface,
4046         .change_interface = iwl_mac_change_interface,
4047         .config = iwlagn_mac_config,
4048         .configure_filter = iwlagn_configure_filter,
4049         .set_key = iwlagn_mac_set_key,
4050         .update_tkip_key = iwlagn_mac_update_tkip_key,
4051         .conf_tx = iwl_mac_conf_tx,
4052         .bss_info_changed = iwlagn_bss_info_changed,
4053         .ampdu_action = iwlagn_mac_ampdu_action,
4054         .hw_scan = iwl_mac_hw_scan,
4055         .sta_notify = iwlagn_mac_sta_notify,
4056         .sta_add = iwlagn_mac_sta_add,
4057         .sta_remove = iwl_mac_sta_remove,
4058         .channel_switch = iwlagn_mac_channel_switch,
4059         .flush = iwlagn_mac_flush,
4060         .tx_last_beacon = iwl_mac_tx_last_beacon,
4061         .remain_on_channel = iwl_mac_remain_on_channel,
4062         .cancel_remain_on_channel = iwl_mac_cancel_remain_on_channel,
4063 };
4064 #endif
4065
4066 static void iwl_hw_detect(struct iwl_priv *priv)
4067 {
4068         priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
4069         priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
4070         pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
4071         IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", priv->rev_id);
4072 }
4073
4074 static int iwl_set_hw_params(struct iwl_priv *priv)
4075 {
4076         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
4077         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
4078         if (priv->cfg->mod_params->amsdu_size_8K)
4079                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
4080         else
4081                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
4082
4083         priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
4084
4085         if (priv->cfg->mod_params->disable_11n)
4086                 priv->cfg->sku &= ~IWL_SKU_N;
4087
4088         /* Device-specific setup */
4089         return priv->cfg->ops->lib->set_hw_params(priv);
4090 }
4091
4092 static const u8 iwlagn_bss_ac_to_fifo[] = {
4093         IWL_TX_FIFO_VO,
4094         IWL_TX_FIFO_VI,
4095         IWL_TX_FIFO_BE,
4096         IWL_TX_FIFO_BK,
4097 };
4098
4099 static const u8 iwlagn_bss_ac_to_queue[] = {
4100         0, 1, 2, 3,
4101 };
4102
4103 static const u8 iwlagn_pan_ac_to_fifo[] = {
4104         IWL_TX_FIFO_VO_IPAN,
4105         IWL_TX_FIFO_VI_IPAN,
4106         IWL_TX_FIFO_BE_IPAN,
4107         IWL_TX_FIFO_BK_IPAN,
4108 };
4109
4110 static const u8 iwlagn_pan_ac_to_queue[] = {
4111         7, 6, 5, 4,
4112 };
4113
4114 static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
4115 {
4116         int err = 0, i;
4117         struct iwl_priv *priv;
4118         struct ieee80211_hw *hw;
4119         struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
4120         unsigned long flags;
4121         u16 pci_cmd, num_mac;
4122
4123         /************************
4124          * 1. Allocating HW data
4125          ************************/
4126
4127         /* Disabling hardware scan means that mac80211 will perform scans
4128          * "the hard way", rather than using device's scan. */
4129         if (cfg->mod_params->disable_hw_scan) {
4130                 dev_printk(KERN_DEBUG, &(pdev->dev),
4131                         "sw scan support is deprecated\n");
4132 #ifdef CONFIG_IWL5000
4133                 iwlagn_hw_ops.hw_scan = NULL;
4134 #endif
4135 #ifdef CONFIG_IWL4965
4136                 iwl4965_hw_ops.hw_scan = NULL;
4137 #endif
4138         }
4139
4140         hw = iwl_alloc_all(cfg);
4141         if (!hw) {
4142                 err = -ENOMEM;
4143                 goto out;
4144         }
4145         priv = hw->priv;
4146         /* At this point both hw and priv are allocated. */
4147
4148         /*
4149          * The default context is always valid,
4150          * more may be discovered when firmware
4151          * is loaded.
4152          */
4153         priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
4154
4155         for (i = 0; i < NUM_IWL_RXON_CTX; i++)
4156                 priv->contexts[i].ctxid = i;
4157
4158         priv->contexts[IWL_RXON_CTX_BSS].always_active = true;
4159         priv->contexts[IWL_RXON_CTX_BSS].is_active = true;
4160         priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
4161         priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
4162         priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
4163         priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
4164         priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
4165         priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
4166         priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
4167         priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
4168         priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
4169                 BIT(NL80211_IFTYPE_ADHOC);
4170         priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
4171                 BIT(NL80211_IFTYPE_STATION);
4172         priv->contexts[IWL_RXON_CTX_BSS].ap_devtype = RXON_DEV_TYPE_AP;
4173         priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
4174         priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
4175         priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
4176
4177         priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
4178         priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING;
4179         priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC;
4180         priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
4181         priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
4182         priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
4183         priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
4184         priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
4185         priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
4186         priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
4187         priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
4188         priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
4189                 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
4190 #ifdef CONFIG_IWL_P2P
4191         priv->contexts[IWL_RXON_CTX_PAN].interface_modes |=
4192                 BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT(NL80211_IFTYPE_P2P_GO);
4193 #endif
4194         priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP;
4195         priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA;
4196         priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P;
4197
4198         BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
4199
4200         SET_IEEE80211_DEV(hw, &pdev->dev);
4201
4202         IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
4203         priv->cfg = cfg;
4204         priv->pci_dev = pdev;
4205         priv->inta_mask = CSR_INI_SET_MASK;
4206
4207         /* is antenna coupling more than 35dB ? */
4208         priv->bt_ant_couple_ok =
4209                 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
4210                 true : false;
4211
4212         /* enable/disable bt channel inhibition */
4213         priv->bt_ch_announce = iwlagn_bt_ch_announce;
4214         IWL_DEBUG_INFO(priv, "BT channel inhibition is %s\n",
4215                        (priv->bt_ch_announce) ? "On" : "Off");
4216
4217         if (iwl_alloc_traffic_mem(priv))
4218                 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
4219
4220         /**************************
4221          * 2. Initializing PCI bus
4222          **************************/
4223         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
4224                                 PCIE_LINK_STATE_CLKPM);
4225
4226         if (pci_enable_device(pdev)) {
4227                 err = -ENODEV;
4228                 goto out_ieee80211_free_hw;
4229         }
4230
4231         pci_set_master(pdev);
4232
4233         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
4234         if (!err)
4235                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
4236         if (err) {
4237                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4238                 if (!err)
4239                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4240                 /* both attempts failed: */
4241                 if (err) {
4242                         IWL_WARN(priv, "No suitable DMA available.\n");
4243                         goto out_pci_disable_device;
4244                 }
4245         }
4246
4247         err = pci_request_regions(pdev, DRV_NAME);
4248         if (err)
4249                 goto out_pci_disable_device;
4250
4251         pci_set_drvdata(pdev, priv);
4252
4253
4254         /***********************
4255          * 3. Read REV register
4256          ***********************/
4257         priv->hw_base = pci_iomap(pdev, 0, 0);
4258         if (!priv->hw_base) {
4259                 err = -ENODEV;
4260                 goto out_pci_release_regions;
4261         }
4262
4263         IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
4264                 (unsigned long long) pci_resource_len(pdev, 0));
4265         IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
4266
4267         /* these spin locks will be used in apm_ops.init and EEPROM access
4268          * we should init now
4269          */
4270         spin_lock_init(&priv->reg_lock);
4271         spin_lock_init(&priv->lock);
4272
4273         /*
4274          * stop and reset the on-board processor just in case it is in a
4275          * strange state ... like being left stranded by a primary kernel
4276          * and this is now the kdump kernel trying to start up
4277          */
4278         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4279
4280         iwl_hw_detect(priv);
4281         IWL_INFO(priv, "Detected %s, REV=0x%X\n",
4282                 priv->cfg->name, priv->hw_rev);
4283
4284         /* We disable the RETRY_TIMEOUT register (0x41) to keep
4285          * PCI Tx retries from interfering with C3 CPU state */
4286         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
4287
4288         iwl_prepare_card_hw(priv);
4289         if (!priv->hw_ready) {
4290                 IWL_WARN(priv, "Failed, HW not ready\n");
4291                 goto out_iounmap;
4292         }
4293
4294         /*****************
4295          * 4. Read EEPROM
4296          *****************/
4297         /* Read the EEPROM */
4298         err = iwl_eeprom_init(priv);
4299         if (err) {
4300                 IWL_ERR(priv, "Unable to init EEPROM\n");
4301                 goto out_iounmap;
4302         }
4303         err = iwl_eeprom_check_version(priv);
4304         if (err)
4305                 goto out_free_eeprom;
4306
4307         err = iwl_eeprom_check_sku(priv);
4308         if (err)
4309                 goto out_free_eeprom;
4310
4311         /* extract MAC Address */
4312         iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
4313         IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
4314         priv->hw->wiphy->addresses = priv->addresses;
4315         priv->hw->wiphy->n_addresses = 1;
4316         num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
4317         if (num_mac > 1) {
4318                 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
4319                        ETH_ALEN);
4320                 priv->addresses[1].addr[5]++;
4321                 priv->hw->wiphy->n_addresses++;
4322         }
4323
4324         /************************
4325          * 5. Setup HW constants
4326          ************************/
4327         if (iwl_set_hw_params(priv)) {
4328                 IWL_ERR(priv, "failed to set hw parameters\n");
4329                 goto out_free_eeprom;
4330         }
4331
4332         /*******************
4333          * 6. Setup priv
4334          *******************/
4335
4336         err = iwl_init_drv(priv);
4337         if (err)
4338                 goto out_free_eeprom;
4339         /* At this point both hw and priv are initialized. */
4340
4341         /********************
4342          * 7. Setup services
4343          ********************/
4344         spin_lock_irqsave(&priv->lock, flags);
4345         iwl_disable_interrupts(priv);
4346         spin_unlock_irqrestore(&priv->lock, flags);
4347
4348         pci_enable_msi(priv->pci_dev);
4349
4350         if (priv->cfg->ops->lib->isr_ops.alloc)
4351                 priv->cfg->ops->lib->isr_ops.alloc(priv);
4352
4353         err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr_ops.isr,
4354                           IRQF_SHARED, DRV_NAME, priv);
4355         if (err) {
4356                 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4357                 goto out_disable_msi;
4358         }
4359
4360         iwl_setup_deferred_work(priv);
4361         iwl_setup_rx_handlers(priv);
4362
4363         /*********************************************
4364          * 8. Enable interrupts and read RFKILL state
4365          *********************************************/
4366
4367         /* enable rfkill interrupt: hw bug w/a */
4368         pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
4369         if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
4370                 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
4371                 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
4372         }
4373
4374         iwl_enable_rfkill_int(priv);
4375
4376         /* If platform's RF_KILL switch is NOT set to KILL */
4377         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
4378                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
4379         else
4380                 set_bit(STATUS_RF_KILL_HW, &priv->status);
4381
4382         wiphy_rfkill_set_hw_state(priv->hw->wiphy,
4383                 test_bit(STATUS_RF_KILL_HW, &priv->status));
4384
4385         iwl_power_initialize(priv);
4386         iwl_tt_initialize(priv);
4387
4388         init_completion(&priv->_agn.firmware_loading_complete);
4389
4390         err = iwl_request_firmware(priv, true);
4391         if (err)
4392                 goto out_destroy_workqueue;
4393
4394         return 0;
4395
4396  out_destroy_workqueue:
4397         destroy_workqueue(priv->workqueue);
4398         priv->workqueue = NULL;
4399         free_irq(priv->pci_dev->irq, priv);
4400         if (priv->cfg->ops->lib->isr_ops.free)
4401                 priv->cfg->ops->lib->isr_ops.free(priv);
4402  out_disable_msi:
4403         pci_disable_msi(priv->pci_dev);
4404         iwl_uninit_drv(priv);
4405  out_free_eeprom:
4406         iwl_eeprom_free(priv);
4407  out_iounmap:
4408         pci_iounmap(pdev, priv->hw_base);
4409  out_pci_release_regions:
4410         pci_set_drvdata(pdev, NULL);
4411         pci_release_regions(pdev);
4412  out_pci_disable_device:
4413         pci_disable_device(pdev);
4414  out_ieee80211_free_hw:
4415         iwl_free_traffic_mem(priv);
4416         ieee80211_free_hw(priv->hw);
4417  out:
4418         return err;
4419 }
4420
4421 static void __devexit iwl_pci_remove(struct pci_dev *pdev)
4422 {
4423         struct iwl_priv *priv = pci_get_drvdata(pdev);
4424         unsigned long flags;
4425
4426         if (!priv)
4427                 return;
4428
4429         wait_for_completion(&priv->_agn.firmware_loading_complete);
4430
4431         IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
4432
4433         iwl_dbgfs_unregister(priv);
4434         sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
4435
4436         /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
4437          * to be called and iwl_down since we are removing the device
4438          * we need to set STATUS_EXIT_PENDING bit.
4439          */
4440         set_bit(STATUS_EXIT_PENDING, &priv->status);
4441
4442         iwl_leds_exit(priv);
4443
4444         if (priv->mac80211_registered) {
4445                 ieee80211_unregister_hw(priv->hw);
4446                 priv->mac80211_registered = 0;
4447         } else {
4448                 iwl_down(priv);
4449         }
4450
4451         /*
4452          * Make sure device is reset to low power before unloading driver.
4453          * This may be redundant with iwl_down(), but there are paths to
4454          * run iwl_down() without calling apm_ops.stop(), and there are
4455          * paths to avoid running iwl_down() at all before leaving driver.
4456          * This (inexpensive) call *makes sure* device is reset.
4457          */
4458         iwl_apm_stop(priv);
4459
4460         iwl_tt_exit(priv);
4461
4462         /* make sure we flush any pending irq or
4463          * tasklet for the driver
4464          */
4465         spin_lock_irqsave(&priv->lock, flags);
4466         iwl_disable_interrupts(priv);
4467         spin_unlock_irqrestore(&priv->lock, flags);
4468
4469         iwl_synchronize_irq(priv);
4470
4471         iwl_dealloc_ucode_pci(priv);
4472
4473         if (priv->rxq.bd)
4474                 iwlagn_rx_queue_free(priv, &priv->rxq);
4475         iwlagn_hw_txq_ctx_free(priv);
4476
4477         iwl_eeprom_free(priv);
4478
4479
4480         /*netif_stop_queue(dev); */
4481         flush_workqueue(priv->workqueue);
4482
4483         /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
4484          * priv->workqueue... so we can't take down the workqueue
4485          * until now... */
4486         destroy_workqueue(priv->workqueue);
4487         priv->workqueue = NULL;
4488         iwl_free_traffic_mem(priv);
4489
4490         free_irq(priv->pci_dev->irq, priv);
4491         pci_disable_msi(priv->pci_dev);
4492         pci_iounmap(pdev, priv->hw_base);
4493         pci_release_regions(pdev);
4494         pci_disable_device(pdev);
4495         pci_set_drvdata(pdev, NULL);
4496
4497         iwl_uninit_drv(priv);
4498
4499         if (priv->cfg->ops->lib->isr_ops.free)
4500                 priv->cfg->ops->lib->isr_ops.free(priv);
4501
4502         dev_kfree_skb(priv->beacon_skb);
4503
4504         ieee80211_free_hw(priv->hw);
4505 }
4506
4507
4508 /*****************************************************************************
4509  *
4510  * driver and module entry point
4511  *
4512  *****************************************************************************/
4513
4514 /* Hardware specific file defines the PCI IDs table for that hardware module */
4515 static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4516 #ifdef CONFIG_IWL4965
4517         {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
4518         {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4519 #endif /* CONFIG_IWL4965 */
4520 #ifdef CONFIG_IWL5000
4521 /* 5100 Series WiFi */
4522         {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
4523         {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
4524         {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
4525         {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
4526         {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
4527         {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
4528         {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
4529         {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
4530         {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
4531         {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
4532         {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
4533         {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
4534         {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
4535         {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
4536         {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
4537         {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
4538         {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
4539         {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
4540         {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
4541         {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
4542         {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
4543         {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
4544         {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
4545         {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
4546
4547 /* 5300 Series WiFi */
4548         {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
4549         {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
4550         {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
4551         {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
4552         {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
4553         {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
4554         {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
4555         {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
4556         {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
4557         {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
4558         {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
4559         {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
4560
4561 /* 5350 Series WiFi/WiMax */
4562         {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4563         {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4564         {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4565
4566 /* 5150 Series Wifi/WiMax */
4567         {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4568         {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4569         {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4570         {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4571         {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4572         {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4573
4574         {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4575         {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4576         {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4577         {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
4578
4579 /* 6x00 Series */
4580         {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4581         {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4582         {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4583         {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4584         {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4585         {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4586         {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4587         {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4588         {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4589         {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4590
4591 /* 6x05 Series */
4592         {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6005_2agn_cfg)},
4593         {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6005_2abg_cfg)},
4594         {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6005_2bg_cfg)},
4595         {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6005_2agn_cfg)},
4596         {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6005_2abg_cfg)},
4597         {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6005_2agn_cfg)},
4598         {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6005_2abg_cfg)},
4599
4600 /* 6x30 Series */
4601         {IWL_PCI_DEVICE(0x008A, 0x5305, iwl1030_bgn_cfg)},
4602         {IWL_PCI_DEVICE(0x008A, 0x5307, iwl1030_bg_cfg)},
4603         {IWL_PCI_DEVICE(0x008A, 0x5325, iwl1030_bgn_cfg)},
4604         {IWL_PCI_DEVICE(0x008A, 0x5327, iwl1030_bg_cfg)},
4605         {IWL_PCI_DEVICE(0x008B, 0x5315, iwl1030_bgn_cfg)},
4606         {IWL_PCI_DEVICE(0x008B, 0x5317, iwl1030_bg_cfg)},
4607         {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6030_2agn_cfg)},
4608         {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6030_2bgn_cfg)},
4609         {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6030_2abg_cfg)},
4610         {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6030_2agn_cfg)},
4611         {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6030_2bgn_cfg)},
4612         {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6030_2abg_cfg)},
4613         {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6030_2bg_cfg)},
4614         {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6030_2agn_cfg)},
4615         {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6030_2bgn_cfg)},
4616         {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6030_2abg_cfg)},
4617
4618 /* 6x50 WiFi/WiMax Series */
4619         {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4620         {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4621         {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4622         {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
4623         {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4624         {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4625
4626 /* 6150 WiFi/WiMax Series */
4627         {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6150_bgn_cfg)},
4628         {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6150_bgn_cfg)},
4629         {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6150_bgn_cfg)},
4630         {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6150_bgn_cfg)},
4631         {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6150_bgn_cfg)},
4632         {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6150_bgn_cfg)},
4633
4634 /* 1000 Series WiFi */
4635         {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4636         {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4637         {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4638         {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4639         {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4640         {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4641         {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4642         {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4643         {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4644         {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4645         {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4646         {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
4647
4648 /* 100 Series WiFi */
4649         {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
4650         {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
4651         {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
4652         {IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg)},
4653         {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
4654         {IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg)},
4655
4656 /* 130 Series WiFi */
4657         {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)},
4658         {IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)},
4659         {IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)},
4660         {IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)},
4661         {IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)},
4662         {IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)},
4663
4664 /* 2x00 Series */
4665         {IWL_PCI_DEVICE(0x0890, 0x4022, iwl2000_2bgn_cfg)},
4666         {IWL_PCI_DEVICE(0x0891, 0x4222, iwl2000_2bgn_cfg)},
4667         {IWL_PCI_DEVICE(0x0890, 0x4422, iwl2000_2bgn_cfg)},
4668         {IWL_PCI_DEVICE(0x0890, 0x4026, iwl2000_2bg_cfg)},
4669         {IWL_PCI_DEVICE(0x0891, 0x4226, iwl2000_2bg_cfg)},
4670         {IWL_PCI_DEVICE(0x0890, 0x4426, iwl2000_2bg_cfg)},
4671
4672 /* 2x30 Series */
4673         {IWL_PCI_DEVICE(0x0887, 0x4062, iwl2030_2bgn_cfg)},
4674         {IWL_PCI_DEVICE(0x0888, 0x4262, iwl2030_2bgn_cfg)},
4675         {IWL_PCI_DEVICE(0x0887, 0x4462, iwl2030_2bgn_cfg)},
4676         {IWL_PCI_DEVICE(0x0887, 0x4066, iwl2030_2bg_cfg)},
4677         {IWL_PCI_DEVICE(0x0888, 0x4266, iwl2030_2bg_cfg)},
4678         {IWL_PCI_DEVICE(0x0887, 0x4466, iwl2030_2bg_cfg)},
4679
4680 /* 6x35 Series */
4681         {IWL_PCI_DEVICE(0x088E, 0x4060, iwl6035_2agn_cfg)},
4682         {IWL_PCI_DEVICE(0x088F, 0x4260, iwl6035_2agn_cfg)},
4683         {IWL_PCI_DEVICE(0x088E, 0x4460, iwl6035_2agn_cfg)},
4684         {IWL_PCI_DEVICE(0x088E, 0x4064, iwl6035_2abg_cfg)},
4685         {IWL_PCI_DEVICE(0x088F, 0x4264, iwl6035_2abg_cfg)},
4686         {IWL_PCI_DEVICE(0x088E, 0x4464, iwl6035_2abg_cfg)},
4687         {IWL_PCI_DEVICE(0x088E, 0x4066, iwl6035_2bg_cfg)},
4688         {IWL_PCI_DEVICE(0x088F, 0x4266, iwl6035_2bg_cfg)},
4689         {IWL_PCI_DEVICE(0x088E, 0x4466, iwl6035_2bg_cfg)},
4690
4691 /* 200 Series */
4692         {IWL_PCI_DEVICE(0x0894, 0x0022, iwl200_bgn_cfg)},
4693         {IWL_PCI_DEVICE(0x0895, 0x0222, iwl200_bgn_cfg)},
4694         {IWL_PCI_DEVICE(0x0894, 0x0422, iwl200_bgn_cfg)},
4695         {IWL_PCI_DEVICE(0x0894, 0x0026, iwl200_bg_cfg)},
4696         {IWL_PCI_DEVICE(0x0895, 0x0226, iwl200_bg_cfg)},
4697         {IWL_PCI_DEVICE(0x0894, 0x0426, iwl200_bg_cfg)},
4698
4699 /* 230 Series */
4700         {IWL_PCI_DEVICE(0x0892, 0x0062, iwl230_bgn_cfg)},
4701         {IWL_PCI_DEVICE(0x0893, 0x0262, iwl230_bgn_cfg)},
4702         {IWL_PCI_DEVICE(0x0892, 0x0462, iwl230_bgn_cfg)},
4703         {IWL_PCI_DEVICE(0x0892, 0x0066, iwl230_bg_cfg)},
4704         {IWL_PCI_DEVICE(0x0893, 0x0266, iwl230_bg_cfg)},
4705         {IWL_PCI_DEVICE(0x0892, 0x0466, iwl230_bg_cfg)},
4706
4707 #endif /* CONFIG_IWL5000 */
4708
4709         {0}
4710 };
4711 MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4712
4713 static struct pci_driver iwl_driver = {
4714         .name = DRV_NAME,
4715         .id_table = iwl_hw_card_ids,
4716         .probe = iwl_pci_probe,
4717         .remove = __devexit_p(iwl_pci_remove),
4718         .driver.pm = IWL_PM_OPS,
4719 };
4720
4721 static int __init iwl_init(void)
4722 {
4723
4724         int ret;
4725         pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4726         pr_info(DRV_COPYRIGHT "\n");
4727
4728         ret = iwlagn_rate_control_register();
4729         if (ret) {
4730                 pr_err("Unable to register rate control algorithm: %d\n", ret);
4731                 return ret;
4732         }
4733
4734         ret = pci_register_driver(&iwl_driver);
4735         if (ret) {
4736                 pr_err("Unable to initialize PCI module\n");
4737                 goto error_register;
4738         }
4739
4740         return ret;
4741
4742 error_register:
4743         iwlagn_rate_control_unregister();
4744         return ret;
4745 }
4746
4747 static void __exit iwl_exit(void)
4748 {
4749         pci_unregister_driver(&iwl_driver);
4750         iwlagn_rate_control_unregister();
4751 }
4752
4753 module_exit(iwl_exit);
4754 module_init(iwl_init);
4755
4756 #ifdef CONFIG_IWLWIFI_DEBUG
4757 module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
4758 MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4759 module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
4760 MODULE_PARM_DESC(debug, "debug output mask");
4761 #endif
4762
4763 module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
4764 MODULE_PARM_DESC(swcrypto50,
4765                  "using crypto in software (default 0 [hardware]) (deprecated)");
4766 module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4767 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4768 module_param_named(queues_num50,
4769                    iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4770 MODULE_PARM_DESC(queues_num50,
4771                  "number of hw queues in 50xx series (deprecated)");
4772 module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4773 MODULE_PARM_DESC(queues_num, "number of hw queues.");
4774 module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4775 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
4776 module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4777 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4778 module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
4779                    int, S_IRUGO);
4780 MODULE_PARM_DESC(amsdu_size_8K50,
4781                  "enable 8K amsdu size in 50XX series (deprecated)");
4782 module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4783                    int, S_IRUGO);
4784 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4785 module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4786 MODULE_PARM_DESC(fw_restart50,
4787                  "restart firmware in case of error (deprecated)");
4788 module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4789 MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4790 module_param_named(
4791         disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
4792 MODULE_PARM_DESC(disable_hw_scan,
4793                  "disable hardware scanning (default 0) (deprecated)");
4794
4795 module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4796                    S_IRUGO);
4797 MODULE_PARM_DESC(ucode_alternative,
4798                  "specify ucode alternative to use from ucode file");
4799
4800 module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
4801 MODULE_PARM_DESC(antenna_coupling,
4802                  "specify antenna coupling in dB (defualt: 0 dB)");
4803
4804 module_param_named(bt_ch_inhibition, iwlagn_bt_ch_announce, bool, S_IRUGO);
4805 MODULE_PARM_DESC(bt_ch_inhibition,
4806                  "Disable BT channel inhibition (default: enable)");