1 #ifndef B43_TABLES_NPHY_H_
2 #define B43_TABLES_NPHY_H_
4 #include <linux/types.h>
7 struct b43_phy_n_sfo_cfg {
16 struct b43_nphy_channeltab_entry_rev2 {
17 /* The channel number */
19 /* The channel frequency in MHz */
21 /* An unknown value */
23 /* Radio register values on channelswitch */
33 u8 radio_lgbuf_cenbuf;
36 u8 radio_c1_lgbuf_atune;
37 u8 radio_c1_lgbuf_gtune;
39 u8 radio_c1_tx_pgapadtn;
40 u8 radio_c1_tx_mxbgtrim;
41 u8 radio_c2_lgbuf_atune;
42 u8 radio_c2_lgbuf_gtune;
44 u8 radio_c2_tx_pgapadtn;
45 u8 radio_c2_tx_mxbgtrim;
46 /* PHY register values on channelswitch */
47 struct b43_phy_n_sfo_cfg phy_regs;
50 struct b43_nphy_channeltab_entry_rev3 {
51 /* The channel number */
53 /* The channel frequency in MHz */
55 /* Radio register values on channelswitch */
57 /* PHY register values on channelswitch */
58 struct b43_phy_n_sfo_cfg phy_regs;
64 struct nphy_txiqcal_ladder {
69 struct nphy_rf_control_override_rev2 {
76 struct nphy_rf_control_override_rev3 {
85 /* Upload the default register value table.
86 * If "ghz5" is true, we upload the 5Ghz table. Otherwise the 2.4Ghz
87 * table is uploaded. If "ignore_uploadflag" is true, we upload any value
88 * and ignore the "UPLOAD" flag. */
89 void b2055_upload_inittab(struct b43_wldev *dev,
90 bool ghz5, bool ignore_uploadflag);
93 /* Get the NPHY Channel Switch Table entry for a channel number.
94 * Returns NULL on failure to find an entry. */
95 const struct b43_nphy_channeltab_entry_rev2 *
96 b43_nphy_get_chantabent_rev2(struct b43_wldev *dev, u8 channel);
99 /* The N-PHY tables. */
101 #define B43_NTAB_TYPEMASK 0xF0000000
102 #define B43_NTAB_8BIT 0x10000000
103 #define B43_NTAB_16BIT 0x20000000
104 #define B43_NTAB_32BIT 0x30000000
105 #define B43_NTAB8(table, offset) (((table) << 10) | (offset) | B43_NTAB_8BIT)
106 #define B43_NTAB16(table, offset) (((table) << 10) | (offset) | B43_NTAB_16BIT)
107 #define B43_NTAB32(table, offset) (((table) << 10) | (offset) | B43_NTAB_32BIT)
109 /* Static N-PHY tables */
110 #define B43_NTAB_FRAMESTRUCT B43_NTAB32(0x0A, 0x000) /* Frame Struct Table */
111 #define B43_NTAB_FRAMESTRUCT_SIZE 832
112 #define B43_NTAB_FRAMELT B43_NTAB8 (0x18, 0x000) /* Frame Lookup Table */
113 #define B43_NTAB_FRAMELT_SIZE 32
114 #define B43_NTAB_TMAP B43_NTAB32(0x0C, 0x000) /* T Map Table */
115 #define B43_NTAB_TMAP_SIZE 448
116 #define B43_NTAB_TDTRN B43_NTAB32(0x0E, 0x000) /* TDTRN Table */
117 #define B43_NTAB_TDTRN_SIZE 704
118 #define B43_NTAB_INTLEVEL B43_NTAB32(0x0D, 0x000) /* Int Level Table */
119 #define B43_NTAB_INTLEVEL_SIZE 7
120 #define B43_NTAB_PILOT B43_NTAB16(0x0B, 0x000) /* Pilot Table */
121 #define B43_NTAB_PILOT_SIZE 88
122 #define B43_NTAB_PILOTLT B43_NTAB32(0x14, 0x000) /* Pilot Lookup Table */
123 #define B43_NTAB_PILOTLT_SIZE 6
124 #define B43_NTAB_TDI20A0 B43_NTAB32(0x13, 0x080) /* TDI Table 20 Antenna 0 */
125 #define B43_NTAB_TDI20A0_SIZE 55
126 #define B43_NTAB_TDI20A1 B43_NTAB32(0x13, 0x100) /* TDI Table 20 Antenna 1 */
127 #define B43_NTAB_TDI20A1_SIZE 55
128 #define B43_NTAB_TDI40A0 B43_NTAB32(0x13, 0x280) /* TDI Table 40 Antenna 0 */
129 #define B43_NTAB_TDI40A0_SIZE 110
130 #define B43_NTAB_TDI40A1 B43_NTAB32(0x13, 0x300) /* TDI Table 40 Antenna 1 */
131 #define B43_NTAB_TDI40A1_SIZE 110
132 #define B43_NTAB_BDI B43_NTAB16(0x15, 0x000) /* BDI Table */
133 #define B43_NTAB_BDI_SIZE 6
134 #define B43_NTAB_CHANEST B43_NTAB32(0x16, 0x000) /* Channel Estimate Table */
135 #define B43_NTAB_CHANEST_SIZE 96
136 #define B43_NTAB_MCS B43_NTAB8 (0x12, 0x000) /* MCS Table */
137 #define B43_NTAB_MCS_SIZE 128
139 /* Volatile N-PHY tables */
140 #define B43_NTAB_NOISEVAR10 B43_NTAB32(0x10, 0x000) /* Noise Var Table 10 */
141 #define B43_NTAB_NOISEVAR10_SIZE 256
142 #define B43_NTAB_NOISEVAR11 B43_NTAB32(0x10, 0x080) /* Noise Var Table 11 */
143 #define B43_NTAB_NOISEVAR11_SIZE 256
144 #define B43_NTAB_C0_ESTPLT B43_NTAB8 (0x1A, 0x000) /* Estimate Power Lookup Table Core 0 */
145 #define B43_NTAB_C0_ESTPLT_SIZE 64
146 #define B43_NTAB_C1_ESTPLT B43_NTAB8 (0x1B, 0x000) /* Estimate Power Lookup Table Core 1 */
147 #define B43_NTAB_C1_ESTPLT_SIZE 64
148 #define B43_NTAB_C0_ADJPLT B43_NTAB8 (0x1A, 0x040) /* Adjust Power Lookup Table Core 0 */
149 #define B43_NTAB_C0_ADJPLT_SIZE 128
150 #define B43_NTAB_C1_ADJPLT B43_NTAB8 (0x1B, 0x040) /* Adjust Power Lookup Table Core 1 */
151 #define B43_NTAB_C1_ADJPLT_SIZE 128
152 #define B43_NTAB_C0_GAINCTL B43_NTAB32(0x1A, 0x0C0) /* Gain Control Lookup Table Core 0 */
153 #define B43_NTAB_C0_GAINCTL_SIZE 128
154 #define B43_NTAB_C1_GAINCTL B43_NTAB32(0x1B, 0x0C0) /* Gain Control Lookup Table Core 1 */
155 #define B43_NTAB_C1_GAINCTL_SIZE 128
156 #define B43_NTAB_C0_IQLT B43_NTAB32(0x1A, 0x140) /* IQ Lookup Table Core 0 */
157 #define B43_NTAB_C0_IQLT_SIZE 128
158 #define B43_NTAB_C1_IQLT B43_NTAB32(0x1B, 0x140) /* IQ Lookup Table Core 1 */
159 #define B43_NTAB_C1_IQLT_SIZE 128
160 #define B43_NTAB_C0_LOFEEDTH B43_NTAB16(0x1A, 0x1C0) /* Local Oscillator Feed Through Lookup Table Core 0 */
161 #define B43_NTAB_C0_LOFEEDTH_SIZE 128
162 #define B43_NTAB_C1_LOFEEDTH B43_NTAB16(0x1B, 0x1C0) /* Local Oscillator Feed Through Lookup Table Core 1 */
163 #define B43_NTAB_C1_LOFEEDTH_SIZE 128
165 #define B43_NTAB_TX_IQLO_CAL_LOFT_LADDER_40_SIZE 18
166 #define B43_NTAB_TX_IQLO_CAL_LOFT_LADDER_20_SIZE 18
167 #define B43_NTAB_TX_IQLO_CAL_IQIMB_LADDER_40_SIZE 18
168 #define B43_NTAB_TX_IQLO_CAL_IQIMB_LADDER_20_SIZE 18
169 #define B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3 11
170 #define B43_NTAB_TX_IQLO_CAL_STARTCOEFS 9
171 #define B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3 12
172 #define B43_NTAB_TX_IQLO_CAL_CMDS_RECAL 10
173 #define B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL 10
174 #define B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3 12
176 u32 b43_ntab_read(struct b43_wldev *dev, u32 offset);
177 void b43_ntab_read_bulk(struct b43_wldev *dev, u32 offset,
178 unsigned int nr_elements, void *_data);
179 void b43_ntab_write(struct b43_wldev *dev, u32 offset, u32 value);
180 void b43_ntab_write_bulk(struct b43_wldev *dev, u32 offset,
181 unsigned int nr_elements, const void *_data);
183 void b43_nphy_rev0_1_2_tables_init(struct b43_wldev *dev);
184 void b43_nphy_rev3plus_tables_init(struct b43_wldev *dev);
186 extern const u32 b43_ntab_tx_gain_rev0_1_2[];
187 extern const u32 b43_ntab_tx_gain_rev3plus_2ghz[];
188 extern const u32 b43_ntab_tx_gain_rev3_5ghz[];
189 extern const u32 b43_ntab_tx_gain_rev4_5ghz[];
190 extern const u32 b43_ntab_tx_gain_rev5plus_5ghz[];
192 extern const u32 txpwrctrl_tx_gain_ipa[];
193 extern const u32 txpwrctrl_tx_gain_ipa_rev5[];
194 extern const u32 txpwrctrl_tx_gain_ipa_rev6[];
195 extern const u32 txpwrctrl_tx_gain_ipa_5g[];
196 extern const u16 tbl_iqcal_gainparams[2][9][8];
197 extern const struct nphy_txiqcal_ladder ladder_lo[];
198 extern const struct nphy_txiqcal_ladder ladder_iq[];
199 extern const u16 loscale[];
201 extern const u16 tbl_tx_iqlo_cal_loft_ladder_40[];
202 extern const u16 tbl_tx_iqlo_cal_loft_ladder_20[];
203 extern const u16 tbl_tx_iqlo_cal_iqimb_ladder_40[];
204 extern const u16 tbl_tx_iqlo_cal_iqimb_ladder_20[];
205 extern const u16 tbl_tx_iqlo_cal_startcoefs_nphyrev3[];
206 extern const u16 tbl_tx_iqlo_cal_startcoefs[];
207 extern const u16 tbl_tx_iqlo_cal_cmds_recal_nphyrev3[];
208 extern const u16 tbl_tx_iqlo_cal_cmds_recal[];
209 extern const u16 tbl_tx_iqlo_cal_cmds_fullcal[];
210 extern const u16 tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[];
211 extern const s16 tbl_tx_filter_coef_rev4[7][15];
213 extern const struct nphy_rf_control_override_rev2
214 tbl_rf_control_override_rev2[];
215 extern const struct nphy_rf_control_override_rev3
216 tbl_rf_control_override_rev3[];
218 #endif /* B43_TABLES_NPHY_H_ */