Pileus Git - ~andy/linux/blob - drivers/net/wireless/b43/phy_n.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n PHY support
   5
   6   Copyright (c) 2008 Michael Buesch <m@bues.ch>
   7   Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
   8
   9   This program is free software; you can redistribute it and/or modify
  10   it under the terms of the GNU General Public License as published by
  11   the Free Software Foundation; either version 2 of the License, or
  12   (at your option) any later version.
  13
  14   This program is distributed in the hope that it will be useful,
  15   but WITHOUT ANY WARRANTY; without even the implied warranty of
  16   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17   GNU General Public License for more details.
  18
  19   You should have received a copy of the GNU General Public License
  20   along with this program; see the file COPYING.  If not, write to
  21   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  22   Boston, MA 02110-1301, USA.
  23
  24 */
  25
  26 #include <linux/delay.h>
  27 #include <linux/slab.h>
  28 #include <linux/types.h>
  29
  30 #include "b43.h"
  31 #include "phy_n.h"
  32 #include "tables_nphy.h"
  33 #include "radio_2055.h"
  34 #include "radio_2056.h"
  35 #include "radio_2057.h"
  36 #include "main.h"
  37
  38 struct nphy_txgains {
  39         u16 txgm[2];
  40         u16 pga[2];
  41         u16 pad[2];
  42         u16 ipa[2];
  43 };
  44
  45 struct nphy_iqcal_params {
  46         u16 txgm;
  47         u16 pga;
  48         u16 pad;
  49         u16 ipa;
  50         u16 cal_gain;
  51         u16 ncorr[5];
  52 };
  53
  54 struct nphy_iq_est {
  55         s32 iq0_prod;
  56         u32 i0_pwr;
  57         u32 q0_pwr;
  58         s32 iq1_prod;
  59         u32 i1_pwr;
  60         u32 q1_pwr;
  61 };
  62
  63 enum b43_nphy_rf_sequence {
  64         B43_RFSEQ_RX2TX,
  65         B43_RFSEQ_TX2RX,
  66         B43_RFSEQ_RESET2RX,
  67         B43_RFSEQ_UPDATE_GAINH,
  68         B43_RFSEQ_UPDATE_GAINL,
  69         B43_RFSEQ_UPDATE_GAINU,
  70 };
  71
  72 enum b43_nphy_rssi_type {
  73         B43_NPHY_RSSI_X = 0,
  74         B43_NPHY_RSSI_Y,
  75         B43_NPHY_RSSI_Z,
  76         B43_NPHY_RSSI_PWRDET,
  77         B43_NPHY_RSSI_TSSI_I,
  78         B43_NPHY_RSSI_TSSI_Q,
  79         B43_NPHY_RSSI_TBD,
  80 };
  81
  82 enum n_rail_type {
  83         N_RAIL_I = 0,
  84         N_RAIL_Q = 1,
  85 };
  86
  87 static inline bool b43_nphy_ipa(struct b43_wldev *dev)
  88 {
  89         enum ieee80211_band band = b43_current_band(dev->wl);
  90         return ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
  91                 (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ));
  92 }
  93
  94 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreGetState */
  95 static u8 b43_nphy_get_rx_core_state(struct b43_wldev *dev)
  96 {
  97         return (b43_phy_read(dev, B43_NPHY_RFSEQCA) & B43_NPHY_RFSEQCA_RXEN) >>
  98                 B43_NPHY_RFSEQCA_RXEN_SHIFT;
  99 }
 100
 101 /**************************************************
 102  * RF (just without b43_nphy_rf_control_intc_override)
 103  **************************************************/
 104
 105 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
 106 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
 107                                        enum b43_nphy_rf_sequence seq)
 108 {
 109         static const u16 trigger[] = {
 110                 [B43_RFSEQ_RX2TX]               = B43_NPHY_RFSEQTR_RX2TX,
 111                 [B43_RFSEQ_TX2RX]               = B43_NPHY_RFSEQTR_TX2RX,
 112                 [B43_RFSEQ_RESET2RX]            = B43_NPHY_RFSEQTR_RST2RX,
 113                 [B43_RFSEQ_UPDATE_GAINH]        = B43_NPHY_RFSEQTR_UPGH,
 114                 [B43_RFSEQ_UPDATE_GAINL]        = B43_NPHY_RFSEQTR_UPGL,
 115                 [B43_RFSEQ_UPDATE_GAINU]        = B43_NPHY_RFSEQTR_UPGU,
 116         };
 117         int i;
 118         u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
 119
 120         B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
 121
 122         b43_phy_set(dev, B43_NPHY_RFSEQMODE,
 123                     B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
 124         b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
 125         for (i = 0; i < 200; i++) {
 126                 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
 127                         goto ok;
 128                 msleep(1);
 129         }
 130         b43err(dev->wl, "RF sequence status timeout\n");
 131 ok:
 132         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
 133 }
 134
 135 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverrideRev7 */
 136 static void b43_nphy_rf_control_override_rev7(struct b43_wldev *dev, u16 field,
 137                                               u16 value, u8 core, bool off,
 138                                               u8 override)
 139 {
 140         const struct nphy_rf_control_override_rev7 *e;
 141         u16 en_addrs[3][2] = {
 142                 { 0x0E7, 0x0EC }, { 0x342, 0x343 }, { 0x346, 0x347 }
 143         };
 144         u16 en_addr;
 145         u16 en_mask = field;
 146         u16 val_addr;
 147         u8 i;
 148
 149         /* Remember: we can get NULL! */
 150         e = b43_nphy_get_rf_ctl_over_rev7(dev, field, override);
 151
 152         for (i = 0; i < 2; i++) {
 153                 if (override >= ARRAY_SIZE(en_addrs)) {
 154                         b43err(dev->wl, "Invalid override value %d\n", override);
 155                         return;
 156                 }
 157                 en_addr = en_addrs[override][i];
 158
 159                 val_addr = (i == 0) ? e->val_addr_core0 : e->val_addr_core1;
 160
 161                 if (off) {
 162                         b43_phy_mask(dev, en_addr, ~en_mask);
 163                         if (e) /* Do it safer, better than wl */
 164                                 b43_phy_mask(dev, val_addr, ~e->val_mask);
 165                 } else {
 166                         if (!core || (core & (1 << i))) {
 167                                 b43_phy_set(dev, en_addr, en_mask);
 168                                 if (e)
 169                                         b43_phy_maskset(dev, val_addr, ~e->val_mask, (value << e->val_shift));
 170                         }
 171                 }
 172         }
 173 }
 174
 175 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
 176 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
 177                                                 u16 value, u8 core, bool off)
 178 {
 179         int i;
 180         u8 index = fls(field);
 181         u8 addr, en_addr, val_addr;
 182         /* we expect only one bit set */
 183         B43_WARN_ON(field & (~(1 << (index - 1))));
 184
 185         if (dev->phy.rev >= 3) {
 186                 const struct nphy_rf_control_override_rev3 *rf_ctrl;
 187                 for (i = 0; i < 2; i++) {
 188                         if (index == 0 || index == 16) {
 189                                 b43err(dev->wl,
 190                                         "Unsupported RF Ctrl Override call\n");
 191                                 return;
 192                         }
 193
 194                         rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
 195                         en_addr = B43_PHY_N((i == 0) ?
 196                                 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
 197                         val_addr = B43_PHY_N((i == 0) ?
 198                                 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
 199
 200                         if (off) {
 201                                 b43_phy_mask(dev, en_addr, ~(field));
 202                                 b43_phy_mask(dev, val_addr,
 203                                                 ~(rf_ctrl->val_mask));
 204                         } else {
 205                                 if (core == 0 || ((1 << i) & core)) {
 206                                         b43_phy_set(dev, en_addr, field);
 207                                         b43_phy_maskset(dev, val_addr,
 208                                                 ~(rf_ctrl->val_mask),
 209                                                 (value << rf_ctrl->val_shift));
 210                                 }
 211                         }
 212                 }
 213         } else {
 214                 const struct nphy_rf_control_override_rev2 *rf_ctrl;
 215                 if (off) {
 216                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
 217                         value = 0;
 218                 } else {
 219                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
 220                 }
 221
 222                 for (i = 0; i < 2; i++) {
 223                         if (index <= 1 || index == 16) {
 224                                 b43err(dev->wl,
 225                                         "Unsupported RF Ctrl Override call\n");
 226                                 return;
 227                         }
 228
 229                         if (index == 2 || index == 10 ||
 230                             (index >= 13 && index <= 15)) {
 231                                 core = 1;
 232                         }
 233
 234                         rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
 235                         addr = B43_PHY_N((i == 0) ?
 236                                 rf_ctrl->addr0 : rf_ctrl->addr1);
 237
 238                         if ((1 << i) & core)
 239                                 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
 240                                                 (value << rf_ctrl->shift));
 241
 242                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
 243                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 244                                         B43_NPHY_RFCTL_CMD_START);
 245                         udelay(1);
 246                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
 247                 }
 248         }
 249 }
 250
 251 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
 252 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
 253                                                 u16 value, u8 core)
 254 {
 255         u8 i, j;
 256         u16 reg, tmp, val;
 257
 258         B43_WARN_ON(dev->phy.rev < 3);
 259         B43_WARN_ON(field > 4);
 260
 261         for (i = 0; i < 2; i++) {
 262                 if ((core == 1 && i == 1) || (core == 2 && !i))
 263                         continue;
 264
 265                 reg = (i == 0) ?
 266                         B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
 267                 b43_phy_set(dev, reg, 0x400);
 268
 269                 switch (field) {
 270                 case 0:
 271                         b43_phy_write(dev, reg, 0);
 272                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
 273                         break;
 274                 case 1:
 275                         if (!i) {
 276                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
 277                                                 0xFC3F, (value << 6));
 278                                 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
 279                                                 0xFFFE, 1);
 280                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 281                                                 B43_NPHY_RFCTL_CMD_START);
 282                                 for (j = 0; j < 100; j++) {
 283                                         if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START)) {
 284                                                 j = 0;
 285                                                 break;
 286                                         }
 287                                         udelay(10);
 288                                 }
 289                                 if (j)
 290                                         b43err(dev->wl,
 291                                                 "intc override timeout\n");
 292                                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
 293                                                 0xFFFE);
 294                         } else {
 295                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
 296                                                 0xFC3F, (value << 6));
 297                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
 298                                                 0xFFFE, 1);
 299                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 300                                                 B43_NPHY_RFCTL_CMD_RXTX);
 301                                 for (j = 0; j < 100; j++) {
 302                                         if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX)) {
 303                                                 j = 0;
 304                                                 break;
 305                                         }
 306                                         udelay(10);
 307                                 }
 308                                 if (j)
 309                                         b43err(dev->wl,
 310                                                 "intc override timeout\n");
 311                                 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
 312                                                 0xFFFE);
 313                         }
 314                         break;
 315                 case 2:
 316                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
 317                                 tmp = 0x0020;
 318                                 val = value << 5;
 319                         } else {
 320                                 tmp = 0x0010;
 321                                 val = value << 4;
 322                         }
 323                         b43_phy_maskset(dev, reg, ~tmp, val);
 324                         break;
 325                 case 3:
 326                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
 327                                 tmp = 0x0001;
 328                                 val = value;
 329                         } else {
 330                                 tmp = 0x0004;
 331                                 val = value << 2;
 332                         }
 333                         b43_phy_maskset(dev, reg, ~tmp, val);
 334                         break;
 335                 case 4:
 336                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
 337                                 tmp = 0x0002;
 338                                 val = value << 1;
 339                         } else {
 340                                 tmp = 0x0008;
 341                                 val = value << 3;
 342                         }
 343                         b43_phy_maskset(dev, reg, ~tmp, val);
 344                         break;
 345                 }
 346         }
 347 }
 348
 349 /**************************************************
 350  * Various PHY ops
 351  **************************************************/
 352
 353 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 354 static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
 355                                           const u16 *clip_st)
 356 {
 357         b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
 358         b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
 359 }
 360
 361 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 362 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 363 {
 364         clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
 365         clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
 366 }
 367
 368 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
 369 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
 370 {
 371         u16 tmp;
 372
 373         if (dev->dev->core_rev == 16)
 374                 b43_mac_suspend(dev);
 375
 376         tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
 377         tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
 378                 B43_NPHY_CLASSCTL_WAITEDEN);
 379         tmp &= ~mask;
 380         tmp |= (val & mask);
 381         b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
 382
 383         if (dev->dev->core_rev == 16)
 384                 b43_mac_enable(dev);
 385
 386         return tmp;
 387 }
 388
 389 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
 390 static void b43_nphy_reset_cca(struct b43_wldev *dev)
 391 {
 392         u16 bbcfg;
 393
 394         b43_phy_force_clock(dev, 1);
 395         bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
 396         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
 397         udelay(1);
 398         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
 399         b43_phy_force_clock(dev, 0);
 400         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
 401 }
 402
 403 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
 404 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
 405 {
 406         struct b43_phy *phy = &dev->phy;
 407         struct b43_phy_n *nphy = phy->n;
 408
 409         if (enable) {
 410                 static const u16 clip[] = { 0xFFFF, 0xFFFF };
 411                 if (nphy->deaf_count++ == 0) {
 412                         nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
 413                         b43_nphy_classifier(dev, 0x7, 0);
 414                         b43_nphy_read_clip_detection(dev, nphy->clip_state);
 415                         b43_nphy_write_clip_detection(dev, clip);
 416                 }
 417                 b43_nphy_reset_cca(dev);
 418         } else {
 419                 if (--nphy->deaf_count == 0) {
 420                         b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
 421                         b43_nphy_write_clip_detection(dev, nphy->clip_state);
 422                 }
 423         }
 424 }
 425
 426 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
 427 static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
 428 {
 429         struct b43_phy_n *nphy = dev->phy.n;
 430
 431         u8 i;
 432         s16 tmp;
 433         u16 data[4];
 434         s16 gain[2];
 435         u16 minmax[2];
 436         static const u16 lna_gain[4] = { -2, 10, 19, 25 };
 437
 438         if (nphy->hang_avoid)
 439                 b43_nphy_stay_in_carrier_search(dev, 1);
 440
 441         if (nphy->gain_boost) {
 442                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 443                         gain[0] = 6;
 444                         gain[1] = 6;
 445                 } else {
 446                         tmp = 40370 - 315 * dev->phy.channel;
 447                         gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
 448                         tmp = 23242 - 224 * dev->phy.channel;
 449                         gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
 450                 }
 451         } else {
 452                 gain[0] = 0;
 453                 gain[1] = 0;
 454         }
 455
 456         for (i = 0; i < 2; i++) {
 457                 if (nphy->elna_gain_config) {
 458                         data[0] = 19 + gain[i];
 459                         data[1] = 25 + gain[i];
 460                         data[2] = 25 + gain[i];
 461                         data[3] = 25 + gain[i];
 462                 } else {
 463                         data[0] = lna_gain[0] + gain[i];
 464                         data[1] = lna_gain[1] + gain[i];
 465                         data[2] = lna_gain[2] + gain[i];
 466                         data[3] = lna_gain[3] + gain[i];
 467                 }
 468                 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
 469
 470                 minmax[i] = 23 + gain[i];
 471         }
 472
 473         b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
 474                                 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
 475         b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
 476                                 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
 477
 478         if (nphy->hang_avoid)
 479                 b43_nphy_stay_in_carrier_search(dev, 0);
 480 }
 481
 482 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
 483 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
 484                                         u8 *events, u8 *delays, u8 length)
 485 {
 486         struct b43_phy_n *nphy = dev->phy.n;
 487         u8 i;
 488         u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
 489         u16 offset1 = cmd << 4;
 490         u16 offset2 = offset1 + 0x80;
 491
 492         if (nphy->hang_avoid)
 493                 b43_nphy_stay_in_carrier_search(dev, true);
 494
 495         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
 496         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
 497
 498         for (i = length; i < 16; i++) {
 499                 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
 500                 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
 501         }
 502
 503         if (nphy->hang_avoid)
 504                 b43_nphy_stay_in_carrier_search(dev, false);
 505 }
 506
 507 /**************************************************
 508  * Radio 0x2057
 509  **************************************************/
 510
 511 /* http://bcm-v4.sipsolutions.net/PHY/radio2057_rcal */
 512 static u8 b43_radio_2057_rcal(struct b43_wldev *dev)
 513 {
 514         struct b43_phy *phy = &dev->phy;
 515         u16 tmp;
 516
 517         if (phy->radio_rev == 5) {
 518                 b43_phy_mask(dev, 0x342, ~0x2);
 519                 udelay(10);
 520                 b43_radio_set(dev, R2057_IQTEST_SEL_PU, 0x1);
 521                 b43_radio_maskset(dev, 0x1ca, ~0x2, 0x1);
 522         }
 523
 524         b43_radio_set(dev, R2057_RCAL_CONFIG, 0x1);
 525         udelay(10);
 526         b43_radio_set(dev, R2057_RCAL_CONFIG, 0x3);
 527         if (!b43_radio_wait_value(dev, R2057_RCCAL_N1_1, 1, 1, 100, 1000000)) {
 528                 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
 529                 return 0;
 530         }
 531         b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x2);
 532         tmp = b43_radio_read(dev, R2057_RCAL_STATUS) & 0x3E;
 533         b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x1);
 534
 535         if (phy->radio_rev == 5) {
 536                 b43_radio_mask(dev, R2057_IPA2G_CASCONV_CORE0, ~0x1);
 537                 b43_radio_mask(dev, 0x1ca, ~0x2);
 538         }
 539         if (phy->radio_rev <= 4 || phy->radio_rev == 6) {
 540                 b43_radio_maskset(dev, R2057_TEMPSENSE_CONFIG, ~0x3C, tmp);
 541                 b43_radio_maskset(dev, R2057_BANDGAP_RCAL_TRIM, ~0xF0,
 542                                   tmp << 2);
 543         }
 544
 545         return tmp & 0x3e;
 546 }
 547
 548 /* http://bcm-v4.sipsolutions.net/PHY/radio2057_rccal */
 549 static u16 b43_radio_2057_rccal(struct b43_wldev *dev)
 550 {
 551         struct b43_phy *phy = &dev->phy;
 552         bool special = (phy->radio_rev == 3 || phy->radio_rev == 4 ||
 553                         phy->radio_rev == 6);
 554         u16 tmp;
 555
 556         if (special) {
 557                 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x61);
 558                 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xC0);
 559         } else {
 560                 b43_radio_write(dev, 0x1AE, 0x61);
 561                 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xE1);
 562         }
 563         b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
 564         b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
 565         if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
 566                                   5000000))
 567                 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
 568         b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
 569         if (special) {
 570                 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x69);
 571                 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
 572         } else {
 573                 b43_radio_write(dev, 0x1AE, 0x69);
 574                 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xD5);
 575         }
 576         b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
 577         b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
 578         if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
 579                                   5000000))
 580                 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
 581         b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
 582         if (special) {
 583                 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x73);
 584                 b43_radio_write(dev, R2057_RCCAL_X1, 0x28);
 585                 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
 586         } else {
 587                 b43_radio_write(dev, 0x1AE, 0x73);
 588                 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
 589                 b43_radio_write(dev, R2057_RCCAL_TRC0, 0x99);
 590         }
 591         b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
 592         if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
 593                                   5000000)) {
 594                 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
 595                 return 0;
 596         }
 597         tmp = b43_radio_read(dev, R2057_RCCAL_DONE_OSCCAP);
 598         b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
 599         return tmp;
 600 }
 601
 602 static void b43_radio_2057_init_pre(struct b43_wldev *dev)
 603 {
 604         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_CHIP0PU);
 605         /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
 606         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_OEPORFORCE);
 607         b43_phy_set(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
 608         b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_CHIP0PU);
 609 }
 610
 611 static void b43_radio_2057_init_post(struct b43_wldev *dev)
 612 {
 613         b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x1);
 614
 615         b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x78);
 616         b43_radio_set(dev, R2057_XTAL_CONFIG2, 0x80);
 617         mdelay(2);
 618         b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x78);
 619         b43_radio_mask(dev, R2057_XTAL_CONFIG2, ~0x80);
 620
 621         if (dev->phy.n->init_por) {
 622                 b43_radio_2057_rcal(dev);
 623                 b43_radio_2057_rccal(dev);
 624         }
 625         b43_radio_mask(dev, R2057_RFPLL_MASTER, ~0x8);
 626
 627         dev->phy.n->init_por = false;
 628 }
 629
 630 /* http://bcm-v4.sipsolutions.net/802.11/Radio/2057/Init */
 631 static void b43_radio_2057_init(struct b43_wldev *dev)
 632 {
 633         b43_radio_2057_init_pre(dev);
 634         r2057_upload_inittabs(dev);
 635         b43_radio_2057_init_post(dev);
 636 }
 637
 638 /**************************************************
 639  * Radio 0x2056
 640  **************************************************/
 641
 642 static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
 643                                 const struct b43_nphy_channeltab_entry_rev3 *e)
 644 {
 645         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
 646         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
 647         b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
 648         b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
 649         b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
 650         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
 651                                         e->radio_syn_pll_loopfilter1);
 652         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
 653                                         e->radio_syn_pll_loopfilter2);
 654         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
 655                                         e->radio_syn_pll_loopfilter3);
 656         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
 657                                         e->radio_syn_pll_loopfilter4);
 658         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
 659                                         e->radio_syn_pll_loopfilter5);
 660         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
 661                                         e->radio_syn_reserved_addr27);
 662         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
 663                                         e->radio_syn_reserved_addr28);
 664         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
 665                                         e->radio_syn_reserved_addr29);
 666         b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
 667                                         e->radio_syn_logen_vcobuf1);
 668         b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
 669         b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
 670         b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
 671
 672         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
 673                                         e->radio_rx0_lnaa_tune);
 674         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
 675                                         e->radio_rx0_lnag_tune);
 676
 677         b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
 678                                         e->radio_tx0_intpaa_boost_tune);
 679         b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
 680                                         e->radio_tx0_intpag_boost_tune);
 681         b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
 682                                         e->radio_tx0_pada_boost_tune);
 683         b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
 684                                         e->radio_tx0_padg_boost_tune);
 685         b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
 686                                         e->radio_tx0_pgaa_boost_tune);
 687         b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
 688                                         e->radio_tx0_pgag_boost_tune);
 689         b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
 690                                         e->radio_tx0_mixa_boost_tune);
 691         b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
 692                                         e->radio_tx0_mixg_boost_tune);
 693
 694         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
 695                                         e->radio_rx1_lnaa_tune);
 696         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
 697                                         e->radio_rx1_lnag_tune);
 698
 699         b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
 700                                         e->radio_tx1_intpaa_boost_tune);
 701         b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
 702                                         e->radio_tx1_intpag_boost_tune);
 703         b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
 704                                         e->radio_tx1_pada_boost_tune);
 705         b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
 706                                         e->radio_tx1_padg_boost_tune);
 707         b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
 708                                         e->radio_tx1_pgaa_boost_tune);
 709         b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
 710                                         e->radio_tx1_pgag_boost_tune);
 711         b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
 712                                         e->radio_tx1_mixa_boost_tune);
 713         b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
 714                                         e->radio_tx1_mixg_boost_tune);
 715 }
 716
 717 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
 718 static void b43_radio_2056_setup(struct b43_wldev *dev,
 719                                 const struct b43_nphy_channeltab_entry_rev3 *e)
 720 {
 721         struct ssb_sprom *sprom = dev->dev->bus_sprom;
 722         enum ieee80211_band band = b43_current_band(dev->wl);
 723         u16 offset;
 724         u8 i;
 725         u16 bias, cbias;
 726         u16 pag_boost, padg_boost, pgag_boost, mixg_boost;
 727         u16 paa_boost, pada_boost, pgaa_boost, mixa_boost;
 728
 729         B43_WARN_ON(dev->phy.rev < 3);
 730
 731         b43_chantab_radio_2056_upload(dev, e);
 732         b2056_upload_syn_pll_cp2(dev, band == IEEE80211_BAND_5GHZ);
 733
 734         if (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
 735             b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 736                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
 737                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
 738                 if (dev->dev->chip_id == 0x4716) {
 739                         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x14);
 740                         b43_radio_write(dev, B2056_SYN_PLL_CP2, 0);
 741                 } else {
 742                         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0B);
 743                         b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x14);
 744                 }
 745         }
 746         if (sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
 747             b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
 748                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
 749                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
 750                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x05);
 751                 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x0C);
 752         }
 753
 754         if (dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) {
 755                 for (i = 0; i < 2; i++) {
 756                         offset = i ? B2056_TX1 : B2056_TX0;
 757                         if (dev->phy.rev >= 5) {
 758                                 b43_radio_write(dev,
 759                                         offset | B2056_TX_PADG_IDAC, 0xcc);
 760
 761                                 if (dev->dev->chip_id == 0x4716) {
 762                                         bias = 0x40;
 763                                         cbias = 0x45;
 764                                         pag_boost = 0x5;
 765                                         pgag_boost = 0x33;
 766                                         mixg_boost = 0x55;
 767                                 } else {
 768                                         bias = 0x25;
 769                                         cbias = 0x20;
 770                                         pag_boost = 0x4;
 771                                         pgag_boost = 0x03;
 772                                         mixg_boost = 0x65;
 773                                 }
 774                                 padg_boost = 0x77;
 775
 776                                 b43_radio_write(dev,
 777                                         offset | B2056_TX_INTPAG_IMAIN_STAT,
 778                                         bias);
 779                                 b43_radio_write(dev,
 780                                         offset | B2056_TX_INTPAG_IAUX_STAT,
 781                                         bias);
 782                                 b43_radio_write(dev,
 783                                         offset | B2056_TX_INTPAG_CASCBIAS,
 784                                         cbias);
 785                                 b43_radio_write(dev,
 786                                         offset | B2056_TX_INTPAG_BOOST_TUNE,
 787                                         pag_boost);
 788                                 b43_radio_write(dev,
 789                                         offset | B2056_TX_PGAG_BOOST_TUNE,
 790                                         pgag_boost);
 791                                 b43_radio_write(dev,
 792                                         offset | B2056_TX_PADG_BOOST_TUNE,
 793                                         padg_boost);
 794                                 b43_radio_write(dev,
 795                                         offset | B2056_TX_MIXG_BOOST_TUNE,
 796                                         mixg_boost);
 797                         } else {
 798                                 bias = dev->phy.is_40mhz ? 0x40 : 0x20;
 799                                 b43_radio_write(dev,
 800                                         offset | B2056_TX_INTPAG_IMAIN_STAT,
 801                                         bias);
 802                                 b43_radio_write(dev,
 803                                         offset | B2056_TX_INTPAG_IAUX_STAT,
 804                                         bias);
 805                                 b43_radio_write(dev,
 806                                         offset | B2056_TX_INTPAG_CASCBIAS,
 807                                         0x30);
 808                         }
 809                         b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee);
 810                 }
 811         } else if (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ) {
 812                 u16 freq = dev->phy.channel_freq;
 813                 if (freq < 5100) {
 814                         paa_boost = 0xA;
 815                         pada_boost = 0x77;
 816                         pgaa_boost = 0xF;
 817                         mixa_boost = 0xF;
 818                 } else if (freq < 5340) {
 819                         paa_boost = 0x8;
 820                         pada_boost = 0x77;
 821                         pgaa_boost = 0xFB;
 822                         mixa_boost = 0xF;
 823                 } else if (freq < 5650) {
 824                         paa_boost = 0x0;
 825                         pada_boost = 0x77;
 826                         pgaa_boost = 0xB;
 827                         mixa_boost = 0xF;
 828                 } else {
 829                         paa_boost = 0x0;
 830                         pada_boost = 0x77;
 831                         if (freq != 5825)
 832                                 pgaa_boost = -(freq - 18) / 36 + 168;
 833                         else
 834                                 pgaa_boost = 6;
 835                         mixa_boost = 0xF;
 836                 }
 837
 838                 for (i = 0; i < 2; i++) {
 839                         offset = i ? B2056_TX1 : B2056_TX0;
 840
 841                         b43_radio_write(dev,
 842                                 offset | B2056_TX_INTPAA_BOOST_TUNE, paa_boost);
 843                         b43_radio_write(dev,
 844                                 offset | B2056_TX_PADA_BOOST_TUNE, pada_boost);
 845                         b43_radio_write(dev,
 846                                 offset | B2056_TX_PGAA_BOOST_TUNE, pgaa_boost);
 847                         b43_radio_write(dev,
 848                                 offset | B2056_TX_MIXA_BOOST_TUNE, mixa_boost);
 849                         b43_radio_write(dev,
 850                                 offset | B2056_TX_TXSPARE1, 0x30);
 851                         b43_radio_write(dev,
 852                                 offset | B2056_TX_PA_SPARE2, 0xee);
 853                         b43_radio_write(dev,
 854                                 offset | B2056_TX_PADA_CASCBIAS, 0x03);
 855                         b43_radio_write(dev,
 856                                 offset | B2056_TX_INTPAA_IAUX_STAT, 0x50);
 857                         b43_radio_write(dev,
 858                                 offset | B2056_TX_INTPAA_IMAIN_STAT, 0x50);
 859                         b43_radio_write(dev,
 860                                 offset | B2056_TX_INTPAA_CASCBIAS, 0x30);
 861                 }
 862         }
 863
 864         udelay(50);
 865         /* VCO calibration */
 866         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
 867         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
 868         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
 869         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
 870         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
 871         udelay(300);
 872 }
 873
 874 static u8 b43_radio_2056_rcal(struct b43_wldev *dev)
 875 {
 876         struct b43_phy *phy = &dev->phy;
 877         u16 mast2, tmp;
 878
 879         if (phy->rev != 3)
 880                 return 0;
 881
 882         mast2 = b43_radio_read(dev, B2056_SYN_PLL_MAST2);
 883         b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2 | 0x7);
 884
 885         udelay(10);
 886         b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
 887         udelay(10);
 888         b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x09);
 889
 890         if (!b43_radio_wait_value(dev, B2056_SYN_RCAL_CODE_OUT, 0x80, 0x80, 100,
 891                                   1000000)) {
 892                 b43err(dev->wl, "Radio recalibration timeout\n");
 893                 return 0;
 894         }
 895
 896         b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
 897         tmp = b43_radio_read(dev, B2056_SYN_RCAL_CODE_OUT);
 898         b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x00);
 899
 900         b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2);
 901
 902         return tmp & 0x1f;
 903 }
 904
 905 static void b43_radio_init2056_pre(struct b43_wldev *dev)
 906 {
 907         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 908                      ~B43_NPHY_RFCTL_CMD_CHIP0PU);
 909         /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
 910         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 911                      B43_NPHY_RFCTL_CMD_OEPORFORCE);
 912         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 913                     ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
 914         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 915                     B43_NPHY_RFCTL_CMD_CHIP0PU);
 916 }
 917
 918 static void b43_radio_init2056_post(struct b43_wldev *dev)
 919 {
 920         b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
 921         b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
 922         b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
 923         msleep(1);
 924         b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
 925         b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
 926         b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
 927         if (dev->phy.n->init_por)
 928                 b43_radio_2056_rcal(dev);
 929 }
 930
 931 /*
 932  * Initialize a Broadcom 2056 N-radio
 933  * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
 934  */
 935 static void b43_radio_init2056(struct b43_wldev *dev)
 936 {
 937         b43_radio_init2056_pre(dev);
 938         b2056_upload_inittabs(dev, 0, 0);
 939         b43_radio_init2056_post(dev);
 940
 941         dev->phy.n->init_por = false;
 942 }
 943
 944 /**************************************************
 945  * Radio 0x2055
 946  **************************************************/
 947
 948 static void b43_chantab_radio_upload(struct b43_wldev *dev,
 949                                 const struct b43_nphy_channeltab_entry_rev2 *e)
 950 {
 951         b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
 952         b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
 953         b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
 954         b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
 955         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 956
 957         b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
 958         b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
 959         b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
 960         b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
 961         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 962
 963         b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
 964         b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
 965         b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
 966         b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
 967         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 968
 969         b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
 970         b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
 971         b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
 972         b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
 973         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 974
 975         b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
 976         b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
 977         b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
 978         b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
 979         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 980
 981         b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
 982         b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
 983 }
 984
 985 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
 986 static void b43_radio_2055_setup(struct b43_wldev *dev,
 987                                 const struct b43_nphy_channeltab_entry_rev2 *e)
 988 {
 989         B43_WARN_ON(dev->phy.rev >= 3);
 990
 991         b43_chantab_radio_upload(dev, e);
 992         udelay(50);
 993         b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
 994         b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
 995         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 996         b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
 997         udelay(300);
 998 }
 999
1000 static void b43_radio_init2055_pre(struct b43_wldev *dev)
1001 {
1002         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1003                      ~B43_NPHY_RFCTL_CMD_PORFORCE);
1004         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1005                     B43_NPHY_RFCTL_CMD_CHIP0PU |
1006                     B43_NPHY_RFCTL_CMD_OEPORFORCE);
1007         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1008                     B43_NPHY_RFCTL_CMD_PORFORCE);
1009 }
1010
1011 static void b43_radio_init2055_post(struct b43_wldev *dev)
1012 {
1013         struct b43_phy_n *nphy = dev->phy.n;
1014         struct ssb_sprom *sprom = dev->dev->bus_sprom;
1015         bool workaround = false;
1016
1017         if (sprom->revision < 4)
1018                 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
1019                               && dev->dev->board_type == 0x46D
1020                               && dev->dev->board_rev >= 0x41);
1021         else
1022                 workaround =
1023                         !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
1024
1025         b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
1026         if (workaround) {
1027                 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
1028                 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
1029         }
1030         b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
1031         b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
1032         b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
1033         b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
1034         b43_radio_set(dev, B2055_CAL_MISC, 0x1);
1035         msleep(1);
1036         b43_radio_set(dev, B2055_CAL_MISC, 0x40);
1037         if (!b43_radio_wait_value(dev, B2055_CAL_COUT2, 0x80, 0x80, 10, 2000))
1038                 b43err(dev->wl, "radio post init timeout\n");
1039         b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
1040         b43_switch_channel(dev, dev->phy.channel);
1041         b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
1042         b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
1043         b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
1044         b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
1045         b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
1046         b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
1047         if (!nphy->gain_boost) {
1048                 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
1049                 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
1050         } else {
1051                 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
1052                 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
1053         }
1054         udelay(2);
1055 }
1056
1057 /*
1058  * Initialize a Broadcom 2055 N-radio
1059  * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
1060  */
1061 static void b43_radio_init2055(struct b43_wldev *dev)
1062 {
1063         b43_radio_init2055_pre(dev);
1064         if (b43_status(dev) < B43_STAT_INITIALIZED) {
1065                 /* Follow wl, not specs. Do not force uploading all regs */
1066                 b2055_upload_inittab(dev, 0, 0);
1067         } else {
1068                 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
1069                 b2055_upload_inittab(dev, ghz5, 0);
1070         }
1071         b43_radio_init2055_post(dev);
1072 }
1073
1074 /**************************************************
1075  * Samples
1076  **************************************************/
1077
1078 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1079 static int b43_nphy_load_samples(struct b43_wldev *dev,
1080                                         struct b43_c32 *samples, u16 len) {
1081         struct b43_phy_n *nphy = dev->phy.n;
1082         u16 i;
1083         u32 *data;
1084
1085         data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1086         if (!data) {
1087                 b43err(dev->wl, "allocation for samples loading failed\n");
1088                 return -ENOMEM;
1089         }
1090         if (nphy->hang_avoid)
1091                 b43_nphy_stay_in_carrier_search(dev, 1);
1092
1093         for (i = 0; i < len; i++) {
1094                 data[i] = (samples[i].i & 0x3FF << 10);
1095                 data[i] |= samples[i].q & 0x3FF;
1096         }
1097         b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1098
1099         kfree(data);
1100         if (nphy->hang_avoid)
1101                 b43_nphy_stay_in_carrier_search(dev, 0);
1102         return 0;
1103 }
1104
1105 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1106 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1107                                         bool test)
1108 {
1109         int i;
1110         u16 bw, len, rot, angle;
1111         struct b43_c32 *samples;
1112
1113
1114         bw = (dev->phy.is_40mhz) ? 40 : 20;
1115         len = bw << 3;
1116
1117         if (test) {
1118                 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1119                         bw = 82;
1120                 else
1121                         bw = 80;
1122
1123                 if (dev->phy.is_40mhz)
1124                         bw <<= 1;
1125
1126                 len = bw << 1;
1127         }
1128
1129         samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
1130         if (!samples) {
1131                 b43err(dev->wl, "allocation for samples generation failed\n");
1132                 return 0;
1133         }
1134         rot = (((freq * 36) / bw) << 16) / 100;
1135         angle = 0;
1136
1137         for (i = 0; i < len; i++) {
1138                 samples[i] = b43_cordic(angle);
1139                 angle += rot;
1140                 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1141                 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
1142         }
1143
1144         i = b43_nphy_load_samples(dev, samples, len);
1145         kfree(samples);
1146         return (i < 0) ? 0 : len;
1147 }
1148
1149 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1150 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1151                                         u16 wait, bool iqmode, bool dac_test)
1152 {
1153         struct b43_phy_n *nphy = dev->phy.n;
1154         int i;
1155         u16 seq_mode;
1156         u32 tmp;
1157
1158         if (nphy->hang_avoid)
1159                 b43_nphy_stay_in_carrier_search(dev, true);
1160
1161         if ((nphy->bb_mult_save & 0x80000000) == 0) {
1162                 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1163                 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1164         }
1165
1166         if (!dev->phy.is_40mhz)
1167                 tmp = 0x6464;
1168         else
1169                 tmp = 0x4747;
1170         b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1171
1172         if (nphy->hang_avoid)
1173                 b43_nphy_stay_in_carrier_search(dev, false);
1174
1175         b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1176
1177         if (loops != 0xFFFF)
1178                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1179         else
1180                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1181
1182         b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1183
1184         seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1185
1186         b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1187         if (iqmode) {
1188                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1189                 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1190         } else {
1191                 if (dac_test)
1192                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1193                 else
1194                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1195         }
1196         for (i = 0; i < 100; i++) {
1197                 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & 1)) {
1198                         i = 0;
1199                         break;
1200                 }
1201                 udelay(10);
1202         }
1203         if (i)
1204                 b43err(dev->wl, "run samples timeout\n");
1205
1206         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1207 }
1208
1209 /**************************************************
1210  * RSSI
1211  **************************************************/
1212
1213 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1214 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1215                                         s8 offset, u8 core,
1216                                         enum n_rail_type rail,
1217                                         enum b43_nphy_rssi_type rssi_type)
1218 {
1219         u16 tmp;
1220         bool core1or5 = (core == 1) || (core == 5);
1221         bool core2or5 = (core == 2) || (core == 5);
1222
1223         offset = clamp_val(offset, -32, 31);
1224         tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
1225
1226         switch (rssi_type) {
1227         case B43_NPHY_RSSI_Z:
1228                 if (core1or5 && rail == N_RAIL_I)
1229                         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1230                 if (core1or5 && rail == N_RAIL_Q)
1231                         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1232                 if (core2or5 && rail == N_RAIL_I)
1233                         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1234                 if (core2or5 && rail == N_RAIL_Q)
1235                         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1236                 break;
1237         case B43_NPHY_RSSI_X:
1238                 if (core1or5 && rail == N_RAIL_I)
1239                         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1240                 if (core1or5 && rail == N_RAIL_Q)
1241                         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1242                 if (core2or5 && rail == N_RAIL_I)
1243                         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1244                 if (core2or5 && rail == N_RAIL_Q)
1245                         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1246                 break;
1247         case B43_NPHY_RSSI_Y:
1248                 if (core1or5 && rail == N_RAIL_I)
1249                         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1250                 if (core1or5 && rail == N_RAIL_Q)
1251                         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1252                 if (core2or5 && rail == N_RAIL_I)
1253                         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1254                 if (core2or5 && rail == N_RAIL_Q)
1255                         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1256                 break;
1257         case B43_NPHY_RSSI_TBD:
1258                 if (core1or5 && rail == N_RAIL_I)
1259                         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1260                 if (core1or5 && rail == N_RAIL_Q)
1261                         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1262                 if (core2or5 && rail == N_RAIL_I)
1263                         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1264                 if (core2or5 && rail == N_RAIL_Q)
1265                         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1266                 break;
1267         case B43_NPHY_RSSI_PWRDET:
1268                 if (core1or5 && rail == N_RAIL_I)
1269                         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1270                 if (core1or5 && rail == N_RAIL_Q)
1271                         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1272                 if (core2or5 && rail == N_RAIL_I)
1273                         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1274                 if (core2or5 && rail == N_RAIL_Q)
1275                         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1276                 break;
1277         case B43_NPHY_RSSI_TSSI_I:
1278                 if (core1or5)
1279                         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1280                 if (core2or5)
1281                         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1282                 break;
1283         case B43_NPHY_RSSI_TSSI_Q:
1284                 if (core1or5)
1285                         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1286                 if (core2or5)
1287                         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1288                 break;
1289         }
1290 }
1291
1292 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1293 {
1294         u8 i;
1295         u16 reg, val;
1296
1297         if (code == 0) {
1298                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1299                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1300                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1301                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1302                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1303                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1304                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1305                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1306         } else {
1307                 for (i = 0; i < 2; i++) {
1308                         if ((code == 1 && i == 1) || (code == 2 && !i))
1309                                 continue;
1310
1311                         reg = (i == 0) ?
1312                                 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1313                         b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
1314
1315                         if (type < 3) {
1316                                 reg = (i == 0) ?
1317                                         B43_NPHY_AFECTL_C1 :
1318                                         B43_NPHY_AFECTL_C2;
1319                                 b43_phy_maskset(dev, reg, 0xFCFF, 0);
1320
1321                                 reg = (i == 0) ?
1322                                         B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1323                                         B43_NPHY_RFCTL_LUT_TRSW_UP2;
1324                                 b43_phy_maskset(dev, reg, 0xFFC3, 0);
1325
1326                                 if (type == 0)
1327                                         val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
1328                                 else if (type == 1)
1329                                         val = 16;
1330                                 else
1331                                         val = 32;
1332                                 b43_phy_set(dev, reg, val);
1333
1334                                 reg = (i == 0) ?
1335                                         B43_NPHY_TXF_40CO_B1S0 :
1336                                         B43_NPHY_TXF_40CO_B32S1;
1337                                 b43_phy_set(dev, reg, 0x0020);
1338                         } else {
1339                                 if (type == 6)
1340                                         val = 0x0100;
1341                                 else if (type == 3)
1342                                         val = 0x0200;
1343                                 else
1344                                         val = 0x0300;
1345
1346                                 reg = (i == 0) ?
1347                                         B43_NPHY_AFECTL_C1 :
1348                                         B43_NPHY_AFECTL_C2;
1349
1350                                 b43_phy_maskset(dev, reg, 0xFCFF, val);
1351                                 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
1352
1353                                 if (type != 3 && type != 6) {
1354                                         enum ieee80211_band band =
1355                                                 b43_current_band(dev->wl);
1356
1357                                         if (b43_nphy_ipa(dev))
1358                                                 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1359                                         else
1360                                                 val = 0x11;
1361                                         reg = (i == 0) ? 0x2000 : 0x3000;
1362                                         reg |= B2055_PADDRV;
1363                                         b43_radio_write16(dev, reg, val);
1364
1365                                         reg = (i == 0) ?
1366                                                 B43_NPHY_AFECTL_OVER1 :
1367                                                 B43_NPHY_AFECTL_OVER;
1368                                         b43_phy_set(dev, reg, 0x0200);
1369                                 }
1370                         }
1371                 }
1372         }
1373 }
1374
1375 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1376 {
1377         u16 val;
1378
1379         if (type < 3)
1380                 val = 0;
1381         else if (type == 6)
1382                 val = 1;
1383         else if (type == 3)
1384                 val = 2;
1385         else
1386                 val = 3;
1387
1388         val = (val << 12) | (val << 14);
1389         b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1390         b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1391
1392         if (type < 3) {
1393                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1394                                 (type + 1) << 4);
1395                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1396                                 (type + 1) << 4);
1397         }
1398
1399         if (code == 0) {
1400                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
1401                 if (type < 3) {
1402                         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1403                                 ~(B43_NPHY_RFCTL_CMD_RXEN |
1404                                   B43_NPHY_RFCTL_CMD_CORESEL));
1405                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1406                                 ~(0x1 << 12 |
1407                                   0x1 << 5 |
1408                                   0x1 << 1 |
1409                                   0x1));
1410                         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1411                                 ~B43_NPHY_RFCTL_CMD_START);
1412                         udelay(20);
1413                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1414                 }
1415         } else {
1416                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
1417                 if (type < 3) {
1418                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1419                                 ~(B43_NPHY_RFCTL_CMD_RXEN |
1420                                   B43_NPHY_RFCTL_CMD_CORESEL),
1421                                 (B43_NPHY_RFCTL_CMD_RXEN |
1422                                  code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
1423                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
1424                                 (0x1 << 12 |
1425                                   0x1 << 5 |
1426                                   0x1 << 1 |
1427                                   0x1));
1428                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1429                                 B43_NPHY_RFCTL_CMD_START);
1430                         udelay(20);
1431                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1432                 }
1433         }
1434 }
1435
1436 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1437 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1438 {
1439         if (dev->phy.rev >= 3)
1440                 b43_nphy_rev3_rssi_select(dev, code, type);
1441         else
1442                 b43_nphy_rev2_rssi_select(dev, code, type);
1443 }
1444
1445 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1446 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
1447 {
1448         int i;
1449         for (i = 0; i < 2; i++) {
1450                 if (type == 2) {
1451                         if (i == 0) {
1452                                 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1453                                                   0xFC, buf[0]);
1454                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1455                                                   0xFC, buf[1]);
1456                         } else {
1457                                 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1458                                                   0xFC, buf[2 * i]);
1459                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1460                                                   0xFC, buf[2 * i + 1]);
1461                         }
1462                 } else {
1463                         if (i == 0)
1464                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1465                                                   0xF3, buf[0] << 2);
1466                         else
1467                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1468                                                   0xF3, buf[2 * i + 1] << 2);
1469                 }
1470         }
1471 }
1472
1473 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1474 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
1475                                 u8 nsamp)
1476 {
1477         int i;
1478         int out;
1479         u16 save_regs_phy[9];
1480         u16 s[2];
1481
1482         if (dev->phy.rev >= 3) {
1483                 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1484                 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1485                 save_regs_phy[2] = b43_phy_read(dev,
1486                                                 B43_NPHY_RFCTL_LUT_TRSW_UP1);
1487                 save_regs_phy[3] = b43_phy_read(dev,
1488                                                 B43_NPHY_RFCTL_LUT_TRSW_UP2);
1489                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1490                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1491                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1492                 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1493                 save_regs_phy[8] = 0;
1494         } else {
1495                 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1496                 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1497                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1498                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
1499                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
1500                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
1501                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
1502                 save_regs_phy[7] = 0;
1503                 save_regs_phy[8] = 0;
1504         }
1505
1506         b43_nphy_rssi_select(dev, 5, type);
1507
1508         if (dev->phy.rev < 2) {
1509                 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1510                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1511         }
1512
1513         for (i = 0; i < 4; i++)
1514                 buf[i] = 0;
1515
1516         for (i = 0; i < nsamp; i++) {
1517                 if (dev->phy.rev < 2) {
1518                         s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1519                         s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
1520                 } else {
1521                         s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1522                         s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
1523                 }
1524
1525                 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1526                 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1527                 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1528                 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1529         }
1530         out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1531                 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
1532
1533         if (dev->phy.rev < 2)
1534                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
1535
1536         if (dev->phy.rev >= 3) {
1537                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1538                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
1539                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
1540                                 save_regs_phy[2]);
1541                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1542                                 save_regs_phy[3]);
1543                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1544                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1545                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1546                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1547         } else {
1548                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1549                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
1550                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
1551                 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
1552                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
1553                 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
1554                 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
1555         }
1556
1557         return out;
1558 }
1559
1560 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
1561 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1562 {
1563         struct b43_phy_n *nphy = dev->phy.n;
1564
1565         u16 saved_regs_phy_rfctl[2];
1566         u16 saved_regs_phy[13];
1567         u16 regs_to_store[] = {
1568                 B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER,
1569                 B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2,
1570                 B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER,
1571                 B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1,
1572                 B43_NPHY_RFCTL_CMD,
1573                 B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1574                 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2
1575         };
1576
1577         u16 class;
1578
1579         u16 clip_state[2];
1580         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1581
1582         u8 vcm_final = 0;
1583         s32 offset[4];
1584         s32 results[8][4] = { };
1585         s32 results_min[4] = { };
1586         s32 poll_results[4] = { };
1587
1588         u16 *rssical_radio_regs = NULL;
1589         u16 *rssical_phy_regs = NULL;
1590
1591         u16 r; /* routing */
1592         u8 rx_core_state;
1593         u8 core, i, j;
1594
1595         class = b43_nphy_classifier(dev, 0, 0);
1596         b43_nphy_classifier(dev, 7, 4);
1597         b43_nphy_read_clip_detection(dev, clip_state);
1598         b43_nphy_write_clip_detection(dev, clip_off);
1599
1600         saved_regs_phy_rfctl[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1601         saved_regs_phy_rfctl[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1602         for (i = 0; i < ARRAY_SIZE(regs_to_store); i++)
1603                 saved_regs_phy[i] = b43_phy_read(dev, regs_to_store[i]);
1604
1605         b43_nphy_rf_control_intc_override(dev, 0, 0, 7);
1606         b43_nphy_rf_control_intc_override(dev, 1, 1, 7);
1607         b43_nphy_rf_control_override(dev, 0x1, 0, 0, false);
1608         b43_nphy_rf_control_override(dev, 0x2, 1, 0, false);
1609         b43_nphy_rf_control_override(dev, 0x80, 1, 0, false);
1610         b43_nphy_rf_control_override(dev, 0x40, 1, 0, false);
1611
1612         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1613                 b43_nphy_rf_control_override(dev, 0x20, 0, 0, false);
1614                 b43_nphy_rf_control_override(dev, 0x10, 1, 0, false);
1615         } else {
1616                 b43_nphy_rf_control_override(dev, 0x10, 0, 0, false);
1617                 b43_nphy_rf_control_override(dev, 0x20, 1, 0, false);
1618         }
1619
1620         rx_core_state = b43_nphy_get_rx_core_state(dev);
1621         for (core = 0; core < 2; core++) {
1622                 if (!(rx_core_state & (1 << core)))
1623                         continue;
1624                 r = core ? B2056_RX1 : B2056_RX0;
1625                 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_I, 2);
1626                 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_Q, 2);
1627                 for (i = 0; i < 8; i++) {
1628                         b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 0xE3,
1629                                         i << 2);
1630                         b43_nphy_poll_rssi(dev, 2, results[i], 8);
1631                 }
1632                 for (i = 0; i < 4; i += 2) {
1633                         s32 curr;
1634                         s32 mind = 0x100000;
1635                         s32 minpoll = 249;
1636                         u8 minvcm = 0;
1637                         if (2 * core != i)
1638                                 continue;
1639                         for (j = 0; j < 8; j++) {
1640                                 curr = results[j][i] * results[j][i] +
1641                                         results[j][i + 1] * results[j][i];
1642                                 if (curr < mind) {
1643                                         mind = curr;
1644                                         minvcm = j;
1645                                 }
1646                                 if (results[j][i] < minpoll)
1647                                         minpoll = results[j][i];
1648                         }
1649                         vcm_final = minvcm;
1650                         results_min[i] = minpoll;
1651                 }
1652                 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 0xE3,
1653                                   vcm_final << 2);
1654                 for (i = 0; i < 4; i++) {
1655                         if (core != i / 2)
1656                                 continue;
1657                         offset[i] = -results[vcm_final][i];
1658                         if (offset[i] < 0)
1659                                 offset[i] = -((abs(offset[i]) + 4) / 8);
1660                         else
1661                                 offset[i] = (offset[i] + 4) / 8;
1662                         if (results_min[i] == 248)
1663                                 offset[i] = -32;
1664                         b43_nphy_scale_offset_rssi(dev, 0, offset[i],
1665                                                    (i / 2 == 0) ? 1 : 2,
1666                                                    (i % 2 == 0) ? N_RAIL_I : N_RAIL_Q,
1667                                                    2);
1668                 }
1669         }
1670         for (core = 0; core < 2; core++) {
1671                 if (!(rx_core_state & (1 << core)))
1672                         continue;
1673                 for (i = 0; i < 2; i++) {
1674                         b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
1675                                                    N_RAIL_I, i);
1676                         b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
1677                                                    N_RAIL_Q, i);
1678                         b43_nphy_poll_rssi(dev, i, poll_results, 8);
1679                         for (j = 0; j < 4; j++) {
1680                                 if (j / 2 == core) {
1681                                         offset[j] = 232 - poll_results[j];
1682                                         if (offset[j] < 0)
1683                                                 offset[j] = -(abs(offset[j] + 4) / 8);
1684                                         else
1685                                                 offset[j] = (offset[j] + 4) / 8;
1686                                         b43_nphy_scale_offset_rssi(dev, 0,
1687                                                 offset[2 * core], core + 1, j % 2, i);
1688                                 }
1689                         }
1690                 }
1691         }
1692
1693         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, saved_regs_phy_rfctl[0]);
1694         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, saved_regs_phy_rfctl[1]);
1695
1696         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1697
1698         b43_phy_set(dev, B43_NPHY_TXF_40CO_B1S1, 0x1);
1699         b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_START);
1700         b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1);
1701
1702         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1703         b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_RXTX);
1704         b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1);
1705
1706         for (i = 0; i < ARRAY_SIZE(regs_to_store); i++)
1707                 b43_phy_write(dev, regs_to_store[i], saved_regs_phy[i]);
1708
1709         /* Store for future configuration */
1710         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1711                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
1712                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
1713         } else {
1714                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
1715                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
1716         }
1717         rssical_radio_regs[0] = b43_radio_read(dev, 0x602B);
1718         rssical_radio_regs[0] = b43_radio_read(dev, 0x702B);
1719         rssical_phy_regs[0] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Z);
1720         rssical_phy_regs[1] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z);
1721         rssical_phy_regs[2] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Z);
1722         rssical_phy_regs[3] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z);
1723         rssical_phy_regs[4] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_X);
1724         rssical_phy_regs[5] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_X);
1725         rssical_phy_regs[6] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_X);
1726         rssical_phy_regs[7] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_X);
1727         rssical_phy_regs[8] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Y);
1728         rssical_phy_regs[9] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y);
1729         rssical_phy_regs[10] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Y);
1730         rssical_phy_regs[11] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y);
1731
1732         /* Remember for which channel we store configuration */
1733         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1734                 nphy->rssical_chanspec_2G.center_freq = dev->phy.channel_freq;
1735         else
1736                 nphy->rssical_chanspec_5G.center_freq = dev->phy.channel_freq;
1737
1738         /* End of calibration, restore configuration */
1739         b43_nphy_classifier(dev, 7, class);
1740         b43_nphy_write_clip_detection(dev, clip_state);
1741 }
1742
1743 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1744 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
1745 {
1746         int i, j;
1747         u8 state[4];
1748         u8 code, val;
1749         u16 class, override;
1750         u8 regs_save_radio[2];
1751         u16 regs_save_phy[2];
1752
1753         s32 offset[4];
1754         u8 core;
1755         u8 rail;
1756
1757         u16 clip_state[2];
1758         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1759         s32 results_min[4] = { };
1760         u8 vcm_final[4] = { };
1761         s32 results[4][4] = { };
1762         s32 miniq[4][2] = { };
1763
1764         if (type == 2) {
1765                 code = 0;
1766                 val = 6;
1767         } else if (type < 2) {
1768                 code = 25;
1769                 val = 4;
1770         } else {
1771                 B43_WARN_ON(1);
1772                 return;
1773         }
1774
1775         class = b43_nphy_classifier(dev, 0, 0);
1776         b43_nphy_classifier(dev, 7, 4);
1777         b43_nphy_read_clip_detection(dev, clip_state);
1778         b43_nphy_write_clip_detection(dev, clip_off);
1779
1780         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1781                 override = 0x140;
1782         else
1783                 override = 0x110;
1784
1785         regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1786         regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
1787         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1788         b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
1789
1790         regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1791         regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
1792         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1793         b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
1794
1795         state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1796         state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1797         b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1798         b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1799         state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
1800         state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
1801
1802         b43_nphy_rssi_select(dev, 5, type);
1803         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_I, type);
1804         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_Q, type);
1805
1806         for (i = 0; i < 4; i++) {
1807                 u8 tmp[4];
1808                 for (j = 0; j < 4; j++)
1809                         tmp[j] = i;
1810                 if (type != 1)
1811                         b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
1812                 b43_nphy_poll_rssi(dev, type, results[i], 8);
1813                 if (type < 2)
1814                         for (j = 0; j < 2; j++)
1815                                 miniq[i][j] = min(results[i][2 * j],
1816                                                 results[i][2 * j + 1]);
1817         }
1818
1819         for (i = 0; i < 4; i++) {
1820                 s32 mind = 0x100000;
1821                 u8 minvcm = 0;
1822                 s32 minpoll = 249;
1823                 s32 curr;
1824                 for (j = 0; j < 4; j++) {
1825                         if (type == 2)
1826                                 curr = abs(results[j][i]);
1827                         else
1828                                 curr = abs(miniq[j][i / 2] - code * 8);
1829
1830                         if (curr < mind) {
1831                                 mind = curr;
1832                                 minvcm = j;
1833                         }
1834
1835                         if (results[j][i] < minpoll)
1836                                 minpoll = results[j][i];
1837                 }
1838                 results_min[i] = minpoll;
1839                 vcm_final[i] = minvcm;
1840         }
1841
1842         if (type != 1)
1843                 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
1844
1845         for (i = 0; i < 4; i++) {
1846                 offset[i] = (code * 8) - results[vcm_final[i]][i];
1847
1848                 if (offset[i] < 0)
1849                         offset[i] = -((abs(offset[i]) + 4) / 8);
1850                 else
1851                         offset[i] = (offset[i] + 4) / 8;
1852
1853                 if (results_min[i] == 248)
1854                         offset[i] = code - 32;
1855
1856                 core = (i / 2) ? 2 : 1;
1857                 rail = (i % 2) ? N_RAIL_Q : N_RAIL_I;
1858
1859                 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
1860                                                 type);
1861         }
1862
1863         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
1864         b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
1865
1866         switch (state[2]) {
1867         case 1:
1868                 b43_nphy_rssi_select(dev, 1, 2);
1869                 break;
1870         case 4:
1871                 b43_nphy_rssi_select(dev, 1, 0);
1872                 break;
1873         case 2:
1874                 b43_nphy_rssi_select(dev, 1, 1);
1875                 break;
1876         default:
1877                 b43_nphy_rssi_select(dev, 1, 1);
1878                 break;
1879         }
1880
1881         switch (state[3]) {
1882         case 1:
1883                 b43_nphy_rssi_select(dev, 2, 2);
1884                 break;
1885         case 4:
1886                 b43_nphy_rssi_select(dev, 2, 0);
1887                 break;
1888         default:
1889                 b43_nphy_rssi_select(dev, 2, 1);
1890                 break;
1891         }
1892
1893         b43_nphy_rssi_select(dev, 0, type);
1894
1895         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
1896         b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
1897         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
1898         b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
1899
1900         b43_nphy_classifier(dev, 7, class);
1901         b43_nphy_write_clip_detection(dev, clip_state);
1902         /* Specs don't say about reset here, but it makes wl and b43 dumps
1903            identical, it really seems wl performs this */
1904         b43_nphy_reset_cca(dev);
1905 }
1906
1907 /*
1908  * RSSI Calibration
1909  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
1910  */
1911 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
1912 {
1913         if (dev->phy.rev >= 3) {
1914                 b43_nphy_rev3_rssi_cal(dev);
1915         } else {
1916                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Z);
1917                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_X);
1918                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Y);
1919         }
1920 }
1921
1922 /**************************************************
1923  * Workarounds
1924  **************************************************/
1925
1926 static void b43_nphy_gain_ctl_workarounds_rev3plus(struct b43_wldev *dev)
1927 {
1928         struct ssb_sprom *sprom = dev->dev->bus_sprom;
1929
1930         bool ghz5;
1931         bool ext_lna;
1932         u16 rssi_gain;
1933         struct nphy_gain_ctl_workaround_entry *e;
1934         u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
1935         u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
1936
1937         /* Prepare values */
1938         ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
1939                 & B43_NPHY_BANDCTL_5GHZ;
1940         ext_lna = ghz5 ? sprom->boardflags_hi & B43_BFH_EXTLNA_5GHZ :
1941                 sprom->boardflags_lo & B43_BFL_EXTLNA;
1942         e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
1943         if (ghz5 && dev->phy.rev >= 5)
1944                 rssi_gain = 0x90;
1945         else
1946                 rssi_gain = 0x50;
1947
1948         b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
1949
1950         /* Set Clip 2 detect */
1951         b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1952                         B43_NPHY_C1_CGAINI_CL2DETECT);
1953         b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1954                         B43_NPHY_C2_CGAINI_CL2DETECT);
1955
1956         b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1957                         0x17);
1958         b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1959                         0x17);
1960         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
1961         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
1962         b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
1963         b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
1964         b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
1965                         rssi_gain);
1966         b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
1967                         rssi_gain);
1968         b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1969                         0x17);
1970         b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1971                         0x17);
1972         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
1973         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
1974
1975         b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
1976         b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
1977         b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
1978         b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
1979         b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
1980         b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
1981         b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
1982         b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
1983         b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
1984         b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
1985         b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
1986         b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
1987
1988         b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
1989         b43_phy_write(dev, 0x2A7, e->init_gain);
1990         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
1991                                 e->rfseq_init);
1992
1993         /* TODO: check defines. Do not match variables names */
1994         b43_phy_write(dev, B43_NPHY_C1_CLIP1_MEDGAIN, e->cliphi_gain);
1995         b43_phy_write(dev, 0x2A9, e->cliphi_gain);
1996         b43_phy_write(dev, B43_NPHY_C1_CLIP2_GAIN, e->clipmd_gain);
1997         b43_phy_write(dev, 0x2AB, e->clipmd_gain);
1998         b43_phy_write(dev, B43_NPHY_C2_CLIP1_HIGAIN, e->cliplo_gain);
1999         b43_phy_write(dev, 0x2AD, e->cliplo_gain);
2000
2001         b43_phy_maskset(dev, 0x27D, 0xFF00, e->crsmin);
2002         b43_phy_maskset(dev, 0x280, 0xFF00, e->crsminl);
2003         b43_phy_maskset(dev, 0x283, 0xFF00, e->crsminu);
2004         b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
2005         b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
2006         b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
2007                         ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
2008         b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
2009                         ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
2010         b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
2011 }
2012
2013 static void b43_nphy_gain_ctl_workarounds_rev1_2(struct b43_wldev *dev)
2014 {
2015         struct b43_phy_n *nphy = dev->phy.n;
2016
2017         u8 i, j;
2018         u8 code;
2019         u16 tmp;
2020         u8 rfseq_events[3] = { 6, 8, 7 };
2021         u8 rfseq_delays[3] = { 10, 30, 1 };
2022
2023         /* Set Clip 2 detect */
2024         b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
2025         b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
2026
2027         /* Set narrowband clip threshold */
2028         b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
2029         b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
2030
2031         if (!dev->phy.is_40mhz) {
2032                 /* Set dwell lengths */
2033                 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
2034                 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
2035                 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
2036                 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
2037         }
2038
2039         /* Set wideband clip 2 threshold */
2040         b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
2041                         ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, 21);
2042         b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
2043                         ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, 21);
2044
2045         if (!dev->phy.is_40mhz) {
2046                 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
2047                         ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
2048                 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
2049                         ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
2050                 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
2051                         ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
2052                 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
2053                         ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
2054         }
2055
2056         b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
2057
2058         if (nphy->gain_boost) {
2059                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
2060                         dev->phy.is_40mhz)
2061                         code = 4;
2062                 else
2063                         code = 5;
2064         } else {
2065                 code = dev->phy.is_40mhz ? 6 : 7;
2066         }
2067
2068         /* Set HPVGA2 index */
2069         b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, ~B43_NPHY_C1_INITGAIN_HPVGA2,
2070                         code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
2071         b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, ~B43_NPHY_C2_INITGAIN_HPVGA2,
2072                         code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
2073
2074         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2075         /* specs say about 2 loops, but wl does 4 */
2076         for (i = 0; i < 4; i++)
2077                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x7C));
2078
2079         b43_nphy_adjust_lna_gain_table(dev);
2080
2081         if (nphy->elna_gain_config) {
2082                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
2083                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2084                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2085                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2086                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2087
2088                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
2089                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2090                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2091                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2092                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2093
2094                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2095                 /* specs say about 2 loops, but wl does 4 */
2096                 for (i = 0; i < 4; i++)
2097                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
2098                                                 (code << 8 | 0x74));
2099         }
2100
2101         if (dev->phy.rev == 2) {
2102                 for (i = 0; i < 4; i++) {
2103                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
2104                                         (0x0400 * i) + 0x0020);
2105                         for (j = 0; j < 21; j++) {
2106                                 tmp = j * (i < 2 ? 3 : 1);
2107                                 b43_phy_write(dev,
2108                                         B43_NPHY_TABLE_DATALO, tmp);
2109                         }
2110                 }
2111         }
2112
2113         b43_nphy_set_rf_sequence(dev, 5, rfseq_events, rfseq_delays, 3);
2114         b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
2115                 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
2116                 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
2117
2118         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2119                 b43_phy_maskset(dev, B43_PHY_N(0xC5D), 0xFF80, 4);
2120 }
2121
2122 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
2123 static void b43_nphy_gain_ctl_workarounds(struct b43_wldev *dev)
2124 {
2125         if (dev->phy.rev >= 7)
2126                 ; /* TODO */
2127         else if (dev->phy.rev >= 3)
2128                 b43_nphy_gain_ctl_workarounds_rev3plus(dev);
2129         else
2130                 b43_nphy_gain_ctl_workarounds_rev1_2(dev);
2131 }
2132
2133 /* http://bcm-v4.sipsolutions.net/PHY/N/Read_Lpf_Bw_Ctl */
2134 static u16 b43_nphy_read_lpf_ctl(struct b43_wldev *dev, u16 offset)
2135 {
2136         if (!offset)
2137                 offset = (dev->phy.is_40mhz) ? 0x159 : 0x154;
2138         return b43_ntab_read(dev, B43_NTAB16(7, offset)) & 0x7;
2139 }
2140
2141 static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2142 {
2143         struct ssb_sprom *sprom = dev->dev->bus_sprom;
2144         struct b43_phy *phy = &dev->phy;
2145
2146         u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2147                                         0x1F };
2148         u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2149
2150         u16 ntab7_15e_16e[] = { 0x10f, 0x10f };
2151         u8 ntab7_138_146[] = { 0x11, 0x11 };
2152         u8 ntab7_133[] = { 0x77, 0x11, 0x11 };
2153
2154         u16 lpf_20, lpf_40, lpf_11b;
2155         u16 bcap_val, bcap_val_11b, bcap_val_11n_20, bcap_val_11n_40;
2156         u16 scap_val, scap_val_11b, scap_val_11n_20, scap_val_11n_40;
2157         bool rccal_ovrd = false;
2158
2159         u16 rx2tx_lut_20_11b, rx2tx_lut_20_11n, rx2tx_lut_40_11n;
2160         u16 bias, conv, filt;
2161
2162         u32 tmp32;
2163         u8 core;
2164
2165         if (phy->rev == 7) {
2166                 b43_phy_set(dev, B43_NPHY_FINERX2_CGC, 0x10);
2167                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0xFF80, 0x0020);
2168                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0x80FF, 0x2700);
2169                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0xFF80, 0x002E);
2170                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0x80FF, 0x3300);
2171                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0xFF80, 0x0037);
2172                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0x80FF, 0x3A00);
2173                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0xFF80, 0x003C);
2174                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0x80FF, 0x3E00);
2175                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0xFF80, 0x003E);
2176                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0x80FF, 0x3F00);
2177                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0xFF80, 0x0040);
2178                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0x80FF, 0x4000);
2179                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0xFF80, 0x0040);
2180                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0x80FF, 0x4000);
2181                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0xFF80, 0x0040);
2182                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000);
2183         }
2184         if (phy->rev <= 8) {
2185                 b43_phy_write(dev, 0x23F, 0x1B0);
2186                 b43_phy_write(dev, 0x240, 0x1B0);
2187         }
2188         if (phy->rev >= 8)
2189                 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72);
2190
2191         b43_ntab_write(dev, B43_NTAB16(8, 0x00), 2);
2192         b43_ntab_write(dev, B43_NTAB16(8, 0x10), 2);
2193         tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2194         tmp32 &= 0xffffff;
2195         b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
2196         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x15e), 2, ntab7_15e_16e);
2197         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x16e), 2, ntab7_15e_16e);
2198
2199         if (b43_nphy_ipa(dev))
2200                 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2201                                 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
2202
2203         b43_phy_maskset(dev, 0x299, 0x3FFF, 0x4000);
2204         b43_phy_maskset(dev, 0x29D, 0x3FFF, 0x4000);
2205
2206         lpf_20 = b43_nphy_read_lpf_ctl(dev, 0x154);
2207         lpf_40 = b43_nphy_read_lpf_ctl(dev, 0x159);
2208         lpf_11b = b43_nphy_read_lpf_ctl(dev, 0x152);
2209         if (b43_nphy_ipa(dev)) {
2210                 if ((phy->radio_rev == 5 && phy->is_40mhz) ||
2211                     phy->radio_rev == 7 || phy->radio_rev == 8) {
2212                         bcap_val = b43_radio_read(dev, 0x16b);
2213                         scap_val = b43_radio_read(dev, 0x16a);
2214                         scap_val_11b = scap_val;
2215                         bcap_val_11b = bcap_val;
2216                         if (phy->radio_rev == 5 && phy->is_40mhz) {
2217                                 scap_val_11n_20 = scap_val;
2218                                 bcap_val_11n_20 = bcap_val;
2219                                 scap_val_11n_40 = bcap_val_11n_40 = 0xc;
2220                                 rccal_ovrd = true;
2221                         } else { /* Rev 7/8 */
2222                                 lpf_20 = 4;
2223                                 lpf_11b = 1;
2224                                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2225                                         scap_val_11n_20 = 0xc;
2226                                         bcap_val_11n_20 = 0xc;
2227                                         scap_val_11n_40 = 0xa;
2228                                         bcap_val_11n_40 = 0xa;
2229                                 } else {
2230                                         scap_val_11n_20 = 0x14;
2231                                         bcap_val_11n_20 = 0x14;
2232                                         scap_val_11n_40 = 0xf;
2233                                         bcap_val_11n_40 = 0xf;
2234                                 }
2235                                 rccal_ovrd = true;
2236                         }
2237                 }
2238         } else {
2239                 if (phy->radio_rev == 5) {
2240                         lpf_20 = 1;
2241                         lpf_40 = 3;
2242                         bcap_val = b43_radio_read(dev, 0x16b);
2243                         scap_val = b43_radio_read(dev, 0x16a);
2244                         scap_val_11b = scap_val;
2245                         bcap_val_11b = bcap_val;
2246                         scap_val_11n_20 = 0x11;
2247                         scap_val_11n_40 = 0x11;
2248                         bcap_val_11n_20 = 0x13;
2249                         bcap_val_11n_40 = 0x13;
2250                         rccal_ovrd = true;
2251                 }
2252         }
2253         if (rccal_ovrd) {
2254                 rx2tx_lut_20_11b = (bcap_val_11b << 8) |
2255                                    (scap_val_11b << 3) |
2256                                    lpf_11b;
2257                 rx2tx_lut_20_11n = (bcap_val_11n_20 << 8) |
2258                                    (scap_val_11n_20 << 3) |
2259                                    lpf_20;
2260                 rx2tx_lut_40_11n = (bcap_val_11n_40 << 8) |
2261                                    (scap_val_11n_40 << 3) |
2262                                    lpf_40;
2263                 for (core = 0; core < 2; core++) {
2264                         b43_ntab_write(dev, B43_NTAB16(7, 0x152 + core * 16),
2265                                        rx2tx_lut_20_11b);
2266                         b43_ntab_write(dev, B43_NTAB16(7, 0x153 + core * 16),
2267                                        rx2tx_lut_20_11n);
2268                         b43_ntab_write(dev, B43_NTAB16(7, 0x154 + core * 16),
2269                                        rx2tx_lut_20_11n);
2270                         b43_ntab_write(dev, B43_NTAB16(7, 0x155 + core * 16),
2271                                        rx2tx_lut_40_11n);
2272                         b43_ntab_write(dev, B43_NTAB16(7, 0x156 + core * 16),
2273                                        rx2tx_lut_40_11n);
2274                         b43_ntab_write(dev, B43_NTAB16(7, 0x157 + core * 16),
2275                                        rx2tx_lut_40_11n);
2276                         b43_ntab_write(dev, B43_NTAB16(7, 0x158 + core * 16),
2277                                        rx2tx_lut_40_11n);
2278                         b43_ntab_write(dev, B43_NTAB16(7, 0x159 + core * 16),
2279                                        rx2tx_lut_40_11n);
2280                 }
2281                 b43_nphy_rf_control_override_rev7(dev, 16, 1, 3, false, 2);
2282         }
2283         b43_phy_write(dev, 0x32F, 0x3);
2284         if (phy->radio_rev == 4 || phy->radio_rev == 6)
2285                 b43_nphy_rf_control_override_rev7(dev, 4, 1, 3, false, 0);
2286
2287         if (phy->radio_rev == 3 || phy->radio_rev == 4 || phy->radio_rev == 6) {
2288                 if (sprom->revision &&
2289                     sprom->boardflags2_hi & B43_BFH2_IPALVLSHIFT_3P3) {
2290                         b43_radio_write(dev, 0x5, 0x05);
2291                         b43_radio_write(dev, 0x6, 0x30);
2292                         b43_radio_write(dev, 0x7, 0x00);
2293                         b43_radio_set(dev, 0x4f, 0x1);
2294                         b43_radio_set(dev, 0xd4, 0x1);
2295                         bias = 0x1f;
2296                         conv = 0x6f;
2297                         filt = 0xaa;
2298                 } else {
2299                         bias = 0x2b;
2300                         conv = 0x7f;
2301                         filt = 0xee;
2302                 }
2303                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2304                         for (core = 0; core < 2; core++) {
2305                                 if (core == 0) {
2306                                         b43_radio_write(dev, 0x5F, bias);
2307                                         b43_radio_write(dev, 0x64, conv);
2308                                         b43_radio_write(dev, 0x66, filt);
2309                                 } else {
2310                                         b43_radio_write(dev, 0xE8, bias);
2311                                         b43_radio_write(dev, 0xE9, conv);
2312                                         b43_radio_write(dev, 0xEB, filt);
2313                                 }
2314                         }
2315                 }
2316         }
2317
2318         if (b43_nphy_ipa(dev)) {
2319                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2320                         if (phy->radio_rev == 3 || phy->radio_rev == 4 ||
2321                             phy->radio_rev == 6) {
2322                                 for (core = 0; core < 2; core++) {
2323                                         if (core == 0)
2324                                                 b43_radio_write(dev, 0x51,
2325                                                                 0x7f);
2326                                         else
2327                                                 b43_radio_write(dev, 0xd6,
2328                                                                 0x7f);
2329                                 }
2330                         }
2331                         if (phy->radio_rev == 3) {
2332                                 for (core = 0; core < 2; core++) {
2333                                         if (core == 0) {
2334                                                 b43_radio_write(dev, 0x64,
2335                                                                 0x13);
2336                                                 b43_radio_write(dev, 0x5F,
2337                                                                 0x1F);
2338                                                 b43_radio_write(dev, 0x66,
2339                                                                 0xEE);
2340                                                 b43_radio_write(dev, 0x59,
2341                                                                 0x8A);
2342                                                 b43_radio_write(dev, 0x80,
2343                                                                 0x3E);
2344                                         } else {
2345                                                 b43_radio_write(dev, 0x69,
2346                                                                 0x13);
2347                                                 b43_radio_write(dev, 0xE8,
2348                                                                 0x1F);
2349                                                 b43_radio_write(dev, 0xEB,
2350                                                                 0xEE);
2351                                                 b43_radio_write(dev, 0xDE,
2352                                                                 0x8A);
2353                                                 b43_radio_write(dev, 0x105,
2354                                                                 0x3E);
2355                                         }
2356                                 }
2357                         } else if (phy->radio_rev == 7 || phy->radio_rev == 8) {
2358                                 if (!phy->is_40mhz) {
2359                                         b43_radio_write(dev, 0x5F, 0x14);
2360                                         b43_radio_write(dev, 0xE8, 0x12);
2361                                 } else {
2362                                         b43_radio_write(dev, 0x5F, 0x16);
2363                                         b43_radio_write(dev, 0xE8, 0x16);
2364                                 }
2365                         }
2366                 } else {
2367                         u16 freq = phy->channel_freq;
2368                         if ((freq >= 5180 && freq <= 5230) ||
2369                             (freq >= 5745 && freq <= 5805)) {
2370                                 b43_radio_write(dev, 0x7D, 0xFF);
2371                                 b43_radio_write(dev, 0xFE, 0xFF);
2372                         }
2373                 }
2374         } else {
2375                 if (phy->radio_rev != 5) {
2376                         for (core = 0; core < 2; core++) {
2377                                 if (core == 0) {
2378                                         b43_radio_write(dev, 0x5c, 0x61);
2379                                         b43_radio_write(dev, 0x51, 0x70);
2380                                 } else {
2381                                         b43_radio_write(dev, 0xe1, 0x61);
2382                                         b43_radio_write(dev, 0xd6, 0x70);
2383                                 }
2384                         }
2385                 }
2386         }
2387
2388         if (phy->radio_rev == 4) {
2389                 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
2390                 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
2391                 for (core = 0; core < 2; core++) {
2392                         if (core == 0) {
2393                                 b43_radio_write(dev, 0x1a1, 0x00);
2394                                 b43_radio_write(dev, 0x1a2, 0x3f);
2395                                 b43_radio_write(dev, 0x1a6, 0x3f);
2396                         } else {
2397                                 b43_radio_write(dev, 0x1a7, 0x00);
2398                                 b43_radio_write(dev, 0x1ab, 0x3f);
2399                                 b43_radio_write(dev, 0x1ac, 0x3f);
2400                         }
2401                 }
2402         } else {
2403                 b43_phy_set(dev, B43_NPHY_AFECTL_C1, 0x4);
2404                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x4);
2405                 b43_phy_set(dev, B43_NPHY_AFECTL_C2, 0x4);
2406                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4);
2407
2408                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x1);
2409                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x1);
2410                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x1);
2411                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x1);
2412                 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
2413                 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
2414
2415                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x4);
2416                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x4);
2417                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x4);
2418                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4);
2419         }
2420
2421         b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, 0x2);
2422
2423         b43_ntab_write(dev, B43_NTAB32(16, 0x100), 20);
2424         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x138), 2, ntab7_138_146);
2425         b43_ntab_write(dev, B43_NTAB16(7, 0x141), 0x77);
2426         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x133), 3, ntab7_133);
2427         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x146), 2, ntab7_138_146);
2428         b43_ntab_write(dev, B43_NTAB16(7, 0x123), 0x77);
2429         b43_ntab_write(dev, B43_NTAB16(7, 0x12A), 0x77);
2430
2431         if (!phy->is_40mhz) {
2432                 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x18D);
2433                 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x18D);
2434         } else {
2435                 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x14D);
2436                 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x14D);
2437         }
2438
2439         b43_nphy_gain_ctl_workarounds(dev);
2440
2441         /* TODO
2442         b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4,
2443                             aux_adc_vmid_rev7_core0);
2444         b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4,
2445                             aux_adc_vmid_rev7_core1);
2446         b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0C), 4,
2447                             aux_adc_gain_rev7);
2448         b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1C), 4,
2449                             aux_adc_gain_rev7);
2450         */
2451 }
2452
2453 static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
2454 {
2455         struct b43_phy_n *nphy = dev->phy.n;
2456         struct ssb_sprom *sprom = dev->dev->bus_sprom;
2457
2458         /* TX to RX */
2459         u8 tx2rx_events[8] = { 0x4, 0x3, 0x6, 0x5, 0x2, 0x1, 0x8, 0x1F };
2460         u8 tx2rx_delays[8] = { 8, 4, 2, 2, 4, 4, 6, 1 };
2461         /* RX to TX */
2462         u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2463                                         0x1F };
2464         u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2465         u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F };
2466         u8 rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 };
2467
2468         u16 tmp16;
2469         u32 tmp32;
2470
2471         b43_phy_write(dev, 0x23f, 0x1f8);
2472         b43_phy_write(dev, 0x240, 0x1f8);
2473
2474         tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2475         tmp32 &= 0xffffff;
2476         b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
2477
2478         b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
2479         b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
2480         b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
2481         b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
2482         b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
2483         b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
2484
2485         b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C);
2486         b43_phy_write(dev, 0x2AE, 0x000C);
2487
2488         /* TX to RX */
2489         b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
2490                                  ARRAY_SIZE(tx2rx_events));
2491
2492         /* RX to TX */
2493         if (b43_nphy_ipa(dev))
2494                 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2495                                 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
2496         if (nphy->hw_phyrxchain != 3 &&
2497             nphy->hw_phyrxchain != nphy->hw_phytxchain) {
2498                 if (b43_nphy_ipa(dev)) {
2499                         rx2tx_delays[5] = 59;
2500                         rx2tx_delays[6] = 1;
2501                         rx2tx_events[7] = 0x1F;
2502                 }
2503                 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events, rx2tx_delays,
2504                                          ARRAY_SIZE(rx2tx_events));
2505         }
2506
2507         tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
2508                 0x2 : 0x9C40;
2509         b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
2510
2511         b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700);
2512
2513         if (!dev->phy.is_40mhz) {
2514                 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
2515                 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
2516         } else {
2517                 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x14D);
2518                 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x14D);
2519         }
2520
2521         b43_nphy_gain_ctl_workarounds(dev);
2522
2523         b43_ntab_write(dev, B43_NTAB16(8, 0), 2);
2524         b43_ntab_write(dev, B43_NTAB16(8, 16), 2);
2525
2526         /* TODO */
2527
2528         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
2529         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
2530         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
2531         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
2532         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
2533         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
2534         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
2535         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
2536         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
2537         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
2538         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
2539         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
2540
2541         /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
2542
2543         if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
2544              b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
2545             (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
2546              b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
2547                 tmp32 = 0x00088888;
2548         else
2549                 tmp32 = 0x88888888;
2550         b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
2551         b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
2552         b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
2553
2554         if (dev->phy.rev == 4 &&
2555             b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2556                 b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
2557                                 0x70);
2558                 b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
2559                                 0x70);
2560         }
2561
2562         /* Dropped probably-always-true condition */
2563         b43_phy_write(dev, 0x224, 0x03eb);
2564         b43_phy_write(dev, 0x225, 0x03eb);
2565         b43_phy_write(dev, 0x226, 0x0341);
2566         b43_phy_write(dev, 0x227, 0x0341);
2567         b43_phy_write(dev, 0x228, 0x042b);
2568         b43_phy_write(dev, 0x229, 0x042b);
2569         b43_phy_write(dev, 0x22a, 0x0381);
2570         b43_phy_write(dev, 0x22b, 0x0381);
2571         b43_phy_write(dev, 0x22c, 0x042b);
2572         b43_phy_write(dev, 0x22d, 0x042b);
2573         b43_phy_write(dev, 0x22e, 0x0381);
2574         b43_phy_write(dev, 0x22f, 0x0381);
2575
2576         if (dev->phy.rev >= 6 && sprom->boardflags2_lo & B43_BFL2_SINGLEANT_CCK)
2577                 ; /* TODO: 0x0080000000000000 HF */
2578 }
2579
2580 static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
2581 {
2582         struct ssb_sprom *sprom = dev->dev->bus_sprom;
2583         struct b43_phy *phy = &dev->phy;
2584         struct b43_phy_n *nphy = phy->n;
2585
2586         u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
2587         u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
2588
2589         u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
2590         u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
2591
2592         if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
2593             dev->dev->board_type == 0x8B) {
2594                 delays1[0] = 0x1;
2595                 delays1[5] = 0x14;
2596         }
2597
2598         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
2599             nphy->band5g_pwrgain) {
2600                 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
2601                 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
2602         } else {
2603                 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
2604                 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
2605         }
2606
2607         b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
2608         b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
2609         if (dev->phy.rev < 3) {
2610                 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
2611                 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
2612         }
2613
2614         if (dev->phy.rev < 2) {
2615                 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
2616                 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
2617                 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
2618                 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
2619                 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
2620                 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
2621         }
2622
2623         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
2624         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
2625         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
2626         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
2627
2628         b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
2629         b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
2630
2631         b43_nphy_gain_ctl_workarounds(dev);
2632
2633         if (dev->phy.rev < 2) {
2634                 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
2635                         b43_hf_write(dev, b43_hf_read(dev) |
2636                                         B43_HF_MLADVW);
2637         } else if (dev->phy.rev == 2) {
2638                 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
2639                 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
2640         }
2641
2642         if (dev->phy.rev < 2)
2643                 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
2644                                 ~B43_NPHY_SCRAM_SIGCTL_SCM);
2645
2646         /* Set phase track alpha and beta */
2647         b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
2648         b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
2649         b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
2650         b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
2651         b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
2652         b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
2653
2654         if (dev->phy.rev < 3) {
2655                 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
2656                              ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
2657                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
2658                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
2659                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
2660         }
2661
2662         if (dev->phy.rev == 2)
2663                 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
2664                                 B43_NPHY_FINERX2_CGC_DECGC);
2665 }
2666
2667 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
2668 static void b43_nphy_workarounds(struct b43_wldev *dev)
2669 {
2670         struct b43_phy *phy = &dev->phy;
2671         struct b43_phy_n *nphy = phy->n;
2672
2673         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2674                 b43_nphy_classifier(dev, 1, 0);
2675         else
2676                 b43_nphy_classifier(dev, 1, 1);
2677
2678         if (nphy->hang_avoid)
2679                 b43_nphy_stay_in_carrier_search(dev, 1);
2680
2681         b43_phy_set(dev, B43_NPHY_IQFLIP,
2682                     B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
2683
2684         if (dev->phy.rev >= 7)
2685                 b43_nphy_workarounds_rev7plus(dev);
2686         else if (dev->phy.rev >= 3)
2687                 b43_nphy_workarounds_rev3plus(dev);
2688         else
2689                 b43_nphy_workarounds_rev1_2(dev);
2690
2691         if (nphy->hang_avoid)
2692                 b43_nphy_stay_in_carrier_search(dev, 0);
2693 }
2694
2695 /**************************************************
2696  * Tx/Rx common
2697  **************************************************/
2698
2699 /*
2700  * Transmits a known value for LO calibration
2701  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
2702  */
2703 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
2704                                 bool iqmode, bool dac_test)
2705 {
2706         u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
2707         if (samp == 0)
2708                 return -1;
2709         b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
2710         return 0;
2711 }
2712
2713 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
2714 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
2715 {
2716         struct b43_phy_n *nphy = dev->phy.n;
2717
2718         bool override = false;
2719         u16 chain = 0x33;
2720
2721         if (nphy->txrx_chain == 0) {
2722                 chain = 0x11;
2723                 override = true;
2724         } else if (nphy->txrx_chain == 1) {
2725                 chain = 0x22;
2726                 override = true;
2727         }
2728
2729         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2730                         ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
2731                         chain);
2732
2733         if (override)
2734                 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
2735                                 B43_NPHY_RFSEQMODE_CAOVER);
2736         else
2737                 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
2738                                 ~B43_NPHY_RFSEQMODE_CAOVER);
2739 }
2740
2741 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
2742 static void b43_nphy_stop_playback(struct b43_wldev *dev)
2743 {
2744         struct b43_phy_n *nphy = dev->phy.n;
2745         u16 tmp;
2746
2747         if (nphy->hang_avoid)
2748                 b43_nphy_stay_in_carrier_search(dev, 1);
2749
2750         tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
2751         if (tmp & 0x1)
2752                 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
2753         else if (tmp & 0x2)
2754                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
2755
2756         b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
2757
2758         if (nphy->bb_mult_save & 0x80000000) {
2759                 tmp = nphy->bb_mult_save & 0xFFFF;
2760                 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
2761                 nphy->bb_mult_save = 0;
2762         }
2763
2764         if (nphy->hang_avoid)
2765                 b43_nphy_stay_in_carrier_search(dev, 0);
2766 }
2767
2768 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2769 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2770                                         struct nphy_txgains target,
2771                                         struct nphy_iqcal_params *params)
2772 {
2773         int i, j, indx;
2774         u16 gain;
2775
2776         if (dev->phy.rev >= 3) {
2777                 params->txgm = target.txgm[core];
2778                 params->pga = target.pga[core];
2779                 params->pad = target.pad[core];
2780                 params->ipa = target.ipa[core];
2781                 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2782                                         (params->pad << 4) | (params->ipa);
2783                 for (j = 0; j < 5; j++)
2784                         params->ncorr[j] = 0x79;
2785         } else {
2786                 gain = (target.pad[core]) | (target.pga[core] << 4) |
2787                         (target.txgm[core] << 8);
2788
2789                 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2790                         1 : 0;
2791                 for (i = 0; i < 9; i++)
2792                         if (tbl_iqcal_gainparams[indx][i][0] == gain)
2793                                 break;
2794                 i = min(i, 8);
2795
2796                 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2797                 params->pga = tbl_iqcal_gainparams[indx][i][2];
2798                 params->pad = tbl_iqcal_gainparams[indx][i][3];
2799                 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2800                                         (params->pad << 2);
2801                 for (j = 0; j < 4; j++)
2802                         params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2803         }
2804 }
2805
2806 /**************************************************
2807  * Tx and Rx
2808  **************************************************/
2809
2810 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
2811 {//TODO
2812 }
2813
2814 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
2815                                                         bool ignore_tssi)
2816 {//TODO
2817         return B43_TXPWR_RES_DONE;
2818 }
2819
2820 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
2821 static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
2822 {
2823         struct b43_phy_n *nphy = dev->phy.n;
2824         u8 i;
2825         u16 bmask, val, tmp;
2826         enum ieee80211_band band = b43_current_band(dev->wl);
2827
2828         if (nphy->hang_avoid)
2829                 b43_nphy_stay_in_carrier_search(dev, 1);
2830
2831         nphy->txpwrctrl = enable;
2832         if (!enable) {
2833                 if (dev->phy.rev >= 3 &&
2834                     (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) &
2835                      (B43_NPHY_TXPCTL_CMD_COEFF |
2836                       B43_NPHY_TXPCTL_CMD_HWPCTLEN |
2837                       B43_NPHY_TXPCTL_CMD_PCTLEN))) {
2838                         /* We disable enabled TX pwr ctl, save it's state */
2839                         nphy->tx_pwr_idx[0] = b43_phy_read(dev,
2840                                                 B43_NPHY_C1_TXPCTL_STAT) & 0x7f;
2841                         nphy->tx_pwr_idx[1] = b43_phy_read(dev,
2842                                                 B43_NPHY_C2_TXPCTL_STAT) & 0x7f;
2843                 }
2844
2845                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
2846                 for (i = 0; i < 84; i++)
2847                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
2848
2849                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
2850                 for (i = 0; i < 84; i++)
2851                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
2852
2853                 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
2854                 if (dev->phy.rev >= 3)
2855                         tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
2856                 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
2857
2858                 if (dev->phy.rev >= 3) {
2859                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
2860                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
2861                 } else {
2862                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
2863                 }
2864
2865                 if (dev->phy.rev == 2)
2866                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
2867                                 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
2868                 else if (dev->phy.rev < 2)
2869                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
2870                                 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
2871
2872                 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
2873                         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW);
2874         } else {
2875                 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
2876                                     nphy->adj_pwr_tbl);
2877                 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84,
2878                                     nphy->adj_pwr_tbl);
2879
2880                 bmask = B43_NPHY_TXPCTL_CMD_COEFF |
2881                         B43_NPHY_TXPCTL_CMD_HWPCTLEN;
2882                 /* wl does useless check for "enable" param here */
2883                 val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
2884                 if (dev->phy.rev >= 3) {
2885                         bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN;
2886                         if (val)
2887                                 val |= B43_NPHY_TXPCTL_CMD_PCTLEN;
2888                 }
2889                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val);
2890
2891                 if (band == IEEE80211_BAND_5GHZ) {
2892                         b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
2893                                         ~B43_NPHY_TXPCTL_CMD_INIT, 0x64);
2894                         if (dev->phy.rev > 1)
2895                                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
2896                                                 ~B43_NPHY_TXPCTL_INIT_PIDXI1,
2897                                                 0x64);
2898                 }
2899
2900                 if (dev->phy.rev >= 3) {
2901                         if (nphy->tx_pwr_idx[0] != 128 &&
2902                             nphy->tx_pwr_idx[1] != 128) {
2903                                 /* Recover TX pwr ctl state */
2904                                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
2905                                                 ~B43_NPHY_TXPCTL_CMD_INIT,
2906                                                 nphy->tx_pwr_idx[0]);
2907                                 if (dev->phy.rev > 1)
2908                                         b43_phy_maskset(dev,
2909                                                 B43_NPHY_TXPCTL_INIT,
2910                                                 ~0xff, nphy->tx_pwr_idx[1]);
2911                         }
2912                 }
2913
2914                 if (dev->phy.rev >= 3) {
2915                         b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100);
2916                         b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100);
2917                 } else {
2918                         b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000);
2919                 }
2920
2921                 if (dev->phy.rev == 2)
2922                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
2923                 else if (dev->phy.rev < 2)
2924                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40);
2925
2926                 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
2927                         b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW);
2928
2929                 if (b43_nphy_ipa(dev)) {
2930                         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4);
2931                         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4);
2932                 }
2933         }
2934
2935         if (nphy->hang_avoid)
2936                 b43_nphy_stay_in_carrier_search(dev, 0);
2937 }
2938
2939 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
2940 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
2941 {
2942         struct b43_phy_n *nphy = dev->phy.n;
2943         struct ssb_sprom *sprom = dev->dev->bus_sprom;
2944
2945         u8 txpi[2], bbmult, i;
2946         u16 tmp, radio_gain, dac_gain;
2947         u16 freq = dev->phy.channel_freq;
2948         u32 txgain;
2949         /* u32 gaintbl; rev3+ */
2950
2951         if (nphy->hang_avoid)
2952                 b43_nphy_stay_in_carrier_search(dev, 1);
2953
2954         if (dev->phy.rev >= 7) {
2955                 txpi[0] = txpi[1] = 30;
2956         } else if (dev->phy.rev >= 3) {
2957                 txpi[0] = 40;
2958                 txpi[1] = 40;
2959         } else if (sprom->revision < 4) {
2960                 txpi[0] = 72;
2961                 txpi[1] = 72;
2962         } else {
2963                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2964                         txpi[0] = sprom->txpid2g[0];
2965                         txpi[1] = sprom->txpid2g[1];
2966                 } else if (freq >= 4900 && freq < 5100) {
2967                         txpi[0] = sprom->txpid5gl[0];
2968                         txpi[1] = sprom->txpid5gl[1];
2969                 } else if (freq >= 5100 && freq < 5500) {
2970                         txpi[0] = sprom->txpid5g[0];
2971                         txpi[1] = sprom->txpid5g[1];
2972                 } else if (freq >= 5500) {
2973                         txpi[0] = sprom->txpid5gh[0];
2974                         txpi[1] = sprom->txpid5gh[1];
2975                 } else {
2976                         txpi[0] = 91;
2977                         txpi[1] = 91;
2978                 }
2979         }
2980         if (dev->phy.rev < 7 &&
2981             (txpi[0] < 40 || txpi[0] > 100 || txpi[1] < 40 || txpi[1] > 100))
2982                 txpi[0] = txpi[1] = 91;
2983
2984         /*
2985         for (i = 0; i < 2; i++) {
2986                 nphy->txpwrindex[i].index_internal = txpi[i];
2987                 nphy->txpwrindex[i].index_internal_save = txpi[i];
2988         }
2989         */
2990
2991         for (i = 0; i < 2; i++) {
2992                 txgain = *(b43_nphy_get_tx_gain_table(dev) + txpi[i]);
2993
2994                 if (dev->phy.rev >= 3)
2995                         radio_gain = (txgain >> 16) & 0x1FFFF;
2996                 else
2997                         radio_gain = (txgain >> 16) & 0x1FFF;
2998
2999                 if (dev->phy.rev >= 7)
3000                         dac_gain = (txgain >> 8) & 0x7;
3001                 else
3002                         dac_gain = (txgain >> 8) & 0x3F;
3003                 bbmult = txgain & 0xFF;
3004
3005                 if (dev->phy.rev >= 3) {
3006                         if (i == 0)
3007                                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
3008                         else
3009                                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
3010                 } else {
3011                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
3012                 }
3013
3014                 if (i == 0)
3015                         b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
3016                 else
3017                         b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
3018
3019                 b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain);
3020
3021                 tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57));
3022                 if (i == 0)
3023                         tmp = (tmp & 0x00FF) | (bbmult << 8);
3024                 else
3025                         tmp = (tmp & 0xFF00) | bbmult;
3026                 b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp);
3027
3028                 if (b43_nphy_ipa(dev)) {
3029                         u32 tmp32;
3030                         u16 reg = (i == 0) ?
3031                                 B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1;
3032                         tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i,
3033                                                               576 + txpi[i]));
3034                         b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4);
3035                         b43_phy_set(dev, reg, 0x4);
3036                 }
3037         }
3038
3039         b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
3040
3041         if (nphy->hang_avoid)
3042                 b43_nphy_stay_in_carrier_search(dev, 0);
3043 }
3044
3045 static void b43_nphy_ipa_internal_tssi_setup(struct b43_wldev *dev)
3046 {
3047         struct b43_phy *phy = &dev->phy;
3048
3049         u8 core;
3050         u16 r; /* routing */
3051
3052         if (phy->rev >= 7) {
3053                 for (core = 0; core < 2; core++) {
3054                         r = core ? 0x190 : 0x170;
3055                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3056                                 b43_radio_write(dev, r + 0x5, 0x5);
3057                                 b43_radio_write(dev, r + 0x9, 0xE);
3058                                 if (phy->rev != 5)
3059                                         b43_radio_write(dev, r + 0xA, 0);
3060                                 if (phy->rev != 7)
3061                                         b43_radio_write(dev, r + 0xB, 1);
3062                                 else
3063                                         b43_radio_write(dev, r + 0xB, 0x31);
3064                         } else {
3065                                 b43_radio_write(dev, r + 0x5, 0x9);
3066                                 b43_radio_write(dev, r + 0x9, 0xC);
3067                                 b43_radio_write(dev, r + 0xB, 0x0);
3068                                 if (phy->rev != 5)
3069                                         b43_radio_write(dev, r + 0xA, 1);
3070                                 else
3071                                         b43_radio_write(dev, r + 0xA, 0x31);
3072                         }
3073                         b43_radio_write(dev, r + 0x6, 0);
3074                         b43_radio_write(dev, r + 0x7, 0);
3075                         b43_radio_write(dev, r + 0x8, 3);
3076                         b43_radio_write(dev, r + 0xC, 0);
3077                 }
3078         } else {
3079                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3080                         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x128);
3081                 else
3082                         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x80);
3083                 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR30, 0);
3084                 b43_radio_write(dev, B2056_SYN_GPIO_MASTER1, 0x29);
3085
3086                 for (core = 0; core < 2; core++) {
3087                         r = core ? B2056_TX1 : B2056_TX0;
3088
3089                         b43_radio_write(dev, r | B2056_TX_IQCAL_VCM_HG, 0);
3090                         b43_radio_write(dev, r | B2056_TX_IQCAL_IDAC, 0);
3091                         b43_radio_write(dev, r | B2056_TX_TSSI_VCM, 3);
3092                         b43_radio_write(dev, r | B2056_TX_TX_AMP_DET, 0);
3093                         b43_radio_write(dev, r | B2056_TX_TSSI_MISC1, 8);
3094                         b43_radio_write(dev, r | B2056_TX_TSSI_MISC2, 0);
3095                         b43_radio_write(dev, r | B2056_TX_TSSI_MISC3, 0);
3096                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3097                                 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
3098                                                 0x5);
3099                                 if (phy->rev != 5)
3100                                         b43_radio_write(dev, r | B2056_TX_TSSIA,
3101                                                         0x00);
3102                                 if (phy->rev >= 5)
3103                                         b43_radio_write(dev, r | B2056_TX_TSSIG,
3104                                                         0x31);
3105                                 else
3106                                         b43_radio_write(dev, r | B2056_TX_TSSIG,
3107                                                         0x11);
3108                                 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
3109                                                 0xE);
3110                         } else {
3111                                 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
3112                                                 0x9);
3113                                 b43_radio_write(dev, r | B2056_TX_TSSIA, 0x31);
3114                                 b43_radio_write(dev, r | B2056_TX_TSSIG, 0x0);
3115                                 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
3116                                                 0xC);
3117                         }
3118                 }
3119         }
3120 }
3121
3122 /*
3123  * Stop radio and transmit known signal. Then check received signal strength to
3124  * get TSSI (Transmit Signal Strength Indicator).
3125  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlIdleTssi
3126  */
3127 static void b43_nphy_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
3128 {
3129         struct b43_phy *phy = &dev->phy;
3130         struct b43_phy_n *nphy = dev->phy.n;
3131
3132         u32 tmp;
3133         s32 rssi[4] = { };
3134
3135         /* TODO: check if we can transmit */
3136
3137         if (b43_nphy_ipa(dev))
3138                 b43_nphy_ipa_internal_tssi_setup(dev);
3139
3140         if (phy->rev >= 7)
3141                 b43_nphy_rf_control_override_rev7(dev, 0x2000, 0, 3, false, 0);
3142         else if (phy->rev >= 3)
3143                 b43_nphy_rf_control_override(dev, 0x2000, 0, 3, false);
3144
3145         b43_nphy_stop_playback(dev);
3146         b43_nphy_tx_tone(dev, 0xFA0, 0, false, false);
3147         udelay(20);
3148         tmp = b43_nphy_poll_rssi(dev, 4, rssi, 1);
3149         b43_nphy_stop_playback(dev);
3150         b43_nphy_rssi_select(dev, 0, 0);
3151
3152         if (phy->rev >= 7)
3153                 b43_nphy_rf_control_override_rev7(dev, 0x2000, 0, 3, true, 0);
3154         else if (phy->rev >= 3)
3155                 b43_nphy_rf_control_override(dev, 0x2000, 0, 3, true);
3156
3157         if (phy->rev >= 3) {
3158                 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 24) & 0xFF;
3159                 nphy->pwr_ctl_info[1].idle_tssi_5g = (tmp >> 8) & 0xFF;
3160         } else {
3161                 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 16) & 0xFF;
3162                 nphy->pwr_ctl_info[1].idle_tssi_5g = tmp & 0xFF;
3163         }
3164         nphy->pwr_ctl_info[0].idle_tssi_2g = (tmp >> 24) & 0xFF;
3165         nphy->pwr_ctl_info[1].idle_tssi_2g = (tmp >> 8) & 0xFF;
3166 }
3167
3168 /* http://bcm-v4.sipsolutions.net/PHY/N/TxPwrLimitToTbl */
3169 static void b43_nphy_tx_prepare_adjusted_power_table(struct b43_wldev *dev)
3170 {
3171         struct b43_phy_n *nphy = dev->phy.n;
3172
3173         u8 idx, delta;
3174         u8 i, stf_mode;
3175
3176         for (i = 0; i < 4; i++)
3177                 nphy->adj_pwr_tbl[i] = nphy->tx_power_offset[i];
3178
3179         for (stf_mode = 0; stf_mode < 4; stf_mode++) {
3180                 delta = 0;
3181                 switch (stf_mode) {
3182                 case 0:
3183                         if (dev->phy.is_40mhz && dev->phy.rev >= 5) {
3184                                 idx = 68;
3185                         } else {
3186                                 delta = 1;
3187                                 idx = dev->phy.is_40mhz ? 52 : 4;
3188                         }
3189                         break;
3190                 case 1:
3191                         idx = dev->phy.is_40mhz ? 76 : 28;
3192                         break;
3193                 case 2:
3194                         idx = dev->phy.is_40mhz ? 84 : 36;
3195                         break;
3196                 case 3:
3197                         idx = dev->phy.is_40mhz ? 92 : 44;
3198                         break;
3199                 }
3200
3201                 for (i = 0; i < 20; i++) {
3202                         nphy->adj_pwr_tbl[4 + 4 * i + stf_mode] =
3203                                 nphy->tx_power_offset[idx];
3204                         if (i == 0)
3205                                 idx += delta;
3206                         if (i == 14)
3207                                 idx += 1 - delta;
3208                         if (i == 3 || i == 4 || i == 7 || i == 8 || i == 11 ||
3209                             i == 13)
3210                                 idx += 1;
3211                 }
3212         }
3213 }
3214
3215 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlSetup */
3216 static void b43_nphy_tx_power_ctl_setup(struct b43_wldev *dev)
3217 {
3218         struct b43_phy_n *nphy = dev->phy.n;
3219         struct ssb_sprom *sprom = dev->dev->bus_sprom;
3220
3221         s16 a1[2], b0[2], b1[2];
3222         u8 idle[2];
3223         s8 target[2];
3224         s32 num, den, pwr;
3225         u32 regval[64];
3226
3227         u16 freq = dev->phy.channel_freq;
3228         u16 tmp;
3229         u16 r; /* routing */
3230         u8 i, c;
3231
3232         if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
3233                 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
3234                 b43_read32(dev, B43_MMIO_MACCTL);
3235                 udelay(1);
3236         }
3237
3238         if (nphy->hang_avoid)
3239                 b43_nphy_stay_in_carrier_search(dev, true);
3240
3241         b43_phy_set(dev, B43_NPHY_TSSIMODE, B43_NPHY_TSSIMODE_EN);
3242         if (dev->phy.rev >= 3)
3243                 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD,
3244                              ~B43_NPHY_TXPCTL_CMD_PCTLEN & 0xFFFF);
3245         else
3246                 b43_phy_set(dev, B43_NPHY_TXPCTL_CMD,
3247                             B43_NPHY_TXPCTL_CMD_PCTLEN);
3248
3249         if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
3250                 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
3251
3252         if (sprom->revision < 4) {
3253                 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_2g;
3254                 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_2g;
3255                 target[0] = target[1] = 52;
3256                 a1[0] = a1[1] = -424;
3257                 b0[0] = b0[1] = 5612;
3258                 b1[0] = b1[1] = -1393;
3259         } else {
3260                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3261                         for (c = 0; c < 2; c++) {
3262                                 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_2g;
3263                                 target[c] = sprom->core_pwr_info[c].maxpwr_2g;
3264                                 a1[c] = sprom->core_pwr_info[c].pa_2g[0];
3265                                 b0[c] = sprom->core_pwr_info[c].pa_2g[1];
3266                                 b1[c] = sprom->core_pwr_info[c].pa_2g[2];
3267                         }
3268                 } else if (freq >= 4900 && freq < 5100) {
3269                         for (c = 0; c < 2; c++) {
3270                                 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3271                                 target[c] = sprom->core_pwr_info[c].maxpwr_5gl;
3272                                 a1[c] = sprom->core_pwr_info[c].pa_5gl[0];
3273                                 b0[c] = sprom->core_pwr_info[c].pa_5gl[1];
3274                                 b1[c] = sprom->core_pwr_info[c].pa_5gl[2];
3275                         }
3276                 } else if (freq >= 5100 && freq < 5500) {
3277                         for (c = 0; c < 2; c++) {
3278                                 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3279                                 target[c] = sprom->core_pwr_info[c].maxpwr_5g;
3280                                 a1[c] = sprom->core_pwr_info[c].pa_5g[0];
3281                                 b0[c] = sprom->core_pwr_info[c].pa_5g[1];
3282                                 b1[c] = sprom->core_pwr_info[c].pa_5g[2];
3283                         }
3284                 } else if (freq >= 5500) {
3285                         for (c = 0; c < 2; c++) {
3286                                 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3287                                 target[c] = sprom->core_pwr_info[c].maxpwr_5gh;
3288                                 a1[c] = sprom->core_pwr_info[c].pa_5gh[0];
3289                                 b0[c] = sprom->core_pwr_info[c].pa_5gh[1];
3290                                 b1[c] = sprom->core_pwr_info[c].pa_5gh[2];
3291                         }
3292                 } else {
3293                         idle[0] = nphy->pwr_ctl_info[0].idle_tssi_5g;
3294                         idle[1] = nphy->pwr_ctl_info[1].idle_tssi_5g;
3295                         target[0] = target[1] = 52;
3296                         a1[0] = a1[1] = -424;
3297                         b0[0] = b0[1] = 5612;
3298                         b1[0] = b1[1] = -1393;
3299                 }
3300         }
3301         /* target[0] = target[1] = nphy->tx_power_max; */
3302
3303         if (dev->phy.rev >= 3) {
3304                 if (sprom->fem.ghz2.tssipos)
3305                         b43_phy_set(dev, B43_NPHY_TXPCTL_ITSSI, 0x4000);
3306                 if (dev->phy.rev >= 7) {
3307                         for (c = 0; c < 2; c++) {
3308                                 r = c ? 0x190 : 0x170;
3309                                 if (b43_nphy_ipa(dev))
3310                                         b43_radio_write(dev, r + 0x9, (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ? 0xE : 0xC);
3311                         }
3312                 } else {
3313                         if (b43_nphy_ipa(dev)) {
3314                                 tmp = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
3315                                 b43_radio_write(dev,
3316                                         B2056_TX0 | B2056_TX_TX_SSI_MUX, tmp);
3317                                 b43_radio_write(dev,
3318                                         B2056_TX1 | B2056_TX_TX_SSI_MUX, tmp);
3319                         } else {
3320                                 b43_radio_write(dev,
3321                                         B2056_TX0 | B2056_TX_TX_SSI_MUX, 0x11);
3322                                 b43_radio_write(dev,
3323                                         B2056_TX1 | B2056_TX_TX_SSI_MUX, 0x11);
3324                         }
3325                 }
3326         }
3327
3328         if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
3329                 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
3330                 b43_read32(dev, B43_MMIO_MACCTL);
3331                 udelay(1);
3332         }
3333
3334         if (dev->phy.rev >= 7) {
3335                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3336                                 ~B43_NPHY_TXPCTL_CMD_INIT, 0x19);
3337                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3338                                 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x19);
3339         } else {
3340                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3341                                 ~B43_NPHY_TXPCTL_CMD_INIT, 0x40);
3342                 if (dev->phy.rev > 1)
3343                         b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3344                                 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x40);
3345         }
3346
3347         if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
3348                 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
3349
3350         b43_phy_write(dev, B43_NPHY_TXPCTL_N,
3351                       0xF0 << B43_NPHY_TXPCTL_N_TSSID_SHIFT |
3352                       3 << B43_NPHY_TXPCTL_N_NPTIL2_SHIFT);
3353         b43_phy_write(dev, B43_NPHY_TXPCTL_ITSSI,
3354                       idle[0] << B43_NPHY_TXPCTL_ITSSI_0_SHIFT |
3355                       idle[1] << B43_NPHY_TXPCTL_ITSSI_1_SHIFT |
3356                       B43_NPHY_TXPCTL_ITSSI_BINF);
3357         b43_phy_write(dev, B43_NPHY_TXPCTL_TPWR,
3358                       target[0] << B43_NPHY_TXPCTL_TPWR_0_SHIFT |
3359                       target[1] << B43_NPHY_TXPCTL_TPWR_1_SHIFT);
3360
3361         for (c = 0; c < 2; c++) {
3362                 for (i = 0; i < 64; i++) {
3363                         num = 8 * (16 * b0[c] + b1[c] * i);
3364                         den = 32768 + a1[c] * i;
3365                         pwr = max((4 * num + den / 2) / den, -8);
3366                         if (dev->phy.rev < 3 && (i <= (31 - idle[c] + 1)))
3367                                 pwr = max(pwr, target[c] + 1);
3368                         regval[i] = pwr;
3369                 }
3370                 b43_ntab_write_bulk(dev, B43_NTAB32(26 + c, 0), 64, regval);
3371         }
3372
3373         b43_nphy_tx_prepare_adjusted_power_table(dev);
3374         /*
3375         b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84, nphy->adj_pwr_tbl);
3376         b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84, nphy->adj_pwr_tbl);
3377         */
3378
3379         if (nphy->hang_avoid)
3380                 b43_nphy_stay_in_carrier_search(dev, false);
3381 }
3382
3383 static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
3384 {
3385         struct b43_phy *phy = &dev->phy;
3386
3387         const u32 *table = NULL;
3388         u32 rfpwr_offset;
3389         u8 pga_gain;
3390         int i;
3391
3392         table = b43_nphy_get_tx_gain_table(dev);
3393         b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table);
3394         b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table);
3395
3396         if (phy->rev >= 3) {
3397 #if 0
3398                 nphy->gmval = (table[0] >> 16) & 0x7000;
3399 #endif
3400
3401                 for (i = 0; i < 128; i++) {
3402                         pga_gain = (table[i] >> 24) & 0xF;
3403                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3404                                 rfpwr_offset =
3405                                  b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain];
3406                         else
3407                                 rfpwr_offset =
3408                                  0; /* FIXME */
3409                         b43_ntab_write(dev, B43_NTAB32(26, 576 + i),
3410                                        rfpwr_offset);
3411                         b43_ntab_write(dev, B43_NTAB32(27, 576 + i),
3412                                        rfpwr_offset);
3413                 }
3414         }
3415 }
3416
3417 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
3418 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
3419 {
3420         struct b43_phy_n *nphy = dev->phy.n;
3421         enum ieee80211_band band;
3422         u16 tmp;
3423
3424         if (!enable) {
3425                 nphy->rfctrl_intc1_save = b43_phy_read(dev,
3426                                                        B43_NPHY_RFCTL_INTC1);
3427                 nphy->rfctrl_intc2_save = b43_phy_read(dev,
3428                                                        B43_NPHY_RFCTL_INTC2);
3429                 band = b43_current_band(dev->wl);
3430                 if (dev->phy.rev >= 3) {
3431                         if (band == IEEE80211_BAND_5GHZ)
3432                                 tmp = 0x600;
3433                         else
3434                                 tmp = 0x480;
3435                 } else {
3436                         if (band == IEEE80211_BAND_5GHZ)
3437                                 tmp = 0x180;
3438                         else
3439                                 tmp = 0x120;
3440                 }
3441                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
3442                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
3443         } else {
3444                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
3445                                 nphy->rfctrl_intc1_save);
3446                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
3447                                 nphy->rfctrl_intc2_save);
3448         }
3449 }
3450
3451 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
3452 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
3453 {
3454         u16 tmp;
3455
3456         if (dev->phy.rev >= 3) {
3457                 if (b43_nphy_ipa(dev)) {
3458                         tmp = 4;
3459                         b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
3460                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
3461                 }
3462
3463                 tmp = 1;
3464                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
3465                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
3466         }
3467 }
3468
3469 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
3470 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
3471                                 u16 samps, u8 time, bool wait)
3472 {
3473         int i;
3474         u16 tmp;
3475
3476         b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
3477         b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
3478         if (wait)
3479                 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
3480         else
3481                 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
3482
3483         b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
3484
3485         for (i = 1000; i; i--) {
3486                 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
3487                 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
3488                         est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
3489                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
3490                         est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
3491                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
3492                         est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
3493                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
3494
3495                         est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
3496                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
3497                         est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
3498                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
3499                         est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
3500                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
3501                         return;
3502                 }
3503                 udelay(10);
3504         }
3505         memset(est, 0, sizeof(*est));
3506 }
3507
3508 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
3509 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
3510                                         struct b43_phy_n_iq_comp *pcomp)
3511 {
3512         if (write) {
3513                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
3514                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
3515                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
3516                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
3517         } else {
3518                 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
3519                 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
3520                 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
3521                 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
3522         }
3523 }
3524
3525 #if 0
3526 /* Ready but not used anywhere */
3527 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
3528 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
3529 {
3530         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
3531
3532         b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
3533         if (core == 0) {
3534                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
3535                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
3536         } else {
3537                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
3538                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
3539         }
3540         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
3541         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
3542         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
3543         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
3544         b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
3545         b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
3546         b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
3547         b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
3548 }
3549
3550 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
3551 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
3552 {
3553         u8 rxval, txval;
3554         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
3555
3556         regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
3557         if (core == 0) {
3558                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
3559                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
3560         } else {
3561                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
3562                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3563         }
3564         regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
3565         regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
3566         regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
3567         regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
3568         regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
3569         regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
3570         regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
3571         regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
3572
3573         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
3574         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
3575
3576         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
3577                         ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
3578                         ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
3579         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
3580                         ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
3581         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3582                         (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
3583         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
3584                         (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
3585
3586         if (core == 0) {
3587                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
3588                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
3589         } else {
3590                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
3591                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
3592         }
3593
3594         b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
3595         b43_nphy_rf_control_override(dev, 8, 0, 3, false);
3596         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3597
3598         if (core == 0) {
3599                 rxval = 1;
3600                 txval = 8;
3601         } else {
3602                 rxval = 4;
3603                 txval = 2;
3604         }
3605         b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
3606         b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
3607 }
3608 #endif
3609
3610 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
3611 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
3612 {
3613         int i;
3614         s32 iq;
3615         u32 ii;
3616         u32 qq;
3617         int iq_nbits, qq_nbits;
3618         int arsh, brsh;
3619         u16 tmp, a, b;
3620
3621         struct nphy_iq_est est;
3622         struct b43_phy_n_iq_comp old;
3623         struct b43_phy_n_iq_comp new = { };
3624         bool error = false;
3625
3626         if (mask == 0)
3627                 return;
3628
3629         b43_nphy_rx_iq_coeffs(dev, false, &old);
3630         b43_nphy_rx_iq_coeffs(dev, true, &new);
3631         b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
3632         new = old;
3633
3634         for (i = 0; i < 2; i++) {
3635                 if (i == 0 && (mask & 1)) {
3636                         iq = est.iq0_prod;
3637                         ii = est.i0_pwr;
3638                         qq = est.q0_pwr;
3639                 } else if (i == 1 && (mask & 2)) {
3640                         iq = est.iq1_prod;
3641                         ii = est.i1_pwr;
3642                         qq = est.q1_pwr;
3643                 } else {
3644                         continue;
3645                 }
3646
3647                 if (ii + qq < 2) {
3648                         error = true;
3649                         break;
3650                 }
3651
3652                 iq_nbits = fls(abs(iq));
3653                 qq_nbits = fls(qq);
3654
3655                 arsh = iq_nbits - 20;
3656                 if (arsh >= 0) {
3657                         a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
3658                         tmp = ii >> arsh;
3659                 } else {
3660                         a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
3661                         tmp = ii << -arsh;
3662                 }
3663                 if (tmp == 0) {
3664                         error = true;
3665                         break;
3666                 }
3667                 a /= tmp;
3668
3669                 brsh = qq_nbits - 11;
3670                 if (brsh >= 0) {
3671                         b = (qq << (31 - qq_nbits));
3672                         tmp = ii >> brsh;
3673                 } else {
3674                         b = (qq << (31 - qq_nbits));
3675                         tmp = ii << -brsh;
3676                 }
3677                 if (tmp == 0) {
3678                         error = true;
3679                         break;
3680                 }
3681                 b = int_sqrt(b / tmp - a * a) - (1 << 10);
3682
3683                 if (i == 0 && (mask & 0x1)) {
3684                         if (dev->phy.rev >= 3) {
3685                                 new.a0 = a & 0x3FF;
3686                                 new.b0 = b & 0x3FF;
3687                         } else {
3688                                 new.a0 = b & 0x3FF;
3689                                 new.b0 = a & 0x3FF;
3690                         }
3691                 } else if (i == 1 && (mask & 0x2)) {
3692                         if (dev->phy.rev >= 3) {
3693                                 new.a1 = a & 0x3FF;
3694                                 new.b1 = b & 0x3FF;
3695                         } else {
3696                                 new.a1 = b & 0x3FF;
3697                                 new.b1 = a & 0x3FF;
3698                         }
3699                 }
3700         }
3701
3702         if (error)
3703                 new = old;
3704
3705         b43_nphy_rx_iq_coeffs(dev, true, &new);
3706 }
3707
3708 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
3709 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
3710 {
3711         u16 array[4];
3712         b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array);
3713
3714         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
3715         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
3716         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
3717         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
3718 }
3719
3720 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
3721 static void b43_nphy_spur_workaround(struct b43_wldev *dev)
3722 {
3723         struct b43_phy_n *nphy = dev->phy.n;
3724
3725         u8 channel = dev->phy.channel;
3726         int tone[2] = { 57, 58 };
3727         u32 noise[2] = { 0x3FF, 0x3FF };
3728
3729         B43_WARN_ON(dev->phy.rev < 3);
3730
3731         if (nphy->hang_avoid)
3732                 b43_nphy_stay_in_carrier_search(dev, 1);
3733
3734         if (nphy->gband_spurwar_en) {
3735                 /* TODO: N PHY Adjust Analog Pfbw (7) */
3736                 if (channel == 11 && dev->phy.is_40mhz)
3737                         ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
3738                 else
3739                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
3740                 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
3741         }
3742
3743         if (nphy->aband_spurwar_en) {
3744                 if (channel == 54) {
3745                         tone[0] = 0x20;
3746                         noise[0] = 0x25F;
3747                 } else if (channel == 38 || channel == 102 || channel == 118) {
3748                         if (0 /* FIXME */) {
3749                                 tone[0] = 0x20;
3750                                 noise[0] = 0x21F;
3751                         } else {
3752                                 tone[0] = 0;
3753                                 noise[0] = 0;
3754                         }
3755                 } else if (channel == 134) {
3756                         tone[0] = 0x20;
3757                         noise[0] = 0x21F;
3758                 } else if (channel == 151) {
3759                         tone[0] = 0x10;
3760                         noise[0] = 0x23F;
3761                 } else if (channel == 153 || channel == 161) {
3762                         tone[0] = 0x30;
3763                         noise[0] = 0x23F;
3764                 } else {
3765                         tone[0] = 0;
3766                         noise[0] = 0;
3767                 }
3768
3769                 if (!tone[0] && !noise[0])
3770                         ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
3771                 else
3772                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
3773         }
3774
3775         if (nphy->hang_avoid)
3776                 b43_nphy_stay_in_carrier_search(dev, 0);
3777 }
3778
3779 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
3780 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
3781 {
3782         struct b43_phy_n *nphy = dev->phy.n;
3783         int i, j;
3784         u32 tmp;
3785         u32 cur_real, cur_imag, real_part, imag_part;
3786
3787         u16 buffer[7];
3788
3789         if (nphy->hang_avoid)
3790                 b43_nphy_stay_in_carrier_search(dev, true);
3791
3792         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
3793
3794         for (i = 0; i < 2; i++) {
3795                 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
3796                         (buffer[i * 2 + 1] & 0x3FF);
3797                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
3798                                 (((i + 26) << 10) | 320));
3799                 for (j = 0; j < 128; j++) {
3800                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
3801                                         ((tmp >> 16) & 0xFFFF));
3802                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
3803                                         (tmp & 0xFFFF));
3804                 }
3805         }
3806
3807         for (i = 0; i < 2; i++) {
3808                 tmp = buffer[5 + i];
3809                 real_part = (tmp >> 8) & 0xFF;
3810                 imag_part = (tmp & 0xFF);
3811                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
3812                                 (((i + 26) << 10) | 448));
3813
3814                 if (dev->phy.rev >= 3) {
3815                         cur_real = real_part;
3816                         cur_imag = imag_part;
3817                         tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
3818                 }
3819
3820                 for (j = 0; j < 128; j++) {
3821                         if (dev->phy.rev < 3) {
3822                                 cur_real = (real_part * loscale[j] + 128) >> 8;
3823                                 cur_imag = (imag_part * loscale[j] + 128) >> 8;
3824                                 tmp = ((cur_real & 0xFF) << 8) |
3825                                         (cur_imag & 0xFF);
3826                         }
3827                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
3828                                         ((tmp >> 16) & 0xFFFF));
3829                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
3830                                         (tmp & 0xFFFF));
3831                 }
3832         }
3833
3834         if (dev->phy.rev >= 3) {
3835                 b43_shm_write16(dev, B43_SHM_SHARED,
3836                                 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
3837                 b43_shm_write16(dev, B43_SHM_SHARED,
3838                                 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
3839         }
3840
3841         if (nphy->hang_avoid)
3842                 b43_nphy_stay_in_carrier_search(dev, false);
3843 }
3844
3845 /*
3846  * Restore RSSI Calibration
3847  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
3848  */
3849 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
3850 {
3851         struct b43_phy_n *nphy = dev->phy.n;
3852
3853         u16 *rssical_radio_regs = NULL;
3854         u16 *rssical_phy_regs = NULL;
3855
3856         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3857                 if (!nphy->rssical_chanspec_2G.center_freq)
3858                         return;
3859                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
3860                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
3861         } else {
3862                 if (!nphy->rssical_chanspec_5G.center_freq)
3863                         return;
3864                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
3865                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
3866         }
3867
3868         /* TODO use some definitions */
3869         b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
3870         b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
3871
3872         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
3873         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
3874         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
3875         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
3876
3877         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
3878         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
3879         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
3880         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
3881
3882         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
3883         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
3884         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
3885         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
3886 }
3887
3888 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
3889 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
3890 {
3891         struct b43_phy_n *nphy = dev->phy.n;
3892         u16 *save = nphy->tx_rx_cal_radio_saveregs;
3893         u16 tmp;
3894         u8 offset, i;
3895
3896         if (dev->phy.rev >= 3) {
3897             for (i = 0; i < 2; i++) {
3898                 tmp = (i == 0) ? 0x2000 : 0x3000;
3899                 offset = i * 11;
3900
3901                 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
3902                 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
3903                 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
3904                 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
3905                 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
3906                 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
3907                 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
3908                 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
3909                 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
3910                 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
3911                 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
3912
3913                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
3914                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
3915                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
3916                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
3917                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
3918                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
3919                         if (nphy->ipa5g_on) {
3920                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
3921                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
3922                         } else {
3923                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
3924                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
3925                         }
3926                         b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
3927                 } else {
3928                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
3929                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
3930                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
3931                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
3932                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
3933                         b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
3934                         if (nphy->ipa2g_on) {
3935                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
3936                                 b43_radio_write16(dev, tmp | B2055_XOCTL2,
3937                                         (dev->phy.rev < 5) ? 0x11 : 0x01);
3938                         } else {
3939                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
3940                                 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
3941                         }
3942                 }
3943                 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
3944                 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
3945                 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
3946             }
3947         } else {
3948                 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
3949                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
3950
3951                 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
3952                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
3953
3954                 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
3955                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
3956
3957                 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
3958                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
3959
3960                 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
3961                 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
3962
3963                 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
3964                     B43_NPHY_BANDCTL_5GHZ)) {
3965                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
3966                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
3967                 } else {
3968                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
3969                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
3970                 }
3971
3972                 if (dev->phy.rev < 2) {
3973                         b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
3974                         b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
3975                 } else {
3976                         b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
3977                         b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
3978                 }
3979         }
3980 }
3981
3982 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
3983 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
3984 {
3985         struct b43_phy_n *nphy = dev->phy.n;
3986         int i;
3987         u16 scale, entry;
3988
3989         u16 tmp = nphy->txcal_bbmult;
3990         if (core == 0)
3991                 tmp >>= 8;
3992         tmp &= 0xff;
3993
3994         for (i = 0; i < 18; i++) {
3995                 scale = (ladder_lo[i].percent * tmp) / 100;
3996                 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
3997                 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
3998
3999                 scale = (ladder_iq[i].percent * tmp) / 100;
4000                 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
4001                 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
4002         }
4003 }
4004
4005 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
4006 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
4007 {
4008         int i;
4009         for (i = 0; i < 15; i++)
4010                 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
4011                                 tbl_tx_filter_coef_rev4[2][i]);
4012 }
4013
4014 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
4015 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
4016 {
4017         int i, j;
4018         /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
4019         static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
4020
4021         for (i = 0; i < 3; i++)
4022                 for (j = 0; j < 15; j++)
4023                         b43_phy_write(dev, B43_PHY_N(offset[i] + j),
4024                                         tbl_tx_filter_coef_rev4[i][j]);
4025
4026         if (dev->phy.is_40mhz) {
4027                 for (j = 0; j < 15; j++)
4028                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4029                                         tbl_tx_filter_coef_rev4[3][j]);
4030         } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
4031                 for (j = 0; j < 15; j++)
4032                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4033                                         tbl_tx_filter_coef_rev4[5][j]);
4034         }
4035
4036         if (dev->phy.channel == 14)
4037                 for (j = 0; j < 15; j++)
4038                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4039                                         tbl_tx_filter_coef_rev4[6][j]);
4040 }
4041
4042 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
4043 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
4044 {
4045         struct b43_phy_n *nphy = dev->phy.n;
4046
4047         u16 curr_gain[2];
4048         struct nphy_txgains target;
4049         const u32 *table = NULL;
4050
4051         if (!nphy->txpwrctrl) {
4052                 int i;
4053
4054                 if (nphy->hang_avoid)
4055                         b43_nphy_stay_in_carrier_search(dev, true);
4056                 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
4057                 if (nphy->hang_avoid)
4058                         b43_nphy_stay_in_carrier_search(dev, false);
4059
4060                 for (i = 0; i < 2; ++i) {
4061                         if (dev->phy.rev >= 3) {
4062                                 target.ipa[i] = curr_gain[i] & 0x000F;
4063                                 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
4064                                 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
4065                                 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
4066                         } else {
4067                                 target.ipa[i] = curr_gain[i] & 0x0003;
4068                                 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
4069                                 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
4070                                 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
4071                         }
4072                 }
4073         } else {
4074                 int i;
4075                 u16 index[2];
4076                 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
4077                         B43_NPHY_TXPCTL_STAT_BIDX) >>
4078                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
4079                 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
4080                         B43_NPHY_TXPCTL_STAT_BIDX) >>
4081                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
4082
4083                 for (i = 0; i < 2; ++i) {
4084                         table = b43_nphy_get_tx_gain_table(dev);
4085                         if (dev->phy.rev >= 3) {
4086                                 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
4087                                 target.pad[i] = (table[index[i]] >> 20) & 0xF;
4088                                 target.pga[i] = (table[index[i]] >> 24) & 0xF;
4089                                 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
4090                         } else {
4091                                 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
4092                                 target.pad[i] = (table[index[i]] >> 18) & 0x3;
4093                                 target.pga[i] = (table[index[i]] >> 20) & 0x7;
4094                                 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
4095                         }
4096                 }
4097         }
4098
4099         return target;
4100 }
4101
4102 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
4103 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
4104 {
4105         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4106
4107         if (dev->phy.rev >= 3) {
4108                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
4109                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
4110                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
4111                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
4112                 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
4113                 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
4114                 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
4115                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
4116                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
4117                 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
4118                 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
4119                 b43_nphy_reset_cca(dev);
4120         } else {
4121                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
4122                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
4123                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
4124                 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
4125                 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
4126                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
4127                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
4128         }
4129 }
4130
4131 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
4132 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
4133 {
4134         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4135         u16 tmp;
4136
4137         regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
4138         regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
4139         if (dev->phy.rev >= 3) {
4140                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
4141                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
4142
4143                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
4144                 regs[2] = tmp;
4145                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
4146
4147                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4148                 regs[3] = tmp;
4149                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
4150
4151                 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
4152                 b43_phy_mask(dev, B43_NPHY_BBCFG,
4153                              ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
4154
4155                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
4156                 regs[5] = tmp;
4157                 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
4158
4159                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
4160                 regs[6] = tmp;
4161                 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
4162                 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4163                 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4164
4165                 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
4166                 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
4167                 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
4168
4169                 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
4170                 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
4171                 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
4172                 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
4173         } else {
4174                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
4175                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
4176                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4177                 regs[2] = tmp;
4178                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
4179                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
4180                 regs[3] = tmp;
4181                 tmp |= 0x2000;
4182                 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
4183                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
4184                 regs[4] = tmp;
4185                 tmp |= 0x2000;
4186                 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
4187                 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4188                 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4189                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
4190                         tmp = 0x0180;
4191                 else
4192                         tmp = 0x0120;
4193                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
4194                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
4195         }
4196 }
4197
4198 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
4199 static void b43_nphy_save_cal(struct b43_wldev *dev)
4200 {
4201         struct b43_phy_n *nphy = dev->phy.n;
4202
4203         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
4204         u16 *txcal_radio_regs = NULL;
4205         struct b43_chanspec *iqcal_chanspec;
4206         u16 *table = NULL;
4207
4208         if (nphy->hang_avoid)
4209                 b43_nphy_stay_in_carrier_search(dev, 1);
4210
4211         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4212                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
4213                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
4214                 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
4215                 table = nphy->cal_cache.txcal_coeffs_2G;
4216         } else {
4217                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
4218                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
4219                 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
4220                 table = nphy->cal_cache.txcal_coeffs_5G;
4221         }
4222
4223         b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
4224         /* TODO use some definitions */
4225         if (dev->phy.rev >= 3) {
4226                 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
4227                 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
4228                 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
4229                 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
4230                 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
4231                 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
4232                 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
4233                 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
4234         } else {
4235                 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
4236                 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
4237                 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
4238                 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
4239         }
4240         iqcal_chanspec->center_freq = dev->phy.channel_freq;
4241         iqcal_chanspec->channel_type = dev->phy.channel_type;
4242         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
4243
4244         if (nphy->hang_avoid)
4245                 b43_nphy_stay_in_carrier_search(dev, 0);
4246 }
4247
4248 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
4249 static void b43_nphy_restore_cal(struct b43_wldev *dev)
4250 {
4251         struct b43_phy_n *nphy = dev->phy.n;
4252
4253         u16 coef[4];
4254         u16 *loft = NULL;
4255         u16 *table = NULL;
4256
4257         int i;
4258         u16 *txcal_radio_regs = NULL;
4259         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
4260
4261         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4262                 if (!nphy->iqcal_chanspec_2G.center_freq)
4263                         return;
4264                 table = nphy->cal_cache.txcal_coeffs_2G;
4265                 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
4266         } else {
4267                 if (!nphy->iqcal_chanspec_5G.center_freq)
4268                         return;
4269                 table = nphy->cal_cache.txcal_coeffs_5G;
4270                 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
4271         }
4272
4273         b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
4274
4275         for (i = 0; i < 4; i++) {
4276                 if (dev->phy.rev >= 3)
4277                         table[i] = coef[i];
4278                 else
4279                         coef[i] = 0;
4280         }
4281
4282         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
4283         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
4284         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
4285
4286         if (dev->phy.rev < 2)
4287                 b43_nphy_tx_iq_workaround(dev);
4288
4289         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4290                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
4291                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
4292         } else {
4293                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
4294                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
4295         }
4296
4297         /* TODO use some definitions */
4298         if (dev->phy.rev >= 3) {
4299                 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
4300                 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
4301                 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
4302                 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
4303                 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
4304                 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
4305                 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
4306                 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
4307         } else {
4308                 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
4309                 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
4310                 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
4311                 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
4312         }
4313         b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
4314 }
4315
4316 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
4317 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
4318                                 struct nphy_txgains target,
4319                                 bool full, bool mphase)
4320 {
4321         struct b43_phy_n *nphy = dev->phy.n;
4322         int i;
4323         int error = 0;
4324         int freq;
4325         bool avoid = false;
4326         u8 length;
4327         u16 tmp, core, type, count, max, numb, last = 0, cmd;
4328         const u16 *table;
4329         bool phy6or5x;
4330
4331         u16 buffer[11];
4332         u16 diq_start = 0;
4333         u16 save[2];
4334         u16 gain[2];
4335         struct nphy_iqcal_params params[2];
4336         bool updated[2] = { };
4337
4338         b43_nphy_stay_in_carrier_search(dev, true);
4339
4340         if (dev->phy.rev >= 4) {
4341                 avoid = nphy->hang_avoid;
4342                 nphy->hang_avoid = false;
4343         }
4344
4345         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
4346
4347         for (i = 0; i < 2; i++) {
4348                 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
4349                 gain[i] = params[i].cal_gain;
4350         }
4351
4352         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
4353
4354         b43_nphy_tx_cal_radio_setup(dev);
4355         b43_nphy_tx_cal_phy_setup(dev);
4356
4357         phy6or5x = dev->phy.rev >= 6 ||
4358                 (dev->phy.rev == 5 && nphy->ipa2g_on &&
4359                 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
4360         if (phy6or5x) {
4361                 if (dev->phy.is_40mhz) {
4362                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
4363                                         tbl_tx_iqlo_cal_loft_ladder_40);
4364                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
4365                                         tbl_tx_iqlo_cal_iqimb_ladder_40);
4366                 } else {
4367                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
4368                                         tbl_tx_iqlo_cal_loft_ladder_20);
4369                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
4370                                         tbl_tx_iqlo_cal_iqimb_ladder_20);
4371                 }
4372         }
4373
4374         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
4375
4376         if (!dev->phy.is_40mhz)
4377                 freq = 2500;
4378         else
4379                 freq = 5000;
4380
4381         if (nphy->mphase_cal_phase_id > 2)
4382                 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
4383                                         0xFFFF, 0, true, false);
4384         else
4385                 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
4386
4387         if (error == 0) {
4388                 if (nphy->mphase_cal_phase_id > 2) {
4389                         table = nphy->mphase_txcal_bestcoeffs;
4390                         length = 11;
4391                         if (dev->phy.rev < 3)
4392                                 length -= 2;
4393                 } else {
4394                         if (!full && nphy->txiqlocal_coeffsvalid) {
4395                                 table = nphy->txiqlocal_bestc;
4396                                 length = 11;
4397                                 if (dev->phy.rev < 3)
4398                                         length -= 2;
4399                         } else {
4400                                 full = true;
4401                                 if (dev->phy.rev >= 3) {
4402                                         table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
4403                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
4404                                 } else {
4405                                         table = tbl_tx_iqlo_cal_startcoefs;
4406                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
4407                                 }
4408                         }
4409                 }
4410
4411                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
4412
4413                 if (full) {
4414                         if (dev->phy.rev >= 3)
4415                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
4416                         else
4417                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
4418                 } else {
4419                         if (dev->phy.rev >= 3)
4420                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
4421                         else
4422                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
4423                 }
4424
4425                 if (mphase) {
4426                         count = nphy->mphase_txcal_cmdidx;
4427                         numb = min(max,
4428                                 (u16)(count + nphy->mphase_txcal_numcmds));
4429                 } else {
4430                         count = 0;
4431                         numb = max;
4432                 }
4433
4434                 for (; count < numb; count++) {
4435                         if (full) {
4436                                 if (dev->phy.rev >= 3)
4437                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
4438                                 else
4439                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
4440                         } else {
4441                                 if (dev->phy.rev >= 3)
4442                                         cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
4443                                 else
4444                                         cmd = tbl_tx_iqlo_cal_cmds_recal[count];
4445                         }
4446
4447                         core = (cmd & 0x3000) >> 12;
4448                         type = (cmd & 0x0F00) >> 8;
4449
4450                         if (phy6or5x && updated[core] == 0) {
4451                                 b43_nphy_update_tx_cal_ladder(dev, core);
4452                                 updated[core] = true;
4453                         }
4454
4455                         tmp = (params[core].ncorr[type] << 8) | 0x66;
4456                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
4457
4458                         if (type == 1 || type == 3 || type == 4) {
4459                                 buffer[0] = b43_ntab_read(dev,
4460                                                 B43_NTAB16(15, 69 + core));
4461                                 diq_start = buffer[0];
4462                                 buffer[0] = 0;
4463                                 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
4464                                                 0);
4465                         }
4466
4467                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
4468                         for (i = 0; i < 2000; i++) {
4469                                 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
4470                                 if (tmp & 0xC000)
4471                                         break;
4472                                 udelay(10);
4473                         }
4474
4475                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4476                                                 buffer);
4477                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
4478                                                 buffer);
4479
4480                         if (type == 1 || type == 3 || type == 4)
4481                                 buffer[0] = diq_start;
4482                 }
4483
4484                 if (mphase)
4485                         nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
4486
4487                 last = (dev->phy.rev < 3) ? 6 : 7;
4488
4489                 if (!mphase || nphy->mphase_cal_phase_id == last) {
4490                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
4491                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
4492                         if (dev->phy.rev < 3) {
4493                                 buffer[0] = 0;
4494                                 buffer[1] = 0;
4495                                 buffer[2] = 0;
4496                                 buffer[3] = 0;
4497                         }
4498                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
4499                                                 buffer);
4500                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
4501                                                 buffer);
4502                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
4503                                                 buffer);
4504                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
4505                                                 buffer);
4506                         length = 11;
4507                         if (dev->phy.rev < 3)
4508                                 length -= 2;
4509                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4510                                                 nphy->txiqlocal_bestc);
4511                         nphy->txiqlocal_coeffsvalid = true;
4512                         nphy->txiqlocal_chanspec.center_freq =
4513                                                         dev->phy.channel_freq;
4514                         nphy->txiqlocal_chanspec.channel_type =
4515                                                         dev->phy.channel_type;
4516                 } else {
4517                         length = 11;
4518                         if (dev->phy.rev < 3)
4519                                 length -= 2;
4520                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4521                                                 nphy->mphase_txcal_bestcoeffs);
4522                 }
4523
4524                 b43_nphy_stop_playback(dev);
4525                 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
4526         }
4527
4528         b43_nphy_tx_cal_phy_cleanup(dev);
4529         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
4530
4531         if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
4532                 b43_nphy_tx_iq_workaround(dev);
4533
4534         if (dev->phy.rev >= 4)
4535                 nphy->hang_avoid = avoid;
4536
4537         b43_nphy_stay_in_carrier_search(dev, false);
4538
4539         return error;
4540 }
4541
4542 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
4543 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
4544 {
4545         struct b43_phy_n *nphy = dev->phy.n;
4546         u8 i;
4547         u16 buffer[7];
4548         bool equal = true;
4549
4550         if (!nphy->txiqlocal_coeffsvalid ||
4551             nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
4552             nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
4553                 return;
4554
4555         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
4556         for (i = 0; i < 4; i++) {
4557                 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
4558                         equal = false;
4559                         break;
4560                 }
4561         }
4562
4563         if (!equal) {
4564                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
4565                                         nphy->txiqlocal_bestc);
4566                 for (i = 0; i < 4; i++)
4567                         buffer[i] = 0;
4568                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
4569                                         buffer);
4570                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
4571                                         &nphy->txiqlocal_bestc[5]);
4572                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
4573                                         &nphy->txiqlocal_bestc[5]);
4574         }
4575 }
4576
4577 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
4578 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
4579                         struct nphy_txgains target, u8 type, bool debug)
4580 {
4581         struct b43_phy_n *nphy = dev->phy.n;
4582         int i, j, index;
4583         u8 rfctl[2];
4584         u8 afectl_core;
4585         u16 tmp[6];
4586         u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
4587         u32 real, imag;
4588         enum ieee80211_band band;
4589
4590         u8 use;
4591         u16 cur_hpf;
4592         u16 lna[3] = { 3, 3, 1 };
4593         u16 hpf1[3] = { 7, 2, 0 };
4594         u16 hpf2[3] = { 2, 0, 0 };
4595         u32 power[3] = { };
4596         u16 gain_save[2];
4597         u16 cal_gain[2];
4598         struct nphy_iqcal_params cal_params[2];
4599         struct nphy_iq_est est;
4600         int ret = 0;
4601         bool playtone = true;
4602         int desired = 13;
4603
4604         b43_nphy_stay_in_carrier_search(dev, 1);
4605
4606         if (dev->phy.rev < 2)
4607                 b43_nphy_reapply_tx_cal_coeffs(dev);
4608         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
4609         for (i = 0; i < 2; i++) {
4610                 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
4611                 cal_gain[i] = cal_params[i].cal_gain;
4612         }
4613         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
4614
4615         for (i = 0; i < 2; i++) {
4616                 if (i == 0) {
4617                         rfctl[0] = B43_NPHY_RFCTL_INTC1;
4618                         rfctl[1] = B43_NPHY_RFCTL_INTC2;
4619                         afectl_core = B43_NPHY_AFECTL_C1;
4620                 } else {
4621                         rfctl[0] = B43_NPHY_RFCTL_INTC2;
4622                         rfctl[1] = B43_NPHY_RFCTL_INTC1;
4623                         afectl_core = B43_NPHY_AFECTL_C2;
4624                 }
4625
4626                 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
4627                 tmp[2] = b43_phy_read(dev, afectl_core);
4628                 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4629                 tmp[4] = b43_phy_read(dev, rfctl[0]);
4630                 tmp[5] = b43_phy_read(dev, rfctl[1]);
4631
4632                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
4633                                 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
4634                                 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
4635                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
4636                                 (1 - i));
4637                 b43_phy_set(dev, afectl_core, 0x0006);
4638                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
4639
4640                 band = b43_current_band(dev->wl);
4641
4642                 if (nphy->rxcalparams & 0xFF000000) {
4643                         if (band == IEEE80211_BAND_5GHZ)
4644                                 b43_phy_write(dev, rfctl[0], 0x140);
4645                         else
4646                                 b43_phy_write(dev, rfctl[0], 0x110);
4647                 } else {
4648                         if (band == IEEE80211_BAND_5GHZ)
4649                                 b43_phy_write(dev, rfctl[0], 0x180);
4650                         else
4651                                 b43_phy_write(dev, rfctl[0], 0x120);
4652                 }
4653
4654                 if (band == IEEE80211_BAND_5GHZ)
4655                         b43_phy_write(dev, rfctl[1], 0x148);
4656                 else
4657                         b43_phy_write(dev, rfctl[1], 0x114);
4658
4659                 if (nphy->rxcalparams & 0x10000) {
4660                         b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
4661                                         (i + 1));
4662                         b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
4663                                         (2 - i));
4664                 }
4665
4666                 for (j = 0; j < 4; j++) {
4667                         if (j < 3) {
4668                                 cur_lna = lna[j];
4669                                 cur_hpf1 = hpf1[j];
4670                                 cur_hpf2 = hpf2[j];
4671                         } else {
4672                                 if (power[1] > 10000) {
4673                                         use = 1;
4674                                         cur_hpf = cur_hpf1;
4675                                         index = 2;
4676                                 } else {
4677                                         if (power[0] > 10000) {
4678                                                 use = 1;
4679                                                 cur_hpf = cur_hpf1;
4680                                                 index = 1;
4681                                         } else {
4682                                                 index = 0;
4683                                                 use = 2;
4684                                                 cur_hpf = cur_hpf2;
4685                                         }
4686                                 }
4687                                 cur_lna = lna[index];
4688                                 cur_hpf1 = hpf1[index];
4689                                 cur_hpf2 = hpf2[index];
4690                                 cur_hpf += desired - hweight32(power[index]);
4691                                 cur_hpf = clamp_val(cur_hpf, 0, 10);
4692                                 if (use == 1)
4693                                         cur_hpf1 = cur_hpf;
4694                                 else
4695                                         cur_hpf2 = cur_hpf;
4696                         }
4697
4698                         tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
4699                                         (cur_lna << 2));
4700                         b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
4701                                                                         false);
4702                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
4703                         b43_nphy_stop_playback(dev);
4704
4705                         if (playtone) {
4706                                 ret = b43_nphy_tx_tone(dev, 4000,
4707                                                 (nphy->rxcalparams & 0xFFFF),
4708                                                 false, false);
4709                                 playtone = false;
4710                         } else {
4711                                 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
4712                                                         false, false);
4713                         }
4714
4715                         if (ret == 0) {
4716                                 if (j < 3) {
4717                                         b43_nphy_rx_iq_est(dev, &est, 1024, 32,
4718                                                                         false);
4719                                         if (i == 0) {
4720                                                 real = est.i0_pwr;
4721                                                 imag = est.q0_pwr;
4722                                         } else {
4723                                                 real = est.i1_pwr;
4724                                                 imag = est.q1_pwr;
4725                                         }
4726                                         power[i] = ((real + imag) / 1024) + 1;
4727                                 } else {
4728                                         b43_nphy_calc_rx_iq_comp(dev, 1 << i);
4729                                 }
4730                                 b43_nphy_stop_playback(dev);
4731                         }
4732
4733                         if (ret != 0)
4734                                 break;
4735                 }
4736
4737                 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
4738                 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
4739                 b43_phy_write(dev, rfctl[1], tmp[5]);
4740                 b43_phy_write(dev, rfctl[0], tmp[4]);
4741                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
4742                 b43_phy_write(dev, afectl_core, tmp[2]);
4743                 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
4744
4745                 if (ret != 0)
4746                         break;
4747         }
4748
4749         b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
4750         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
4751         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
4752
4753         b43_nphy_stay_in_carrier_search(dev, 0);
4754
4755         return ret;
4756 }
4757
4758 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
4759                         struct nphy_txgains target, u8 type, bool debug)
4760 {
4761         return -1;
4762 }
4763
4764 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
4765 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
4766                         struct nphy_txgains target, u8 type, bool debug)
4767 {
4768         if (dev->phy.rev >= 3)
4769                 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
4770         else
4771                 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
4772 }
4773
4774 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
4775 static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
4776 {
4777         struct b43_phy *phy = &dev->phy;
4778         struct b43_phy_n *nphy = phy->n;
4779         /* u16 buf[16]; it's rev3+ */
4780
4781         nphy->phyrxchain = mask;
4782
4783         if (0 /* FIXME clk */)
4784                 return;
4785
4786         b43_mac_suspend(dev);
4787
4788         if (nphy->hang_avoid)
4789                 b43_nphy_stay_in_carrier_search(dev, true);
4790
4791         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
4792                         (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
4793
4794         if ((mask & 0x3) != 0x3) {
4795                 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
4796                 if (dev->phy.rev >= 3) {
4797                         /* TODO */
4798                 }
4799         } else {
4800                 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
4801                 if (dev->phy.rev >= 3) {
4802                         /* TODO */
4803                 }
4804         }
4805
4806         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
4807
4808         if (nphy->hang_avoid)
4809                 b43_nphy_stay_in_carrier_search(dev, false);
4810
4811         b43_mac_enable(dev);
4812 }
4813
4814 /**************************************************
4815  * N-PHY init
4816  **************************************************/
4817
4818 /*
4819  * Upload the N-PHY tables.
4820  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
4821  */
4822 static void b43_nphy_tables_init(struct b43_wldev *dev)
4823 {
4824         if (dev->phy.rev < 3)
4825                 b43_nphy_rev0_1_2_tables_init(dev);
4826         else
4827                 b43_nphy_rev3plus_tables_init(dev);
4828 }
4829
4830 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
4831 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
4832 {
4833         u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
4834
4835         mimocfg |= B43_NPHY_MIMOCFG_AUTO;
4836         if (preamble == 1)
4837                 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
4838         else
4839                 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
4840
4841         b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
4842 }
4843
4844 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
4845 static void b43_nphy_bphy_init(struct b43_wldev *dev)
4846 {
4847         unsigned int i;
4848         u16 val;
4849
4850         val = 0x1E1F;
4851         for (i = 0; i < 16; i++) {
4852                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
4853                 val -= 0x202;
4854         }
4855         val = 0x3E3F;
4856         for (i = 0; i < 16; i++) {
4857                 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
4858                 val -= 0x202;
4859         }
4860         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
4861 }
4862
4863 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
4864 static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
4865 {
4866         if (dev->phy.rev >= 3) {
4867                 if (!init)
4868                         return;
4869                 if (0 /* FIXME */) {
4870                         b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
4871                         b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
4872                         b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
4873                         b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
4874                 }
4875         } else {
4876                 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
4877                 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
4878
4879                 switch (dev->dev->bus_type) {
4880 #ifdef CONFIG_B43_BCMA
4881                 case B43_BUS_BCMA:
4882                         bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
4883                                                  0xFC00, 0xFC00);
4884                         break;
4885 #endif
4886 #ifdef CONFIG_B43_SSB
4887                 case B43_BUS_SSB:
4888                         ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
4889                                                 0xFC00, 0xFC00);
4890                         break;
4891 #endif
4892                 }
4893
4894                 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
4895                 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xFC00);
4896                 b43_maskset16(dev, B43_MMIO_GPIO_CONTROL, (~0xFC00 & 0xFFFF),
4897                               0);
4898
4899                 if (init) {
4900                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
4901                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
4902                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
4903                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
4904                 }
4905         }
4906 }
4907
4908 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N */
4909 static int b43_phy_initn(struct b43_wldev *dev)
4910 {
4911         struct ssb_sprom *sprom = dev->dev->bus_sprom;
4912         struct b43_phy *phy = &dev->phy;
4913         struct b43_phy_n *nphy = phy->n;
4914         u8 tx_pwr_state;
4915         struct nphy_txgains target;
4916         u16 tmp;
4917         enum ieee80211_band tmp2;
4918         bool do_rssi_cal;
4919
4920         u16 clip[2];
4921         bool do_cal = false;
4922
4923         if ((dev->phy.rev >= 3) &&
4924            (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
4925            (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
4926                 switch (dev->dev->bus_type) {
4927 #ifdef CONFIG_B43_BCMA
4928                 case B43_BUS_BCMA:
4929                         bcma_cc_set32(&dev->dev->bdev->bus->drv_cc,
4930                                       BCMA_CC_CHIPCTL, 0x40);
4931                         break;
4932 #endif
4933 #ifdef CONFIG_B43_SSB
4934                 case B43_BUS_SSB:
4935                         chipco_set32(&dev->dev->sdev->bus->chipco,
4936                                      SSB_CHIPCO_CHIPCTL, 0x40);
4937                         break;
4938 #endif
4939                 }
4940         }
4941         nphy->deaf_count = 0;
4942         b43_nphy_tables_init(dev);
4943         nphy->crsminpwr_adjusted = false;
4944         nphy->noisevars_adjusted = false;
4945
4946         /* Clear all overrides */
4947         if (dev->phy.rev >= 3) {
4948                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
4949                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
4950                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
4951                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
4952         } else {
4953                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
4954         }
4955         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
4956         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
4957         if (dev->phy.rev < 6) {
4958                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
4959                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
4960         }
4961         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
4962                      ~(B43_NPHY_RFSEQMODE_CAOVER |
4963                        B43_NPHY_RFSEQMODE_TROVER));
4964         if (dev->phy.rev >= 3)
4965                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
4966         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
4967
4968         if (dev->phy.rev <= 2) {
4969                 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
4970                 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
4971                                 ~B43_NPHY_BPHY_CTL3_SCALE,
4972                                 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
4973         }
4974         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
4975         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
4976
4977         if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
4978             (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
4979              dev->dev->board_type == 0x8B))
4980                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
4981         else
4982                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
4983         b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
4984         b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
4985         b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
4986
4987         b43_nphy_update_mimo_config(dev, nphy->preamble_override);
4988         b43_nphy_update_txrx_chain(dev);
4989
4990         if (phy->rev < 2) {
4991                 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
4992                 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
4993         }
4994
4995         tmp2 = b43_current_band(dev->wl);
4996         if (b43_nphy_ipa(dev)) {
4997                 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
4998                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
4999                                 nphy->papd_epsilon_offset[0] << 7);
5000                 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
5001                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
5002                                 nphy->papd_epsilon_offset[1] << 7);
5003                 b43_nphy_int_pa_set_tx_dig_filters(dev);
5004         } else if (phy->rev >= 5) {
5005                 b43_nphy_ext_pa_set_tx_dig_filters(dev);
5006         }
5007
5008         b43_nphy_workarounds(dev);
5009
5010         /* Reset CCA, in init code it differs a little from standard way */
5011         b43_phy_force_clock(dev, 1);
5012         tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
5013         b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
5014         b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
5015         b43_phy_force_clock(dev, 0);
5016
5017         b43_mac_phy_clock_set(dev, true);
5018
5019         b43_nphy_pa_override(dev, false);
5020         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
5021         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
5022         b43_nphy_pa_override(dev, true);
5023
5024         b43_nphy_classifier(dev, 0, 0);
5025         b43_nphy_read_clip_detection(dev, clip);
5026         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5027                 b43_nphy_bphy_init(dev);
5028
5029         tx_pwr_state = nphy->txpwrctrl;
5030         b43_nphy_tx_power_ctrl(dev, false);
5031         b43_nphy_tx_power_fix(dev);
5032         b43_nphy_tx_power_ctl_idle_tssi(dev);
5033         b43_nphy_tx_power_ctl_setup(dev);
5034         b43_nphy_tx_gain_table_upload(dev);
5035
5036         if (nphy->phyrxchain != 3)
5037                 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
5038         if (nphy->mphase_cal_phase_id > 0)
5039                 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
5040
5041         do_rssi_cal = false;
5042         if (phy->rev >= 3) {
5043                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5044                         do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
5045                 else
5046                         do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
5047
5048                 if (do_rssi_cal)
5049                         b43_nphy_rssi_cal(dev);
5050                 else
5051                         b43_nphy_restore_rssi_cal(dev);
5052         } else {
5053                 b43_nphy_rssi_cal(dev);
5054         }
5055
5056         if (!((nphy->measure_hold & 0x6) != 0)) {
5057                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5058                         do_cal = !nphy->iqcal_chanspec_2G.center_freq;
5059                 else
5060                         do_cal = !nphy->iqcal_chanspec_5G.center_freq;
5061
5062                 if (nphy->mute)
5063                         do_cal = false;
5064
5065                 if (do_cal) {
5066                         target = b43_nphy_get_tx_gains(dev);
5067
5068                         if (nphy->antsel_type == 2)
5069                                 b43_nphy_superswitch_init(dev, true);
5070                         if (nphy->perical != 2) {
5071                                 b43_nphy_rssi_cal(dev);
5072                                 if (phy->rev >= 3) {
5073                                         nphy->cal_orig_pwr_idx[0] =
5074                                             nphy->txpwrindex[0].index_internal;
5075                                         nphy->cal_orig_pwr_idx[1] =
5076                                             nphy->txpwrindex[1].index_internal;
5077                                         /* TODO N PHY Pre Calibrate TX Gain */
5078                                         target = b43_nphy_get_tx_gains(dev);
5079                                 }
5080                                 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
5081                                         if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
5082                                                 b43_nphy_save_cal(dev);
5083                         } else if (nphy->mphase_cal_phase_id == 0)
5084                                 ;/* N PHY Periodic Calibration with arg 3 */
5085                 } else {
5086                         b43_nphy_restore_cal(dev);
5087                 }
5088         }
5089
5090         b43_nphy_tx_pwr_ctrl_coef_setup(dev);
5091         b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
5092         b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
5093         b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
5094         if (phy->rev >= 3 && phy->rev <= 6)
5095                 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
5096         b43_nphy_tx_lp_fbw(dev);
5097         if (phy->rev >= 3)
5098                 b43_nphy_spur_workaround(dev);
5099
5100         return 0;
5101 }
5102
5103 /**************************************************
5104  * Channel switching ops.
5105  **************************************************/
5106
5107 static void b43_chantab_phy_upload(struct b43_wldev *dev,
5108                                    const struct b43_phy_n_sfo_cfg *e)
5109 {
5110         b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
5111         b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
5112         b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
5113         b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
5114         b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
5115         b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
5116 }
5117
5118 /* http://bcm-v4.sipsolutions.net/802.11/PmuSpurAvoid */
5119 static void b43_nphy_pmu_spur_avoid(struct b43_wldev *dev, bool avoid)
5120 {
5121         switch (dev->dev->bus_type) {
5122 #ifdef CONFIG_B43_BCMA
5123         case B43_BUS_BCMA:
5124                 bcma_pmu_spuravoid_pllupdate(&dev->dev->bdev->bus->drv_cc,
5125                                              avoid);
5126                 break;
5127 #endif
5128 #ifdef CONFIG_B43_SSB
5129         case B43_BUS_SSB:
5130                 /* FIXME */
5131                 break;
5132 #endif
5133         }
5134 }
5135
5136 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
5137 static void b43_nphy_channel_setup(struct b43_wldev *dev,
5138                                 const struct b43_phy_n_sfo_cfg *e,
5139                                 struct ieee80211_channel *new_channel)
5140 {
5141         struct b43_phy *phy = &dev->phy;
5142         struct b43_phy_n *nphy = dev->phy.n;
5143         int ch = new_channel->hw_value;
5144
5145         u16 old_band_5ghz;
5146         u32 tmp32;
5147
5148         old_band_5ghz =
5149                 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
5150         if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
5151                 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
5152                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
5153                 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
5154                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
5155                 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
5156         } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
5157                 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
5158                 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
5159                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
5160                 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
5161                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
5162         }
5163
5164         b43_chantab_phy_upload(dev, e);
5165
5166         if (new_channel->hw_value == 14) {
5167                 b43_nphy_classifier(dev, 2, 0);
5168                 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
5169         } else {
5170                 b43_nphy_classifier(dev, 2, 2);
5171                 if (new_channel->band == IEEE80211_BAND_2GHZ)
5172                         b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
5173         }
5174
5175         if (!nphy->txpwrctrl)
5176                 b43_nphy_tx_power_fix(dev);
5177
5178         if (dev->phy.rev < 3)
5179                 b43_nphy_adjust_lna_gain_table(dev);
5180
5181         b43_nphy_tx_lp_fbw(dev);
5182
5183         if (dev->phy.rev >= 3 &&
5184             dev->phy.n->spur_avoid != B43_SPUR_AVOID_DISABLE) {
5185                 bool avoid = false;
5186                 if (dev->phy.n->spur_avoid == B43_SPUR_AVOID_FORCE) {
5187                         avoid = true;
5188                 } else if (!b43_channel_type_is_40mhz(phy->channel_type)) {
5189                         if ((ch >= 5 && ch <= 8) || ch == 13 || ch == 14)
5190                                 avoid = true;
5191                 } else { /* 40MHz */
5192                         if (nphy->aband_spurwar_en &&
5193                             (ch == 38 || ch == 102 || ch == 118))
5194                                 avoid = dev->dev->chip_id == 0x4716;
5195                 }
5196
5197                 b43_nphy_pmu_spur_avoid(dev, avoid);
5198
5199                 if (dev->dev->chip_id == 43222 || dev->dev->chip_id == 43224 ||
5200                     dev->dev->chip_id == 43225) {
5201                         b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW,
5202                                     avoid ? 0x5341 : 0x8889);
5203                         b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
5204                 }
5205
5206                 if (dev->phy.rev == 3 || dev->phy.rev == 4)
5207                         ; /* TODO: reset PLL */
5208
5209                 if (avoid)
5210                         b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTRX);
5211                 else
5212                         b43_phy_mask(dev, B43_NPHY_BBCFG,
5213                                      ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
5214
5215                 b43_nphy_reset_cca(dev);
5216
5217                 /* wl sets useless phy_isspuravoid here */
5218         }
5219
5220         b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
5221
5222         if (phy->rev >= 3)
5223                 b43_nphy_spur_workaround(dev);
5224 }
5225
5226 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
5227 static int b43_nphy_set_channel(struct b43_wldev *dev,
5228                                 struct ieee80211_channel *channel,
5229                                 enum nl80211_channel_type channel_type)
5230 {
5231         struct b43_phy *phy = &dev->phy;
5232
5233         const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
5234         const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
5235
5236         u8 tmp;
5237
5238         if (dev->phy.rev >= 3) {
5239                 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
5240                                                         channel->center_freq);
5241                 if (!tabent_r3)
5242                         return -ESRCH;
5243         } else {
5244                 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
5245                                                         channel->hw_value);
5246                 if (!tabent_r2)
5247                         return -ESRCH;
5248         }
5249
5250         /* Channel is set later in common code, but we need to set it on our
5251            own to let this function's subcalls work properly. */
5252         phy->channel = channel->hw_value;
5253         phy->channel_freq = channel->center_freq;
5254
5255         if (b43_channel_type_is_40mhz(phy->channel_type) !=
5256                 b43_channel_type_is_40mhz(channel_type))
5257                 ; /* TODO: BMAC BW Set (channel_type) */
5258
5259         if (channel_type == NL80211_CHAN_HT40PLUS)
5260                 b43_phy_set(dev, B43_NPHY_RXCTL,
5261                                 B43_NPHY_RXCTL_BSELU20);
5262         else if (channel_type == NL80211_CHAN_HT40MINUS)
5263                 b43_phy_mask(dev, B43_NPHY_RXCTL,
5264                                 ~B43_NPHY_RXCTL_BSELU20);
5265
5266         if (dev->phy.rev >= 3) {
5267                 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
5268                 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
5269                 b43_radio_2056_setup(dev, tabent_r3);
5270                 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
5271         } else {
5272                 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
5273                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
5274                 b43_radio_2055_setup(dev, tabent_r2);
5275                 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
5276         }
5277
5278         return 0;
5279 }
5280
5281 /**************************************************
5282  * Basic PHY ops.
5283  **************************************************/
5284
5285 static int b43_nphy_op_allocate(struct b43_wldev *dev)
5286 {
5287         struct b43_phy_n *nphy;
5288
5289         nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
5290         if (!nphy)
5291                 return -ENOMEM;
5292         dev->phy.n = nphy;
5293
5294         return 0;
5295 }
5296
5297 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
5298 {
5299         struct b43_phy *phy = &dev->phy;
5300         struct b43_phy_n *nphy = phy->n;
5301         struct ssb_sprom *sprom = dev->dev->bus_sprom;
5302
5303         memset(nphy, 0, sizeof(*nphy));
5304
5305         nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
5306         nphy->spur_avoid = (phy->rev >= 3) ?
5307                                 B43_SPUR_AVOID_AUTO : B43_SPUR_AVOID_DISABLE;
5308         nphy->init_por = true;
5309         nphy->gain_boost = true; /* this way we follow wl, assume it is true */
5310         nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
5311         nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
5312         nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
5313         /* 128 can mean disabled-by-default state of TX pwr ctl. Max value is
5314          * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */
5315         nphy->tx_pwr_idx[0] = 128;
5316         nphy->tx_pwr_idx[1] = 128;
5317
5318         /* Hardware TX power control and 5GHz power gain */
5319         nphy->txpwrctrl = false;
5320         nphy->pwg_gain_5ghz = false;
5321         if (dev->phy.rev >= 3 ||
5322             (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
5323              (dev->dev->core_rev == 11 || dev->dev->core_rev == 12))) {
5324                 nphy->txpwrctrl = true;
5325                 nphy->pwg_gain_5ghz = true;
5326         } else if (sprom->revision >= 4) {
5327                 if (dev->phy.rev >= 2 &&
5328                     (sprom->boardflags2_lo & B43_BFL2_TXPWRCTRL_EN)) {
5329                         nphy->txpwrctrl = true;
5330 #ifdef CONFIG_B43_SSB
5331                         if (dev->dev->bus_type == B43_BUS_SSB &&
5332                             dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) {
5333                                 struct pci_dev *pdev =
5334                                         dev->dev->sdev->bus->host_pci;
5335                                 if (pdev->device == 0x4328 ||
5336                                     pdev->device == 0x432a)
5337                                         nphy->pwg_gain_5ghz = true;
5338                         }
5339 #endif
5340                 } else if (sprom->boardflags2_lo & B43_BFL2_5G_PWRGAIN) {
5341                         nphy->pwg_gain_5ghz = true;
5342                 }
5343         }
5344
5345         if (dev->phy.rev >= 3) {
5346                 nphy->ipa2g_on = sprom->fem.ghz2.extpa_gain == 2;
5347                 nphy->ipa5g_on = sprom->fem.ghz5.extpa_gain == 2;
5348         }
5349
5350         nphy->init_por = true;
5351 }
5352
5353 static void b43_nphy_op_free(struct b43_wldev *dev)
5354 {
5355         struct b43_phy *phy = &dev->phy;
5356         struct b43_phy_n *nphy = phy->n;
5357
5358         kfree(nphy);
5359         phy->n = NULL;
5360 }
5361
5362 static int b43_nphy_op_init(struct b43_wldev *dev)
5363 {
5364         return b43_phy_initn(dev);
5365 }
5366
5367 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
5368 {
5369 #if B43_DEBUG
5370         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
5371                 /* OFDM registers are onnly available on A/G-PHYs */
5372                 b43err(dev->wl, "Invalid OFDM PHY access at "
5373                        "0x%04X on N-PHY\n", offset);
5374                 dump_stack();
5375         }
5376         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
5377                 /* Ext-G registers are only available on G-PHYs */
5378                 b43err(dev->wl, "Invalid EXT-G PHY access at "
5379                        "0x%04X on N-PHY\n", offset);
5380                 dump_stack();
5381         }
5382 #endif /* B43_DEBUG */
5383 }
5384
5385 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
5386 {
5387         check_phyreg(dev, reg);
5388         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5389         return b43_read16(dev, B43_MMIO_PHY_DATA);
5390 }
5391
5392 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
5393 {
5394         check_phyreg(dev, reg);
5395         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5396         b43_write16(dev, B43_MMIO_PHY_DATA, value);
5397 }
5398
5399 static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
5400                                  u16 set)
5401 {
5402         check_phyreg(dev, reg);
5403         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5404         b43_maskset16(dev, B43_MMIO_PHY_DATA, mask, set);
5405 }
5406
5407 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
5408 {
5409         /* Register 1 is a 32-bit register. */
5410         B43_WARN_ON(reg == 1);
5411         /* N-PHY needs 0x100 for read access */
5412         reg |= 0x100;
5413
5414         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
5415         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
5416 }
5417
5418 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
5419 {
5420         /* Register 1 is a 32-bit register. */
5421         B43_WARN_ON(reg == 1);
5422
5423         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
5424         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
5425 }
5426
5427 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
5428 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
5429                                         bool blocked)
5430 {
5431         if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
5432                 b43err(dev->wl, "MAC not suspended\n");
5433
5434         if (blocked) {
5435                 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
5436                                 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
5437                 if (dev->phy.rev >= 7) {
5438                         /* TODO */
5439                 } else if (dev->phy.rev >= 3) {
5440                         b43_radio_mask(dev, 0x09, ~0x2);
5441
5442                         b43_radio_write(dev, 0x204D, 0);
5443                         b43_radio_write(dev, 0x2053, 0);
5444                         b43_radio_write(dev, 0x2058, 0);
5445                         b43_radio_write(dev, 0x205E, 0);
5446                         b43_radio_mask(dev, 0x2062, ~0xF0);
5447                         b43_radio_write(dev, 0x2064, 0);
5448
5449                         b43_radio_write(dev, 0x304D, 0);
5450                         b43_radio_write(dev, 0x3053, 0);
5451                         b43_radio_write(dev, 0x3058, 0);
5452                         b43_radio_write(dev, 0x305E, 0);
5453                         b43_radio_mask(dev, 0x3062, ~0xF0);
5454                         b43_radio_write(dev, 0x3064, 0);
5455                 }
5456         } else {
5457                 if (dev->phy.rev >= 7) {
5458                         b43_radio_2057_init(dev);
5459                         b43_switch_channel(dev, dev->phy.channel);
5460                 } else if (dev->phy.rev >= 3) {
5461                         b43_radio_init2056(dev);
5462                         b43_switch_channel(dev, dev->phy.channel);
5463                 } else {
5464                         b43_radio_init2055(dev);
5465                 }
5466         }
5467 }
5468
5469 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
5470 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
5471 {
5472         u16 override = on ? 0x0 : 0x7FFF;
5473         u16 core = on ? 0xD : 0x00FD;
5474
5475         if (dev->phy.rev >= 3) {
5476                 if (on) {
5477                         b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
5478                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
5479                         b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
5480                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5481                 } else {
5482                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
5483                         b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
5484                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5485                         b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
5486                 }
5487         } else {
5488                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5489         }
5490 }
5491
5492 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
5493                                       unsigned int new_channel)
5494 {
5495         struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan;
5496         enum nl80211_channel_type channel_type =
5497                 cfg80211_get_chandef_type(&dev->wl->hw->conf.chandef);
5498
5499         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
5500                 if ((new_channel < 1) || (new_channel > 14))
5501                         return -EINVAL;
5502         } else {
5503                 if (new_channel > 200)
5504                         return -EINVAL;
5505         }
5506
5507         return b43_nphy_set_channel(dev, channel, channel_type);
5508 }
5509
5510 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
5511 {
5512         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5513                 return 1;
5514         return 36;
5515 }
5516
5517 const struct b43_phy_operations b43_phyops_n = {
5518         .allocate               = b43_nphy_op_allocate,
5519         .free                   = b43_nphy_op_free,
5520         .prepare_structs        = b43_nphy_op_prepare_structs,
5521         .init                   = b43_nphy_op_init,
5522         .phy_read               = b43_nphy_op_read,
5523         .phy_write              = b43_nphy_op_write,
5524         .phy_maskset            = b43_nphy_op_maskset,
5525         .radio_read             = b43_nphy_op_radio_read,
5526         .radio_write            = b43_nphy_op_radio_write,
5527         .software_rfkill        = b43_nphy_op_software_rfkill,
5528         .switch_analog          = b43_nphy_op_switch_analog,
5529         .switch_channel         = b43_nphy_op_switch_channel,
5530         .get_default_chan       = b43_nphy_op_get_default_chan,
5531         .recalc_txpower         = b43_nphy_op_recalc_txpower,
5532         .adjust_txpower         = b43_nphy_op_adjust_txpower,
5533 };