Pileus Git - ~andy/linux/blob - drivers/net/wireless/b43/phy_ht.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n HT-PHY support
   5
   6   Copyright (c) 2011 Rafał Miłecki <zajec5@gmail.com>
   7
   8   This program is free software; you can redistribute it and/or modify
   9   it under the terms of the GNU General Public License as published by
  10   the Free Software Foundation; either version 2 of the License, or
  11   (at your option) any later version.
  12
  13   This program is distributed in the hope that it will be useful,
  14   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16   GNU General Public License for more details.
  17
  18   You should have received a copy of the GNU General Public License
  19   along with this program; see the file COPYING.  If not, write to
  20   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  21   Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #include <linux/slab.h>
  26
  27 #include "b43.h"
  28 #include "phy_ht.h"
  29 #include "tables_phy_ht.h"
  30 #include "radio_2059.h"
  31 #include "main.h"
  32
  33 /**************************************************
  34  * Radio 2059.
  35  **************************************************/
  36
  37 static void b43_radio_2059_channel_setup(struct b43_wldev *dev,
  38                         const struct b43_phy_ht_channeltab_e_radio2059 *e)
  39 {
  40         static const u16 routing[] = { R2059_C1, R2059_C2, R2059_C3, };
  41         u16 r;
  42         int core;
  43
  44         b43_radio_write(dev, 0x16, e->radio_syn16);
  45         b43_radio_write(dev, 0x17, e->radio_syn17);
  46         b43_radio_write(dev, 0x22, e->radio_syn22);
  47         b43_radio_write(dev, 0x25, e->radio_syn25);
  48         b43_radio_write(dev, 0x27, e->radio_syn27);
  49         b43_radio_write(dev, 0x28, e->radio_syn28);
  50         b43_radio_write(dev, 0x29, e->radio_syn29);
  51         b43_radio_write(dev, 0x2c, e->radio_syn2c);
  52         b43_radio_write(dev, 0x2d, e->radio_syn2d);
  53         b43_radio_write(dev, 0x37, e->radio_syn37);
  54         b43_radio_write(dev, 0x41, e->radio_syn41);
  55         b43_radio_write(dev, 0x43, e->radio_syn43);
  56         b43_radio_write(dev, 0x47, e->radio_syn47);
  57
  58         for (core = 0; core < 3; core++) {
  59                 r = routing[core];
  60                 b43_radio_write(dev, r | 0x4a, e->radio_rxtx4a);
  61                 b43_radio_write(dev, r | 0x58, e->radio_rxtx58);
  62                 b43_radio_write(dev, r | 0x5a, e->radio_rxtx5a);
  63                 b43_radio_write(dev, r | 0x6a, e->radio_rxtx6a);
  64                 b43_radio_write(dev, r | 0x6d, e->radio_rxtx6d);
  65                 b43_radio_write(dev, r | 0x6e, e->radio_rxtx6e);
  66                 b43_radio_write(dev, r | 0x92, e->radio_rxtx92);
  67                 b43_radio_write(dev, r | 0x98, e->radio_rxtx98);
  68         }
  69
  70         udelay(50);
  71
  72         /* Calibration */
  73         b43_radio_mask(dev, 0x2b, ~0x1);
  74         b43_radio_mask(dev, 0x2e, ~0x4);
  75         b43_radio_set(dev, 0x2e, 0x4);
  76         b43_radio_set(dev, 0x2b, 0x1);
  77
  78         udelay(300);
  79 }
  80
  81 static void b43_radio_2059_init(struct b43_wldev *dev)
  82 {
  83         const u16 routing[] = { R2059_C1, R2059_C2, R2059_C3 };
  84         const u16 radio_values[3][2] = {
  85                 { 0x61, 0xE9 }, { 0x69, 0xD5 }, { 0x73, 0x99 },
  86         };
  87         u16 i, j;
  88
  89         b43_radio_write(dev, R2059_ALL | 0x51, 0x0070);
  90         b43_radio_write(dev, R2059_ALL | 0x5a, 0x0003);
  91
  92         for (i = 0; i < ARRAY_SIZE(routing); i++)
  93                 b43_radio_set(dev, routing[i] | 0x146, 0x3);
  94
  95         b43_radio_set(dev, 0x2e, 0x0078);
  96         b43_radio_set(dev, 0xc0, 0x0080);
  97         msleep(2);
  98         b43_radio_mask(dev, 0x2e, ~0x0078);
  99         b43_radio_mask(dev, 0xc0, ~0x0080);
 100
 101         if (1) { /* FIXME */
 102                 b43_radio_set(dev, R2059_C3 | 0x4, 0x1);
 103                 udelay(10);
 104                 b43_radio_set(dev, R2059_C3 | 0x0BF, 0x1);
 105                 b43_radio_maskset(dev, R2059_C3 | 0x19B, 0x3, 0x2);
 106
 107                 b43_radio_set(dev, R2059_C3 | 0x4, 0x2);
 108                 udelay(100);
 109                 b43_radio_mask(dev, R2059_C3 | 0x4, ~0x2);
 110
 111                 for (i = 0; i < 10000; i++) {
 112                         if (b43_radio_read(dev, R2059_C3 | 0x145) & 1) {
 113                                 i = 0;
 114                                 break;
 115                         }
 116                         udelay(100);
 117                 }
 118                 if (i)
 119                         b43err(dev->wl, "radio 0x945 timeout\n");
 120
 121                 b43_radio_mask(dev, R2059_C3 | 0x4, ~0x1);
 122                 b43_radio_set(dev, 0xa, 0x60);
 123
 124                 for (i = 0; i < 3; i++) {
 125                         b43_radio_write(dev, 0x17F, radio_values[i][0]);
 126                         b43_radio_write(dev, 0x13D, 0x6E);
 127                         b43_radio_write(dev, 0x13E, radio_values[i][1]);
 128                         b43_radio_write(dev, 0x13C, 0x55);
 129
 130                         for (j = 0; j < 10000; j++) {
 131                                 if (b43_radio_read(dev, 0x140) & 2) {
 132                                         j = 0;
 133                                         break;
 134                                 }
 135                                 udelay(500);
 136                         }
 137                         if (j)
 138                                 b43err(dev->wl, "radio 0x140 timeout\n");
 139
 140                         b43_radio_write(dev, 0x13C, 0x15);
 141                 }
 142
 143                 b43_radio_mask(dev, 0x17F, ~0x1);
 144         }
 145
 146         b43_radio_mask(dev, 0x11, ~0x0008);
 147 }
 148
 149 /**************************************************
 150  * RF
 151  **************************************************/
 152
 153 static void b43_phy_ht_force_rf_sequence(struct b43_wldev *dev, u16 rf_seq)
 154 {
 155         u8 i;
 156
 157         u16 save_seq_mode = b43_phy_read(dev, B43_PHY_HT_RF_SEQ_MODE);
 158         b43_phy_set(dev, B43_PHY_HT_RF_SEQ_MODE, 0x3);
 159
 160         b43_phy_set(dev, B43_PHY_HT_RF_SEQ_TRIG, rf_seq);
 161         for (i = 0; i < 200; i++) {
 162                 if (!(b43_phy_read(dev, B43_PHY_HT_RF_SEQ_STATUS) & rf_seq)) {
 163                         i = 0;
 164                         break;
 165                 }
 166                 msleep(1);
 167         }
 168         if (i)
 169                 b43err(dev->wl, "Forcing RF sequence timeout\n");
 170
 171         b43_phy_write(dev, B43_PHY_HT_RF_SEQ_MODE, save_seq_mode);
 172 }
 173
 174 static void b43_phy_ht_pa_override(struct b43_wldev *dev, bool enable)
 175 {
 176         struct b43_phy_ht *htphy = dev->phy.ht;
 177         static const u16 regs[3] = { B43_PHY_HT_RF_CTL_INT_C1,
 178                                      B43_PHY_HT_RF_CTL_INT_C2,
 179                                      B43_PHY_HT_RF_CTL_INT_C3 };
 180         int i;
 181
 182         if (enable) {
 183                 for (i = 0; i < 3; i++)
 184                         b43_phy_write(dev, regs[i], htphy->rf_ctl_int_save[i]);
 185         } else {
 186                 for (i = 0; i < 3; i++)
 187                         htphy->rf_ctl_int_save[i] = b43_phy_read(dev, regs[i]);
 188                 /* TODO: Does 5GHz band use different value (not 0x0400)? */
 189                 for (i = 0; i < 3; i++)
 190                         b43_phy_write(dev, regs[i], 0x0400);
 191         }
 192 }
 193
 194 /**************************************************
 195  * Various PHY ops
 196  **************************************************/
 197
 198 static u16 b43_phy_ht_classifier(struct b43_wldev *dev, u16 mask, u16 val)
 199 {
 200         u16 tmp;
 201         u16 allowed = B43_PHY_HT_CLASS_CTL_CCK_EN |
 202                       B43_PHY_HT_CLASS_CTL_OFDM_EN |
 203                       B43_PHY_HT_CLASS_CTL_WAITED_EN;
 204
 205         tmp = b43_phy_read(dev, B43_PHY_HT_CLASS_CTL);
 206         tmp &= allowed;
 207         tmp &= ~mask;
 208         tmp |= (val & mask);
 209         b43_phy_maskset(dev, B43_PHY_HT_CLASS_CTL, ~allowed, tmp);
 210
 211         return tmp;
 212 }
 213
 214 static void b43_phy_ht_reset_cca(struct b43_wldev *dev)
 215 {
 216         u16 bbcfg;
 217
 218         b43_phy_force_clock(dev, true);
 219         bbcfg = b43_phy_read(dev, B43_PHY_HT_BBCFG);
 220         b43_phy_write(dev, B43_PHY_HT_BBCFG, bbcfg | B43_PHY_HT_BBCFG_RSTCCA);
 221         udelay(1);
 222         b43_phy_write(dev, B43_PHY_HT_BBCFG, bbcfg & ~B43_PHY_HT_BBCFG_RSTCCA);
 223         b43_phy_force_clock(dev, false);
 224
 225         b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RST2RX);
 226 }
 227
 228 static void b43_phy_ht_zero_extg(struct b43_wldev *dev)
 229 {
 230         u8 i, j;
 231         u16 base[] = { 0x40, 0x60, 0x80 };
 232
 233         for (i = 0; i < ARRAY_SIZE(base); i++) {
 234                 for (j = 0; j < 4; j++)
 235                         b43_phy_write(dev, B43_PHY_EXTG(base[i] + j), 0);
 236         }
 237
 238         for (i = 0; i < ARRAY_SIZE(base); i++)
 239                 b43_phy_write(dev, B43_PHY_EXTG(base[i] + 0xc), 0);
 240 }
 241
 242 /* Some unknown AFE (Analog Frondned) op */
 243 static void b43_phy_ht_afe_unk1(struct b43_wldev *dev)
 244 {
 245         u8 i;
 246
 247         static const u16 ctl_regs[3][2] = {
 248                 { B43_PHY_HT_AFE_C1_OVER, B43_PHY_HT_AFE_C1 },
 249                 { B43_PHY_HT_AFE_C2_OVER, B43_PHY_HT_AFE_C2 },
 250                 { B43_PHY_HT_AFE_C3_OVER, B43_PHY_HT_AFE_C3},
 251         };
 252
 253         for (i = 0; i < 3; i++) {
 254                 /* TODO: verify masks&sets */
 255                 b43_phy_set(dev, ctl_regs[i][1], 0x4);
 256                 b43_phy_set(dev, ctl_regs[i][0], 0x4);
 257                 b43_phy_mask(dev, ctl_regs[i][1], ~0x1);
 258                 b43_phy_set(dev, ctl_regs[i][0], 0x1);
 259                 b43_httab_write(dev, B43_HTTAB16(8, 5 + (i * 0x10)), 0);
 260                 b43_phy_mask(dev, ctl_regs[i][0], ~0x4);
 261         }
 262 }
 263
 264 static void b43_phy_ht_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 265 {
 266         clip_st[0] = b43_phy_read(dev, B43_PHY_HT_C1_CLIP1THRES);
 267         clip_st[1] = b43_phy_read(dev, B43_PHY_HT_C2_CLIP1THRES);
 268         clip_st[2] = b43_phy_read(dev, B43_PHY_HT_C3_CLIP1THRES);
 269 }
 270
 271 static void b43_phy_ht_bphy_init(struct b43_wldev *dev)
 272 {
 273         unsigned int i;
 274         u16 val;
 275
 276         val = 0x1E1F;
 277         for (i = 0; i < 16; i++) {
 278                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
 279                 val -= 0x202;
 280         }
 281         val = 0x3E3F;
 282         for (i = 0; i < 16; i++) {
 283                 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
 284                 val -= 0x202;
 285         }
 286         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
 287 }
 288
 289 /**************************************************
 290  * Samples
 291  **************************************************/
 292
 293 static void b43_phy_ht_stop_playback(struct b43_wldev *dev)
 294 {
 295         struct b43_phy_ht *phy_ht = dev->phy.ht;
 296         u16 tmp;
 297         int i;
 298
 299         tmp = b43_phy_read(dev, B43_PHY_HT_SAMP_STAT);
 300         if (tmp & 0x1)
 301                 b43_phy_set(dev, B43_PHY_HT_SAMP_CMD, B43_PHY_HT_SAMP_CMD_STOP);
 302         else if (tmp & 0x2)
 303                 b43_phy_mask(dev, B43_PHY_HT_IQLOCAL_CMDGCTL, 0x7FFF);
 304
 305         b43_phy_mask(dev, B43_PHY_HT_SAMP_CMD, ~0x0004);
 306
 307         for (i = 0; i < 3; i++) {
 308                 if (phy_ht->bb_mult_save[i] >= 0) {
 309                         b43_httab_write(dev, B43_HTTAB16(13, 0x63 + i * 4),
 310                                         phy_ht->bb_mult_save[i]);
 311                         b43_httab_write(dev, B43_HTTAB16(13, 0x67 + i * 4),
 312                                         phy_ht->bb_mult_save[i]);
 313                 }
 314         }
 315 }
 316
 317 static u16 b43_phy_ht_load_samples(struct b43_wldev *dev)
 318 {
 319         int i;
 320         u16 len = 20 << 3;
 321
 322         b43_phy_write(dev, B43_PHY_HT_TABLE_ADDR, 0x4400);
 323
 324         for (i = 0; i < len; i++) {
 325                 b43_phy_write(dev, B43_PHY_HT_TABLE_DATAHI, 0);
 326                 b43_phy_write(dev, B43_PHY_HT_TABLE_DATALO, 0);
 327         }
 328
 329         return len;
 330 }
 331
 332 static void b43_phy_ht_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
 333                                    u16 wait)
 334 {
 335         struct b43_phy_ht *phy_ht = dev->phy.ht;
 336         u16 save_seq_mode;
 337         int i;
 338
 339         for (i = 0; i < 3; i++) {
 340                 if (phy_ht->bb_mult_save[i] < 0)
 341                         phy_ht->bb_mult_save[i] = b43_httab_read(dev, B43_HTTAB16(13, 0x63 + i * 4));
 342         }
 343
 344         b43_phy_write(dev, B43_PHY_HT_SAMP_DEP_CNT, samps - 1);
 345         if (loops != 0xFFFF)
 346                 loops--;
 347         b43_phy_write(dev, B43_PHY_HT_SAMP_LOOP_CNT, loops);
 348         b43_phy_write(dev, B43_PHY_HT_SAMP_WAIT_CNT, wait);
 349
 350         save_seq_mode = b43_phy_read(dev, B43_PHY_HT_RF_SEQ_MODE);
 351         b43_phy_set(dev, B43_PHY_HT_RF_SEQ_MODE,
 352                     B43_PHY_HT_RF_SEQ_MODE_CA_OVER);
 353
 354         /* TODO: find out mask bits! Do we need more function arguments? */
 355         b43_phy_mask(dev, B43_PHY_HT_SAMP_CMD, ~0);
 356         b43_phy_mask(dev, B43_PHY_HT_SAMP_CMD, ~0);
 357         b43_phy_mask(dev, B43_PHY_HT_IQLOCAL_CMDGCTL, ~0);
 358         b43_phy_set(dev, B43_PHY_HT_SAMP_CMD, 0x1);
 359
 360         for (i = 0; i < 100; i++) {
 361                 if (!(b43_phy_read(dev, B43_PHY_HT_RF_SEQ_STATUS) & 1)) {
 362                         i = 0;
 363                         break;
 364                 }
 365                 udelay(10);
 366         }
 367         if (i)
 368                 b43err(dev->wl, "run samples timeout\n");
 369
 370         b43_phy_write(dev, B43_PHY_HT_RF_SEQ_MODE, save_seq_mode);
 371 }
 372
 373 static void b43_phy_ht_tx_tone(struct b43_wldev *dev)
 374 {
 375         u16 samp;
 376
 377         samp = b43_phy_ht_load_samples(dev);
 378         b43_phy_ht_run_samples(dev, samp, 0xFFFF, 0);
 379 }
 380
 381 /**************************************************
 382  * RSSI
 383  **************************************************/
 384
 385 static void b43_phy_ht_rssi_select(struct b43_wldev *dev, u8 core_sel,
 386                                    u8 rssi_type)
 387 {
 388         static const u16 ctl_regs[3][2] = {
 389                 { B43_PHY_HT_AFE_C1, B43_PHY_HT_AFE_C1_OVER, },
 390                 { B43_PHY_HT_AFE_C2, B43_PHY_HT_AFE_C2_OVER, },
 391                 { B43_PHY_HT_AFE_C3, B43_PHY_HT_AFE_C3_OVER, },
 392         };
 393         static const u16 radio_r[] = { R2059_C1, R2059_C2, R2059_C3, };
 394         int core;
 395
 396         if (core_sel == 0) {
 397                 b43err(dev->wl, "RSSI selection for core off not implemented yet\n");
 398         } else {
 399                 for (core = 0; core < 3; core++) {
 400                         /* Check if caller requested a one specific core */
 401                         if ((core_sel == 1 && core != 0) ||
 402                             (core_sel == 2 && core != 1) ||
 403                             (core_sel == 3 && core != 2))
 404                                 continue;
 405
 406                         switch (rssi_type) {
 407                         case 4:
 408                                 b43_phy_set(dev, ctl_regs[core][0], 0x3 << 8);
 409                                 b43_phy_set(dev, ctl_regs[core][0], 0x3 << 10);
 410                                 b43_phy_set(dev, ctl_regs[core][1], 0x1 << 9);
 411                                 b43_phy_set(dev, ctl_regs[core][1], 0x1 << 10);
 412
 413                                 b43_radio_set(dev, R2059_C3 | 0xbf, 0x1);
 414                                 b43_radio_write(dev, radio_r[core] | 0x159,
 415                                                 0x11);
 416                                 break;
 417                         default:
 418                                 b43err(dev->wl, "RSSI selection for type %d not implemented yet\n",
 419                                        rssi_type);
 420                         }
 421                 }
 422         }
 423 }
 424
 425 static void b43_phy_ht_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
 426                                  u8 nsamp)
 427 {
 428         u16 phy_regs_values[12];
 429         static const u16 phy_regs_to_save[] = {
 430                 B43_PHY_HT_AFE_C1, B43_PHY_HT_AFE_C1_OVER,
 431                 0x848, 0x841,
 432                 B43_PHY_HT_AFE_C2, B43_PHY_HT_AFE_C2_OVER,
 433                 0x868, 0x861,
 434                 B43_PHY_HT_AFE_C3, B43_PHY_HT_AFE_C3_OVER,
 435                 0x888, 0x881,
 436         };
 437         u16 tmp[3];
 438         int i;
 439
 440         for (i = 0; i < 12; i++)
 441                 phy_regs_values[i] = b43_phy_read(dev, phy_regs_to_save[i]);
 442
 443         b43_phy_ht_rssi_select(dev, 5, type);
 444
 445         for (i = 0; i < 6; i++)
 446                 buf[i] = 0;
 447
 448         for (i = 0; i < nsamp; i++) {
 449                 tmp[0] = b43_phy_read(dev, B43_PHY_HT_RSSI_C1);
 450                 tmp[1] = b43_phy_read(dev, B43_PHY_HT_RSSI_C2);
 451                 tmp[2] = b43_phy_read(dev, B43_PHY_HT_RSSI_C3);
 452
 453                 buf[0] += ((s8)((tmp[0] & 0x3F) << 2)) >> 2;
 454                 buf[1] += ((s8)(((tmp[0] >> 8) & 0x3F) << 2)) >> 2;
 455                 buf[2] += ((s8)((tmp[1] & 0x3F) << 2)) >> 2;
 456                 buf[3] += ((s8)(((tmp[1] >> 8) & 0x3F) << 2)) >> 2;
 457                 buf[4] += ((s8)((tmp[2] & 0x3F) << 2)) >> 2;
 458                 buf[5] += ((s8)(((tmp[2] >> 8) & 0x3F) << 2)) >> 2;
 459         }
 460
 461         for (i = 0; i < 12; i++)
 462                 b43_phy_write(dev, phy_regs_to_save[i], phy_regs_values[i]);
 463 }
 464
 465 /**************************************************
 466  * Tx/Rx
 467  **************************************************/
 468
 469 static void b43_phy_ht_tx_power_fix(struct b43_wldev *dev)
 470 {
 471         int i;
 472
 473         for (i = 0; i < 3; i++) {
 474                 u16 mask;
 475                 u32 tmp = b43_httab_read(dev, B43_HTTAB32(26, 0xE8));
 476
 477                 if (0) /* FIXME */
 478                         mask = 0x2 << (i * 4);
 479                 else
 480                         mask = 0;
 481                 b43_phy_mask(dev, B43_PHY_EXTG(0x108), mask);
 482
 483                 b43_httab_write(dev, B43_HTTAB16(7, 0x110 + i), tmp >> 16);
 484                 b43_httab_write(dev, B43_HTTAB8(13, 0x63 + (i * 4)),
 485                                 tmp & 0xFF);
 486                 b43_httab_write(dev, B43_HTTAB8(13, 0x73 + (i * 4)),
 487                                 tmp & 0xFF);
 488         }
 489 }
 490
 491 static void b43_phy_ht_tx_power_ctl(struct b43_wldev *dev, bool enable)
 492 {
 493         struct b43_phy_ht *phy_ht = dev->phy.ht;
 494         u16 en_bits = B43_PHY_HT_TXPCTL_CMD_C1_COEFF |
 495                       B43_PHY_HT_TXPCTL_CMD_C1_HWPCTLEN |
 496                       B43_PHY_HT_TXPCTL_CMD_C1_PCTLEN;
 497         static const u16 cmd_regs[3] = { B43_PHY_HT_TXPCTL_CMD_C1,
 498                                          B43_PHY_HT_TXPCTL_CMD_C2,
 499                                          B43_PHY_HT_TXPCTL_CMD_C3 };
 500         int i;
 501
 502         if (!enable) {
 503                 if (b43_phy_read(dev, B43_PHY_HT_TXPCTL_CMD_C1) & en_bits) {
 504                         /* We disable enabled TX pwr ctl, save it's state */
 505                         /*
 506                          * TODO: find the registers. On N-PHY they were 0x1ed
 507                          * and 0x1ee, we need 3 such a registers for HT-PHY
 508                          */
 509                 }
 510                 b43_phy_mask(dev, B43_PHY_HT_TXPCTL_CMD_C1, ~en_bits);
 511         } else {
 512                 b43_phy_set(dev, B43_PHY_HT_TXPCTL_CMD_C1, en_bits);
 513
 514                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
 515                         for (i = 0; i < 3; i++)
 516                                 b43_phy_write(dev, cmd_regs[i], 0x32);
 517                 }
 518
 519                 for (i = 0; i < 3; i++)
 520                         if (phy_ht->tx_pwr_idx[i] <=
 521                             B43_PHY_HT_TXPCTL_CMD_C1_INIT)
 522                                 b43_phy_write(dev, cmd_regs[i],
 523                                               phy_ht->tx_pwr_idx[i]);
 524         }
 525
 526         phy_ht->tx_pwr_ctl = enable;
 527 }
 528
 529 static void b43_phy_ht_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
 530 {
 531         struct b43_phy_ht *phy_ht = dev->phy.ht;
 532         static const u16 base[] = { 0x840, 0x860, 0x880 };
 533         u16 save_regs[3][3];
 534         s32 rssi_buf[6];
 535         int core;
 536
 537         for (core = 0; core < 3; core++) {
 538                 save_regs[core][1] = b43_phy_read(dev, base[core] + 6);
 539                 save_regs[core][2] = b43_phy_read(dev, base[core] + 7);
 540                 save_regs[core][0] = b43_phy_read(dev, base[core] + 0);
 541
 542                 b43_phy_write(dev, base[core] + 6, 0);
 543                 b43_phy_mask(dev, base[core] + 7, ~0xF); /* 0xF? Or just 0x6? */
 544                 b43_phy_set(dev, base[core] + 0, 0x0400);
 545                 b43_phy_set(dev, base[core] + 0, 0x1000);
 546         }
 547
 548         b43_phy_ht_tx_tone(dev);
 549         udelay(20);
 550         b43_phy_ht_poll_rssi(dev, 4, rssi_buf, 1);
 551         b43_phy_ht_stop_playback(dev);
 552         b43_phy_ht_reset_cca(dev);
 553
 554         phy_ht->idle_tssi[0] = rssi_buf[0] & 0xff;
 555         phy_ht->idle_tssi[1] = rssi_buf[2] & 0xff;
 556         phy_ht->idle_tssi[2] = rssi_buf[4] & 0xff;
 557
 558         for (core = 0; core < 3; core++) {
 559                 b43_phy_write(dev, base[core] + 0, save_regs[core][0]);
 560                 b43_phy_write(dev, base[core] + 6, save_regs[core][1]);
 561                 b43_phy_write(dev, base[core] + 7, save_regs[core][2]);
 562         }
 563 }
 564
 565 static void b43_phy_ht_tx_power_ctl_setup(struct b43_wldev *dev)
 566 {
 567         struct b43_phy_ht *phy_ht = dev->phy.ht;
 568         struct ssb_sprom *sprom = dev->dev->bus_sprom;
 569
 570         u8 *idle = phy_ht->idle_tssi;
 571         u8 target[3];
 572         s16 a1[3], b0[3], b1[3];
 573
 574         u16 freq = dev->phy.channel_freq;
 575         int i, c;
 576
 577         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 578                 for (c = 0; c < 3; c++) {
 579                         target[c] = sprom->core_pwr_info[c].maxpwr_2g;
 580                         a1[c] = sprom->core_pwr_info[c].pa_2g[0];
 581                         b0[c] = sprom->core_pwr_info[c].pa_2g[1];
 582                         b1[c] = sprom->core_pwr_info[c].pa_2g[2];
 583                 }
 584         } else if (freq >= 4900 && freq < 5100) {
 585                 for (c = 0; c < 3; c++) {
 586                         target[c] = sprom->core_pwr_info[c].maxpwr_5gl;
 587                         a1[c] = sprom->core_pwr_info[c].pa_5gl[0];
 588                         b0[c] = sprom->core_pwr_info[c].pa_5gl[1];
 589                         b1[c] = sprom->core_pwr_info[c].pa_5gl[2];
 590                 }
 591         } else if (freq >= 5100 && freq < 5500) {
 592                 for (c = 0; c < 3; c++) {
 593                         target[c] = sprom->core_pwr_info[c].maxpwr_5g;
 594                         a1[c] = sprom->core_pwr_info[c].pa_5g[0];
 595                         b0[c] = sprom->core_pwr_info[c].pa_5g[1];
 596                         b1[c] = sprom->core_pwr_info[c].pa_5g[2];
 597                 }
 598         } else if (freq >= 5500) {
 599                 for (c = 0; c < 3; c++) {
 600                         target[c] = sprom->core_pwr_info[c].maxpwr_5gh;
 601                         a1[c] = sprom->core_pwr_info[c].pa_5gh[0];
 602                         b0[c] = sprom->core_pwr_info[c].pa_5gh[1];
 603                         b1[c] = sprom->core_pwr_info[c].pa_5gh[2];
 604                 }
 605         } else {
 606                 target[0] = target[1] = target[2] = 52;
 607                 a1[0] = a1[1] = a1[2] = -424;
 608                 b0[0] = b0[1] = b0[2] = 5612;
 609                 b1[0] = b1[1] = b1[2] = -1393;
 610         }
 611
 612         b43_phy_set(dev, B43_PHY_HT_TSSIMODE, B43_PHY_HT_TSSIMODE_EN);
 613         b43_phy_mask(dev, B43_PHY_HT_TXPCTL_CMD_C1,
 614                      ~B43_PHY_HT_TXPCTL_CMD_C1_PCTLEN & 0xFFFF);
 615
 616         /* TODO: Does it depend on sprom->fem.ghz2.tssipos? */
 617         b43_phy_set(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI, 0x4000);
 618
 619         b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C1,
 620                         ~B43_PHY_HT_TXPCTL_CMD_C1_INIT, 0x19);
 621         b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C2,
 622                         ~B43_PHY_HT_TXPCTL_CMD_C2_INIT, 0x19);
 623         b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C3,
 624                         ~B43_PHY_HT_TXPCTL_CMD_C3_INIT, 0x19);
 625
 626         b43_phy_set(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI,
 627                     B43_PHY_HT_TXPCTL_IDLE_TSSI_BINF);
 628
 629         b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI,
 630                         ~B43_PHY_HT_TXPCTL_IDLE_TSSI_C1,
 631                         idle[0] << B43_PHY_HT_TXPCTL_IDLE_TSSI_C1_SHIFT);
 632         b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI,
 633                         ~B43_PHY_HT_TXPCTL_IDLE_TSSI_C2,
 634                         idle[1] << B43_PHY_HT_TXPCTL_IDLE_TSSI_C2_SHIFT);
 635         b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI2,
 636                         ~B43_PHY_HT_TXPCTL_IDLE_TSSI2_C3,
 637                         idle[2] << B43_PHY_HT_TXPCTL_IDLE_TSSI2_C3_SHIFT);
 638
 639         b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_N, ~B43_PHY_HT_TXPCTL_N_TSSID,
 640                         0xf0);
 641         b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_N, ~B43_PHY_HT_TXPCTL_N_NPTIL2,
 642                         0x3 << B43_PHY_HT_TXPCTL_N_NPTIL2_SHIFT);
 643 #if 0
 644         /* TODO: what to mask/set? */
 645         b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C1, 0x800, 0)
 646         b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C1, 0x400, 0)
 647 #endif
 648
 649         b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_TARG_PWR,
 650                         ~B43_PHY_HT_TXPCTL_TARG_PWR_C1,
 651                         target[0] << B43_PHY_HT_TXPCTL_TARG_PWR_C1_SHIFT);
 652         b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_TARG_PWR,
 653                         ~B43_PHY_HT_TXPCTL_TARG_PWR_C2 & 0xFFFF,
 654                         target[1] << B43_PHY_HT_TXPCTL_TARG_PWR_C2_SHIFT);
 655         b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_TARG_PWR2,
 656                         ~B43_PHY_HT_TXPCTL_TARG_PWR2_C3,
 657                         target[2] << B43_PHY_HT_TXPCTL_TARG_PWR2_C3_SHIFT);
 658
 659         for (c = 0; c < 3; c++) {
 660                 s32 num, den, pwr;
 661                 u32 regval[64];
 662
 663                 for (i = 0; i < 64; i++) {
 664                         num = 8 * (16 * b0[c] + b1[c] * i);
 665                         den = 32768 + a1[c] * i;
 666                         pwr = max((4 * num + den / 2) / den, -8);
 667                         regval[i] = pwr;
 668                 }
 669                 b43_httab_write_bulk(dev, B43_HTTAB16(26 + c, 0), 64, regval);
 670         }
 671 }
 672
 673 /**************************************************
 674  * Channel switching ops.
 675  **************************************************/
 676
 677 static void b43_phy_ht_spur_avoid(struct b43_wldev *dev,
 678                                   struct ieee80211_channel *new_channel)
 679 {
 680         struct bcma_device *core = dev->dev->bdev;
 681         int spuravoid = 0;
 682         u16 tmp;
 683
 684         /* Check for 13 and 14 is just a guess, we don't have enough logs. */
 685         if (new_channel->hw_value == 13 || new_channel->hw_value == 14)
 686                 spuravoid = 1;
 687         bcma_core_pll_ctl(core, B43_BCMA_CLKCTLST_PHY_PLL_REQ, 0, false);
 688         bcma_pmu_spuravoid_pllupdate(&core->bus->drv_cc, spuravoid);
 689         bcma_core_pll_ctl(core,
 690                           B43_BCMA_CLKCTLST_80211_PLL_REQ |
 691                           B43_BCMA_CLKCTLST_PHY_PLL_REQ,
 692                           B43_BCMA_CLKCTLST_80211_PLL_ST |
 693                           B43_BCMA_CLKCTLST_PHY_PLL_ST, false);
 694
 695         /* Values has been taken from wlc_bmac_switch_macfreq comments */
 696         switch (spuravoid) {
 697         case 2: /* 126MHz */
 698                 tmp = 0x2082;
 699                 break;
 700         case 1: /* 123MHz */
 701                 tmp = 0x5341;
 702                 break;
 703         default: /* 120MHz */
 704                 tmp = 0x8889;
 705         }
 706
 707         b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, tmp);
 708         b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
 709
 710         /* TODO: reset PLL */
 711
 712         if (spuravoid)
 713                 b43_phy_set(dev, B43_PHY_HT_BBCFG, B43_PHY_HT_BBCFG_RSTRX);
 714         else
 715                 b43_phy_mask(dev, B43_PHY_HT_BBCFG,
 716                                 ~B43_PHY_HT_BBCFG_RSTRX & 0xFFFF);
 717
 718         b43_phy_ht_reset_cca(dev);
 719 }
 720
 721 static void b43_phy_ht_channel_setup(struct b43_wldev *dev,
 722                                 const struct b43_phy_ht_channeltab_e_phy *e,
 723                                 struct ieee80211_channel *new_channel)
 724 {
 725         bool old_band_5ghz;
 726
 727         old_band_5ghz = b43_phy_read(dev, B43_PHY_HT_BANDCTL) & 0; /* FIXME */
 728         if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
 729                 /* TODO */
 730         } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
 731                 /* TODO */
 732         }
 733
 734         b43_phy_write(dev, B43_PHY_HT_BW1, e->bw1);
 735         b43_phy_write(dev, B43_PHY_HT_BW2, e->bw2);
 736         b43_phy_write(dev, B43_PHY_HT_BW3, e->bw3);
 737         b43_phy_write(dev, B43_PHY_HT_BW4, e->bw4);
 738         b43_phy_write(dev, B43_PHY_HT_BW5, e->bw5);
 739         b43_phy_write(dev, B43_PHY_HT_BW6, e->bw6);
 740
 741         if (new_channel->hw_value == 14) {
 742                 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_OFDM_EN, 0);
 743                 b43_phy_set(dev, B43_PHY_HT_TEST, 0x0800);
 744         } else {
 745                 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_OFDM_EN,
 746                                       B43_PHY_HT_CLASS_CTL_OFDM_EN);
 747                 if (new_channel->band == IEEE80211_BAND_2GHZ)
 748                         b43_phy_mask(dev, B43_PHY_HT_TEST, ~0x840);
 749         }
 750
 751         if (1) /* TODO: On N it's for early devices only, what about HT? */
 752                 b43_phy_ht_tx_power_fix(dev);
 753
 754         b43_phy_ht_spur_avoid(dev, new_channel);
 755
 756         b43_phy_write(dev, 0x017e, 0x3830);
 757 }
 758
 759 static int b43_phy_ht_set_channel(struct b43_wldev *dev,
 760                                   struct ieee80211_channel *channel,
 761                                   enum nl80211_channel_type channel_type)
 762 {
 763         struct b43_phy *phy = &dev->phy;
 764
 765         const struct b43_phy_ht_channeltab_e_radio2059 *chent_r2059 = NULL;
 766
 767         if (phy->radio_ver == 0x2059) {
 768                 chent_r2059 = b43_phy_ht_get_channeltab_e_r2059(dev,
 769                                                         channel->center_freq);
 770                 if (!chent_r2059)
 771                         return -ESRCH;
 772         } else {
 773                 return -ESRCH;
 774         }
 775
 776         /* TODO: In case of N-PHY some bandwidth switching goes here */
 777
 778         if (phy->radio_ver == 0x2059) {
 779                 b43_radio_2059_channel_setup(dev, chent_r2059);
 780                 b43_phy_ht_channel_setup(dev, &(chent_r2059->phy_regs),
 781                                          channel);
 782         } else {
 783                 return -ESRCH;
 784         }
 785
 786         return 0;
 787 }
 788
 789 /**************************************************
 790  * Basic PHY ops.
 791  **************************************************/
 792
 793 static int b43_phy_ht_op_allocate(struct b43_wldev *dev)
 794 {
 795         struct b43_phy_ht *phy_ht;
 796
 797         phy_ht = kzalloc(sizeof(*phy_ht), GFP_KERNEL);
 798         if (!phy_ht)
 799                 return -ENOMEM;
 800         dev->phy.ht = phy_ht;
 801
 802         return 0;
 803 }
 804
 805 static void b43_phy_ht_op_prepare_structs(struct b43_wldev *dev)
 806 {
 807         struct b43_phy *phy = &dev->phy;
 808         struct b43_phy_ht *phy_ht = phy->ht;
 809         int i;
 810
 811         memset(phy_ht, 0, sizeof(*phy_ht));
 812
 813         phy_ht->tx_pwr_ctl = true;
 814         for (i = 0; i < 3; i++)
 815                 phy_ht->tx_pwr_idx[i] = B43_PHY_HT_TXPCTL_CMD_C1_INIT + 1;
 816
 817         for (i = 0; i < 3; i++)
 818                 phy_ht->bb_mult_save[i] = -1;
 819 }
 820
 821 static int b43_phy_ht_op_init(struct b43_wldev *dev)
 822 {
 823         struct b43_phy_ht *phy_ht = dev->phy.ht;
 824         u16 tmp;
 825         u16 clip_state[3];
 826         bool saved_tx_pwr_ctl;
 827
 828         if (dev->dev->bus_type != B43_BUS_BCMA) {
 829                 b43err(dev->wl, "HT-PHY is supported only on BCMA bus!\n");
 830                 return -EOPNOTSUPP;
 831         }
 832
 833         b43_phy_ht_tables_init(dev);
 834
 835         b43_phy_mask(dev, 0x0be, ~0x2);
 836         b43_phy_set(dev, 0x23f, 0x7ff);
 837         b43_phy_set(dev, 0x240, 0x7ff);
 838         b43_phy_set(dev, 0x241, 0x7ff);
 839
 840         b43_phy_ht_zero_extg(dev);
 841
 842         b43_phy_mask(dev, B43_PHY_EXTG(0), ~0x3);
 843
 844         b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0);
 845         b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0);
 846         b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0);
 847
 848         b43_phy_write(dev, B43_PHY_EXTG(0x103), 0x20);
 849         b43_phy_write(dev, B43_PHY_EXTG(0x101), 0x20);
 850         b43_phy_write(dev, 0x20d, 0xb8);
 851         b43_phy_write(dev, B43_PHY_EXTG(0x14f), 0xc8);
 852         b43_phy_write(dev, 0x70, 0x50);
 853         b43_phy_write(dev, 0x1ff, 0x30);
 854
 855         if (0) /* TODO: condition */
 856                 ; /* TODO: PHY op on reg 0x217 */
 857
 858         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
 859                 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_CCK_EN, 0);
 860         else
 861                 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_CCK_EN,
 862                                       B43_PHY_HT_CLASS_CTL_CCK_EN);
 863
 864         b43_phy_set(dev, 0xb1, 0x91);
 865         b43_phy_write(dev, 0x32f, 0x0003);
 866         b43_phy_write(dev, 0x077, 0x0010);
 867         b43_phy_write(dev, 0x0b4, 0x0258);
 868         b43_phy_mask(dev, 0x17e, ~0x4000);
 869
 870         b43_phy_write(dev, 0x0b9, 0x0072);
 871
 872         b43_httab_write_few(dev, B43_HTTAB16(7, 0x14e), 2, 0x010f, 0x010f);
 873         b43_httab_write_few(dev, B43_HTTAB16(7, 0x15e), 2, 0x010f, 0x010f);
 874         b43_httab_write_few(dev, B43_HTTAB16(7, 0x16e), 2, 0x010f, 0x010f);
 875
 876         b43_phy_ht_afe_unk1(dev);
 877
 878         b43_httab_write_few(dev, B43_HTTAB16(7, 0x130), 9, 0x777, 0x111, 0x111,
 879                             0x777, 0x111, 0x111, 0x777, 0x111, 0x111);
 880
 881         b43_httab_write(dev, B43_HTTAB16(7, 0x120), 0x0777);
 882         b43_httab_write(dev, B43_HTTAB16(7, 0x124), 0x0777);
 883
 884         b43_httab_write(dev, B43_HTTAB16(8, 0x00), 0x02);
 885         b43_httab_write(dev, B43_HTTAB16(8, 0x10), 0x02);
 886         b43_httab_write(dev, B43_HTTAB16(8, 0x20), 0x02);
 887
 888         b43_httab_write_few(dev, B43_HTTAB16(8, 0x08), 4,
 889                             0x8e, 0x96, 0x96, 0x96);
 890         b43_httab_write_few(dev, B43_HTTAB16(8, 0x18), 4,
 891                             0x8f, 0x9f, 0x9f, 0x9f);
 892         b43_httab_write_few(dev, B43_HTTAB16(8, 0x28), 4,
 893                             0x8f, 0x9f, 0x9f, 0x9f);
 894
 895         b43_httab_write_few(dev, B43_HTTAB16(8, 0x0c), 4, 0x2, 0x2, 0x2, 0x2);
 896         b43_httab_write_few(dev, B43_HTTAB16(8, 0x1c), 4, 0x2, 0x2, 0x2, 0x2);
 897         b43_httab_write_few(dev, B43_HTTAB16(8, 0x2c), 4, 0x2, 0x2, 0x2, 0x2);
 898
 899         b43_phy_maskset(dev, 0x0280, 0xff00, 0x3e);
 900         b43_phy_maskset(dev, 0x0283, 0xff00, 0x3e);
 901         b43_phy_maskset(dev, B43_PHY_OFDM(0x0141), 0xff00, 0x46);
 902         b43_phy_maskset(dev, 0x0283, 0xff00, 0x40);
 903
 904         b43_httab_write_few(dev, B43_HTTAB16(00, 0x8), 4,
 905                             0x09, 0x0e, 0x13, 0x18);
 906         b43_httab_write_few(dev, B43_HTTAB16(01, 0x8), 4,
 907                             0x09, 0x0e, 0x13, 0x18);
 908         /* TODO: Did wl mean 2 instead of 40? */
 909         b43_httab_write_few(dev, B43_HTTAB16(40, 0x8), 4,
 910                             0x09, 0x0e, 0x13, 0x18);
 911
 912         b43_phy_maskset(dev, B43_PHY_OFDM(0x24), 0x3f, 0xd);
 913         b43_phy_maskset(dev, B43_PHY_OFDM(0x64), 0x3f, 0xd);
 914         b43_phy_maskset(dev, B43_PHY_OFDM(0xa4), 0x3f, 0xd);
 915
 916         b43_phy_set(dev, B43_PHY_EXTG(0x060), 0x1);
 917         b43_phy_set(dev, B43_PHY_EXTG(0x064), 0x1);
 918         b43_phy_set(dev, B43_PHY_EXTG(0x080), 0x1);
 919         b43_phy_set(dev, B43_PHY_EXTG(0x084), 0x1);
 920
 921         /* Copy some tables entries */
 922         tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x144));
 923         b43_httab_write(dev, B43_HTTAB16(7, 0x14a), tmp);
 924         tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x154));
 925         b43_httab_write(dev, B43_HTTAB16(7, 0x15a), tmp);
 926         tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x164));
 927         b43_httab_write(dev, B43_HTTAB16(7, 0x16a), tmp);
 928
 929         /* Reset CCA */
 930         b43_phy_force_clock(dev, true);
 931         tmp = b43_phy_read(dev, B43_PHY_HT_BBCFG);
 932         b43_phy_write(dev, B43_PHY_HT_BBCFG, tmp | B43_PHY_HT_BBCFG_RSTCCA);
 933         b43_phy_write(dev, B43_PHY_HT_BBCFG, tmp & ~B43_PHY_HT_BBCFG_RSTCCA);
 934         b43_phy_force_clock(dev, false);
 935
 936         b43_mac_phy_clock_set(dev, true);
 937
 938         b43_phy_ht_pa_override(dev, false);
 939         b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RX2TX);
 940         b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RST2RX);
 941         b43_phy_ht_pa_override(dev, true);
 942
 943         /* TODO: Should we restore it? Or store it in global PHY info? */
 944         b43_phy_ht_classifier(dev, 0, 0);
 945         b43_phy_ht_read_clip_detection(dev, clip_state);
 946
 947         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 948                 b43_phy_ht_bphy_init(dev);
 949
 950         b43_httab_write_bulk(dev, B43_HTTAB32(0x1a, 0xc0),
 951                         B43_HTTAB_1A_C0_LATE_SIZE, b43_httab_0x1a_0xc0_late);
 952
 953         saved_tx_pwr_ctl = phy_ht->tx_pwr_ctl;
 954         b43_phy_ht_tx_power_fix(dev);
 955         b43_phy_ht_tx_power_ctl(dev, false);
 956         b43_phy_ht_tx_power_ctl_idle_tssi(dev);
 957         b43_phy_ht_tx_power_ctl_setup(dev);
 958         b43_phy_ht_tx_power_ctl(dev, saved_tx_pwr_ctl);
 959
 960         return 0;
 961 }
 962
 963 static void b43_phy_ht_op_free(struct b43_wldev *dev)
 964 {
 965         struct b43_phy *phy = &dev->phy;
 966         struct b43_phy_ht *phy_ht = phy->ht;
 967
 968         kfree(phy_ht);
 969         phy->ht = NULL;
 970 }
 971
 972 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
 973 static void b43_phy_ht_op_software_rfkill(struct b43_wldev *dev,
 974                                         bool blocked)
 975 {
 976         if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
 977                 b43err(dev->wl, "MAC not suspended\n");
 978
 979         /* In the following PHY ops we copy wl's dummy behaviour.
 980          * TODO: Find out if reads (currently hidden in masks/masksets) are
 981          * needed and replace following ops with just writes or w&r.
 982          * Note: B43_PHY_HT_RF_CTL1 register is tricky, wrong operation can
 983          * cause delayed (!) machine lock up. */
 984         if (blocked) {
 985                 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
 986         } else {
 987                 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
 988                 b43_phy_maskset(dev, B43_PHY_HT_RF_CTL1, 0, 0x1);
 989                 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
 990                 b43_phy_maskset(dev, B43_PHY_HT_RF_CTL1, 0, 0x2);
 991
 992                 if (dev->phy.radio_ver == 0x2059)
 993                         b43_radio_2059_init(dev);
 994                 else
 995                         B43_WARN_ON(1);
 996
 997                 b43_switch_channel(dev, dev->phy.channel);
 998         }
 999 }
1000
1001 static void b43_phy_ht_op_switch_analog(struct b43_wldev *dev, bool on)
1002 {
1003         if (on) {
1004                 b43_phy_write(dev, B43_PHY_HT_AFE_C1, 0x00cd);
1005                 b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0x0000);
1006                 b43_phy_write(dev, B43_PHY_HT_AFE_C2, 0x00cd);
1007                 b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0x0000);
1008                 b43_phy_write(dev, B43_PHY_HT_AFE_C3, 0x00cd);
1009                 b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0x0000);
1010         } else {
1011                 b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0x07ff);
1012                 b43_phy_write(dev, B43_PHY_HT_AFE_C1, 0x00fd);
1013                 b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0x07ff);
1014                 b43_phy_write(dev, B43_PHY_HT_AFE_C2, 0x00fd);
1015                 b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0x07ff);
1016                 b43_phy_write(dev, B43_PHY_HT_AFE_C3, 0x00fd);
1017         }
1018 }
1019
1020 static int b43_phy_ht_op_switch_channel(struct b43_wldev *dev,
1021                                         unsigned int new_channel)
1022 {
1023         struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan;
1024         enum nl80211_channel_type channel_type =
1025                 cfg80211_get_chandef_type(&dev->wl->hw->conf.chandef);
1026
1027         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1028                 if ((new_channel < 1) || (new_channel > 14))
1029                         return -EINVAL;
1030         } else {
1031                 return -EINVAL;
1032         }
1033
1034         return b43_phy_ht_set_channel(dev, channel, channel_type);
1035 }
1036
1037 static unsigned int b43_phy_ht_op_get_default_chan(struct b43_wldev *dev)
1038 {
1039         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1040                 return 11;
1041         return 36;
1042 }
1043
1044 /**************************************************
1045  * R/W ops.
1046  **************************************************/
1047
1048 static u16 b43_phy_ht_op_read(struct b43_wldev *dev, u16 reg)
1049 {
1050         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1051         return b43_read16(dev, B43_MMIO_PHY_DATA);
1052 }
1053
1054 static void b43_phy_ht_op_write(struct b43_wldev *dev, u16 reg, u16 value)
1055 {
1056         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1057         b43_write16(dev, B43_MMIO_PHY_DATA, value);
1058 }
1059
1060 static void b43_phy_ht_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
1061                                  u16 set)
1062 {
1063         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1064         b43_write16(dev, B43_MMIO_PHY_DATA,
1065                     (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
1066 }
1067
1068 static u16 b43_phy_ht_op_radio_read(struct b43_wldev *dev, u16 reg)
1069 {
1070         /* HT-PHY needs 0x200 for read access */
1071         reg |= 0x200;
1072
1073         b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
1074         return b43_read16(dev, B43_MMIO_RADIO24_DATA);
1075 }
1076
1077 static void b43_phy_ht_op_radio_write(struct b43_wldev *dev, u16 reg,
1078                                       u16 value)
1079 {
1080         b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
1081         b43_write16(dev, B43_MMIO_RADIO24_DATA, value);
1082 }
1083
1084 static enum b43_txpwr_result
1085 b43_phy_ht_op_recalc_txpower(struct b43_wldev *dev, bool ignore_tssi)
1086 {
1087         return B43_TXPWR_RES_DONE;
1088 }
1089
1090 static void b43_phy_ht_op_adjust_txpower(struct b43_wldev *dev)
1091 {
1092 }
1093
1094 /**************************************************
1095  * PHY ops struct.
1096  **************************************************/
1097
1098 const struct b43_phy_operations b43_phyops_ht = {
1099         .allocate               = b43_phy_ht_op_allocate,
1100         .free                   = b43_phy_ht_op_free,
1101         .prepare_structs        = b43_phy_ht_op_prepare_structs,
1102         .init                   = b43_phy_ht_op_init,
1103         .phy_read               = b43_phy_ht_op_read,
1104         .phy_write              = b43_phy_ht_op_write,
1105         .phy_maskset            = b43_phy_ht_op_maskset,
1106         .radio_read             = b43_phy_ht_op_radio_read,
1107         .radio_write            = b43_phy_ht_op_radio_write,
1108         .software_rfkill        = b43_phy_ht_op_software_rfkill,
1109         .switch_analog          = b43_phy_ht_op_switch_analog,
1110         .switch_channel         = b43_phy_ht_op_switch_channel,
1111         .get_default_chan       = b43_phy_ht_op_get_default_chan,
1112         .recalc_txpower         = b43_phy_ht_op_recalc_txpower,
1113         .adjust_txpower         = b43_phy_ht_op_adjust_txpower,
1114 };