Pileus Git - ~andy/linux/blob - drivers/net/wireless/b43/phy_ht.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n HT-PHY support
   5
   6   Copyright (c) 2011 Rafał Miłecki <zajec5@gmail.com>
   7
   8   This program is free software; you can redistribute it and/or modify
   9   it under the terms of the GNU General Public License as published by
  10   the Free Software Foundation; either version 2 of the License, or
  11   (at your option) any later version.
  12
  13   This program is distributed in the hope that it will be useful,
  14   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16   GNU General Public License for more details.
  17
  18   You should have received a copy of the GNU General Public License
  19   along with this program; see the file COPYING.  If not, write to
  20   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  21   Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #include <linux/slab.h>
  26
  27 #include "b43.h"
  28 #include "phy_ht.h"
  29 #include "tables_phy_ht.h"
  30 #include "radio_2059.h"
  31 #include "main.h"
  32
  33 /**************************************************
  34  * Radio 2059.
  35  **************************************************/
  36
  37 static void b43_radio_2059_channel_setup(struct b43_wldev *dev,
  38                         const struct b43_phy_ht_channeltab_e_radio2059 *e)
  39 {
  40         u8 i;
  41         u16 routing;
  42
  43         b43_radio_write(dev, 0x16, e->radio_syn16);
  44         b43_radio_write(dev, 0x17, e->radio_syn17);
  45         b43_radio_write(dev, 0x22, e->radio_syn22);
  46         b43_radio_write(dev, 0x25, e->radio_syn25);
  47         b43_radio_write(dev, 0x27, e->radio_syn27);
  48         b43_radio_write(dev, 0x28, e->radio_syn28);
  49         b43_radio_write(dev, 0x29, e->radio_syn29);
  50         b43_radio_write(dev, 0x2c, e->radio_syn2c);
  51         b43_radio_write(dev, 0x2d, e->radio_syn2d);
  52         b43_radio_write(dev, 0x37, e->radio_syn37);
  53         b43_radio_write(dev, 0x41, e->radio_syn41);
  54         b43_radio_write(dev, 0x43, e->radio_syn43);
  55         b43_radio_write(dev, 0x47, e->radio_syn47);
  56         b43_radio_write(dev, 0x4a, e->radio_syn4a);
  57         b43_radio_write(dev, 0x58, e->radio_syn58);
  58         b43_radio_write(dev, 0x5a, e->radio_syn5a);
  59         b43_radio_write(dev, 0x6a, e->radio_syn6a);
  60         b43_radio_write(dev, 0x6d, e->radio_syn6d);
  61         b43_radio_write(dev, 0x6e, e->radio_syn6e);
  62         b43_radio_write(dev, 0x92, e->radio_syn92);
  63         b43_radio_write(dev, 0x98, e->radio_syn98);
  64
  65         for (i = 0; i < 2; i++) {
  66                 routing = i ? R2059_RXRX1 : R2059_TXRX0;
  67                 b43_radio_write(dev, routing | 0x4a, e->radio_rxtx4a);
  68                 b43_radio_write(dev, routing | 0x58, e->radio_rxtx58);
  69                 b43_radio_write(dev, routing | 0x5a, e->radio_rxtx5a);
  70                 b43_radio_write(dev, routing | 0x6a, e->radio_rxtx6a);
  71                 b43_radio_write(dev, routing | 0x6d, e->radio_rxtx6d);
  72                 b43_radio_write(dev, routing | 0x6e, e->radio_rxtx6e);
  73                 b43_radio_write(dev, routing | 0x92, e->radio_rxtx92);
  74                 b43_radio_write(dev, routing | 0x98, e->radio_rxtx98);
  75         }
  76
  77         udelay(50);
  78
  79         /* Calibration */
  80         b43_radio_mask(dev, 0x2b, ~0x1);
  81         b43_radio_mask(dev, 0x2e, ~0x4);
  82         b43_radio_set(dev, 0x2e, 0x4);
  83         b43_radio_set(dev, 0x2b, 0x1);
  84
  85         udelay(300);
  86 }
  87
  88 static void b43_radio_2059_init(struct b43_wldev *dev)
  89 {
  90         const u16 routing[] = { R2059_SYN, R2059_TXRX0, R2059_RXRX1 };
  91         const u16 radio_values[3][2] = {
  92                 { 0x61, 0xE9 }, { 0x69, 0xD5 }, { 0x73, 0x99 },
  93         };
  94         u16 i, j;
  95
  96         b43_radio_write(dev, R2059_ALL | 0x51, 0x0070);
  97         b43_radio_write(dev, R2059_ALL | 0x5a, 0x0003);
  98
  99         for (i = 0; i < ARRAY_SIZE(routing); i++)
 100                 b43_radio_set(dev, routing[i] | 0x146, 0x3);
 101
 102         b43_radio_set(dev, 0x2e, 0x0078);
 103         b43_radio_set(dev, 0xc0, 0x0080);
 104         msleep(2);
 105         b43_radio_mask(dev, 0x2e, ~0x0078);
 106         b43_radio_mask(dev, 0xc0, ~0x0080);
 107
 108         if (1) { /* FIXME */
 109                 b43_radio_set(dev, R2059_RXRX1 | 0x4, 0x1);
 110                 udelay(10);
 111                 b43_radio_set(dev, R2059_RXRX1 | 0x0BF, 0x1);
 112                 b43_radio_maskset(dev, R2059_RXRX1 | 0x19B, 0x3, 0x2);
 113
 114                 b43_radio_set(dev, R2059_RXRX1 | 0x4, 0x2);
 115                 udelay(100);
 116                 b43_radio_mask(dev, R2059_RXRX1 | 0x4, ~0x2);
 117
 118                 for (i = 0; i < 10000; i++) {
 119                         if (b43_radio_read(dev, R2059_RXRX1 | 0x145) & 1) {
 120                                 i = 0;
 121                                 break;
 122                         }
 123                         udelay(100);
 124                 }
 125                 if (i)
 126                         b43err(dev->wl, "radio 0x945 timeout\n");
 127
 128                 b43_radio_mask(dev, R2059_RXRX1 | 0x4, ~0x1);
 129                 b43_radio_set(dev, 0xa, 0x60);
 130
 131                 for (i = 0; i < 3; i++) {
 132                         b43_radio_write(dev, 0x17F, radio_values[i][0]);
 133                         b43_radio_write(dev, 0x13D, 0x6E);
 134                         b43_radio_write(dev, 0x13E, radio_values[i][1]);
 135                         b43_radio_write(dev, 0x13C, 0x55);
 136
 137                         for (j = 0; j < 10000; j++) {
 138                                 if (b43_radio_read(dev, 0x140) & 2) {
 139                                         j = 0;
 140                                         break;
 141                                 }
 142                                 udelay(500);
 143                         }
 144                         if (j)
 145                                 b43err(dev->wl, "radio 0x140 timeout\n");
 146
 147                         b43_radio_write(dev, 0x13C, 0x15);
 148                 }
 149
 150                 b43_radio_mask(dev, 0x17F, ~0x1);
 151         }
 152
 153         b43_radio_mask(dev, 0x11, ~0x0008);
 154 }
 155
 156 /**************************************************
 157  * RF
 158  **************************************************/
 159
 160 static void b43_phy_ht_force_rf_sequence(struct b43_wldev *dev, u16 rf_seq)
 161 {
 162         u8 i;
 163
 164         u16 save_seq_mode = b43_phy_read(dev, B43_PHY_HT_RF_SEQ_MODE);
 165         b43_phy_set(dev, B43_PHY_HT_RF_SEQ_MODE, 0x3);
 166
 167         b43_phy_set(dev, B43_PHY_HT_RF_SEQ_TRIG, rf_seq);
 168         for (i = 0; i < 200; i++) {
 169                 if (!(b43_phy_read(dev, B43_PHY_HT_RF_SEQ_STATUS) & rf_seq)) {
 170                         i = 0;
 171                         break;
 172                 }
 173                 msleep(1);
 174         }
 175         if (i)
 176                 b43err(dev->wl, "Forcing RF sequence timeout\n");
 177
 178         b43_phy_write(dev, B43_PHY_HT_RF_SEQ_MODE, save_seq_mode);
 179 }
 180
 181 static void b43_phy_ht_pa_override(struct b43_wldev *dev, bool enable)
 182 {
 183         struct b43_phy_ht *htphy = dev->phy.ht;
 184         static const u16 regs[3] = { B43_PHY_HT_RF_CTL_INT_C1,
 185                                      B43_PHY_HT_RF_CTL_INT_C2,
 186                                      B43_PHY_HT_RF_CTL_INT_C3 };
 187         int i;
 188
 189         if (enable) {
 190                 for (i = 0; i < 3; i++)
 191                         b43_phy_write(dev, regs[i], htphy->rf_ctl_int_save[i]);
 192         } else {
 193                 for (i = 0; i < 3; i++)
 194                         htphy->rf_ctl_int_save[i] = b43_phy_read(dev, regs[i]);
 195                 /* TODO: Does 5GHz band use different value (not 0x0400)? */
 196                 for (i = 0; i < 3; i++)
 197                         b43_phy_write(dev, regs[i], 0x0400);
 198         }
 199 }
 200
 201 /**************************************************
 202  * Various PHY ops
 203  **************************************************/
 204
 205 static u16 b43_phy_ht_classifier(struct b43_wldev *dev, u16 mask, u16 val)
 206 {
 207         u16 tmp;
 208         u16 allowed = B43_PHY_HT_CLASS_CTL_CCK_EN |
 209                       B43_PHY_HT_CLASS_CTL_OFDM_EN |
 210                       B43_PHY_HT_CLASS_CTL_WAITED_EN;
 211
 212         tmp = b43_phy_read(dev, B43_PHY_HT_CLASS_CTL);
 213         tmp &= allowed;
 214         tmp &= ~mask;
 215         tmp |= (val & mask);
 216         b43_phy_maskset(dev, B43_PHY_HT_CLASS_CTL, ~allowed, tmp);
 217
 218         return tmp;
 219 }
 220
 221 static void b43_phy_ht_reset_cca(struct b43_wldev *dev)
 222 {
 223         u16 bbcfg;
 224
 225         b43_phy_force_clock(dev, true);
 226         bbcfg = b43_phy_read(dev, B43_PHY_HT_BBCFG);
 227         b43_phy_write(dev, B43_PHY_HT_BBCFG, bbcfg | B43_PHY_HT_BBCFG_RSTCCA);
 228         udelay(1);
 229         b43_phy_write(dev, B43_PHY_HT_BBCFG, bbcfg & ~B43_PHY_HT_BBCFG_RSTCCA);
 230         b43_phy_force_clock(dev, false);
 231
 232         b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RST2RX);
 233 }
 234
 235 static void b43_phy_ht_zero_extg(struct b43_wldev *dev)
 236 {
 237         u8 i, j;
 238         u16 base[] = { 0x40, 0x60, 0x80 };
 239
 240         for (i = 0; i < ARRAY_SIZE(base); i++) {
 241                 for (j = 0; j < 4; j++)
 242                         b43_phy_write(dev, B43_PHY_EXTG(base[i] + j), 0);
 243         }
 244
 245         for (i = 0; i < ARRAY_SIZE(base); i++)
 246                 b43_phy_write(dev, B43_PHY_EXTG(base[i] + 0xc), 0);
 247 }
 248
 249 /* Some unknown AFE (Analog Frondned) op */
 250 static void b43_phy_ht_afe_unk1(struct b43_wldev *dev)
 251 {
 252         u8 i;
 253
 254         static const u16 ctl_regs[3][2] = {
 255                 { B43_PHY_HT_AFE_C1_OVER, B43_PHY_HT_AFE_C1 },
 256                 { B43_PHY_HT_AFE_C2_OVER, B43_PHY_HT_AFE_C2 },
 257                 { B43_PHY_HT_AFE_C3_OVER, B43_PHY_HT_AFE_C3},
 258         };
 259
 260         for (i = 0; i < 3; i++) {
 261                 /* TODO: verify masks&sets */
 262                 b43_phy_set(dev, ctl_regs[i][1], 0x4);
 263                 b43_phy_set(dev, ctl_regs[i][0], 0x4);
 264                 b43_phy_mask(dev, ctl_regs[i][1], ~0x1);
 265                 b43_phy_set(dev, ctl_regs[i][0], 0x1);
 266                 b43_httab_write(dev, B43_HTTAB16(8, 5 + (i * 0x10)), 0);
 267                 b43_phy_mask(dev, ctl_regs[i][0], ~0x4);
 268         }
 269 }
 270
 271 static void b43_phy_ht_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 272 {
 273         clip_st[0] = b43_phy_read(dev, B43_PHY_HT_C1_CLIP1THRES);
 274         clip_st[1] = b43_phy_read(dev, B43_PHY_HT_C2_CLIP1THRES);
 275         clip_st[2] = b43_phy_read(dev, B43_PHY_HT_C3_CLIP1THRES);
 276 }
 277
 278 static void b43_phy_ht_bphy_init(struct b43_wldev *dev)
 279 {
 280         unsigned int i;
 281         u16 val;
 282
 283         val = 0x1E1F;
 284         for (i = 0; i < 16; i++) {
 285                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
 286                 val -= 0x202;
 287         }
 288         val = 0x3E3F;
 289         for (i = 0; i < 16; i++) {
 290                 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
 291                 val -= 0x202;
 292         }
 293         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
 294 }
 295
 296 /**************************************************
 297  * Samples
 298  **************************************************/
 299
 300 #if 0
 301 static void b43_phy_ht_stop_playback(struct b43_wldev *dev)
 302 {
 303         struct b43_phy_ht *phy_ht = dev->phy.ht;
 304         u16 tmp;
 305         int i;
 306
 307         tmp = b43_phy_read(dev, B43_PHY_HT_SAMP_STAT);
 308         if (tmp & 0x1)
 309                 b43_phy_set(dev, B43_PHY_HT_SAMP_CMD, B43_PHY_HT_SAMP_CMD_STOP);
 310         else if (tmp & 0x2)
 311                 b43_phy_mask(dev, B43_PHY_HT_IQLOCAL_CMDGCTL, 0x7FFF);
 312
 313         b43_phy_mask(dev, B43_PHY_HT_SAMP_CMD, ~0x0004);
 314
 315         for (i = 0; i < 3; i++) {
 316                 if (phy_ht->bb_mult_save[i] >= 0) {
 317                         b43_httab_write(dev, B43_HTTAB16(13, 0x63 + i * 4),
 318                                         phy_ht->bb_mult_save[i]);
 319                         b43_httab_write(dev, B43_HTTAB16(13, 0x67 + i * 4),
 320                                         phy_ht->bb_mult_save[i]);
 321                 }
 322         }
 323 }
 324
 325 static u16 b43_phy_ht_load_samples(struct b43_wldev *dev)
 326 {
 327         int i;
 328         u16 len = 20 << 3;
 329
 330         b43_phy_write(dev, B43_PHY_HT_TABLE_ADDR, 0x4400);
 331
 332         for (i = 0; i < len; i++) {
 333                 b43_phy_write(dev, B43_PHY_HT_TABLE_DATAHI, 0);
 334                 b43_phy_write(dev, B43_PHY_HT_TABLE_DATALO, 0);
 335         }
 336
 337         return len;
 338 }
 339
 340 static void b43_phy_ht_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
 341                                    u16 wait)
 342 {
 343         struct b43_phy_ht *phy_ht = dev->phy.ht;
 344         u16 save_seq_mode;
 345         int i;
 346
 347         for (i = 0; i < 3; i++) {
 348                 if (phy_ht->bb_mult_save[i] < 0)
 349                         phy_ht->bb_mult_save[i] = b43_httab_read(dev, B43_HTTAB16(13, 0x63 + i * 4));
 350         }
 351
 352         b43_phy_write(dev, B43_PHY_HT_SAMP_DEP_CNT, samps - 1);
 353         if (loops != 0xFFFF)
 354                 loops--;
 355         b43_phy_write(dev, B43_PHY_HT_SAMP_LOOP_CNT, loops);
 356         b43_phy_write(dev, B43_PHY_HT_SAMP_WAIT_CNT, wait);
 357
 358         save_seq_mode = b43_phy_read(dev, B43_PHY_HT_RF_SEQ_MODE);
 359         b43_phy_set(dev, B43_PHY_HT_RF_SEQ_MODE,
 360                     B43_PHY_HT_RF_SEQ_MODE_CA_OVER);
 361
 362         /* TODO: find out mask bits! Do we need more function arguments? */
 363         b43_phy_mask(dev, B43_PHY_HT_SAMP_CMD, ~0);
 364         b43_phy_mask(dev, B43_PHY_HT_SAMP_CMD, ~0);
 365         b43_phy_mask(dev, B43_PHY_HT_IQLOCAL_CMDGCTL, ~0);
 366         b43_phy_set(dev, B43_PHY_HT_SAMP_CMD, 0x1);
 367
 368         for (i = 0; i < 100; i++) {
 369                 if (!(b43_phy_read(dev, B43_PHY_HT_RF_SEQ_STATUS) & 1)) {
 370                         i = 0;
 371                         break;
 372                 }
 373                 udelay(10);
 374         }
 375         if (i)
 376                 b43err(dev->wl, "run samples timeout\n");
 377
 378         b43_phy_write(dev, B43_PHY_HT_RF_SEQ_MODE, save_seq_mode);
 379 }
 380
 381 static void b43_phy_ht_tx_tone(struct b43_wldev *dev)
 382 {
 383         u16 samp;
 384
 385         samp = b43_phy_ht_load_samples(dev);
 386         b43_phy_ht_run_samples(dev, samp, 0xFFFF, 0);
 387 }
 388 #endif
 389
 390 /**************************************************
 391  * RSSI
 392  **************************************************/
 393
 394 #if 0
 395 static void b43_phy_ht_rssi_select(struct b43_wldev *dev, u8 core_sel,
 396                                    u8 rssi_type)
 397 {
 398         static const u16 ctl_regs[3][2] = {
 399                 { B43_PHY_HT_AFE_C1, B43_PHY_HT_AFE_C1_OVER, },
 400                 { B43_PHY_HT_AFE_C2, B43_PHY_HT_AFE_C2_OVER, },
 401                 { B43_PHY_HT_AFE_C3, B43_PHY_HT_AFE_C3_OVER, },
 402         };
 403         static const u16 radio_r[] = { R2059_SYN, R2059_TXRX0, R2059_RXRX1, };
 404         int core;
 405
 406         if (core_sel == 0) {
 407                 b43err(dev->wl, "RSSI selection for core off not implemented yet\n");
 408         } else {
 409                 for (core = 0; core < 3; core++) {
 410                         /* Check if caller requested a one specific core */
 411                         if ((core_sel == 1 && core != 0) ||
 412                             (core_sel == 2 && core != 1) ||
 413                             (core_sel == 3 && core != 2))
 414                                 continue;
 415
 416                         switch (rssi_type) {
 417                         case 4:
 418                                 b43_phy_set(dev, ctl_regs[core][0], 0x3 << 8);
 419                                 b43_phy_set(dev, ctl_regs[core][0], 0x3 << 10);
 420                                 b43_phy_set(dev, ctl_regs[core][1], 0x1 << 9);
 421                                 b43_phy_set(dev, ctl_regs[core][1], 0x1 << 10);
 422
 423                                 b43_radio_set(dev, R2059_RXRX1 | 0xbf, 0x1);
 424                                 b43_radio_write(dev, radio_r[core] | 0x159,
 425                                                 0x11);
 426                                 break;
 427                         default:
 428                                 b43err(dev->wl, "RSSI selection for type %d not implemented yet\n",
 429                                        rssi_type);
 430                         }
 431                 }
 432         }
 433 }
 434
 435 static void b43_phy_ht_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
 436                                  u8 nsamp)
 437 {
 438         u16 phy_regs_values[12];
 439         static const u16 phy_regs_to_save[] = {
 440                 B43_PHY_HT_AFE_C1, B43_PHY_HT_AFE_C1_OVER,
 441                 0x848, 0x841,
 442                 B43_PHY_HT_AFE_C2, B43_PHY_HT_AFE_C2_OVER,
 443                 0x868, 0x861,
 444                 B43_PHY_HT_AFE_C3, B43_PHY_HT_AFE_C3_OVER,
 445                 0x888, 0x881,
 446         };
 447         u16 tmp[3];
 448         int i;
 449
 450         for (i = 0; i < 12; i++)
 451                 phy_regs_values[i] = b43_phy_read(dev, phy_regs_to_save[i]);
 452
 453         b43_phy_ht_rssi_select(dev, 5, type);
 454
 455         for (i = 0; i < 6; i++)
 456                 buf[i] = 0;
 457
 458         for (i = 0; i < nsamp; i++) {
 459                 tmp[0] = b43_phy_read(dev, B43_PHY_HT_RSSI_C1);
 460                 tmp[1] = b43_phy_read(dev, B43_PHY_HT_RSSI_C2);
 461                 tmp[2] = b43_phy_read(dev, B43_PHY_HT_RSSI_C3);
 462
 463                 buf[0] += ((s8)((tmp[0] & 0x3F) << 2)) >> 2;
 464                 buf[1] += ((s8)(((tmp[0] >> 8) & 0x3F) << 2)) >> 2;
 465                 buf[2] += ((s8)((tmp[1] & 0x3F) << 2)) >> 2;
 466                 buf[3] += ((s8)(((tmp[1] >> 8) & 0x3F) << 2)) >> 2;
 467                 buf[4] += ((s8)((tmp[2] & 0x3F) << 2)) >> 2;
 468                 buf[5] += ((s8)(((tmp[2] >> 8) & 0x3F) << 2)) >> 2;
 469         }
 470
 471         for (i = 0; i < 12; i++)
 472                 b43_phy_write(dev, phy_regs_to_save[i], phy_regs_values[i]);
 473 }
 474 #endif
 475
 476 /**************************************************
 477  * Tx/Rx
 478  **************************************************/
 479
 480 static void b43_phy_ht_tx_power_fix(struct b43_wldev *dev)
 481 {
 482         int i;
 483
 484         for (i = 0; i < 3; i++) {
 485                 u16 mask;
 486                 u32 tmp = b43_httab_read(dev, B43_HTTAB32(26, 0xE8));
 487
 488                 if (0) /* FIXME */
 489                         mask = 0x2 << (i * 4);
 490                 else
 491                         mask = 0;
 492                 b43_phy_mask(dev, B43_PHY_EXTG(0x108), mask);
 493
 494                 b43_httab_write(dev, B43_HTTAB16(7, 0x110 + i), tmp >> 16);
 495                 b43_httab_write(dev, B43_HTTAB8(13, 0x63 + (i * 4)),
 496                                 tmp & 0xFF);
 497                 b43_httab_write(dev, B43_HTTAB8(13, 0x73 + (i * 4)),
 498                                 tmp & 0xFF);
 499         }
 500 }
 501
 502 #if 0
 503 static void b43_phy_ht_tx_power_ctl(struct b43_wldev *dev, bool enable)
 504 {
 505         struct b43_phy_ht *phy_ht = dev->phy.ht;
 506         u16 en_bits = B43_PHY_HT_TXPCTL_CMD_C1_COEFF |
 507                       B43_PHY_HT_TXPCTL_CMD_C1_HWPCTLEN |
 508                       B43_PHY_HT_TXPCTL_CMD_C1_PCTLEN;
 509         static const u16 cmd_regs[3] = { B43_PHY_HT_TXPCTL_CMD_C1,
 510                                          B43_PHY_HT_TXPCTL_CMD_C2,
 511                                          B43_PHY_HT_TXPCTL_CMD_C3 };
 512         int i;
 513
 514         if (!enable) {
 515                 if (b43_phy_read(dev, B43_PHY_HT_TXPCTL_CMD_C1) & en_bits) {
 516                         /* We disable enabled TX pwr ctl, save it's state */
 517                         /*
 518                          * TODO: find the registers. On N-PHY they were 0x1ed
 519                          * and 0x1ee, we need 3 such a registers for HT-PHY
 520                          */
 521                 }
 522                 b43_phy_mask(dev, B43_PHY_HT_TXPCTL_CMD_C1, ~en_bits);
 523         } else {
 524                 b43_phy_set(dev, B43_PHY_HT_TXPCTL_CMD_C1, en_bits);
 525
 526                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
 527                         for (i = 0; i < 3; i++)
 528                                 b43_phy_write(dev, cmd_regs[i], 0x32);
 529                 }
 530
 531                 for (i = 0; i < 3; i++)
 532                         if (phy_ht->tx_pwr_idx[i] <=
 533                             B43_PHY_HT_TXPCTL_CMD_C1_INIT)
 534                                 b43_phy_write(dev, cmd_regs[i],
 535                                               phy_ht->tx_pwr_idx[i]);
 536         }
 537
 538         phy_ht->tx_pwr_ctl = enable;
 539 }
 540
 541 static void b43_phy_ht_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
 542 {
 543         struct b43_phy_ht *phy_ht = dev->phy.ht;
 544         s32 rssi_buf[6];
 545
 546         /* TODO */
 547
 548         b43_phy_ht_tx_tone(dev);
 549         udelay(20);
 550         b43_phy_ht_poll_rssi(dev, 4, rssi_buf, 1);
 551         b43_phy_ht_stop_playback(dev);
 552         b43_phy_ht_reset_cca(dev);
 553
 554         phy_ht->idle_tssi[0] = rssi_buf[0] & 0xff;
 555         phy_ht->idle_tssi[1] = rssi_buf[2] & 0xff;
 556         phy_ht->idle_tssi[2] = rssi_buf[4] & 0xff;
 557
 558         /* TODO */
 559 }
 560
 561 static void b43_phy_ht_tx_power_ctl_setup(struct b43_wldev *dev)
 562 {
 563         struct b43_phy_ht *phy_ht = dev->phy.ht;
 564         struct ssb_sprom *sprom = dev->dev->bus_sprom;
 565
 566         u8 *idle = phy_ht->idle_tssi;
 567         u8 target[3];
 568         s16 a1[3], b0[3], b1[3];
 569
 570         u16 freq = dev->phy.channel_freq;
 571         int i, c;
 572
 573         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 574                 for (c = 0; c < 3; c++) {
 575                         target[c] = sprom->core_pwr_info[c].maxpwr_2g;
 576                         a1[c] = sprom->core_pwr_info[c].pa_2g[0];
 577                         b0[c] = sprom->core_pwr_info[c].pa_2g[1];
 578                         b1[c] = sprom->core_pwr_info[c].pa_2g[2];
 579                 }
 580         } else if (freq >= 4900 && freq < 5100) {
 581                 for (c = 0; c < 3; c++) {
 582                         target[c] = sprom->core_pwr_info[c].maxpwr_5gl;
 583                         a1[c] = sprom->core_pwr_info[c].pa_5gl[0];
 584                         b0[c] = sprom->core_pwr_info[c].pa_5gl[1];
 585                         b1[c] = sprom->core_pwr_info[c].pa_5gl[2];
 586                 }
 587         } else if (freq >= 5100 && freq < 5500) {
 588                 for (c = 0; c < 3; c++) {
 589                         target[c] = sprom->core_pwr_info[c].maxpwr_5g;
 590                         a1[c] = sprom->core_pwr_info[c].pa_5g[0];
 591                         b0[c] = sprom->core_pwr_info[c].pa_5g[1];
 592                         b1[c] = sprom->core_pwr_info[c].pa_5g[2];
 593                 }
 594         } else if (freq >= 5500) {
 595                 for (c = 0; c < 3; c++) {
 596                         target[c] = sprom->core_pwr_info[c].maxpwr_5gh;
 597                         a1[c] = sprom->core_pwr_info[c].pa_5gh[0];
 598                         b0[c] = sprom->core_pwr_info[c].pa_5gh[1];
 599                         b1[c] = sprom->core_pwr_info[c].pa_5gh[2];
 600                 }
 601         } else {
 602                 target[0] = target[1] = target[2] = 52;
 603                 a1[0] = a1[1] = a1[2] = -424;
 604                 b0[0] = b0[1] = b0[2] = 5612;
 605                 b1[0] = b1[1] = b1[2] = -1393;
 606         }
 607
 608         b43_phy_set(dev, B43_PHY_HT_TSSIMODE, B43_PHY_HT_TSSIMODE_EN);
 609         b43_phy_mask(dev, B43_PHY_HT_TXPCTL_CMD_C1,
 610                      ~B43_PHY_HT_TXPCTL_CMD_C1_PCTLEN & 0xFFFF);
 611
 612         /* TODO: Does it depend on sprom->fem.ghz2.tssipos? */
 613         b43_phy_set(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI, 0x4000);
 614
 615         b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C1,
 616                         ~B43_PHY_HT_TXPCTL_CMD_C1_INIT, 0x19);
 617         b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C2,
 618                         ~B43_PHY_HT_TXPCTL_CMD_C2_INIT, 0x19);
 619         b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C3,
 620                         ~B43_PHY_HT_TXPCTL_CMD_C3_INIT, 0x19);
 621
 622         b43_phy_set(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI,
 623                     B43_PHY_HT_TXPCTL_IDLE_TSSI_BINF);
 624
 625         b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI,
 626                         ~B43_PHY_HT_TXPCTL_IDLE_TSSI_C1,
 627                         idle[0] << B43_PHY_HT_TXPCTL_IDLE_TSSI_C1_SHIFT);
 628         b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI,
 629                         ~B43_PHY_HT_TXPCTL_IDLE_TSSI_C2,
 630                         idle[1] << B43_PHY_HT_TXPCTL_IDLE_TSSI_C2_SHIFT);
 631         b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI2,
 632                         ~B43_PHY_HT_TXPCTL_IDLE_TSSI2_C3,
 633                         idle[2] << B43_PHY_HT_TXPCTL_IDLE_TSSI2_C3_SHIFT);
 634
 635         b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_N, ~B43_PHY_HT_TXPCTL_N_TSSID,
 636                         0xf0);
 637         b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_N, ~B43_PHY_HT_TXPCTL_N_NPTIL2,
 638                         0x3 << B43_PHY_HT_TXPCTL_N_NPTIL2_SHIFT);
 639 #if 0
 640         /* TODO: what to mask/set? */
 641         b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C1, 0x800, 0)
 642         b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C1, 0x400, 0)
 643 #endif
 644
 645         b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_TARG_PWR,
 646                         ~B43_PHY_HT_TXPCTL_TARG_PWR_C1,
 647                         target[0] << B43_PHY_HT_TXPCTL_TARG_PWR_C1_SHIFT);
 648         b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_TARG_PWR,
 649                         ~B43_PHY_HT_TXPCTL_TARG_PWR_C2 & 0xFFFF,
 650                         target[1] << B43_PHY_HT_TXPCTL_TARG_PWR_C2_SHIFT);
 651         b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_TARG_PWR2,
 652                         ~B43_PHY_HT_TXPCTL_TARG_PWR2_C3,
 653                         target[2] << B43_PHY_HT_TXPCTL_TARG_PWR2_C3_SHIFT);
 654
 655         for (c = 0; c < 3; c++) {
 656                 s32 num, den, pwr;
 657                 u32 regval[64];
 658
 659                 for (i = 0; i < 64; i++) {
 660                         num = 8 * (16 * b0[c] + b1[c] * i);
 661                         den = 32768 + a1[c] * i;
 662                         pwr = max((4 * num + den / 2) / den, -8);
 663                         regval[i] = pwr;
 664                 }
 665                 b43_httab_write_bulk(dev, B43_HTTAB16(26 + c, 0), 64, regval);
 666         }
 667 }
 668 #endif
 669
 670 /**************************************************
 671  * Channel switching ops.
 672  **************************************************/
 673
 674 static void b43_phy_ht_spur_avoid(struct b43_wldev *dev,
 675                                   struct ieee80211_channel *new_channel)
 676 {
 677         struct bcma_device *core = dev->dev->bdev;
 678         int spuravoid = 0;
 679         u16 tmp;
 680
 681         /* Check for 13 and 14 is just a guess, we don't have enough logs. */
 682         if (new_channel->hw_value == 13 || new_channel->hw_value == 14)
 683                 spuravoid = 1;
 684         bcma_core_pll_ctl(core, B43_BCMA_CLKCTLST_PHY_PLL_REQ, 0, false);
 685         bcma_pmu_spuravoid_pllupdate(&core->bus->drv_cc, spuravoid);
 686         bcma_core_pll_ctl(core,
 687                           B43_BCMA_CLKCTLST_80211_PLL_REQ |
 688                           B43_BCMA_CLKCTLST_PHY_PLL_REQ,
 689                           B43_BCMA_CLKCTLST_80211_PLL_ST |
 690                           B43_BCMA_CLKCTLST_PHY_PLL_ST, false);
 691
 692         /* Values has been taken from wlc_bmac_switch_macfreq comments */
 693         switch (spuravoid) {
 694         case 2: /* 126MHz */
 695                 tmp = 0x2082;
 696                 break;
 697         case 1: /* 123MHz */
 698                 tmp = 0x5341;
 699                 break;
 700         default: /* 120MHz */
 701                 tmp = 0x8889;
 702         }
 703
 704         b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, tmp);
 705         b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
 706
 707         /* TODO: reset PLL */
 708
 709         if (spuravoid)
 710                 b43_phy_set(dev, B43_PHY_HT_BBCFG, B43_PHY_HT_BBCFG_RSTRX);
 711         else
 712                 b43_phy_mask(dev, B43_PHY_HT_BBCFG,
 713                                 ~B43_PHY_HT_BBCFG_RSTRX & 0xFFFF);
 714
 715         b43_phy_ht_reset_cca(dev);
 716 }
 717
 718 static void b43_phy_ht_channel_setup(struct b43_wldev *dev,
 719                                 const struct b43_phy_ht_channeltab_e_phy *e,
 720                                 struct ieee80211_channel *new_channel)
 721 {
 722         bool old_band_5ghz;
 723
 724         old_band_5ghz = b43_phy_read(dev, B43_PHY_HT_BANDCTL) & 0; /* FIXME */
 725         if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
 726                 /* TODO */
 727         } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
 728                 /* TODO */
 729         }
 730
 731         b43_phy_write(dev, B43_PHY_HT_BW1, e->bw1);
 732         b43_phy_write(dev, B43_PHY_HT_BW2, e->bw2);
 733         b43_phy_write(dev, B43_PHY_HT_BW3, e->bw3);
 734         b43_phy_write(dev, B43_PHY_HT_BW4, e->bw4);
 735         b43_phy_write(dev, B43_PHY_HT_BW5, e->bw5);
 736         b43_phy_write(dev, B43_PHY_HT_BW6, e->bw6);
 737
 738         if (new_channel->hw_value == 14) {
 739                 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_OFDM_EN, 0);
 740                 b43_phy_set(dev, B43_PHY_HT_TEST, 0x0800);
 741         } else {
 742                 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_OFDM_EN,
 743                                       B43_PHY_HT_CLASS_CTL_OFDM_EN);
 744                 if (new_channel->band == IEEE80211_BAND_2GHZ)
 745                         b43_phy_mask(dev, B43_PHY_HT_TEST, ~0x840);
 746         }
 747
 748         if (1) /* TODO: On N it's for early devices only, what about HT? */
 749                 b43_phy_ht_tx_power_fix(dev);
 750
 751         b43_phy_ht_spur_avoid(dev, new_channel);
 752
 753         b43_phy_write(dev, 0x017e, 0x3830);
 754 }
 755
 756 static int b43_phy_ht_set_channel(struct b43_wldev *dev,
 757                                   struct ieee80211_channel *channel,
 758                                   enum nl80211_channel_type channel_type)
 759 {
 760         struct b43_phy *phy = &dev->phy;
 761
 762         const struct b43_phy_ht_channeltab_e_radio2059 *chent_r2059 = NULL;
 763
 764         if (phy->radio_ver == 0x2059) {
 765                 chent_r2059 = b43_phy_ht_get_channeltab_e_r2059(dev,
 766                                                         channel->center_freq);
 767                 if (!chent_r2059)
 768                         return -ESRCH;
 769         } else {
 770                 return -ESRCH;
 771         }
 772
 773         /* TODO: In case of N-PHY some bandwidth switching goes here */
 774
 775         if (phy->radio_ver == 0x2059) {
 776                 b43_radio_2059_channel_setup(dev, chent_r2059);
 777                 b43_phy_ht_channel_setup(dev, &(chent_r2059->phy_regs),
 778                                          channel);
 779         } else {
 780                 return -ESRCH;
 781         }
 782
 783         return 0;
 784 }
 785
 786 /**************************************************
 787  * Basic PHY ops.
 788  **************************************************/
 789
 790 static int b43_phy_ht_op_allocate(struct b43_wldev *dev)
 791 {
 792         struct b43_phy_ht *phy_ht;
 793
 794         phy_ht = kzalloc(sizeof(*phy_ht), GFP_KERNEL);
 795         if (!phy_ht)
 796                 return -ENOMEM;
 797         dev->phy.ht = phy_ht;
 798
 799         return 0;
 800 }
 801
 802 static void b43_phy_ht_op_prepare_structs(struct b43_wldev *dev)
 803 {
 804         struct b43_phy *phy = &dev->phy;
 805         struct b43_phy_ht *phy_ht = phy->ht;
 806         int i;
 807
 808         memset(phy_ht, 0, sizeof(*phy_ht));
 809
 810         phy_ht->tx_pwr_ctl = true;
 811         for (i = 0; i < 3; i++)
 812                 phy_ht->tx_pwr_idx[i] = B43_PHY_HT_TXPCTL_CMD_C1_INIT + 1;
 813
 814         for (i = 0; i < 3; i++)
 815                 phy_ht->bb_mult_save[i] = -1;
 816 }
 817
 818 static int b43_phy_ht_op_init(struct b43_wldev *dev)
 819 {
 820         struct b43_phy_ht *phy_ht = dev->phy.ht;
 821         u16 tmp;
 822         u16 clip_state[3];
 823         bool saved_tx_pwr_ctl;
 824
 825         if (dev->dev->bus_type != B43_BUS_BCMA) {
 826                 b43err(dev->wl, "HT-PHY is supported only on BCMA bus!\n");
 827                 return -EOPNOTSUPP;
 828         }
 829
 830         b43_phy_ht_tables_init(dev);
 831
 832         b43_phy_mask(dev, 0x0be, ~0x2);
 833         b43_phy_set(dev, 0x23f, 0x7ff);
 834         b43_phy_set(dev, 0x240, 0x7ff);
 835         b43_phy_set(dev, 0x241, 0x7ff);
 836
 837         b43_phy_ht_zero_extg(dev);
 838
 839         b43_phy_mask(dev, B43_PHY_EXTG(0), ~0x3);
 840
 841         b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0);
 842         b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0);
 843         b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0);
 844
 845         b43_phy_write(dev, B43_PHY_EXTG(0x103), 0x20);
 846         b43_phy_write(dev, B43_PHY_EXTG(0x101), 0x20);
 847         b43_phy_write(dev, 0x20d, 0xb8);
 848         b43_phy_write(dev, B43_PHY_EXTG(0x14f), 0xc8);
 849         b43_phy_write(dev, 0x70, 0x50);
 850         b43_phy_write(dev, 0x1ff, 0x30);
 851
 852         if (0) /* TODO: condition */
 853                 ; /* TODO: PHY op on reg 0x217 */
 854
 855         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
 856                 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_CCK_EN, 0);
 857         else
 858                 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_CCK_EN,
 859                                       B43_PHY_HT_CLASS_CTL_CCK_EN);
 860
 861         b43_phy_set(dev, 0xb1, 0x91);
 862         b43_phy_write(dev, 0x32f, 0x0003);
 863         b43_phy_write(dev, 0x077, 0x0010);
 864         b43_phy_write(dev, 0x0b4, 0x0258);
 865         b43_phy_mask(dev, 0x17e, ~0x4000);
 866
 867         b43_phy_write(dev, 0x0b9, 0x0072);
 868
 869         b43_httab_write_few(dev, B43_HTTAB16(7, 0x14e), 2, 0x010f, 0x010f);
 870         b43_httab_write_few(dev, B43_HTTAB16(7, 0x15e), 2, 0x010f, 0x010f);
 871         b43_httab_write_few(dev, B43_HTTAB16(7, 0x16e), 2, 0x010f, 0x010f);
 872
 873         b43_phy_ht_afe_unk1(dev);
 874
 875         b43_httab_write_few(dev, B43_HTTAB16(7, 0x130), 9, 0x777, 0x111, 0x111,
 876                             0x777, 0x111, 0x111, 0x777, 0x111, 0x111);
 877
 878         b43_httab_write(dev, B43_HTTAB16(7, 0x120), 0x0777);
 879         b43_httab_write(dev, B43_HTTAB16(7, 0x124), 0x0777);
 880
 881         b43_httab_write(dev, B43_HTTAB16(8, 0x00), 0x02);
 882         b43_httab_write(dev, B43_HTTAB16(8, 0x10), 0x02);
 883         b43_httab_write(dev, B43_HTTAB16(8, 0x20), 0x02);
 884
 885         b43_httab_write_few(dev, B43_HTTAB16(8, 0x08), 4,
 886                             0x8e, 0x96, 0x96, 0x96);
 887         b43_httab_write_few(dev, B43_HTTAB16(8, 0x18), 4,
 888                             0x8f, 0x9f, 0x9f, 0x9f);
 889         b43_httab_write_few(dev, B43_HTTAB16(8, 0x28), 4,
 890                             0x8f, 0x9f, 0x9f, 0x9f);
 891
 892         b43_httab_write_few(dev, B43_HTTAB16(8, 0x0c), 4, 0x2, 0x2, 0x2, 0x2);
 893         b43_httab_write_few(dev, B43_HTTAB16(8, 0x1c), 4, 0x2, 0x2, 0x2, 0x2);
 894         b43_httab_write_few(dev, B43_HTTAB16(8, 0x2c), 4, 0x2, 0x2, 0x2, 0x2);
 895
 896         b43_phy_maskset(dev, 0x0280, 0xff00, 0x3e);
 897         b43_phy_maskset(dev, 0x0283, 0xff00, 0x3e);
 898         b43_phy_maskset(dev, B43_PHY_OFDM(0x0141), 0xff00, 0x46);
 899         b43_phy_maskset(dev, 0x0283, 0xff00, 0x40);
 900
 901         b43_httab_write_few(dev, B43_HTTAB16(00, 0x8), 4,
 902                             0x09, 0x0e, 0x13, 0x18);
 903         b43_httab_write_few(dev, B43_HTTAB16(01, 0x8), 4,
 904                             0x09, 0x0e, 0x13, 0x18);
 905         /* TODO: Did wl mean 2 instead of 40? */
 906         b43_httab_write_few(dev, B43_HTTAB16(40, 0x8), 4,
 907                             0x09, 0x0e, 0x13, 0x18);
 908
 909         b43_phy_maskset(dev, B43_PHY_OFDM(0x24), 0x3f, 0xd);
 910         b43_phy_maskset(dev, B43_PHY_OFDM(0x64), 0x3f, 0xd);
 911         b43_phy_maskset(dev, B43_PHY_OFDM(0xa4), 0x3f, 0xd);
 912
 913         b43_phy_set(dev, B43_PHY_EXTG(0x060), 0x1);
 914         b43_phy_set(dev, B43_PHY_EXTG(0x064), 0x1);
 915         b43_phy_set(dev, B43_PHY_EXTG(0x080), 0x1);
 916         b43_phy_set(dev, B43_PHY_EXTG(0x084), 0x1);
 917
 918         /* Copy some tables entries */
 919         tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x144));
 920         b43_httab_write(dev, B43_HTTAB16(7, 0x14a), tmp);
 921         tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x154));
 922         b43_httab_write(dev, B43_HTTAB16(7, 0x15a), tmp);
 923         tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x164));
 924         b43_httab_write(dev, B43_HTTAB16(7, 0x16a), tmp);
 925
 926         /* Reset CCA */
 927         b43_phy_force_clock(dev, true);
 928         tmp = b43_phy_read(dev, B43_PHY_HT_BBCFG);
 929         b43_phy_write(dev, B43_PHY_HT_BBCFG, tmp | B43_PHY_HT_BBCFG_RSTCCA);
 930         b43_phy_write(dev, B43_PHY_HT_BBCFG, tmp & ~B43_PHY_HT_BBCFG_RSTCCA);
 931         b43_phy_force_clock(dev, false);
 932
 933         b43_mac_phy_clock_set(dev, true);
 934
 935         b43_phy_ht_pa_override(dev, false);
 936         b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RX2TX);
 937         b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RST2RX);
 938         b43_phy_ht_pa_override(dev, true);
 939
 940         /* TODO: Should we restore it? Or store it in global PHY info? */
 941         b43_phy_ht_classifier(dev, 0, 0);
 942         b43_phy_ht_read_clip_detection(dev, clip_state);
 943
 944         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 945                 b43_phy_ht_bphy_init(dev);
 946
 947         b43_httab_write_bulk(dev, B43_HTTAB32(0x1a, 0xc0),
 948                         B43_HTTAB_1A_C0_LATE_SIZE, b43_httab_0x1a_0xc0_late);
 949
 950         saved_tx_pwr_ctl = phy_ht->tx_pwr_ctl;
 951         b43_phy_ht_tx_power_fix(dev);
 952 #if 0
 953         b43_phy_ht_tx_power_ctl(dev, false);
 954         b43_phy_ht_tx_power_ctl_idle_tssi(dev);
 955         b43_phy_ht_tx_power_ctl_setup(dev);
 956         /* TODO */
 957         b43_phy_ht_tx_power_ctl(dev, saved_tx_pwr_ctl);
 958 #endif
 959
 960         return 0;
 961 }
 962
 963 static void b43_phy_ht_op_free(struct b43_wldev *dev)
 964 {
 965         struct b43_phy *phy = &dev->phy;
 966         struct b43_phy_ht *phy_ht = phy->ht;
 967
 968         kfree(phy_ht);
 969         phy->ht = NULL;
 970 }
 971
 972 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
 973 static void b43_phy_ht_op_software_rfkill(struct b43_wldev *dev,
 974                                         bool blocked)
 975 {
 976         if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
 977                 b43err(dev->wl, "MAC not suspended\n");
 978
 979         /* In the following PHY ops we copy wl's dummy behaviour.
 980          * TODO: Find out if reads (currently hidden in masks/masksets) are
 981          * needed and replace following ops with just writes or w&r.
 982          * Note: B43_PHY_HT_RF_CTL1 register is tricky, wrong operation can
 983          * cause delayed (!) machine lock up. */
 984         if (blocked) {
 985                 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
 986         } else {
 987                 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
 988                 b43_phy_maskset(dev, B43_PHY_HT_RF_CTL1, 0, 0x1);
 989                 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
 990                 b43_phy_maskset(dev, B43_PHY_HT_RF_CTL1, 0, 0x2);
 991
 992                 if (dev->phy.radio_ver == 0x2059)
 993                         b43_radio_2059_init(dev);
 994                 else
 995                         B43_WARN_ON(1);
 996
 997                 b43_switch_channel(dev, dev->phy.channel);
 998         }
 999 }
1000
1001 static void b43_phy_ht_op_switch_analog(struct b43_wldev *dev, bool on)
1002 {
1003         if (on) {
1004                 b43_phy_write(dev, B43_PHY_HT_AFE_C1, 0x00cd);
1005                 b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0x0000);
1006                 b43_phy_write(dev, B43_PHY_HT_AFE_C2, 0x00cd);
1007                 b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0x0000);
1008                 b43_phy_write(dev, B43_PHY_HT_AFE_C3, 0x00cd);
1009                 b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0x0000);
1010         } else {
1011                 b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0x07ff);
1012                 b43_phy_write(dev, B43_PHY_HT_AFE_C1, 0x00fd);
1013                 b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0x07ff);
1014                 b43_phy_write(dev, B43_PHY_HT_AFE_C2, 0x00fd);
1015                 b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0x07ff);
1016                 b43_phy_write(dev, B43_PHY_HT_AFE_C3, 0x00fd);
1017         }
1018 }
1019
1020 static int b43_phy_ht_op_switch_channel(struct b43_wldev *dev,
1021                                         unsigned int new_channel)
1022 {
1023         struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
1024         enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
1025
1026         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1027                 if ((new_channel < 1) || (new_channel > 14))
1028                         return -EINVAL;
1029         } else {
1030                 return -EINVAL;
1031         }
1032
1033         return b43_phy_ht_set_channel(dev, channel, channel_type);
1034 }
1035
1036 static unsigned int b43_phy_ht_op_get_default_chan(struct b43_wldev *dev)
1037 {
1038         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1039                 return 11;
1040         return 36;
1041 }
1042
1043 /**************************************************
1044  * R/W ops.
1045  **************************************************/
1046
1047 static u16 b43_phy_ht_op_read(struct b43_wldev *dev, u16 reg)
1048 {
1049         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1050         return b43_read16(dev, B43_MMIO_PHY_DATA);
1051 }
1052
1053 static void b43_phy_ht_op_write(struct b43_wldev *dev, u16 reg, u16 value)
1054 {
1055         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1056         b43_write16(dev, B43_MMIO_PHY_DATA, value);
1057 }
1058
1059 static void b43_phy_ht_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
1060                                  u16 set)
1061 {
1062         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1063         b43_write16(dev, B43_MMIO_PHY_DATA,
1064                     (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
1065 }
1066
1067 static u16 b43_phy_ht_op_radio_read(struct b43_wldev *dev, u16 reg)
1068 {
1069         /* HT-PHY needs 0x200 for read access */
1070         reg |= 0x200;
1071
1072         b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
1073         return b43_read16(dev, B43_MMIO_RADIO24_DATA);
1074 }
1075
1076 static void b43_phy_ht_op_radio_write(struct b43_wldev *dev, u16 reg,
1077                                       u16 value)
1078 {
1079         b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
1080         b43_write16(dev, B43_MMIO_RADIO24_DATA, value);
1081 }
1082
1083 static enum b43_txpwr_result
1084 b43_phy_ht_op_recalc_txpower(struct b43_wldev *dev, bool ignore_tssi)
1085 {
1086         return B43_TXPWR_RES_DONE;
1087 }
1088
1089 static void b43_phy_ht_op_adjust_txpower(struct b43_wldev *dev)
1090 {
1091 }
1092
1093 /**************************************************
1094  * PHY ops struct.
1095  **************************************************/
1096
1097 const struct b43_phy_operations b43_phyops_ht = {
1098         .allocate               = b43_phy_ht_op_allocate,
1099         .free                   = b43_phy_ht_op_free,
1100         .prepare_structs        = b43_phy_ht_op_prepare_structs,
1101         .init                   = b43_phy_ht_op_init,
1102         .phy_read               = b43_phy_ht_op_read,
1103         .phy_write              = b43_phy_ht_op_write,
1104         .phy_maskset            = b43_phy_ht_op_maskset,
1105         .radio_read             = b43_phy_ht_op_radio_read,
1106         .radio_write            = b43_phy_ht_op_radio_write,
1107         .software_rfkill        = b43_phy_ht_op_software_rfkill,
1108         .switch_analog          = b43_phy_ht_op_switch_analog,
1109         .switch_channel         = b43_phy_ht_op_switch_channel,
1110         .get_default_chan       = b43_phy_ht_op_get_default_chan,
1111         .recalc_txpower         = b43_phy_ht_op_recalc_txpower,
1112         .adjust_txpower         = b43_phy_ht_op_adjust_txpower,
1113 };