Pileus Git - ~andy/linux/blob - drivers/net/wireless/b43/phy_ht.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n HT-PHY support
   5
   6   Copyright (c) 2011 Rafał Miłecki <zajec5@gmail.com>
   7
   8   This program is free software; you can redistribute it and/or modify
   9   it under the terms of the GNU General Public License as published by
  10   the Free Software Foundation; either version 2 of the License, or
  11   (at your option) any later version.
  12
  13   This program is distributed in the hope that it will be useful,
  14   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16   GNU General Public License for more details.
  17
  18   You should have received a copy of the GNU General Public License
  19   along with this program; see the file COPYING.  If not, write to
  20   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  21   Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #include <linux/slab.h>
  26
  27 #include "b43.h"
  28 #include "phy_ht.h"
  29 #include "tables_phy_ht.h"
  30 #include "radio_2059.h"
  31 #include "main.h"
  32
  33 /**************************************************
  34  * Radio 2059.
  35  **************************************************/
  36
  37 static void b43_radio_2059_channel_setup(struct b43_wldev *dev,
  38                         const struct b43_phy_ht_channeltab_e_radio2059 *e)
  39 {
  40         u8 i;
  41         u16 routing;
  42
  43         b43_radio_write(dev, 0x16, e->radio_syn16);
  44         b43_radio_write(dev, 0x17, e->radio_syn17);
  45         b43_radio_write(dev, 0x22, e->radio_syn22);
  46         b43_radio_write(dev, 0x25, e->radio_syn25);
  47         b43_radio_write(dev, 0x27, e->radio_syn27);
  48         b43_radio_write(dev, 0x28, e->radio_syn28);
  49         b43_radio_write(dev, 0x29, e->radio_syn29);
  50         b43_radio_write(dev, 0x2c, e->radio_syn2c);
  51         b43_radio_write(dev, 0x2d, e->radio_syn2d);
  52         b43_radio_write(dev, 0x37, e->radio_syn37);
  53         b43_radio_write(dev, 0x41, e->radio_syn41);
  54         b43_radio_write(dev, 0x43, e->radio_syn43);
  55         b43_radio_write(dev, 0x47, e->radio_syn47);
  56         b43_radio_write(dev, 0x4a, e->radio_syn4a);
  57         b43_radio_write(dev, 0x58, e->radio_syn58);
  58         b43_radio_write(dev, 0x5a, e->radio_syn5a);
  59         b43_radio_write(dev, 0x6a, e->radio_syn6a);
  60         b43_radio_write(dev, 0x6d, e->radio_syn6d);
  61         b43_radio_write(dev, 0x6e, e->radio_syn6e);
  62         b43_radio_write(dev, 0x92, e->radio_syn92);
  63         b43_radio_write(dev, 0x98, e->radio_syn98);
  64
  65         for (i = 0; i < 2; i++) {
  66                 routing = i ? R2059_RXRX1 : R2059_TXRX0;
  67                 b43_radio_write(dev, routing | 0x4a, e->radio_rxtx4a);
  68                 b43_radio_write(dev, routing | 0x58, e->radio_rxtx58);
  69                 b43_radio_write(dev, routing | 0x5a, e->radio_rxtx5a);
  70                 b43_radio_write(dev, routing | 0x6a, e->radio_rxtx6a);
  71                 b43_radio_write(dev, routing | 0x6d, e->radio_rxtx6d);
  72                 b43_radio_write(dev, routing | 0x6e, e->radio_rxtx6e);
  73                 b43_radio_write(dev, routing | 0x92, e->radio_rxtx92);
  74                 b43_radio_write(dev, routing | 0x98, e->radio_rxtx98);
  75         }
  76
  77         udelay(50);
  78
  79         /* Calibration */
  80         b43_radio_mask(dev, 0x2b, ~0x1);
  81         b43_radio_mask(dev, 0x2e, ~0x4);
  82         b43_radio_set(dev, 0x2e, 0x4);
  83         b43_radio_set(dev, 0x2b, 0x1);
  84
  85         udelay(300);
  86 }
  87
  88 static void b43_radio_2059_init(struct b43_wldev *dev)
  89 {
  90         const u16 routing[] = { R2059_SYN, R2059_TXRX0, R2059_RXRX1 };
  91         const u16 radio_values[3][2] = {
  92                 { 0x61, 0xE9 }, { 0x69, 0xD5 }, { 0x73, 0x99 },
  93         };
  94         u16 i, j;
  95
  96         b43_radio_write(dev, R2059_ALL | 0x51, 0x0070);
  97         b43_radio_write(dev, R2059_ALL | 0x5a, 0x0003);
  98
  99         for (i = 0; i < ARRAY_SIZE(routing); i++)
 100                 b43_radio_set(dev, routing[i] | 0x146, 0x3);
 101
 102         b43_radio_set(dev, 0x2e, 0x0078);
 103         b43_radio_set(dev, 0xc0, 0x0080);
 104         msleep(2);
 105         b43_radio_mask(dev, 0x2e, ~0x0078);
 106         b43_radio_mask(dev, 0xc0, ~0x0080);
 107
 108         if (1) { /* FIXME */
 109                 b43_radio_set(dev, R2059_RXRX1 | 0x4, 0x1);
 110                 udelay(10);
 111                 b43_radio_set(dev, R2059_RXRX1 | 0x0BF, 0x1);
 112                 b43_radio_maskset(dev, R2059_RXRX1 | 0x19B, 0x3, 0x2);
 113
 114                 b43_radio_set(dev, R2059_RXRX1 | 0x4, 0x2);
 115                 udelay(100);
 116                 b43_radio_mask(dev, R2059_RXRX1 | 0x4, ~0x2);
 117
 118                 for (i = 0; i < 10000; i++) {
 119                         if (b43_radio_read(dev, R2059_RXRX1 | 0x145) & 1) {
 120                                 i = 0;
 121                                 break;
 122                         }
 123                         udelay(100);
 124                 }
 125                 if (i)
 126                         b43err(dev->wl, "radio 0x945 timeout\n");
 127
 128                 b43_radio_mask(dev, R2059_RXRX1 | 0x4, ~0x1);
 129                 b43_radio_set(dev, 0xa, 0x60);
 130
 131                 for (i = 0; i < 3; i++) {
 132                         b43_radio_write(dev, 0x17F, radio_values[i][0]);
 133                         b43_radio_write(dev, 0x13D, 0x6E);
 134                         b43_radio_write(dev, 0x13E, radio_values[i][1]);
 135                         b43_radio_write(dev, 0x13C, 0x55);
 136
 137                         for (j = 0; j < 10000; j++) {
 138                                 if (b43_radio_read(dev, 0x140) & 2) {
 139                                         j = 0;
 140                                         break;
 141                                 }
 142                                 udelay(500);
 143                         }
 144                         if (j)
 145                                 b43err(dev->wl, "radio 0x140 timeout\n");
 146
 147                         b43_radio_write(dev, 0x13C, 0x15);
 148                 }
 149
 150                 b43_radio_mask(dev, 0x17F, ~0x1);
 151         }
 152
 153         b43_radio_mask(dev, 0x11, ~0x0008);
 154 }
 155
 156 /**************************************************
 157  * Various PHY ops
 158  **************************************************/
 159
 160 static u16 b43_phy_ht_classifier(struct b43_wldev *dev, u16 mask, u16 val)
 161 {
 162         u16 tmp;
 163         u16 allowed = B43_PHY_HT_CLASS_CTL_CCK_EN |
 164                       B43_PHY_HT_CLASS_CTL_OFDM_EN |
 165                       B43_PHY_HT_CLASS_CTL_WAITED_EN;
 166
 167         tmp = b43_phy_read(dev, B43_PHY_HT_CLASS_CTL);
 168         tmp &= allowed;
 169         tmp &= ~mask;
 170         tmp |= (val & mask);
 171         b43_phy_maskset(dev, B43_PHY_HT_CLASS_CTL, ~allowed, tmp);
 172
 173         return tmp;
 174 }
 175
 176 static void b43_phy_ht_zero_extg(struct b43_wldev *dev)
 177 {
 178         u8 i, j;
 179         u16 base[] = { 0x40, 0x60, 0x80 };
 180
 181         for (i = 0; i < ARRAY_SIZE(base); i++) {
 182                 for (j = 0; j < 4; j++)
 183                         b43_phy_write(dev, B43_PHY_EXTG(base[i] + j), 0);
 184         }
 185
 186         for (i = 0; i < ARRAY_SIZE(base); i++)
 187                 b43_phy_write(dev, B43_PHY_EXTG(base[i] + 0xc), 0);
 188 }
 189
 190 /* Some unknown AFE (Analog Frondned) op */
 191 static void b43_phy_ht_afe_unk1(struct b43_wldev *dev)
 192 {
 193         u8 i;
 194
 195         static const u16 ctl_regs[3][2] = {
 196                 { B43_PHY_HT_AFE_C1_OVER, B43_PHY_HT_AFE_C1 },
 197                 { B43_PHY_HT_AFE_C2_OVER, B43_PHY_HT_AFE_C2 },
 198                 { B43_PHY_HT_AFE_C3_OVER, B43_PHY_HT_AFE_C3},
 199         };
 200
 201         for (i = 0; i < 3; i++) {
 202                 /* TODO: verify masks&sets */
 203                 b43_phy_set(dev, ctl_regs[i][1], 0x4);
 204                 b43_phy_set(dev, ctl_regs[i][0], 0x4);
 205                 b43_phy_mask(dev, ctl_regs[i][1], ~0x1);
 206                 b43_phy_set(dev, ctl_regs[i][0], 0x1);
 207                 b43_httab_write(dev, B43_HTTAB16(8, 5 + (i * 0x10)), 0);
 208                 b43_phy_mask(dev, ctl_regs[i][0], ~0x4);
 209         }
 210 }
 211
 212 static void b43_phy_ht_force_rf_sequence(struct b43_wldev *dev, u16 rf_seq)
 213 {
 214         u8 i;
 215
 216         u16 save_seq_mode = b43_phy_read(dev, B43_PHY_HT_RF_SEQ_MODE);
 217         b43_phy_set(dev, B43_PHY_HT_RF_SEQ_MODE, 0x3);
 218
 219         b43_phy_set(dev, B43_PHY_HT_RF_SEQ_TRIG, rf_seq);
 220         for (i = 0; i < 200; i++) {
 221                 if (!(b43_phy_read(dev, B43_PHY_HT_RF_SEQ_STATUS) & rf_seq)) {
 222                         i = 0;
 223                         break;
 224                 }
 225                 msleep(1);
 226         }
 227         if (i)
 228                 b43err(dev->wl, "Forcing RF sequence timeout\n");
 229
 230         b43_phy_write(dev, B43_PHY_HT_RF_SEQ_MODE, save_seq_mode);
 231 }
 232
 233 static void b43_phy_ht_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 234 {
 235         clip_st[0] = b43_phy_read(dev, B43_PHY_HT_C1_CLIP1THRES);
 236         clip_st[1] = b43_phy_read(dev, B43_PHY_HT_C2_CLIP1THRES);
 237         clip_st[2] = b43_phy_read(dev, B43_PHY_HT_C3_CLIP1THRES);
 238 }
 239
 240 static void b43_phy_ht_bphy_init(struct b43_wldev *dev)
 241 {
 242         unsigned int i;
 243         u16 val;
 244
 245         val = 0x1E1F;
 246         for (i = 0; i < 16; i++) {
 247                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
 248                 val -= 0x202;
 249         }
 250         val = 0x3E3F;
 251         for (i = 0; i < 16; i++) {
 252                 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
 253                 val -= 0x202;
 254         }
 255         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
 256 }
 257
 258 /**************************************************
 259  * Tx/Rx
 260  **************************************************/
 261
 262 static void b43_phy_ht_tx_power_fix(struct b43_wldev *dev)
 263 {
 264         int i;
 265
 266         for (i = 0; i < 3; i++) {
 267                 u16 mask;
 268                 u32 tmp = b43_httab_read(dev, B43_HTTAB32(26, 0xE8));
 269
 270                 if (0) /* FIXME */
 271                         mask = 0x2 << (i * 4);
 272                 else
 273                         mask = 0;
 274                 b43_phy_mask(dev, B43_PHY_EXTG(0x108), mask);
 275
 276                 b43_httab_write(dev, B43_HTTAB16(7, 0x110 + i), tmp >> 16);
 277                 b43_httab_write(dev, B43_HTTAB8(13, 0x63 + (i * 4)),
 278                                 tmp & 0xFF);
 279                 b43_httab_write(dev, B43_HTTAB8(13, 0x73 + (i * 4)),
 280                                 tmp & 0xFF);
 281         }
 282 }
 283
 284 /**************************************************
 285  * Channel switching ops.
 286  **************************************************/
 287
 288 static void b43_phy_ht_spur_avoid(struct b43_wldev *dev,
 289                                   struct ieee80211_channel *new_channel)
 290 {
 291         struct bcma_device *core = dev->dev->bdev;
 292         int spuravoid = 0;
 293
 294         /* Check for 13 and 14 is just a guess, we don't have enough logs. */
 295         if (new_channel->hw_value == 13 || new_channel->hw_value == 14)
 296                 spuravoid = 1;
 297         bcma_core_pll_ctl(core, B43_BCMA_CLKCTLST_PHY_PLL_REQ, 0, false);
 298         bcma_pmu_spuravoid_pllupdate(&core->bus->drv_cc, spuravoid);
 299         bcma_core_pll_ctl(core,
 300                           B43_BCMA_CLKCTLST_80211_PLL_REQ |
 301                           B43_BCMA_CLKCTLST_PHY_PLL_REQ,
 302                           B43_BCMA_CLKCTLST_80211_PLL_ST |
 303                           B43_BCMA_CLKCTLST_PHY_PLL_ST, false);
 304 }
 305
 306 static void b43_phy_ht_channel_setup(struct b43_wldev *dev,
 307                                 const struct b43_phy_ht_channeltab_e_phy *e,
 308                                 struct ieee80211_channel *new_channel)
 309 {
 310         bool old_band_5ghz;
 311
 312         old_band_5ghz = b43_phy_read(dev, B43_PHY_HT_BANDCTL) & 0; /* FIXME */
 313         if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
 314                 /* TODO */
 315         } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
 316                 /* TODO */
 317         }
 318
 319         b43_phy_write(dev, B43_PHY_HT_BW1, e->bw1);
 320         b43_phy_write(dev, B43_PHY_HT_BW2, e->bw2);
 321         b43_phy_write(dev, B43_PHY_HT_BW3, e->bw3);
 322         b43_phy_write(dev, B43_PHY_HT_BW4, e->bw4);
 323         b43_phy_write(dev, B43_PHY_HT_BW5, e->bw5);
 324         b43_phy_write(dev, B43_PHY_HT_BW6, e->bw6);
 325
 326         if (new_channel->hw_value == 14) {
 327                 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_OFDM_EN, 0);
 328                 b43_phy_set(dev, B43_PHY_HT_TEST, 0x0800);
 329         } else {
 330                 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_OFDM_EN,
 331                                       B43_PHY_HT_CLASS_CTL_OFDM_EN);
 332                 if (new_channel->band == IEEE80211_BAND_2GHZ)
 333                         b43_phy_mask(dev, B43_PHY_HT_TEST, ~0x840);
 334         }
 335
 336         if (1) /* TODO: On N it's for early devices only, what about HT? */
 337                 b43_phy_ht_tx_power_fix(dev);
 338
 339         b43_phy_ht_spur_avoid(dev, new_channel);
 340
 341         b43_phy_write(dev, 0x017e, 0x3830);
 342 }
 343
 344 static int b43_phy_ht_set_channel(struct b43_wldev *dev,
 345                                   struct ieee80211_channel *channel,
 346                                   enum nl80211_channel_type channel_type)
 347 {
 348         struct b43_phy *phy = &dev->phy;
 349
 350         const struct b43_phy_ht_channeltab_e_radio2059 *chent_r2059 = NULL;
 351
 352         if (phy->radio_ver == 0x2059) {
 353                 chent_r2059 = b43_phy_ht_get_channeltab_e_r2059(dev,
 354                                                         channel->center_freq);
 355                 if (!chent_r2059)
 356                         return -ESRCH;
 357         } else {
 358                 return -ESRCH;
 359         }
 360
 361         /* TODO: In case of N-PHY some bandwidth switching goes here */
 362
 363         if (phy->radio_ver == 0x2059) {
 364                 b43_radio_2059_channel_setup(dev, chent_r2059);
 365                 b43_phy_ht_channel_setup(dev, &(chent_r2059->phy_regs),
 366                                          channel);
 367         } else {
 368                 return -ESRCH;
 369         }
 370
 371         return 0;
 372 }
 373
 374 /**************************************************
 375  * Basic PHY ops.
 376  **************************************************/
 377
 378 static int b43_phy_ht_op_allocate(struct b43_wldev *dev)
 379 {
 380         struct b43_phy_ht *phy_ht;
 381
 382         phy_ht = kzalloc(sizeof(*phy_ht), GFP_KERNEL);
 383         if (!phy_ht)
 384                 return -ENOMEM;
 385         dev->phy.ht = phy_ht;
 386
 387         return 0;
 388 }
 389
 390 static void b43_phy_ht_op_prepare_structs(struct b43_wldev *dev)
 391 {
 392         struct b43_phy *phy = &dev->phy;
 393         struct b43_phy_ht *phy_ht = phy->ht;
 394
 395         memset(phy_ht, 0, sizeof(*phy_ht));
 396 }
 397
 398 static int b43_phy_ht_op_init(struct b43_wldev *dev)
 399 {
 400         u16 tmp;
 401         u16 clip_state[3];
 402
 403         if (dev->dev->bus_type != B43_BUS_BCMA) {
 404                 b43err(dev->wl, "HT-PHY is supported only on BCMA bus!\n");
 405                 return -EOPNOTSUPP;
 406         }
 407
 408         b43_phy_ht_tables_init(dev);
 409
 410         b43_phy_mask(dev, 0x0be, ~0x2);
 411         b43_phy_set(dev, 0x23f, 0x7ff);
 412         b43_phy_set(dev, 0x240, 0x7ff);
 413         b43_phy_set(dev, 0x241, 0x7ff);
 414
 415         b43_phy_ht_zero_extg(dev);
 416
 417         b43_phy_mask(dev, B43_PHY_EXTG(0), ~0x3);
 418
 419         b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0);
 420         b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0);
 421         b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0);
 422
 423         b43_phy_write(dev, B43_PHY_EXTG(0x103), 0x20);
 424         b43_phy_write(dev, B43_PHY_EXTG(0x101), 0x20);
 425         b43_phy_write(dev, 0x20d, 0xb8);
 426         b43_phy_write(dev, B43_PHY_EXTG(0x14f), 0xc8);
 427         b43_phy_write(dev, 0x70, 0x50);
 428         b43_phy_write(dev, 0x1ff, 0x30);
 429
 430         if (0) /* TODO: condition */
 431                 ; /* TODO: PHY op on reg 0x217 */
 432
 433         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
 434                 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_CCK_EN, 0);
 435         else
 436                 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_CCK_EN,
 437                                       B43_PHY_HT_CLASS_CTL_CCK_EN);
 438
 439         b43_phy_set(dev, 0xb1, 0x91);
 440         b43_phy_write(dev, 0x32f, 0x0003);
 441         b43_phy_write(dev, 0x077, 0x0010);
 442         b43_phy_write(dev, 0x0b4, 0x0258);
 443         b43_phy_mask(dev, 0x17e, ~0x4000);
 444
 445         b43_phy_write(dev, 0x0b9, 0x0072);
 446
 447         b43_httab_write_few(dev, B43_HTTAB16(7, 0x14e), 2, 0x010f, 0x010f);
 448         b43_httab_write_few(dev, B43_HTTAB16(7, 0x15e), 2, 0x010f, 0x010f);
 449         b43_httab_write_few(dev, B43_HTTAB16(7, 0x16e), 2, 0x010f, 0x010f);
 450
 451         b43_phy_ht_afe_unk1(dev);
 452
 453         b43_httab_write_few(dev, B43_HTTAB16(7, 0x130), 9, 0x777, 0x111, 0x111,
 454                             0x777, 0x111, 0x111, 0x777, 0x111, 0x111);
 455
 456         b43_httab_write(dev, B43_HTTAB16(7, 0x120), 0x0777);
 457         b43_httab_write(dev, B43_HTTAB16(7, 0x124), 0x0777);
 458
 459         b43_httab_write(dev, B43_HTTAB16(8, 0x00), 0x02);
 460         b43_httab_write(dev, B43_HTTAB16(8, 0x10), 0x02);
 461         b43_httab_write(dev, B43_HTTAB16(8, 0x20), 0x02);
 462
 463         b43_httab_write_few(dev, B43_HTTAB16(8, 0x08), 4,
 464                             0x8e, 0x96, 0x96, 0x96);
 465         b43_httab_write_few(dev, B43_HTTAB16(8, 0x18), 4,
 466                             0x8f, 0x9f, 0x9f, 0x9f);
 467         b43_httab_write_few(dev, B43_HTTAB16(8, 0x28), 4,
 468                             0x8f, 0x9f, 0x9f, 0x9f);
 469
 470         b43_httab_write_few(dev, B43_HTTAB16(8, 0x0c), 4, 0x2, 0x2, 0x2, 0x2);
 471         b43_httab_write_few(dev, B43_HTTAB16(8, 0x1c), 4, 0x2, 0x2, 0x2, 0x2);
 472         b43_httab_write_few(dev, B43_HTTAB16(8, 0x2c), 4, 0x2, 0x2, 0x2, 0x2);
 473
 474         b43_phy_maskset(dev, 0x0280, 0xff00, 0x3e);
 475         b43_phy_maskset(dev, 0x0283, 0xff00, 0x3e);
 476         b43_phy_maskset(dev, B43_PHY_OFDM(0x0141), 0xff00, 0x46);
 477         b43_phy_maskset(dev, 0x0283, 0xff00, 0x40);
 478
 479         b43_httab_write_few(dev, B43_HTTAB16(00, 0x8), 4,
 480                             0x09, 0x0e, 0x13, 0x18);
 481         b43_httab_write_few(dev, B43_HTTAB16(01, 0x8), 4,
 482                             0x09, 0x0e, 0x13, 0x18);
 483         /* TODO: Did wl mean 2 instead of 40? */
 484         b43_httab_write_few(dev, B43_HTTAB16(40, 0x8), 4,
 485                             0x09, 0x0e, 0x13, 0x18);
 486
 487         b43_phy_maskset(dev, B43_PHY_OFDM(0x24), 0x3f, 0xd);
 488         b43_phy_maskset(dev, B43_PHY_OFDM(0x64), 0x3f, 0xd);
 489         b43_phy_maskset(dev, B43_PHY_OFDM(0xa4), 0x3f, 0xd);
 490
 491         b43_phy_set(dev, B43_PHY_EXTG(0x060), 0x1);
 492         b43_phy_set(dev, B43_PHY_EXTG(0x064), 0x1);
 493         b43_phy_set(dev, B43_PHY_EXTG(0x080), 0x1);
 494         b43_phy_set(dev, B43_PHY_EXTG(0x084), 0x1);
 495
 496         /* Copy some tables entries */
 497         tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x144));
 498         b43_httab_write(dev, B43_HTTAB16(7, 0x14a), tmp);
 499         tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x154));
 500         b43_httab_write(dev, B43_HTTAB16(7, 0x15a), tmp);
 501         tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x164));
 502         b43_httab_write(dev, B43_HTTAB16(7, 0x16a), tmp);
 503
 504         /* Reset CCA */
 505         b43_phy_force_clock(dev, true);
 506         tmp = b43_phy_read(dev, B43_PHY_HT_BBCFG);
 507         b43_phy_write(dev, B43_PHY_HT_BBCFG, tmp | B43_PHY_HT_BBCFG_RSTCCA);
 508         b43_phy_write(dev, B43_PHY_HT_BBCFG, tmp & ~B43_PHY_HT_BBCFG_RSTCCA);
 509         b43_phy_force_clock(dev, false);
 510
 511         b43_mac_phy_clock_set(dev, true);
 512
 513         b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RX2TX);
 514         b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RST2RX);
 515
 516         /* TODO: Should we restore it? Or store it in global PHY info? */
 517         b43_phy_ht_classifier(dev, 0, 0);
 518         b43_phy_ht_read_clip_detection(dev, clip_state);
 519
 520         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 521                 b43_phy_ht_bphy_init(dev);
 522
 523         b43_httab_write_bulk(dev, B43_HTTAB32(0x1a, 0xc0),
 524                         B43_HTTAB_1A_C0_LATE_SIZE, b43_httab_0x1a_0xc0_late);
 525
 526         return 0;
 527 }
 528
 529 static void b43_phy_ht_op_free(struct b43_wldev *dev)
 530 {
 531         struct b43_phy *phy = &dev->phy;
 532         struct b43_phy_ht *phy_ht = phy->ht;
 533
 534         kfree(phy_ht);
 535         phy->ht = NULL;
 536 }
 537
 538 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
 539 static void b43_phy_ht_op_software_rfkill(struct b43_wldev *dev,
 540                                         bool blocked)
 541 {
 542         if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
 543                 b43err(dev->wl, "MAC not suspended\n");
 544
 545         /* In the following PHY ops we copy wl's dummy behaviour.
 546          * TODO: Find out if reads (currently hidden in masks/masksets) are
 547          * needed and replace following ops with just writes or w&r.
 548          * Note: B43_PHY_HT_RF_CTL1 register is tricky, wrong operation can
 549          * cause delayed (!) machine lock up. */
 550         if (blocked) {
 551                 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
 552         } else {
 553                 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
 554                 b43_phy_maskset(dev, B43_PHY_HT_RF_CTL1, 0, 0x1);
 555                 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
 556                 b43_phy_maskset(dev, B43_PHY_HT_RF_CTL1, 0, 0x2);
 557
 558                 if (dev->phy.radio_ver == 0x2059)
 559                         b43_radio_2059_init(dev);
 560                 else
 561                         B43_WARN_ON(1);
 562
 563                 b43_switch_channel(dev, dev->phy.channel);
 564         }
 565 }
 566
 567 static void b43_phy_ht_op_switch_analog(struct b43_wldev *dev, bool on)
 568 {
 569         if (on) {
 570                 b43_phy_write(dev, B43_PHY_HT_AFE_C1, 0x00cd);
 571                 b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0x0000);
 572                 b43_phy_write(dev, B43_PHY_HT_AFE_C2, 0x00cd);
 573                 b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0x0000);
 574                 b43_phy_write(dev, B43_PHY_HT_AFE_C3, 0x00cd);
 575                 b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0x0000);
 576         } else {
 577                 b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0x07ff);
 578                 b43_phy_write(dev, B43_PHY_HT_AFE_C1, 0x00fd);
 579                 b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0x07ff);
 580                 b43_phy_write(dev, B43_PHY_HT_AFE_C2, 0x00fd);
 581                 b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0x07ff);
 582                 b43_phy_write(dev, B43_PHY_HT_AFE_C3, 0x00fd);
 583         }
 584 }
 585
 586 static int b43_phy_ht_op_switch_channel(struct b43_wldev *dev,
 587                                         unsigned int new_channel)
 588 {
 589         struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
 590         enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
 591
 592         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 593                 if ((new_channel < 1) || (new_channel > 14))
 594                         return -EINVAL;
 595         } else {
 596                 return -EINVAL;
 597         }
 598
 599         return b43_phy_ht_set_channel(dev, channel, channel_type);
 600 }
 601
 602 static unsigned int b43_phy_ht_op_get_default_chan(struct b43_wldev *dev)
 603 {
 604         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 605                 return 11;
 606         return 36;
 607 }
 608
 609 /**************************************************
 610  * R/W ops.
 611  **************************************************/
 612
 613 static u16 b43_phy_ht_op_read(struct b43_wldev *dev, u16 reg)
 614 {
 615         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 616         return b43_read16(dev, B43_MMIO_PHY_DATA);
 617 }
 618
 619 static void b43_phy_ht_op_write(struct b43_wldev *dev, u16 reg, u16 value)
 620 {
 621         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 622         b43_write16(dev, B43_MMIO_PHY_DATA, value);
 623 }
 624
 625 static void b43_phy_ht_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
 626                                  u16 set)
 627 {
 628         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 629         b43_write16(dev, B43_MMIO_PHY_DATA,
 630                     (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
 631 }
 632
 633 static u16 b43_phy_ht_op_radio_read(struct b43_wldev *dev, u16 reg)
 634 {
 635         /* HT-PHY needs 0x200 for read access */
 636         reg |= 0x200;
 637
 638         b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
 639         return b43_read16(dev, B43_MMIO_RADIO24_DATA);
 640 }
 641
 642 static void b43_phy_ht_op_radio_write(struct b43_wldev *dev, u16 reg,
 643                                       u16 value)
 644 {
 645         b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
 646         b43_write16(dev, B43_MMIO_RADIO24_DATA, value);
 647 }
 648
 649 static enum b43_txpwr_result
 650 b43_phy_ht_op_recalc_txpower(struct b43_wldev *dev, bool ignore_tssi)
 651 {
 652         return B43_TXPWR_RES_DONE;
 653 }
 654
 655 static void b43_phy_ht_op_adjust_txpower(struct b43_wldev *dev)
 656 {
 657 }
 658
 659 /**************************************************
 660  * PHY ops struct.
 661  **************************************************/
 662
 663 const struct b43_phy_operations b43_phyops_ht = {
 664         .allocate               = b43_phy_ht_op_allocate,
 665         .free                   = b43_phy_ht_op_free,
 666         .prepare_structs        = b43_phy_ht_op_prepare_structs,
 667         .init                   = b43_phy_ht_op_init,
 668         .phy_read               = b43_phy_ht_op_read,
 669         .phy_write              = b43_phy_ht_op_write,
 670         .phy_maskset            = b43_phy_ht_op_maskset,
 671         .radio_read             = b43_phy_ht_op_radio_read,
 672         .radio_write            = b43_phy_ht_op_radio_write,
 673         .software_rfkill        = b43_phy_ht_op_software_rfkill,
 674         .switch_analog          = b43_phy_ht_op_switch_analog,
 675         .switch_channel         = b43_phy_ht_op_switch_channel,
 676         .get_default_chan       = b43_phy_ht_op_get_default_chan,
 677         .recalc_txpower         = b43_phy_ht_op_recalc_txpower,
 678         .adjust_txpower         = b43_phy_ht_op_adjust_txpower,
 679 };