3 Broadcom B43 wireless driver
4 IEEE 802.11n HT-PHY support
6 Copyright (c) 2011 Rafał Miłecki <zajec5@gmail.com>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21 Boston, MA 02110-1301, USA.
25 #include <linux/slab.h>
29 #include "tables_phy_ht.h"
30 #include "radio_2059.h"
33 /**************************************************
35 **************************************************/
37 static void b43_radio_2059_channel_setup(struct b43_wldev *dev,
38 const struct b43_phy_ht_channeltab_e_radio2059 *e)
40 static const u16 routing[] = { R2059_C1, R2059_C2, R2059_C3, };
44 b43_radio_write(dev, 0x16, e->radio_syn16);
45 b43_radio_write(dev, 0x17, e->radio_syn17);
46 b43_radio_write(dev, 0x22, e->radio_syn22);
47 b43_radio_write(dev, 0x25, e->radio_syn25);
48 b43_radio_write(dev, 0x27, e->radio_syn27);
49 b43_radio_write(dev, 0x28, e->radio_syn28);
50 b43_radio_write(dev, 0x29, e->radio_syn29);
51 b43_radio_write(dev, 0x2c, e->radio_syn2c);
52 b43_radio_write(dev, 0x2d, e->radio_syn2d);
53 b43_radio_write(dev, 0x37, e->radio_syn37);
54 b43_radio_write(dev, 0x41, e->radio_syn41);
55 b43_radio_write(dev, 0x43, e->radio_syn43);
56 b43_radio_write(dev, 0x47, e->radio_syn47);
58 for (core = 0; core < 3; core++) {
60 b43_radio_write(dev, r | 0x4a, e->radio_rxtx4a);
61 b43_radio_write(dev, r | 0x58, e->radio_rxtx58);
62 b43_radio_write(dev, r | 0x5a, e->radio_rxtx5a);
63 b43_radio_write(dev, r | 0x6a, e->radio_rxtx6a);
64 b43_radio_write(dev, r | 0x6d, e->radio_rxtx6d);
65 b43_radio_write(dev, r | 0x6e, e->radio_rxtx6e);
66 b43_radio_write(dev, r | 0x92, e->radio_rxtx92);
67 b43_radio_write(dev, r | 0x98, e->radio_rxtx98);
73 b43_radio_mask(dev, 0x2b, ~0x1);
74 b43_radio_mask(dev, 0x2e, ~0x4);
75 b43_radio_set(dev, 0x2e, 0x4);
76 b43_radio_set(dev, 0x2b, 0x1);
81 static void b43_radio_2059_init(struct b43_wldev *dev)
83 const u16 routing[] = { R2059_C1, R2059_C2, R2059_C3 };
84 const u16 radio_values[3][2] = {
85 { 0x61, 0xE9 }, { 0x69, 0xD5 }, { 0x73, 0x99 },
89 b43_radio_write(dev, R2059_ALL | 0x51, 0x0070);
90 b43_radio_write(dev, R2059_ALL | 0x5a, 0x0003);
92 for (i = 0; i < ARRAY_SIZE(routing); i++)
93 b43_radio_set(dev, routing[i] | 0x146, 0x3);
95 b43_radio_set(dev, 0x2e, 0x0078);
96 b43_radio_set(dev, 0xc0, 0x0080);
98 b43_radio_mask(dev, 0x2e, ~0x0078);
99 b43_radio_mask(dev, 0xc0, ~0x0080);
102 b43_radio_set(dev, R2059_C3 | 0x4, 0x1);
104 b43_radio_set(dev, R2059_C3 | 0x0BF, 0x1);
105 b43_radio_maskset(dev, R2059_C3 | 0x19B, 0x3, 0x2);
107 b43_radio_set(dev, R2059_C3 | 0x4, 0x2);
109 b43_radio_mask(dev, R2059_C3 | 0x4, ~0x2);
111 for (i = 0; i < 10000; i++) {
112 if (b43_radio_read(dev, R2059_C3 | 0x145) & 1) {
119 b43err(dev->wl, "radio 0x945 timeout\n");
121 b43_radio_mask(dev, R2059_C3 | 0x4, ~0x1);
122 b43_radio_set(dev, 0xa, 0x60);
124 for (i = 0; i < 3; i++) {
125 b43_radio_write(dev, 0x17F, radio_values[i][0]);
126 b43_radio_write(dev, 0x13D, 0x6E);
127 b43_radio_write(dev, 0x13E, radio_values[i][1]);
128 b43_radio_write(dev, 0x13C, 0x55);
130 for (j = 0; j < 10000; j++) {
131 if (b43_radio_read(dev, 0x140) & 2) {
138 b43err(dev->wl, "radio 0x140 timeout\n");
140 b43_radio_write(dev, 0x13C, 0x15);
143 b43_radio_mask(dev, 0x17F, ~0x1);
146 b43_radio_mask(dev, 0x11, ~0x0008);
149 /**************************************************
151 **************************************************/
153 static void b43_phy_ht_force_rf_sequence(struct b43_wldev *dev, u16 rf_seq)
157 u16 save_seq_mode = b43_phy_read(dev, B43_PHY_HT_RF_SEQ_MODE);
158 b43_phy_set(dev, B43_PHY_HT_RF_SEQ_MODE, 0x3);
160 b43_phy_set(dev, B43_PHY_HT_RF_SEQ_TRIG, rf_seq);
161 for (i = 0; i < 200; i++) {
162 if (!(b43_phy_read(dev, B43_PHY_HT_RF_SEQ_STATUS) & rf_seq)) {
169 b43err(dev->wl, "Forcing RF sequence timeout\n");
171 b43_phy_write(dev, B43_PHY_HT_RF_SEQ_MODE, save_seq_mode);
174 static void b43_phy_ht_pa_override(struct b43_wldev *dev, bool enable)
176 struct b43_phy_ht *htphy = dev->phy.ht;
177 static const u16 regs[3] = { B43_PHY_HT_RF_CTL_INT_C1,
178 B43_PHY_HT_RF_CTL_INT_C2,
179 B43_PHY_HT_RF_CTL_INT_C3 };
183 for (i = 0; i < 3; i++)
184 b43_phy_write(dev, regs[i], htphy->rf_ctl_int_save[i]);
186 for (i = 0; i < 3; i++)
187 htphy->rf_ctl_int_save[i] = b43_phy_read(dev, regs[i]);
188 /* TODO: Does 5GHz band use different value (not 0x0400)? */
189 for (i = 0; i < 3; i++)
190 b43_phy_write(dev, regs[i], 0x0400);
194 /**************************************************
196 **************************************************/
198 static u16 b43_phy_ht_classifier(struct b43_wldev *dev, u16 mask, u16 val)
201 u16 allowed = B43_PHY_HT_CLASS_CTL_CCK_EN |
202 B43_PHY_HT_CLASS_CTL_OFDM_EN |
203 B43_PHY_HT_CLASS_CTL_WAITED_EN;
205 tmp = b43_phy_read(dev, B43_PHY_HT_CLASS_CTL);
209 b43_phy_maskset(dev, B43_PHY_HT_CLASS_CTL, ~allowed, tmp);
214 static void b43_phy_ht_reset_cca(struct b43_wldev *dev)
218 b43_phy_force_clock(dev, true);
219 bbcfg = b43_phy_read(dev, B43_PHY_HT_BBCFG);
220 b43_phy_write(dev, B43_PHY_HT_BBCFG, bbcfg | B43_PHY_HT_BBCFG_RSTCCA);
222 b43_phy_write(dev, B43_PHY_HT_BBCFG, bbcfg & ~B43_PHY_HT_BBCFG_RSTCCA);
223 b43_phy_force_clock(dev, false);
225 b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RST2RX);
228 static void b43_phy_ht_zero_extg(struct b43_wldev *dev)
231 u16 base[] = { 0x40, 0x60, 0x80 };
233 for (i = 0; i < ARRAY_SIZE(base); i++) {
234 for (j = 0; j < 4; j++)
235 b43_phy_write(dev, B43_PHY_EXTG(base[i] + j), 0);
238 for (i = 0; i < ARRAY_SIZE(base); i++)
239 b43_phy_write(dev, B43_PHY_EXTG(base[i] + 0xc), 0);
242 /* Some unknown AFE (Analog Frondned) op */
243 static void b43_phy_ht_afe_unk1(struct b43_wldev *dev)
247 static const u16 ctl_regs[3][2] = {
248 { B43_PHY_HT_AFE_C1_OVER, B43_PHY_HT_AFE_C1 },
249 { B43_PHY_HT_AFE_C2_OVER, B43_PHY_HT_AFE_C2 },
250 { B43_PHY_HT_AFE_C3_OVER, B43_PHY_HT_AFE_C3},
253 for (i = 0; i < 3; i++) {
254 /* TODO: verify masks&sets */
255 b43_phy_set(dev, ctl_regs[i][1], 0x4);
256 b43_phy_set(dev, ctl_regs[i][0], 0x4);
257 b43_phy_mask(dev, ctl_regs[i][1], ~0x1);
258 b43_phy_set(dev, ctl_regs[i][0], 0x1);
259 b43_httab_write(dev, B43_HTTAB16(8, 5 + (i * 0x10)), 0);
260 b43_phy_mask(dev, ctl_regs[i][0], ~0x4);
264 static void b43_phy_ht_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
266 clip_st[0] = b43_phy_read(dev, B43_PHY_HT_C1_CLIP1THRES);
267 clip_st[1] = b43_phy_read(dev, B43_PHY_HT_C2_CLIP1THRES);
268 clip_st[2] = b43_phy_read(dev, B43_PHY_HT_C3_CLIP1THRES);
271 static void b43_phy_ht_bphy_init(struct b43_wldev *dev)
277 for (i = 0; i < 16; i++) {
278 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
282 for (i = 0; i < 16; i++) {
283 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
286 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
289 /**************************************************
291 **************************************************/
293 static void b43_phy_ht_stop_playback(struct b43_wldev *dev)
295 struct b43_phy_ht *phy_ht = dev->phy.ht;
299 tmp = b43_phy_read(dev, B43_PHY_HT_SAMP_STAT);
301 b43_phy_set(dev, B43_PHY_HT_SAMP_CMD, B43_PHY_HT_SAMP_CMD_STOP);
303 b43_phy_mask(dev, B43_PHY_HT_IQLOCAL_CMDGCTL, 0x7FFF);
305 b43_phy_mask(dev, B43_PHY_HT_SAMP_CMD, ~0x0004);
307 for (i = 0; i < 3; i++) {
308 if (phy_ht->bb_mult_save[i] >= 0) {
309 b43_httab_write(dev, B43_HTTAB16(13, 0x63 + i * 4),
310 phy_ht->bb_mult_save[i]);
311 b43_httab_write(dev, B43_HTTAB16(13, 0x67 + i * 4),
312 phy_ht->bb_mult_save[i]);
317 static u16 b43_phy_ht_load_samples(struct b43_wldev *dev)
322 b43_phy_write(dev, B43_PHY_HT_TABLE_ADDR, 0x4400);
324 for (i = 0; i < len; i++) {
325 b43_phy_write(dev, B43_PHY_HT_TABLE_DATAHI, 0);
326 b43_phy_write(dev, B43_PHY_HT_TABLE_DATALO, 0);
332 static void b43_phy_ht_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
335 struct b43_phy_ht *phy_ht = dev->phy.ht;
339 for (i = 0; i < 3; i++) {
340 if (phy_ht->bb_mult_save[i] < 0)
341 phy_ht->bb_mult_save[i] = b43_httab_read(dev, B43_HTTAB16(13, 0x63 + i * 4));
344 b43_phy_write(dev, B43_PHY_HT_SAMP_DEP_CNT, samps - 1);
347 b43_phy_write(dev, B43_PHY_HT_SAMP_LOOP_CNT, loops);
348 b43_phy_write(dev, B43_PHY_HT_SAMP_WAIT_CNT, wait);
350 save_seq_mode = b43_phy_read(dev, B43_PHY_HT_RF_SEQ_MODE);
351 b43_phy_set(dev, B43_PHY_HT_RF_SEQ_MODE,
352 B43_PHY_HT_RF_SEQ_MODE_CA_OVER);
354 /* TODO: find out mask bits! Do we need more function arguments? */
355 b43_phy_mask(dev, B43_PHY_HT_SAMP_CMD, ~0);
356 b43_phy_mask(dev, B43_PHY_HT_SAMP_CMD, ~0);
357 b43_phy_mask(dev, B43_PHY_HT_IQLOCAL_CMDGCTL, ~0);
358 b43_phy_set(dev, B43_PHY_HT_SAMP_CMD, 0x1);
360 for (i = 0; i < 100; i++) {
361 if (!(b43_phy_read(dev, B43_PHY_HT_RF_SEQ_STATUS) & 1)) {
368 b43err(dev->wl, "run samples timeout\n");
370 b43_phy_write(dev, B43_PHY_HT_RF_SEQ_MODE, save_seq_mode);
373 static void b43_phy_ht_tx_tone(struct b43_wldev *dev)
377 samp = b43_phy_ht_load_samples(dev);
378 b43_phy_ht_run_samples(dev, samp, 0xFFFF, 0);
381 /**************************************************
383 **************************************************/
385 static void b43_phy_ht_rssi_select(struct b43_wldev *dev, u8 core_sel,
388 static const u16 ctl_regs[3][2] = {
389 { B43_PHY_HT_AFE_C1, B43_PHY_HT_AFE_C1_OVER, },
390 { B43_PHY_HT_AFE_C2, B43_PHY_HT_AFE_C2_OVER, },
391 { B43_PHY_HT_AFE_C3, B43_PHY_HT_AFE_C3_OVER, },
393 static const u16 radio_r[] = { R2059_C1, R2059_C2, R2059_C3, };
397 b43err(dev->wl, "RSSI selection for core off not implemented yet\n");
399 for (core = 0; core < 3; core++) {
400 /* Check if caller requested a one specific core */
401 if ((core_sel == 1 && core != 0) ||
402 (core_sel == 2 && core != 1) ||
403 (core_sel == 3 && core != 2))
408 b43_phy_set(dev, ctl_regs[core][0], 0x3 << 8);
409 b43_phy_set(dev, ctl_regs[core][0], 0x3 << 10);
410 b43_phy_set(dev, ctl_regs[core][1], 0x1 << 9);
411 b43_phy_set(dev, ctl_regs[core][1], 0x1 << 10);
413 b43_radio_set(dev, R2059_C3 | 0xbf, 0x1);
414 b43_radio_write(dev, radio_r[core] | 0x159,
418 b43err(dev->wl, "RSSI selection for type %d not implemented yet\n",
425 static void b43_phy_ht_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
428 u16 phy_regs_values[12];
429 static const u16 phy_regs_to_save[] = {
430 B43_PHY_HT_AFE_C1, B43_PHY_HT_AFE_C1_OVER,
432 B43_PHY_HT_AFE_C2, B43_PHY_HT_AFE_C2_OVER,
434 B43_PHY_HT_AFE_C3, B43_PHY_HT_AFE_C3_OVER,
440 for (i = 0; i < 12; i++)
441 phy_regs_values[i] = b43_phy_read(dev, phy_regs_to_save[i]);
443 b43_phy_ht_rssi_select(dev, 5, type);
445 for (i = 0; i < 6; i++)
448 for (i = 0; i < nsamp; i++) {
449 tmp[0] = b43_phy_read(dev, B43_PHY_HT_RSSI_C1);
450 tmp[1] = b43_phy_read(dev, B43_PHY_HT_RSSI_C2);
451 tmp[2] = b43_phy_read(dev, B43_PHY_HT_RSSI_C3);
453 buf[0] += ((s8)((tmp[0] & 0x3F) << 2)) >> 2;
454 buf[1] += ((s8)(((tmp[0] >> 8) & 0x3F) << 2)) >> 2;
455 buf[2] += ((s8)((tmp[1] & 0x3F) << 2)) >> 2;
456 buf[3] += ((s8)(((tmp[1] >> 8) & 0x3F) << 2)) >> 2;
457 buf[4] += ((s8)((tmp[2] & 0x3F) << 2)) >> 2;
458 buf[5] += ((s8)(((tmp[2] >> 8) & 0x3F) << 2)) >> 2;
461 for (i = 0; i < 12; i++)
462 b43_phy_write(dev, phy_regs_to_save[i], phy_regs_values[i]);
465 /**************************************************
467 **************************************************/
469 static void b43_phy_ht_tx_power_fix(struct b43_wldev *dev)
473 for (i = 0; i < 3; i++) {
475 u32 tmp = b43_httab_read(dev, B43_HTTAB32(26, 0xE8));
478 mask = 0x2 << (i * 4);
481 b43_phy_mask(dev, B43_PHY_EXTG(0x108), mask);
483 b43_httab_write(dev, B43_HTTAB16(7, 0x110 + i), tmp >> 16);
484 b43_httab_write(dev, B43_HTTAB8(13, 0x63 + (i * 4)),
486 b43_httab_write(dev, B43_HTTAB8(13, 0x73 + (i * 4)),
491 static void b43_phy_ht_tx_power_ctl(struct b43_wldev *dev, bool enable)
493 struct b43_phy_ht *phy_ht = dev->phy.ht;
494 u16 en_bits = B43_PHY_HT_TXPCTL_CMD_C1_COEFF |
495 B43_PHY_HT_TXPCTL_CMD_C1_HWPCTLEN |
496 B43_PHY_HT_TXPCTL_CMD_C1_PCTLEN;
497 static const u16 cmd_regs[3] = { B43_PHY_HT_TXPCTL_CMD_C1,
498 B43_PHY_HT_TXPCTL_CMD_C2,
499 B43_PHY_HT_TXPCTL_CMD_C3 };
503 if (b43_phy_read(dev, B43_PHY_HT_TXPCTL_CMD_C1) & en_bits) {
504 /* We disable enabled TX pwr ctl, save it's state */
506 * TODO: find the registers. On N-PHY they were 0x1ed
507 * and 0x1ee, we need 3 such a registers for HT-PHY
510 b43_phy_mask(dev, B43_PHY_HT_TXPCTL_CMD_C1, ~en_bits);
512 b43_phy_set(dev, B43_PHY_HT_TXPCTL_CMD_C1, en_bits);
514 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
515 for (i = 0; i < 3; i++)
516 b43_phy_write(dev, cmd_regs[i], 0x32);
519 for (i = 0; i < 3; i++)
520 if (phy_ht->tx_pwr_idx[i] <=
521 B43_PHY_HT_TXPCTL_CMD_C1_INIT)
522 b43_phy_write(dev, cmd_regs[i],
523 phy_ht->tx_pwr_idx[i]);
526 phy_ht->tx_pwr_ctl = enable;
529 static void b43_phy_ht_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
531 struct b43_phy_ht *phy_ht = dev->phy.ht;
536 b43_phy_ht_tx_tone(dev);
538 b43_phy_ht_poll_rssi(dev, 4, rssi_buf, 1);
539 b43_phy_ht_stop_playback(dev);
540 b43_phy_ht_reset_cca(dev);
542 phy_ht->idle_tssi[0] = rssi_buf[0] & 0xff;
543 phy_ht->idle_tssi[1] = rssi_buf[2] & 0xff;
544 phy_ht->idle_tssi[2] = rssi_buf[4] & 0xff;
549 static void b43_phy_ht_tx_power_ctl_setup(struct b43_wldev *dev)
551 struct b43_phy_ht *phy_ht = dev->phy.ht;
552 struct ssb_sprom *sprom = dev->dev->bus_sprom;
554 u8 *idle = phy_ht->idle_tssi;
556 s16 a1[3], b0[3], b1[3];
558 u16 freq = dev->phy.channel_freq;
561 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
562 for (c = 0; c < 3; c++) {
563 target[c] = sprom->core_pwr_info[c].maxpwr_2g;
564 a1[c] = sprom->core_pwr_info[c].pa_2g[0];
565 b0[c] = sprom->core_pwr_info[c].pa_2g[1];
566 b1[c] = sprom->core_pwr_info[c].pa_2g[2];
568 } else if (freq >= 4900 && freq < 5100) {
569 for (c = 0; c < 3; c++) {
570 target[c] = sprom->core_pwr_info[c].maxpwr_5gl;
571 a1[c] = sprom->core_pwr_info[c].pa_5gl[0];
572 b0[c] = sprom->core_pwr_info[c].pa_5gl[1];
573 b1[c] = sprom->core_pwr_info[c].pa_5gl[2];
575 } else if (freq >= 5100 && freq < 5500) {
576 for (c = 0; c < 3; c++) {
577 target[c] = sprom->core_pwr_info[c].maxpwr_5g;
578 a1[c] = sprom->core_pwr_info[c].pa_5g[0];
579 b0[c] = sprom->core_pwr_info[c].pa_5g[1];
580 b1[c] = sprom->core_pwr_info[c].pa_5g[2];
582 } else if (freq >= 5500) {
583 for (c = 0; c < 3; c++) {
584 target[c] = sprom->core_pwr_info[c].maxpwr_5gh;
585 a1[c] = sprom->core_pwr_info[c].pa_5gh[0];
586 b0[c] = sprom->core_pwr_info[c].pa_5gh[1];
587 b1[c] = sprom->core_pwr_info[c].pa_5gh[2];
590 target[0] = target[1] = target[2] = 52;
591 a1[0] = a1[1] = a1[2] = -424;
592 b0[0] = b0[1] = b0[2] = 5612;
593 b1[0] = b1[1] = b1[2] = -1393;
596 b43_phy_set(dev, B43_PHY_HT_TSSIMODE, B43_PHY_HT_TSSIMODE_EN);
597 b43_phy_mask(dev, B43_PHY_HT_TXPCTL_CMD_C1,
598 ~B43_PHY_HT_TXPCTL_CMD_C1_PCTLEN & 0xFFFF);
600 /* TODO: Does it depend on sprom->fem.ghz2.tssipos? */
601 b43_phy_set(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI, 0x4000);
603 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C1,
604 ~B43_PHY_HT_TXPCTL_CMD_C1_INIT, 0x19);
605 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C2,
606 ~B43_PHY_HT_TXPCTL_CMD_C2_INIT, 0x19);
607 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C3,
608 ~B43_PHY_HT_TXPCTL_CMD_C3_INIT, 0x19);
610 b43_phy_set(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI,
611 B43_PHY_HT_TXPCTL_IDLE_TSSI_BINF);
613 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI,
614 ~B43_PHY_HT_TXPCTL_IDLE_TSSI_C1,
615 idle[0] << B43_PHY_HT_TXPCTL_IDLE_TSSI_C1_SHIFT);
616 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI,
617 ~B43_PHY_HT_TXPCTL_IDLE_TSSI_C2,
618 idle[1] << B43_PHY_HT_TXPCTL_IDLE_TSSI_C2_SHIFT);
619 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI2,
620 ~B43_PHY_HT_TXPCTL_IDLE_TSSI2_C3,
621 idle[2] << B43_PHY_HT_TXPCTL_IDLE_TSSI2_C3_SHIFT);
623 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_N, ~B43_PHY_HT_TXPCTL_N_TSSID,
625 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_N, ~B43_PHY_HT_TXPCTL_N_NPTIL2,
626 0x3 << B43_PHY_HT_TXPCTL_N_NPTIL2_SHIFT);
628 /* TODO: what to mask/set? */
629 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C1, 0x800, 0)
630 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C1, 0x400, 0)
633 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_TARG_PWR,
634 ~B43_PHY_HT_TXPCTL_TARG_PWR_C1,
635 target[0] << B43_PHY_HT_TXPCTL_TARG_PWR_C1_SHIFT);
636 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_TARG_PWR,
637 ~B43_PHY_HT_TXPCTL_TARG_PWR_C2 & 0xFFFF,
638 target[1] << B43_PHY_HT_TXPCTL_TARG_PWR_C2_SHIFT);
639 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_TARG_PWR2,
640 ~B43_PHY_HT_TXPCTL_TARG_PWR2_C3,
641 target[2] << B43_PHY_HT_TXPCTL_TARG_PWR2_C3_SHIFT);
643 for (c = 0; c < 3; c++) {
647 for (i = 0; i < 64; i++) {
648 num = 8 * (16 * b0[c] + b1[c] * i);
649 den = 32768 + a1[c] * i;
650 pwr = max((4 * num + den / 2) / den, -8);
653 b43_httab_write_bulk(dev, B43_HTTAB16(26 + c, 0), 64, regval);
657 /**************************************************
658 * Channel switching ops.
659 **************************************************/
661 static void b43_phy_ht_spur_avoid(struct b43_wldev *dev,
662 struct ieee80211_channel *new_channel)
664 struct bcma_device *core = dev->dev->bdev;
668 /* Check for 13 and 14 is just a guess, we don't have enough logs. */
669 if (new_channel->hw_value == 13 || new_channel->hw_value == 14)
671 bcma_core_pll_ctl(core, B43_BCMA_CLKCTLST_PHY_PLL_REQ, 0, false);
672 bcma_pmu_spuravoid_pllupdate(&core->bus->drv_cc, spuravoid);
673 bcma_core_pll_ctl(core,
674 B43_BCMA_CLKCTLST_80211_PLL_REQ |
675 B43_BCMA_CLKCTLST_PHY_PLL_REQ,
676 B43_BCMA_CLKCTLST_80211_PLL_ST |
677 B43_BCMA_CLKCTLST_PHY_PLL_ST, false);
679 /* Values has been taken from wlc_bmac_switch_macfreq comments */
687 default: /* 120MHz */
691 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, tmp);
692 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
694 /* TODO: reset PLL */
697 b43_phy_set(dev, B43_PHY_HT_BBCFG, B43_PHY_HT_BBCFG_RSTRX);
699 b43_phy_mask(dev, B43_PHY_HT_BBCFG,
700 ~B43_PHY_HT_BBCFG_RSTRX & 0xFFFF);
702 b43_phy_ht_reset_cca(dev);
705 static void b43_phy_ht_channel_setup(struct b43_wldev *dev,
706 const struct b43_phy_ht_channeltab_e_phy *e,
707 struct ieee80211_channel *new_channel)
711 old_band_5ghz = b43_phy_read(dev, B43_PHY_HT_BANDCTL) & 0; /* FIXME */
712 if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
714 } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
718 b43_phy_write(dev, B43_PHY_HT_BW1, e->bw1);
719 b43_phy_write(dev, B43_PHY_HT_BW2, e->bw2);
720 b43_phy_write(dev, B43_PHY_HT_BW3, e->bw3);
721 b43_phy_write(dev, B43_PHY_HT_BW4, e->bw4);
722 b43_phy_write(dev, B43_PHY_HT_BW5, e->bw5);
723 b43_phy_write(dev, B43_PHY_HT_BW6, e->bw6);
725 if (new_channel->hw_value == 14) {
726 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_OFDM_EN, 0);
727 b43_phy_set(dev, B43_PHY_HT_TEST, 0x0800);
729 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_OFDM_EN,
730 B43_PHY_HT_CLASS_CTL_OFDM_EN);
731 if (new_channel->band == IEEE80211_BAND_2GHZ)
732 b43_phy_mask(dev, B43_PHY_HT_TEST, ~0x840);
735 if (1) /* TODO: On N it's for early devices only, what about HT? */
736 b43_phy_ht_tx_power_fix(dev);
738 b43_phy_ht_spur_avoid(dev, new_channel);
740 b43_phy_write(dev, 0x017e, 0x3830);
743 static int b43_phy_ht_set_channel(struct b43_wldev *dev,
744 struct ieee80211_channel *channel,
745 enum nl80211_channel_type channel_type)
747 struct b43_phy *phy = &dev->phy;
749 const struct b43_phy_ht_channeltab_e_radio2059 *chent_r2059 = NULL;
751 if (phy->radio_ver == 0x2059) {
752 chent_r2059 = b43_phy_ht_get_channeltab_e_r2059(dev,
753 channel->center_freq);
760 /* TODO: In case of N-PHY some bandwidth switching goes here */
762 if (phy->radio_ver == 0x2059) {
763 b43_radio_2059_channel_setup(dev, chent_r2059);
764 b43_phy_ht_channel_setup(dev, &(chent_r2059->phy_regs),
773 /**************************************************
775 **************************************************/
777 static int b43_phy_ht_op_allocate(struct b43_wldev *dev)
779 struct b43_phy_ht *phy_ht;
781 phy_ht = kzalloc(sizeof(*phy_ht), GFP_KERNEL);
784 dev->phy.ht = phy_ht;
789 static void b43_phy_ht_op_prepare_structs(struct b43_wldev *dev)
791 struct b43_phy *phy = &dev->phy;
792 struct b43_phy_ht *phy_ht = phy->ht;
795 memset(phy_ht, 0, sizeof(*phy_ht));
797 phy_ht->tx_pwr_ctl = true;
798 for (i = 0; i < 3; i++)
799 phy_ht->tx_pwr_idx[i] = B43_PHY_HT_TXPCTL_CMD_C1_INIT + 1;
801 for (i = 0; i < 3; i++)
802 phy_ht->bb_mult_save[i] = -1;
805 static int b43_phy_ht_op_init(struct b43_wldev *dev)
807 struct b43_phy_ht *phy_ht = dev->phy.ht;
810 bool saved_tx_pwr_ctl;
812 if (dev->dev->bus_type != B43_BUS_BCMA) {
813 b43err(dev->wl, "HT-PHY is supported only on BCMA bus!\n");
817 b43_phy_ht_tables_init(dev);
819 b43_phy_mask(dev, 0x0be, ~0x2);
820 b43_phy_set(dev, 0x23f, 0x7ff);
821 b43_phy_set(dev, 0x240, 0x7ff);
822 b43_phy_set(dev, 0x241, 0x7ff);
824 b43_phy_ht_zero_extg(dev);
826 b43_phy_mask(dev, B43_PHY_EXTG(0), ~0x3);
828 b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0);
829 b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0);
830 b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0);
832 b43_phy_write(dev, B43_PHY_EXTG(0x103), 0x20);
833 b43_phy_write(dev, B43_PHY_EXTG(0x101), 0x20);
834 b43_phy_write(dev, 0x20d, 0xb8);
835 b43_phy_write(dev, B43_PHY_EXTG(0x14f), 0xc8);
836 b43_phy_write(dev, 0x70, 0x50);
837 b43_phy_write(dev, 0x1ff, 0x30);
839 if (0) /* TODO: condition */
840 ; /* TODO: PHY op on reg 0x217 */
842 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
843 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_CCK_EN, 0);
845 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_CCK_EN,
846 B43_PHY_HT_CLASS_CTL_CCK_EN);
848 b43_phy_set(dev, 0xb1, 0x91);
849 b43_phy_write(dev, 0x32f, 0x0003);
850 b43_phy_write(dev, 0x077, 0x0010);
851 b43_phy_write(dev, 0x0b4, 0x0258);
852 b43_phy_mask(dev, 0x17e, ~0x4000);
854 b43_phy_write(dev, 0x0b9, 0x0072);
856 b43_httab_write_few(dev, B43_HTTAB16(7, 0x14e), 2, 0x010f, 0x010f);
857 b43_httab_write_few(dev, B43_HTTAB16(7, 0x15e), 2, 0x010f, 0x010f);
858 b43_httab_write_few(dev, B43_HTTAB16(7, 0x16e), 2, 0x010f, 0x010f);
860 b43_phy_ht_afe_unk1(dev);
862 b43_httab_write_few(dev, B43_HTTAB16(7, 0x130), 9, 0x777, 0x111, 0x111,
863 0x777, 0x111, 0x111, 0x777, 0x111, 0x111);
865 b43_httab_write(dev, B43_HTTAB16(7, 0x120), 0x0777);
866 b43_httab_write(dev, B43_HTTAB16(7, 0x124), 0x0777);
868 b43_httab_write(dev, B43_HTTAB16(8, 0x00), 0x02);
869 b43_httab_write(dev, B43_HTTAB16(8, 0x10), 0x02);
870 b43_httab_write(dev, B43_HTTAB16(8, 0x20), 0x02);
872 b43_httab_write_few(dev, B43_HTTAB16(8, 0x08), 4,
873 0x8e, 0x96, 0x96, 0x96);
874 b43_httab_write_few(dev, B43_HTTAB16(8, 0x18), 4,
875 0x8f, 0x9f, 0x9f, 0x9f);
876 b43_httab_write_few(dev, B43_HTTAB16(8, 0x28), 4,
877 0x8f, 0x9f, 0x9f, 0x9f);
879 b43_httab_write_few(dev, B43_HTTAB16(8, 0x0c), 4, 0x2, 0x2, 0x2, 0x2);
880 b43_httab_write_few(dev, B43_HTTAB16(8, 0x1c), 4, 0x2, 0x2, 0x2, 0x2);
881 b43_httab_write_few(dev, B43_HTTAB16(8, 0x2c), 4, 0x2, 0x2, 0x2, 0x2);
883 b43_phy_maskset(dev, 0x0280, 0xff00, 0x3e);
884 b43_phy_maskset(dev, 0x0283, 0xff00, 0x3e);
885 b43_phy_maskset(dev, B43_PHY_OFDM(0x0141), 0xff00, 0x46);
886 b43_phy_maskset(dev, 0x0283, 0xff00, 0x40);
888 b43_httab_write_few(dev, B43_HTTAB16(00, 0x8), 4,
889 0x09, 0x0e, 0x13, 0x18);
890 b43_httab_write_few(dev, B43_HTTAB16(01, 0x8), 4,
891 0x09, 0x0e, 0x13, 0x18);
892 /* TODO: Did wl mean 2 instead of 40? */
893 b43_httab_write_few(dev, B43_HTTAB16(40, 0x8), 4,
894 0x09, 0x0e, 0x13, 0x18);
896 b43_phy_maskset(dev, B43_PHY_OFDM(0x24), 0x3f, 0xd);
897 b43_phy_maskset(dev, B43_PHY_OFDM(0x64), 0x3f, 0xd);
898 b43_phy_maskset(dev, B43_PHY_OFDM(0xa4), 0x3f, 0xd);
900 b43_phy_set(dev, B43_PHY_EXTG(0x060), 0x1);
901 b43_phy_set(dev, B43_PHY_EXTG(0x064), 0x1);
902 b43_phy_set(dev, B43_PHY_EXTG(0x080), 0x1);
903 b43_phy_set(dev, B43_PHY_EXTG(0x084), 0x1);
905 /* Copy some tables entries */
906 tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x144));
907 b43_httab_write(dev, B43_HTTAB16(7, 0x14a), tmp);
908 tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x154));
909 b43_httab_write(dev, B43_HTTAB16(7, 0x15a), tmp);
910 tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x164));
911 b43_httab_write(dev, B43_HTTAB16(7, 0x16a), tmp);
914 b43_phy_force_clock(dev, true);
915 tmp = b43_phy_read(dev, B43_PHY_HT_BBCFG);
916 b43_phy_write(dev, B43_PHY_HT_BBCFG, tmp | B43_PHY_HT_BBCFG_RSTCCA);
917 b43_phy_write(dev, B43_PHY_HT_BBCFG, tmp & ~B43_PHY_HT_BBCFG_RSTCCA);
918 b43_phy_force_clock(dev, false);
920 b43_mac_phy_clock_set(dev, true);
922 b43_phy_ht_pa_override(dev, false);
923 b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RX2TX);
924 b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RST2RX);
925 b43_phy_ht_pa_override(dev, true);
927 /* TODO: Should we restore it? Or store it in global PHY info? */
928 b43_phy_ht_classifier(dev, 0, 0);
929 b43_phy_ht_read_clip_detection(dev, clip_state);
931 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
932 b43_phy_ht_bphy_init(dev);
934 b43_httab_write_bulk(dev, B43_HTTAB32(0x1a, 0xc0),
935 B43_HTTAB_1A_C0_LATE_SIZE, b43_httab_0x1a_0xc0_late);
937 saved_tx_pwr_ctl = phy_ht->tx_pwr_ctl;
938 b43_phy_ht_tx_power_fix(dev);
939 b43_phy_ht_tx_power_ctl(dev, false);
940 b43_phy_ht_tx_power_ctl_idle_tssi(dev);
941 b43_phy_ht_tx_power_ctl_setup(dev);
942 b43_phy_ht_tx_power_ctl(dev, saved_tx_pwr_ctl);
947 static void b43_phy_ht_op_free(struct b43_wldev *dev)
949 struct b43_phy *phy = &dev->phy;
950 struct b43_phy_ht *phy_ht = phy->ht;
956 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
957 static void b43_phy_ht_op_software_rfkill(struct b43_wldev *dev,
960 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
961 b43err(dev->wl, "MAC not suspended\n");
963 /* In the following PHY ops we copy wl's dummy behaviour.
964 * TODO: Find out if reads (currently hidden in masks/masksets) are
965 * needed and replace following ops with just writes or w&r.
966 * Note: B43_PHY_HT_RF_CTL1 register is tricky, wrong operation can
967 * cause delayed (!) machine lock up. */
969 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
971 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
972 b43_phy_maskset(dev, B43_PHY_HT_RF_CTL1, 0, 0x1);
973 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
974 b43_phy_maskset(dev, B43_PHY_HT_RF_CTL1, 0, 0x2);
976 if (dev->phy.radio_ver == 0x2059)
977 b43_radio_2059_init(dev);
981 b43_switch_channel(dev, dev->phy.channel);
985 static void b43_phy_ht_op_switch_analog(struct b43_wldev *dev, bool on)
988 b43_phy_write(dev, B43_PHY_HT_AFE_C1, 0x00cd);
989 b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0x0000);
990 b43_phy_write(dev, B43_PHY_HT_AFE_C2, 0x00cd);
991 b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0x0000);
992 b43_phy_write(dev, B43_PHY_HT_AFE_C3, 0x00cd);
993 b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0x0000);
995 b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0x07ff);
996 b43_phy_write(dev, B43_PHY_HT_AFE_C1, 0x00fd);
997 b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0x07ff);
998 b43_phy_write(dev, B43_PHY_HT_AFE_C2, 0x00fd);
999 b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0x07ff);
1000 b43_phy_write(dev, B43_PHY_HT_AFE_C3, 0x00fd);
1004 static int b43_phy_ht_op_switch_channel(struct b43_wldev *dev,
1005 unsigned int new_channel)
1007 struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan;
1008 enum nl80211_channel_type channel_type =
1009 cfg80211_get_chandef_type(&dev->wl->hw->conf.chandef);
1011 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1012 if ((new_channel < 1) || (new_channel > 14))
1018 return b43_phy_ht_set_channel(dev, channel, channel_type);
1021 static unsigned int b43_phy_ht_op_get_default_chan(struct b43_wldev *dev)
1023 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1028 /**************************************************
1030 **************************************************/
1032 static u16 b43_phy_ht_op_read(struct b43_wldev *dev, u16 reg)
1034 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1035 return b43_read16(dev, B43_MMIO_PHY_DATA);
1038 static void b43_phy_ht_op_write(struct b43_wldev *dev, u16 reg, u16 value)
1040 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1041 b43_write16(dev, B43_MMIO_PHY_DATA, value);
1044 static void b43_phy_ht_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
1047 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1048 b43_write16(dev, B43_MMIO_PHY_DATA,
1049 (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
1052 static u16 b43_phy_ht_op_radio_read(struct b43_wldev *dev, u16 reg)
1054 /* HT-PHY needs 0x200 for read access */
1057 b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
1058 return b43_read16(dev, B43_MMIO_RADIO24_DATA);
1061 static void b43_phy_ht_op_radio_write(struct b43_wldev *dev, u16 reg,
1064 b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
1065 b43_write16(dev, B43_MMIO_RADIO24_DATA, value);
1068 static enum b43_txpwr_result
1069 b43_phy_ht_op_recalc_txpower(struct b43_wldev *dev, bool ignore_tssi)
1071 return B43_TXPWR_RES_DONE;
1074 static void b43_phy_ht_op_adjust_txpower(struct b43_wldev *dev)
1078 /**************************************************
1080 **************************************************/
1082 const struct b43_phy_operations b43_phyops_ht = {
1083 .allocate = b43_phy_ht_op_allocate,
1084 .free = b43_phy_ht_op_free,
1085 .prepare_structs = b43_phy_ht_op_prepare_structs,
1086 .init = b43_phy_ht_op_init,
1087 .phy_read = b43_phy_ht_op_read,
1088 .phy_write = b43_phy_ht_op_write,
1089 .phy_maskset = b43_phy_ht_op_maskset,
1090 .radio_read = b43_phy_ht_op_radio_read,
1091 .radio_write = b43_phy_ht_op_radio_write,
1092 .software_rfkill = b43_phy_ht_op_software_rfkill,
1093 .switch_analog = b43_phy_ht_op_switch_analog,
1094 .switch_channel = b43_phy_ht_op_switch_channel,
1095 .get_default_chan = b43_phy_ht_op_get_default_chan,
1096 .recalc_txpower = b43_phy_ht_op_recalc_txpower,
1097 .adjust_txpower = b43_phy_ht_op_adjust_txpower,