Pileus Git - ~andy/linux/blob - drivers/net/wireless/b43/phy_ht.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n HT-PHY support
   5
   6   Copyright (c) 2011 Rafał Miłecki <zajec5@gmail.com>
   7
   8   This program is free software; you can redistribute it and/or modify
   9   it under the terms of the GNU General Public License as published by
  10   the Free Software Foundation; either version 2 of the License, or
  11   (at your option) any later version.
  12
  13   This program is distributed in the hope that it will be useful,
  14   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16   GNU General Public License for more details.
  17
  18   You should have received a copy of the GNU General Public License
  19   along with this program; see the file COPYING.  If not, write to
  20   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  21   Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #include <linux/slab.h>
  26
  27 #include "b43.h"
  28 #include "phy_ht.h"
  29 #include "tables_phy_ht.h"
  30 #include "radio_2059.h"
  31 #include "main.h"
  32
  33 /**************************************************
  34  * Radio 2059.
  35  **************************************************/
  36
  37 static void b43_radio_2059_channel_setup(struct b43_wldev *dev,
  38                         const struct b43_phy_ht_channeltab_e_radio2059 *e)
  39 {
  40         u8 i;
  41         u16 routing;
  42
  43         b43_radio_write(dev, 0x16, e->radio_syn16);
  44         b43_radio_write(dev, 0x17, e->radio_syn17);
  45         b43_radio_write(dev, 0x22, e->radio_syn22);
  46         b43_radio_write(dev, 0x25, e->radio_syn25);
  47         b43_radio_write(dev, 0x27, e->radio_syn27);
  48         b43_radio_write(dev, 0x28, e->radio_syn28);
  49         b43_radio_write(dev, 0x29, e->radio_syn29);
  50         b43_radio_write(dev, 0x2c, e->radio_syn2c);
  51         b43_radio_write(dev, 0x2d, e->radio_syn2d);
  52         b43_radio_write(dev, 0x37, e->radio_syn37);
  53         b43_radio_write(dev, 0x41, e->radio_syn41);
  54         b43_radio_write(dev, 0x43, e->radio_syn43);
  55         b43_radio_write(dev, 0x47, e->radio_syn47);
  56         b43_radio_write(dev, 0x4a, e->radio_syn4a);
  57         b43_radio_write(dev, 0x58, e->radio_syn58);
  58         b43_radio_write(dev, 0x5a, e->radio_syn5a);
  59         b43_radio_write(dev, 0x6a, e->radio_syn6a);
  60         b43_radio_write(dev, 0x6d, e->radio_syn6d);
  61         b43_radio_write(dev, 0x6e, e->radio_syn6e);
  62         b43_radio_write(dev, 0x92, e->radio_syn92);
  63         b43_radio_write(dev, 0x98, e->radio_syn98);
  64
  65         for (i = 0; i < 2; i++) {
  66                 routing = i ? R2059_RXRX1 : R2059_TXRX0;
  67                 b43_radio_write(dev, routing | 0x4a, e->radio_rxtx4a);
  68                 b43_radio_write(dev, routing | 0x58, e->radio_rxtx58);
  69                 b43_radio_write(dev, routing | 0x5a, e->radio_rxtx5a);
  70                 b43_radio_write(dev, routing | 0x6a, e->radio_rxtx6a);
  71                 b43_radio_write(dev, routing | 0x6d, e->radio_rxtx6d);
  72                 b43_radio_write(dev, routing | 0x6e, e->radio_rxtx6e);
  73                 b43_radio_write(dev, routing | 0x92, e->radio_rxtx92);
  74                 b43_radio_write(dev, routing | 0x98, e->radio_rxtx98);
  75         }
  76
  77         udelay(50);
  78
  79         /* Calibration */
  80         b43_radio_mask(dev, 0x2b, ~0x1);
  81         b43_radio_mask(dev, 0x2e, ~0x4);
  82         b43_radio_set(dev, 0x2e, 0x4);
  83         b43_radio_set(dev, 0x2b, 0x1);
  84
  85         udelay(300);
  86 }
  87
  88 static void b43_radio_2059_init(struct b43_wldev *dev)
  89 {
  90         const u16 routing[] = { R2059_SYN, R2059_TXRX0, R2059_RXRX1 };
  91         const u16 radio_values[3][2] = {
  92                 { 0x61, 0xE9 }, { 0x69, 0xD5 }, { 0x73, 0x99 },
  93         };
  94         u16 i, j;
  95
  96         b43_radio_write(dev, R2059_ALL | 0x51, 0x0070);
  97         b43_radio_write(dev, R2059_ALL | 0x5a, 0x0003);
  98
  99         for (i = 0; i < ARRAY_SIZE(routing); i++)
 100                 b43_radio_set(dev, routing[i] | 0x146, 0x3);
 101
 102         b43_radio_set(dev, 0x2e, 0x0078);
 103         b43_radio_set(dev, 0xc0, 0x0080);
 104         msleep(2);
 105         b43_radio_mask(dev, 0x2e, ~0x0078);
 106         b43_radio_mask(dev, 0xc0, ~0x0080);
 107
 108         if (1) { /* FIXME */
 109                 b43_radio_set(dev, R2059_RXRX1 | 0x4, 0x1);
 110                 udelay(10);
 111                 b43_radio_set(dev, R2059_RXRX1 | 0x0BF, 0x1);
 112                 b43_radio_maskset(dev, R2059_RXRX1 | 0x19B, 0x3, 0x2);
 113
 114                 b43_radio_set(dev, R2059_RXRX1 | 0x4, 0x2);
 115                 udelay(100);
 116                 b43_radio_mask(dev, R2059_RXRX1 | 0x4, ~0x2);
 117
 118                 for (i = 0; i < 10000; i++) {
 119                         if (b43_radio_read(dev, R2059_RXRX1 | 0x145) & 1) {
 120                                 i = 0;
 121                                 break;
 122                         }
 123                         udelay(100);
 124                 }
 125                 if (i)
 126                         b43err(dev->wl, "radio 0x945 timeout\n");
 127
 128                 b43_radio_mask(dev, R2059_RXRX1 | 0x4, ~0x1);
 129                 b43_radio_set(dev, 0xa, 0x60);
 130
 131                 for (i = 0; i < 3; i++) {
 132                         b43_radio_write(dev, 0x17F, radio_values[i][0]);
 133                         b43_radio_write(dev, 0x13D, 0x6E);
 134                         b43_radio_write(dev, 0x13E, radio_values[i][1]);
 135                         b43_radio_write(dev, 0x13C, 0x55);
 136
 137                         for (j = 0; j < 10000; j++) {
 138                                 if (b43_radio_read(dev, 0x140) & 2) {
 139                                         j = 0;
 140                                         break;
 141                                 }
 142                                 udelay(500);
 143                         }
 144                         if (j)
 145                                 b43err(dev->wl, "radio 0x140 timeout\n");
 146
 147                         b43_radio_write(dev, 0x13C, 0x15);
 148                 }
 149
 150                 b43_radio_mask(dev, 0x17F, ~0x1);
 151         }
 152
 153         b43_radio_mask(dev, 0x11, ~0x0008);
 154 }
 155
 156 /**************************************************
 157  * RF
 158  **************************************************/
 159
 160 static void b43_phy_ht_force_rf_sequence(struct b43_wldev *dev, u16 rf_seq)
 161 {
 162         u8 i;
 163
 164         u16 save_seq_mode = b43_phy_read(dev, B43_PHY_HT_RF_SEQ_MODE);
 165         b43_phy_set(dev, B43_PHY_HT_RF_SEQ_MODE, 0x3);
 166
 167         b43_phy_set(dev, B43_PHY_HT_RF_SEQ_TRIG, rf_seq);
 168         for (i = 0; i < 200; i++) {
 169                 if (!(b43_phy_read(dev, B43_PHY_HT_RF_SEQ_STATUS) & rf_seq)) {
 170                         i = 0;
 171                         break;
 172                 }
 173                 msleep(1);
 174         }
 175         if (i)
 176                 b43err(dev->wl, "Forcing RF sequence timeout\n");
 177
 178         b43_phy_write(dev, B43_PHY_HT_RF_SEQ_MODE, save_seq_mode);
 179 }
 180
 181 static void b43_phy_ht_pa_override(struct b43_wldev *dev, bool enable)
 182 {
 183         struct b43_phy_ht *htphy = dev->phy.ht;
 184         static const u16 regs[3] = { B43_PHY_HT_RF_CTL_INT_C1,
 185                                      B43_PHY_HT_RF_CTL_INT_C2,
 186                                      B43_PHY_HT_RF_CTL_INT_C3 };
 187         int i;
 188
 189         if (enable) {
 190                 for (i = 0; i < 3; i++)
 191                         b43_phy_write(dev, regs[i], htphy->rf_ctl_int_save[i]);
 192         } else {
 193                 for (i = 0; i < 3; i++)
 194                         htphy->rf_ctl_int_save[i] = b43_phy_read(dev, regs[i]);
 195                 /* TODO: Does 5GHz band use different value (not 0x0400)? */
 196                 for (i = 0; i < 3; i++)
 197                         b43_phy_write(dev, regs[i], 0x0400);
 198         }
 199 }
 200
 201 /**************************************************
 202  * Various PHY ops
 203  **************************************************/
 204
 205 static u16 b43_phy_ht_classifier(struct b43_wldev *dev, u16 mask, u16 val)
 206 {
 207         u16 tmp;
 208         u16 allowed = B43_PHY_HT_CLASS_CTL_CCK_EN |
 209                       B43_PHY_HT_CLASS_CTL_OFDM_EN |
 210                       B43_PHY_HT_CLASS_CTL_WAITED_EN;
 211
 212         tmp = b43_phy_read(dev, B43_PHY_HT_CLASS_CTL);
 213         tmp &= allowed;
 214         tmp &= ~mask;
 215         tmp |= (val & mask);
 216         b43_phy_maskset(dev, B43_PHY_HT_CLASS_CTL, ~allowed, tmp);
 217
 218         return tmp;
 219 }
 220
 221 static void b43_phy_ht_reset_cca(struct b43_wldev *dev)
 222 {
 223         u16 bbcfg;
 224
 225         b43_phy_force_clock(dev, true);
 226         bbcfg = b43_phy_read(dev, B43_PHY_HT_BBCFG);
 227         b43_phy_write(dev, B43_PHY_HT_BBCFG, bbcfg | B43_PHY_HT_BBCFG_RSTCCA);
 228         udelay(1);
 229         b43_phy_write(dev, B43_PHY_HT_BBCFG, bbcfg & ~B43_PHY_HT_BBCFG_RSTCCA);
 230         b43_phy_force_clock(dev, false);
 231
 232         b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RST2RX);
 233 }
 234
 235 static void b43_phy_ht_zero_extg(struct b43_wldev *dev)
 236 {
 237         u8 i, j;
 238         u16 base[] = { 0x40, 0x60, 0x80 };
 239
 240         for (i = 0; i < ARRAY_SIZE(base); i++) {
 241                 for (j = 0; j < 4; j++)
 242                         b43_phy_write(dev, B43_PHY_EXTG(base[i] + j), 0);
 243         }
 244
 245         for (i = 0; i < ARRAY_SIZE(base); i++)
 246                 b43_phy_write(dev, B43_PHY_EXTG(base[i] + 0xc), 0);
 247 }
 248
 249 /* Some unknown AFE (Analog Frondned) op */
 250 static void b43_phy_ht_afe_unk1(struct b43_wldev *dev)
 251 {
 252         u8 i;
 253
 254         static const u16 ctl_regs[3][2] = {
 255                 { B43_PHY_HT_AFE_C1_OVER, B43_PHY_HT_AFE_C1 },
 256                 { B43_PHY_HT_AFE_C2_OVER, B43_PHY_HT_AFE_C2 },
 257                 { B43_PHY_HT_AFE_C3_OVER, B43_PHY_HT_AFE_C3},
 258         };
 259
 260         for (i = 0; i < 3; i++) {
 261                 /* TODO: verify masks&sets */
 262                 b43_phy_set(dev, ctl_regs[i][1], 0x4);
 263                 b43_phy_set(dev, ctl_regs[i][0], 0x4);
 264                 b43_phy_mask(dev, ctl_regs[i][1], ~0x1);
 265                 b43_phy_set(dev, ctl_regs[i][0], 0x1);
 266                 b43_httab_write(dev, B43_HTTAB16(8, 5 + (i * 0x10)), 0);
 267                 b43_phy_mask(dev, ctl_regs[i][0], ~0x4);
 268         }
 269 }
 270
 271 static void b43_phy_ht_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 272 {
 273         clip_st[0] = b43_phy_read(dev, B43_PHY_HT_C1_CLIP1THRES);
 274         clip_st[1] = b43_phy_read(dev, B43_PHY_HT_C2_CLIP1THRES);
 275         clip_st[2] = b43_phy_read(dev, B43_PHY_HT_C3_CLIP1THRES);
 276 }
 277
 278 static void b43_phy_ht_bphy_init(struct b43_wldev *dev)
 279 {
 280         unsigned int i;
 281         u16 val;
 282
 283         val = 0x1E1F;
 284         for (i = 0; i < 16; i++) {
 285                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
 286                 val -= 0x202;
 287         }
 288         val = 0x3E3F;
 289         for (i = 0; i < 16; i++) {
 290                 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
 291                 val -= 0x202;
 292         }
 293         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
 294 }
 295
 296 /**************************************************
 297  * Samples
 298  **************************************************/
 299
 300 #if 0
 301 static void b43_phy_ht_stop_playback(struct b43_wldev *dev)
 302 {
 303         struct b43_phy_ht *phy_ht = dev->phy.ht;
 304         u16 tmp;
 305         int i;
 306
 307         tmp = b43_phy_read(dev, B43_PHY_HT_SAMP_STAT);
 308         if (tmp & 0x1)
 309                 b43_phy_set(dev, B43_PHY_HT_SAMP_CMD, B43_PHY_HT_SAMP_CMD_STOP);
 310         else if (tmp & 0x2)
 311                 b43_phy_mask(dev, B43_PHY_HT_IQLOCAL_CMDGCTL, 0x7FFF);
 312
 313         b43_phy_mask(dev, B43_PHY_HT_SAMP_CMD, ~0x0004);
 314
 315         for (i = 0; i < 3; i++) {
 316                 if (phy_ht->bb_mult_save[i] >= 0) {
 317                         b43_httab_write(dev, B43_HTTAB16(13, 0x63 + i * 4),
 318                                         phy_ht->bb_mult_save[i]);
 319                         b43_httab_write(dev, B43_HTTAB16(13, 0x67 + i * 4),
 320                                         phy_ht->bb_mult_save[i]);
 321                 }
 322         }
 323 }
 324
 325 static u16 b43_phy_ht_load_samples(struct b43_wldev *dev)
 326 {
 327         int i;
 328         u16 len = 20 << 3;
 329
 330         b43_phy_write(dev, B43_PHY_HT_TABLE_ADDR, 0x4400);
 331
 332         for (i = 0; i < len; i++) {
 333                 b43_phy_write(dev, B43_PHY_HT_TABLE_DATAHI, 0);
 334                 b43_phy_write(dev, B43_PHY_HT_TABLE_DATALO, 0);
 335         }
 336
 337         return len;
 338 }
 339
 340 static void b43_phy_ht_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
 341                                    u16 wait)
 342 {
 343         struct b43_phy_ht *phy_ht = dev->phy.ht;
 344         u16 save_seq_mode;
 345         int i;
 346
 347         for (i = 0; i < 3; i++) {
 348                 if (phy_ht->bb_mult_save[i] < 0)
 349                         phy_ht->bb_mult_save[i] = b43_httab_read(dev, B43_HTTAB16(13, 0x63 + i * 4));
 350         }
 351
 352         b43_phy_write(dev, B43_PHY_HT_SAMP_DEP_CNT, samps - 1);
 353         if (loops != 0xFFFF)
 354                 loops--;
 355         b43_phy_write(dev, B43_PHY_HT_SAMP_LOOP_CNT, loops);
 356         b43_phy_write(dev, B43_PHY_HT_SAMP_WAIT_CNT, wait);
 357
 358         save_seq_mode = b43_phy_read(dev, B43_PHY_HT_RF_SEQ_MODE);
 359         b43_phy_set(dev, B43_PHY_HT_RF_SEQ_MODE,
 360                     B43_PHY_HT_RF_SEQ_MODE_CA_OVER);
 361
 362         /* TODO: find out mask bits! Do we need more function arguments? */
 363         b43_phy_mask(dev, B43_PHY_HT_SAMP_CMD, ~0);
 364         b43_phy_mask(dev, B43_PHY_HT_SAMP_CMD, ~0);
 365         b43_phy_mask(dev, B43_PHY_HT_IQLOCAL_CMDGCTL, ~0);
 366         b43_phy_set(dev, B43_PHY_HT_SAMP_CMD, 0x1);
 367
 368         for (i = 0; i < 100; i++) {
 369                 if (!(b43_phy_read(dev, B43_PHY_HT_RF_SEQ_STATUS) & 1)) {
 370                         i = 0;
 371                         break;
 372                 }
 373                 udelay(10);
 374         }
 375         if (i)
 376                 b43err(dev->wl, "run samples timeout\n");
 377
 378         b43_phy_write(dev, B43_PHY_HT_RF_SEQ_MODE, save_seq_mode);
 379 }
 380
 381 static void b43_phy_ht_tx_tone(struct b43_wldev *dev)
 382 {
 383         u16 samp;
 384
 385         samp = b43_phy_ht_load_samples(dev);
 386         b43_phy_ht_run_samples(dev, samp, 0xFFFF, 0);
 387 }
 388 #endif
 389
 390 /**************************************************
 391  * Tx/Rx
 392  **************************************************/
 393
 394 static void b43_phy_ht_tx_power_fix(struct b43_wldev *dev)
 395 {
 396         int i;
 397
 398         for (i = 0; i < 3; i++) {
 399                 u16 mask;
 400                 u32 tmp = b43_httab_read(dev, B43_HTTAB32(26, 0xE8));
 401
 402                 if (0) /* FIXME */
 403                         mask = 0x2 << (i * 4);
 404                 else
 405                         mask = 0;
 406                 b43_phy_mask(dev, B43_PHY_EXTG(0x108), mask);
 407
 408                 b43_httab_write(dev, B43_HTTAB16(7, 0x110 + i), tmp >> 16);
 409                 b43_httab_write(dev, B43_HTTAB8(13, 0x63 + (i * 4)),
 410                                 tmp & 0xFF);
 411                 b43_httab_write(dev, B43_HTTAB8(13, 0x73 + (i * 4)),
 412                                 tmp & 0xFF);
 413         }
 414 }
 415
 416 #if 0
 417 static void b43_phy_ht_tx_power_ctl(struct b43_wldev *dev, bool enable)
 418 {
 419         struct b43_phy_ht *phy_ht = dev->phy.ht;
 420         u16 en_bits = B43_PHY_HT_TXPCTL_CMD_C1_COEFF |
 421                       B43_PHY_HT_TXPCTL_CMD_C1_HWPCTLEN |
 422                       B43_PHY_HT_TXPCTL_CMD_C1_PCTLEN;
 423         static const u16 cmd_regs[3] = { B43_PHY_HT_TXPCTL_CMD_C1,
 424                                          B43_PHY_HT_TXPCTL_CMD_C2,
 425                                          B43_PHY_HT_TXPCTL_CMD_C3 };
 426         int i;
 427
 428         if (!enable) {
 429                 if (b43_phy_read(dev, B43_PHY_HT_TXPCTL_CMD_C1) & en_bits) {
 430                         /* We disable enabled TX pwr ctl, save it's state */
 431                         /*
 432                          * TODO: find the registers. On N-PHY they were 0x1ed
 433                          * and 0x1ee, we need 3 such a registers for HT-PHY
 434                          */
 435                 }
 436                 b43_phy_mask(dev, B43_PHY_HT_TXPCTL_CMD_C1, ~en_bits);
 437         } else {
 438                 b43_phy_set(dev, B43_PHY_HT_TXPCTL_CMD_C1, en_bits);
 439
 440                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
 441                         for (i = 0; i < 3; i++)
 442                                 b43_phy_write(dev, cmd_regs[i], 0x32);
 443                 }
 444
 445                 for (i = 0; i < 3; i++)
 446                         if (phy_ht->tx_pwr_idx[i] <=
 447                             B43_PHY_HT_TXPCTL_CMD_C1_INIT)
 448                                 b43_phy_write(dev, cmd_regs[i],
 449                                               phy_ht->tx_pwr_idx[i]);
 450         }
 451
 452         phy_ht->tx_pwr_ctl = enable;
 453 }
 454
 455 static void b43_phy_ht_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
 456 {
 457         /* TODO */
 458
 459         b43_phy_ht_tx_tone(dev);
 460         udelay(20);
 461         /* TODO: poll RSSI */
 462         b43_phy_ht_stop_playback(dev);
 463
 464         /* TODO */
 465 }
 466 #endif
 467
 468 /**************************************************
 469  * Channel switching ops.
 470  **************************************************/
 471
 472 static void b43_phy_ht_spur_avoid(struct b43_wldev *dev,
 473                                   struct ieee80211_channel *new_channel)
 474 {
 475         struct bcma_device *core = dev->dev->bdev;
 476         int spuravoid = 0;
 477         u16 tmp;
 478
 479         /* Check for 13 and 14 is just a guess, we don't have enough logs. */
 480         if (new_channel->hw_value == 13 || new_channel->hw_value == 14)
 481                 spuravoid = 1;
 482         bcma_core_pll_ctl(core, B43_BCMA_CLKCTLST_PHY_PLL_REQ, 0, false);
 483         bcma_pmu_spuravoid_pllupdate(&core->bus->drv_cc, spuravoid);
 484         bcma_core_pll_ctl(core,
 485                           B43_BCMA_CLKCTLST_80211_PLL_REQ |
 486                           B43_BCMA_CLKCTLST_PHY_PLL_REQ,
 487                           B43_BCMA_CLKCTLST_80211_PLL_ST |
 488                           B43_BCMA_CLKCTLST_PHY_PLL_ST, false);
 489
 490         /* Values has been taken from wlc_bmac_switch_macfreq comments */
 491         switch (spuravoid) {
 492         case 2: /* 126MHz */
 493                 tmp = 0x2082;
 494                 break;
 495         case 1: /* 123MHz */
 496                 tmp = 0x5341;
 497                 break;
 498         default: /* 120MHz */
 499                 tmp = 0x8889;
 500         }
 501
 502         b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, tmp);
 503         b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
 504
 505         /* TODO: reset PLL */
 506
 507         if (spuravoid)
 508                 b43_phy_set(dev, B43_PHY_HT_BBCFG, B43_PHY_HT_BBCFG_RSTRX);
 509         else
 510                 b43_phy_mask(dev, B43_PHY_HT_BBCFG,
 511                                 ~B43_PHY_HT_BBCFG_RSTRX & 0xFFFF);
 512
 513         b43_phy_ht_reset_cca(dev);
 514 }
 515
 516 static void b43_phy_ht_channel_setup(struct b43_wldev *dev,
 517                                 const struct b43_phy_ht_channeltab_e_phy *e,
 518                                 struct ieee80211_channel *new_channel)
 519 {
 520         bool old_band_5ghz;
 521
 522         old_band_5ghz = b43_phy_read(dev, B43_PHY_HT_BANDCTL) & 0; /* FIXME */
 523         if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
 524                 /* TODO */
 525         } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
 526                 /* TODO */
 527         }
 528
 529         b43_phy_write(dev, B43_PHY_HT_BW1, e->bw1);
 530         b43_phy_write(dev, B43_PHY_HT_BW2, e->bw2);
 531         b43_phy_write(dev, B43_PHY_HT_BW3, e->bw3);
 532         b43_phy_write(dev, B43_PHY_HT_BW4, e->bw4);
 533         b43_phy_write(dev, B43_PHY_HT_BW5, e->bw5);
 534         b43_phy_write(dev, B43_PHY_HT_BW6, e->bw6);
 535
 536         if (new_channel->hw_value == 14) {
 537                 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_OFDM_EN, 0);
 538                 b43_phy_set(dev, B43_PHY_HT_TEST, 0x0800);
 539         } else {
 540                 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_OFDM_EN,
 541                                       B43_PHY_HT_CLASS_CTL_OFDM_EN);
 542                 if (new_channel->band == IEEE80211_BAND_2GHZ)
 543                         b43_phy_mask(dev, B43_PHY_HT_TEST, ~0x840);
 544         }
 545
 546         if (1) /* TODO: On N it's for early devices only, what about HT? */
 547                 b43_phy_ht_tx_power_fix(dev);
 548
 549         b43_phy_ht_spur_avoid(dev, new_channel);
 550
 551         b43_phy_write(dev, 0x017e, 0x3830);
 552 }
 553
 554 static int b43_phy_ht_set_channel(struct b43_wldev *dev,
 555                                   struct ieee80211_channel *channel,
 556                                   enum nl80211_channel_type channel_type)
 557 {
 558         struct b43_phy *phy = &dev->phy;
 559
 560         const struct b43_phy_ht_channeltab_e_radio2059 *chent_r2059 = NULL;
 561
 562         if (phy->radio_ver == 0x2059) {
 563                 chent_r2059 = b43_phy_ht_get_channeltab_e_r2059(dev,
 564                                                         channel->center_freq);
 565                 if (!chent_r2059)
 566                         return -ESRCH;
 567         } else {
 568                 return -ESRCH;
 569         }
 570
 571         /* TODO: In case of N-PHY some bandwidth switching goes here */
 572
 573         if (phy->radio_ver == 0x2059) {
 574                 b43_radio_2059_channel_setup(dev, chent_r2059);
 575                 b43_phy_ht_channel_setup(dev, &(chent_r2059->phy_regs),
 576                                          channel);
 577         } else {
 578                 return -ESRCH;
 579         }
 580
 581         return 0;
 582 }
 583
 584 /**************************************************
 585  * Basic PHY ops.
 586  **************************************************/
 587
 588 static int b43_phy_ht_op_allocate(struct b43_wldev *dev)
 589 {
 590         struct b43_phy_ht *phy_ht;
 591
 592         phy_ht = kzalloc(sizeof(*phy_ht), GFP_KERNEL);
 593         if (!phy_ht)
 594                 return -ENOMEM;
 595         dev->phy.ht = phy_ht;
 596
 597         return 0;
 598 }
 599
 600 static void b43_phy_ht_op_prepare_structs(struct b43_wldev *dev)
 601 {
 602         struct b43_phy *phy = &dev->phy;
 603         struct b43_phy_ht *phy_ht = phy->ht;
 604         int i;
 605
 606         memset(phy_ht, 0, sizeof(*phy_ht));
 607
 608         phy_ht->tx_pwr_ctl = true;
 609         for (i = 0; i < 3; i++)
 610                 phy_ht->tx_pwr_idx[i] = B43_PHY_HT_TXPCTL_CMD_C1_INIT + 1;
 611
 612         for (i = 0; i < 3; i++)
 613                 phy_ht->bb_mult_save[i] = -1;
 614 }
 615
 616 static int b43_phy_ht_op_init(struct b43_wldev *dev)
 617 {
 618         struct b43_phy_ht *phy_ht = dev->phy.ht;
 619         u16 tmp;
 620         u16 clip_state[3];
 621         bool saved_tx_pwr_ctl;
 622
 623         if (dev->dev->bus_type != B43_BUS_BCMA) {
 624                 b43err(dev->wl, "HT-PHY is supported only on BCMA bus!\n");
 625                 return -EOPNOTSUPP;
 626         }
 627
 628         b43_phy_ht_tables_init(dev);
 629
 630         b43_phy_mask(dev, 0x0be, ~0x2);
 631         b43_phy_set(dev, 0x23f, 0x7ff);
 632         b43_phy_set(dev, 0x240, 0x7ff);
 633         b43_phy_set(dev, 0x241, 0x7ff);
 634
 635         b43_phy_ht_zero_extg(dev);
 636
 637         b43_phy_mask(dev, B43_PHY_EXTG(0), ~0x3);
 638
 639         b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0);
 640         b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0);
 641         b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0);
 642
 643         b43_phy_write(dev, B43_PHY_EXTG(0x103), 0x20);
 644         b43_phy_write(dev, B43_PHY_EXTG(0x101), 0x20);
 645         b43_phy_write(dev, 0x20d, 0xb8);
 646         b43_phy_write(dev, B43_PHY_EXTG(0x14f), 0xc8);
 647         b43_phy_write(dev, 0x70, 0x50);
 648         b43_phy_write(dev, 0x1ff, 0x30);
 649
 650         if (0) /* TODO: condition */
 651                 ; /* TODO: PHY op on reg 0x217 */
 652
 653         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
 654                 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_CCK_EN, 0);
 655         else
 656                 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_CCK_EN,
 657                                       B43_PHY_HT_CLASS_CTL_CCK_EN);
 658
 659         b43_phy_set(dev, 0xb1, 0x91);
 660         b43_phy_write(dev, 0x32f, 0x0003);
 661         b43_phy_write(dev, 0x077, 0x0010);
 662         b43_phy_write(dev, 0x0b4, 0x0258);
 663         b43_phy_mask(dev, 0x17e, ~0x4000);
 664
 665         b43_phy_write(dev, 0x0b9, 0x0072);
 666
 667         b43_httab_write_few(dev, B43_HTTAB16(7, 0x14e), 2, 0x010f, 0x010f);
 668         b43_httab_write_few(dev, B43_HTTAB16(7, 0x15e), 2, 0x010f, 0x010f);
 669         b43_httab_write_few(dev, B43_HTTAB16(7, 0x16e), 2, 0x010f, 0x010f);
 670
 671         b43_phy_ht_afe_unk1(dev);
 672
 673         b43_httab_write_few(dev, B43_HTTAB16(7, 0x130), 9, 0x777, 0x111, 0x111,
 674                             0x777, 0x111, 0x111, 0x777, 0x111, 0x111);
 675
 676         b43_httab_write(dev, B43_HTTAB16(7, 0x120), 0x0777);
 677         b43_httab_write(dev, B43_HTTAB16(7, 0x124), 0x0777);
 678
 679         b43_httab_write(dev, B43_HTTAB16(8, 0x00), 0x02);
 680         b43_httab_write(dev, B43_HTTAB16(8, 0x10), 0x02);
 681         b43_httab_write(dev, B43_HTTAB16(8, 0x20), 0x02);
 682
 683         b43_httab_write_few(dev, B43_HTTAB16(8, 0x08), 4,
 684                             0x8e, 0x96, 0x96, 0x96);
 685         b43_httab_write_few(dev, B43_HTTAB16(8, 0x18), 4,
 686                             0x8f, 0x9f, 0x9f, 0x9f);
 687         b43_httab_write_few(dev, B43_HTTAB16(8, 0x28), 4,
 688                             0x8f, 0x9f, 0x9f, 0x9f);
 689
 690         b43_httab_write_few(dev, B43_HTTAB16(8, 0x0c), 4, 0x2, 0x2, 0x2, 0x2);
 691         b43_httab_write_few(dev, B43_HTTAB16(8, 0x1c), 4, 0x2, 0x2, 0x2, 0x2);
 692         b43_httab_write_few(dev, B43_HTTAB16(8, 0x2c), 4, 0x2, 0x2, 0x2, 0x2);
 693
 694         b43_phy_maskset(dev, 0x0280, 0xff00, 0x3e);
 695         b43_phy_maskset(dev, 0x0283, 0xff00, 0x3e);
 696         b43_phy_maskset(dev, B43_PHY_OFDM(0x0141), 0xff00, 0x46);
 697         b43_phy_maskset(dev, 0x0283, 0xff00, 0x40);
 698
 699         b43_httab_write_few(dev, B43_HTTAB16(00, 0x8), 4,
 700                             0x09, 0x0e, 0x13, 0x18);
 701         b43_httab_write_few(dev, B43_HTTAB16(01, 0x8), 4,
 702                             0x09, 0x0e, 0x13, 0x18);
 703         /* TODO: Did wl mean 2 instead of 40? */
 704         b43_httab_write_few(dev, B43_HTTAB16(40, 0x8), 4,
 705                             0x09, 0x0e, 0x13, 0x18);
 706
 707         b43_phy_maskset(dev, B43_PHY_OFDM(0x24), 0x3f, 0xd);
 708         b43_phy_maskset(dev, B43_PHY_OFDM(0x64), 0x3f, 0xd);
 709         b43_phy_maskset(dev, B43_PHY_OFDM(0xa4), 0x3f, 0xd);
 710
 711         b43_phy_set(dev, B43_PHY_EXTG(0x060), 0x1);
 712         b43_phy_set(dev, B43_PHY_EXTG(0x064), 0x1);
 713         b43_phy_set(dev, B43_PHY_EXTG(0x080), 0x1);
 714         b43_phy_set(dev, B43_PHY_EXTG(0x084), 0x1);
 715
 716         /* Copy some tables entries */
 717         tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x144));
 718         b43_httab_write(dev, B43_HTTAB16(7, 0x14a), tmp);
 719         tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x154));
 720         b43_httab_write(dev, B43_HTTAB16(7, 0x15a), tmp);
 721         tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x164));
 722         b43_httab_write(dev, B43_HTTAB16(7, 0x16a), tmp);
 723
 724         /* Reset CCA */
 725         b43_phy_force_clock(dev, true);
 726         tmp = b43_phy_read(dev, B43_PHY_HT_BBCFG);
 727         b43_phy_write(dev, B43_PHY_HT_BBCFG, tmp | B43_PHY_HT_BBCFG_RSTCCA);
 728         b43_phy_write(dev, B43_PHY_HT_BBCFG, tmp & ~B43_PHY_HT_BBCFG_RSTCCA);
 729         b43_phy_force_clock(dev, false);
 730
 731         b43_mac_phy_clock_set(dev, true);
 732
 733         b43_phy_ht_pa_override(dev, false);
 734         b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RX2TX);
 735         b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RST2RX);
 736         b43_phy_ht_pa_override(dev, true);
 737
 738         /* TODO: Should we restore it? Or store it in global PHY info? */
 739         b43_phy_ht_classifier(dev, 0, 0);
 740         b43_phy_ht_read_clip_detection(dev, clip_state);
 741
 742         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 743                 b43_phy_ht_bphy_init(dev);
 744
 745         b43_httab_write_bulk(dev, B43_HTTAB32(0x1a, 0xc0),
 746                         B43_HTTAB_1A_C0_LATE_SIZE, b43_httab_0x1a_0xc0_late);
 747
 748         saved_tx_pwr_ctl = phy_ht->tx_pwr_ctl;
 749         b43_phy_ht_tx_power_fix(dev);
 750 #if 0
 751         b43_phy_ht_tx_power_ctl(dev, false);
 752         b43_phy_ht_tx_power_ctl_idle_tssi(dev);
 753         /* TODO */
 754         b43_phy_ht_tx_power_ctl(dev, saved_tx_pwr_ctl);
 755 #endif
 756
 757         return 0;
 758 }
 759
 760 static void b43_phy_ht_op_free(struct b43_wldev *dev)
 761 {
 762         struct b43_phy *phy = &dev->phy;
 763         struct b43_phy_ht *phy_ht = phy->ht;
 764
 765         kfree(phy_ht);
 766         phy->ht = NULL;
 767 }
 768
 769 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
 770 static void b43_phy_ht_op_software_rfkill(struct b43_wldev *dev,
 771                                         bool blocked)
 772 {
 773         if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
 774                 b43err(dev->wl, "MAC not suspended\n");
 775
 776         /* In the following PHY ops we copy wl's dummy behaviour.
 777          * TODO: Find out if reads (currently hidden in masks/masksets) are
 778          * needed and replace following ops with just writes or w&r.
 779          * Note: B43_PHY_HT_RF_CTL1 register is tricky, wrong operation can
 780          * cause delayed (!) machine lock up. */
 781         if (blocked) {
 782                 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
 783         } else {
 784                 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
 785                 b43_phy_maskset(dev, B43_PHY_HT_RF_CTL1, 0, 0x1);
 786                 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
 787                 b43_phy_maskset(dev, B43_PHY_HT_RF_CTL1, 0, 0x2);
 788
 789                 if (dev->phy.radio_ver == 0x2059)
 790                         b43_radio_2059_init(dev);
 791                 else
 792                         B43_WARN_ON(1);
 793
 794                 b43_switch_channel(dev, dev->phy.channel);
 795         }
 796 }
 797
 798 static void b43_phy_ht_op_switch_analog(struct b43_wldev *dev, bool on)
 799 {
 800         if (on) {
 801                 b43_phy_write(dev, B43_PHY_HT_AFE_C1, 0x00cd);
 802                 b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0x0000);
 803                 b43_phy_write(dev, B43_PHY_HT_AFE_C2, 0x00cd);
 804                 b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0x0000);
 805                 b43_phy_write(dev, B43_PHY_HT_AFE_C3, 0x00cd);
 806                 b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0x0000);
 807         } else {
 808                 b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0x07ff);
 809                 b43_phy_write(dev, B43_PHY_HT_AFE_C1, 0x00fd);
 810                 b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0x07ff);
 811                 b43_phy_write(dev, B43_PHY_HT_AFE_C2, 0x00fd);
 812                 b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0x07ff);
 813                 b43_phy_write(dev, B43_PHY_HT_AFE_C3, 0x00fd);
 814         }
 815 }
 816
 817 static int b43_phy_ht_op_switch_channel(struct b43_wldev *dev,
 818                                         unsigned int new_channel)
 819 {
 820         struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
 821         enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
 822
 823         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 824                 if ((new_channel < 1) || (new_channel > 14))
 825                         return -EINVAL;
 826         } else {
 827                 return -EINVAL;
 828         }
 829
 830         return b43_phy_ht_set_channel(dev, channel, channel_type);
 831 }
 832
 833 static unsigned int b43_phy_ht_op_get_default_chan(struct b43_wldev *dev)
 834 {
 835         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 836                 return 11;
 837         return 36;
 838 }
 839
 840 /**************************************************
 841  * R/W ops.
 842  **************************************************/
 843
 844 static u16 b43_phy_ht_op_read(struct b43_wldev *dev, u16 reg)
 845 {
 846         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 847         return b43_read16(dev, B43_MMIO_PHY_DATA);
 848 }
 849
 850 static void b43_phy_ht_op_write(struct b43_wldev *dev, u16 reg, u16 value)
 851 {
 852         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 853         b43_write16(dev, B43_MMIO_PHY_DATA, value);
 854 }
 855
 856 static void b43_phy_ht_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
 857                                  u16 set)
 858 {
 859         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 860         b43_write16(dev, B43_MMIO_PHY_DATA,
 861                     (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
 862 }
 863
 864 static u16 b43_phy_ht_op_radio_read(struct b43_wldev *dev, u16 reg)
 865 {
 866         /* HT-PHY needs 0x200 for read access */
 867         reg |= 0x200;
 868
 869         b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
 870         return b43_read16(dev, B43_MMIO_RADIO24_DATA);
 871 }
 872
 873 static void b43_phy_ht_op_radio_write(struct b43_wldev *dev, u16 reg,
 874                                       u16 value)
 875 {
 876         b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
 877         b43_write16(dev, B43_MMIO_RADIO24_DATA, value);
 878 }
 879
 880 static enum b43_txpwr_result
 881 b43_phy_ht_op_recalc_txpower(struct b43_wldev *dev, bool ignore_tssi)
 882 {
 883         return B43_TXPWR_RES_DONE;
 884 }
 885
 886 static void b43_phy_ht_op_adjust_txpower(struct b43_wldev *dev)
 887 {
 888 }
 889
 890 /**************************************************
 891  * PHY ops struct.
 892  **************************************************/
 893
 894 const struct b43_phy_operations b43_phyops_ht = {
 895         .allocate               = b43_phy_ht_op_allocate,
 896         .free                   = b43_phy_ht_op_free,
 897         .prepare_structs        = b43_phy_ht_op_prepare_structs,
 898         .init                   = b43_phy_ht_op_init,
 899         .phy_read               = b43_phy_ht_op_read,
 900         .phy_write              = b43_phy_ht_op_write,
 901         .phy_maskset            = b43_phy_ht_op_maskset,
 902         .radio_read             = b43_phy_ht_op_radio_read,
 903         .radio_write            = b43_phy_ht_op_radio_write,
 904         .software_rfkill        = b43_phy_ht_op_software_rfkill,
 905         .switch_analog          = b43_phy_ht_op_switch_analog,
 906         .switch_channel         = b43_phy_ht_op_switch_channel,
 907         .get_default_chan       = b43_phy_ht_op_get_default_chan,
 908         .recalc_txpower         = b43_phy_ht_op_recalc_txpower,
 909         .adjust_txpower         = b43_phy_ht_op_adjust_txpower,
 910 };