Pileus Git - ~andy/linux/blob - drivers/net/wireless/ath9k/main.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include "ath9k.h"
  19
  20 #define ATH_PCI_VERSION "0.1"
  21
  22 static char *dev_info = "ath9k";
  23
  24 MODULE_AUTHOR("Atheros Communications");
  25 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  26 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  27 MODULE_LICENSE("Dual BSD/GPL");
  28
  29 static int modparam_nohwcrypt;
  30 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
  31 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
  32
  33 /* We use the hw_value as an index into our private channel structure */
  34
  35 #define CHAN2G(_freq, _idx)  { \
  36         .center_freq = (_freq), \
  37         .hw_value = (_idx), \
  38         .max_power = 30, \
  39 }
  40
  41 #define CHAN5G(_freq, _idx) { \
  42         .band = IEEE80211_BAND_5GHZ, \
  43         .center_freq = (_freq), \
  44         .hw_value = (_idx), \
  45         .max_power = 30, \
  46 }
  47
  48 /* Some 2 GHz radios are actually tunable on 2312-2732
  49  * on 5 MHz steps, we support the channels which we know
  50  * we have calibration data for all cards though to make
  51  * this static */
  52 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
  53         CHAN2G(2412, 0), /* Channel 1 */
  54         CHAN2G(2417, 1), /* Channel 2 */
  55         CHAN2G(2422, 2), /* Channel 3 */
  56         CHAN2G(2427, 3), /* Channel 4 */
  57         CHAN2G(2432, 4), /* Channel 5 */
  58         CHAN2G(2437, 5), /* Channel 6 */
  59         CHAN2G(2442, 6), /* Channel 7 */
  60         CHAN2G(2447, 7), /* Channel 8 */
  61         CHAN2G(2452, 8), /* Channel 9 */
  62         CHAN2G(2457, 9), /* Channel 10 */
  63         CHAN2G(2462, 10), /* Channel 11 */
  64         CHAN2G(2467, 11), /* Channel 12 */
  65         CHAN2G(2472, 12), /* Channel 13 */
  66         CHAN2G(2484, 13), /* Channel 14 */
  67 };
  68
  69 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
  70  * on 5 MHz steps, we support the channels which we know
  71  * we have calibration data for all cards though to make
  72  * this static */
  73 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
  74         /* _We_ call this UNII 1 */
  75         CHAN5G(5180, 14), /* Channel 36 */
  76         CHAN5G(5200, 15), /* Channel 40 */
  77         CHAN5G(5220, 16), /* Channel 44 */
  78         CHAN5G(5240, 17), /* Channel 48 */
  79         /* _We_ call this UNII 2 */
  80         CHAN5G(5260, 18), /* Channel 52 */
  81         CHAN5G(5280, 19), /* Channel 56 */
  82         CHAN5G(5300, 20), /* Channel 60 */
  83         CHAN5G(5320, 21), /* Channel 64 */
  84         /* _We_ call this "Middle band" */
  85         CHAN5G(5500, 22), /* Channel 100 */
  86         CHAN5G(5520, 23), /* Channel 104 */
  87         CHAN5G(5540, 24), /* Channel 108 */
  88         CHAN5G(5560, 25), /* Channel 112 */
  89         CHAN5G(5580, 26), /* Channel 116 */
  90         CHAN5G(5600, 27), /* Channel 120 */
  91         CHAN5G(5620, 28), /* Channel 124 */
  92         CHAN5G(5640, 29), /* Channel 128 */
  93         CHAN5G(5660, 30), /* Channel 132 */
  94         CHAN5G(5680, 31), /* Channel 136 */
  95         CHAN5G(5700, 32), /* Channel 140 */
  96         /* _We_ call this UNII 3 */
  97         CHAN5G(5745, 33), /* Channel 149 */
  98         CHAN5G(5765, 34), /* Channel 153 */
  99         CHAN5G(5785, 35), /* Channel 157 */
 100         CHAN5G(5805, 36), /* Channel 161 */
 101         CHAN5G(5825, 37), /* Channel 165 */
 102 };
 103
 104 static void ath_cache_conf_rate(struct ath_softc *sc,
 105                                 struct ieee80211_conf *conf)
 106 {
 107         switch (conf->channel->band) {
 108         case IEEE80211_BAND_2GHZ:
 109                 if (conf_is_ht20(conf))
 110                         sc->cur_rate_table =
 111                           sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
 112                 else if (conf_is_ht40_minus(conf))
 113                         sc->cur_rate_table =
 114                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
 115                 else if (conf_is_ht40_plus(conf))
 116                         sc->cur_rate_table =
 117                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
 118                 else
 119                         sc->cur_rate_table =
 120                           sc->hw_rate_table[ATH9K_MODE_11G];
 121                 break;
 122         case IEEE80211_BAND_5GHZ:
 123                 if (conf_is_ht20(conf))
 124                         sc->cur_rate_table =
 125                           sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
 126                 else if (conf_is_ht40_minus(conf))
 127                         sc->cur_rate_table =
 128                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
 129                 else if (conf_is_ht40_plus(conf))
 130                         sc->cur_rate_table =
 131                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
 132                 else
 133                         sc->cur_rate_table =
 134                           sc->hw_rate_table[ATH9K_MODE_11A];
 135                 break;
 136         default:
 137                 BUG_ON(1);
 138                 break;
 139         }
 140 }
 141
 142 static void ath_update_txpow(struct ath_softc *sc)
 143 {
 144         struct ath_hw *ah = sc->sc_ah;
 145         u32 txpow;
 146
 147         if (sc->curtxpow != sc->config.txpowlimit) {
 148                 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
 149                 /* read back in case value is clamped */
 150                 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
 151                 sc->curtxpow = txpow;
 152         }
 153 }
 154
 155 static u8 parse_mpdudensity(u8 mpdudensity)
 156 {
 157         /*
 158          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
 159          *   0 for no restriction
 160          *   1 for 1/4 us
 161          *   2 for 1/2 us
 162          *   3 for 1 us
 163          *   4 for 2 us
 164          *   5 for 4 us
 165          *   6 for 8 us
 166          *   7 for 16 us
 167          */
 168         switch (mpdudensity) {
 169         case 0:
 170                 return 0;
 171         case 1:
 172         case 2:
 173         case 3:
 174                 /* Our lower layer calculations limit our precision to
 175                    1 microsecond */
 176                 return 1;
 177         case 4:
 178                 return 2;
 179         case 5:
 180                 return 4;
 181         case 6:
 182                 return 8;
 183         case 7:
 184                 return 16;
 185         default:
 186                 return 0;
 187         }
 188 }
 189
 190 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
 191 {
 192         struct ath_rate_table *rate_table = NULL;
 193         struct ieee80211_supported_band *sband;
 194         struct ieee80211_rate *rate;
 195         int i, maxrates;
 196
 197         switch (band) {
 198         case IEEE80211_BAND_2GHZ:
 199                 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
 200                 break;
 201         case IEEE80211_BAND_5GHZ:
 202                 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
 203                 break;
 204         default:
 205                 break;
 206         }
 207
 208         if (rate_table == NULL)
 209                 return;
 210
 211         sband = &sc->sbands[band];
 212         rate = sc->rates[band];
 213
 214         if (rate_table->rate_cnt > ATH_RATE_MAX)
 215                 maxrates = ATH_RATE_MAX;
 216         else
 217                 maxrates = rate_table->rate_cnt;
 218
 219         for (i = 0; i < maxrates; i++) {
 220                 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
 221                 rate[i].hw_value = rate_table->info[i].ratecode;
 222                 if (rate_table->info[i].short_preamble) {
 223                         rate[i].hw_value_short = rate_table->info[i].ratecode |
 224                                 rate_table->info[i].short_preamble;
 225                         rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
 226                 }
 227                 sband->n_bitrates++;
 228
 229                 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
 230                         rate[i].bitrate / 10, rate[i].hw_value);
 231         }
 232 }
 233
 234 /*
 235  * Set/change channels.  If the channel is really being changed, it's done
 236  * by reseting the chip.  To accomplish this we must first cleanup any pending
 237  * DMA, then restart stuff.
 238 */
 239 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
 240                     struct ath9k_channel *hchan)
 241 {
 242         struct ath_hw *ah = sc->sc_ah;
 243         bool fastcc = true, stopped;
 244         struct ieee80211_channel *channel = hw->conf.channel;
 245         int r;
 246
 247         if (sc->sc_flags & SC_OP_INVALID)
 248                 return -EIO;
 249
 250         ath9k_ps_wakeup(sc);
 251
 252         /*
 253          * This is only performed if the channel settings have
 254          * actually changed.
 255          *
 256          * To switch channels clear any pending DMA operations;
 257          * wait long enough for the RX fifo to drain, reset the
 258          * hardware at the new frequency, and then re-enable
 259          * the relevant bits of the h/w.
 260          */
 261         ath9k_hw_set_interrupts(ah, 0);
 262         ath_drain_all_txq(sc, false);
 263         stopped = ath_stoprecv(sc);
 264
 265         /* XXX: do not flush receive queue here. We don't want
 266          * to flush data frames already in queue because of
 267          * changing channel. */
 268
 269         if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
 270                 fastcc = false;
 271
 272         DPRINTF(sc, ATH_DBG_CONFIG,
 273                 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
 274                 sc->sc_ah->curchan->channel,
 275                 channel->center_freq, sc->tx_chan_width);
 276
 277         spin_lock_bh(&sc->sc_resetlock);
 278
 279         r = ath9k_hw_reset(ah, hchan, fastcc);
 280         if (r) {
 281                 DPRINTF(sc, ATH_DBG_FATAL,
 282                         "Unable to reset channel (%u Mhz) "
 283                         "reset status %u\n",
 284                         channel->center_freq, r);
 285                 spin_unlock_bh(&sc->sc_resetlock);
 286                 return r;
 287         }
 288         spin_unlock_bh(&sc->sc_resetlock);
 289
 290         sc->sc_flags &= ~SC_OP_FULL_RESET;
 291
 292         if (ath_startrecv(sc) != 0) {
 293                 DPRINTF(sc, ATH_DBG_FATAL,
 294                         "Unable to restart recv logic\n");
 295                 return -EIO;
 296         }
 297
 298         ath_cache_conf_rate(sc, &hw->conf);
 299         ath_update_txpow(sc);
 300         ath9k_hw_set_interrupts(ah, sc->imask);
 301         ath9k_ps_restore(sc);
 302         return 0;
 303 }
 304
 305 /*
 306  *  This routine performs the periodic noise floor calibration function
 307  *  that is used to adjust and optimize the chip performance.  This
 308  *  takes environmental changes (location, temperature) into account.
 309  *  When the task is complete, it reschedules itself depending on the
 310  *  appropriate interval that was calculated.
 311  */
 312 static void ath_ani_calibrate(unsigned long data)
 313 {
 314         struct ath_softc *sc = (struct ath_softc *)data;
 315         struct ath_hw *ah = sc->sc_ah;
 316         bool longcal = false;
 317         bool shortcal = false;
 318         bool aniflag = false;
 319         unsigned int timestamp = jiffies_to_msecs(jiffies);
 320         u32 cal_interval, short_cal_interval;
 321
 322         short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
 323                 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
 324
 325         /*
 326         * don't calibrate when we're scanning.
 327         * we are most likely not on our home channel.
 328         */
 329         if (sc->sc_flags & SC_OP_SCANNING)
 330                 goto set_timer;
 331
 332         /* Long calibration runs independently of short calibration. */
 333         if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
 334                 longcal = true;
 335                 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
 336                 sc->ani.longcal_timer = timestamp;
 337         }
 338
 339         /* Short calibration applies only while caldone is false */
 340         if (!sc->ani.caldone) {
 341                 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
 342                         shortcal = true;
 343                         DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
 344                         sc->ani.shortcal_timer = timestamp;
 345                         sc->ani.resetcal_timer = timestamp;
 346                 }
 347         } else {
 348                 if ((timestamp - sc->ani.resetcal_timer) >=
 349                     ATH_RESTART_CALINTERVAL) {
 350                         sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
 351                         if (sc->ani.caldone)
 352                                 sc->ani.resetcal_timer = timestamp;
 353                 }
 354         }
 355
 356         /* Verify whether we must check ANI */
 357         if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
 358                 aniflag = true;
 359                 sc->ani.checkani_timer = timestamp;
 360         }
 361
 362         /* Skip all processing if there's nothing to do. */
 363         if (longcal || shortcal || aniflag) {
 364                 /* Call ANI routine if necessary */
 365                 if (aniflag)
 366                         ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
 367
 368                 /* Perform calibration if necessary */
 369                 if (longcal || shortcal) {
 370                         bool iscaldone = false;
 371
 372                         if (ath9k_hw_calibrate(ah, ah->curchan,
 373                                                sc->rx_chainmask, longcal,
 374                                                &iscaldone)) {
 375                                 if (longcal)
 376                                         sc->ani.noise_floor =
 377                                                 ath9k_hw_getchan_noise(ah,
 378                                                                ah->curchan);
 379
 380                                 DPRINTF(sc, ATH_DBG_ANI,
 381                                         "calibrate chan %u/%x nf: %d\n",
 382                                         ah->curchan->channel,
 383                                         ah->curchan->channelFlags,
 384                                         sc->ani.noise_floor);
 385                         } else {
 386                                 DPRINTF(sc, ATH_DBG_ANY,
 387                                         "calibrate chan %u/%x failed\n",
 388                                         ah->curchan->channel,
 389                                         ah->curchan->channelFlags);
 390                         }
 391                         sc->ani.caldone = iscaldone;
 392                 }
 393         }
 394
 395 set_timer:
 396         /*
 397         * Set timer interval based on previous results.
 398         * The interval must be the shortest necessary to satisfy ANI,
 399         * short calibration and long calibration.
 400         */
 401         cal_interval = ATH_LONG_CALINTERVAL;
 402         if (sc->sc_ah->config.enable_ani)
 403                 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
 404         if (!sc->ani.caldone)
 405                 cal_interval = min(cal_interval, (u32)short_cal_interval);
 406
 407         mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
 408 }
 409
 410 /*
 411  * Update tx/rx chainmask. For legacy association,
 412  * hard code chainmask to 1x1, for 11n association, use
 413  * the chainmask configuration, for bt coexistence, use
 414  * the chainmask configuration even in legacy mode.
 415  */
 416 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
 417 {
 418         if (is_ht ||
 419             (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
 420                 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
 421                 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
 422         } else {
 423                 sc->tx_chainmask = 1;
 424                 sc->rx_chainmask = 1;
 425         }
 426
 427         DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
 428                 sc->tx_chainmask, sc->rx_chainmask);
 429 }
 430
 431 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
 432 {
 433         struct ath_node *an;
 434
 435         an = (struct ath_node *)sta->drv_priv;
 436
 437         if (sc->sc_flags & SC_OP_TXAGGR) {
 438                 ath_tx_node_init(sc, an);
 439                 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
 440                                      sta->ht_cap.ampdu_factor);
 441                 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
 442         }
 443 }
 444
 445 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 446 {
 447         struct ath_node *an = (struct ath_node *)sta->drv_priv;
 448
 449         if (sc->sc_flags & SC_OP_TXAGGR)
 450                 ath_tx_node_cleanup(sc, an);
 451 }
 452
 453 static void ath9k_tasklet(unsigned long data)
 454 {
 455         struct ath_softc *sc = (struct ath_softc *)data;
 456         u32 status = sc->intrstatus;
 457
 458         if (status & ATH9K_INT_FATAL) {
 459                 ath_reset(sc, false);
 460                 return;
 461         }
 462
 463         if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
 464                 spin_lock_bh(&sc->rx.rxflushlock);
 465                 ath_rx_tasklet(sc, 0);
 466                 spin_unlock_bh(&sc->rx.rxflushlock);
 467         }
 468
 469         if (status & ATH9K_INT_TX)
 470                 ath_tx_tasklet(sc);
 471
 472         /* re-enable hardware interrupt */
 473         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
 474 }
 475
 476 irqreturn_t ath_isr(int irq, void *dev)
 477 {
 478 #define SCHED_INTR (                            \
 479                 ATH9K_INT_FATAL |               \
 480                 ATH9K_INT_RXORN |               \
 481                 ATH9K_INT_RXEOL |               \
 482                 ATH9K_INT_RX |                  \
 483                 ATH9K_INT_TX |                  \
 484                 ATH9K_INT_BMISS |               \
 485                 ATH9K_INT_CST |                 \
 486                 ATH9K_INT_TSFOOR)
 487
 488         struct ath_softc *sc = dev;
 489         struct ath_hw *ah = sc->sc_ah;
 490         enum ath9k_int status;
 491         bool sched = false;
 492
 493         /*
 494          * The hardware is not ready/present, don't
 495          * touch anything. Note this can happen early
 496          * on if the IRQ is shared.
 497          */
 498         if (sc->sc_flags & SC_OP_INVALID)
 499                 return IRQ_NONE;
 500
 501         ath9k_ps_wakeup(sc);
 502
 503         /* shared irq, not for us */
 504
 505         if (!ath9k_hw_intrpend(ah)) {
 506                 ath9k_ps_restore(sc);
 507                 return IRQ_NONE;
 508         }
 509
 510         /*
 511          * Figure out the reason(s) for the interrupt.  Note
 512          * that the hal returns a pseudo-ISR that may include
 513          * bits we haven't explicitly enabled so we mask the
 514          * value to insure we only process bits we requested.
 515          */
 516         ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
 517         status &= sc->imask;    /* discard unasked-for bits */
 518
 519         /*
 520          * If there are no status bits set, then this interrupt was not
 521          * for me (should have been caught above).
 522          */
 523         if (!status) {
 524                 ath9k_ps_restore(sc);
 525                 return IRQ_NONE;
 526         }
 527
 528         /* Cache the status */
 529         sc->intrstatus = status;
 530
 531         if (status & SCHED_INTR)
 532                 sched = true;
 533
 534         /*
 535          * If a FATAL or RXORN interrupt is received, we have to reset the
 536          * chip immediately.
 537          */
 538         if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
 539                 goto chip_reset;
 540
 541         if (status & ATH9K_INT_SWBA)
 542                 tasklet_schedule(&sc->bcon_tasklet);
 543
 544         if (status & ATH9K_INT_TXURN)
 545                 ath9k_hw_updatetxtriglevel(ah, true);
 546
 547         if (status & ATH9K_INT_MIB) {
 548                 /*
 549                  * Disable interrupts until we service the MIB
 550                  * interrupt; otherwise it will continue to
 551                  * fire.
 552                  */
 553                 ath9k_hw_set_interrupts(ah, 0);
 554                 /*
 555                  * Let the hal handle the event. We assume
 556                  * it will clear whatever condition caused
 557                  * the interrupt.
 558                  */
 559                 ath9k_hw_procmibevent(ah, &sc->nodestats);
 560                 ath9k_hw_set_interrupts(ah, sc->imask);
 561         }
 562
 563         if (status & ATH9K_INT_TIM_TIMER) {
 564                 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
 565                         /* Clear RxAbort bit so that we can
 566                          * receive frames */
 567                         ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
 568                         ath9k_hw_setrxabort(ah, 0);
 569                         sched = true;
 570                         sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
 571                 }
 572         }
 573
 574 chip_reset:
 575
 576         ath9k_ps_restore(sc);
 577         ath_debug_stat_interrupt(sc, status);
 578
 579         if (sched) {
 580                 /* turn off every interrupt except SWBA */
 581                 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
 582                 tasklet_schedule(&sc->intr_tq);
 583         }
 584
 585         return IRQ_HANDLED;
 586
 587 #undef SCHED_INTR
 588 }
 589
 590 static u32 ath_get_extchanmode(struct ath_softc *sc,
 591                                struct ieee80211_channel *chan,
 592                                enum nl80211_channel_type channel_type)
 593 {
 594         u32 chanmode = 0;
 595
 596         switch (chan->band) {
 597         case IEEE80211_BAND_2GHZ:
 598                 switch(channel_type) {
 599                 case NL80211_CHAN_NO_HT:
 600                 case NL80211_CHAN_HT20:
 601                         chanmode = CHANNEL_G_HT20;
 602                         break;
 603                 case NL80211_CHAN_HT40PLUS:
 604                         chanmode = CHANNEL_G_HT40PLUS;
 605                         break;
 606                 case NL80211_CHAN_HT40MINUS:
 607                         chanmode = CHANNEL_G_HT40MINUS;
 608                         break;
 609                 }
 610                 break;
 611         case IEEE80211_BAND_5GHZ:
 612                 switch(channel_type) {
 613                 case NL80211_CHAN_NO_HT:
 614                 case NL80211_CHAN_HT20:
 615                         chanmode = CHANNEL_A_HT20;
 616                         break;
 617                 case NL80211_CHAN_HT40PLUS:
 618                         chanmode = CHANNEL_A_HT40PLUS;
 619                         break;
 620                 case NL80211_CHAN_HT40MINUS:
 621                         chanmode = CHANNEL_A_HT40MINUS;
 622                         break;
 623                 }
 624                 break;
 625         default:
 626                 break;
 627         }
 628
 629         return chanmode;
 630 }
 631
 632 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
 633                            struct ath9k_keyval *hk, const u8 *addr,
 634                            bool authenticator)
 635 {
 636         const u8 *key_rxmic;
 637         const u8 *key_txmic;
 638
 639         key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
 640         key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
 641
 642         if (addr == NULL) {
 643                 /*
 644                  * Group key installation - only two key cache entries are used
 645                  * regardless of splitmic capability since group key is only
 646                  * used either for TX or RX.
 647                  */
 648                 if (authenticator) {
 649                         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 650                         memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
 651                 } else {
 652                         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 653                         memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
 654                 }
 655                 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
 656         }
 657         if (!sc->splitmic) {
 658                 /* TX and RX keys share the same key cache entry. */
 659                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 660                 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
 661                 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
 662         }
 663
 664         /* Separate key cache entries for TX and RX */
 665
 666         /* TX key goes at first index, RX key at +32. */
 667         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 668         if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
 669                 /* TX MIC entry failed. No need to proceed further */
 670                 DPRINTF(sc, ATH_DBG_FATAL,
 671                         "Setting TX MIC Key Failed\n");
 672                 return 0;
 673         }
 674
 675         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 676         /* XXX delete tx key on failure? */
 677         return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
 678 }
 679
 680 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
 681 {
 682         int i;
 683
 684         for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
 685                 if (test_bit(i, sc->keymap) ||
 686                     test_bit(i + 64, sc->keymap))
 687                         continue; /* At least one part of TKIP key allocated */
 688                 if (sc->splitmic &&
 689                     (test_bit(i + 32, sc->keymap) ||
 690                      test_bit(i + 64 + 32, sc->keymap)))
 691                         continue; /* At least one part of TKIP key allocated */
 692
 693                 /* Found a free slot for a TKIP key */
 694                 return i;
 695         }
 696         return -1;
 697 }
 698
 699 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
 700 {
 701         int i;
 702
 703         /* First, try to find slots that would not be available for TKIP. */
 704         if (sc->splitmic) {
 705                 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
 706                         if (!test_bit(i, sc->keymap) &&
 707                             (test_bit(i + 32, sc->keymap) ||
 708                              test_bit(i + 64, sc->keymap) ||
 709                              test_bit(i + 64 + 32, sc->keymap)))
 710                                 return i;
 711                         if (!test_bit(i + 32, sc->keymap) &&
 712                             (test_bit(i, sc->keymap) ||
 713                              test_bit(i + 64, sc->keymap) ||
 714                              test_bit(i + 64 + 32, sc->keymap)))
 715                                 return i + 32;
 716                         if (!test_bit(i + 64, sc->keymap) &&
 717                             (test_bit(i , sc->keymap) ||
 718                              test_bit(i + 32, sc->keymap) ||
 719                              test_bit(i + 64 + 32, sc->keymap)))
 720                                 return i + 64;
 721                         if (!test_bit(i + 64 + 32, sc->keymap) &&
 722                             (test_bit(i, sc->keymap) ||
 723                              test_bit(i + 32, sc->keymap) ||
 724                              test_bit(i + 64, sc->keymap)))
 725                                 return i + 64 + 32;
 726                 }
 727         } else {
 728                 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
 729                         if (!test_bit(i, sc->keymap) &&
 730                             test_bit(i + 64, sc->keymap))
 731                                 return i;
 732                         if (test_bit(i, sc->keymap) &&
 733                             !test_bit(i + 64, sc->keymap))
 734                                 return i + 64;
 735                 }
 736         }
 737
 738         /* No partially used TKIP slots, pick any available slot */
 739         for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
 740                 /* Do not allow slots that could be needed for TKIP group keys
 741                  * to be used. This limitation could be removed if we know that
 742                  * TKIP will not be used. */
 743                 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
 744                         continue;
 745                 if (sc->splitmic) {
 746                         if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
 747                                 continue;
 748                         if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
 749                                 continue;
 750                 }
 751
 752                 if (!test_bit(i, sc->keymap))
 753                         return i; /* Found a free slot for a key */
 754         }
 755
 756         /* No free slot found */
 757         return -1;
 758 }
 759
 760 static int ath_key_config(struct ath_softc *sc,
 761                           struct ieee80211_vif *vif,
 762                           struct ieee80211_sta *sta,
 763                           struct ieee80211_key_conf *key)
 764 {
 765         struct ath9k_keyval hk;
 766         const u8 *mac = NULL;
 767         int ret = 0;
 768         int idx;
 769
 770         memset(&hk, 0, sizeof(hk));
 771
 772         switch (key->alg) {
 773         case ALG_WEP:
 774                 hk.kv_type = ATH9K_CIPHER_WEP;
 775                 break;
 776         case ALG_TKIP:
 777                 hk.kv_type = ATH9K_CIPHER_TKIP;
 778                 break;
 779         case ALG_CCMP:
 780                 hk.kv_type = ATH9K_CIPHER_AES_CCM;
 781                 break;
 782         default:
 783                 return -EOPNOTSUPP;
 784         }
 785
 786         hk.kv_len = key->keylen;
 787         memcpy(hk.kv_val, key->key, key->keylen);
 788
 789         if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
 790                 /* For now, use the default keys for broadcast keys. This may
 791                  * need to change with virtual interfaces. */
 792                 idx = key->keyidx;
 793         } else if (key->keyidx) {
 794                 if (WARN_ON(!sta))
 795                         return -EOPNOTSUPP;
 796                 mac = sta->addr;
 797
 798                 if (vif->type != NL80211_IFTYPE_AP) {
 799                         /* Only keyidx 0 should be used with unicast key, but
 800                          * allow this for client mode for now. */
 801                         idx = key->keyidx;
 802                 } else
 803                         return -EIO;
 804         } else {
 805                 if (WARN_ON(!sta))
 806                         return -EOPNOTSUPP;
 807                 mac = sta->addr;
 808
 809                 if (key->alg == ALG_TKIP)
 810                         idx = ath_reserve_key_cache_slot_tkip(sc);
 811                 else
 812                         idx = ath_reserve_key_cache_slot(sc);
 813                 if (idx < 0)
 814                         return -ENOSPC; /* no free key cache entries */
 815         }
 816
 817         if (key->alg == ALG_TKIP)
 818                 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
 819                                       vif->type == NL80211_IFTYPE_AP);
 820         else
 821                 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
 822
 823         if (!ret)
 824                 return -EIO;
 825
 826         set_bit(idx, sc->keymap);
 827         if (key->alg == ALG_TKIP) {
 828                 set_bit(idx + 64, sc->keymap);
 829                 if (sc->splitmic) {
 830                         set_bit(idx + 32, sc->keymap);
 831                         set_bit(idx + 64 + 32, sc->keymap);
 832                 }
 833         }
 834
 835         return idx;
 836 }
 837
 838 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
 839 {
 840         ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
 841         if (key->hw_key_idx < IEEE80211_WEP_NKID)
 842                 return;
 843
 844         clear_bit(key->hw_key_idx, sc->keymap);
 845         if (key->alg != ALG_TKIP)
 846                 return;
 847
 848         clear_bit(key->hw_key_idx + 64, sc->keymap);
 849         if (sc->splitmic) {
 850                 clear_bit(key->hw_key_idx + 32, sc->keymap);
 851                 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
 852         }
 853 }
 854
 855 static void setup_ht_cap(struct ath_softc *sc,
 856                          struct ieee80211_sta_ht_cap *ht_info)
 857 {
 858 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3       /* 2 ^ 16 */
 859 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6          /* 8 usec */
 860
 861         ht_info->ht_supported = true;
 862         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
 863                        IEEE80211_HT_CAP_SM_PS |
 864                        IEEE80211_HT_CAP_SGI_40 |
 865                        IEEE80211_HT_CAP_DSSSCCK40;
 866
 867         ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
 868         ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
 869
 870         /* set up supported mcs set */
 871         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
 872
 873         switch(sc->rx_chainmask) {
 874         case 1:
 875                 ht_info->mcs.rx_mask[0] = 0xff;
 876                 break;
 877         case 3:
 878         case 5:
 879         case 7:
 880         default:
 881                 ht_info->mcs.rx_mask[0] = 0xff;
 882                 ht_info->mcs.rx_mask[1] = 0xff;
 883                 break;
 884         }
 885
 886         ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
 887 }
 888
 889 static void ath9k_bss_assoc_info(struct ath_softc *sc,
 890                                  struct ieee80211_vif *vif,
 891                                  struct ieee80211_bss_conf *bss_conf)
 892 {
 893         struct ath_vif *avp = (void *)vif->drv_priv;
 894
 895         if (bss_conf->assoc) {
 896                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
 897                         bss_conf->aid, sc->curbssid);
 898
 899                 /* New association, store aid */
 900                 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
 901                         sc->curaid = bss_conf->aid;
 902                         ath9k_hw_write_associd(sc);
 903                 }
 904
 905                 /* Configure the beacon */
 906                 ath_beacon_config(sc, vif);
 907
 908                 /* Reset rssi stats */
 909                 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
 910                 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
 911                 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
 912                 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
 913
 914                 /* Start ANI */
 915                 mod_timer(&sc->ani.timer,
 916                           jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
 917         } else {
 918                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
 919                 sc->curaid = 0;
 920         }
 921 }
 922
 923 /********************************/
 924 /*       LED functions          */
 925 /********************************/
 926
 927 static void ath_led_blink_work(struct work_struct *work)
 928 {
 929         struct ath_softc *sc = container_of(work, struct ath_softc,
 930                                             ath_led_blink_work.work);
 931
 932         if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
 933                 return;
 934
 935         if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
 936             (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
 937                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
 938         else
 939                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
 940                                   (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
 941
 942         queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
 943                            (sc->sc_flags & SC_OP_LED_ON) ?
 944                            msecs_to_jiffies(sc->led_off_duration) :
 945                            msecs_to_jiffies(sc->led_on_duration));
 946
 947         sc->led_on_duration = sc->led_on_cnt ?
 948                         max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
 949                         ATH_LED_ON_DURATION_IDLE;
 950         sc->led_off_duration = sc->led_off_cnt ?
 951                         max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
 952                         ATH_LED_OFF_DURATION_IDLE;
 953         sc->led_on_cnt = sc->led_off_cnt = 0;
 954         if (sc->sc_flags & SC_OP_LED_ON)
 955                 sc->sc_flags &= ~SC_OP_LED_ON;
 956         else
 957                 sc->sc_flags |= SC_OP_LED_ON;
 958 }
 959
 960 static void ath_led_brightness(struct led_classdev *led_cdev,
 961                                enum led_brightness brightness)
 962 {
 963         struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
 964         struct ath_softc *sc = led->sc;
 965
 966         switch (brightness) {
 967         case LED_OFF:
 968                 if (led->led_type == ATH_LED_ASSOC ||
 969                     led->led_type == ATH_LED_RADIO) {
 970                         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
 971                                 (led->led_type == ATH_LED_RADIO));
 972                         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
 973                         if (led->led_type == ATH_LED_RADIO)
 974                                 sc->sc_flags &= ~SC_OP_LED_ON;
 975                 } else {
 976                         sc->led_off_cnt++;
 977                 }
 978                 break;
 979         case LED_FULL:
 980                 if (led->led_type == ATH_LED_ASSOC) {
 981                         sc->sc_flags |= SC_OP_LED_ASSOCIATED;
 982                         queue_delayed_work(sc->hw->workqueue,
 983                                            &sc->ath_led_blink_work, 0);
 984                 } else if (led->led_type == ATH_LED_RADIO) {
 985                         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
 986                         sc->sc_flags |= SC_OP_LED_ON;
 987                 } else {
 988                         sc->led_on_cnt++;
 989                 }
 990                 break;
 991         default:
 992                 break;
 993         }
 994 }
 995
 996 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
 997                             char *trigger)
 998 {
 999         int ret;
1000
1001         led->sc = sc;
1002         led->led_cdev.name = led->name;
1003         led->led_cdev.default_trigger = trigger;
1004         led->led_cdev.brightness_set = ath_led_brightness;
1005
1006         ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1007         if (ret)
1008                 DPRINTF(sc, ATH_DBG_FATAL,
1009                         "Failed to register led:%s", led->name);
1010         else
1011                 led->registered = 1;
1012         return ret;
1013 }
1014
1015 static void ath_unregister_led(struct ath_led *led)
1016 {
1017         if (led->registered) {
1018                 led_classdev_unregister(&led->led_cdev);
1019                 led->registered = 0;
1020         }
1021 }
1022
1023 static void ath_deinit_leds(struct ath_softc *sc)
1024 {
1025         cancel_delayed_work_sync(&sc->ath_led_blink_work);
1026         ath_unregister_led(&sc->assoc_led);
1027         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1028         ath_unregister_led(&sc->tx_led);
1029         ath_unregister_led(&sc->rx_led);
1030         ath_unregister_led(&sc->radio_led);
1031         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1032 }
1033
1034 static void ath_init_leds(struct ath_softc *sc)
1035 {
1036         char *trigger;
1037         int ret;
1038
1039         /* Configure gpio 1 for output */
1040         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1041                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1042         /* LED off, active low */
1043         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1044
1045         INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1046
1047         trigger = ieee80211_get_radio_led_name(sc->hw);
1048         snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1049                 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1050         ret = ath_register_led(sc, &sc->radio_led, trigger);
1051         sc->radio_led.led_type = ATH_LED_RADIO;
1052         if (ret)
1053                 goto fail;
1054
1055         trigger = ieee80211_get_assoc_led_name(sc->hw);
1056         snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1057                 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1058         ret = ath_register_led(sc, &sc->assoc_led, trigger);
1059         sc->assoc_led.led_type = ATH_LED_ASSOC;
1060         if (ret)
1061                 goto fail;
1062
1063         trigger = ieee80211_get_tx_led_name(sc->hw);
1064         snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1065                 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1066         ret = ath_register_led(sc, &sc->tx_led, trigger);
1067         sc->tx_led.led_type = ATH_LED_TX;
1068         if (ret)
1069                 goto fail;
1070
1071         trigger = ieee80211_get_rx_led_name(sc->hw);
1072         snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1073                 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1074         ret = ath_register_led(sc, &sc->rx_led, trigger);
1075         sc->rx_led.led_type = ATH_LED_RX;
1076         if (ret)
1077                 goto fail;
1078
1079         return;
1080
1081 fail:
1082         ath_deinit_leds(sc);
1083 }
1084
1085 void ath_radio_enable(struct ath_softc *sc)
1086 {
1087         struct ath_hw *ah = sc->sc_ah;
1088         struct ieee80211_channel *channel = sc->hw->conf.channel;
1089         int r;
1090
1091         ath9k_ps_wakeup(sc);
1092         spin_lock_bh(&sc->sc_resetlock);
1093
1094         r = ath9k_hw_reset(ah, ah->curchan, false);
1095
1096         if (r) {
1097                 DPRINTF(sc, ATH_DBG_FATAL,
1098                         "Unable to reset channel %u (%uMhz) ",
1099                         "reset status %u\n",
1100                         channel->center_freq, r);
1101         }
1102         spin_unlock_bh(&sc->sc_resetlock);
1103
1104         ath_update_txpow(sc);
1105         if (ath_startrecv(sc) != 0) {
1106                 DPRINTF(sc, ATH_DBG_FATAL,
1107                         "Unable to restart recv logic\n");
1108                 return;
1109         }
1110
1111         if (sc->sc_flags & SC_OP_BEACONS)
1112                 ath_beacon_config(sc, NULL);    /* restart beacons */
1113
1114         /* Re-Enable  interrupts */
1115         ath9k_hw_set_interrupts(ah, sc->imask);
1116
1117         /* Enable LED */
1118         ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1119                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1120         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1121
1122         ieee80211_wake_queues(sc->hw);
1123         ath9k_ps_restore(sc);
1124 }
1125
1126 void ath_radio_disable(struct ath_softc *sc)
1127 {
1128         struct ath_hw *ah = sc->sc_ah;
1129         struct ieee80211_channel *channel = sc->hw->conf.channel;
1130         int r;
1131
1132         ath9k_ps_wakeup(sc);
1133         ieee80211_stop_queues(sc->hw);
1134
1135         /* Disable LED */
1136         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1137         ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1138
1139         /* Disable interrupts */
1140         ath9k_hw_set_interrupts(ah, 0);
1141
1142         ath_drain_all_txq(sc, false);   /* clear pending tx frames */
1143         ath_stoprecv(sc);               /* turn off frame recv */
1144         ath_flushrecv(sc);              /* flush recv queue */
1145
1146         spin_lock_bh(&sc->sc_resetlock);
1147         r = ath9k_hw_reset(ah, ah->curchan, false);
1148         if (r) {
1149                 DPRINTF(sc, ATH_DBG_FATAL,
1150                         "Unable to reset channel %u (%uMhz) "
1151                         "reset status %u\n",
1152                         channel->center_freq, r);
1153         }
1154         spin_unlock_bh(&sc->sc_resetlock);
1155
1156         ath9k_hw_phy_disable(ah);
1157         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1158         ath9k_ps_restore(sc);
1159 }
1160
1161 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1162
1163 /*******************/
1164 /*      Rfkill     */
1165 /*******************/
1166
1167 static bool ath_is_rfkill_set(struct ath_softc *sc)
1168 {
1169         struct ath_hw *ah = sc->sc_ah;
1170
1171         return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1172                                   ah->rfkill_polarity;
1173 }
1174
1175 /* h/w rfkill poll function */
1176 static void ath_rfkill_poll(struct work_struct *work)
1177 {
1178         struct ath_softc *sc = container_of(work, struct ath_softc,
1179                                             rf_kill.rfkill_poll.work);
1180         bool radio_on;
1181
1182         if (sc->sc_flags & SC_OP_INVALID)
1183                 return;
1184
1185         radio_on = !ath_is_rfkill_set(sc);
1186
1187         /*
1188          * enable/disable radio only when there is a
1189          * state change in RF switch
1190          */
1191         if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1192                 enum rfkill_state state;
1193
1194                 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1195                         state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1196                                 : RFKILL_STATE_HARD_BLOCKED;
1197                 } else if (radio_on) {
1198                         ath_radio_enable(sc);
1199                         state = RFKILL_STATE_UNBLOCKED;
1200                 } else {
1201                         ath_radio_disable(sc);
1202                         state = RFKILL_STATE_HARD_BLOCKED;
1203                 }
1204
1205                 if (state == RFKILL_STATE_HARD_BLOCKED)
1206                         sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1207                 else
1208                         sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1209
1210                 rfkill_force_state(sc->rf_kill.rfkill, state);
1211         }
1212
1213         queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1214                            msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1215 }
1216
1217 /* s/w rfkill handler */
1218 static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1219 {
1220         struct ath_softc *sc = data;
1221
1222         switch (state) {
1223         case RFKILL_STATE_SOFT_BLOCKED:
1224                 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1225                     SC_OP_RFKILL_SW_BLOCKED)))
1226                         ath_radio_disable(sc);
1227                 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1228                 return 0;
1229         case RFKILL_STATE_UNBLOCKED:
1230                 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1231                         sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1232                         if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1233                                 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
1234                                         "radio as it is disabled by h/w\n");
1235                                 return -EPERM;
1236                         }
1237                         ath_radio_enable(sc);
1238                 }
1239                 return 0;
1240         default:
1241                 return -EINVAL;
1242         }
1243 }
1244
1245 /* Init s/w rfkill */
1246 static int ath_init_sw_rfkill(struct ath_softc *sc)
1247 {
1248         sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1249                                              RFKILL_TYPE_WLAN);
1250         if (!sc->rf_kill.rfkill) {
1251                 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1252                 return -ENOMEM;
1253         }
1254
1255         snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1256                 "ath9k-%s::rfkill", wiphy_name(sc->hw->wiphy));
1257         sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1258         sc->rf_kill.rfkill->data = sc;
1259         sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1260         sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1261
1262         return 0;
1263 }
1264
1265 /* Deinitialize rfkill */
1266 static void ath_deinit_rfkill(struct ath_softc *sc)
1267 {
1268         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1269                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1270
1271         if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1272                 rfkill_unregister(sc->rf_kill.rfkill);
1273                 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1274                 sc->rf_kill.rfkill = NULL;
1275         }
1276 }
1277
1278 static int ath_start_rfkill_poll(struct ath_softc *sc)
1279 {
1280         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1281                 queue_delayed_work(sc->hw->workqueue,
1282                                    &sc->rf_kill.rfkill_poll, 0);
1283
1284         if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1285                 if (rfkill_register(sc->rf_kill.rfkill)) {
1286                         DPRINTF(sc, ATH_DBG_FATAL,
1287                                 "Unable to register rfkill\n");
1288                         rfkill_free(sc->rf_kill.rfkill);
1289
1290                         /* Deinitialize the device */
1291                         ath_cleanup(sc);
1292                         return -EIO;
1293                 } else {
1294                         sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1295                 }
1296         }
1297
1298         return 0;
1299 }
1300 #endif /* CONFIG_RFKILL */
1301
1302 void ath_cleanup(struct ath_softc *sc)
1303 {
1304         ath_detach(sc);
1305         free_irq(sc->irq, sc);
1306         ath_bus_cleanup(sc);
1307         kfree(sc->sec_wiphy);
1308         ieee80211_free_hw(sc->hw);
1309 }
1310
1311 void ath_detach(struct ath_softc *sc)
1312 {
1313         struct ieee80211_hw *hw = sc->hw;
1314         int i = 0;
1315
1316         ath9k_ps_wakeup(sc);
1317
1318         DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1319
1320 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1321         ath_deinit_rfkill(sc);
1322 #endif
1323         ath_deinit_leds(sc);
1324         cancel_work_sync(&sc->chan_work);
1325         cancel_delayed_work_sync(&sc->wiphy_work);
1326
1327         for (i = 0; i < sc->num_sec_wiphy; i++) {
1328                 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1329                 if (aphy == NULL)
1330                         continue;
1331                 sc->sec_wiphy[i] = NULL;
1332                 ieee80211_unregister_hw(aphy->hw);
1333                 ieee80211_free_hw(aphy->hw);
1334         }
1335         ieee80211_unregister_hw(hw);
1336         ath_rx_cleanup(sc);
1337         ath_tx_cleanup(sc);
1338
1339         tasklet_kill(&sc->intr_tq);
1340         tasklet_kill(&sc->bcon_tasklet);
1341
1342         if (!(sc->sc_flags & SC_OP_INVALID))
1343                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1344
1345         /* cleanup tx queues */
1346         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1347                 if (ATH_TXQ_SETUP(sc, i))
1348                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1349
1350         ath9k_hw_detach(sc->sc_ah);
1351         ath9k_exit_debug(sc);
1352         ath9k_ps_restore(sc);
1353 }
1354
1355 static int ath_init(u16 devid, struct ath_softc *sc)
1356 {
1357         struct ath_hw *ah = NULL;
1358         int status;
1359         int error = 0, i;
1360         int csz = 0;
1361
1362         /* XXX: hardware will not be ready until ath_open() being called */
1363         sc->sc_flags |= SC_OP_INVALID;
1364
1365         if (ath9k_init_debug(sc) < 0)
1366                 printk(KERN_ERR "Unable to create debugfs files\n");
1367
1368         spin_lock_init(&sc->wiphy_lock);
1369         spin_lock_init(&sc->sc_resetlock);
1370         spin_lock_init(&sc->sc_serial_rw);
1371         mutex_init(&sc->mutex);
1372         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1373         tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
1374                      (unsigned long)sc);
1375
1376         /*
1377          * Cache line size is used to size and align various
1378          * structures used to communicate with the hardware.
1379          */
1380         ath_read_cachesize(sc, &csz);
1381         /* XXX assert csz is non-zero */
1382         sc->cachelsz = csz << 2;        /* convert to bytes */
1383
1384         ah = ath9k_hw_attach(devid, sc, &status);
1385         if (ah == NULL) {
1386                 DPRINTF(sc, ATH_DBG_FATAL,
1387                         "Unable to attach hardware; HAL status %d\n", status);
1388                 error = -ENXIO;
1389                 goto bad;
1390         }
1391         sc->sc_ah = ah;
1392
1393         /* Get the hardware key cache size. */
1394         sc->keymax = ah->caps.keycache_size;
1395         if (sc->keymax > ATH_KEYMAX) {
1396                 DPRINTF(sc, ATH_DBG_ANY,
1397                         "Warning, using only %u entries in %u key cache\n",
1398                         ATH_KEYMAX, sc->keymax);
1399                 sc->keymax = ATH_KEYMAX;
1400         }
1401
1402         /*
1403          * Reset the key cache since some parts do not
1404          * reset the contents on initial power up.
1405          */
1406         for (i = 0; i < sc->keymax; i++)
1407                 ath9k_hw_keyreset(ah, (u16) i);
1408
1409         if (ath9k_regd_init(sc->sc_ah))
1410                 goto bad;
1411
1412         /* default to MONITOR mode */
1413         sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1414
1415         /* Setup rate tables */
1416
1417         ath_rate_attach(sc);
1418         ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1419         ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1420
1421         /*
1422          * Allocate hardware transmit queues: one queue for
1423          * beacon frames and one data queue for each QoS
1424          * priority.  Note that the hal handles reseting
1425          * these queues at the needed time.
1426          */
1427         sc->beacon.beaconq = ath_beaconq_setup(ah);
1428         if (sc->beacon.beaconq == -1) {
1429                 DPRINTF(sc, ATH_DBG_FATAL,
1430                         "Unable to setup a beacon xmit queue\n");
1431                 error = -EIO;
1432                 goto bad2;
1433         }
1434         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1435         if (sc->beacon.cabq == NULL) {
1436                 DPRINTF(sc, ATH_DBG_FATAL,
1437                         "Unable to setup CAB xmit queue\n");
1438                 error = -EIO;
1439                 goto bad2;
1440         }
1441
1442         sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1443         ath_cabq_update(sc);
1444
1445         for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1446                 sc->tx.hwq_map[i] = -1;
1447
1448         /* Setup data queues */
1449         /* NB: ensure BK queue is the lowest priority h/w queue */
1450         if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1451                 DPRINTF(sc, ATH_DBG_FATAL,
1452                         "Unable to setup xmit queue for BK traffic\n");
1453                 error = -EIO;
1454                 goto bad2;
1455         }
1456
1457         if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1458                 DPRINTF(sc, ATH_DBG_FATAL,
1459                         "Unable to setup xmit queue for BE traffic\n");
1460                 error = -EIO;
1461                 goto bad2;
1462         }
1463         if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1464                 DPRINTF(sc, ATH_DBG_FATAL,
1465                         "Unable to setup xmit queue for VI traffic\n");
1466                 error = -EIO;
1467                 goto bad2;
1468         }
1469         if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1470                 DPRINTF(sc, ATH_DBG_FATAL,
1471                         "Unable to setup xmit queue for VO traffic\n");
1472                 error = -EIO;
1473                 goto bad2;
1474         }
1475
1476         /* Initializes the noise floor to a reasonable default value.
1477          * Later on this will be updated during ANI processing. */
1478
1479         sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1480         setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1481
1482         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1483                                    ATH9K_CIPHER_TKIP, NULL)) {
1484                 /*
1485                  * Whether we should enable h/w TKIP MIC.
1486                  * XXX: if we don't support WME TKIP MIC, then we wouldn't
1487                  * report WMM capable, so it's always safe to turn on
1488                  * TKIP MIC in this case.
1489                  */
1490                 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1491                                        0, 1, NULL);
1492         }
1493
1494         /*
1495          * Check whether the separate key cache entries
1496          * are required to handle both tx+rx MIC keys.
1497          * With split mic keys the number of stations is limited
1498          * to 27 otherwise 59.
1499          */
1500         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1501                                    ATH9K_CIPHER_TKIP, NULL)
1502             && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1503                                       ATH9K_CIPHER_MIC, NULL)
1504             && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1505                                       0, NULL))
1506                 sc->splitmic = 1;
1507
1508         /* turn on mcast key search if possible */
1509         if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1510                 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1511                                              1, NULL);
1512
1513         sc->config.txpowlimit = ATH_TXPOWER_MAX;
1514
1515         /* 11n Capabilities */
1516         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1517                 sc->sc_flags |= SC_OP_TXAGGR;
1518                 sc->sc_flags |= SC_OP_RXAGGR;
1519         }
1520
1521         sc->tx_chainmask = ah->caps.tx_chainmask;
1522         sc->rx_chainmask = ah->caps.rx_chainmask;
1523
1524         ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1525         sc->rx.defant = ath9k_hw_getdefantenna(ah);
1526
1527         if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1528                 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
1529
1530         sc->beacon.slottime = ATH9K_SLOT_TIME_9;        /* default to short slot time */
1531
1532         /* initialize beacon slots */
1533         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1534                 sc->beacon.bslot[i] = NULL;
1535                 sc->beacon.bslot_aphy[i] = NULL;
1536         }
1537
1538         /* setup channels and rates */
1539
1540         sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1541         sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1542                 sc->rates[IEEE80211_BAND_2GHZ];
1543         sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1544         sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1545                 ARRAY_SIZE(ath9k_2ghz_chantable);
1546
1547         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1548                 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1549                 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1550                         sc->rates[IEEE80211_BAND_5GHZ];
1551                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1552                 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1553                         ARRAY_SIZE(ath9k_5ghz_chantable);
1554         }
1555
1556         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1557                 ath9k_hw_btcoex_enable(sc->sc_ah);
1558
1559         return 0;
1560 bad2:
1561         /* cleanup tx queues */
1562         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1563                 if (ATH_TXQ_SETUP(sc, i))
1564                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1565 bad:
1566         if (ah)
1567                 ath9k_hw_detach(ah);
1568         ath9k_exit_debug(sc);
1569
1570         return error;
1571 }
1572
1573 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1574 {
1575         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1576                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1577                 IEEE80211_HW_SIGNAL_DBM |
1578                 IEEE80211_HW_AMPDU_AGGREGATION |
1579                 IEEE80211_HW_SUPPORTS_PS |
1580                 IEEE80211_HW_PS_NULLFUNC_STACK |
1581                 IEEE80211_HW_SPECTRUM_MGMT;
1582
1583         if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1584                 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1585
1586         hw->wiphy->interface_modes =
1587                 BIT(NL80211_IFTYPE_AP) |
1588                 BIT(NL80211_IFTYPE_STATION) |
1589                 BIT(NL80211_IFTYPE_ADHOC) |
1590                 BIT(NL80211_IFTYPE_MESH_POINT);
1591
1592         hw->wiphy->reg_notifier = ath9k_reg_notifier;
1593         hw->wiphy->strict_regulatory = true;
1594
1595         hw->queues = 4;
1596         hw->max_rates = 4;
1597         hw->channel_change_time = 5000;
1598         hw->max_listen_interval = 10;
1599         hw->max_rate_tries = ATH_11N_TXMAXTRY;
1600         hw->sta_data_size = sizeof(struct ath_node);
1601         hw->vif_data_size = sizeof(struct ath_vif);
1602
1603         hw->rate_control_algorithm = "ath9k_rate_control";
1604
1605         hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1606                 &sc->sbands[IEEE80211_BAND_2GHZ];
1607         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1608                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1609                         &sc->sbands[IEEE80211_BAND_5GHZ];
1610 }
1611
1612 int ath_attach(u16 devid, struct ath_softc *sc)
1613 {
1614         struct ieee80211_hw *hw = sc->hw;
1615         const struct ieee80211_regdomain *regd;
1616         int error = 0, i;
1617
1618         DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1619
1620         error = ath_init(devid, sc);
1621         if (error != 0)
1622                 return error;
1623
1624         /* get mac address from hardware and set in mac80211 */
1625
1626         SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1627
1628         ath_set_hw_capab(sc, hw);
1629
1630         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1631                 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1632                 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1633                         setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1634         }
1635
1636         /* initialize tx/rx engine */
1637         error = ath_tx_init(sc, ATH_TXBUF);
1638         if (error != 0)
1639                 goto error_attach;
1640
1641         error = ath_rx_init(sc, ATH_RXBUF);
1642         if (error != 0)
1643                 goto error_attach;
1644
1645 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1646         /* Initialze h/w Rfkill */
1647         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1648                 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1649
1650         /* Initialize s/w rfkill */
1651         error = ath_init_sw_rfkill(sc);
1652         if (error)
1653                 goto error_attach;
1654 #endif
1655
1656         if (ath9k_is_world_regd(sc->sc_ah)) {
1657                 /* Anything applied here (prior to wiphy registration) gets
1658                  * saved on the wiphy orig_* parameters */
1659                 regd = ath9k_world_regdomain(sc->sc_ah);
1660                 hw->wiphy->custom_regulatory = true;
1661                 hw->wiphy->strict_regulatory = false;
1662         } else {
1663                 /* This gets applied in the case of the absense of CRDA,
1664                  * it's our own custom world regulatory domain, similar to
1665                  * cfg80211's but we enable passive scanning */
1666                 regd = ath9k_default_world_regdomain();
1667         }
1668         wiphy_apply_custom_regulatory(hw->wiphy, regd);
1669         ath9k_reg_apply_radar_flags(hw->wiphy);
1670         ath9k_reg_apply_world_flags(hw->wiphy, NL80211_REGDOM_SET_BY_DRIVER);
1671
1672         INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1673         INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1674         sc->wiphy_scheduler_int = msecs_to_jiffies(500);
1675
1676         error = ieee80211_register_hw(hw);
1677
1678         if (!ath9k_is_world_regd(sc->sc_ah)) {
1679                 error = regulatory_hint(hw->wiphy,
1680                         sc->sc_ah->regulatory.alpha2);
1681                 if (error)
1682                         goto error_attach;
1683         }
1684
1685         /* Initialize LED control */
1686         ath_init_leds(sc);
1687
1688
1689         return 0;
1690
1691 error_attach:
1692         /* cleanup tx queues */
1693         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1694                 if (ATH_TXQ_SETUP(sc, i))
1695                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1696
1697         ath9k_hw_detach(sc->sc_ah);
1698         ath9k_exit_debug(sc);
1699
1700         return error;
1701 }
1702
1703 int ath_reset(struct ath_softc *sc, bool retry_tx)
1704 {
1705         struct ath_hw *ah = sc->sc_ah;
1706         struct ieee80211_hw *hw = sc->hw;
1707         int r;
1708
1709         ath9k_hw_set_interrupts(ah, 0);
1710         ath_drain_all_txq(sc, retry_tx);
1711         ath_stoprecv(sc);
1712         ath_flushrecv(sc);
1713
1714         spin_lock_bh(&sc->sc_resetlock);
1715         r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1716         if (r)
1717                 DPRINTF(sc, ATH_DBG_FATAL,
1718                         "Unable to reset hardware; reset status %u\n", r);
1719         spin_unlock_bh(&sc->sc_resetlock);
1720
1721         if (ath_startrecv(sc) != 0)
1722                 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1723
1724         /*
1725          * We may be doing a reset in response to a request
1726          * that changes the channel so update any state that
1727          * might change as a result.
1728          */
1729         ath_cache_conf_rate(sc, &hw->conf);
1730
1731         ath_update_txpow(sc);
1732
1733         if (sc->sc_flags & SC_OP_BEACONS)
1734                 ath_beacon_config(sc, NULL);    /* restart beacons */
1735
1736         ath9k_hw_set_interrupts(ah, sc->imask);
1737
1738         if (retry_tx) {
1739                 int i;
1740                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1741                         if (ATH_TXQ_SETUP(sc, i)) {
1742                                 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1743                                 ath_txq_schedule(sc, &sc->tx.txq[i]);
1744                                 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1745                         }
1746                 }
1747         }
1748
1749         return r;
1750 }
1751
1752 /*
1753  *  This function will allocate both the DMA descriptor structure, and the
1754  *  buffers it contains.  These are used to contain the descriptors used
1755  *  by the system.
1756 */
1757 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1758                       struct list_head *head, const char *name,
1759                       int nbuf, int ndesc)
1760 {
1761 #define DS2PHYS(_dd, _ds)                                               \
1762         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1763 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1764 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1765
1766         struct ath_desc *ds;
1767         struct ath_buf *bf;
1768         int i, bsize, error;
1769
1770         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1771                 name, nbuf, ndesc);
1772
1773         INIT_LIST_HEAD(head);
1774         /* ath_desc must be a multiple of DWORDs */
1775         if ((sizeof(struct ath_desc) % 4) != 0) {
1776                 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1777                 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1778                 error = -ENOMEM;
1779                 goto fail;
1780         }
1781
1782         dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1783
1784         /*
1785          * Need additional DMA memory because we can't use
1786          * descriptors that cross the 4K page boundary. Assume
1787          * one skipped descriptor per 4K page.
1788          */
1789         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1790                 u32 ndesc_skipped =
1791                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1792                 u32 dma_len;
1793
1794                 while (ndesc_skipped) {
1795                         dma_len = ndesc_skipped * sizeof(struct ath_desc);
1796                         dd->dd_desc_len += dma_len;
1797
1798                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1799                 };
1800         }
1801
1802         /* allocate descriptors */
1803         dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1804                                          &dd->dd_desc_paddr, GFP_KERNEL);
1805         if (dd->dd_desc == NULL) {
1806                 error = -ENOMEM;
1807                 goto fail;
1808         }
1809         ds = dd->dd_desc;
1810         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1811                 name, ds, (u32) dd->dd_desc_len,
1812                 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1813
1814         /* allocate buffers */
1815         bsize = sizeof(struct ath_buf) * nbuf;
1816         bf = kzalloc(bsize, GFP_KERNEL);
1817         if (bf == NULL) {
1818                 error = -ENOMEM;
1819                 goto fail2;
1820         }
1821         dd->dd_bufptr = bf;
1822
1823         for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1824                 bf->bf_desc = ds;
1825                 bf->bf_daddr = DS2PHYS(dd, ds);
1826
1827                 if (!(sc->sc_ah->caps.hw_caps &
1828                       ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1829                         /*
1830                          * Skip descriptor addresses which can cause 4KB
1831                          * boundary crossing (addr + length) with a 32 dword
1832                          * descriptor fetch.
1833                          */
1834                         while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1835                                 ASSERT((caddr_t) bf->bf_desc <
1836                                        ((caddr_t) dd->dd_desc +
1837                                         dd->dd_desc_len));
1838
1839                                 ds += ndesc;
1840                                 bf->bf_desc = ds;
1841                                 bf->bf_daddr = DS2PHYS(dd, ds);
1842                         }
1843                 }
1844                 list_add_tail(&bf->list, head);
1845         }
1846         return 0;
1847 fail2:
1848         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1849                           dd->dd_desc_paddr);
1850 fail:
1851         memset(dd, 0, sizeof(*dd));
1852         return error;
1853 #undef ATH_DESC_4KB_BOUND_CHECK
1854 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1855 #undef DS2PHYS
1856 }
1857
1858 void ath_descdma_cleanup(struct ath_softc *sc,
1859                          struct ath_descdma *dd,
1860                          struct list_head *head)
1861 {
1862         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1863                           dd->dd_desc_paddr);
1864
1865         INIT_LIST_HEAD(head);
1866         kfree(dd->dd_bufptr);
1867         memset(dd, 0, sizeof(*dd));
1868 }
1869
1870 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1871 {
1872         int qnum;
1873
1874         switch (queue) {
1875         case 0:
1876                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1877                 break;
1878         case 1:
1879                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1880                 break;
1881         case 2:
1882                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1883                 break;
1884         case 3:
1885                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1886                 break;
1887         default:
1888                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1889                 break;
1890         }
1891
1892         return qnum;
1893 }
1894
1895 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1896 {
1897         int qnum;
1898
1899         switch (queue) {
1900         case ATH9K_WME_AC_VO:
1901                 qnum = 0;
1902                 break;
1903         case ATH9K_WME_AC_VI:
1904                 qnum = 1;
1905                 break;
1906         case ATH9K_WME_AC_BE:
1907                 qnum = 2;
1908                 break;
1909         case ATH9K_WME_AC_BK:
1910                 qnum = 3;
1911                 break;
1912         default:
1913                 qnum = -1;
1914                 break;
1915         }
1916
1917         return qnum;
1918 }
1919
1920 /* XXX: Remove me once we don't depend on ath9k_channel for all
1921  * this redundant data */
1922 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1923                            struct ath9k_channel *ichan)
1924 {
1925         struct ieee80211_channel *chan = hw->conf.channel;
1926         struct ieee80211_conf *conf = &hw->conf;
1927
1928         ichan->channel = chan->center_freq;
1929         ichan->chan = chan;
1930
1931         if (chan->band == IEEE80211_BAND_2GHZ) {
1932                 ichan->chanmode = CHANNEL_G;
1933                 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1934         } else {
1935                 ichan->chanmode = CHANNEL_A;
1936                 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1937         }
1938
1939         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1940
1941         if (conf_is_ht(conf)) {
1942                 if (conf_is_ht40(conf))
1943                         sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1944
1945                 ichan->chanmode = ath_get_extchanmode(sc, chan,
1946                                             conf->channel_type);
1947         }
1948 }
1949
1950 /**********************/
1951 /* mac80211 callbacks */
1952 /**********************/
1953
1954 static int ath9k_start(struct ieee80211_hw *hw)
1955 {
1956         struct ath_wiphy *aphy = hw->priv;
1957         struct ath_softc *sc = aphy->sc;
1958         struct ieee80211_channel *curchan = hw->conf.channel;
1959         struct ath9k_channel *init_channel;
1960         int r, pos;
1961
1962         DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1963                 "initial channel: %d MHz\n", curchan->center_freq);
1964
1965         mutex_lock(&sc->mutex);
1966
1967         if (ath9k_wiphy_started(sc)) {
1968                 if (sc->chan_idx == curchan->hw_value) {
1969                         /*
1970                          * Already on the operational channel, the new wiphy
1971                          * can be marked active.
1972                          */
1973                         aphy->state = ATH_WIPHY_ACTIVE;
1974                         ieee80211_wake_queues(hw);
1975                 } else {
1976                         /*
1977                          * Another wiphy is on another channel, start the new
1978                          * wiphy in paused state.
1979                          */
1980                         aphy->state = ATH_WIPHY_PAUSED;
1981                         ieee80211_stop_queues(hw);
1982                 }
1983                 mutex_unlock(&sc->mutex);
1984                 return 0;
1985         }
1986         aphy->state = ATH_WIPHY_ACTIVE;
1987
1988         /* setup initial channel */
1989
1990         pos = curchan->hw_value;
1991
1992         sc->chan_idx = pos;
1993         init_channel = &sc->sc_ah->channels[pos];
1994         ath9k_update_ichannel(sc, hw, init_channel);
1995
1996         /* Reset SERDES registers */
1997         ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1998
1999         /*
2000          * The basic interface to setting the hardware in a good
2001          * state is ``reset''.  On return the hardware is known to
2002          * be powered up and with interrupts disabled.  This must
2003          * be followed by initialization of the appropriate bits
2004          * and then setup of the interrupt mask.
2005          */
2006         spin_lock_bh(&sc->sc_resetlock);
2007         r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
2008         if (r) {
2009                 DPRINTF(sc, ATH_DBG_FATAL,
2010                         "Unable to reset hardware; reset status %u "
2011                         "(freq %u MHz)\n", r,
2012                         curchan->center_freq);
2013                 spin_unlock_bh(&sc->sc_resetlock);
2014                 goto mutex_unlock;
2015         }
2016         spin_unlock_bh(&sc->sc_resetlock);
2017
2018         /*
2019          * This is needed only to setup initial state
2020          * but it's best done after a reset.
2021          */
2022         ath_update_txpow(sc);
2023
2024         /*
2025          * Setup the hardware after reset:
2026          * The receive engine is set going.
2027          * Frame transmit is handled entirely
2028          * in the frame output path; there's nothing to do
2029          * here except setup the interrupt mask.
2030          */
2031         if (ath_startrecv(sc) != 0) {
2032                 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
2033                 r = -EIO;
2034                 goto mutex_unlock;
2035         }
2036
2037         /* Setup our intr mask. */
2038         sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
2039                 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2040                 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2041
2042         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
2043                 sc->imask |= ATH9K_INT_GTT;
2044
2045         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2046                 sc->imask |= ATH9K_INT_CST;
2047
2048         ath_cache_conf_rate(sc, &hw->conf);
2049
2050         sc->sc_flags &= ~SC_OP_INVALID;
2051
2052         /* Disable BMISS interrupt when we're not associated */
2053         sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2054         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2055
2056         ieee80211_wake_queues(hw);
2057
2058 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2059         r = ath_start_rfkill_poll(sc);
2060 #endif
2061
2062 mutex_unlock:
2063         mutex_unlock(&sc->mutex);
2064
2065         return r;
2066 }
2067
2068 static int ath9k_tx(struct ieee80211_hw *hw,
2069                     struct sk_buff *skb)
2070 {
2071         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2072         struct ath_wiphy *aphy = hw->priv;
2073         struct ath_softc *sc = aphy->sc;
2074         struct ath_tx_control txctl;
2075         int hdrlen, padsize;
2076
2077         if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
2078                 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
2079                        "%d\n", wiphy_name(hw->wiphy), aphy->state);
2080                 goto exit;
2081         }
2082
2083         memset(&txctl, 0, sizeof(struct ath_tx_control));
2084
2085         /*
2086          * As a temporary workaround, assign seq# here; this will likely need
2087          * to be cleaned up to work better with Beacon transmission and virtual
2088          * BSSes.
2089          */
2090         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2091                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2092                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2093                         sc->tx.seq_no += 0x10;
2094                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2095                 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2096         }
2097
2098         /* Add the padding after the header if this is not already done */
2099         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2100         if (hdrlen & 3) {
2101                 padsize = hdrlen % 4;
2102                 if (skb_headroom(skb) < padsize)
2103                         return -1;
2104                 skb_push(skb, padsize);
2105                 memmove(skb->data, skb->data + padsize, hdrlen);
2106         }
2107
2108         /* Check if a tx queue is available */
2109
2110         txctl.txq = ath_test_get_txq(sc, skb);
2111         if (!txctl.txq)
2112                 goto exit;
2113
2114         DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2115
2116         if (ath_tx_start(hw, skb, &txctl) != 0) {
2117                 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2118                 goto exit;
2119         }
2120
2121         return 0;
2122 exit:
2123         dev_kfree_skb_any(skb);
2124         return 0;
2125 }
2126
2127 static void ath9k_stop(struct ieee80211_hw *hw)
2128 {
2129         struct ath_wiphy *aphy = hw->priv;
2130         struct ath_softc *sc = aphy->sc;
2131
2132         aphy->state = ATH_WIPHY_INACTIVE;
2133
2134         if (sc->sc_flags & SC_OP_INVALID) {
2135                 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2136                 return;
2137         }
2138
2139         mutex_lock(&sc->mutex);
2140
2141         ieee80211_stop_queues(hw);
2142
2143         if (ath9k_wiphy_started(sc)) {
2144                 mutex_unlock(&sc->mutex);
2145                 return; /* another wiphy still in use */
2146         }
2147
2148         /* make sure h/w will not generate any interrupt
2149          * before setting the invalid flag. */
2150         ath9k_hw_set_interrupts(sc->sc_ah, 0);
2151
2152         if (!(sc->sc_flags & SC_OP_INVALID)) {
2153                 ath_drain_all_txq(sc, false);
2154                 ath_stoprecv(sc);
2155                 ath9k_hw_phy_disable(sc->sc_ah);
2156         } else
2157                 sc->rx.rxlink = NULL;
2158
2159 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2160         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2161                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2162 #endif
2163         /* disable HAL and put h/w to sleep */
2164         ath9k_hw_disable(sc->sc_ah);
2165         ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2166
2167         sc->sc_flags |= SC_OP_INVALID;
2168
2169         mutex_unlock(&sc->mutex);
2170
2171         DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2172 }
2173
2174 static int ath9k_add_interface(struct ieee80211_hw *hw,
2175                                struct ieee80211_if_init_conf *conf)
2176 {
2177         struct ath_wiphy *aphy = hw->priv;
2178         struct ath_softc *sc = aphy->sc;
2179         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2180         enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2181         int ret = 0;
2182
2183         mutex_lock(&sc->mutex);
2184
2185         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2186             sc->nvifs > 0) {
2187                 ret = -ENOBUFS;
2188                 goto out;
2189         }
2190
2191         switch (conf->type) {
2192         case NL80211_IFTYPE_STATION:
2193                 ic_opmode = NL80211_IFTYPE_STATION;
2194                 break;
2195         case NL80211_IFTYPE_ADHOC:
2196         case NL80211_IFTYPE_AP:
2197         case NL80211_IFTYPE_MESH_POINT:
2198                 if (sc->nbcnvifs >= ATH_BCBUF) {
2199                         ret = -ENOBUFS;
2200                         goto out;
2201                 }
2202                 ic_opmode = conf->type;
2203                 break;
2204         default:
2205                 DPRINTF(sc, ATH_DBG_FATAL,
2206                         "Interface type %d not yet supported\n", conf->type);
2207                 ret = -EOPNOTSUPP;
2208                 goto out;
2209         }
2210
2211         DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
2212
2213         /* Set the VIF opmode */
2214         avp->av_opmode = ic_opmode;
2215         avp->av_bslot = -1;
2216
2217         sc->nvifs++;
2218
2219         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2220                 ath9k_set_bssid_mask(hw);
2221
2222         if (sc->nvifs > 1)
2223                 goto out; /* skip global settings for secondary vif */
2224
2225         if (ic_opmode == NL80211_IFTYPE_AP) {
2226                 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2227                 sc->sc_flags |= SC_OP_TSF_RESET;
2228         }
2229
2230         /* Set the device opmode */
2231         sc->sc_ah->opmode = ic_opmode;
2232
2233         /*
2234          * Enable MIB interrupts when there are hardware phy counters.
2235          * Note we only do this (at the moment) for station mode.
2236          */
2237         if ((conf->type == NL80211_IFTYPE_STATION) ||
2238             (conf->type == NL80211_IFTYPE_ADHOC) ||
2239             (conf->type == NL80211_IFTYPE_MESH_POINT)) {
2240                 if (ath9k_hw_phycounters(sc->sc_ah))
2241                         sc->imask |= ATH9K_INT_MIB;
2242                 sc->imask |= ATH9K_INT_TSFOOR;
2243         }
2244
2245         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2246
2247         if (conf->type == NL80211_IFTYPE_AP) {
2248                 /* TODO: is this a suitable place to start ANI for AP mode? */
2249                 /* Start ANI */
2250                 mod_timer(&sc->ani.timer,
2251                           jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2252         }
2253
2254 out:
2255         mutex_unlock(&sc->mutex);
2256         return ret;
2257 }
2258
2259 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2260                                    struct ieee80211_if_init_conf *conf)
2261 {
2262         struct ath_wiphy *aphy = hw->priv;
2263         struct ath_softc *sc = aphy->sc;
2264         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2265         int i;
2266
2267         DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2268
2269         mutex_lock(&sc->mutex);
2270
2271         /* Stop ANI */
2272         del_timer_sync(&sc->ani.timer);
2273
2274         /* Reclaim beacon resources */
2275         if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2276             (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2277             (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
2278                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2279                 ath_beacon_return(sc, avp);
2280         }
2281
2282         sc->sc_flags &= ~SC_OP_BEACONS;
2283
2284         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2285                 if (sc->beacon.bslot[i] == conf->vif) {
2286                         printk(KERN_DEBUG "%s: vif had allocated beacon "
2287                                "slot\n", __func__);
2288                         sc->beacon.bslot[i] = NULL;
2289                         sc->beacon.bslot_aphy[i] = NULL;
2290                 }
2291         }
2292
2293         sc->nvifs--;
2294
2295         mutex_unlock(&sc->mutex);
2296 }
2297
2298 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2299 {
2300         struct ath_wiphy *aphy = hw->priv;
2301         struct ath_softc *sc = aphy->sc;
2302         struct ieee80211_conf *conf = &hw->conf;
2303         struct ath_hw *ah = sc->sc_ah;
2304
2305         mutex_lock(&sc->mutex);
2306
2307         if (changed & IEEE80211_CONF_CHANGE_PS) {
2308                 if (conf->flags & IEEE80211_CONF_PS) {
2309                         if (!(ah->caps.hw_caps &
2310                               ATH9K_HW_CAP_AUTOSLEEP)) {
2311                                 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2312                                         sc->imask |= ATH9K_INT_TIM_TIMER;
2313                                         ath9k_hw_set_interrupts(sc->sc_ah,
2314                                                         sc->imask);
2315                                 }
2316                                 ath9k_hw_setrxabort(sc->sc_ah, 1);
2317                         }
2318                         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2319                 } else {
2320                         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2321                         if (!(ah->caps.hw_caps &
2322                               ATH9K_HW_CAP_AUTOSLEEP)) {
2323                                 ath9k_hw_setrxabort(sc->sc_ah, 0);
2324                                 sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON;
2325                                 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2326                                         sc->imask &= ~ATH9K_INT_TIM_TIMER;
2327                                         ath9k_hw_set_interrupts(sc->sc_ah,
2328                                                         sc->imask);
2329                                 }
2330                         }
2331                 }
2332         }
2333
2334         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2335                 struct ieee80211_channel *curchan = hw->conf.channel;
2336                 int pos = curchan->hw_value;
2337
2338                 aphy->chan_idx = pos;
2339                 aphy->chan_is_ht = conf_is_ht(conf);
2340
2341                 if (aphy->state == ATH_WIPHY_SCAN ||
2342                     aphy->state == ATH_WIPHY_ACTIVE)
2343                         ath9k_wiphy_pause_all_forced(sc, aphy);
2344                 else {
2345                         /*
2346                          * Do not change operational channel based on a paused
2347                          * wiphy changes.
2348                          */
2349                         goto skip_chan_change;
2350                 }
2351
2352                 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2353                         curchan->center_freq);
2354
2355                 /* XXX: remove me eventualy */
2356                 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
2357
2358                 ath_update_chainmask(sc, conf_is_ht(conf));
2359
2360                 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2361                         DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2362                         mutex_unlock(&sc->mutex);
2363                         return -EINVAL;
2364                 }
2365         }
2366
2367 skip_chan_change:
2368         if (changed & IEEE80211_CONF_CHANGE_POWER)
2369                 sc->config.txpowlimit = 2 * conf->power_level;
2370
2371         /*
2372          * The HW TSF has to be reset when the beacon interval changes.
2373          * We set the flag here, and ath_beacon_config_ap() would take this
2374          * into account when it gets called through the subsequent
2375          * config_interface() call - with IFCC_BEACON in the changed field.
2376          */
2377
2378         if (changed & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
2379                 sc->sc_flags |= SC_OP_TSF_RESET;
2380
2381         mutex_unlock(&sc->mutex);
2382
2383         return 0;
2384 }
2385
2386 static int ath9k_config_interface(struct ieee80211_hw *hw,
2387                                   struct ieee80211_vif *vif,
2388                                   struct ieee80211_if_conf *conf)
2389 {
2390         struct ath_wiphy *aphy = hw->priv;
2391         struct ath_softc *sc = aphy->sc;
2392         struct ath_hw *ah = sc->sc_ah;
2393         struct ath_vif *avp = (void *)vif->drv_priv;
2394         u32 rfilt = 0;
2395         int error, i;
2396
2397         mutex_lock(&sc->mutex);
2398
2399         /* TODO: Need to decide which hw opmode to use for multi-interface
2400          * cases */
2401         if (vif->type == NL80211_IFTYPE_AP &&
2402             ah->opmode != NL80211_IFTYPE_AP) {
2403                 ah->opmode = NL80211_IFTYPE_STATION;
2404                 ath9k_hw_setopmode(ah);
2405                 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2406                 sc->curaid = 0;
2407                 ath9k_hw_write_associd(sc);
2408                 /* Request full reset to get hw opmode changed properly */
2409                 sc->sc_flags |= SC_OP_FULL_RESET;
2410         }
2411
2412         if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2413             !is_zero_ether_addr(conf->bssid)) {
2414                 switch (vif->type) {
2415                 case NL80211_IFTYPE_STATION:
2416                 case NL80211_IFTYPE_ADHOC:
2417                 case NL80211_IFTYPE_MESH_POINT:
2418                         /* Set BSSID */
2419                         memcpy(sc->curbssid, conf->bssid, ETH_ALEN);
2420                         memcpy(avp->bssid, conf->bssid, ETH_ALEN);
2421                         sc->curaid = 0;
2422                         ath9k_hw_write_associd(sc);
2423
2424                         /* Set aggregation protection mode parameters */
2425                         sc->config.ath_aggr_prot = 0;
2426
2427                         DPRINTF(sc, ATH_DBG_CONFIG,
2428                                 "RX filter 0x%x bssid %pM aid 0x%x\n",
2429                                 rfilt, sc->curbssid, sc->curaid);
2430
2431                         /* need to reconfigure the beacon */
2432                         sc->sc_flags &= ~SC_OP_BEACONS ;
2433
2434                         break;
2435                 default:
2436                         break;
2437                 }
2438         }
2439
2440         if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2441             (vif->type == NL80211_IFTYPE_AP) ||
2442             (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2443                 if ((conf->changed & IEEE80211_IFCC_BEACON) ||
2444                     (conf->changed & IEEE80211_IFCC_BEACON_ENABLED &&
2445                      conf->enable_beacon)) {
2446                         /*
2447                          * Allocate and setup the beacon frame.
2448                          *
2449                          * Stop any previous beacon DMA.  This may be
2450                          * necessary, for example, when an ibss merge
2451                          * causes reconfiguration; we may be called
2452                          * with beacon transmission active.
2453                          */
2454                         ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2455
2456                         error = ath_beacon_alloc(aphy, vif);
2457                         if (error != 0) {
2458                                 mutex_unlock(&sc->mutex);
2459                                 return error;
2460                         }
2461
2462                         ath_beacon_config(sc, vif);
2463                 }
2464         }
2465
2466         /* Check for WLAN_CAPABILITY_PRIVACY ? */
2467         if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2468                 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2469                         if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2470                                 ath9k_hw_keysetmac(sc->sc_ah,
2471                                                    (u16)i,
2472                                                    sc->curbssid);
2473         }
2474
2475         /* Only legacy IBSS for now */
2476         if (vif->type == NL80211_IFTYPE_ADHOC)
2477                 ath_update_chainmask(sc, 0);
2478
2479         mutex_unlock(&sc->mutex);
2480
2481         return 0;
2482 }
2483
2484 #define SUPPORTED_FILTERS                       \
2485         (FIF_PROMISC_IN_BSS |                   \
2486         FIF_ALLMULTI |                          \
2487         FIF_CONTROL |                           \
2488         FIF_OTHER_BSS |                         \
2489         FIF_BCN_PRBRESP_PROMISC |               \
2490         FIF_FCSFAIL)
2491
2492 /* FIXME: sc->sc_full_reset ? */
2493 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2494                                    unsigned int changed_flags,
2495                                    unsigned int *total_flags,
2496                                    int mc_count,
2497                                    struct dev_mc_list *mclist)
2498 {
2499         struct ath_wiphy *aphy = hw->priv;
2500         struct ath_softc *sc = aphy->sc;
2501         u32 rfilt;
2502
2503         changed_flags &= SUPPORTED_FILTERS;
2504         *total_flags &= SUPPORTED_FILTERS;
2505
2506         sc->rx.rxfilter = *total_flags;
2507         rfilt = ath_calcrxfilter(sc);
2508         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2509
2510         DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2511 }
2512
2513 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2514                              struct ieee80211_vif *vif,
2515                              enum sta_notify_cmd cmd,
2516                              struct ieee80211_sta *sta)
2517 {
2518         struct ath_wiphy *aphy = hw->priv;
2519         struct ath_softc *sc = aphy->sc;
2520
2521         switch (cmd) {
2522         case STA_NOTIFY_ADD:
2523                 ath_node_attach(sc, sta);
2524                 break;
2525         case STA_NOTIFY_REMOVE:
2526                 ath_node_detach(sc, sta);
2527                 break;
2528         default:
2529                 break;
2530         }
2531 }
2532
2533 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2534                          const struct ieee80211_tx_queue_params *params)
2535 {
2536         struct ath_wiphy *aphy = hw->priv;
2537         struct ath_softc *sc = aphy->sc;
2538         struct ath9k_tx_queue_info qi;
2539         int ret = 0, qnum;
2540
2541         if (queue >= WME_NUM_AC)
2542                 return 0;
2543
2544         mutex_lock(&sc->mutex);
2545
2546         memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2547
2548         qi.tqi_aifs = params->aifs;
2549         qi.tqi_cwmin = params->cw_min;
2550         qi.tqi_cwmax = params->cw_max;
2551         qi.tqi_burstTime = params->txop;
2552         qnum = ath_get_hal_qnum(queue, sc);
2553
2554         DPRINTF(sc, ATH_DBG_CONFIG,
2555                 "Configure tx [queue/halq] [%d/%d],  "
2556                 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2557                 queue, qnum, params->aifs, params->cw_min,
2558                 params->cw_max, params->txop);
2559
2560         ret = ath_txq_update(sc, qnum, &qi);
2561         if (ret)
2562                 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2563
2564         mutex_unlock(&sc->mutex);
2565
2566         return ret;
2567 }
2568
2569 static int ath9k_set_key(struct ieee80211_hw *hw,
2570                          enum set_key_cmd cmd,
2571                          struct ieee80211_vif *vif,
2572                          struct ieee80211_sta *sta,
2573                          struct ieee80211_key_conf *key)
2574 {
2575         struct ath_wiphy *aphy = hw->priv;
2576         struct ath_softc *sc = aphy->sc;
2577         int ret = 0;
2578
2579         if (modparam_nohwcrypt)
2580                 return -ENOSPC;
2581
2582         mutex_lock(&sc->mutex);
2583         ath9k_ps_wakeup(sc);
2584         DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n");
2585
2586         switch (cmd) {
2587         case SET_KEY:
2588                 ret = ath_key_config(sc, vif, sta, key);
2589                 if (ret >= 0) {
2590                         key->hw_key_idx = ret;
2591                         /* push IV and Michael MIC generation to stack */
2592                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2593                         if (key->alg == ALG_TKIP)
2594                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2595                         if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2596                                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2597                         ret = 0;
2598                 }
2599                 break;
2600         case DISABLE_KEY:
2601                 ath_key_delete(sc, key);
2602                 break;
2603         default:
2604                 ret = -EINVAL;
2605         }
2606
2607         ath9k_ps_restore(sc);
2608         mutex_unlock(&sc->mutex);
2609
2610         return ret;
2611 }
2612
2613 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2614                                    struct ieee80211_vif *vif,
2615                                    struct ieee80211_bss_conf *bss_conf,
2616                                    u32 changed)
2617 {
2618         struct ath_wiphy *aphy = hw->priv;
2619         struct ath_softc *sc = aphy->sc;
2620
2621         mutex_lock(&sc->mutex);
2622
2623         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2624                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2625                         bss_conf->use_short_preamble);
2626                 if (bss_conf->use_short_preamble)
2627                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2628                 else
2629                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2630         }
2631
2632         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2633                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2634                         bss_conf->use_cts_prot);
2635                 if (bss_conf->use_cts_prot &&
2636                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2637                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2638                 else
2639                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2640         }
2641
2642         if (changed & BSS_CHANGED_ASSOC) {
2643                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2644                         bss_conf->assoc);
2645                 ath9k_bss_assoc_info(sc, vif, bss_conf);
2646         }
2647
2648         mutex_unlock(&sc->mutex);
2649 }
2650
2651 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2652 {
2653         u64 tsf;
2654         struct ath_wiphy *aphy = hw->priv;
2655         struct ath_softc *sc = aphy->sc;
2656
2657         mutex_lock(&sc->mutex);
2658         tsf = ath9k_hw_gettsf64(sc->sc_ah);
2659         mutex_unlock(&sc->mutex);
2660
2661         return tsf;
2662 }
2663
2664 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2665 {
2666         struct ath_wiphy *aphy = hw->priv;
2667         struct ath_softc *sc = aphy->sc;
2668
2669         mutex_lock(&sc->mutex);
2670         ath9k_hw_settsf64(sc->sc_ah, tsf);
2671         mutex_unlock(&sc->mutex);
2672 }
2673
2674 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2675 {
2676         struct ath_wiphy *aphy = hw->priv;
2677         struct ath_softc *sc = aphy->sc;
2678
2679         mutex_lock(&sc->mutex);
2680         ath9k_hw_reset_tsf(sc->sc_ah);
2681         mutex_unlock(&sc->mutex);
2682 }
2683
2684 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2685                               enum ieee80211_ampdu_mlme_action action,
2686                               struct ieee80211_sta *sta,
2687                               u16 tid, u16 *ssn)
2688 {
2689         struct ath_wiphy *aphy = hw->priv;
2690         struct ath_softc *sc = aphy->sc;
2691         int ret = 0;
2692
2693         switch (action) {
2694         case IEEE80211_AMPDU_RX_START:
2695                 if (!(sc->sc_flags & SC_OP_RXAGGR))
2696                         ret = -ENOTSUPP;
2697                 break;
2698         case IEEE80211_AMPDU_RX_STOP:
2699                 break;
2700         case IEEE80211_AMPDU_TX_START:
2701                 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2702                 if (ret < 0)
2703                         DPRINTF(sc, ATH_DBG_FATAL,
2704                                 "Unable to start TX aggregation\n");
2705                 else
2706                         ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2707                 break;
2708         case IEEE80211_AMPDU_TX_STOP:
2709                 ret = ath_tx_aggr_stop(sc, sta, tid);
2710                 if (ret < 0)
2711                         DPRINTF(sc, ATH_DBG_FATAL,
2712                                 "Unable to stop TX aggregation\n");
2713
2714                 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2715                 break;
2716         case IEEE80211_AMPDU_TX_OPERATIONAL:
2717                 ath_tx_aggr_resume(sc, sta, tid);
2718                 break;
2719         default:
2720                 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2721         }
2722
2723         return ret;
2724 }
2725
2726 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2727 {
2728         struct ath_wiphy *aphy = hw->priv;
2729         struct ath_softc *sc = aphy->sc;
2730
2731         if (ath9k_wiphy_scanning(sc)) {
2732                 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2733                        "same time\n");
2734                 /*
2735                  * Do not allow the concurrent scanning state for now. This
2736                  * could be improved with scanning control moved into ath9k.
2737                  */
2738                 return;
2739         }
2740
2741         aphy->state = ATH_WIPHY_SCAN;
2742         ath9k_wiphy_pause_all_forced(sc, aphy);
2743
2744         mutex_lock(&sc->mutex);
2745         sc->sc_flags |= SC_OP_SCANNING;
2746         mutex_unlock(&sc->mutex);
2747 }
2748
2749 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2750 {
2751         struct ath_wiphy *aphy = hw->priv;
2752         struct ath_softc *sc = aphy->sc;
2753
2754         mutex_lock(&sc->mutex);
2755         aphy->state = ATH_WIPHY_ACTIVE;
2756         sc->sc_flags &= ~SC_OP_SCANNING;
2757         mutex_unlock(&sc->mutex);
2758 }
2759
2760 struct ieee80211_ops ath9k_ops = {
2761         .tx                 = ath9k_tx,
2762         .start              = ath9k_start,
2763         .stop               = ath9k_stop,
2764         .add_interface      = ath9k_add_interface,
2765         .remove_interface   = ath9k_remove_interface,
2766         .config             = ath9k_config,
2767         .config_interface   = ath9k_config_interface,
2768         .configure_filter   = ath9k_configure_filter,
2769         .sta_notify         = ath9k_sta_notify,
2770         .conf_tx            = ath9k_conf_tx,
2771         .bss_info_changed   = ath9k_bss_info_changed,
2772         .set_key            = ath9k_set_key,
2773         .get_tsf            = ath9k_get_tsf,
2774         .set_tsf            = ath9k_set_tsf,
2775         .reset_tsf          = ath9k_reset_tsf,
2776         .ampdu_action       = ath9k_ampdu_action,
2777         .sw_scan_start      = ath9k_sw_scan_start,
2778         .sw_scan_complete   = ath9k_sw_scan_complete,
2779 };
2780
2781 static struct {
2782         u32 version;
2783         const char * name;
2784 } ath_mac_bb_names[] = {
2785         { AR_SREV_VERSION_5416_PCI,     "5416" },
2786         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2787         { AR_SREV_VERSION_9100,         "9100" },
2788         { AR_SREV_VERSION_9160,         "9160" },
2789         { AR_SREV_VERSION_9280,         "9280" },
2790         { AR_SREV_VERSION_9285,         "9285" }
2791 };
2792
2793 static struct {
2794         u16 version;
2795         const char * name;
2796 } ath_rf_names[] = {
2797         { 0,                            "5133" },
2798         { AR_RAD5133_SREV_MAJOR,        "5133" },
2799         { AR_RAD5122_SREV_MAJOR,        "5122" },
2800         { AR_RAD2133_SREV_MAJOR,        "2133" },
2801         { AR_RAD2122_SREV_MAJOR,        "2122" }
2802 };
2803
2804 /*
2805  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2806  */
2807 const char *
2808 ath_mac_bb_name(u32 mac_bb_version)
2809 {
2810         int i;
2811
2812         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2813                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2814                         return ath_mac_bb_names[i].name;
2815                 }
2816         }
2817
2818         return "????";
2819 }
2820
2821 /*
2822  * Return the RF name. "????" is returned if the RF is unknown.
2823  */
2824 const char *
2825 ath_rf_name(u16 rf_version)
2826 {
2827         int i;
2828
2829         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2830                 if (ath_rf_names[i].version == rf_version) {
2831                         return ath_rf_names[i].name;
2832                 }
2833         }
2834
2835         return "????";
2836 }
2837
2838 static int __init ath9k_init(void)
2839 {
2840         int error;
2841
2842         /* Register rate control algorithm */
2843         error = ath_rate_control_register();
2844         if (error != 0) {
2845                 printk(KERN_ERR
2846                         "ath9k: Unable to register rate control "
2847                         "algorithm: %d\n",
2848                         error);
2849                 goto err_out;
2850         }
2851
2852         error = ath9k_debug_create_root();
2853         if (error) {
2854                 printk(KERN_ERR
2855                         "ath9k: Unable to create debugfs root: %d\n",
2856                         error);
2857                 goto err_rate_unregister;
2858         }
2859
2860         error = ath_pci_init();
2861         if (error < 0) {
2862                 printk(KERN_ERR
2863                         "ath9k: No PCI devices found, driver not installed.\n");
2864                 error = -ENODEV;
2865                 goto err_remove_root;
2866         }
2867
2868         error = ath_ahb_init();
2869         if (error < 0) {
2870                 error = -ENODEV;
2871                 goto err_pci_exit;
2872         }
2873
2874         return 0;
2875
2876  err_pci_exit:
2877         ath_pci_exit();
2878
2879  err_remove_root:
2880         ath9k_debug_remove_root();
2881  err_rate_unregister:
2882         ath_rate_control_unregister();
2883  err_out:
2884         return error;
2885 }
2886 module_init(ath9k_init);
2887
2888 static void __exit ath9k_exit(void)
2889 {
2890         ath_ahb_exit();
2891         ath_pci_exit();
2892         ath9k_debug_remove_root();
2893         ath_rate_control_unregister();
2894         printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2895 }
2896 module_exit(ath9k_exit);