2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/version.h>
44 #include <linux/module.h>
45 #include <linux/delay.h>
47 #include <linux/netdevice.h>
48 #include <linux/cache.h>
49 #include <linux/pci.h>
50 #include <linux/ethtool.h>
51 #include <linux/uaccess.h>
53 #include <net/ieee80211_radiotap.h>
55 #include <asm/unaligned.h>
61 /* unaligned little endian access */
62 #define LE_READ_2(_p) (le16_to_cpu(get_unaligned((__le16 *)(_p))))
63 #define LE_READ_4(_p) (le32_to_cpu(get_unaligned((__le32 *)(_p))))
70 static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
78 MODULE_AUTHOR("Jiri Slaby");
79 MODULE_AUTHOR("Nick Kossifidis");
80 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
81 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
82 MODULE_LICENSE("Dual BSD/GPL");
83 MODULE_VERSION("0.1.1 (EXPERIMENTAL)");
87 static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
88 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
89 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
90 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
91 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
92 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
93 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
94 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
96 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
102 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
103 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
104 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* 5424 Condor (PCI-E)*/
105 { PCI_VDEVICE(ATHEROS, 0x0023), .driver_data = AR5K_AR5212 }, /* 5416 */
106 { PCI_VDEVICE(ATHEROS, 0x0024), .driver_data = AR5K_AR5212 }, /* 5418 */
109 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
112 static struct ath5k_srev_name srev_names[] = {
113 { "5210", AR5K_VERSION_VER, AR5K_SREV_VER_AR5210 },
114 { "5311", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311 },
115 { "5311A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311A },
116 { "5311B", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311B },
117 { "5211", AR5K_VERSION_VER, AR5K_SREV_VER_AR5211 },
118 { "5212", AR5K_VERSION_VER, AR5K_SREV_VER_AR5212 },
119 { "5213", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213 },
120 { "5213A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213A },
121 { "2424", AR5K_VERSION_VER, AR5K_SREV_VER_AR2424 },
122 { "5424", AR5K_VERSION_VER, AR5K_SREV_VER_AR5424 },
123 { "5413", AR5K_VERSION_VER, AR5K_SREV_VER_AR5413 },
124 { "5414", AR5K_VERSION_VER, AR5K_SREV_VER_AR5414 },
125 { "5416", AR5K_VERSION_VER, AR5K_SREV_VER_AR5416 },
126 { "5418", AR5K_VERSION_VER, AR5K_SREV_VER_AR5418 },
127 { "xxxxx", AR5K_VERSION_VER, AR5K_SREV_UNKNOWN },
128 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
129 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
130 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
131 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
132 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
133 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
134 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
135 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC1 },
136 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC2 },
137 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
138 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
142 * Prototypes - PCI stack related functions
144 static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
145 const struct pci_device_id *id);
146 static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
148 static int ath5k_pci_suspend(struct pci_dev *pdev,
150 static int ath5k_pci_resume(struct pci_dev *pdev);
152 #define ath5k_pci_suspend NULL
153 #define ath5k_pci_resume NULL
154 #endif /* CONFIG_PM */
156 static struct pci_driver ath5k_pci_drv_id = {
158 .id_table = ath5k_pci_id_table,
159 .probe = ath5k_pci_probe,
160 .remove = __devexit_p(ath5k_pci_remove),
161 .suspend = ath5k_pci_suspend,
162 .resume = ath5k_pci_resume,
168 * Prototypes - MAC 802.11 stack related functions
170 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
171 struct ieee80211_tx_control *ctl);
172 static int ath5k_reset(struct ieee80211_hw *hw);
173 static int ath5k_start(struct ieee80211_hw *hw);
174 static void ath5k_stop(struct ieee80211_hw *hw);
175 static int ath5k_add_interface(struct ieee80211_hw *hw,
176 struct ieee80211_if_init_conf *conf);
177 static void ath5k_remove_interface(struct ieee80211_hw *hw,
178 struct ieee80211_if_init_conf *conf);
179 static int ath5k_config(struct ieee80211_hw *hw,
180 struct ieee80211_conf *conf);
181 static int ath5k_config_interface(struct ieee80211_hw *hw,
182 struct ieee80211_vif *vif,
183 struct ieee80211_if_conf *conf);
184 static void ath5k_configure_filter(struct ieee80211_hw *hw,
185 unsigned int changed_flags,
186 unsigned int *new_flags,
187 int mc_count, struct dev_mc_list *mclist);
188 static int ath5k_set_key(struct ieee80211_hw *hw,
189 enum set_key_cmd cmd,
190 const u8 *local_addr, const u8 *addr,
191 struct ieee80211_key_conf *key);
192 static int ath5k_get_stats(struct ieee80211_hw *hw,
193 struct ieee80211_low_level_stats *stats);
194 static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
195 struct ieee80211_tx_queue_stats *stats);
196 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
197 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
198 static int ath5k_beacon_update(struct ieee80211_hw *hw,
200 struct ieee80211_tx_control *ctl);
202 static struct ieee80211_ops ath5k_hw_ops = {
204 .start = ath5k_start,
206 .add_interface = ath5k_add_interface,
207 .remove_interface = ath5k_remove_interface,
208 .config = ath5k_config,
209 .config_interface = ath5k_config_interface,
210 .configure_filter = ath5k_configure_filter,
211 .set_key = ath5k_set_key,
212 .get_stats = ath5k_get_stats,
214 .get_tx_stats = ath5k_get_tx_stats,
215 .get_tsf = ath5k_get_tsf,
216 .reset_tsf = ath5k_reset_tsf,
217 .beacon_update = ath5k_beacon_update,
221 * Prototypes - Internal functions
224 static int ath5k_attach(struct pci_dev *pdev,
225 struct ieee80211_hw *hw);
226 static void ath5k_detach(struct pci_dev *pdev,
227 struct ieee80211_hw *hw);
228 /* Channel/mode setup */
229 static inline short ath5k_ieee2mhz(short chan);
230 static unsigned int ath5k_copy_rates(struct ieee80211_rate *rates,
231 const struct ath5k_rate_table *rt,
233 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
234 struct ieee80211_channel *channels,
237 static int ath5k_getchannels(struct ieee80211_hw *hw);
238 static int ath5k_chan_set(struct ath5k_softc *sc,
239 struct ieee80211_channel *chan);
240 static void ath5k_setcurmode(struct ath5k_softc *sc,
242 static void ath5k_mode_setup(struct ath5k_softc *sc);
243 /* Descriptor setup */
244 static int ath5k_desc_alloc(struct ath5k_softc *sc,
245 struct pci_dev *pdev);
246 static void ath5k_desc_free(struct ath5k_softc *sc,
247 struct pci_dev *pdev);
249 static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
250 struct ath5k_buf *bf);
251 static int ath5k_txbuf_setup(struct ath5k_softc *sc,
252 struct ath5k_buf *bf,
253 struct ieee80211_tx_control *ctl);
255 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
256 struct ath5k_buf *bf)
261 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
263 dev_kfree_skb(bf->skb);
268 static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
269 int qtype, int subtype);
270 static int ath5k_beaconq_setup(struct ath5k_hw *ah);
271 static int ath5k_beaconq_config(struct ath5k_softc *sc);
272 static void ath5k_txq_drainq(struct ath5k_softc *sc,
273 struct ath5k_txq *txq);
274 static void ath5k_txq_cleanup(struct ath5k_softc *sc);
275 static void ath5k_txq_release(struct ath5k_softc *sc);
277 static int ath5k_rx_start(struct ath5k_softc *sc);
278 static void ath5k_rx_stop(struct ath5k_softc *sc);
279 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
280 struct ath5k_desc *ds,
281 struct sk_buff *skb);
282 static void ath5k_tasklet_rx(unsigned long data);
284 static void ath5k_tx_processq(struct ath5k_softc *sc,
285 struct ath5k_txq *txq);
286 static void ath5k_tasklet_tx(unsigned long data);
287 /* Beacon handling */
288 static int ath5k_beacon_setup(struct ath5k_softc *sc,
289 struct ath5k_buf *bf,
290 struct ieee80211_tx_control *ctl);
291 static void ath5k_beacon_send(struct ath5k_softc *sc);
292 static void ath5k_beacon_config(struct ath5k_softc *sc);
293 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
295 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
297 u64 tsf = ath5k_hw_get_tsf64(ah);
299 if ((tsf & 0x7fff) < rstamp)
302 return (tsf & ~0x7fff) | rstamp;
305 /* Interrupt handling */
306 static int ath5k_init(struct ath5k_softc *sc);
307 static int ath5k_stop_locked(struct ath5k_softc *sc);
308 static int ath5k_stop_hw(struct ath5k_softc *sc);
309 static irqreturn_t ath5k_intr(int irq, void *dev_id);
310 static void ath5k_tasklet_reset(unsigned long data);
312 static void ath5k_calibrate(unsigned long data);
314 static void ath5k_led_off(unsigned long data);
315 static void ath5k_led_blink(struct ath5k_softc *sc,
318 static void ath5k_led_event(struct ath5k_softc *sc,
323 * Module init/exit functions
332 ret = pci_register_driver(&ath5k_pci_drv_id);
334 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
344 pci_unregister_driver(&ath5k_pci_drv_id);
346 ath5k_debug_finish();
349 module_init(init_ath5k_pci);
350 module_exit(exit_ath5k_pci);
353 /********************\
354 * PCI Initialization *
355 \********************/
358 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
360 const char *name = "xxxxx";
363 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
364 if (srev_names[i].sr_type != type)
366 if ((val & 0xff) < srev_names[i + 1].sr_val) {
367 name = srev_names[i].sr_name;
376 ath5k_pci_probe(struct pci_dev *pdev,
377 const struct pci_device_id *id)
380 struct ath5k_softc *sc;
381 struct ieee80211_hw *hw;
385 ret = pci_enable_device(pdev);
387 dev_err(&pdev->dev, "can't enable device\n");
391 /* XXX 32-bit addressing only */
392 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
394 dev_err(&pdev->dev, "32-bit DMA not available\n");
399 * Cache line size is used to size and align various
400 * structures used to communicate with the hardware.
402 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
405 * Linux 2.4.18 (at least) writes the cache line size
406 * register as a 16-bit wide register which is wrong.
407 * We must have this setup properly for rx buffer
408 * DMA to work so force a reasonable value here if it
411 csz = L1_CACHE_BYTES / sizeof(u32);
412 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
415 * The default setting of latency timer yields poor results,
416 * set it to the value used by other systems. It may be worth
417 * tweaking this setting more.
419 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
421 /* Enable bus mastering */
422 pci_set_master(pdev);
425 * Disable the RETRY_TIMEOUT register (0x41) to keep
426 * PCI Tx retries from interfering with C3 CPU state.
428 pci_write_config_byte(pdev, 0x41, 0);
430 ret = pci_request_region(pdev, 0, "ath5k");
432 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
436 mem = pci_iomap(pdev, 0, 0);
438 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
444 * Allocate hw (mac80211 main struct)
445 * and hw->priv (driver private data)
447 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
449 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
454 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
456 /* Initialize driver private data */
457 SET_IEEE80211_DEV(hw, &pdev->dev);
458 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS;
459 hw->extra_tx_headroom = 2;
460 hw->channel_change_time = 5000;
461 /* these names are misleading */
462 hw->max_rssi = -110; /* signal in dBm */
463 hw->max_noise = -110; /* noise in dBm */
464 hw->max_signal = 100; /* we will provide a percentage based on rssi */
469 ath5k_debug_init_device(sc);
472 * Mark the device as detached to avoid processing
473 * interrupts until setup is complete.
475 __set_bit(ATH_STAT_INVALID, sc->status);
477 sc->iobase = mem; /* So we can unmap it on detach */
478 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
479 sc->opmode = IEEE80211_IF_TYPE_STA;
480 mutex_init(&sc->lock);
481 spin_lock_init(&sc->rxbuflock);
482 spin_lock_init(&sc->txbuflock);
484 /* Set private data */
485 pci_set_drvdata(pdev, hw);
487 /* Enable msi for devices that support it */
488 pci_enable_msi(pdev);
490 /* Setup interrupt handler */
491 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
493 ATH5K_ERR(sc, "request_irq failed\n");
497 /* Initialize device */
498 sc->ah = ath5k_hw_attach(sc, id->driver_data);
499 if (IS_ERR(sc->ah)) {
500 ret = PTR_ERR(sc->ah);
504 /* Finish private driver data initialization */
505 ret = ath5k_attach(pdev, hw);
509 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
510 ath5k_chip_name(AR5K_VERSION_VER,sc->ah->ah_mac_srev),
512 sc->ah->ah_phy_revision);
514 if(!sc->ah->ah_single_chip){
515 /* Single chip radio (!RF5111) */
516 if(sc->ah->ah_radio_5ghz_revision && !sc->ah->ah_radio_2ghz_revision) {
517 /* No 5GHz support -> report 2GHz radio */
518 if(!test_bit(MODE_IEEE80211A, sc->ah->ah_capabilities.cap_mode)){
519 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
520 ath5k_chip_name(AR5K_VERSION_RAD,sc->ah->ah_radio_5ghz_revision),
521 sc->ah->ah_radio_5ghz_revision);
522 /* No 2GHz support (5110 and some 5Ghz only cards) -> report 5Ghz radio */
523 } else if(!test_bit(MODE_IEEE80211B, sc->ah->ah_capabilities.cap_mode)){
524 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
525 ath5k_chip_name(AR5K_VERSION_RAD,sc->ah->ah_radio_5ghz_revision),
526 sc->ah->ah_radio_5ghz_revision);
527 /* Multiband radio */
529 ATH5K_INFO(sc, "RF%s multiband radio found"
531 ath5k_chip_name(AR5K_VERSION_RAD,sc->ah->ah_radio_5ghz_revision),
532 sc->ah->ah_radio_5ghz_revision);
535 /* Multi chip radio (RF5111 - RF2111) -> report both 2GHz/5GHz radios */
536 else if(sc->ah->ah_radio_5ghz_revision && sc->ah->ah_radio_2ghz_revision){
537 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
538 ath5k_chip_name(AR5K_VERSION_RAD,sc->ah->ah_radio_5ghz_revision),
539 sc->ah->ah_radio_5ghz_revision);
540 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
541 ath5k_chip_name(AR5K_VERSION_RAD,sc->ah->ah_radio_2ghz_revision),
542 sc->ah->ah_radio_2ghz_revision);
547 /* ready to process interrupts */
548 __clear_bit(ATH_STAT_INVALID, sc->status);
552 ath5k_hw_detach(sc->ah);
554 free_irq(pdev->irq, sc);
556 pci_disable_msi(pdev);
557 ieee80211_free_hw(hw);
559 pci_iounmap(pdev, mem);
561 pci_release_region(pdev, 0);
563 pci_disable_device(pdev);
568 static void __devexit
569 ath5k_pci_remove(struct pci_dev *pdev)
571 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
572 struct ath5k_softc *sc = hw->priv;
574 ath5k_debug_finish_device(sc);
575 ath5k_detach(pdev, hw);
576 ath5k_hw_detach(sc->ah);
577 free_irq(pdev->irq, sc);
578 pci_disable_msi(pdev);
579 pci_iounmap(pdev, sc->iobase);
580 pci_release_region(pdev, 0);
581 pci_disable_device(pdev);
582 ieee80211_free_hw(hw);
587 ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
589 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
590 struct ath5k_softc *sc = hw->priv;
592 if (test_bit(ATH_STAT_LEDSOFT, sc->status))
593 ath5k_hw_set_gpio(sc->ah, sc->led_pin, 1);
596 pci_save_state(pdev);
597 pci_disable_device(pdev);
598 pci_set_power_state(pdev, PCI_D3hot);
604 ath5k_pci_resume(struct pci_dev *pdev)
606 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
607 struct ath5k_softc *sc = hw->priv;
608 struct ath5k_hw *ah = sc->ah;
611 err = pci_set_power_state(pdev, PCI_D0);
615 err = pci_enable_device(pdev);
619 pci_restore_state(pdev);
621 * Suspend/Resume resets the PCI configuration space, so we have to
622 * re-disable the RETRY_TIMEOUT register (0x41) to keep
623 * PCI Tx retries from interfering with C3 CPU state
625 pci_write_config_byte(pdev, 0x41, 0);
628 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
629 ath5k_hw_set_gpio_output(ah, sc->led_pin);
630 ath5k_hw_set_gpio(ah, sc->led_pin, 0);
634 * Reset the key cache since some parts do not
635 * reset the contents on initial power up or resume.
637 * FIXME: This may need to be revisited when mac80211 becomes
638 * aware of suspend/resume.
640 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
641 ath5k_hw_reset_key(ah, i);
645 #endif /* CONFIG_PM */
649 /***********************\
650 * Driver Initialization *
651 \***********************/
654 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
656 struct ath5k_softc *sc = hw->priv;
657 struct ath5k_hw *ah = sc->ah;
662 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
665 * Check if the MAC has multi-rate retry support.
666 * We do this by trying to setup a fake extended
667 * descriptor. MAC's that don't have support will
668 * return false w/o doing anything. MAC's that do
669 * support it will return true w/o doing anything.
671 if (ah->ah_setup_xtx_desc(ah, NULL, 0, 0, 0, 0, 0, 0))
672 __set_bit(ATH_STAT_MRRETRY, sc->status);
675 * Reset the key cache since some parts do not
676 * reset the contents on initial power up.
678 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
679 ath5k_hw_reset_key(ah, i);
682 * Collect the channel list. The 802.11 layer
683 * is resposible for filtering this list based
684 * on settings like the phy mode and regulatory
685 * domain restrictions.
687 ret = ath5k_getchannels(hw);
689 ATH5K_ERR(sc, "can't get channels\n");
693 /* NB: setup here so ath5k_rate_update is happy */
694 if (test_bit(MODE_IEEE80211A, ah->ah_modes))
695 ath5k_setcurmode(sc, MODE_IEEE80211A);
697 ath5k_setcurmode(sc, MODE_IEEE80211B);
700 * Allocate tx+rx descriptors and populate the lists.
702 ret = ath5k_desc_alloc(sc, pdev);
704 ATH5K_ERR(sc, "can't allocate descriptors\n");
709 * Allocate hardware transmit queues: one queue for
710 * beacon frames and one data queue for each QoS
711 * priority. Note that hw functions handle reseting
712 * these queues at the needed time.
714 ret = ath5k_beaconq_setup(ah);
716 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
721 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
722 if (IS_ERR(sc->txq)) {
723 ATH5K_ERR(sc, "can't setup xmit queue\n");
724 ret = PTR_ERR(sc->txq);
728 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
729 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
730 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
731 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
732 setup_timer(&sc->led_tim, ath5k_led_off, (unsigned long)sc);
734 sc->led_on = 0; /* low true */
736 * Auto-enable soft led processing for IBM cards and for
737 * 5211 minipci cards.
739 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
740 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
741 __set_bit(ATH_STAT_LEDSOFT, sc->status);
744 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
745 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
746 __set_bit(ATH_STAT_LEDSOFT, sc->status);
749 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
750 ath5k_hw_set_gpio_output(ah, sc->led_pin);
751 ath5k_hw_set_gpio(ah, sc->led_pin, !sc->led_on);
754 ath5k_hw_get_lladdr(ah, mac);
755 SET_IEEE80211_PERM_ADDR(hw, mac);
756 /* All MAC address bits matter for ACKs */
757 memset(sc->bssidmask, 0xff, ETH_ALEN);
758 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
760 ret = ieee80211_register_hw(hw);
762 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
768 ath5k_txq_release(sc);
770 ath5k_hw_release_tx_queue(ah, sc->bhalq);
772 ath5k_desc_free(sc, pdev);
778 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
780 struct ath5k_softc *sc = hw->priv;
783 * NB: the order of these is important:
784 * o call the 802.11 layer before detaching ath5k_hw to
785 * insure callbacks into the driver to delete global
786 * key cache entries can be handled
787 * o reclaim the tx queue data structures after calling
788 * the 802.11 layer as we'll get called back to reclaim
789 * node state and potentially want to use them
790 * o to cleanup the tx queues the hal is called, so detach
792 * XXX: ??? detach ath5k_hw ???
793 * Other than that, it's straightforward...
795 ieee80211_unregister_hw(hw);
796 ath5k_desc_free(sc, pdev);
797 ath5k_txq_release(sc);
798 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
801 * NB: can't reclaim these until after ieee80211_ifdetach
802 * returns because we'll get called back to reclaim node
803 * state and potentially want to use them.
810 /********************\
811 * Channel/mode setup *
812 \********************/
815 * Convert IEEE channel number to MHz frequency.
818 ath5k_ieee2mhz(short chan)
820 if (chan <= 14 || chan >= 27)
821 return ieee80211chan2mhz(chan);
823 return 2212 + chan * 20;
827 ath5k_copy_rates(struct ieee80211_rate *rates,
828 const struct ath5k_rate_table *rt,
831 unsigned int i, count;
836 for (i = 0, count = 0; i < rt->rate_count && max > 0; i++) {
837 if (!rt->rates[i].valid)
839 rates->rate = rt->rates[i].rate_kbps / 100;
840 rates->val = rt->rates[i].rate_code;
841 rates->flags = rt->rates[i].modulation;
851 ath5k_copy_channels(struct ath5k_hw *ah,
852 struct ieee80211_channel *channels,
856 static const struct { unsigned int mode, mask, chan; } map[] = {
857 [MODE_IEEE80211A] = { CHANNEL_OFDM, CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_A },
858 [MODE_ATHEROS_TURBO] = { CHANNEL_OFDM|CHANNEL_TURBO, CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_T },
859 [MODE_IEEE80211B] = { CHANNEL_CCK, CHANNEL_CCK, CHANNEL_B },
860 [MODE_IEEE80211G] = { CHANNEL_OFDM, CHANNEL_OFDM, CHANNEL_G },
861 [MODE_ATHEROS_TURBOG] = { CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_TG },
863 static const struct ath5k_regchannel chans_2ghz[] =
864 IEEE80211_CHANNELS_2GHZ;
865 static const struct ath5k_regchannel chans_5ghz[] =
866 IEEE80211_CHANNELS_5GHZ;
867 const struct ath5k_regchannel *chans;
868 enum ath5k_regdom dmn;
869 unsigned int i, count, size, chfreq, all, f, ch;
871 if (!test_bit(mode, ah->ah_modes))
874 all = ah->ah_regdomain == DMN_DEFAULT || CHAN_DEBUG == 1;
877 case MODE_IEEE80211A:
878 case MODE_ATHEROS_TURBO:
879 /* 1..220, but 2GHz frequencies are filtered by check_channel */
880 size = all ? 220 : ARRAY_SIZE(chans_5ghz);
882 dmn = ath5k_regdom2flag(ah->ah_regdomain,
883 IEEE80211_CHANNELS_5GHZ_MIN);
884 chfreq = CHANNEL_5GHZ;
886 case MODE_IEEE80211B:
887 case MODE_IEEE80211G:
888 case MODE_ATHEROS_TURBOG:
889 size = all ? 26 : ARRAY_SIZE(chans_2ghz);
891 dmn = ath5k_regdom2flag(ah->ah_regdomain,
892 IEEE80211_CHANNELS_2GHZ_MIN);
893 chfreq = CHANNEL_2GHZ;
896 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
900 for (i = 0, count = 0; i < size && max > 0; i++) {
901 ch = all ? i + 1 : chans[i].chan;
902 f = ath5k_ieee2mhz(ch);
903 /* Check if channel is supported by the chipset */
904 if (!ath5k_channel_ok(ah, f, chfreq))
907 /* Match regulation domain */
908 if (!all && !(IEEE80211_DMN(chans[i].domain) &
912 if (!all && (chans[i].mode & map[mode].mask) != map[mode].mode)
915 /* Write channel and increment counter */
918 channels->val = map[mode].chan;
927 /* Only tries to register modes our EEPROM says it can support */
928 #define REGISTER_MODE(m) do { \
929 ret = ath5k_register_mode(hw, m); \
935 ath5k_register_mode(struct ieee80211_hw *hw, u8 m)
937 struct ath5k_softc *sc = hw->priv;
938 struct ieee80211_hw_mode *modes = sc->modes;
942 if (!test_bit(m, sc->ah->ah_capabilities.cap_mode))
945 for (i = 0; i < NUM_DRIVER_MODES; i++) {
946 if (modes[i].mode != m || !modes[i].num_channels)
948 ret = ieee80211_register_hwmode(hw, &modes[i]);
950 ATH5K_ERR(sc, "can't register hwmode %u\n", m);
959 ath5k_getchannels(struct ieee80211_hw *hw)
961 struct ath5k_softc *sc = hw->priv;
962 struct ath5k_hw *ah = sc->ah;
963 struct ieee80211_hw_mode *modes = sc->modes;
964 unsigned int i, max_r, max_c;
967 BUILD_BUG_ON(ARRAY_SIZE(sc->modes) < 3);
969 /* The order here does not matter */
970 modes[0].mode = MODE_IEEE80211G;
971 modes[1].mode = MODE_IEEE80211B;
972 modes[2].mode = MODE_IEEE80211A;
974 max_r = ARRAY_SIZE(sc->rates);
975 max_c = ARRAY_SIZE(sc->channels);
977 for (i = 0; i < NUM_DRIVER_MODES; i++) {
978 struct ieee80211_hw_mode *mode = &modes[i];
979 const struct ath5k_rate_table *hw_rates;
982 modes[0].rates = sc->rates;
983 modes->channels = sc->channels;
985 struct ieee80211_hw_mode *prev_mode = &modes[i-1];
986 int prev_num_r = prev_mode->num_rates;
987 int prev_num_c = prev_mode->num_channels;
988 mode->rates = &prev_mode->rates[prev_num_r];
989 mode->channels = &prev_mode->channels[prev_num_c];
992 hw_rates = ath5k_hw_get_rate_table(ah, mode->mode);
993 mode->num_rates = ath5k_copy_rates(mode->rates, hw_rates,
995 mode->num_channels = ath5k_copy_channels(ah, mode->channels,
997 max_r -= mode->num_rates;
998 max_c -= mode->num_channels;
1001 /* We try to register all modes this driver supports. We don't bother
1002 * with MODE_IEEE80211B for AR5212 as MODE_IEEE80211G already accounts
1003 * for that as per mac80211. Then, REGISTER_MODE() will will actually
1004 * check the eeprom reading for more reliable capability information.
1005 * Order matters here as per mac80211's latest preference. This will
1006 * all hopefullly soon go away. */
1008 REGISTER_MODE(MODE_IEEE80211G);
1009 if (ah->ah_version != AR5K_AR5212)
1010 REGISTER_MODE(MODE_IEEE80211B);
1011 REGISTER_MODE(MODE_IEEE80211A);
1013 ath5k_debug_dump_modes(sc, modes);
1019 * Set/change channels. If the channel is really being changed,
1020 * it's done by reseting the chip. To accomplish this we must
1021 * first cleanup any pending DMA, then restart stuff after a la
1025 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1027 struct ath5k_hw *ah = sc->ah;
1030 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "%u (%u MHz) -> %u (%u MHz)\n",
1031 sc->curchan->chan, sc->curchan->freq,
1032 chan->chan, chan->freq);
1034 if (chan->freq != sc->curchan->freq || chan->val != sc->curchan->val) {
1036 * To switch channels clear any pending DMA operations;
1037 * wait long enough for the RX fifo to drain, reset the
1038 * hardware at the new frequency, and then re-enable
1039 * the relevant bits of the h/w.
1041 ath5k_hw_set_intr(ah, 0); /* disable interrupts */
1042 ath5k_txq_cleanup(sc); /* clear pending tx frames */
1043 ath5k_rx_stop(sc); /* turn off frame recv */
1044 ret = ath5k_hw_reset(ah, sc->opmode, chan, true);
1046 ATH5K_ERR(sc, "%s: unable to reset channel %u "
1047 "(%u Mhz)\n", __func__, chan->chan, chan->freq);
1051 ath5k_hw_set_txpower_limit(sc->ah, 0);
1054 * Re-enable rx framework.
1056 ret = ath5k_rx_start(sc);
1058 ATH5K_ERR(sc, "%s: unable to restart recv logic\n",
1064 * Change channels and update the h/w rate map
1065 * if we're switching; e.g. 11a to 11b/g.
1069 /* ath5k_chan_change(sc, chan); */
1071 ath5k_beacon_config(sc);
1073 * Re-enable interrupts.
1075 ath5k_hw_set_intr(ah, sc->imask);
1082 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1084 if (unlikely(test_bit(ATH_STAT_LEDSOFT, sc->status))) {
1085 /* from Atheros NDIS driver, w/ permission */
1086 static const struct {
1087 u16 rate; /* tx/rx 802.11 rate */
1088 u16 timeOn; /* LED on time (ms) */
1089 u16 timeOff; /* LED off time (ms) */
1106 const struct ath5k_rate_table *rt =
1107 ath5k_hw_get_rate_table(sc->ah, mode);
1112 memset(sc->hwmap, 0, sizeof(sc->hwmap));
1113 for (i = 0; i < 32; i++) {
1114 u8 ix = rt->rate_code_to_index[i];
1116 sc->hwmap[i].ledon = msecs_to_jiffies(500);
1117 sc->hwmap[i].ledoff = msecs_to_jiffies(130);
1120 sc->hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD;
1121 if (SHPREAMBLE_FLAG(ix) || rt->rates[ix].modulation ==
1122 IEEE80211_RATE_OFDM)
1123 sc->hwmap[i].txflags |=
1124 IEEE80211_RADIOTAP_F_SHORTPRE;
1125 /* receive frames include FCS */
1126 sc->hwmap[i].rxflags = sc->hwmap[i].txflags |
1127 IEEE80211_RADIOTAP_F_FCS;
1128 /* setup blink rate table to avoid per-packet lookup */
1129 for (j = 0; j < ARRAY_SIZE(blinkrates) - 1; j++)
1130 if (blinkrates[j].rate == /* XXX why 7f? */
1131 (rt->rates[ix].dot11_rate&0x7f))
1134 sc->hwmap[i].ledon = msecs_to_jiffies(blinkrates[j].
1136 sc->hwmap[i].ledoff = msecs_to_jiffies(blinkrates[j].
1145 ath5k_mode_setup(struct ath5k_softc *sc)
1147 struct ath5k_hw *ah = sc->ah;
1150 /* configure rx filter */
1151 rfilt = sc->filter_flags;
1152 ath5k_hw_set_rx_filter(ah, rfilt);
1154 if (ath5k_hw_hasbssidmask(ah))
1155 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1157 /* configure operational mode */
1158 ath5k_hw_set_opmode(ah);
1160 ath5k_hw_set_mcast_filter(ah, 0, 0);
1161 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1172 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1174 struct ath5k_hw *ah = sc->ah;
1175 struct sk_buff *skb = bf->skb;
1176 struct ath5k_desc *ds;
1178 if (likely(skb == NULL)) {
1182 * Allocate buffer with headroom_needed space for the
1183 * fake physical layer header at the start.
1185 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1186 if (unlikely(skb == NULL)) {
1187 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1188 sc->rxbufsize + sc->cachelsz - 1);
1192 * Cache-line-align. This is important (for the
1193 * 5210 at least) as not doing so causes bogus data
1196 off = ((unsigned long)skb->data) % sc->cachelsz;
1198 skb_reserve(skb, sc->cachelsz - off);
1201 bf->skbaddr = pci_map_single(sc->pdev,
1202 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1203 if (unlikely(pci_dma_mapping_error(bf->skbaddr))) {
1204 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1212 * Setup descriptors. For receive we always terminate
1213 * the descriptor list with a self-linked entry so we'll
1214 * not get overrun under high load (as can happen with a
1215 * 5212 when ANI processing enables PHY error frames).
1217 * To insure the last descriptor is self-linked we create
1218 * each descriptor as self-linked and add it to the end. As
1219 * each additional descriptor is added the previous self-linked
1220 * entry is ``fixed'' naturally. This should be safe even
1221 * if DMA is happening. When processing RX interrupts we
1222 * never remove/process the last, self-linked, entry on the
1223 * descriptor list. This insures the hardware always has
1224 * someplace to write a new frame.
1227 ds->ds_link = bf->daddr; /* link to self */
1228 ds->ds_data = bf->skbaddr;
1229 ath5k_hw_setup_rx_desc(ah, ds,
1230 skb_tailroom(skb), /* buffer size */
1233 if (sc->rxlink != NULL)
1234 *sc->rxlink = bf->daddr;
1235 sc->rxlink = &ds->ds_link;
1240 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1241 struct ieee80211_tx_control *ctl)
1243 struct ath5k_hw *ah = sc->ah;
1244 struct ath5k_txq *txq = sc->txq;
1245 struct ath5k_desc *ds = bf->desc;
1246 struct sk_buff *skb = bf->skb;
1247 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1250 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1252 /* XXX endianness */
1253 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1256 if (ctl->flags & IEEE80211_TXCTL_NO_ACK)
1257 flags |= AR5K_TXDESC_NOACK;
1259 pktlen = skb->len + FCS_LEN;
1261 if (!(ctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT)) {
1262 keyidx = ctl->key_idx;
1263 pktlen += ctl->icv_len;
1266 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1267 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1268 (ctl->power_level * 2), ctl->tx_rate, ctl->retry_limit, keyidx, 0, flags, 0, 0);
1273 ds->ds_data = bf->skbaddr;
1275 spin_lock_bh(&txq->lock);
1276 list_add_tail(&bf->list, &txq->q);
1277 sc->tx_stats.data[txq->qnum].len++;
1278 if (txq->link == NULL) /* is this first packet? */
1279 ath5k_hw_put_tx_buf(ah, txq->qnum, bf->daddr);
1280 else /* no, so only link it */
1281 *txq->link = bf->daddr;
1283 txq->link = &ds->ds_link;
1284 ath5k_hw_tx_start(ah, txq->qnum);
1285 spin_unlock_bh(&txq->lock);
1289 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1293 /*******************\
1294 * Descriptors setup *
1295 \*******************/
1298 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1300 struct ath5k_desc *ds;
1301 struct ath5k_buf *bf;
1306 /* allocate descriptors */
1307 sc->desc_len = sizeof(struct ath5k_desc) *
1308 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1309 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1310 if (sc->desc == NULL) {
1311 ATH5K_ERR(sc, "can't allocate descriptors\n");
1316 da = sc->desc_daddr;
1317 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1318 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1320 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1321 sizeof(struct ath5k_buf), GFP_KERNEL);
1323 ATH5K_ERR(sc, "can't allocate bufptr\n");
1329 INIT_LIST_HEAD(&sc->rxbuf);
1330 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1333 list_add_tail(&bf->list, &sc->rxbuf);
1336 INIT_LIST_HEAD(&sc->txbuf);
1337 sc->txbuf_len = ATH_TXBUF;
1338 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1339 da += sizeof(*ds)) {
1342 list_add_tail(&bf->list, &sc->txbuf);
1352 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1359 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1361 struct ath5k_buf *bf;
1363 ath5k_txbuf_free(sc, sc->bbuf);
1364 list_for_each_entry(bf, &sc->txbuf, list)
1365 ath5k_txbuf_free(sc, bf);
1366 list_for_each_entry(bf, &sc->rxbuf, list)
1367 ath5k_txbuf_free(sc, bf);
1369 /* Free memory associated with all descriptors */
1370 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1384 static struct ath5k_txq *
1385 ath5k_txq_setup(struct ath5k_softc *sc,
1386 int qtype, int subtype)
1388 struct ath5k_hw *ah = sc->ah;
1389 struct ath5k_txq *txq;
1390 struct ath5k_txq_info qi = {
1391 .tqi_subtype = subtype,
1392 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1393 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1394 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1399 * Enable interrupts only for EOL and DESC conditions.
1400 * We mark tx descriptors to receive a DESC interrupt
1401 * when a tx queue gets deep; otherwise waiting for the
1402 * EOL to reap descriptors. Note that this is done to
1403 * reduce interrupt load and this only defers reaping
1404 * descriptors, never transmitting frames. Aside from
1405 * reducing interrupts this also permits more concurrency.
1406 * The only potential downside is if the tx queue backs
1407 * up in which case the top half of the kernel may backup
1408 * due to a lack of tx descriptors.
1410 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1411 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1412 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1415 * NB: don't print a message, this happens
1416 * normally on parts with too few tx queues
1418 return ERR_PTR(qnum);
1420 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1421 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1422 qnum, ARRAY_SIZE(sc->txqs));
1423 ath5k_hw_release_tx_queue(ah, qnum);
1424 return ERR_PTR(-EINVAL);
1426 txq = &sc->txqs[qnum];
1430 INIT_LIST_HEAD(&txq->q);
1431 spin_lock_init(&txq->lock);
1434 return &sc->txqs[qnum];
1438 ath5k_beaconq_setup(struct ath5k_hw *ah)
1440 struct ath5k_txq_info qi = {
1441 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1442 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1443 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1444 /* NB: for dynamic turbo, don't enable any other interrupts */
1445 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1448 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1452 ath5k_beaconq_config(struct ath5k_softc *sc)
1454 struct ath5k_hw *ah = sc->ah;
1455 struct ath5k_txq_info qi;
1458 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1461 if (sc->opmode == IEEE80211_IF_TYPE_AP ||
1462 sc->opmode == IEEE80211_IF_TYPE_IBSS) {
1464 * Always burst out beacon and CAB traffic
1465 * (aifs = cwmin = cwmax = 0)
1472 ret = ath5k_hw_setup_tx_queueprops(ah, sc->bhalq, &qi);
1474 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1475 "hardware queue!\n", __func__);
1479 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1483 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1485 struct ath5k_buf *bf, *bf0;
1488 * NB: this assumes output has been stopped and
1489 * we do not need to block ath5k_tx_tasklet
1491 spin_lock_bh(&txq->lock);
1492 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1493 ath5k_debug_printtxbuf(sc, bf, !sc->ah->ah_proc_tx_desc(sc->ah,
1496 ath5k_txbuf_free(sc, bf);
1498 spin_lock_bh(&sc->txbuflock);
1499 sc->tx_stats.data[txq->qnum].len--;
1500 list_move_tail(&bf->list, &sc->txbuf);
1502 spin_unlock_bh(&sc->txbuflock);
1505 spin_unlock_bh(&txq->lock);
1509 * Drain the transmit queues and reclaim resources.
1512 ath5k_txq_cleanup(struct ath5k_softc *sc)
1514 struct ath5k_hw *ah = sc->ah;
1517 /* XXX return value */
1518 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1519 /* don't touch the hardware if marked invalid */
1520 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1521 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1522 ath5k_hw_get_tx_buf(ah, sc->bhalq));
1523 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1524 if (sc->txqs[i].setup) {
1525 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1526 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1529 ath5k_hw_get_tx_buf(ah,
1534 ieee80211_start_queues(sc->hw); /* XXX move to callers */
1536 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1537 if (sc->txqs[i].setup)
1538 ath5k_txq_drainq(sc, &sc->txqs[i]);
1542 ath5k_txq_release(struct ath5k_softc *sc)
1544 struct ath5k_txq *txq = sc->txqs;
1547 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1549 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1562 * Enable the receive h/w following a reset.
1565 ath5k_rx_start(struct ath5k_softc *sc)
1567 struct ath5k_hw *ah = sc->ah;
1568 struct ath5k_buf *bf;
1571 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1573 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1574 sc->cachelsz, sc->rxbufsize);
1578 spin_lock_bh(&sc->rxbuflock);
1579 list_for_each_entry(bf, &sc->rxbuf, list) {
1580 ret = ath5k_rxbuf_setup(sc, bf);
1582 spin_unlock_bh(&sc->rxbuflock);
1586 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1587 spin_unlock_bh(&sc->rxbuflock);
1589 ath5k_hw_put_rx_buf(ah, bf->daddr);
1590 ath5k_hw_start_rx(ah); /* enable recv descriptors */
1591 ath5k_mode_setup(sc); /* set filters, etc. */
1592 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1600 * Disable the receive h/w in preparation for a reset.
1603 ath5k_rx_stop(struct ath5k_softc *sc)
1605 struct ath5k_hw *ah = sc->ah;
1607 ath5k_hw_stop_pcu_recv(ah); /* disable PCU */
1608 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1609 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1610 mdelay(3); /* 3ms is long enough for 1 frame */
1612 ath5k_debug_printrxbuffs(sc, ah);
1614 sc->rxlink = NULL; /* just in case */
1618 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1619 struct sk_buff *skb)
1621 struct ieee80211_hdr *hdr = (void *)skb->data;
1622 unsigned int keyix, hlen = ieee80211_get_hdrlen_from_skb(skb);
1624 if (!(ds->ds_rxstat.rs_status & AR5K_RXERR_DECRYPT) &&
1625 ds->ds_rxstat.rs_keyix != AR5K_RXKEYIX_INVALID)
1626 return RX_FLAG_DECRYPTED;
1628 /* Apparently when a default key is used to decrypt the packet
1629 the hw does not set the index used to decrypt. In such cases
1630 get the index from the packet. */
1631 if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED) &&
1632 !(ds->ds_rxstat.rs_status & AR5K_RXERR_DECRYPT) &&
1633 skb->len >= hlen + 4) {
1634 keyix = skb->data[hlen + 3] >> 6;
1636 if (test_bit(keyix, sc->keymap))
1637 return RX_FLAG_DECRYPTED;
1644 ath5k_tasklet_rx(unsigned long data)
1646 struct ieee80211_rx_status rxs = {};
1647 struct sk_buff *skb;
1648 struct ath5k_softc *sc = (void *)data;
1649 struct ath5k_buf *bf;
1650 struct ath5k_desc *ds;
1657 spin_lock(&sc->rxbuflock);
1659 if (unlikely(list_empty(&sc->rxbuf))) {
1660 ATH5K_WARN(sc, "empty rx buf pool\n");
1663 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1664 BUG_ON(bf->skb == NULL);
1668 /* TODO only one segment */
1669 pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr,
1670 sc->desc_len, PCI_DMA_FROMDEVICE);
1672 if (unlikely(ds->ds_link == bf->daddr)) /* this is the end */
1675 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds);
1676 if (unlikely(ret == -EINPROGRESS))
1678 else if (unlikely(ret)) {
1679 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1683 if (unlikely(ds->ds_rxstat.rs_more)) {
1684 ATH5K_WARN(sc, "unsupported jumbo\n");
1688 stat = ds->ds_rxstat.rs_status;
1689 if (unlikely(stat)) {
1690 if (stat & AR5K_RXERR_PHY)
1692 if (stat & AR5K_RXERR_DECRYPT) {
1694 * Decrypt error. If the error occurred
1695 * because there was no hardware key, then
1696 * let the frame through so the upper layers
1697 * can process it. This is necessary for 5210
1698 * parts which have no way to setup a ``clear''
1701 * XXX do key cache faulting
1703 if (ds->ds_rxstat.rs_keyix ==
1704 AR5K_RXKEYIX_INVALID &&
1705 !(stat & AR5K_RXERR_CRC))
1708 if (stat & AR5K_RXERR_MIC) {
1709 rxs.flag |= RX_FLAG_MMIC_ERROR;
1713 /* let crypto-error packets fall through in MNTR */
1714 if ((stat & ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1715 sc->opmode != IEEE80211_IF_TYPE_MNTR)
1719 len = ds->ds_rxstat.rs_datalen;
1720 pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr, len,
1721 PCI_DMA_FROMDEVICE);
1722 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1723 PCI_DMA_FROMDEVICE);
1729 * the hardware adds a padding to 4 byte boundaries between
1730 * the header and the payload data if the header length is
1731 * not multiples of 4 - remove it
1733 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1736 memmove(skb->data + pad, skb->data, hdrlen);
1740 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
1741 rxs.mactime = ath5k_extend_tsf(sc->ah,
1742 ds->ds_rxstat.rs_tstamp);
1744 rxs.mactime = ds->ds_rxstat.rs_tstamp;
1745 rxs.freq = sc->curchan->freq;
1746 rxs.channel = sc->curchan->chan;
1747 rxs.phymode = sc->curmode;
1751 * the names here are misleading and the usage of these
1752 * values by iwconfig makes it even worse
1754 /* noise floor in dBm, from the last noise calibration */
1755 rxs.noise = sc->ah->ah_noise_floor;
1756 /* signal level in dBm */
1757 rxs.ssi = rxs.noise + ds->ds_rxstat.rs_rssi;
1759 * "signal" is actually displayed as Link Quality by iwconfig
1760 * we provide a percentage based on rssi (assuming max rssi 64)
1762 rxs.signal = ds->ds_rxstat.rs_rssi * 100 / 64;
1764 rxs.antenna = ds->ds_rxstat.rs_antenna;
1765 rxs.rate = ds->ds_rxstat.rs_rate;
1766 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb);
1768 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1770 __ieee80211_rx(sc->hw, skb, &rxs);
1771 sc->led_rxrate = ds->ds_rxstat.rs_rate;
1772 ath5k_led_event(sc, ATH_LED_RX);
1774 list_move_tail(&bf->list, &sc->rxbuf);
1775 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1776 spin_unlock(&sc->rxbuflock);
1787 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1789 struct ieee80211_tx_status txs = {};
1790 struct ath5k_buf *bf, *bf0;
1791 struct ath5k_desc *ds;
1792 struct sk_buff *skb;
1795 spin_lock(&txq->lock);
1796 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1799 /* TODO only one segment */
1800 pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr,
1801 sc->desc_len, PCI_DMA_FROMDEVICE);
1802 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds);
1803 if (unlikely(ret == -EINPROGRESS))
1805 else if (unlikely(ret)) {
1806 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1813 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1816 txs.control = bf->ctl;
1817 txs.retry_count = ds->ds_txstat.ts_shortretry +
1818 ds->ds_txstat.ts_longretry / 6;
1819 if (unlikely(ds->ds_txstat.ts_status)) {
1820 sc->ll_stats.dot11ACKFailureCount++;
1821 if (ds->ds_txstat.ts_status & AR5K_TXERR_XRETRY)
1822 txs.excessive_retries = 1;
1823 else if (ds->ds_txstat.ts_status & AR5K_TXERR_FILT)
1824 txs.flags |= IEEE80211_TX_STATUS_TX_FILTERED;
1826 txs.flags |= IEEE80211_TX_STATUS_ACK;
1827 txs.ack_signal = ds->ds_txstat.ts_rssi;
1830 ieee80211_tx_status(sc->hw, skb, &txs);
1831 sc->tx_stats.data[txq->qnum].count++;
1833 spin_lock(&sc->txbuflock);
1834 sc->tx_stats.data[txq->qnum].len--;
1835 list_move_tail(&bf->list, &sc->txbuf);
1837 spin_unlock(&sc->txbuflock);
1839 if (likely(list_empty(&txq->q)))
1841 spin_unlock(&txq->lock);
1842 if (sc->txbuf_len > ATH_TXBUF / 5)
1843 ieee80211_wake_queues(sc->hw);
1847 ath5k_tasklet_tx(unsigned long data)
1849 struct ath5k_softc *sc = (void *)data;
1851 ath5k_tx_processq(sc, sc->txq);
1853 ath5k_led_event(sc, ATH_LED_TX);
1864 * Setup the beacon frame for transmit.
1867 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1868 struct ieee80211_tx_control *ctl)
1870 struct sk_buff *skb = bf->skb;
1871 struct ath5k_hw *ah = sc->ah;
1872 struct ath5k_desc *ds;
1873 int ret, antenna = 0;
1876 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1878 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1879 "skbaddr %llx\n", skb, skb->data, skb->len,
1880 (unsigned long long)bf->skbaddr);
1881 if (pci_dma_mapping_error(bf->skbaddr)) {
1882 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1888 flags = AR5K_TXDESC_NOACK;
1889 if (sc->opmode == IEEE80211_IF_TYPE_IBSS && ath5k_hw_hasveol(ah)) {
1890 ds->ds_link = bf->daddr; /* self-linked */
1891 flags |= AR5K_TXDESC_VEOL;
1893 * Let hardware handle antenna switching if txantenna is not set
1898 * Switch antenna every 4 beacons if txantenna is not set
1899 * XXX assumes two antennas
1902 antenna = sc->bsent & 4 ? 2 : 1;
1905 ds->ds_data = bf->skbaddr;
1906 ret = ah->ah_setup_tx_desc(ah, ds, skb->len + FCS_LEN,
1907 ieee80211_get_hdrlen_from_skb(skb),
1908 AR5K_PKT_TYPE_BEACON, (ctl->power_level * 2), ctl->tx_rate, 1,
1909 AR5K_TXKEYIX_INVALID, antenna, flags, 0, 0);
1915 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1920 * Transmit a beacon frame at SWBA. Dynamic updates to the
1921 * frame contents are done as needed and the slot time is
1922 * also adjusted based on current state.
1924 * this is usually called from interrupt context (ath5k_intr())
1925 * but also from ath5k_beacon_config() in IBSS mode which in turn
1926 * can be called from a tasklet and user context
1929 ath5k_beacon_send(struct ath5k_softc *sc)
1931 struct ath5k_buf *bf = sc->bbuf;
1932 struct ath5k_hw *ah = sc->ah;
1934 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON_PROC, "in beacon_send\n");
1936 if (unlikely(bf->skb == NULL || sc->opmode == IEEE80211_IF_TYPE_STA ||
1937 sc->opmode == IEEE80211_IF_TYPE_MNTR)) {
1938 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1942 * Check if the previous beacon has gone out. If
1943 * not don't don't try to post another, skip this
1944 * period and wait for the next. Missed beacons
1945 * indicate a problem and should not occur. If we
1946 * miss too many consecutive beacons reset the device.
1948 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1950 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON_PROC,
1951 "missed %u consecutive beacons\n", sc->bmisscount);
1952 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
1953 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON_PROC,
1954 "stuck beacon time (%u missed)\n",
1956 tasklet_schedule(&sc->restq);
1960 if (unlikely(sc->bmisscount != 0)) {
1961 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON_PROC,
1962 "resume beacon xmit after %u misses\n",
1968 * Stop any current dma and put the new frame on the queue.
1969 * This should never fail since we check above that no frames
1970 * are still pending on the queue.
1972 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
1973 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
1974 /* NB: hw still stops DMA, so proceed */
1976 pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr, bf->skb->len,
1979 ath5k_hw_put_tx_buf(ah, sc->bhalq, bf->daddr);
1980 ath5k_hw_tx_start(ah, sc->bhalq);
1981 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON_PROC, "TXDP[%u] = %llx (%p)\n",
1982 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
1989 * ath5k_beacon_update_timers - update beacon timers
1991 * @sc: struct ath5k_softc pointer we are operating on
1992 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1993 * beacon timer update based on the current HW TSF.
1995 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
1996 * of a received beacon or the current local hardware TSF and write it to the
1997 * beacon timer registers.
1999 * This is called in a variety of situations, e.g. when a beacon is received,
2000 * when a HW merge has been detected, but also when an new IBSS is created or
2001 * when we otherwise know we have to update the timers, but we keep it in this
2002 * function to have it all together in one place.
2005 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2007 struct ath5k_hw *ah = sc->ah;
2008 u32 nexttbtt, intval, hw_tu, bc_tu;
2011 intval = sc->bintval & AR5K_BEACON_PERIOD;
2012 if (WARN_ON(!intval))
2015 /* beacon TSF converted to TU */
2016 bc_tu = TSF_TO_TU(bc_tsf);
2018 /* current TSF converted to TU */
2019 hw_tsf = ath5k_hw_get_tsf64(ah);
2020 hw_tu = TSF_TO_TU(hw_tsf);
2023 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2026 * no beacons received, called internally.
2027 * just need to refresh timers based on HW TSF.
2029 nexttbtt = roundup(hw_tu + FUDGE, intval);
2030 } else if (bc_tsf == 0) {
2032 * no beacon received, probably called by ath5k_reset_tsf().
2033 * reset TSF to start with 0.
2036 intval |= AR5K_BEACON_RESET_TSF;
2037 } else if (bc_tsf > hw_tsf) {
2039 * beacon received, SW merge happend but HW TSF not yet updated.
2040 * not possible to reconfigure timers yet, but next time we
2041 * receive a beacon with the same BSSID, the hardware will
2042 * automatically update the TSF and then we need to reconfigure
2045 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2046 "need to wait for HW TSF sync\n");
2050 * most important case for beacon synchronization between STA.
2052 * beacon received and HW TSF has been already updated by HW.
2053 * update next TBTT based on the TSF of the beacon, but make
2054 * sure it is ahead of our local TSF timer.
2056 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2060 intval |= AR5K_BEACON_ENA;
2061 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2064 * debugging output last in order to preserve the time critical aspect
2068 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2069 "reconfigured timers based on HW TSF\n");
2070 else if (bc_tsf == 0)
2071 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2072 "reset HW TSF and timers\n");
2074 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2075 "updated timers based on beacon TSF\n");
2077 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2078 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2079 bc_tsf, hw_tsf, bc_tu, hw_tu, nexttbtt);
2080 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2081 intval & AR5K_BEACON_PERIOD,
2082 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2083 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2088 * Configure the beacon timers and interrupts based on the operating mode
2090 * When operating in station mode we want to receive a BMISS interrupt when we
2091 * stop seeing beacons from the AP we've associated with so we can look for
2092 * another AP to associate with.
2094 * In IBSS mode we need to configure the beacon timers and use a self-linked tx
2095 * descriptor if possible. If the hardware cannot deal with that we enable SWBA
2096 * interrupts to send the beacons from the interrupt handler.
2099 ath5k_beacon_config(struct ath5k_softc *sc)
2101 struct ath5k_hw *ah = sc->ah;
2103 ath5k_hw_set_intr(ah, 0);
2106 if (sc->opmode == IEEE80211_IF_TYPE_STA) {
2107 sc->imask |= AR5K_INT_BMISS;
2108 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2110 * In IBSS mode enable the beacon timers but only enable SWBA
2111 * interrupts if we need to manually prepare beacon frames.
2112 * Otherwise we use a self-linked tx descriptor and let the
2113 * hardware deal with things. In that case we have to load it
2116 ath5k_beaconq_config(sc);
2118 if (!ath5k_hw_hasveol(ah))
2119 sc->imask |= AR5K_INT_SWBA;
2121 ath5k_beacon_send(sc);
2125 ath5k_hw_set_intr(ah, sc->imask);
2129 /********************\
2130 * Interrupt handling *
2131 \********************/
2134 ath5k_init(struct ath5k_softc *sc)
2138 mutex_lock(&sc->lock);
2140 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2143 * Stop anything previously setup. This is safe
2144 * no matter this is the first time through or not.
2146 ath5k_stop_locked(sc);
2149 * The basic interface to setting the hardware in a good
2150 * state is ``reset''. On return the hardware is known to
2151 * be powered up and with interrupts disabled. This must
2152 * be followed by initialization of the appropriate bits
2153 * and then setup of the interrupt mask.
2155 sc->curchan = sc->hw->conf.chan;
2156 ret = ath5k_hw_reset(sc->ah, sc->opmode, sc->curchan, false);
2158 ATH5K_ERR(sc, "unable to reset hardware: %d\n", ret);
2162 * This is needed only to setup initial state
2163 * but it's best done after a reset.
2165 ath5k_hw_set_txpower_limit(sc->ah, 0);
2168 * Setup the hardware after reset: the key cache
2169 * is filled as needed and the receive engine is
2170 * set going. Frame transmit is handled entirely
2171 * in the frame output path; there's nothing to do
2172 * here except setup the interrupt mask.
2174 ret = ath5k_rx_start(sc);
2179 * Enable interrupts.
2181 sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL |
2182 AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL;
2184 ath5k_hw_set_intr(sc->ah, sc->imask);
2185 /* Set ack to be sent at low bit-rates */
2186 ath5k_hw_set_ack_bitrate_high(sc->ah, false);
2188 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2189 msecs_to_jiffies(ath5k_calinterval * 1000)));
2193 mutex_unlock(&sc->lock);
2198 ath5k_stop_locked(struct ath5k_softc *sc)
2200 struct ath5k_hw *ah = sc->ah;
2202 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2203 test_bit(ATH_STAT_INVALID, sc->status));
2206 * Shutdown the hardware and driver:
2207 * stop output from above
2208 * disable interrupts
2210 * turn off the radio
2211 * clear transmit machinery
2212 * clear receive machinery
2213 * drain and release tx queues
2214 * reclaim beacon resources
2215 * power down hardware
2217 * Note that some of this work is not possible if the
2218 * hardware is gone (invalid).
2220 ieee80211_stop_queues(sc->hw);
2222 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2223 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2224 del_timer_sync(&sc->led_tim);
2225 ath5k_hw_set_gpio(ah, sc->led_pin, !sc->led_on);
2226 __clear_bit(ATH_STAT_LEDBLINKING, sc->status);
2228 ath5k_hw_set_intr(ah, 0);
2230 ath5k_txq_cleanup(sc);
2231 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2233 ath5k_hw_phy_disable(ah);
2241 * Stop the device, grabbing the top-level lock to protect
2242 * against concurrent entry through ath5k_init (which can happen
2243 * if another thread does a system call and the thread doing the
2244 * stop is preempted).
2247 ath5k_stop_hw(struct ath5k_softc *sc)
2251 mutex_lock(&sc->lock);
2252 ret = ath5k_stop_locked(sc);
2253 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2255 * Set the chip in full sleep mode. Note that we are
2256 * careful to do this only when bringing the interface
2257 * completely to a stop. When the chip is in this state
2258 * it must be carefully woken up or references to
2259 * registers in the PCI clock domain may freeze the bus
2260 * (and system). This varies by chip and is mostly an
2261 * issue with newer parts that go to sleep more quickly.
2263 if (sc->ah->ah_mac_srev >= 0x78) {
2266 * don't put newer MAC revisions > 7.8 to sleep because
2267 * of the above mentioned problems
2269 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2270 "not putting device to sleep\n");
2272 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2273 "putting device to full sleep\n");
2274 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2277 ath5k_txbuf_free(sc, sc->bbuf);
2278 mutex_unlock(&sc->lock);
2280 del_timer_sync(&sc->calib_tim);
2286 ath5k_intr(int irq, void *dev_id)
2288 struct ath5k_softc *sc = dev_id;
2289 struct ath5k_hw *ah = sc->ah;
2290 enum ath5k_int status;
2291 unsigned int counter = 1000;
2293 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2294 !ath5k_hw_is_intr_pending(ah)))
2299 * Figure out the reason(s) for the interrupt. Note
2300 * that get_isr returns a pseudo-ISR that may include
2301 * bits we haven't explicitly enabled so we mask the
2302 * value to insure we only process bits we requested.
2304 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2305 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2307 status &= sc->imask; /* discard unasked for bits */
2308 if (unlikely(status & AR5K_INT_FATAL)) {
2310 * Fatal errors are unrecoverable.
2311 * Typically these are caused by DMA errors.
2313 tasklet_schedule(&sc->restq);
2314 } else if (unlikely(status & AR5K_INT_RXORN)) {
2315 tasklet_schedule(&sc->restq);
2317 if (status & AR5K_INT_SWBA) {
2319 * Software beacon alert--time to send a beacon.
2320 * Handle beacon transmission directly; deferring
2321 * this is too slow to meet timing constraints
2324 ath5k_beacon_send(sc);
2326 if (status & AR5K_INT_RXEOL) {
2328 * NB: the hardware should re-read the link when
2329 * RXE bit is written, but it doesn't work at
2330 * least on older hardware revs.
2334 if (status & AR5K_INT_TXURN) {
2335 /* bump tx trigger level */
2336 ath5k_hw_update_tx_triglevel(ah, true);
2338 if (status & AR5K_INT_RX)
2339 tasklet_schedule(&sc->rxtq);
2340 if (status & AR5K_INT_TX)
2341 tasklet_schedule(&sc->txtq);
2342 if (status & AR5K_INT_BMISS) {
2344 if (status & AR5K_INT_MIB) {
2348 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2350 if (unlikely(!counter))
2351 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2357 ath5k_tasklet_reset(unsigned long data)
2359 struct ath5k_softc *sc = (void *)data;
2361 ath5k_reset(sc->hw);
2365 * Periodically recalibrate the PHY to account
2366 * for temperature/environment changes.
2369 ath5k_calibrate(unsigned long data)
2371 struct ath5k_softc *sc = (void *)data;
2372 struct ath5k_hw *ah = sc->ah;
2374 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2375 sc->curchan->chan, sc->curchan->val);
2377 if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2379 * Rfgain is out of bounds, reset the chip
2380 * to load new gain values.
2382 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2383 ath5k_reset(sc->hw);
2385 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2386 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2389 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2390 msecs_to_jiffies(ath5k_calinterval * 1000)));
2400 ath5k_led_off(unsigned long data)
2402 struct ath5k_softc *sc = (void *)data;
2404 if (test_bit(ATH_STAT_LEDENDBLINK, sc->status))
2405 __clear_bit(ATH_STAT_LEDBLINKING, sc->status);
2407 __set_bit(ATH_STAT_LEDENDBLINK, sc->status);
2408 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2409 mod_timer(&sc->led_tim, jiffies + sc->led_off);
2414 * Blink the LED according to the specified on/off times.
2417 ath5k_led_blink(struct ath5k_softc *sc, unsigned int on,
2420 ATH5K_DBG(sc, ATH5K_DEBUG_LED, "on %u off %u\n", on, off);
2421 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
2422 __set_bit(ATH_STAT_LEDBLINKING, sc->status);
2423 __clear_bit(ATH_STAT_LEDENDBLINK, sc->status);
2425 mod_timer(&sc->led_tim, jiffies + on);
2429 ath5k_led_event(struct ath5k_softc *sc, int event)
2431 if (likely(!test_bit(ATH_STAT_LEDSOFT, sc->status)))
2433 if (unlikely(test_bit(ATH_STAT_LEDBLINKING, sc->status)))
2434 return; /* don't interrupt active blink */
2437 ath5k_led_blink(sc, sc->hwmap[sc->led_txrate].ledon,
2438 sc->hwmap[sc->led_txrate].ledoff);
2441 ath5k_led_blink(sc, sc->hwmap[sc->led_rxrate].ledon,
2442 sc->hwmap[sc->led_rxrate].ledoff);
2450 /********************\
2451 * Mac80211 functions *
2452 \********************/
2455 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
2456 struct ieee80211_tx_control *ctl)
2458 struct ath5k_softc *sc = hw->priv;
2459 struct ath5k_buf *bf;
2460 unsigned long flags;
2464 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2466 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2467 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2470 * the hardware expects the header padded to 4 byte boundaries
2471 * if this is not the case we add the padding after the header
2473 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2476 if (skb_headroom(skb) < pad) {
2477 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2478 " headroom to pad %d\n", hdrlen, pad);
2482 memmove(skb->data, skb->data+pad, hdrlen);
2485 sc->led_txrate = ctl->tx_rate;
2487 spin_lock_irqsave(&sc->txbuflock, flags);
2488 if (list_empty(&sc->txbuf)) {
2489 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2490 spin_unlock_irqrestore(&sc->txbuflock, flags);
2491 ieee80211_stop_queue(hw, ctl->queue);
2494 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2495 list_del(&bf->list);
2497 if (list_empty(&sc->txbuf))
2498 ieee80211_stop_queues(hw);
2499 spin_unlock_irqrestore(&sc->txbuflock, flags);
2503 if (ath5k_txbuf_setup(sc, bf, ctl)) {
2505 spin_lock_irqsave(&sc->txbuflock, flags);
2506 list_add_tail(&bf->list, &sc->txbuf);
2508 spin_unlock_irqrestore(&sc->txbuflock, flags);
2509 dev_kfree_skb_any(skb);
2517 ath5k_reset(struct ieee80211_hw *hw)
2519 struct ath5k_softc *sc = hw->priv;
2520 struct ath5k_hw *ah = sc->ah;
2523 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2525 * Convert to a hw channel description with the flags
2526 * constrained to reflect the current operating mode.
2528 sc->curchan = hw->conf.chan;
2530 ath5k_hw_set_intr(ah, 0);
2531 ath5k_txq_cleanup(sc);
2534 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
2535 if (unlikely(ret)) {
2536 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2539 ath5k_hw_set_txpower_limit(sc->ah, 0);
2541 ret = ath5k_rx_start(sc);
2542 if (unlikely(ret)) {
2543 ATH5K_ERR(sc, "can't start recv logic\n");
2547 * We may be doing a reset in response to an ioctl
2548 * that changes the channel so update any state that
2549 * might change as a result.
2553 /* ath5k_chan_change(sc, c); */
2554 ath5k_beacon_config(sc);
2555 /* intrs are started by ath5k_beacon_config */
2557 ieee80211_wake_queues(hw);
2564 static int ath5k_start(struct ieee80211_hw *hw)
2566 return ath5k_init(hw->priv);
2569 static void ath5k_stop(struct ieee80211_hw *hw)
2571 ath5k_stop_hw(hw->priv);
2574 static int ath5k_add_interface(struct ieee80211_hw *hw,
2575 struct ieee80211_if_init_conf *conf)
2577 struct ath5k_softc *sc = hw->priv;
2580 mutex_lock(&sc->lock);
2586 sc->vif = conf->vif;
2588 switch (conf->type) {
2589 case IEEE80211_IF_TYPE_STA:
2590 case IEEE80211_IF_TYPE_IBSS:
2591 case IEEE80211_IF_TYPE_MNTR:
2592 sc->opmode = conf->type;
2600 mutex_unlock(&sc->lock);
2605 ath5k_remove_interface(struct ieee80211_hw *hw,
2606 struct ieee80211_if_init_conf *conf)
2608 struct ath5k_softc *sc = hw->priv;
2610 mutex_lock(&sc->lock);
2611 if (sc->vif != conf->vif)
2616 mutex_unlock(&sc->lock);
2620 ath5k_config(struct ieee80211_hw *hw,
2621 struct ieee80211_conf *conf)
2623 struct ath5k_softc *sc = hw->priv;
2625 sc->bintval = conf->beacon_int;
2626 ath5k_setcurmode(sc, conf->phymode);
2628 return ath5k_chan_set(sc, conf->chan);
2632 ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2633 struct ieee80211_if_conf *conf)
2635 struct ath5k_softc *sc = hw->priv;
2636 struct ath5k_hw *ah = sc->ah;
2639 /* Set to a reasonable value. Note that this will
2640 * be set to mac80211's value at ath5k_config(). */
2642 mutex_lock(&sc->lock);
2643 if (sc->vif != vif) {
2648 /* Cache for later use during resets */
2649 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2650 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2651 * a clean way of letting us retrieve this yet. */
2652 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
2654 mutex_unlock(&sc->lock);
2656 return ath5k_reset(hw);
2658 mutex_unlock(&sc->lock);
2662 #define SUPPORTED_FIF_FLAGS \
2663 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2664 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2665 FIF_BCN_PRBRESP_PROMISC
2667 * o always accept unicast, broadcast, and multicast traffic
2668 * o multicast traffic for all BSSIDs will be enabled if mac80211
2670 * o maintain current state of phy ofdm or phy cck error reception.
2671 * If the hardware detects any of these type of errors then
2672 * ath5k_hw_get_rx_filter() will pass to us the respective
2673 * hardware filters to be able to receive these type of frames.
2674 * o probe request frames are accepted only when operating in
2675 * hostap, adhoc, or monitor modes
2676 * o enable promiscuous mode according to the interface state
2678 * - when operating in adhoc mode so the 802.11 layer creates
2679 * node table entries for peers,
2680 * - when operating in station mode for collecting rssi data when
2681 * the station is otherwise quiet, or
2684 static void ath5k_configure_filter(struct ieee80211_hw *hw,
2685 unsigned int changed_flags,
2686 unsigned int *new_flags,
2687 int mc_count, struct dev_mc_list *mclist)
2689 struct ath5k_softc *sc = hw->priv;
2690 struct ath5k_hw *ah = sc->ah;
2691 u32 mfilt[2], val, rfilt;
2698 /* Only deal with supported flags */
2699 changed_flags &= SUPPORTED_FIF_FLAGS;
2700 *new_flags &= SUPPORTED_FIF_FLAGS;
2702 /* If HW detects any phy or radar errors, leave those filters on.
2703 * Also, always enable Unicast, Broadcasts and Multicast
2704 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2705 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2706 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2707 AR5K_RX_FILTER_MCAST);
2709 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2710 if (*new_flags & FIF_PROMISC_IN_BSS) {
2711 rfilt |= AR5K_RX_FILTER_PROM;
2712 __set_bit(ATH_STAT_PROMISC, sc->status);
2715 __clear_bit(ATH_STAT_PROMISC, sc->status);
2718 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2719 if (*new_flags & FIF_ALLMULTI) {
2723 for (i = 0; i < mc_count; i++) {
2726 /* calculate XOR of eight 6-bit values */
2727 val = LE_READ_4(mclist->dmi_addr + 0);
2728 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2729 val = LE_READ_4(mclist->dmi_addr + 3);
2730 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2732 mfilt[pos / 32] |= (1 << (pos % 32));
2733 /* XXX: we might be able to just do this instead,
2734 * but not sure, needs testing, if we do use this we'd
2735 * neet to inform below to not reset the mcast */
2736 /* ath5k_hw_set_mcast_filterindex(ah,
2737 * mclist->dmi_addr[5]); */
2738 mclist = mclist->next;
2742 /* This is the best we can do */
2743 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2744 rfilt |= AR5K_RX_FILTER_PHYERR;
2746 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2747 * and probes for any BSSID, this needs testing */
2748 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2749 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2751 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2752 * set we should only pass on control frames for this
2753 * station. This needs testing. I believe right now this
2754 * enables *all* control frames, which is OK.. but
2755 * but we should see if we can improve on granularity */
2756 if (*new_flags & FIF_CONTROL)
2757 rfilt |= AR5K_RX_FILTER_CONTROL;
2759 /* Additional settings per mode -- this is per ath5k */
2761 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2763 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2764 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2765 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2766 if (sc->opmode != IEEE80211_IF_TYPE_STA)
2767 rfilt |= AR5K_RX_FILTER_PROBEREQ;
2768 if (sc->opmode != IEEE80211_IF_TYPE_AP &&
2769 test_bit(ATH_STAT_PROMISC, sc->status))
2770 rfilt |= AR5K_RX_FILTER_PROM;
2771 if (sc->opmode == IEEE80211_IF_TYPE_STA ||
2772 sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2773 rfilt |= AR5K_RX_FILTER_BEACON;
2777 ath5k_hw_set_rx_filter(ah,rfilt);
2779 /* Set multicast bits */
2780 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2781 /* Set the cached hw filter flags, this will alter actually
2783 sc->filter_flags = rfilt;
2787 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2788 const u8 *local_addr, const u8 *addr,
2789 struct ieee80211_key_conf *key)
2791 struct ath5k_softc *sc = hw->priv;
2805 mutex_lock(&sc->lock);
2809 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr);
2811 ATH5K_ERR(sc, "can't set the key\n");
2814 __set_bit(key->keyidx, sc->keymap);
2815 key->hw_key_idx = key->keyidx;
2818 ath5k_hw_reset_key(sc->ah, key->keyidx);
2819 __clear_bit(key->keyidx, sc->keymap);
2827 mutex_unlock(&sc->lock);
2832 ath5k_get_stats(struct ieee80211_hw *hw,
2833 struct ieee80211_low_level_stats *stats)
2835 struct ath5k_softc *sc = hw->priv;
2837 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
2843 ath5k_get_tx_stats(struct ieee80211_hw *hw,
2844 struct ieee80211_tx_queue_stats *stats)
2846 struct ath5k_softc *sc = hw->priv;
2848 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
2854 ath5k_get_tsf(struct ieee80211_hw *hw)
2856 struct ath5k_softc *sc = hw->priv;
2858 return ath5k_hw_get_tsf64(sc->ah);
2862 ath5k_reset_tsf(struct ieee80211_hw *hw)
2864 struct ath5k_softc *sc = hw->priv;
2867 * in IBSS mode we need to update the beacon timers too.
2868 * this will also reset the TSF if we call it with 0
2870 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
2871 ath5k_beacon_update_timers(sc, 0);
2873 ath5k_hw_reset_tsf(sc->ah);
2877 ath5k_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
2878 struct ieee80211_tx_control *ctl)
2880 struct ath5k_softc *sc = hw->priv;
2883 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
2885 mutex_lock(&sc->lock);
2887 if (sc->opmode != IEEE80211_IF_TYPE_IBSS) {
2892 ath5k_txbuf_free(sc, sc->bbuf);
2893 sc->bbuf->skb = skb;
2894 ret = ath5k_beacon_setup(sc, sc->bbuf, ctl);
2896 sc->bbuf->skb = NULL;
2898 ath5k_beacon_config(sc);
2901 mutex_unlock(&sc->lock);