2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define TIME_SYMBOLS(t) ((t) >> 2)
33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
38 static u16 bits_per_symbol[][2] = {
40 { 26, 54 }, /* 0: BPSK */
41 { 52, 108 }, /* 1: QPSK 1/2 */
42 { 78, 162 }, /* 2: QPSK 3/4 */
43 { 104, 216 }, /* 3: 16-QAM 1/2 */
44 { 156, 324 }, /* 4: 16-QAM 3/4 */
45 { 208, 432 }, /* 5: 64-QAM 2/3 */
46 { 234, 486 }, /* 6: 64-QAM 3/4 */
47 { 260, 540 }, /* 7: 64-QAM 5/6 */
50 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
52 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
53 struct ath_atx_tid *tid, struct sk_buff *skb);
54 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
55 int tx_flags, struct ath_txq *txq);
56 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
57 struct ath_txq *txq, struct list_head *bf_q,
58 struct ath_tx_status *ts, int txok);
59 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
60 struct list_head *head, bool internal);
61 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
62 struct ath_tx_status *ts, int nframes, int nbad,
64 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
66 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
68 struct ath_atx_tid *tid,
78 /*********************/
79 /* Aggregation logic */
80 /*********************/
82 void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq)
83 __acquires(&txq->axq_lock)
85 spin_lock_bh(&txq->axq_lock);
88 void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq)
89 __releases(&txq->axq_lock)
91 spin_unlock_bh(&txq->axq_lock);
94 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
95 __releases(&txq->axq_lock)
97 struct sk_buff_head q;
100 __skb_queue_head_init(&q);
101 skb_queue_splice_init(&txq->complete_q, &q);
102 spin_unlock_bh(&txq->axq_lock);
104 while ((skb = __skb_dequeue(&q)))
105 ieee80211_tx_status(sc->hw, skb);
108 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
110 struct ath_atx_ac *ac = tid->ac;
119 list_add_tail(&tid->list, &ac->tid_q);
125 list_add_tail(&ac->list, &txq->axq_acq);
128 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
130 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
131 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
132 sizeof(tx_info->rate_driver_data));
133 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
136 static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
141 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
142 seqno << IEEE80211_SEQ_SEQ_SHIFT);
145 static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta,
148 ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates,
149 ARRAY_SIZE(bf->rates));
152 static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq,
157 q = skb_get_queue_mapping(skb);
158 if (txq == sc->tx.uapsdq)
159 txq = sc->tx.txq_map[q];
161 if (txq != sc->tx.txq_map[q])
164 if (WARN_ON(--txq->pending_frames < 0))
165 txq->pending_frames = 0;
168 txq->pending_frames < sc->tx.txq_max_pending[q]) {
169 ieee80211_wake_queue(sc->hw, q);
170 txq->stopped = false;
174 static struct ath_atx_tid *
175 ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb)
177 struct ieee80211_hdr *hdr;
180 hdr = (struct ieee80211_hdr *) skb->data;
181 if (ieee80211_is_data_qos(hdr->frame_control))
182 tidno = ieee80211_get_qos_ctl(hdr)[0];
184 tidno &= IEEE80211_QOS_CTL_TID_MASK;
185 return ATH_AN_2_TID(an, tidno);
188 static bool ath_tid_has_buffered(struct ath_atx_tid *tid)
190 return !skb_queue_empty(&tid->buf_q) || !skb_queue_empty(&tid->retry_q);
193 static struct sk_buff *ath_tid_dequeue(struct ath_atx_tid *tid)
197 skb = __skb_dequeue(&tid->retry_q);
199 skb = __skb_dequeue(&tid->buf_q);
205 * ath_tx_tid_change_state:
206 * - clears a-mpdu flag of previous session
207 * - force sequence number allocation to fix next BlockAck Window
210 ath_tx_tid_change_state(struct ath_softc *sc, struct ath_atx_tid *tid)
212 struct ath_txq *txq = tid->ac->txq;
213 struct ieee80211_tx_info *tx_info;
214 struct sk_buff *skb, *tskb;
216 struct ath_frame_info *fi;
218 skb_queue_walk_safe(&tid->buf_q, skb, tskb) {
219 fi = get_frame_info(skb);
222 tx_info = IEEE80211_SKB_CB(skb);
223 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU;
228 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
230 __skb_unlink(skb, &tid->buf_q);
231 ath_txq_skb_done(sc, txq, skb);
232 ieee80211_free_txskb(sc->hw, skb);
239 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
241 struct ath_txq *txq = tid->ac->txq;
244 struct list_head bf_head;
245 struct ath_tx_status ts;
246 struct ath_frame_info *fi;
247 bool sendbar = false;
249 INIT_LIST_HEAD(&bf_head);
251 memset(&ts, 0, sizeof(ts));
253 while ((skb = __skb_dequeue(&tid->retry_q))) {
254 fi = get_frame_info(skb);
257 ath_txq_skb_done(sc, txq, skb);
258 ieee80211_free_txskb(sc->hw, skb);
262 if (fi->baw_tracked) {
263 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
267 list_add_tail(&bf->list, &bf_head);
268 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
272 ath_txq_unlock(sc, txq);
273 ath_send_bar(tid, tid->seq_start);
274 ath_txq_lock(sc, txq);
278 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
283 index = ATH_BA_INDEX(tid->seq_start, seqno);
284 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
286 __clear_bit(cindex, tid->tx_buf);
288 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
289 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
290 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
291 if (tid->bar_index >= 0)
296 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
299 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
300 u16 seqno = bf->bf_state.seqno;
303 index = ATH_BA_INDEX(tid->seq_start, seqno);
304 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
305 __set_bit(cindex, tid->tx_buf);
308 if (index >= ((tid->baw_tail - tid->baw_head) &
309 (ATH_TID_MAX_BUFS - 1))) {
310 tid->baw_tail = cindex;
311 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
316 * TODO: For frame(s) that are in the retry state, we will reuse the
317 * sequence number(s) without setting the retry bit. The
318 * alternative is to give up on these and BAR the receiver's window
321 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
322 struct ath_atx_tid *tid)
327 struct list_head bf_head;
328 struct ath_tx_status ts;
329 struct ath_frame_info *fi;
331 memset(&ts, 0, sizeof(ts));
332 INIT_LIST_HEAD(&bf_head);
334 while ((skb = ath_tid_dequeue(tid))) {
335 fi = get_frame_info(skb);
339 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
343 list_add_tail(&bf->list, &bf_head);
345 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
346 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
349 tid->seq_next = tid->seq_start;
350 tid->baw_tail = tid->baw_head;
354 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
355 struct sk_buff *skb, int count)
357 struct ath_frame_info *fi = get_frame_info(skb);
358 struct ath_buf *bf = fi->bf;
359 struct ieee80211_hdr *hdr;
360 int prev = fi->retries;
362 TX_STAT_INC(txq->axq_qnum, a_retries);
363 fi->retries += count;
368 hdr = (struct ieee80211_hdr *)skb->data;
369 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
370 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
371 sizeof(*hdr), DMA_TO_DEVICE);
374 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
376 struct ath_buf *bf = NULL;
378 spin_lock_bh(&sc->tx.txbuflock);
380 if (unlikely(list_empty(&sc->tx.txbuf))) {
381 spin_unlock_bh(&sc->tx.txbuflock);
385 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
388 spin_unlock_bh(&sc->tx.txbuflock);
393 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
395 spin_lock_bh(&sc->tx.txbuflock);
396 list_add_tail(&bf->list, &sc->tx.txbuf);
397 spin_unlock_bh(&sc->tx.txbuflock);
400 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
404 tbf = ath_tx_get_buffer(sc);
408 ATH_TXBUF_RESET(tbf);
410 tbf->bf_mpdu = bf->bf_mpdu;
411 tbf->bf_buf_addr = bf->bf_buf_addr;
412 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
413 tbf->bf_state = bf->bf_state;
418 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
419 struct ath_tx_status *ts, int txok,
420 int *nframes, int *nbad)
422 struct ath_frame_info *fi;
424 u32 ba[WME_BA_BMP_SIZE >> 5];
431 isaggr = bf_isaggr(bf);
433 seq_st = ts->ts_seqnum;
434 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
438 fi = get_frame_info(bf->bf_mpdu);
439 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
442 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
450 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
451 struct ath_buf *bf, struct list_head *bf_q,
452 struct ath_tx_status *ts, int txok)
454 struct ath_node *an = NULL;
456 struct ieee80211_sta *sta;
457 struct ieee80211_hw *hw = sc->hw;
458 struct ieee80211_hdr *hdr;
459 struct ieee80211_tx_info *tx_info;
460 struct ath_atx_tid *tid = NULL;
461 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
462 struct list_head bf_head;
463 struct sk_buff_head bf_pending;
464 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
465 u32 ba[WME_BA_BMP_SIZE >> 5];
466 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
467 bool rc_update = true, isba;
468 struct ieee80211_tx_rate rates[4];
469 struct ath_frame_info *fi;
471 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
476 hdr = (struct ieee80211_hdr *)skb->data;
478 tx_info = IEEE80211_SKB_CB(skb);
480 memcpy(rates, bf->rates, sizeof(rates));
482 retries = ts->ts_longretry + 1;
483 for (i = 0; i < ts->ts_rateindex; i++)
484 retries += rates[i].count;
488 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
492 INIT_LIST_HEAD(&bf_head);
494 bf_next = bf->bf_next;
496 if (!bf->bf_stale || bf_next != NULL)
497 list_move_tail(&bf->list, &bf_head);
499 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 0);
506 an = (struct ath_node *)sta->drv_priv;
507 tid = ath_get_skb_tid(sc, an, skb);
508 seq_first = tid->seq_start;
509 isba = ts->ts_flags & ATH9K_TX_BA;
512 * The hardware occasionally sends a tx status for the wrong TID.
513 * In this case, the BA status cannot be considered valid and all
514 * subframes need to be retransmitted
516 * Only BlockAcks have a TID and therefore normal Acks cannot be
519 if (isba && tid->tidno != ts->tid)
522 isaggr = bf_isaggr(bf);
523 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
525 if (isaggr && txok) {
526 if (ts->ts_flags & ATH9K_TX_BA) {
527 seq_st = ts->ts_seqnum;
528 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
531 * AR5416 can become deaf/mute when BA
532 * issue happens. Chip needs to be reset.
533 * But AP code may have sychronization issues
534 * when perform internal reset in this routine.
535 * Only enable reset in STA mode for now.
537 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
542 __skb_queue_head_init(&bf_pending);
544 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
546 u16 seqno = bf->bf_state.seqno;
548 txfail = txpending = sendbar = 0;
549 bf_next = bf->bf_next;
552 tx_info = IEEE80211_SKB_CB(skb);
553 fi = get_frame_info(skb);
555 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) ||
558 * Outside of the current BlockAck window,
559 * maybe part of a previous session
562 } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
563 /* transmit completion, subframe is
564 * acked by block ack */
566 } else if (!isaggr && txok) {
567 /* transmit completion */
571 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
572 if (txok || !an->sleeping)
573 ath_tx_set_retry(sc, txq, bf->bf_mpdu,
580 bar_index = max_t(int, bar_index,
581 ATH_BA_INDEX(seq_first, seqno));
585 * Make sure the last desc is reclaimed if it
586 * not a holding desc.
588 INIT_LIST_HEAD(&bf_head);
589 if (bf_next != NULL || !bf_last->bf_stale)
590 list_move_tail(&bf->list, &bf_head);
594 * complete the acked-ones/xretried ones; update
597 ath_tx_update_baw(sc, tid, seqno);
599 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
600 memcpy(tx_info->control.rates, rates, sizeof(rates));
601 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
605 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
608 if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) {
609 tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP;
610 ieee80211_sta_eosp(sta);
612 /* retry the un-acked ones */
613 if (bf->bf_next == NULL && bf_last->bf_stale) {
616 tbf = ath_clone_txbuf(sc, bf_last);
618 * Update tx baw and complete the
619 * frame with failed status if we
623 ath_tx_update_baw(sc, tid, seqno);
625 ath_tx_complete_buf(sc, bf, txq,
627 bar_index = max_t(int, bar_index,
628 ATH_BA_INDEX(seq_first, seqno));
636 * Put this buffer to the temporary pending
637 * queue to retain ordering
639 __skb_queue_tail(&bf_pending, skb);
645 /* prepend un-acked frames to the beginning of the pending frame queue */
646 if (!skb_queue_empty(&bf_pending)) {
648 ieee80211_sta_set_buffered(sta, tid->tidno, true);
650 skb_queue_splice_tail(&bf_pending, &tid->retry_q);
652 ath_tx_queue_tid(txq, tid);
654 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
655 tid->ac->clear_ps_filter = true;
659 if (bar_index >= 0) {
660 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
662 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
663 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
665 ath_txq_unlock(sc, txq);
666 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
667 ath_txq_lock(sc, txq);
673 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
676 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
678 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
679 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
682 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
683 struct ath_tx_status *ts, struct ath_buf *bf,
684 struct list_head *bf_head)
686 struct ieee80211_tx_info *info;
689 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
690 flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
691 txq->axq_tx_inprogress = false;
694 if (bf_is_ampdu_not_probing(bf))
695 txq->axq_ampdu_depth--;
697 if (!bf_isampdu(bf)) {
699 info = IEEE80211_SKB_CB(bf->bf_mpdu);
700 memcpy(info->control.rates, bf->rates,
701 sizeof(info->control.rates));
702 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
704 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok);
706 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok);
709 ath_txq_schedule(sc, txq);
712 static bool ath_lookup_legacy(struct ath_buf *bf)
715 struct ieee80211_tx_info *tx_info;
716 struct ieee80211_tx_rate *rates;
720 tx_info = IEEE80211_SKB_CB(skb);
721 rates = tx_info->control.rates;
723 for (i = 0; i < 4; i++) {
724 if (!rates[i].count || rates[i].idx < 0)
727 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
734 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
735 struct ath_atx_tid *tid)
738 struct ieee80211_tx_info *tx_info;
739 struct ieee80211_tx_rate *rates;
740 u32 max_4ms_framelen, frmlen;
741 u16 aggr_limit, bt_aggr_limit, legacy = 0;
742 int q = tid->ac->txq->mac80211_qnum;
746 tx_info = IEEE80211_SKB_CB(skb);
750 * Find the lowest frame length among the rate series that will have a
751 * 4ms (or TXOP limited) transmit duration.
753 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
755 for (i = 0; i < 4; i++) {
761 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
766 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
771 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
774 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx];
775 max_4ms_framelen = min(max_4ms_framelen, frmlen);
779 * limit aggregate size by the minimum rate if rate selected is
780 * not a probe rate, if rate selected is a probe rate then
781 * avoid aggregation of this packet.
783 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
786 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX);
789 * Override the default aggregation limit for BTCOEX.
791 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen);
793 aggr_limit = bt_aggr_limit;
796 * h/w can accept aggregates up to 16 bit lengths (65535).
797 * The IE, however can hold up to 65536, which shows up here
798 * as zero. Ignore 65536 since we are constrained by hw.
800 if (tid->an->maxampdu)
801 aggr_limit = min(aggr_limit, tid->an->maxampdu);
807 * Returns the number of delimiters to be added to
808 * meet the minimum required mpdudensity.
810 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
811 struct ath_buf *bf, u16 frmlen,
814 #define FIRST_DESC_NDELIMS 60
815 u32 nsymbits, nsymbols;
818 int width, streams, half_gi, ndelim, mindelim;
819 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
821 /* Select standard number of delimiters based on frame length alone */
822 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
825 * If encryption enabled, hardware requires some more padding between
827 * TODO - this could be improved to be dependent on the rate.
828 * The hardware can keep up at lower rates, but not higher rates
830 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
831 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
832 ndelim += ATH_AGGR_ENCRYPTDELIM;
835 * Add delimiter when using RTS/CTS with aggregation
836 * and non enterprise AR9003 card
838 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
839 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
840 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
843 * Convert desired mpdu density from microeconds to bytes based
844 * on highest rate in rate series (i.e. first rate) to determine
845 * required minimum length for subframe. Take into account
846 * whether high rate is 20 or 40Mhz and half or full GI.
848 * If there is no mpdu density restriction, no further calculation
852 if (tid->an->mpdudensity == 0)
855 rix = bf->rates[0].idx;
856 flags = bf->rates[0].flags;
857 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
858 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
861 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
863 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
868 streams = HT_RC_2_STREAMS(rix);
869 nsymbits = bits_per_symbol[rix % 8][width] * streams;
870 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
872 if (frmlen < minlen) {
873 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
874 ndelim = max(mindelim, ndelim);
880 static struct ath_buf *
881 ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq,
882 struct ath_atx_tid *tid, struct sk_buff_head **q)
884 struct ieee80211_tx_info *tx_info;
885 struct ath_frame_info *fi;
892 if (skb_queue_empty(*q))
899 fi = get_frame_info(skb);
902 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
905 __skb_unlink(skb, *q);
906 ath_txq_skb_done(sc, txq, skb);
907 ieee80211_free_txskb(sc->hw, skb);
914 tx_info = IEEE80211_SKB_CB(skb);
915 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
916 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
917 bf->bf_state.bf_type = 0;
921 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
922 seqno = bf->bf_state.seqno;
924 /* do not step over block-ack window */
925 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno))
928 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
929 struct ath_tx_status ts = {};
930 struct list_head bf_head;
932 INIT_LIST_HEAD(&bf_head);
933 list_add(&bf->list, &bf_head);
934 __skb_unlink(skb, *q);
935 ath_tx_update_baw(sc, tid, seqno);
936 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
947 ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq,
948 struct ath_atx_tid *tid, struct list_head *bf_q,
949 struct ath_buf *bf_first, struct sk_buff_head *tid_q,
952 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
953 struct ath_buf *bf = bf_first, *bf_prev = NULL;
954 int nframes = 0, ndelim;
955 u16 aggr_limit = 0, al = 0, bpad = 0,
956 al_delta, h_baw = tid->baw_size / 2;
957 struct ieee80211_tx_info *tx_info;
958 struct ath_frame_info *fi;
963 aggr_limit = ath_lookup_rate(sc, bf, tid);
967 fi = get_frame_info(skb);
969 /* do not exceed aggregation limit */
970 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
972 if (aggr_limit < al + bpad + al_delta ||
973 ath_lookup_legacy(bf) || nframes >= h_baw)
976 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
977 if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
978 !(tx_info->flags & IEEE80211_TX_CTL_AMPDU))
982 /* add padding for previous frame to aggregation length */
983 al += bpad + al_delta;
986 * Get the delimiters needed to meet the MPDU
987 * density for this node.
989 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
991 bpad = PADBYTES(al_delta) + (ndelim << 2);
996 /* link buffers of this frame to the aggregate */
997 if (!fi->baw_tracked)
998 ath_tx_addto_baw(sc, tid, bf);
999 bf->bf_state.ndelim = ndelim;
1001 __skb_unlink(skb, tid_q);
1002 list_add_tail(&bf->list, bf_q);
1004 bf_prev->bf_next = bf;
1008 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1013 } while (ath_tid_has_buffered(tid));
1016 bf->bf_lastbf = bf_prev;
1018 if (bf == bf_prev) {
1019 al = get_frame_info(bf->bf_mpdu)->framelen;
1020 bf->bf_state.bf_type = BUF_AMPDU;
1022 TX_STAT_INC(txq->axq_qnum, a_aggr);
1033 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1034 * width - 0 for 20 MHz, 1 for 40 MHz
1035 * half_gi - to use 4us v/s 3.6 us for symbol time
1037 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1038 int width, int half_gi, bool shortPreamble)
1040 u32 nbits, nsymbits, duration, nsymbols;
1043 /* find number of symbols: PLCP + data */
1044 streams = HT_RC_2_STREAMS(rix);
1045 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1046 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1047 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1050 duration = SYMBOL_TIME(nsymbols);
1052 duration = SYMBOL_TIME_HALFGI(nsymbols);
1054 /* addup duration for legacy/ht training and signal fields */
1055 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1060 static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi)
1062 int streams = HT_RC_2_STREAMS(mcs);
1066 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec);
1067 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams;
1068 bits -= OFDM_PLCP_BITS;
1070 bytes -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1077 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop)
1079 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi;
1082 /* 4ms is the default (and maximum) duration */
1083 if (!txop || txop > 4096)
1086 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20];
1087 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI];
1088 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40];
1089 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI];
1090 for (mcs = 0; mcs < 32; mcs++) {
1091 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false);
1092 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true);
1093 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false);
1094 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true);
1098 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
1099 struct ath_tx_info *info, int len, bool rts)
1101 struct ath_hw *ah = sc->sc_ah;
1102 struct sk_buff *skb;
1103 struct ieee80211_tx_info *tx_info;
1104 struct ieee80211_tx_rate *rates;
1105 const struct ieee80211_rate *rate;
1106 struct ieee80211_hdr *hdr;
1107 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1108 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1113 tx_info = IEEE80211_SKB_CB(skb);
1115 hdr = (struct ieee80211_hdr *)skb->data;
1117 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1118 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
1119 info->rtscts_rate = fi->rtscts_rate;
1121 for (i = 0; i < ARRAY_SIZE(bf->rates); i++) {
1122 bool is_40, is_sgi, is_sp;
1125 if (!rates[i].count || (rates[i].idx < 0))
1129 info->rates[i].Tries = rates[i].count;
1132 * Handle RTS threshold for unaggregated HT frames.
1134 if (bf_isampdu(bf) && !bf_isaggr(bf) &&
1135 (rates[i].flags & IEEE80211_TX_RC_MCS) &&
1136 unlikely(rts_thresh != (u32) -1)) {
1137 if (!rts_thresh || (len > rts_thresh))
1141 if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1142 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1143 info->flags |= ATH9K_TXDESC_RTSENA;
1144 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1145 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1146 info->flags |= ATH9K_TXDESC_CTSENA;
1149 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1150 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
1151 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1152 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1154 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1155 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1156 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1158 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1160 info->rates[i].Rate = rix | 0x80;
1161 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1162 ah->txchainmask, info->rates[i].Rate);
1163 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
1164 is_40, is_sgi, is_sp);
1165 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1166 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
1171 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
1172 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1173 !(rate->flags & IEEE80211_RATE_ERP_G))
1174 phy = WLAN_RC_PHY_CCK;
1176 phy = WLAN_RC_PHY_OFDM;
1178 info->rates[i].Rate = rate->hw_value;
1179 if (rate->hw_value_short) {
1180 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1181 info->rates[i].Rate |= rate->hw_value_short;
1186 if (bf->bf_state.bfs_paprd)
1187 info->rates[i].ChSel = ah->txchainmask;
1189 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1190 ah->txchainmask, info->rates[i].Rate);
1192 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1193 phy, rate->bitrate * 100, len, rix, is_sp);
1196 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1197 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1198 info->flags &= ~ATH9K_TXDESC_RTSENA;
1200 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1201 if (info->flags & ATH9K_TXDESC_RTSENA)
1202 info->flags &= ~ATH9K_TXDESC_CTSENA;
1205 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1207 struct ieee80211_hdr *hdr;
1208 enum ath9k_pkt_type htype;
1211 hdr = (struct ieee80211_hdr *)skb->data;
1212 fc = hdr->frame_control;
1214 if (ieee80211_is_beacon(fc))
1215 htype = ATH9K_PKT_TYPE_BEACON;
1216 else if (ieee80211_is_probe_resp(fc))
1217 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1218 else if (ieee80211_is_atim(fc))
1219 htype = ATH9K_PKT_TYPE_ATIM;
1220 else if (ieee80211_is_pspoll(fc))
1221 htype = ATH9K_PKT_TYPE_PSPOLL;
1223 htype = ATH9K_PKT_TYPE_NORMAL;
1228 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1229 struct ath_txq *txq, int len)
1231 struct ath_hw *ah = sc->sc_ah;
1232 struct ath_buf *bf_first = NULL;
1233 struct ath_tx_info info;
1234 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1237 memset(&info, 0, sizeof(info));
1238 info.is_first = true;
1239 info.is_last = true;
1240 info.txpower = MAX_RATE_POWER;
1241 info.qcu = txq->axq_qnum;
1244 struct sk_buff *skb = bf->bf_mpdu;
1245 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1246 struct ath_frame_info *fi = get_frame_info(skb);
1247 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1249 info.type = get_hw_packet_type(skb);
1251 info.link = bf->bf_next->bf_daddr;
1258 info.flags = ATH9K_TXDESC_INTREQ;
1259 if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) ||
1260 txq == sc->tx.uapsdq)
1261 info.flags |= ATH9K_TXDESC_CLRDMASK;
1263 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1264 info.flags |= ATH9K_TXDESC_NOACK;
1265 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1266 info.flags |= ATH9K_TXDESC_LDPC;
1268 if (bf->bf_state.bfs_paprd)
1269 info.flags |= (u32) bf->bf_state.bfs_paprd <<
1270 ATH9K_TXDESC_PAPRD_S;
1273 * mac80211 doesn't handle RTS threshold for HT because
1274 * the decision has to be taken based on AMPDU length
1275 * and aggregation is done entirely inside ath9k.
1276 * Set the RTS/CTS flag for the first subframe based
1279 if (aggr && (bf == bf_first) &&
1280 unlikely(rts_thresh != (u32) -1)) {
1282 * "len" is the size of the entire AMPDU.
1284 if (!rts_thresh || (len > rts_thresh))
1287 ath_buf_set_rate(sc, bf, &info, len, rts);
1290 info.buf_addr[0] = bf->bf_buf_addr;
1291 info.buf_len[0] = skb->len;
1292 info.pkt_len = fi->framelen;
1293 info.keyix = fi->keyix;
1294 info.keytype = fi->keytype;
1298 info.aggr = AGGR_BUF_FIRST;
1299 else if (bf == bf_first->bf_lastbf)
1300 info.aggr = AGGR_BUF_LAST;
1302 info.aggr = AGGR_BUF_MIDDLE;
1304 info.ndelim = bf->bf_state.ndelim;
1305 info.aggr_len = len;
1308 if (bf == bf_first->bf_lastbf)
1311 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1317 ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq,
1318 struct ath_atx_tid *tid, struct list_head *bf_q,
1319 struct ath_buf *bf_first, struct sk_buff_head *tid_q)
1321 struct ath_buf *bf = bf_first, *bf_prev = NULL;
1322 struct sk_buff *skb;
1326 struct ieee80211_tx_info *tx_info;
1330 __skb_unlink(skb, tid_q);
1331 list_add_tail(&bf->list, bf_q);
1333 bf_prev->bf_next = bf;
1339 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1343 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1344 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1347 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1351 static bool ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1352 struct ath_atx_tid *tid, bool *stop)
1355 struct ieee80211_tx_info *tx_info;
1356 struct sk_buff_head *tid_q;
1357 struct list_head bf_q;
1359 bool aggr, last = true;
1361 if (!ath_tid_has_buffered(tid))
1364 INIT_LIST_HEAD(&bf_q);
1366 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1370 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1371 aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU);
1372 if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) ||
1373 (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH)) {
1378 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1380 last = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf,
1383 ath_tx_form_burst(sc, txq, tid, &bf_q, bf, tid_q);
1385 if (list_empty(&bf_q))
1388 if (tid->ac->clear_ps_filter || tid->an->no_ps_filter) {
1389 tid->ac->clear_ps_filter = false;
1390 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1393 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1394 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1398 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1401 struct ath_atx_tid *txtid;
1402 struct ath_node *an;
1405 an = (struct ath_node *)sta->drv_priv;
1406 txtid = ATH_AN_2_TID(an, tid);
1408 /* update ampdu factor/density, they may have changed. This may happen
1409 * in HT IBSS when a beacon with HT-info is received after the station
1410 * has already been added.
1412 if (sta->ht_cap.ht_supported) {
1413 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
1414 sta->ht_cap.ampdu_factor);
1415 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
1416 an->mpdudensity = density;
1419 /* force sequence number allocation for pending frames */
1420 ath_tx_tid_change_state(sc, txtid);
1422 txtid->active = true;
1423 txtid->paused = true;
1424 *ssn = txtid->seq_start = txtid->seq_next;
1425 txtid->bar_index = -1;
1427 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1428 txtid->baw_head = txtid->baw_tail = 0;
1433 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1435 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1436 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1437 struct ath_txq *txq = txtid->ac->txq;
1439 ath_txq_lock(sc, txq);
1440 txtid->active = false;
1441 txtid->paused = false;
1442 ath_tx_flush_tid(sc, txtid);
1443 ath_tx_tid_change_state(sc, txtid);
1444 ath_txq_unlock_complete(sc, txq);
1447 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1448 struct ath_node *an)
1450 struct ath_atx_tid *tid;
1451 struct ath_atx_ac *ac;
1452 struct ath_txq *txq;
1456 for (tidno = 0, tid = &an->tid[tidno];
1457 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1465 ath_txq_lock(sc, txq);
1467 buffered = ath_tid_has_buffered(tid);
1470 list_del(&tid->list);
1474 list_del(&ac->list);
1477 ath_txq_unlock(sc, txq);
1479 ieee80211_sta_set_buffered(sta, tidno, buffered);
1483 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1485 struct ath_atx_tid *tid;
1486 struct ath_atx_ac *ac;
1487 struct ath_txq *txq;
1490 for (tidno = 0, tid = &an->tid[tidno];
1491 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1496 ath_txq_lock(sc, txq);
1497 ac->clear_ps_filter = true;
1499 if (!tid->paused && ath_tid_has_buffered(tid)) {
1500 ath_tx_queue_tid(txq, tid);
1501 ath_txq_schedule(sc, txq);
1504 ath_txq_unlock_complete(sc, txq);
1508 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta,
1511 struct ath_atx_tid *tid;
1512 struct ath_node *an;
1513 struct ath_txq *txq;
1515 an = (struct ath_node *)sta->drv_priv;
1516 tid = ATH_AN_2_TID(an, tidno);
1519 ath_txq_lock(sc, txq);
1521 tid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
1522 tid->paused = false;
1524 if (ath_tid_has_buffered(tid)) {
1525 ath_tx_queue_tid(txq, tid);
1526 ath_txq_schedule(sc, txq);
1529 ath_txq_unlock_complete(sc, txq);
1532 void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
1533 struct ieee80211_sta *sta,
1534 u16 tids, int nframes,
1535 enum ieee80211_frame_release_type reason,
1538 struct ath_softc *sc = hw->priv;
1539 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1540 struct ath_txq *txq = sc->tx.uapsdq;
1541 struct ieee80211_tx_info *info;
1542 struct list_head bf_q;
1543 struct ath_buf *bf_tail = NULL, *bf;
1544 struct sk_buff_head *tid_q;
1548 INIT_LIST_HEAD(&bf_q);
1549 for (i = 0; tids && nframes; i++, tids >>= 1) {
1550 struct ath_atx_tid *tid;
1555 tid = ATH_AN_2_TID(an, i);
1559 ath_txq_lock(sc, tid->ac->txq);
1560 while (nframes > 0) {
1561 bf = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq, tid, &tid_q);
1565 __skb_unlink(bf->bf_mpdu, tid_q);
1566 list_add_tail(&bf->list, &bf_q);
1567 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1568 ath_tx_addto_baw(sc, tid, bf);
1569 bf->bf_state.bf_type &= ~BUF_AGGR;
1571 bf_tail->bf_next = bf;
1576 TX_STAT_INC(txq->axq_qnum, a_queued_hw);
1578 if (an->sta && !ath_tid_has_buffered(tid))
1579 ieee80211_sta_set_buffered(an->sta, i, false);
1581 ath_txq_unlock_complete(sc, tid->ac->txq);
1584 if (list_empty(&bf_q))
1587 info = IEEE80211_SKB_CB(bf_tail->bf_mpdu);
1588 info->flags |= IEEE80211_TX_STATUS_EOSP;
1590 bf = list_first_entry(&bf_q, struct ath_buf, list);
1591 ath_txq_lock(sc, txq);
1592 ath_tx_fill_desc(sc, bf, txq, 0);
1593 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1594 ath_txq_unlock(sc, txq);
1597 /********************/
1598 /* Queue Management */
1599 /********************/
1601 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1603 struct ath_hw *ah = sc->sc_ah;
1604 struct ath9k_tx_queue_info qi;
1605 static const int subtype_txq_to_hwq[] = {
1606 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE,
1607 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK,
1608 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI,
1609 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO,
1613 memset(&qi, 0, sizeof(qi));
1614 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1615 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1616 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1617 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1618 qi.tqi_physCompBuf = 0;
1621 * Enable interrupts only for EOL and DESC conditions.
1622 * We mark tx descriptors to receive a DESC interrupt
1623 * when a tx queue gets deep; otherwise waiting for the
1624 * EOL to reap descriptors. Note that this is done to
1625 * reduce interrupt load and this only defers reaping
1626 * descriptors, never transmitting frames. Aside from
1627 * reducing interrupts this also permits more concurrency.
1628 * The only potential downside is if the tx queue backs
1629 * up in which case the top half of the kernel may backup
1630 * due to a lack of tx descriptors.
1632 * The UAPSD queue is an exception, since we take a desc-
1633 * based intr on the EOSP frames.
1635 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1636 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
1638 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1639 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1641 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1642 TXQ_FLAG_TXDESCINT_ENABLE;
1644 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1645 if (axq_qnum == -1) {
1647 * NB: don't print a message, this happens
1648 * normally on parts with too few tx queues
1652 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1653 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1655 txq->axq_qnum = axq_qnum;
1656 txq->mac80211_qnum = -1;
1657 txq->axq_link = NULL;
1658 __skb_queue_head_init(&txq->complete_q);
1659 INIT_LIST_HEAD(&txq->axq_q);
1660 INIT_LIST_HEAD(&txq->axq_acq);
1661 spin_lock_init(&txq->axq_lock);
1663 txq->axq_ampdu_depth = 0;
1664 txq->axq_tx_inprogress = false;
1665 sc->tx.txqsetup |= 1<<axq_qnum;
1667 txq->txq_headidx = txq->txq_tailidx = 0;
1668 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1669 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1671 return &sc->tx.txq[axq_qnum];
1674 int ath_txq_update(struct ath_softc *sc, int qnum,
1675 struct ath9k_tx_queue_info *qinfo)
1677 struct ath_hw *ah = sc->sc_ah;
1679 struct ath9k_tx_queue_info qi;
1681 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1683 ath9k_hw_get_txq_props(ah, qnum, &qi);
1684 qi.tqi_aifs = qinfo->tqi_aifs;
1685 qi.tqi_cwmin = qinfo->tqi_cwmin;
1686 qi.tqi_cwmax = qinfo->tqi_cwmax;
1687 qi.tqi_burstTime = qinfo->tqi_burstTime;
1688 qi.tqi_readyTime = qinfo->tqi_readyTime;
1690 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1691 ath_err(ath9k_hw_common(sc->sc_ah),
1692 "Unable to update hardware queue %u!\n", qnum);
1695 ath9k_hw_resettxqueue(ah, qnum);
1701 int ath_cabq_update(struct ath_softc *sc)
1703 struct ath9k_tx_queue_info qi;
1704 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
1705 int qnum = sc->beacon.cabq->axq_qnum;
1707 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1709 * Ensure the readytime % is within the bounds.
1711 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1712 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1713 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1714 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1716 qi.tqi_readyTime = (cur_conf->beacon_interval *
1717 sc->config.cabqReadytime) / 100;
1718 ath_txq_update(sc, qnum, &qi);
1723 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1724 struct list_head *list)
1726 struct ath_buf *bf, *lastbf;
1727 struct list_head bf_head;
1728 struct ath_tx_status ts;
1730 memset(&ts, 0, sizeof(ts));
1731 ts.ts_status = ATH9K_TX_FLUSH;
1732 INIT_LIST_HEAD(&bf_head);
1734 while (!list_empty(list)) {
1735 bf = list_first_entry(list, struct ath_buf, list);
1738 list_del(&bf->list);
1740 ath_tx_return_buffer(sc, bf);
1744 lastbf = bf->bf_lastbf;
1745 list_cut_position(&bf_head, list, &lastbf->list);
1746 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
1751 * Drain a given TX queue (could be Beacon or Data)
1753 * This assumes output has been stopped and
1754 * we do not need to block ath_tx_tasklet.
1756 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq)
1758 ath_txq_lock(sc, txq);
1760 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1761 int idx = txq->txq_tailidx;
1763 while (!list_empty(&txq->txq_fifo[idx])) {
1764 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]);
1766 INCR(idx, ATH_TXFIFO_DEPTH);
1768 txq->txq_tailidx = idx;
1771 txq->axq_link = NULL;
1772 txq->axq_tx_inprogress = false;
1773 ath_drain_txq_list(sc, txq, &txq->axq_q);
1775 ath_txq_unlock_complete(sc, txq);
1778 bool ath_drain_all_txq(struct ath_softc *sc)
1780 struct ath_hw *ah = sc->sc_ah;
1781 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1782 struct ath_txq *txq;
1786 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
1789 ath9k_hw_abort_tx_dma(ah);
1791 /* Check if any queue remains active */
1792 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1793 if (!ATH_TXQ_SETUP(sc, i))
1796 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1801 ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1803 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1804 if (!ATH_TXQ_SETUP(sc, i))
1808 * The caller will resume queues with ieee80211_wake_queues.
1809 * Mark the queue as not stopped to prevent ath_tx_complete
1810 * from waking the queue too early.
1812 txq = &sc->tx.txq[i];
1813 txq->stopped = false;
1814 ath_draintxq(sc, txq);
1820 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1822 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1823 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1826 /* For each axq_acq entry, for each tid, try to schedule packets
1827 * for transmit until ampdu_depth has reached min Q depth.
1829 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1831 struct ath_atx_ac *ac, *last_ac;
1832 struct ath_atx_tid *tid, *last_tid;
1835 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags) ||
1836 list_empty(&txq->axq_acq))
1841 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
1842 while (!list_empty(&txq->axq_acq)) {
1845 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1846 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1847 list_del(&ac->list);
1850 while (!list_empty(&ac->tid_q)) {
1852 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1854 list_del(&tid->list);
1860 if (ath_tx_sched_aggr(sc, txq, tid, &stop))
1864 * add tid to round-robin queue if more frames
1865 * are pending for the tid
1867 if (ath_tid_has_buffered(tid))
1868 ath_tx_queue_tid(txq, tid);
1870 if (stop || tid == last_tid)
1874 if (!list_empty(&ac->tid_q) && !ac->sched) {
1876 list_add_tail(&ac->list, &txq->axq_acq);
1882 if (ac == last_ac) {
1887 last_ac = list_entry(txq->axq_acq.prev,
1888 struct ath_atx_ac, list);
1900 * Insert a chain of ath_buf (descriptors) on a txq and
1901 * assume the descriptors are already chained together by caller.
1903 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1904 struct list_head *head, bool internal)
1906 struct ath_hw *ah = sc->sc_ah;
1907 struct ath_common *common = ath9k_hw_common(ah);
1908 struct ath_buf *bf, *bf_last;
1909 bool puttxbuf = false;
1913 * Insert the frame on the outbound list and
1914 * pass it on to the hardware.
1917 if (list_empty(head))
1920 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1921 bf = list_first_entry(head, struct ath_buf, list);
1922 bf_last = list_entry(head->prev, struct ath_buf, list);
1924 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n",
1925 txq->axq_qnum, txq->axq_depth);
1927 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1928 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
1929 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1932 list_splice_tail_init(head, &txq->axq_q);
1934 if (txq->axq_link) {
1935 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
1936 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n",
1937 txq->axq_qnum, txq->axq_link,
1938 ito64(bf->bf_daddr), bf->bf_desc);
1942 txq->axq_link = bf_last->bf_desc;
1946 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1947 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1948 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n",
1949 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1953 TX_STAT_INC(txq->axq_qnum, txstart);
1954 ath9k_hw_txstart(ah, txq->axq_qnum);
1960 if (bf_is_ampdu_not_probing(bf))
1961 txq->axq_ampdu_depth++;
1963 bf = bf->bf_lastbf->bf_next;
1968 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1969 struct ath_atx_tid *tid, struct sk_buff *skb)
1971 struct ath_frame_info *fi = get_frame_info(skb);
1972 struct list_head bf_head;
1977 INIT_LIST_HEAD(&bf_head);
1978 list_add_tail(&bf->list, &bf_head);
1979 bf->bf_state.bf_type = 0;
1983 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
1984 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
1985 TX_STAT_INC(txq->axq_qnum, queued);
1988 static void setup_frame_info(struct ieee80211_hw *hw,
1989 struct ieee80211_sta *sta,
1990 struct sk_buff *skb,
1993 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1994 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1995 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1996 const struct ieee80211_rate *rate;
1997 struct ath_frame_info *fi = get_frame_info(skb);
1998 struct ath_node *an = NULL;
1999 enum ath9k_key_type keytype;
2000 bool short_preamble = false;
2003 * We check if Short Preamble is needed for the CTS rate by
2004 * checking the BSS's global flag.
2005 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
2007 if (tx_info->control.vif &&
2008 tx_info->control.vif->bss_conf.use_short_preamble)
2009 short_preamble = true;
2011 rate = ieee80211_get_rts_cts_rate(hw, tx_info);
2012 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
2015 an = (struct ath_node *) sta->drv_priv;
2017 memset(fi, 0, sizeof(*fi));
2019 fi->keyix = hw_key->hw_key_idx;
2020 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
2021 fi->keyix = an->ps_key;
2023 fi->keyix = ATH9K_TXKEYIX_INVALID;
2024 fi->keytype = keytype;
2025 fi->framelen = framelen;
2026 fi->rtscts_rate = rate->hw_value;
2028 fi->rtscts_rate |= rate->hw_value_short;
2031 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
2033 struct ath_hw *ah = sc->sc_ah;
2034 struct ath9k_channel *curchan = ah->curchan;
2036 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) &&
2037 (curchan->channelFlags & CHANNEL_5GHZ) &&
2038 (chainmask == 0x7) && (rate < 0x90))
2040 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
2048 * Assign a descriptor (and sequence number if necessary,
2049 * and map buffer for DMA. Frees skb on error
2051 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
2052 struct ath_txq *txq,
2053 struct ath_atx_tid *tid,
2054 struct sk_buff *skb)
2056 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2057 struct ath_frame_info *fi = get_frame_info(skb);
2058 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2063 bf = ath_tx_get_buffer(sc);
2065 ath_dbg(common, XMIT, "TX buffers are full\n");
2069 ATH_TXBUF_RESET(bf);
2072 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
2073 seqno = tid->seq_next;
2074 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
2077 hdr->seq_ctrl |= cpu_to_le16(fragno);
2079 if (!ieee80211_has_morefrags(hdr->frame_control))
2080 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
2082 bf->bf_state.seqno = seqno;
2087 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
2088 skb->len, DMA_TO_DEVICE);
2089 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
2091 bf->bf_buf_addr = 0;
2092 ath_err(ath9k_hw_common(sc->sc_ah),
2093 "dma_mapping_error() on TX\n");
2094 ath_tx_return_buffer(sc, bf);
2103 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
2104 struct ath_tx_control *txctl)
2106 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2107 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2108 struct ieee80211_sta *sta = txctl->sta;
2109 struct ieee80211_vif *vif = info->control.vif;
2110 struct ath_vif *avp;
2111 struct ath_softc *sc = hw->priv;
2112 int frmlen = skb->len + FCS_LEN;
2113 int padpos, padsize;
2115 /* NOTE: sta can be NULL according to net/mac80211.h */
2117 txctl->an = (struct ath_node *)sta->drv_priv;
2118 else if (vif && ieee80211_is_data(hdr->frame_control)) {
2119 avp = (void *)vif->drv_priv;
2120 txctl->an = &avp->mcast_node;
2123 if (info->control.hw_key)
2124 frmlen += info->control.hw_key->icv_len;
2127 * As a temporary workaround, assign seq# here; this will likely need
2128 * to be cleaned up to work better with Beacon transmission and virtual
2131 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2132 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2133 sc->tx.seq_no += 0x10;
2134 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2135 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2138 if ((vif && vif->type != NL80211_IFTYPE_AP &&
2139 vif->type != NL80211_IFTYPE_AP_VLAN) ||
2140 !ieee80211_is_data(hdr->frame_control))
2141 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
2143 /* Add the padding after the header if this is not already done */
2144 padpos = ieee80211_hdrlen(hdr->frame_control);
2145 padsize = padpos & 3;
2146 if (padsize && skb->len > padpos) {
2147 if (skb_headroom(skb) < padsize)
2150 skb_push(skb, padsize);
2151 memmove(skb->data, skb->data + padsize, padpos);
2154 setup_frame_info(hw, sta, skb, frmlen);
2159 /* Upon failure caller should free skb */
2160 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
2161 struct ath_tx_control *txctl)
2163 struct ieee80211_hdr *hdr;
2164 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2165 struct ieee80211_sta *sta = txctl->sta;
2166 struct ieee80211_vif *vif = info->control.vif;
2167 struct ath_softc *sc = hw->priv;
2168 struct ath_txq *txq = txctl->txq;
2169 struct ath_atx_tid *tid = NULL;
2174 ret = ath_tx_prepare(hw, skb, txctl);
2178 hdr = (struct ieee80211_hdr *) skb->data;
2180 * At this point, the vif, hw_key and sta pointers in the tx control
2181 * info are no longer valid (overwritten by the ath_frame_info data.
2184 q = skb_get_queue_mapping(skb);
2186 ath_txq_lock(sc, txq);
2187 if (txq == sc->tx.txq_map[q] &&
2188 ++txq->pending_frames > sc->tx.txq_max_pending[q] &&
2190 ieee80211_stop_queue(sc->hw, q);
2191 txq->stopped = true;
2194 if (info->flags & IEEE80211_TX_CTL_PS_RESPONSE) {
2195 ath_txq_unlock(sc, txq);
2196 txq = sc->tx.uapsdq;
2197 ath_txq_lock(sc, txq);
2198 } else if (txctl->an &&
2199 ieee80211_is_data_present(hdr->frame_control)) {
2200 tid = ath_get_skb_tid(sc, txctl->an, skb);
2202 WARN_ON(tid->ac->txq != txctl->txq);
2204 if (info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
2205 tid->ac->clear_ps_filter = true;
2208 * Add this frame to software queue for scheduling later
2211 TX_STAT_INC(txq->axq_qnum, a_queued_sw);
2212 __skb_queue_tail(&tid->buf_q, skb);
2213 if (!txctl->an->sleeping)
2214 ath_tx_queue_tid(txq, tid);
2216 ath_txq_schedule(sc, txq);
2220 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
2222 ath_txq_skb_done(sc, txq, skb);
2224 dev_kfree_skb_any(skb);
2226 ieee80211_free_txskb(sc->hw, skb);
2230 bf->bf_state.bfs_paprd = txctl->paprd;
2233 bf->bf_state.bfs_paprd_timestamp = jiffies;
2235 ath_set_rates(vif, sta, bf);
2236 ath_tx_send_normal(sc, txq, tid, skb);
2239 ath_txq_unlock(sc, txq);
2244 void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2245 struct sk_buff *skb)
2247 struct ath_softc *sc = hw->priv;
2248 struct ath_tx_control txctl = {
2249 .txq = sc->beacon.cabq
2251 struct ath_tx_info info = {};
2252 struct ieee80211_hdr *hdr;
2253 struct ath_buf *bf_tail = NULL;
2260 sc->cur_beacon_conf.beacon_interval * 1000 *
2261 sc->cur_beacon_conf.dtim_period / ATH_BCBUF;
2264 struct ath_frame_info *fi = get_frame_info(skb);
2266 if (ath_tx_prepare(hw, skb, &txctl))
2269 bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb);
2274 ath_set_rates(vif, NULL, bf);
2275 ath_buf_set_rate(sc, bf, &info, fi->framelen, false);
2276 duration += info.rates[0].PktDuration;
2278 bf_tail->bf_next = bf;
2280 list_add_tail(&bf->list, &bf_q);
2284 if (duration > max_duration)
2287 skb = ieee80211_get_buffered_bc(hw, vif);
2291 ieee80211_free_txskb(hw, skb);
2293 if (list_empty(&bf_q))
2296 bf = list_first_entry(&bf_q, struct ath_buf, list);
2297 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
2299 if (hdr->frame_control & IEEE80211_FCTL_MOREDATA) {
2300 hdr->frame_control &= ~IEEE80211_FCTL_MOREDATA;
2301 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
2302 sizeof(*hdr), DMA_TO_DEVICE);
2305 ath_txq_lock(sc, txctl.txq);
2306 ath_tx_fill_desc(sc, bf, txctl.txq, 0);
2307 ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false);
2308 TX_STAT_INC(txctl.txq->axq_qnum, queued);
2309 ath_txq_unlock(sc, txctl.txq);
2316 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
2317 int tx_flags, struct ath_txq *txq)
2319 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2320 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2321 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
2322 int padpos, padsize;
2323 unsigned long flags;
2325 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
2327 if (sc->sc_ah->caldata)
2328 sc->sc_ah->caldata->paprd_packet_sent = true;
2330 if (!(tx_flags & ATH_TX_ERROR))
2331 /* Frame was ACKed */
2332 tx_info->flags |= IEEE80211_TX_STAT_ACK;
2334 padpos = ieee80211_hdrlen(hdr->frame_control);
2335 padsize = padpos & 3;
2336 if (padsize && skb->len>padpos+padsize) {
2338 * Remove MAC header padding before giving the frame back to
2341 memmove(skb->data + padsize, skb->data, padpos);
2342 skb_pull(skb, padsize);
2345 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2346 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
2347 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
2349 "Going back to sleep after having received TX status (0x%lx)\n",
2350 sc->ps_flags & (PS_WAIT_FOR_BEACON |
2352 PS_WAIT_FOR_PSPOLL_DATA |
2353 PS_WAIT_FOR_TX_ACK));
2355 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2357 __skb_queue_tail(&txq->complete_q, skb);
2358 ath_txq_skb_done(sc, txq, skb);
2361 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
2362 struct ath_txq *txq, struct list_head *bf_q,
2363 struct ath_tx_status *ts, int txok)
2365 struct sk_buff *skb = bf->bf_mpdu;
2366 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2367 unsigned long flags;
2371 tx_flags |= ATH_TX_ERROR;
2373 if (ts->ts_status & ATH9K_TXERR_FILT)
2374 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2376 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2377 bf->bf_buf_addr = 0;
2379 if (bf->bf_state.bfs_paprd) {
2380 if (time_after(jiffies,
2381 bf->bf_state.bfs_paprd_timestamp +
2382 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2383 dev_kfree_skb_any(skb);
2385 complete(&sc->paprd_complete);
2387 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2388 ath_tx_complete(sc, skb, tx_flags, txq);
2390 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2391 * accidentally reference it later.
2396 * Return the list of ath_buf of this mpdu to free queue
2398 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2399 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2400 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2403 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2404 struct ath_tx_status *ts, int nframes, int nbad,
2407 struct sk_buff *skb = bf->bf_mpdu;
2408 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2409 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2410 struct ieee80211_hw *hw = sc->hw;
2411 struct ath_hw *ah = sc->sc_ah;
2415 tx_info->status.ack_signal = ts->ts_rssi;
2417 tx_rateindex = ts->ts_rateindex;
2418 WARN_ON(tx_rateindex >= hw->max_rates);
2420 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2421 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2423 BUG_ON(nbad > nframes);
2425 tx_info->status.ampdu_len = nframes;
2426 tx_info->status.ampdu_ack_len = nframes - nbad;
2428 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2429 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2431 * If an underrun error is seen assume it as an excessive
2432 * retry only if max frame trigger level has been reached
2433 * (2 KB for single stream, and 4 KB for dual stream).
2434 * Adjust the long retry as if the frame was tried
2435 * hw->max_rate_tries times to affect how rate control updates
2436 * PER for the failed rate.
2437 * In case of congestion on the bus penalizing this type of
2438 * underruns should help hardware actually transmit new frames
2439 * successfully by eventually preferring slower rates.
2440 * This itself should also alleviate congestion on the bus.
2442 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2443 ATH9K_TX_DELIM_UNDERRUN)) &&
2444 ieee80211_is_data(hdr->frame_control) &&
2445 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2446 tx_info->status.rates[tx_rateindex].count =
2450 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2451 tx_info->status.rates[i].count = 0;
2452 tx_info->status.rates[i].idx = -1;
2455 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2458 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2460 struct ath_hw *ah = sc->sc_ah;
2461 struct ath_common *common = ath9k_hw_common(ah);
2462 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2463 struct list_head bf_head;
2464 struct ath_desc *ds;
2465 struct ath_tx_status ts;
2468 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n",
2469 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2472 ath_txq_lock(sc, txq);
2474 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
2477 if (list_empty(&txq->axq_q)) {
2478 txq->axq_link = NULL;
2479 ath_txq_schedule(sc, txq);
2482 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2485 * There is a race condition that a BH gets scheduled
2486 * after sw writes TxE and before hw re-load the last
2487 * descriptor to get the newly chained one.
2488 * Software must keep the last DONE descriptor as a
2489 * holding descriptor - software does so by marking
2490 * it with the STALE flag.
2495 if (list_is_last(&bf_held->list, &txq->axq_q))
2498 bf = list_entry(bf_held->list.next, struct ath_buf,
2502 lastbf = bf->bf_lastbf;
2503 ds = lastbf->bf_desc;
2505 memset(&ts, 0, sizeof(ts));
2506 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2507 if (status == -EINPROGRESS)
2510 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2513 * Remove ath_buf's of the same transmit unit from txq,
2514 * however leave the last descriptor back as the holding
2515 * descriptor for hw.
2517 lastbf->bf_stale = true;
2518 INIT_LIST_HEAD(&bf_head);
2519 if (!list_is_singular(&lastbf->list))
2520 list_cut_position(&bf_head,
2521 &txq->axq_q, lastbf->list.prev);
2524 list_del(&bf_held->list);
2525 ath_tx_return_buffer(sc, bf_held);
2528 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2530 ath_txq_unlock_complete(sc, txq);
2533 void ath_tx_tasklet(struct ath_softc *sc)
2535 struct ath_hw *ah = sc->sc_ah;
2536 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;
2539 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2540 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2541 ath_tx_processq(sc, &sc->tx.txq[i]);
2545 void ath_tx_edma_tasklet(struct ath_softc *sc)
2547 struct ath_tx_status ts;
2548 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2549 struct ath_hw *ah = sc->sc_ah;
2550 struct ath_txq *txq;
2551 struct ath_buf *bf, *lastbf;
2552 struct list_head bf_head;
2553 struct list_head *fifo_list;
2557 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
2560 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2561 if (status == -EINPROGRESS)
2563 if (status == -EIO) {
2564 ath_dbg(common, XMIT, "Error processing tx status\n");
2568 /* Process beacon completions separately */
2569 if (ts.qid == sc->beacon.beaconq) {
2570 sc->beacon.tx_processed = true;
2571 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2575 txq = &sc->tx.txq[ts.qid];
2577 ath_txq_lock(sc, txq);
2579 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2581 fifo_list = &txq->txq_fifo[txq->txq_tailidx];
2582 if (list_empty(fifo_list)) {
2583 ath_txq_unlock(sc, txq);
2587 bf = list_first_entry(fifo_list, struct ath_buf, list);
2589 list_del(&bf->list);
2590 ath_tx_return_buffer(sc, bf);
2591 bf = list_first_entry(fifo_list, struct ath_buf, list);
2594 lastbf = bf->bf_lastbf;
2596 INIT_LIST_HEAD(&bf_head);
2597 if (list_is_last(&lastbf->list, fifo_list)) {
2598 list_splice_tail_init(fifo_list, &bf_head);
2599 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2601 if (!list_empty(&txq->axq_q)) {
2602 struct list_head bf_q;
2604 INIT_LIST_HEAD(&bf_q);
2605 txq->axq_link = NULL;
2606 list_splice_tail_init(&txq->axq_q, &bf_q);
2607 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2610 lastbf->bf_stale = true;
2612 list_cut_position(&bf_head, fifo_list,
2616 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2617 ath_txq_unlock_complete(sc, txq);
2625 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2627 struct ath_descdma *dd = &sc->txsdma;
2628 u8 txs_len = sc->sc_ah->caps.txs_len;
2630 dd->dd_desc_len = size * txs_len;
2631 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
2632 &dd->dd_desc_paddr, GFP_KERNEL);
2639 static int ath_tx_edma_init(struct ath_softc *sc)
2643 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2645 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2646 sc->txsdma.dd_desc_paddr,
2647 ATH_TXSTATUS_RING_SIZE);
2652 int ath_tx_init(struct ath_softc *sc, int nbufs)
2654 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2657 spin_lock_init(&sc->tx.txbuflock);
2659 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2663 "Failed to allocate tx descriptors: %d\n", error);
2667 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2668 "beacon", ATH_BCBUF, 1, 1);
2671 "Failed to allocate beacon descriptors: %d\n", error);
2675 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2677 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2678 error = ath_tx_edma_init(sc);
2683 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2685 struct ath_atx_tid *tid;
2686 struct ath_atx_ac *ac;
2689 for (tidno = 0, tid = &an->tid[tidno];
2690 tidno < IEEE80211_NUM_TIDS;
2694 tid->seq_start = tid->seq_next = 0;
2695 tid->baw_size = WME_MAX_BA;
2696 tid->baw_head = tid->baw_tail = 0;
2698 tid->paused = false;
2699 tid->active = false;
2700 __skb_queue_head_init(&tid->buf_q);
2701 __skb_queue_head_init(&tid->retry_q);
2702 acno = TID_TO_WME_AC(tidno);
2703 tid->ac = &an->ac[acno];
2706 for (acno = 0, ac = &an->ac[acno];
2707 acno < IEEE80211_NUM_ACS; acno++, ac++) {
2709 ac->clear_ps_filter = true;
2710 ac->txq = sc->tx.txq_map[acno];
2711 INIT_LIST_HEAD(&ac->tid_q);
2715 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2717 struct ath_atx_ac *ac;
2718 struct ath_atx_tid *tid;
2719 struct ath_txq *txq;
2722 for (tidno = 0, tid = &an->tid[tidno];
2723 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
2728 ath_txq_lock(sc, txq);
2731 list_del(&tid->list);
2736 list_del(&ac->list);
2737 tid->ac->sched = false;
2740 ath_tid_drain(sc, txq, tid);
2741 tid->active = false;
2743 ath_txq_unlock(sc, txq);