2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define TIME_SYMBOLS(t) ((t) >> 2)
33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
38 static u16 bits_per_symbol[][2] = {
40 { 26, 54 }, /* 0: BPSK */
41 { 52, 108 }, /* 1: QPSK 1/2 */
42 { 78, 162 }, /* 2: QPSK 3/4 */
43 { 104, 216 }, /* 3: 16-QAM 1/2 */
44 { 156, 324 }, /* 4: 16-QAM 3/4 */
45 { 208, 432 }, /* 5: 64-QAM 2/3 */
46 { 234, 486 }, /* 6: 64-QAM 3/4 */
47 { 260, 540 }, /* 7: 64-QAM 5/6 */
50 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
52 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
53 struct ath_atx_tid *tid, struct sk_buff *skb);
54 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
55 int tx_flags, struct ath_txq *txq);
56 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
57 struct ath_txq *txq, struct list_head *bf_q,
58 struct ath_tx_status *ts, int txok);
59 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
60 struct list_head *head, bool internal);
61 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
62 struct ath_tx_status *ts, int nframes, int nbad,
64 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
66 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
68 struct ath_atx_tid *tid,
78 /*********************/
79 /* Aggregation logic */
80 /*********************/
82 void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq)
83 __acquires(&txq->axq_lock)
85 spin_lock_bh(&txq->axq_lock);
88 void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq)
89 __releases(&txq->axq_lock)
91 spin_unlock_bh(&txq->axq_lock);
94 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
95 __releases(&txq->axq_lock)
97 struct sk_buff_head q;
100 __skb_queue_head_init(&q);
101 skb_queue_splice_init(&txq->complete_q, &q);
102 spin_unlock_bh(&txq->axq_lock);
104 while ((skb = __skb_dequeue(&q)))
105 ieee80211_tx_status(sc->hw, skb);
108 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
110 struct ath_atx_ac *ac = tid->ac;
119 list_add_tail(&tid->list, &ac->tid_q);
125 list_add_tail(&ac->list, &txq->axq_acq);
128 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
130 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
131 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
132 sizeof(tx_info->rate_driver_data));
133 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
136 static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
138 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
139 seqno << IEEE80211_SEQ_SEQ_SHIFT);
142 static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta,
145 ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates,
146 ARRAY_SIZE(bf->rates));
149 static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq,
154 q = skb_get_queue_mapping(skb);
155 if (txq == sc->tx.uapsdq)
156 txq = sc->tx.txq_map[q];
158 if (txq != sc->tx.txq_map[q])
161 if (WARN_ON(--txq->pending_frames < 0))
162 txq->pending_frames = 0;
165 txq->pending_frames < sc->tx.txq_max_pending[q]) {
166 ieee80211_wake_queue(sc->hw, q);
167 txq->stopped = false;
171 static bool ath_tid_has_buffered(struct ath_atx_tid *tid)
173 return !skb_queue_empty(&tid->buf_q);
176 static struct sk_buff *ath_tid_dequeue(struct ath_atx_tid *tid)
178 return __skb_dequeue(&tid->buf_q);
181 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
183 struct ath_txq *txq = tid->ac->txq;
186 struct list_head bf_head;
187 struct ath_tx_status ts;
188 struct ath_frame_info *fi;
189 bool sendbar = false;
191 INIT_LIST_HEAD(&bf_head);
193 memset(&ts, 0, sizeof(ts));
195 while ((skb = ath_tid_dequeue(tid))) {
196 fi = get_frame_info(skb);
200 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
202 ath_txq_skb_done(sc, txq, skb);
203 ieee80211_free_txskb(sc->hw, skb);
209 list_add_tail(&bf->list, &bf_head);
210 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
211 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
214 ath_set_rates(tid->an->vif, tid->an->sta, bf);
215 ath_tx_send_normal(sc, txq, NULL, skb);
220 ath_txq_unlock(sc, txq);
221 ath_send_bar(tid, tid->seq_start);
222 ath_txq_lock(sc, txq);
226 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
231 index = ATH_BA_INDEX(tid->seq_start, seqno);
232 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
234 __clear_bit(cindex, tid->tx_buf);
236 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
237 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
238 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
239 if (tid->bar_index >= 0)
244 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
249 index = ATH_BA_INDEX(tid->seq_start, seqno);
250 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
251 __set_bit(cindex, tid->tx_buf);
253 if (index >= ((tid->baw_tail - tid->baw_head) &
254 (ATH_TID_MAX_BUFS - 1))) {
255 tid->baw_tail = cindex;
256 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
261 * TODO: For frame(s) that are in the retry state, we will reuse the
262 * sequence number(s) without setting the retry bit. The
263 * alternative is to give up on these and BAR the receiver's window
266 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
267 struct ath_atx_tid *tid)
272 struct list_head bf_head;
273 struct ath_tx_status ts;
274 struct ath_frame_info *fi;
276 memset(&ts, 0, sizeof(ts));
277 INIT_LIST_HEAD(&bf_head);
279 while ((skb = ath_tid_dequeue(tid))) {
280 fi = get_frame_info(skb);
284 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
288 list_add_tail(&bf->list, &bf_head);
290 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
291 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
294 tid->seq_next = tid->seq_start;
295 tid->baw_tail = tid->baw_head;
299 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
300 struct sk_buff *skb, int count)
302 struct ath_frame_info *fi = get_frame_info(skb);
303 struct ath_buf *bf = fi->bf;
304 struct ieee80211_hdr *hdr;
305 int prev = fi->retries;
307 TX_STAT_INC(txq->axq_qnum, a_retries);
308 fi->retries += count;
313 hdr = (struct ieee80211_hdr *)skb->data;
314 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
315 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
316 sizeof(*hdr), DMA_TO_DEVICE);
319 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
321 struct ath_buf *bf = NULL;
323 spin_lock_bh(&sc->tx.txbuflock);
325 if (unlikely(list_empty(&sc->tx.txbuf))) {
326 spin_unlock_bh(&sc->tx.txbuflock);
330 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
333 spin_unlock_bh(&sc->tx.txbuflock);
338 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
340 spin_lock_bh(&sc->tx.txbuflock);
341 list_add_tail(&bf->list, &sc->tx.txbuf);
342 spin_unlock_bh(&sc->tx.txbuflock);
345 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
349 tbf = ath_tx_get_buffer(sc);
353 ATH_TXBUF_RESET(tbf);
355 tbf->bf_mpdu = bf->bf_mpdu;
356 tbf->bf_buf_addr = bf->bf_buf_addr;
357 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
358 tbf->bf_state = bf->bf_state;
363 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
364 struct ath_tx_status *ts, int txok,
365 int *nframes, int *nbad)
367 struct ath_frame_info *fi;
369 u32 ba[WME_BA_BMP_SIZE >> 5];
376 isaggr = bf_isaggr(bf);
378 seq_st = ts->ts_seqnum;
379 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
383 fi = get_frame_info(bf->bf_mpdu);
384 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
387 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
395 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
396 struct ath_buf *bf, struct list_head *bf_q,
397 struct ath_tx_status *ts, int txok)
399 struct ath_node *an = NULL;
401 struct ieee80211_sta *sta;
402 struct ieee80211_hw *hw = sc->hw;
403 struct ieee80211_hdr *hdr;
404 struct ieee80211_tx_info *tx_info;
405 struct ath_atx_tid *tid = NULL;
406 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
407 struct list_head bf_head;
408 struct sk_buff_head bf_pending;
409 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
410 u32 ba[WME_BA_BMP_SIZE >> 5];
411 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
412 bool rc_update = true, isba;
413 struct ieee80211_tx_rate rates[4];
414 struct ath_frame_info *fi;
417 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
422 hdr = (struct ieee80211_hdr *)skb->data;
424 tx_info = IEEE80211_SKB_CB(skb);
426 memcpy(rates, bf->rates, sizeof(rates));
428 retries = ts->ts_longretry + 1;
429 for (i = 0; i < ts->ts_rateindex; i++)
430 retries += rates[i].count;
434 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
438 INIT_LIST_HEAD(&bf_head);
440 bf_next = bf->bf_next;
442 if (!bf->bf_stale || bf_next != NULL)
443 list_move_tail(&bf->list, &bf_head);
445 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 0);
452 an = (struct ath_node *)sta->drv_priv;
453 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
454 tid = ATH_AN_2_TID(an, tidno);
455 seq_first = tid->seq_start;
456 isba = ts->ts_flags & ATH9K_TX_BA;
459 * The hardware occasionally sends a tx status for the wrong TID.
460 * In this case, the BA status cannot be considered valid and all
461 * subframes need to be retransmitted
463 * Only BlockAcks have a TID and therefore normal Acks cannot be
466 if (isba && tidno != ts->tid)
469 isaggr = bf_isaggr(bf);
470 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
472 if (isaggr && txok) {
473 if (ts->ts_flags & ATH9K_TX_BA) {
474 seq_st = ts->ts_seqnum;
475 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
478 * AR5416 can become deaf/mute when BA
479 * issue happens. Chip needs to be reset.
480 * But AP code may have sychronization issues
481 * when perform internal reset in this routine.
482 * Only enable reset in STA mode for now.
484 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
489 __skb_queue_head_init(&bf_pending);
491 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
493 u16 seqno = bf->bf_state.seqno;
495 txfail = txpending = sendbar = 0;
496 bf_next = bf->bf_next;
499 tx_info = IEEE80211_SKB_CB(skb);
500 fi = get_frame_info(skb);
502 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) {
504 * Outside of the current BlockAck window,
505 * maybe part of a previous session
508 } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
509 /* transmit completion, subframe is
510 * acked by block ack */
512 } else if (!isaggr && txok) {
513 /* transmit completion */
517 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
518 if (txok || !an->sleeping)
519 ath_tx_set_retry(sc, txq, bf->bf_mpdu,
526 bar_index = max_t(int, bar_index,
527 ATH_BA_INDEX(seq_first, seqno));
531 * Make sure the last desc is reclaimed if it
532 * not a holding desc.
534 INIT_LIST_HEAD(&bf_head);
535 if (bf_next != NULL || !bf_last->bf_stale)
536 list_move_tail(&bf->list, &bf_head);
540 * complete the acked-ones/xretried ones; update
543 ath_tx_update_baw(sc, tid, seqno);
545 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
546 memcpy(tx_info->control.rates, rates, sizeof(rates));
547 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
551 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
554 if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) {
555 tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP;
556 ieee80211_sta_eosp(sta);
558 /* retry the un-acked ones */
559 if (bf->bf_next == NULL && bf_last->bf_stale) {
562 tbf = ath_clone_txbuf(sc, bf_last);
564 * Update tx baw and complete the
565 * frame with failed status if we
569 ath_tx_update_baw(sc, tid, seqno);
571 ath_tx_complete_buf(sc, bf, txq,
573 bar_index = max_t(int, bar_index,
574 ATH_BA_INDEX(seq_first, seqno));
582 * Put this buffer to the temporary pending
583 * queue to retain ordering
585 __skb_queue_tail(&bf_pending, skb);
591 /* prepend un-acked frames to the beginning of the pending frame queue */
592 if (!skb_queue_empty(&bf_pending)) {
594 ieee80211_sta_set_buffered(sta, tid->tidno, true);
596 skb_queue_splice(&bf_pending, &tid->buf_q);
598 ath_tx_queue_tid(txq, tid);
600 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
601 tid->ac->clear_ps_filter = true;
605 if (bar_index >= 0) {
606 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
608 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
609 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
611 ath_txq_unlock(sc, txq);
612 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
613 ath_txq_lock(sc, txq);
619 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
622 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
624 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
625 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
628 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
629 struct ath_tx_status *ts, struct ath_buf *bf,
630 struct list_head *bf_head)
632 struct ieee80211_tx_info *info;
635 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
636 flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
637 txq->axq_tx_inprogress = false;
640 if (bf_is_ampdu_not_probing(bf))
641 txq->axq_ampdu_depth--;
643 if (!bf_isampdu(bf)) {
645 info = IEEE80211_SKB_CB(bf->bf_mpdu);
646 memcpy(info->control.rates, bf->rates,
647 sizeof(info->control.rates));
648 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
650 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok);
652 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok);
654 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) && !flush)
655 ath_txq_schedule(sc, txq);
658 static bool ath_lookup_legacy(struct ath_buf *bf)
661 struct ieee80211_tx_info *tx_info;
662 struct ieee80211_tx_rate *rates;
666 tx_info = IEEE80211_SKB_CB(skb);
667 rates = tx_info->control.rates;
669 for (i = 0; i < 4; i++) {
670 if (!rates[i].count || rates[i].idx < 0)
673 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
680 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
681 struct ath_atx_tid *tid)
684 struct ieee80211_tx_info *tx_info;
685 struct ieee80211_tx_rate *rates;
686 u32 max_4ms_framelen, frmlen;
687 u16 aggr_limit, bt_aggr_limit, legacy = 0;
688 int q = tid->ac->txq->mac80211_qnum;
692 tx_info = IEEE80211_SKB_CB(skb);
696 * Find the lowest frame length among the rate series that will have a
697 * 4ms (or TXOP limited) transmit duration.
699 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
701 for (i = 0; i < 4; i++) {
707 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
712 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
717 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
720 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx];
721 max_4ms_framelen = min(max_4ms_framelen, frmlen);
725 * limit aggregate size by the minimum rate if rate selected is
726 * not a probe rate, if rate selected is a probe rate then
727 * avoid aggregation of this packet.
729 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
732 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX);
735 * Override the default aggregation limit for BTCOEX.
737 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen);
739 aggr_limit = bt_aggr_limit;
742 * h/w can accept aggregates up to 16 bit lengths (65535).
743 * The IE, however can hold up to 65536, which shows up here
744 * as zero. Ignore 65536 since we are constrained by hw.
746 if (tid->an->maxampdu)
747 aggr_limit = min(aggr_limit, tid->an->maxampdu);
753 * Returns the number of delimiters to be added to
754 * meet the minimum required mpdudensity.
756 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
757 struct ath_buf *bf, u16 frmlen,
760 #define FIRST_DESC_NDELIMS 60
761 u32 nsymbits, nsymbols;
764 int width, streams, half_gi, ndelim, mindelim;
765 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
767 /* Select standard number of delimiters based on frame length alone */
768 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
771 * If encryption enabled, hardware requires some more padding between
773 * TODO - this could be improved to be dependent on the rate.
774 * The hardware can keep up at lower rates, but not higher rates
776 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
777 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
778 ndelim += ATH_AGGR_ENCRYPTDELIM;
781 * Add delimiter when using RTS/CTS with aggregation
782 * and non enterprise AR9003 card
784 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
785 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
786 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
789 * Convert desired mpdu density from microeconds to bytes based
790 * on highest rate in rate series (i.e. first rate) to determine
791 * required minimum length for subframe. Take into account
792 * whether high rate is 20 or 40Mhz and half or full GI.
794 * If there is no mpdu density restriction, no further calculation
798 if (tid->an->mpdudensity == 0)
801 rix = bf->rates[0].idx;
802 flags = bf->rates[0].flags;
803 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
804 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
807 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
809 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
814 streams = HT_RC_2_STREAMS(rix);
815 nsymbits = bits_per_symbol[rix % 8][width] * streams;
816 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
818 if (frmlen < minlen) {
819 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
820 ndelim = max(mindelim, ndelim);
826 static struct ath_buf *
827 ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq,
828 struct ath_atx_tid *tid, struct sk_buff_head **q)
830 struct ath_frame_info *fi;
841 fi = get_frame_info(skb);
844 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
847 __skb_unlink(skb, *q);
848 ath_txq_skb_done(sc, txq, skb);
849 ieee80211_free_txskb(sc->hw, skb);
853 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
854 seqno = bf->bf_state.seqno;
856 /* do not step over block-ack window */
857 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno))
860 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
861 struct ath_tx_status ts = {};
862 struct list_head bf_head;
864 INIT_LIST_HEAD(&bf_head);
865 list_add(&bf->list, &bf_head);
866 __skb_unlink(skb, *q);
867 ath_tx_update_baw(sc, tid, seqno);
868 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
880 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
882 struct ath_atx_tid *tid,
883 struct list_head *bf_q,
886 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
887 struct ath_buf *bf, *bf_first = NULL, *bf_prev = NULL;
888 int rl = 0, nframes = 0, ndelim, prev_al = 0;
889 u16 aggr_limit = 0, al = 0, bpad = 0,
890 al_delta, h_baw = tid->baw_size / 2;
891 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
892 struct ieee80211_tx_info *tx_info;
893 struct ath_frame_info *fi;
895 struct sk_buff_head *tid_q;
898 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
900 status = ATH_AGGR_BAW_CLOSED;
905 fi = get_frame_info(skb);
911 ath_set_rates(tid->an->vif, tid->an->sta, bf);
912 aggr_limit = ath_lookup_rate(sc, bf, tid);
916 /* do not exceed aggregation limit */
917 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
920 ((aggr_limit < (al + bpad + al_delta + prev_al)) ||
921 ath_lookup_legacy(bf))) {
922 status = ATH_AGGR_LIMITED;
926 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
927 if (nframes && (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE))
930 /* do not exceed subframe limit */
931 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
932 status = ATH_AGGR_LIMITED;
936 /* add padding for previous frame to aggregation length */
937 al += bpad + al_delta;
940 * Get the delimiters needed to meet the MPDU
941 * density for this node.
943 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
945 bpad = PADBYTES(al_delta) + (ndelim << 2);
950 /* link buffers of this frame to the aggregate */
952 ath_tx_addto_baw(sc, tid, bf->bf_state.seqno);
953 bf->bf_state.ndelim = ndelim;
955 __skb_unlink(skb, tid_q);
956 list_add_tail(&bf->list, bf_q);
958 bf_prev->bf_next = bf;
962 } while (ath_tid_has_buffered(tid));
972 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
973 * width - 0 for 20 MHz, 1 for 40 MHz
974 * half_gi - to use 4us v/s 3.6 us for symbol time
976 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
977 int width, int half_gi, bool shortPreamble)
979 u32 nbits, nsymbits, duration, nsymbols;
982 /* find number of symbols: PLCP + data */
983 streams = HT_RC_2_STREAMS(rix);
984 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
985 nsymbits = bits_per_symbol[rix % 8][width] * streams;
986 nsymbols = (nbits + nsymbits - 1) / nsymbits;
989 duration = SYMBOL_TIME(nsymbols);
991 duration = SYMBOL_TIME_HALFGI(nsymbols);
993 /* addup duration for legacy/ht training and signal fields */
994 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
999 static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi)
1001 int streams = HT_RC_2_STREAMS(mcs);
1005 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec);
1006 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams;
1007 bits -= OFDM_PLCP_BITS;
1009 bytes -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1016 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop)
1018 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi;
1021 /* 4ms is the default (and maximum) duration */
1022 if (!txop || txop > 4096)
1025 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20];
1026 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI];
1027 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40];
1028 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI];
1029 for (mcs = 0; mcs < 32; mcs++) {
1030 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false);
1031 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true);
1032 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false);
1033 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true);
1037 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
1038 struct ath_tx_info *info, int len, bool rts)
1040 struct ath_hw *ah = sc->sc_ah;
1041 struct sk_buff *skb;
1042 struct ieee80211_tx_info *tx_info;
1043 struct ieee80211_tx_rate *rates;
1044 const struct ieee80211_rate *rate;
1045 struct ieee80211_hdr *hdr;
1046 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1047 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1052 tx_info = IEEE80211_SKB_CB(skb);
1054 hdr = (struct ieee80211_hdr *)skb->data;
1056 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1057 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
1058 info->rtscts_rate = fi->rtscts_rate;
1060 for (i = 0; i < ARRAY_SIZE(bf->rates); i++) {
1061 bool is_40, is_sgi, is_sp;
1064 if (!rates[i].count || (rates[i].idx < 0))
1068 info->rates[i].Tries = rates[i].count;
1071 * Handle RTS threshold for unaggregated HT frames.
1073 if (bf_isampdu(bf) && !bf_isaggr(bf) &&
1074 (rates[i].flags & IEEE80211_TX_RC_MCS) &&
1075 unlikely(rts_thresh != (u32) -1)) {
1076 if (!rts_thresh || (len > rts_thresh))
1080 if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1081 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1082 info->flags |= ATH9K_TXDESC_RTSENA;
1083 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1084 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1085 info->flags |= ATH9K_TXDESC_CTSENA;
1088 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1089 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
1090 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1091 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1093 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1094 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1095 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1097 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1099 info->rates[i].Rate = rix | 0x80;
1100 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1101 ah->txchainmask, info->rates[i].Rate);
1102 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
1103 is_40, is_sgi, is_sp);
1104 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1105 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
1110 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
1111 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1112 !(rate->flags & IEEE80211_RATE_ERP_G))
1113 phy = WLAN_RC_PHY_CCK;
1115 phy = WLAN_RC_PHY_OFDM;
1117 info->rates[i].Rate = rate->hw_value;
1118 if (rate->hw_value_short) {
1119 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1120 info->rates[i].Rate |= rate->hw_value_short;
1125 if (bf->bf_state.bfs_paprd)
1126 info->rates[i].ChSel = ah->txchainmask;
1128 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1129 ah->txchainmask, info->rates[i].Rate);
1131 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1132 phy, rate->bitrate * 100, len, rix, is_sp);
1135 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1136 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1137 info->flags &= ~ATH9K_TXDESC_RTSENA;
1139 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1140 if (info->flags & ATH9K_TXDESC_RTSENA)
1141 info->flags &= ~ATH9K_TXDESC_CTSENA;
1144 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1146 struct ieee80211_hdr *hdr;
1147 enum ath9k_pkt_type htype;
1150 hdr = (struct ieee80211_hdr *)skb->data;
1151 fc = hdr->frame_control;
1153 if (ieee80211_is_beacon(fc))
1154 htype = ATH9K_PKT_TYPE_BEACON;
1155 else if (ieee80211_is_probe_resp(fc))
1156 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1157 else if (ieee80211_is_atim(fc))
1158 htype = ATH9K_PKT_TYPE_ATIM;
1159 else if (ieee80211_is_pspoll(fc))
1160 htype = ATH9K_PKT_TYPE_PSPOLL;
1162 htype = ATH9K_PKT_TYPE_NORMAL;
1167 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1168 struct ath_txq *txq, int len)
1170 struct ath_hw *ah = sc->sc_ah;
1171 struct ath_buf *bf_first = NULL;
1172 struct ath_tx_info info;
1173 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1176 memset(&info, 0, sizeof(info));
1177 info.is_first = true;
1178 info.is_last = true;
1179 info.txpower = MAX_RATE_POWER;
1180 info.qcu = txq->axq_qnum;
1183 struct sk_buff *skb = bf->bf_mpdu;
1184 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1185 struct ath_frame_info *fi = get_frame_info(skb);
1186 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1188 info.type = get_hw_packet_type(skb);
1190 info.link = bf->bf_next->bf_daddr;
1197 info.flags = ATH9K_TXDESC_INTREQ;
1198 if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) ||
1199 txq == sc->tx.uapsdq)
1200 info.flags |= ATH9K_TXDESC_CLRDMASK;
1202 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1203 info.flags |= ATH9K_TXDESC_NOACK;
1204 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1205 info.flags |= ATH9K_TXDESC_LDPC;
1207 if (bf->bf_state.bfs_paprd)
1208 info.flags |= (u32) bf->bf_state.bfs_paprd <<
1209 ATH9K_TXDESC_PAPRD_S;
1212 * mac80211 doesn't handle RTS threshold for HT because
1213 * the decision has to be taken based on AMPDU length
1214 * and aggregation is done entirely inside ath9k.
1215 * Set the RTS/CTS flag for the first subframe based
1218 if (aggr && (bf == bf_first) &&
1219 unlikely(rts_thresh != (u32) -1)) {
1221 * "len" is the size of the entire AMPDU.
1223 if (!rts_thresh || (len > rts_thresh))
1226 ath_buf_set_rate(sc, bf, &info, len, rts);
1229 info.buf_addr[0] = bf->bf_buf_addr;
1230 info.buf_len[0] = skb->len;
1231 info.pkt_len = fi->framelen;
1232 info.keyix = fi->keyix;
1233 info.keytype = fi->keytype;
1237 info.aggr = AGGR_BUF_FIRST;
1238 else if (bf == bf_first->bf_lastbf)
1239 info.aggr = AGGR_BUF_LAST;
1241 info.aggr = AGGR_BUF_MIDDLE;
1243 info.ndelim = bf->bf_state.ndelim;
1244 info.aggr_len = len;
1247 if (bf == bf_first->bf_lastbf)
1250 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1255 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1256 struct ath_atx_tid *tid)
1259 enum ATH_AGGR_STATUS status;
1260 struct ieee80211_tx_info *tx_info;
1261 struct list_head bf_q;
1265 if (!ath_tid_has_buffered(tid))
1268 INIT_LIST_HEAD(&bf_q);
1270 status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len);
1273 * no frames picked up to be aggregated;
1274 * block-ack window is not open.
1276 if (list_empty(&bf_q))
1279 bf = list_first_entry(&bf_q, struct ath_buf, list);
1280 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
1281 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1283 if (tid->ac->clear_ps_filter) {
1284 tid->ac->clear_ps_filter = false;
1285 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1287 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
1290 /* if only one frame, send as non-aggregate */
1291 if (bf == bf->bf_lastbf) {
1292 aggr_len = get_frame_info(bf->bf_mpdu)->framelen;
1293 bf->bf_state.bf_type = BUF_AMPDU;
1295 TX_STAT_INC(txq->axq_qnum, a_aggr);
1298 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1299 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1300 } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH &&
1301 status != ATH_AGGR_BAW_CLOSED);
1304 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1307 struct ath_atx_tid *txtid;
1308 struct ath_node *an;
1311 an = (struct ath_node *)sta->drv_priv;
1312 txtid = ATH_AN_2_TID(an, tid);
1314 /* update ampdu factor/density, they may have changed. This may happen
1315 * in HT IBSS when a beacon with HT-info is received after the station
1316 * has already been added.
1318 if (sta->ht_cap.ht_supported) {
1319 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
1320 sta->ht_cap.ampdu_factor);
1321 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
1322 an->mpdudensity = density;
1325 txtid->active = true;
1326 txtid->paused = true;
1327 *ssn = txtid->seq_start = txtid->seq_next;
1328 txtid->bar_index = -1;
1330 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1331 txtid->baw_head = txtid->baw_tail = 0;
1336 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1338 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1339 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1340 struct ath_txq *txq = txtid->ac->txq;
1342 ath_txq_lock(sc, txq);
1343 txtid->active = false;
1344 txtid->paused = true;
1345 ath_tx_flush_tid(sc, txtid);
1346 ath_txq_unlock_complete(sc, txq);
1349 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1350 struct ath_node *an)
1352 struct ath_atx_tid *tid;
1353 struct ath_atx_ac *ac;
1354 struct ath_txq *txq;
1358 for (tidno = 0, tid = &an->tid[tidno];
1359 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1367 ath_txq_lock(sc, txq);
1369 buffered = ath_tid_has_buffered(tid);
1372 list_del(&tid->list);
1376 list_del(&ac->list);
1379 ath_txq_unlock(sc, txq);
1381 ieee80211_sta_set_buffered(sta, tidno, buffered);
1385 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1387 struct ath_atx_tid *tid;
1388 struct ath_atx_ac *ac;
1389 struct ath_txq *txq;
1392 for (tidno = 0, tid = &an->tid[tidno];
1393 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1398 ath_txq_lock(sc, txq);
1399 ac->clear_ps_filter = true;
1401 if (!tid->paused && ath_tid_has_buffered(tid)) {
1402 ath_tx_queue_tid(txq, tid);
1403 ath_txq_schedule(sc, txq);
1406 ath_txq_unlock_complete(sc, txq);
1410 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta,
1413 struct ath_atx_tid *tid;
1414 struct ath_node *an;
1415 struct ath_txq *txq;
1417 an = (struct ath_node *)sta->drv_priv;
1418 tid = ATH_AN_2_TID(an, tidno);
1421 ath_txq_lock(sc, txq);
1423 tid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
1424 tid->paused = false;
1426 if (ath_tid_has_buffered(tid)) {
1427 ath_tx_queue_tid(txq, tid);
1428 ath_txq_schedule(sc, txq);
1431 ath_txq_unlock_complete(sc, txq);
1434 void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
1435 struct ieee80211_sta *sta,
1436 u16 tids, int nframes,
1437 enum ieee80211_frame_release_type reason,
1440 struct ath_softc *sc = hw->priv;
1441 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1442 struct ath_txq *txq = sc->tx.uapsdq;
1443 struct ieee80211_tx_info *info;
1444 struct list_head bf_q;
1445 struct ath_buf *bf_tail = NULL, *bf;
1446 struct sk_buff_head *tid_q;
1450 INIT_LIST_HEAD(&bf_q);
1451 for (i = 0; tids && nframes; i++, tids >>= 1) {
1452 struct ath_atx_tid *tid;
1457 tid = ATH_AN_2_TID(an, i);
1461 ath_txq_lock(sc, tid->ac->txq);
1462 while (nframes > 0) {
1463 bf = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq, tid, &tid_q);
1467 __skb_unlink(bf->bf_mpdu, tid_q);
1468 list_add_tail(&bf->list, &bf_q);
1469 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1470 ath_tx_addto_baw(sc, tid, bf->bf_state.seqno);
1471 bf->bf_state.bf_type &= ~BUF_AGGR;
1473 bf_tail->bf_next = bf;
1478 TX_STAT_INC(txq->axq_qnum, a_queued_hw);
1480 if (!ath_tid_has_buffered(tid))
1481 ieee80211_sta_set_buffered(an->sta, i, false);
1483 ath_txq_unlock_complete(sc, tid->ac->txq);
1486 if (list_empty(&bf_q))
1489 info = IEEE80211_SKB_CB(bf_tail->bf_mpdu);
1490 info->flags |= IEEE80211_TX_STATUS_EOSP;
1492 bf = list_first_entry(&bf_q, struct ath_buf, list);
1493 ath_txq_lock(sc, txq);
1494 ath_tx_fill_desc(sc, bf, txq, 0);
1495 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1496 ath_txq_unlock(sc, txq);
1499 /********************/
1500 /* Queue Management */
1501 /********************/
1503 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1505 struct ath_hw *ah = sc->sc_ah;
1506 struct ath9k_tx_queue_info qi;
1507 static const int subtype_txq_to_hwq[] = {
1508 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE,
1509 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK,
1510 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI,
1511 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO,
1515 memset(&qi, 0, sizeof(qi));
1516 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1517 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1518 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1519 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1520 qi.tqi_physCompBuf = 0;
1523 * Enable interrupts only for EOL and DESC conditions.
1524 * We mark tx descriptors to receive a DESC interrupt
1525 * when a tx queue gets deep; otherwise waiting for the
1526 * EOL to reap descriptors. Note that this is done to
1527 * reduce interrupt load and this only defers reaping
1528 * descriptors, never transmitting frames. Aside from
1529 * reducing interrupts this also permits more concurrency.
1530 * The only potential downside is if the tx queue backs
1531 * up in which case the top half of the kernel may backup
1532 * due to a lack of tx descriptors.
1534 * The UAPSD queue is an exception, since we take a desc-
1535 * based intr on the EOSP frames.
1537 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1538 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
1540 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1541 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1543 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1544 TXQ_FLAG_TXDESCINT_ENABLE;
1546 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1547 if (axq_qnum == -1) {
1549 * NB: don't print a message, this happens
1550 * normally on parts with too few tx queues
1554 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1555 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1557 txq->axq_qnum = axq_qnum;
1558 txq->mac80211_qnum = -1;
1559 txq->axq_link = NULL;
1560 __skb_queue_head_init(&txq->complete_q);
1561 INIT_LIST_HEAD(&txq->axq_q);
1562 INIT_LIST_HEAD(&txq->axq_acq);
1563 spin_lock_init(&txq->axq_lock);
1565 txq->axq_ampdu_depth = 0;
1566 txq->axq_tx_inprogress = false;
1567 sc->tx.txqsetup |= 1<<axq_qnum;
1569 txq->txq_headidx = txq->txq_tailidx = 0;
1570 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1571 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1573 return &sc->tx.txq[axq_qnum];
1576 int ath_txq_update(struct ath_softc *sc, int qnum,
1577 struct ath9k_tx_queue_info *qinfo)
1579 struct ath_hw *ah = sc->sc_ah;
1581 struct ath9k_tx_queue_info qi;
1583 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1585 ath9k_hw_get_txq_props(ah, qnum, &qi);
1586 qi.tqi_aifs = qinfo->tqi_aifs;
1587 qi.tqi_cwmin = qinfo->tqi_cwmin;
1588 qi.tqi_cwmax = qinfo->tqi_cwmax;
1589 qi.tqi_burstTime = qinfo->tqi_burstTime;
1590 qi.tqi_readyTime = qinfo->tqi_readyTime;
1592 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1593 ath_err(ath9k_hw_common(sc->sc_ah),
1594 "Unable to update hardware queue %u!\n", qnum);
1597 ath9k_hw_resettxqueue(ah, qnum);
1603 int ath_cabq_update(struct ath_softc *sc)
1605 struct ath9k_tx_queue_info qi;
1606 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
1607 int qnum = sc->beacon.cabq->axq_qnum;
1609 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1611 * Ensure the readytime % is within the bounds.
1613 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1614 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1615 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1616 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1618 qi.tqi_readyTime = (cur_conf->beacon_interval *
1619 sc->config.cabqReadytime) / 100;
1620 ath_txq_update(sc, qnum, &qi);
1625 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1626 struct list_head *list)
1628 struct ath_buf *bf, *lastbf;
1629 struct list_head bf_head;
1630 struct ath_tx_status ts;
1632 memset(&ts, 0, sizeof(ts));
1633 ts.ts_status = ATH9K_TX_FLUSH;
1634 INIT_LIST_HEAD(&bf_head);
1636 while (!list_empty(list)) {
1637 bf = list_first_entry(list, struct ath_buf, list);
1640 list_del(&bf->list);
1642 ath_tx_return_buffer(sc, bf);
1646 lastbf = bf->bf_lastbf;
1647 list_cut_position(&bf_head, list, &lastbf->list);
1648 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
1653 * Drain a given TX queue (could be Beacon or Data)
1655 * This assumes output has been stopped and
1656 * we do not need to block ath_tx_tasklet.
1658 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq)
1660 ath_txq_lock(sc, txq);
1662 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1663 int idx = txq->txq_tailidx;
1665 while (!list_empty(&txq->txq_fifo[idx])) {
1666 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]);
1668 INCR(idx, ATH_TXFIFO_DEPTH);
1670 txq->txq_tailidx = idx;
1673 txq->axq_link = NULL;
1674 txq->axq_tx_inprogress = false;
1675 ath_drain_txq_list(sc, txq, &txq->axq_q);
1677 ath_txq_unlock_complete(sc, txq);
1680 bool ath_drain_all_txq(struct ath_softc *sc)
1682 struct ath_hw *ah = sc->sc_ah;
1683 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1684 struct ath_txq *txq;
1688 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
1691 ath9k_hw_abort_tx_dma(ah);
1693 /* Check if any queue remains active */
1694 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1695 if (!ATH_TXQ_SETUP(sc, i))
1698 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1703 ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1705 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1706 if (!ATH_TXQ_SETUP(sc, i))
1710 * The caller will resume queues with ieee80211_wake_queues.
1711 * Mark the queue as not stopped to prevent ath_tx_complete
1712 * from waking the queue too early.
1714 txq = &sc->tx.txq[i];
1715 txq->stopped = false;
1716 ath_draintxq(sc, txq);
1722 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1724 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1725 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1728 /* For each axq_acq entry, for each tid, try to schedule packets
1729 * for transmit until ampdu_depth has reached min Q depth.
1731 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1733 struct ath_atx_ac *ac, *ac_tmp, *last_ac;
1734 struct ath_atx_tid *tid, *last_tid;
1736 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags) ||
1737 list_empty(&txq->axq_acq) ||
1738 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1743 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1744 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
1746 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1747 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1748 list_del(&ac->list);
1751 while (!list_empty(&ac->tid_q)) {
1752 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1754 list_del(&tid->list);
1760 ath_tx_sched_aggr(sc, txq, tid);
1763 * add tid to round-robin queue if more frames
1764 * are pending for the tid
1766 if (ath_tid_has_buffered(tid))
1767 ath_tx_queue_tid(txq, tid);
1769 if (tid == last_tid ||
1770 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1774 if (!list_empty(&ac->tid_q) && !ac->sched) {
1776 list_add_tail(&ac->list, &txq->axq_acq);
1779 if (ac == last_ac ||
1780 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1792 * Insert a chain of ath_buf (descriptors) on a txq and
1793 * assume the descriptors are already chained together by caller.
1795 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1796 struct list_head *head, bool internal)
1798 struct ath_hw *ah = sc->sc_ah;
1799 struct ath_common *common = ath9k_hw_common(ah);
1800 struct ath_buf *bf, *bf_last;
1801 bool puttxbuf = false;
1805 * Insert the frame on the outbound list and
1806 * pass it on to the hardware.
1809 if (list_empty(head))
1812 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1813 bf = list_first_entry(head, struct ath_buf, list);
1814 bf_last = list_entry(head->prev, struct ath_buf, list);
1816 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n",
1817 txq->axq_qnum, txq->axq_depth);
1819 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1820 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
1821 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1824 list_splice_tail_init(head, &txq->axq_q);
1826 if (txq->axq_link) {
1827 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
1828 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n",
1829 txq->axq_qnum, txq->axq_link,
1830 ito64(bf->bf_daddr), bf->bf_desc);
1834 txq->axq_link = bf_last->bf_desc;
1838 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1839 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1840 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n",
1841 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1845 TX_STAT_INC(txq->axq_qnum, txstart);
1846 ath9k_hw_txstart(ah, txq->axq_qnum);
1852 if (bf_is_ampdu_not_probing(bf))
1853 txq->axq_ampdu_depth++;
1855 bf = bf->bf_lastbf->bf_next;
1860 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_txq *txq,
1861 struct ath_atx_tid *tid, struct sk_buff *skb,
1862 struct ath_tx_control *txctl)
1864 struct ath_frame_info *fi = get_frame_info(skb);
1865 struct list_head bf_head;
1869 * Do not queue to h/w when any of the following conditions is true:
1870 * - there are pending frames in software queue
1871 * - the TID is currently paused for ADDBA/BAR request
1872 * - seqno is not within block-ack window
1873 * - h/w queue depth exceeds low water mark
1875 if ((ath_tid_has_buffered(tid) || tid->paused ||
1876 !BAW_WITHIN(tid->seq_start, tid->baw_size, tid->seq_next) ||
1877 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) &&
1878 txq != sc->tx.uapsdq) {
1880 * Add this frame to software queue for scheduling later
1883 TX_STAT_INC(txq->axq_qnum, a_queued_sw);
1884 __skb_queue_tail(&tid->buf_q, skb);
1885 if (!txctl->an || !txctl->an->sleeping)
1886 ath_tx_queue_tid(txq, tid);
1890 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
1892 ath_txq_skb_done(sc, txq, skb);
1893 ieee80211_free_txskb(sc->hw, skb);
1897 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1898 bf->bf_state.bf_type = BUF_AMPDU;
1899 INIT_LIST_HEAD(&bf_head);
1900 list_add(&bf->list, &bf_head);
1902 /* Add sub-frame to BAW */
1903 ath_tx_addto_baw(sc, tid, bf->bf_state.seqno);
1905 /* Queue to h/w without aggregation */
1906 TX_STAT_INC(txq->axq_qnum, a_queued_hw);
1908 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
1909 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
1912 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1913 struct ath_atx_tid *tid, struct sk_buff *skb)
1915 struct ath_frame_info *fi = get_frame_info(skb);
1916 struct list_head bf_head;
1921 INIT_LIST_HEAD(&bf_head);
1922 list_add_tail(&bf->list, &bf_head);
1923 bf->bf_state.bf_type = 0;
1927 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
1928 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
1929 TX_STAT_INC(txq->axq_qnum, queued);
1932 static void setup_frame_info(struct ieee80211_hw *hw,
1933 struct ieee80211_sta *sta,
1934 struct sk_buff *skb,
1937 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1938 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1939 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1940 const struct ieee80211_rate *rate;
1941 struct ath_frame_info *fi = get_frame_info(skb);
1942 struct ath_node *an = NULL;
1943 enum ath9k_key_type keytype;
1944 bool short_preamble = false;
1947 * We check if Short Preamble is needed for the CTS rate by
1948 * checking the BSS's global flag.
1949 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1951 if (tx_info->control.vif &&
1952 tx_info->control.vif->bss_conf.use_short_preamble)
1953 short_preamble = true;
1955 rate = ieee80211_get_rts_cts_rate(hw, tx_info);
1956 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
1959 an = (struct ath_node *) sta->drv_priv;
1961 memset(fi, 0, sizeof(*fi));
1963 fi->keyix = hw_key->hw_key_idx;
1964 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
1965 fi->keyix = an->ps_key;
1967 fi->keyix = ATH9K_TXKEYIX_INVALID;
1968 fi->keytype = keytype;
1969 fi->framelen = framelen;
1970 fi->rtscts_rate = rate->hw_value;
1972 fi->rtscts_rate |= rate->hw_value_short;
1975 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
1977 struct ath_hw *ah = sc->sc_ah;
1978 struct ath9k_channel *curchan = ah->curchan;
1980 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) &&
1981 (curchan->channelFlags & CHANNEL_5GHZ) &&
1982 (chainmask == 0x7) && (rate < 0x90))
1984 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
1992 * Assign a descriptor (and sequence number if necessary,
1993 * and map buffer for DMA. Frees skb on error
1995 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
1996 struct ath_txq *txq,
1997 struct ath_atx_tid *tid,
1998 struct sk_buff *skb)
2000 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2001 struct ath_frame_info *fi = get_frame_info(skb);
2002 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2007 bf = ath_tx_get_buffer(sc);
2009 ath_dbg(common, XMIT, "TX buffers are full\n");
2013 ATH_TXBUF_RESET(bf);
2016 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
2017 seqno = tid->seq_next;
2018 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
2021 hdr->seq_ctrl |= cpu_to_le16(fragno);
2023 if (!ieee80211_has_morefrags(hdr->frame_control))
2024 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
2026 bf->bf_state.seqno = seqno;
2031 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
2032 skb->len, DMA_TO_DEVICE);
2033 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
2035 bf->bf_buf_addr = 0;
2036 ath_err(ath9k_hw_common(sc->sc_ah),
2037 "dma_mapping_error() on TX\n");
2038 ath_tx_return_buffer(sc, bf);
2047 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
2048 struct ath_tx_control *txctl)
2050 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2051 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2052 struct ieee80211_sta *sta = txctl->sta;
2053 struct ieee80211_vif *vif = info->control.vif;
2054 struct ath_softc *sc = hw->priv;
2055 int frmlen = skb->len + FCS_LEN;
2056 int padpos, padsize;
2058 /* NOTE: sta can be NULL according to net/mac80211.h */
2060 txctl->an = (struct ath_node *)sta->drv_priv;
2062 if (info->control.hw_key)
2063 frmlen += info->control.hw_key->icv_len;
2066 * As a temporary workaround, assign seq# here; this will likely need
2067 * to be cleaned up to work better with Beacon transmission and virtual
2070 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2071 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2072 sc->tx.seq_no += 0x10;
2073 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2074 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2077 if ((vif && vif->type != NL80211_IFTYPE_AP &&
2078 vif->type != NL80211_IFTYPE_AP_VLAN) ||
2079 !ieee80211_is_data(hdr->frame_control))
2080 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
2082 /* Add the padding after the header if this is not already done */
2083 padpos = ieee80211_hdrlen(hdr->frame_control);
2084 padsize = padpos & 3;
2085 if (padsize && skb->len > padpos) {
2086 if (skb_headroom(skb) < padsize)
2089 skb_push(skb, padsize);
2090 memmove(skb->data, skb->data + padsize, padpos);
2093 setup_frame_info(hw, sta, skb, frmlen);
2098 /* Upon failure caller should free skb */
2099 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
2100 struct ath_tx_control *txctl)
2102 struct ieee80211_hdr *hdr;
2103 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2104 struct ieee80211_sta *sta = txctl->sta;
2105 struct ieee80211_vif *vif = info->control.vif;
2106 struct ath_softc *sc = hw->priv;
2107 struct ath_txq *txq = txctl->txq;
2108 struct ath_atx_tid *tid = NULL;
2114 ret = ath_tx_prepare(hw, skb, txctl);
2118 hdr = (struct ieee80211_hdr *) skb->data;
2120 * At this point, the vif, hw_key and sta pointers in the tx control
2121 * info are no longer valid (overwritten by the ath_frame_info data.
2124 q = skb_get_queue_mapping(skb);
2126 ath_txq_lock(sc, txq);
2127 if (txq == sc->tx.txq_map[q] &&
2128 ++txq->pending_frames > sc->tx.txq_max_pending[q] &&
2130 ieee80211_stop_queue(sc->hw, q);
2131 txq->stopped = true;
2134 if (info->flags & IEEE80211_TX_CTL_PS_RESPONSE) {
2135 ath_txq_unlock(sc, txq);
2136 txq = sc->tx.uapsdq;
2137 ath_txq_lock(sc, txq);
2140 if (txctl->an && ieee80211_is_data_qos(hdr->frame_control)) {
2141 tidno = ieee80211_get_qos_ctl(hdr)[0] &
2142 IEEE80211_QOS_CTL_TID_MASK;
2143 tid = ATH_AN_2_TID(txctl->an, tidno);
2145 WARN_ON(tid->ac->txq != txctl->txq);
2148 if ((info->flags & IEEE80211_TX_CTL_AMPDU) && tid) {
2150 * Try aggregation if it's a unicast data frame
2151 * and the destination is HT capable.
2153 ath_tx_send_ampdu(sc, txq, tid, skb, txctl);
2157 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
2159 ath_txq_skb_done(sc, txq, skb);
2161 dev_kfree_skb_any(skb);
2163 ieee80211_free_txskb(sc->hw, skb);
2167 bf->bf_state.bfs_paprd = txctl->paprd;
2170 bf->bf_state.bfs_paprd_timestamp = jiffies;
2172 ath_set_rates(vif, sta, bf);
2173 ath_tx_send_normal(sc, txq, tid, skb);
2176 ath_txq_unlock(sc, txq);
2181 void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2182 struct sk_buff *skb)
2184 struct ath_softc *sc = hw->priv;
2185 struct ath_tx_control txctl = {
2186 .txq = sc->beacon.cabq
2188 struct ath_tx_info info = {};
2189 struct ieee80211_hdr *hdr;
2190 struct ath_buf *bf_tail = NULL;
2197 sc->cur_beacon_conf.beacon_interval * 1000 *
2198 sc->cur_beacon_conf.dtim_period / ATH_BCBUF;
2201 struct ath_frame_info *fi = get_frame_info(skb);
2203 if (ath_tx_prepare(hw, skb, &txctl))
2206 bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb);
2211 ath_set_rates(vif, NULL, bf);
2212 ath_buf_set_rate(sc, bf, &info, fi->framelen, false);
2213 duration += info.rates[0].PktDuration;
2215 bf_tail->bf_next = bf;
2217 list_add_tail(&bf->list, &bf_q);
2221 if (duration > max_duration)
2224 skb = ieee80211_get_buffered_bc(hw, vif);
2228 ieee80211_free_txskb(hw, skb);
2230 if (list_empty(&bf_q))
2233 bf = list_first_entry(&bf_q, struct ath_buf, list);
2234 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
2236 if (hdr->frame_control & IEEE80211_FCTL_MOREDATA) {
2237 hdr->frame_control &= ~IEEE80211_FCTL_MOREDATA;
2238 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
2239 sizeof(*hdr), DMA_TO_DEVICE);
2242 ath_txq_lock(sc, txctl.txq);
2243 ath_tx_fill_desc(sc, bf, txctl.txq, 0);
2244 ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false);
2245 TX_STAT_INC(txctl.txq->axq_qnum, queued);
2246 ath_txq_unlock(sc, txctl.txq);
2253 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
2254 int tx_flags, struct ath_txq *txq)
2256 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2257 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2258 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
2259 int padpos, padsize;
2260 unsigned long flags;
2262 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
2264 if (sc->sc_ah->caldata)
2265 sc->sc_ah->caldata->paprd_packet_sent = true;
2267 if (!(tx_flags & ATH_TX_ERROR))
2268 /* Frame was ACKed */
2269 tx_info->flags |= IEEE80211_TX_STAT_ACK;
2271 padpos = ieee80211_hdrlen(hdr->frame_control);
2272 padsize = padpos & 3;
2273 if (padsize && skb->len>padpos+padsize) {
2275 * Remove MAC header padding before giving the frame back to
2278 memmove(skb->data + padsize, skb->data, padpos);
2279 skb_pull(skb, padsize);
2282 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2283 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
2284 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
2286 "Going back to sleep after having received TX status (0x%lx)\n",
2287 sc->ps_flags & (PS_WAIT_FOR_BEACON |
2289 PS_WAIT_FOR_PSPOLL_DATA |
2290 PS_WAIT_FOR_TX_ACK));
2292 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2294 __skb_queue_tail(&txq->complete_q, skb);
2295 ath_txq_skb_done(sc, txq, skb);
2298 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
2299 struct ath_txq *txq, struct list_head *bf_q,
2300 struct ath_tx_status *ts, int txok)
2302 struct sk_buff *skb = bf->bf_mpdu;
2303 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2304 unsigned long flags;
2308 tx_flags |= ATH_TX_ERROR;
2310 if (ts->ts_status & ATH9K_TXERR_FILT)
2311 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2313 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2314 bf->bf_buf_addr = 0;
2316 if (bf->bf_state.bfs_paprd) {
2317 if (time_after(jiffies,
2318 bf->bf_state.bfs_paprd_timestamp +
2319 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2320 dev_kfree_skb_any(skb);
2322 complete(&sc->paprd_complete);
2324 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2325 ath_tx_complete(sc, skb, tx_flags, txq);
2327 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2328 * accidentally reference it later.
2333 * Return the list of ath_buf of this mpdu to free queue
2335 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2336 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2337 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2340 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2341 struct ath_tx_status *ts, int nframes, int nbad,
2344 struct sk_buff *skb = bf->bf_mpdu;
2345 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2346 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2347 struct ieee80211_hw *hw = sc->hw;
2348 struct ath_hw *ah = sc->sc_ah;
2352 tx_info->status.ack_signal = ts->ts_rssi;
2354 tx_rateindex = ts->ts_rateindex;
2355 WARN_ON(tx_rateindex >= hw->max_rates);
2357 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2358 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2360 BUG_ON(nbad > nframes);
2362 tx_info->status.ampdu_len = nframes;
2363 tx_info->status.ampdu_ack_len = nframes - nbad;
2365 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2366 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2368 * If an underrun error is seen assume it as an excessive
2369 * retry only if max frame trigger level has been reached
2370 * (2 KB for single stream, and 4 KB for dual stream).
2371 * Adjust the long retry as if the frame was tried
2372 * hw->max_rate_tries times to affect how rate control updates
2373 * PER for the failed rate.
2374 * In case of congestion on the bus penalizing this type of
2375 * underruns should help hardware actually transmit new frames
2376 * successfully by eventually preferring slower rates.
2377 * This itself should also alleviate congestion on the bus.
2379 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2380 ATH9K_TX_DELIM_UNDERRUN)) &&
2381 ieee80211_is_data(hdr->frame_control) &&
2382 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2383 tx_info->status.rates[tx_rateindex].count =
2387 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2388 tx_info->status.rates[i].count = 0;
2389 tx_info->status.rates[i].idx = -1;
2392 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2395 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2397 struct ath_hw *ah = sc->sc_ah;
2398 struct ath_common *common = ath9k_hw_common(ah);
2399 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2400 struct list_head bf_head;
2401 struct ath_desc *ds;
2402 struct ath_tx_status ts;
2405 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n",
2406 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2409 ath_txq_lock(sc, txq);
2411 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
2414 if (list_empty(&txq->axq_q)) {
2415 txq->axq_link = NULL;
2416 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2417 ath_txq_schedule(sc, txq);
2420 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2423 * There is a race condition that a BH gets scheduled
2424 * after sw writes TxE and before hw re-load the last
2425 * descriptor to get the newly chained one.
2426 * Software must keep the last DONE descriptor as a
2427 * holding descriptor - software does so by marking
2428 * it with the STALE flag.
2433 if (list_is_last(&bf_held->list, &txq->axq_q))
2436 bf = list_entry(bf_held->list.next, struct ath_buf,
2440 lastbf = bf->bf_lastbf;
2441 ds = lastbf->bf_desc;
2443 memset(&ts, 0, sizeof(ts));
2444 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2445 if (status == -EINPROGRESS)
2448 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2451 * Remove ath_buf's of the same transmit unit from txq,
2452 * however leave the last descriptor back as the holding
2453 * descriptor for hw.
2455 lastbf->bf_stale = true;
2456 INIT_LIST_HEAD(&bf_head);
2457 if (!list_is_singular(&lastbf->list))
2458 list_cut_position(&bf_head,
2459 &txq->axq_q, lastbf->list.prev);
2462 list_del(&bf_held->list);
2463 ath_tx_return_buffer(sc, bf_held);
2466 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2468 ath_txq_unlock_complete(sc, txq);
2471 void ath_tx_tasklet(struct ath_softc *sc)
2473 struct ath_hw *ah = sc->sc_ah;
2474 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;
2477 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2478 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2479 ath_tx_processq(sc, &sc->tx.txq[i]);
2483 void ath_tx_edma_tasklet(struct ath_softc *sc)
2485 struct ath_tx_status ts;
2486 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2487 struct ath_hw *ah = sc->sc_ah;
2488 struct ath_txq *txq;
2489 struct ath_buf *bf, *lastbf;
2490 struct list_head bf_head;
2491 struct list_head *fifo_list;
2495 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
2498 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2499 if (status == -EINPROGRESS)
2501 if (status == -EIO) {
2502 ath_dbg(common, XMIT, "Error processing tx status\n");
2506 /* Process beacon completions separately */
2507 if (ts.qid == sc->beacon.beaconq) {
2508 sc->beacon.tx_processed = true;
2509 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2513 txq = &sc->tx.txq[ts.qid];
2515 ath_txq_lock(sc, txq);
2517 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2519 fifo_list = &txq->txq_fifo[txq->txq_tailidx];
2520 if (list_empty(fifo_list)) {
2521 ath_txq_unlock(sc, txq);
2525 bf = list_first_entry(fifo_list, struct ath_buf, list);
2527 list_del(&bf->list);
2528 ath_tx_return_buffer(sc, bf);
2529 bf = list_first_entry(fifo_list, struct ath_buf, list);
2532 lastbf = bf->bf_lastbf;
2534 INIT_LIST_HEAD(&bf_head);
2535 if (list_is_last(&lastbf->list, fifo_list)) {
2536 list_splice_tail_init(fifo_list, &bf_head);
2537 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2539 if (!list_empty(&txq->axq_q)) {
2540 struct list_head bf_q;
2542 INIT_LIST_HEAD(&bf_q);
2543 txq->axq_link = NULL;
2544 list_splice_tail_init(&txq->axq_q, &bf_q);
2545 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2548 lastbf->bf_stale = true;
2550 list_cut_position(&bf_head, fifo_list,
2554 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2555 ath_txq_unlock_complete(sc, txq);
2563 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2565 struct ath_descdma *dd = &sc->txsdma;
2566 u8 txs_len = sc->sc_ah->caps.txs_len;
2568 dd->dd_desc_len = size * txs_len;
2569 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
2570 &dd->dd_desc_paddr, GFP_KERNEL);
2577 static int ath_tx_edma_init(struct ath_softc *sc)
2581 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2583 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2584 sc->txsdma.dd_desc_paddr,
2585 ATH_TXSTATUS_RING_SIZE);
2590 int ath_tx_init(struct ath_softc *sc, int nbufs)
2592 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2595 spin_lock_init(&sc->tx.txbuflock);
2597 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2601 "Failed to allocate tx descriptors: %d\n", error);
2605 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2606 "beacon", ATH_BCBUF, 1, 1);
2609 "Failed to allocate beacon descriptors: %d\n", error);
2613 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2615 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2616 error = ath_tx_edma_init(sc);
2621 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2623 struct ath_atx_tid *tid;
2624 struct ath_atx_ac *ac;
2627 for (tidno = 0, tid = &an->tid[tidno];
2628 tidno < IEEE80211_NUM_TIDS;
2632 tid->seq_start = tid->seq_next = 0;
2633 tid->baw_size = WME_MAX_BA;
2634 tid->baw_head = tid->baw_tail = 0;
2636 tid->paused = false;
2637 tid->active = false;
2638 __skb_queue_head_init(&tid->buf_q);
2639 acno = TID_TO_WME_AC(tidno);
2640 tid->ac = &an->ac[acno];
2643 for (acno = 0, ac = &an->ac[acno];
2644 acno < IEEE80211_NUM_ACS; acno++, ac++) {
2646 ac->txq = sc->tx.txq_map[acno];
2647 INIT_LIST_HEAD(&ac->tid_q);
2651 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2653 struct ath_atx_ac *ac;
2654 struct ath_atx_tid *tid;
2655 struct ath_txq *txq;
2658 for (tidno = 0, tid = &an->tid[tidno];
2659 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
2664 ath_txq_lock(sc, txq);
2667 list_del(&tid->list);
2672 list_del(&ac->list);
2673 tid->ac->sched = false;
2676 ath_tid_drain(sc, txq, tid);
2677 tid->active = false;
2679 ath_txq_unlock(sc, txq);