2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define TIME_SYMBOLS(t) ((t) >> 2)
33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
38 static u16 bits_per_symbol[][2] = {
40 { 26, 54 }, /* 0: BPSK */
41 { 52, 108 }, /* 1: QPSK 1/2 */
42 { 78, 162 }, /* 2: QPSK 3/4 */
43 { 104, 216 }, /* 3: 16-QAM 1/2 */
44 { 156, 324 }, /* 4: 16-QAM 3/4 */
45 { 208, 432 }, /* 5: 64-QAM 2/3 */
46 { 234, 486 }, /* 6: 64-QAM 3/4 */
47 { 260, 540 }, /* 7: 64-QAM 5/6 */
50 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
52 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
53 struct ath_atx_tid *tid, struct sk_buff *skb);
54 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
55 int tx_flags, struct ath_txq *txq);
56 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
57 struct ath_txq *txq, struct list_head *bf_q,
58 struct ath_tx_status *ts, int txok);
59 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
60 struct list_head *head, bool internal);
61 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
62 struct ath_tx_status *ts, int nframes, int nbad,
64 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
66 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
68 struct ath_atx_tid *tid,
78 /*********************/
79 /* Aggregation logic */
80 /*********************/
82 void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq)
83 __acquires(&txq->axq_lock)
85 spin_lock_bh(&txq->axq_lock);
88 void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq)
89 __releases(&txq->axq_lock)
91 spin_unlock_bh(&txq->axq_lock);
94 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
95 __releases(&txq->axq_lock)
97 struct sk_buff_head q;
100 __skb_queue_head_init(&q);
101 skb_queue_splice_init(&txq->complete_q, &q);
102 spin_unlock_bh(&txq->axq_lock);
104 while ((skb = __skb_dequeue(&q)))
105 ieee80211_tx_status(sc->hw, skb);
108 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
110 struct ath_atx_ac *ac = tid->ac;
119 list_add_tail(&tid->list, &ac->tid_q);
125 list_add_tail(&ac->list, &txq->axq_acq);
128 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
130 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
131 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
132 sizeof(tx_info->rate_driver_data));
133 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
136 static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
138 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
139 seqno << IEEE80211_SEQ_SEQ_SHIFT);
142 static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta,
145 ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates,
146 ARRAY_SIZE(bf->rates));
149 static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq,
154 q = skb_get_queue_mapping(skb);
155 if (txq == sc->tx.uapsdq)
156 txq = sc->tx.txq_map[q];
158 if (txq != sc->tx.txq_map[q])
161 if (WARN_ON(--txq->pending_frames < 0))
162 txq->pending_frames = 0;
165 txq->pending_frames < sc->tx.txq_max_pending[q]) {
166 ieee80211_wake_queue(sc->hw, q);
167 txq->stopped = false;
171 static struct ath_atx_tid *
172 ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb)
174 struct ieee80211_hdr *hdr;
177 hdr = (struct ieee80211_hdr *) skb->data;
178 if (ieee80211_is_data_qos(hdr->frame_control))
179 tidno = ieee80211_get_qos_ctl(hdr)[0];
181 tidno &= IEEE80211_QOS_CTL_TID_MASK;
182 return ATH_AN_2_TID(an, tidno);
185 static bool ath_tid_has_buffered(struct ath_atx_tid *tid)
187 return !skb_queue_empty(&tid->buf_q) || !skb_queue_empty(&tid->retry_q);
190 static struct sk_buff *ath_tid_dequeue(struct ath_atx_tid *tid)
194 skb = __skb_dequeue(&tid->retry_q);
196 skb = __skb_dequeue(&tid->buf_q);
201 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
203 struct ath_txq *txq = tid->ac->txq;
206 struct list_head bf_head;
207 struct ath_tx_status ts;
208 struct ath_frame_info *fi;
209 bool sendbar = false;
211 INIT_LIST_HEAD(&bf_head);
213 memset(&ts, 0, sizeof(ts));
215 while ((skb = ath_tid_dequeue(tid))) {
216 fi = get_frame_info(skb);
220 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
222 ath_txq_skb_done(sc, txq, skb);
223 ieee80211_free_txskb(sc->hw, skb);
228 if (fi->baw_tracked) {
229 list_add_tail(&bf->list, &bf_head);
230 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
231 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
234 ath_set_rates(tid->an->vif, tid->an->sta, bf);
235 ath_tx_send_normal(sc, txq, NULL, skb);
240 ath_txq_unlock(sc, txq);
241 ath_send_bar(tid, tid->seq_start);
242 ath_txq_lock(sc, txq);
246 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
251 index = ATH_BA_INDEX(tid->seq_start, seqno);
252 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
254 __clear_bit(cindex, tid->tx_buf);
256 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
257 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
258 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
259 if (tid->bar_index >= 0)
264 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
267 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
268 u16 seqno = bf->bf_state.seqno;
271 index = ATH_BA_INDEX(tid->seq_start, seqno);
272 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
273 __set_bit(cindex, tid->tx_buf);
276 if (index >= ((tid->baw_tail - tid->baw_head) &
277 (ATH_TID_MAX_BUFS - 1))) {
278 tid->baw_tail = cindex;
279 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
284 * TODO: For frame(s) that are in the retry state, we will reuse the
285 * sequence number(s) without setting the retry bit. The
286 * alternative is to give up on these and BAR the receiver's window
289 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
290 struct ath_atx_tid *tid)
295 struct list_head bf_head;
296 struct ath_tx_status ts;
297 struct ath_frame_info *fi;
299 memset(&ts, 0, sizeof(ts));
300 INIT_LIST_HEAD(&bf_head);
302 while ((skb = ath_tid_dequeue(tid))) {
303 fi = get_frame_info(skb);
307 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
311 list_add_tail(&bf->list, &bf_head);
313 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
314 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
317 tid->seq_next = tid->seq_start;
318 tid->baw_tail = tid->baw_head;
322 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
323 struct sk_buff *skb, int count)
325 struct ath_frame_info *fi = get_frame_info(skb);
326 struct ath_buf *bf = fi->bf;
327 struct ieee80211_hdr *hdr;
328 int prev = fi->retries;
330 TX_STAT_INC(txq->axq_qnum, a_retries);
331 fi->retries += count;
336 hdr = (struct ieee80211_hdr *)skb->data;
337 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
338 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
339 sizeof(*hdr), DMA_TO_DEVICE);
342 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
344 struct ath_buf *bf = NULL;
346 spin_lock_bh(&sc->tx.txbuflock);
348 if (unlikely(list_empty(&sc->tx.txbuf))) {
349 spin_unlock_bh(&sc->tx.txbuflock);
353 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
356 spin_unlock_bh(&sc->tx.txbuflock);
361 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
363 spin_lock_bh(&sc->tx.txbuflock);
364 list_add_tail(&bf->list, &sc->tx.txbuf);
365 spin_unlock_bh(&sc->tx.txbuflock);
368 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
372 tbf = ath_tx_get_buffer(sc);
376 ATH_TXBUF_RESET(tbf);
378 tbf->bf_mpdu = bf->bf_mpdu;
379 tbf->bf_buf_addr = bf->bf_buf_addr;
380 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
381 tbf->bf_state = bf->bf_state;
386 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
387 struct ath_tx_status *ts, int txok,
388 int *nframes, int *nbad)
390 struct ath_frame_info *fi;
392 u32 ba[WME_BA_BMP_SIZE >> 5];
399 isaggr = bf_isaggr(bf);
401 seq_st = ts->ts_seqnum;
402 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
406 fi = get_frame_info(bf->bf_mpdu);
407 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
410 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
418 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
419 struct ath_buf *bf, struct list_head *bf_q,
420 struct ath_tx_status *ts, int txok)
422 struct ath_node *an = NULL;
424 struct ieee80211_sta *sta;
425 struct ieee80211_hw *hw = sc->hw;
426 struct ieee80211_hdr *hdr;
427 struct ieee80211_tx_info *tx_info;
428 struct ath_atx_tid *tid = NULL;
429 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
430 struct list_head bf_head;
431 struct sk_buff_head bf_pending;
432 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
433 u32 ba[WME_BA_BMP_SIZE >> 5];
434 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
435 bool rc_update = true, isba;
436 struct ieee80211_tx_rate rates[4];
437 struct ath_frame_info *fi;
439 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
444 hdr = (struct ieee80211_hdr *)skb->data;
446 tx_info = IEEE80211_SKB_CB(skb);
448 memcpy(rates, bf->rates, sizeof(rates));
450 retries = ts->ts_longretry + 1;
451 for (i = 0; i < ts->ts_rateindex; i++)
452 retries += rates[i].count;
456 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
460 INIT_LIST_HEAD(&bf_head);
462 bf_next = bf->bf_next;
464 if (!bf->bf_stale || bf_next != NULL)
465 list_move_tail(&bf->list, &bf_head);
467 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 0);
474 an = (struct ath_node *)sta->drv_priv;
475 tid = ath_get_skb_tid(sc, an, skb);
476 seq_first = tid->seq_start;
477 isba = ts->ts_flags & ATH9K_TX_BA;
480 * The hardware occasionally sends a tx status for the wrong TID.
481 * In this case, the BA status cannot be considered valid and all
482 * subframes need to be retransmitted
484 * Only BlockAcks have a TID and therefore normal Acks cannot be
487 if (isba && tid->tidno != ts->tid)
490 isaggr = bf_isaggr(bf);
491 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
493 if (isaggr && txok) {
494 if (ts->ts_flags & ATH9K_TX_BA) {
495 seq_st = ts->ts_seqnum;
496 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
499 * AR5416 can become deaf/mute when BA
500 * issue happens. Chip needs to be reset.
501 * But AP code may have sychronization issues
502 * when perform internal reset in this routine.
503 * Only enable reset in STA mode for now.
505 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
510 __skb_queue_head_init(&bf_pending);
512 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
514 u16 seqno = bf->bf_state.seqno;
516 txfail = txpending = sendbar = 0;
517 bf_next = bf->bf_next;
520 tx_info = IEEE80211_SKB_CB(skb);
521 fi = get_frame_info(skb);
523 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) ||
526 * Outside of the current BlockAck window,
527 * maybe part of a previous session
530 } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
531 /* transmit completion, subframe is
532 * acked by block ack */
534 } else if (!isaggr && txok) {
535 /* transmit completion */
539 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
540 if (txok || !an->sleeping)
541 ath_tx_set_retry(sc, txq, bf->bf_mpdu,
548 bar_index = max_t(int, bar_index,
549 ATH_BA_INDEX(seq_first, seqno));
553 * Make sure the last desc is reclaimed if it
554 * not a holding desc.
556 INIT_LIST_HEAD(&bf_head);
557 if (bf_next != NULL || !bf_last->bf_stale)
558 list_move_tail(&bf->list, &bf_head);
562 * complete the acked-ones/xretried ones; update
565 ath_tx_update_baw(sc, tid, seqno);
567 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
568 memcpy(tx_info->control.rates, rates, sizeof(rates));
569 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
573 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
576 if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) {
577 tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP;
578 ieee80211_sta_eosp(sta);
580 /* retry the un-acked ones */
581 if (bf->bf_next == NULL && bf_last->bf_stale) {
584 tbf = ath_clone_txbuf(sc, bf_last);
586 * Update tx baw and complete the
587 * frame with failed status if we
591 ath_tx_update_baw(sc, tid, seqno);
593 ath_tx_complete_buf(sc, bf, txq,
595 bar_index = max_t(int, bar_index,
596 ATH_BA_INDEX(seq_first, seqno));
604 * Put this buffer to the temporary pending
605 * queue to retain ordering
607 __skb_queue_tail(&bf_pending, skb);
613 /* prepend un-acked frames to the beginning of the pending frame queue */
614 if (!skb_queue_empty(&bf_pending)) {
616 ieee80211_sta_set_buffered(sta, tid->tidno, true);
618 skb_queue_splice_tail(&bf_pending, &tid->retry_q);
620 ath_tx_queue_tid(txq, tid);
622 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
623 tid->ac->clear_ps_filter = true;
627 if (bar_index >= 0) {
628 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
630 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
631 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
633 ath_txq_unlock(sc, txq);
634 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
635 ath_txq_lock(sc, txq);
641 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
644 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
646 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
647 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
650 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
651 struct ath_tx_status *ts, struct ath_buf *bf,
652 struct list_head *bf_head)
654 struct ieee80211_tx_info *info;
657 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
658 flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
659 txq->axq_tx_inprogress = false;
662 if (bf_is_ampdu_not_probing(bf))
663 txq->axq_ampdu_depth--;
665 if (!bf_isampdu(bf)) {
667 info = IEEE80211_SKB_CB(bf->bf_mpdu);
668 memcpy(info->control.rates, bf->rates,
669 sizeof(info->control.rates));
670 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
672 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok);
674 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok);
677 ath_txq_schedule(sc, txq);
680 static bool ath_lookup_legacy(struct ath_buf *bf)
683 struct ieee80211_tx_info *tx_info;
684 struct ieee80211_tx_rate *rates;
688 tx_info = IEEE80211_SKB_CB(skb);
689 rates = tx_info->control.rates;
691 for (i = 0; i < 4; i++) {
692 if (!rates[i].count || rates[i].idx < 0)
695 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
702 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
703 struct ath_atx_tid *tid)
706 struct ieee80211_tx_info *tx_info;
707 struct ieee80211_tx_rate *rates;
708 u32 max_4ms_framelen, frmlen;
709 u16 aggr_limit, bt_aggr_limit, legacy = 0;
710 int q = tid->ac->txq->mac80211_qnum;
714 tx_info = IEEE80211_SKB_CB(skb);
718 * Find the lowest frame length among the rate series that will have a
719 * 4ms (or TXOP limited) transmit duration.
721 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
723 for (i = 0; i < 4; i++) {
729 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
734 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
739 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
742 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx];
743 max_4ms_framelen = min(max_4ms_framelen, frmlen);
747 * limit aggregate size by the minimum rate if rate selected is
748 * not a probe rate, if rate selected is a probe rate then
749 * avoid aggregation of this packet.
751 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
754 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX);
757 * Override the default aggregation limit for BTCOEX.
759 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen);
761 aggr_limit = bt_aggr_limit;
764 * h/w can accept aggregates up to 16 bit lengths (65535).
765 * The IE, however can hold up to 65536, which shows up here
766 * as zero. Ignore 65536 since we are constrained by hw.
768 if (tid->an->maxampdu)
769 aggr_limit = min(aggr_limit, tid->an->maxampdu);
775 * Returns the number of delimiters to be added to
776 * meet the minimum required mpdudensity.
778 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
779 struct ath_buf *bf, u16 frmlen,
782 #define FIRST_DESC_NDELIMS 60
783 u32 nsymbits, nsymbols;
786 int width, streams, half_gi, ndelim, mindelim;
787 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
789 /* Select standard number of delimiters based on frame length alone */
790 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
793 * If encryption enabled, hardware requires some more padding between
795 * TODO - this could be improved to be dependent on the rate.
796 * The hardware can keep up at lower rates, but not higher rates
798 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
799 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
800 ndelim += ATH_AGGR_ENCRYPTDELIM;
803 * Add delimiter when using RTS/CTS with aggregation
804 * and non enterprise AR9003 card
806 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
807 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
808 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
811 * Convert desired mpdu density from microeconds to bytes based
812 * on highest rate in rate series (i.e. first rate) to determine
813 * required minimum length for subframe. Take into account
814 * whether high rate is 20 or 40Mhz and half or full GI.
816 * If there is no mpdu density restriction, no further calculation
820 if (tid->an->mpdudensity == 0)
823 rix = bf->rates[0].idx;
824 flags = bf->rates[0].flags;
825 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
826 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
829 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
831 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
836 streams = HT_RC_2_STREAMS(rix);
837 nsymbits = bits_per_symbol[rix % 8][width] * streams;
838 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
840 if (frmlen < minlen) {
841 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
842 ndelim = max(mindelim, ndelim);
848 static struct ath_buf *
849 ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq,
850 struct ath_atx_tid *tid, struct sk_buff_head **q)
852 struct ieee80211_tx_info *tx_info;
853 struct ath_frame_info *fi;
860 if (skb_queue_empty(*q))
867 fi = get_frame_info(skb);
870 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
873 __skb_unlink(skb, *q);
874 ath_txq_skb_done(sc, txq, skb);
875 ieee80211_free_txskb(sc->hw, skb);
882 tx_info = IEEE80211_SKB_CB(skb);
883 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
884 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
885 bf->bf_state.bf_type = 0;
889 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
890 seqno = bf->bf_state.seqno;
892 /* do not step over block-ack window */
893 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno))
896 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
897 struct ath_tx_status ts = {};
898 struct list_head bf_head;
900 INIT_LIST_HEAD(&bf_head);
901 list_add(&bf->list, &bf_head);
902 __skb_unlink(skb, *q);
903 ath_tx_update_baw(sc, tid, seqno);
904 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
914 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
916 struct ath_atx_tid *tid,
917 struct list_head *bf_q,
920 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
921 struct ath_buf *bf, *bf_first = NULL, *bf_prev = NULL;
922 int nframes = 0, ndelim;
923 u16 aggr_limit = 0, al = 0, bpad = 0,
924 al_delta, h_baw = tid->baw_size / 2;
925 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
926 struct ieee80211_tx_info *tx_info;
927 struct ath_frame_info *fi;
929 struct sk_buff_head *tid_q;
932 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
934 status = ATH_AGGR_BAW_CLOSED;
939 fi = get_frame_info(skb);
943 ath_set_rates(tid->an->vif, tid->an->sta, bf);
944 aggr_limit = ath_lookup_rate(sc, bf, tid);
947 /* do not exceed aggregation limit */
948 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
950 if (aggr_limit < al + bpad + al_delta ||
951 ath_lookup_legacy(bf) || nframes >= h_baw) {
952 status = ATH_AGGR_LIMITED;
956 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
957 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)
961 /* add padding for previous frame to aggregation length */
962 al += bpad + al_delta;
965 * Get the delimiters needed to meet the MPDU
966 * density for this node.
968 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
970 bpad = PADBYTES(al_delta) + (ndelim << 2);
975 /* link buffers of this frame to the aggregate */
976 if (!fi->baw_tracked)
977 ath_tx_addto_baw(sc, tid, bf);
978 bf->bf_state.ndelim = ndelim;
980 __skb_unlink(skb, tid_q);
981 list_add_tail(&bf->list, bf_q);
983 bf_prev->bf_next = bf;
987 } while (ath_tid_has_buffered(tid));
997 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
998 * width - 0 for 20 MHz, 1 for 40 MHz
999 * half_gi - to use 4us v/s 3.6 us for symbol time
1001 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1002 int width, int half_gi, bool shortPreamble)
1004 u32 nbits, nsymbits, duration, nsymbols;
1007 /* find number of symbols: PLCP + data */
1008 streams = HT_RC_2_STREAMS(rix);
1009 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1010 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1011 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1014 duration = SYMBOL_TIME(nsymbols);
1016 duration = SYMBOL_TIME_HALFGI(nsymbols);
1018 /* addup duration for legacy/ht training and signal fields */
1019 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1024 static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi)
1026 int streams = HT_RC_2_STREAMS(mcs);
1030 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec);
1031 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams;
1032 bits -= OFDM_PLCP_BITS;
1034 bytes -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1041 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop)
1043 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi;
1046 /* 4ms is the default (and maximum) duration */
1047 if (!txop || txop > 4096)
1050 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20];
1051 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI];
1052 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40];
1053 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI];
1054 for (mcs = 0; mcs < 32; mcs++) {
1055 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false);
1056 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true);
1057 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false);
1058 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true);
1062 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
1063 struct ath_tx_info *info, int len, bool rts)
1065 struct ath_hw *ah = sc->sc_ah;
1066 struct sk_buff *skb;
1067 struct ieee80211_tx_info *tx_info;
1068 struct ieee80211_tx_rate *rates;
1069 const struct ieee80211_rate *rate;
1070 struct ieee80211_hdr *hdr;
1071 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1072 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1077 tx_info = IEEE80211_SKB_CB(skb);
1079 hdr = (struct ieee80211_hdr *)skb->data;
1081 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1082 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
1083 info->rtscts_rate = fi->rtscts_rate;
1085 for (i = 0; i < ARRAY_SIZE(bf->rates); i++) {
1086 bool is_40, is_sgi, is_sp;
1089 if (!rates[i].count || (rates[i].idx < 0))
1093 info->rates[i].Tries = rates[i].count;
1096 * Handle RTS threshold for unaggregated HT frames.
1098 if (bf_isampdu(bf) && !bf_isaggr(bf) &&
1099 (rates[i].flags & IEEE80211_TX_RC_MCS) &&
1100 unlikely(rts_thresh != (u32) -1)) {
1101 if (!rts_thresh || (len > rts_thresh))
1105 if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1106 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1107 info->flags |= ATH9K_TXDESC_RTSENA;
1108 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1109 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1110 info->flags |= ATH9K_TXDESC_CTSENA;
1113 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1114 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
1115 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1116 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1118 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1119 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1120 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1122 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1124 info->rates[i].Rate = rix | 0x80;
1125 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1126 ah->txchainmask, info->rates[i].Rate);
1127 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
1128 is_40, is_sgi, is_sp);
1129 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1130 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
1135 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
1136 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1137 !(rate->flags & IEEE80211_RATE_ERP_G))
1138 phy = WLAN_RC_PHY_CCK;
1140 phy = WLAN_RC_PHY_OFDM;
1142 info->rates[i].Rate = rate->hw_value;
1143 if (rate->hw_value_short) {
1144 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1145 info->rates[i].Rate |= rate->hw_value_short;
1150 if (bf->bf_state.bfs_paprd)
1151 info->rates[i].ChSel = ah->txchainmask;
1153 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1154 ah->txchainmask, info->rates[i].Rate);
1156 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1157 phy, rate->bitrate * 100, len, rix, is_sp);
1160 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1161 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1162 info->flags &= ~ATH9K_TXDESC_RTSENA;
1164 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1165 if (info->flags & ATH9K_TXDESC_RTSENA)
1166 info->flags &= ~ATH9K_TXDESC_CTSENA;
1169 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1171 struct ieee80211_hdr *hdr;
1172 enum ath9k_pkt_type htype;
1175 hdr = (struct ieee80211_hdr *)skb->data;
1176 fc = hdr->frame_control;
1178 if (ieee80211_is_beacon(fc))
1179 htype = ATH9K_PKT_TYPE_BEACON;
1180 else if (ieee80211_is_probe_resp(fc))
1181 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1182 else if (ieee80211_is_atim(fc))
1183 htype = ATH9K_PKT_TYPE_ATIM;
1184 else if (ieee80211_is_pspoll(fc))
1185 htype = ATH9K_PKT_TYPE_PSPOLL;
1187 htype = ATH9K_PKT_TYPE_NORMAL;
1192 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1193 struct ath_txq *txq, int len)
1195 struct ath_hw *ah = sc->sc_ah;
1196 struct ath_buf *bf_first = NULL;
1197 struct ath_tx_info info;
1198 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1201 memset(&info, 0, sizeof(info));
1202 info.is_first = true;
1203 info.is_last = true;
1204 info.txpower = MAX_RATE_POWER;
1205 info.qcu = txq->axq_qnum;
1208 struct sk_buff *skb = bf->bf_mpdu;
1209 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1210 struct ath_frame_info *fi = get_frame_info(skb);
1211 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1213 info.type = get_hw_packet_type(skb);
1215 info.link = bf->bf_next->bf_daddr;
1222 info.flags = ATH9K_TXDESC_INTREQ;
1223 if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) ||
1224 txq == sc->tx.uapsdq)
1225 info.flags |= ATH9K_TXDESC_CLRDMASK;
1227 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1228 info.flags |= ATH9K_TXDESC_NOACK;
1229 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1230 info.flags |= ATH9K_TXDESC_LDPC;
1232 if (bf->bf_state.bfs_paprd)
1233 info.flags |= (u32) bf->bf_state.bfs_paprd <<
1234 ATH9K_TXDESC_PAPRD_S;
1237 * mac80211 doesn't handle RTS threshold for HT because
1238 * the decision has to be taken based on AMPDU length
1239 * and aggregation is done entirely inside ath9k.
1240 * Set the RTS/CTS flag for the first subframe based
1243 if (aggr && (bf == bf_first) &&
1244 unlikely(rts_thresh != (u32) -1)) {
1246 * "len" is the size of the entire AMPDU.
1248 if (!rts_thresh || (len > rts_thresh))
1251 ath_buf_set_rate(sc, bf, &info, len, rts);
1254 info.buf_addr[0] = bf->bf_buf_addr;
1255 info.buf_len[0] = skb->len;
1256 info.pkt_len = fi->framelen;
1257 info.keyix = fi->keyix;
1258 info.keytype = fi->keytype;
1262 info.aggr = AGGR_BUF_FIRST;
1263 else if (bf == bf_first->bf_lastbf)
1264 info.aggr = AGGR_BUF_LAST;
1266 info.aggr = AGGR_BUF_MIDDLE;
1268 info.ndelim = bf->bf_state.ndelim;
1269 info.aggr_len = len;
1272 if (bf == bf_first->bf_lastbf)
1275 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1280 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1281 struct ath_atx_tid *tid)
1284 enum ATH_AGGR_STATUS status;
1285 struct ieee80211_tx_info *tx_info;
1286 struct list_head bf_q;
1290 if (!ath_tid_has_buffered(tid))
1293 INIT_LIST_HEAD(&bf_q);
1295 status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len);
1298 * no frames picked up to be aggregated;
1299 * block-ack window is not open.
1301 if (list_empty(&bf_q))
1304 bf = list_first_entry(&bf_q, struct ath_buf, list);
1305 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
1306 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1308 if (tid->ac->clear_ps_filter) {
1309 tid->ac->clear_ps_filter = false;
1310 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1312 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
1315 /* if only one frame, send as non-aggregate */
1316 if (bf == bf->bf_lastbf) {
1317 aggr_len = get_frame_info(bf->bf_mpdu)->framelen;
1318 bf->bf_state.bf_type = BUF_AMPDU;
1320 TX_STAT_INC(txq->axq_qnum, a_aggr);
1323 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1324 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1325 } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH &&
1326 status != ATH_AGGR_BAW_CLOSED);
1329 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1332 struct ath_atx_tid *txtid;
1333 struct ath_node *an;
1336 an = (struct ath_node *)sta->drv_priv;
1337 txtid = ATH_AN_2_TID(an, tid);
1339 /* update ampdu factor/density, they may have changed. This may happen
1340 * in HT IBSS when a beacon with HT-info is received after the station
1341 * has already been added.
1343 if (sta->ht_cap.ht_supported) {
1344 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
1345 sta->ht_cap.ampdu_factor);
1346 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
1347 an->mpdudensity = density;
1350 txtid->active = true;
1351 txtid->paused = true;
1352 *ssn = txtid->seq_start = txtid->seq_next;
1353 txtid->bar_index = -1;
1355 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1356 txtid->baw_head = txtid->baw_tail = 0;
1361 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1363 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1364 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1365 struct ath_txq *txq = txtid->ac->txq;
1367 ath_txq_lock(sc, txq);
1368 txtid->active = false;
1369 txtid->paused = false;
1370 ath_tx_flush_tid(sc, txtid);
1371 ath_txq_unlock_complete(sc, txq);
1374 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1375 struct ath_node *an)
1377 struct ath_atx_tid *tid;
1378 struct ath_atx_ac *ac;
1379 struct ath_txq *txq;
1383 for (tidno = 0, tid = &an->tid[tidno];
1384 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1392 ath_txq_lock(sc, txq);
1394 buffered = ath_tid_has_buffered(tid);
1397 list_del(&tid->list);
1401 list_del(&ac->list);
1404 ath_txq_unlock(sc, txq);
1406 ieee80211_sta_set_buffered(sta, tidno, buffered);
1410 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1412 struct ath_atx_tid *tid;
1413 struct ath_atx_ac *ac;
1414 struct ath_txq *txq;
1417 for (tidno = 0, tid = &an->tid[tidno];
1418 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1423 ath_txq_lock(sc, txq);
1424 ac->clear_ps_filter = true;
1426 if (!tid->paused && ath_tid_has_buffered(tid)) {
1427 ath_tx_queue_tid(txq, tid);
1428 ath_txq_schedule(sc, txq);
1431 ath_txq_unlock_complete(sc, txq);
1435 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta,
1438 struct ath_atx_tid *tid;
1439 struct ath_node *an;
1440 struct ath_txq *txq;
1442 an = (struct ath_node *)sta->drv_priv;
1443 tid = ATH_AN_2_TID(an, tidno);
1446 ath_txq_lock(sc, txq);
1448 tid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
1449 tid->paused = false;
1451 if (ath_tid_has_buffered(tid)) {
1452 ath_tx_queue_tid(txq, tid);
1453 ath_txq_schedule(sc, txq);
1456 ath_txq_unlock_complete(sc, txq);
1459 void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
1460 struct ieee80211_sta *sta,
1461 u16 tids, int nframes,
1462 enum ieee80211_frame_release_type reason,
1465 struct ath_softc *sc = hw->priv;
1466 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1467 struct ath_txq *txq = sc->tx.uapsdq;
1468 struct ieee80211_tx_info *info;
1469 struct list_head bf_q;
1470 struct ath_buf *bf_tail = NULL, *bf;
1471 struct sk_buff_head *tid_q;
1475 INIT_LIST_HEAD(&bf_q);
1476 for (i = 0; tids && nframes; i++, tids >>= 1) {
1477 struct ath_atx_tid *tid;
1482 tid = ATH_AN_2_TID(an, i);
1486 ath_txq_lock(sc, tid->ac->txq);
1487 while (nframes > 0) {
1488 bf = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq, tid, &tid_q);
1492 __skb_unlink(bf->bf_mpdu, tid_q);
1493 list_add_tail(&bf->list, &bf_q);
1494 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1495 ath_tx_addto_baw(sc, tid, bf);
1496 bf->bf_state.bf_type &= ~BUF_AGGR;
1498 bf_tail->bf_next = bf;
1503 TX_STAT_INC(txq->axq_qnum, a_queued_hw);
1505 if (!ath_tid_has_buffered(tid))
1506 ieee80211_sta_set_buffered(an->sta, i, false);
1508 ath_txq_unlock_complete(sc, tid->ac->txq);
1511 if (list_empty(&bf_q))
1514 info = IEEE80211_SKB_CB(bf_tail->bf_mpdu);
1515 info->flags |= IEEE80211_TX_STATUS_EOSP;
1517 bf = list_first_entry(&bf_q, struct ath_buf, list);
1518 ath_txq_lock(sc, txq);
1519 ath_tx_fill_desc(sc, bf, txq, 0);
1520 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1521 ath_txq_unlock(sc, txq);
1524 /********************/
1525 /* Queue Management */
1526 /********************/
1528 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1530 struct ath_hw *ah = sc->sc_ah;
1531 struct ath9k_tx_queue_info qi;
1532 static const int subtype_txq_to_hwq[] = {
1533 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE,
1534 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK,
1535 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI,
1536 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO,
1540 memset(&qi, 0, sizeof(qi));
1541 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1542 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1543 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1544 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1545 qi.tqi_physCompBuf = 0;
1548 * Enable interrupts only for EOL and DESC conditions.
1549 * We mark tx descriptors to receive a DESC interrupt
1550 * when a tx queue gets deep; otherwise waiting for the
1551 * EOL to reap descriptors. Note that this is done to
1552 * reduce interrupt load and this only defers reaping
1553 * descriptors, never transmitting frames. Aside from
1554 * reducing interrupts this also permits more concurrency.
1555 * The only potential downside is if the tx queue backs
1556 * up in which case the top half of the kernel may backup
1557 * due to a lack of tx descriptors.
1559 * The UAPSD queue is an exception, since we take a desc-
1560 * based intr on the EOSP frames.
1562 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1563 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
1565 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1566 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1568 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1569 TXQ_FLAG_TXDESCINT_ENABLE;
1571 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1572 if (axq_qnum == -1) {
1574 * NB: don't print a message, this happens
1575 * normally on parts with too few tx queues
1579 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1580 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1582 txq->axq_qnum = axq_qnum;
1583 txq->mac80211_qnum = -1;
1584 txq->axq_link = NULL;
1585 __skb_queue_head_init(&txq->complete_q);
1586 INIT_LIST_HEAD(&txq->axq_q);
1587 INIT_LIST_HEAD(&txq->axq_acq);
1588 spin_lock_init(&txq->axq_lock);
1590 txq->axq_ampdu_depth = 0;
1591 txq->axq_tx_inprogress = false;
1592 sc->tx.txqsetup |= 1<<axq_qnum;
1594 txq->txq_headidx = txq->txq_tailidx = 0;
1595 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1596 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1598 return &sc->tx.txq[axq_qnum];
1601 int ath_txq_update(struct ath_softc *sc, int qnum,
1602 struct ath9k_tx_queue_info *qinfo)
1604 struct ath_hw *ah = sc->sc_ah;
1606 struct ath9k_tx_queue_info qi;
1608 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1610 ath9k_hw_get_txq_props(ah, qnum, &qi);
1611 qi.tqi_aifs = qinfo->tqi_aifs;
1612 qi.tqi_cwmin = qinfo->tqi_cwmin;
1613 qi.tqi_cwmax = qinfo->tqi_cwmax;
1614 qi.tqi_burstTime = qinfo->tqi_burstTime;
1615 qi.tqi_readyTime = qinfo->tqi_readyTime;
1617 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1618 ath_err(ath9k_hw_common(sc->sc_ah),
1619 "Unable to update hardware queue %u!\n", qnum);
1622 ath9k_hw_resettxqueue(ah, qnum);
1628 int ath_cabq_update(struct ath_softc *sc)
1630 struct ath9k_tx_queue_info qi;
1631 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
1632 int qnum = sc->beacon.cabq->axq_qnum;
1634 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1636 * Ensure the readytime % is within the bounds.
1638 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1639 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1640 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1641 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1643 qi.tqi_readyTime = (cur_conf->beacon_interval *
1644 sc->config.cabqReadytime) / 100;
1645 ath_txq_update(sc, qnum, &qi);
1650 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1651 struct list_head *list)
1653 struct ath_buf *bf, *lastbf;
1654 struct list_head bf_head;
1655 struct ath_tx_status ts;
1657 memset(&ts, 0, sizeof(ts));
1658 ts.ts_status = ATH9K_TX_FLUSH;
1659 INIT_LIST_HEAD(&bf_head);
1661 while (!list_empty(list)) {
1662 bf = list_first_entry(list, struct ath_buf, list);
1665 list_del(&bf->list);
1667 ath_tx_return_buffer(sc, bf);
1671 lastbf = bf->bf_lastbf;
1672 list_cut_position(&bf_head, list, &lastbf->list);
1673 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
1678 * Drain a given TX queue (could be Beacon or Data)
1680 * This assumes output has been stopped and
1681 * we do not need to block ath_tx_tasklet.
1683 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq)
1685 ath_txq_lock(sc, txq);
1687 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1688 int idx = txq->txq_tailidx;
1690 while (!list_empty(&txq->txq_fifo[idx])) {
1691 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]);
1693 INCR(idx, ATH_TXFIFO_DEPTH);
1695 txq->txq_tailidx = idx;
1698 txq->axq_link = NULL;
1699 txq->axq_tx_inprogress = false;
1700 ath_drain_txq_list(sc, txq, &txq->axq_q);
1702 ath_txq_unlock_complete(sc, txq);
1705 bool ath_drain_all_txq(struct ath_softc *sc)
1707 struct ath_hw *ah = sc->sc_ah;
1708 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1709 struct ath_txq *txq;
1713 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
1716 ath9k_hw_abort_tx_dma(ah);
1718 /* Check if any queue remains active */
1719 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1720 if (!ATH_TXQ_SETUP(sc, i))
1723 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1728 ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1730 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1731 if (!ATH_TXQ_SETUP(sc, i))
1735 * The caller will resume queues with ieee80211_wake_queues.
1736 * Mark the queue as not stopped to prevent ath_tx_complete
1737 * from waking the queue too early.
1739 txq = &sc->tx.txq[i];
1740 txq->stopped = false;
1741 ath_draintxq(sc, txq);
1747 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1749 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1750 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1753 /* For each axq_acq entry, for each tid, try to schedule packets
1754 * for transmit until ampdu_depth has reached min Q depth.
1756 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1758 struct ath_atx_ac *ac, *ac_tmp, *last_ac;
1759 struct ath_atx_tid *tid, *last_tid;
1761 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags) ||
1762 list_empty(&txq->axq_acq) ||
1763 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1768 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1769 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
1771 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1772 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1773 list_del(&ac->list);
1776 while (!list_empty(&ac->tid_q)) {
1777 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1779 list_del(&tid->list);
1785 ath_tx_sched_aggr(sc, txq, tid);
1788 * add tid to round-robin queue if more frames
1789 * are pending for the tid
1791 if (ath_tid_has_buffered(tid))
1792 ath_tx_queue_tid(txq, tid);
1794 if (tid == last_tid ||
1795 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1799 if (!list_empty(&ac->tid_q) && !ac->sched) {
1801 list_add_tail(&ac->list, &txq->axq_acq);
1804 if (ac == last_ac ||
1805 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1817 * Insert a chain of ath_buf (descriptors) on a txq and
1818 * assume the descriptors are already chained together by caller.
1820 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1821 struct list_head *head, bool internal)
1823 struct ath_hw *ah = sc->sc_ah;
1824 struct ath_common *common = ath9k_hw_common(ah);
1825 struct ath_buf *bf, *bf_last;
1826 bool puttxbuf = false;
1830 * Insert the frame on the outbound list and
1831 * pass it on to the hardware.
1834 if (list_empty(head))
1837 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1838 bf = list_first_entry(head, struct ath_buf, list);
1839 bf_last = list_entry(head->prev, struct ath_buf, list);
1841 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n",
1842 txq->axq_qnum, txq->axq_depth);
1844 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1845 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
1846 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1849 list_splice_tail_init(head, &txq->axq_q);
1851 if (txq->axq_link) {
1852 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
1853 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n",
1854 txq->axq_qnum, txq->axq_link,
1855 ito64(bf->bf_daddr), bf->bf_desc);
1859 txq->axq_link = bf_last->bf_desc;
1863 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1864 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1865 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n",
1866 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1870 TX_STAT_INC(txq->axq_qnum, txstart);
1871 ath9k_hw_txstart(ah, txq->axq_qnum);
1877 if (bf_is_ampdu_not_probing(bf))
1878 txq->axq_ampdu_depth++;
1880 bf = bf->bf_lastbf->bf_next;
1885 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_txq *txq,
1886 struct ath_atx_tid *tid, struct sk_buff *skb,
1887 struct ath_tx_control *txctl)
1889 struct ath_frame_info *fi = get_frame_info(skb);
1890 struct list_head bf_head;
1894 * Do not queue to h/w when any of the following conditions is true:
1895 * - there are pending frames in software queue
1896 * - the TID is currently paused for ADDBA/BAR request
1897 * - seqno is not within block-ack window
1898 * - h/w queue depth exceeds low water mark
1900 if ((ath_tid_has_buffered(tid) || tid->paused ||
1901 !BAW_WITHIN(tid->seq_start, tid->baw_size, tid->seq_next) ||
1902 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) &&
1903 txq != sc->tx.uapsdq) {
1905 * Add this frame to software queue for scheduling later
1908 TX_STAT_INC(txq->axq_qnum, a_queued_sw);
1909 __skb_queue_tail(&tid->buf_q, skb);
1910 if (!txctl->an || !txctl->an->sleeping)
1911 ath_tx_queue_tid(txq, tid);
1915 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
1917 ath_txq_skb_done(sc, txq, skb);
1918 ieee80211_free_txskb(sc->hw, skb);
1922 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1923 bf->bf_state.bf_type = BUF_AMPDU;
1924 INIT_LIST_HEAD(&bf_head);
1925 list_add(&bf->list, &bf_head);
1927 /* Add sub-frame to BAW */
1928 ath_tx_addto_baw(sc, tid, bf);
1930 /* Queue to h/w without aggregation */
1931 TX_STAT_INC(txq->axq_qnum, a_queued_hw);
1933 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
1934 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
1937 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1938 struct ath_atx_tid *tid, struct sk_buff *skb)
1940 struct ath_frame_info *fi = get_frame_info(skb);
1941 struct list_head bf_head;
1946 INIT_LIST_HEAD(&bf_head);
1947 list_add_tail(&bf->list, &bf_head);
1948 bf->bf_state.bf_type = 0;
1952 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
1953 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
1954 TX_STAT_INC(txq->axq_qnum, queued);
1957 static void setup_frame_info(struct ieee80211_hw *hw,
1958 struct ieee80211_sta *sta,
1959 struct sk_buff *skb,
1962 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1963 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1964 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1965 const struct ieee80211_rate *rate;
1966 struct ath_frame_info *fi = get_frame_info(skb);
1967 struct ath_node *an = NULL;
1968 enum ath9k_key_type keytype;
1969 bool short_preamble = false;
1972 * We check if Short Preamble is needed for the CTS rate by
1973 * checking the BSS's global flag.
1974 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1976 if (tx_info->control.vif &&
1977 tx_info->control.vif->bss_conf.use_short_preamble)
1978 short_preamble = true;
1980 rate = ieee80211_get_rts_cts_rate(hw, tx_info);
1981 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
1984 an = (struct ath_node *) sta->drv_priv;
1986 memset(fi, 0, sizeof(*fi));
1988 fi->keyix = hw_key->hw_key_idx;
1989 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
1990 fi->keyix = an->ps_key;
1992 fi->keyix = ATH9K_TXKEYIX_INVALID;
1993 fi->keytype = keytype;
1994 fi->framelen = framelen;
1995 fi->rtscts_rate = rate->hw_value;
1997 fi->rtscts_rate |= rate->hw_value_short;
2000 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
2002 struct ath_hw *ah = sc->sc_ah;
2003 struct ath9k_channel *curchan = ah->curchan;
2005 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) &&
2006 (curchan->channelFlags & CHANNEL_5GHZ) &&
2007 (chainmask == 0x7) && (rate < 0x90))
2009 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
2017 * Assign a descriptor (and sequence number if necessary,
2018 * and map buffer for DMA. Frees skb on error
2020 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
2021 struct ath_txq *txq,
2022 struct ath_atx_tid *tid,
2023 struct sk_buff *skb)
2025 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2026 struct ath_frame_info *fi = get_frame_info(skb);
2027 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2032 bf = ath_tx_get_buffer(sc);
2034 ath_dbg(common, XMIT, "TX buffers are full\n");
2038 ATH_TXBUF_RESET(bf);
2041 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
2042 seqno = tid->seq_next;
2043 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
2046 hdr->seq_ctrl |= cpu_to_le16(fragno);
2048 if (!ieee80211_has_morefrags(hdr->frame_control))
2049 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
2051 bf->bf_state.seqno = seqno;
2056 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
2057 skb->len, DMA_TO_DEVICE);
2058 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
2060 bf->bf_buf_addr = 0;
2061 ath_err(ath9k_hw_common(sc->sc_ah),
2062 "dma_mapping_error() on TX\n");
2063 ath_tx_return_buffer(sc, bf);
2072 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
2073 struct ath_tx_control *txctl)
2075 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2076 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2077 struct ieee80211_sta *sta = txctl->sta;
2078 struct ieee80211_vif *vif = info->control.vif;
2079 struct ath_softc *sc = hw->priv;
2080 int frmlen = skb->len + FCS_LEN;
2081 int padpos, padsize;
2083 /* NOTE: sta can be NULL according to net/mac80211.h */
2085 txctl->an = (struct ath_node *)sta->drv_priv;
2087 if (info->control.hw_key)
2088 frmlen += info->control.hw_key->icv_len;
2091 * As a temporary workaround, assign seq# here; this will likely need
2092 * to be cleaned up to work better with Beacon transmission and virtual
2095 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2096 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2097 sc->tx.seq_no += 0x10;
2098 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2099 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2102 if ((vif && vif->type != NL80211_IFTYPE_AP &&
2103 vif->type != NL80211_IFTYPE_AP_VLAN) ||
2104 !ieee80211_is_data(hdr->frame_control))
2105 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
2107 /* Add the padding after the header if this is not already done */
2108 padpos = ieee80211_hdrlen(hdr->frame_control);
2109 padsize = padpos & 3;
2110 if (padsize && skb->len > padpos) {
2111 if (skb_headroom(skb) < padsize)
2114 skb_push(skb, padsize);
2115 memmove(skb->data, skb->data + padsize, padpos);
2118 setup_frame_info(hw, sta, skb, frmlen);
2123 /* Upon failure caller should free skb */
2124 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
2125 struct ath_tx_control *txctl)
2127 struct ieee80211_hdr *hdr;
2128 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2129 struct ieee80211_sta *sta = txctl->sta;
2130 struct ieee80211_vif *vif = info->control.vif;
2131 struct ath_softc *sc = hw->priv;
2132 struct ath_txq *txq = txctl->txq;
2133 struct ath_atx_tid *tid = NULL;
2138 ret = ath_tx_prepare(hw, skb, txctl);
2142 hdr = (struct ieee80211_hdr *) skb->data;
2144 * At this point, the vif, hw_key and sta pointers in the tx control
2145 * info are no longer valid (overwritten by the ath_frame_info data.
2148 q = skb_get_queue_mapping(skb);
2150 ath_txq_lock(sc, txq);
2151 if (txq == sc->tx.txq_map[q] &&
2152 ++txq->pending_frames > sc->tx.txq_max_pending[q] &&
2154 ieee80211_stop_queue(sc->hw, q);
2155 txq->stopped = true;
2158 if (info->flags & IEEE80211_TX_CTL_PS_RESPONSE) {
2159 ath_txq_unlock(sc, txq);
2160 txq = sc->tx.uapsdq;
2161 ath_txq_lock(sc, txq);
2164 if (txctl->an && ieee80211_is_data_qos(hdr->frame_control)) {
2165 tid = ath_get_skb_tid(sc, txctl->an, skb);
2167 WARN_ON(tid->ac->txq != txctl->txq);
2170 if ((info->flags & IEEE80211_TX_CTL_AMPDU) && tid) {
2172 * Try aggregation if it's a unicast data frame
2173 * and the destination is HT capable.
2175 ath_tx_send_ampdu(sc, txq, tid, skb, txctl);
2179 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
2181 ath_txq_skb_done(sc, txq, skb);
2183 dev_kfree_skb_any(skb);
2185 ieee80211_free_txskb(sc->hw, skb);
2189 bf->bf_state.bfs_paprd = txctl->paprd;
2192 bf->bf_state.bfs_paprd_timestamp = jiffies;
2194 ath_set_rates(vif, sta, bf);
2195 ath_tx_send_normal(sc, txq, tid, skb);
2198 ath_txq_unlock(sc, txq);
2203 void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2204 struct sk_buff *skb)
2206 struct ath_softc *sc = hw->priv;
2207 struct ath_tx_control txctl = {
2208 .txq = sc->beacon.cabq
2210 struct ath_tx_info info = {};
2211 struct ieee80211_hdr *hdr;
2212 struct ath_buf *bf_tail = NULL;
2219 sc->cur_beacon_conf.beacon_interval * 1000 *
2220 sc->cur_beacon_conf.dtim_period / ATH_BCBUF;
2223 struct ath_frame_info *fi = get_frame_info(skb);
2225 if (ath_tx_prepare(hw, skb, &txctl))
2228 bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb);
2233 ath_set_rates(vif, NULL, bf);
2234 ath_buf_set_rate(sc, bf, &info, fi->framelen, false);
2235 duration += info.rates[0].PktDuration;
2237 bf_tail->bf_next = bf;
2239 list_add_tail(&bf->list, &bf_q);
2243 if (duration > max_duration)
2246 skb = ieee80211_get_buffered_bc(hw, vif);
2250 ieee80211_free_txskb(hw, skb);
2252 if (list_empty(&bf_q))
2255 bf = list_first_entry(&bf_q, struct ath_buf, list);
2256 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
2258 if (hdr->frame_control & IEEE80211_FCTL_MOREDATA) {
2259 hdr->frame_control &= ~IEEE80211_FCTL_MOREDATA;
2260 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
2261 sizeof(*hdr), DMA_TO_DEVICE);
2264 ath_txq_lock(sc, txctl.txq);
2265 ath_tx_fill_desc(sc, bf, txctl.txq, 0);
2266 ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false);
2267 TX_STAT_INC(txctl.txq->axq_qnum, queued);
2268 ath_txq_unlock(sc, txctl.txq);
2275 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
2276 int tx_flags, struct ath_txq *txq)
2278 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2279 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2280 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
2281 int padpos, padsize;
2282 unsigned long flags;
2284 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
2286 if (sc->sc_ah->caldata)
2287 sc->sc_ah->caldata->paprd_packet_sent = true;
2289 if (!(tx_flags & ATH_TX_ERROR))
2290 /* Frame was ACKed */
2291 tx_info->flags |= IEEE80211_TX_STAT_ACK;
2293 padpos = ieee80211_hdrlen(hdr->frame_control);
2294 padsize = padpos & 3;
2295 if (padsize && skb->len>padpos+padsize) {
2297 * Remove MAC header padding before giving the frame back to
2300 memmove(skb->data + padsize, skb->data, padpos);
2301 skb_pull(skb, padsize);
2304 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2305 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
2306 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
2308 "Going back to sleep after having received TX status (0x%lx)\n",
2309 sc->ps_flags & (PS_WAIT_FOR_BEACON |
2311 PS_WAIT_FOR_PSPOLL_DATA |
2312 PS_WAIT_FOR_TX_ACK));
2314 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2316 __skb_queue_tail(&txq->complete_q, skb);
2317 ath_txq_skb_done(sc, txq, skb);
2320 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
2321 struct ath_txq *txq, struct list_head *bf_q,
2322 struct ath_tx_status *ts, int txok)
2324 struct sk_buff *skb = bf->bf_mpdu;
2325 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2326 unsigned long flags;
2330 tx_flags |= ATH_TX_ERROR;
2332 if (ts->ts_status & ATH9K_TXERR_FILT)
2333 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2335 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2336 bf->bf_buf_addr = 0;
2338 if (bf->bf_state.bfs_paprd) {
2339 if (time_after(jiffies,
2340 bf->bf_state.bfs_paprd_timestamp +
2341 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2342 dev_kfree_skb_any(skb);
2344 complete(&sc->paprd_complete);
2346 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2347 ath_tx_complete(sc, skb, tx_flags, txq);
2349 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2350 * accidentally reference it later.
2355 * Return the list of ath_buf of this mpdu to free queue
2357 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2358 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2359 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2362 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2363 struct ath_tx_status *ts, int nframes, int nbad,
2366 struct sk_buff *skb = bf->bf_mpdu;
2367 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2368 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2369 struct ieee80211_hw *hw = sc->hw;
2370 struct ath_hw *ah = sc->sc_ah;
2374 tx_info->status.ack_signal = ts->ts_rssi;
2376 tx_rateindex = ts->ts_rateindex;
2377 WARN_ON(tx_rateindex >= hw->max_rates);
2379 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2380 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2382 BUG_ON(nbad > nframes);
2384 tx_info->status.ampdu_len = nframes;
2385 tx_info->status.ampdu_ack_len = nframes - nbad;
2387 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2388 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2390 * If an underrun error is seen assume it as an excessive
2391 * retry only if max frame trigger level has been reached
2392 * (2 KB for single stream, and 4 KB for dual stream).
2393 * Adjust the long retry as if the frame was tried
2394 * hw->max_rate_tries times to affect how rate control updates
2395 * PER for the failed rate.
2396 * In case of congestion on the bus penalizing this type of
2397 * underruns should help hardware actually transmit new frames
2398 * successfully by eventually preferring slower rates.
2399 * This itself should also alleviate congestion on the bus.
2401 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2402 ATH9K_TX_DELIM_UNDERRUN)) &&
2403 ieee80211_is_data(hdr->frame_control) &&
2404 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2405 tx_info->status.rates[tx_rateindex].count =
2409 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2410 tx_info->status.rates[i].count = 0;
2411 tx_info->status.rates[i].idx = -1;
2414 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2417 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2419 struct ath_hw *ah = sc->sc_ah;
2420 struct ath_common *common = ath9k_hw_common(ah);
2421 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2422 struct list_head bf_head;
2423 struct ath_desc *ds;
2424 struct ath_tx_status ts;
2427 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n",
2428 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2431 ath_txq_lock(sc, txq);
2433 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
2436 if (list_empty(&txq->axq_q)) {
2437 txq->axq_link = NULL;
2438 ath_txq_schedule(sc, txq);
2441 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2444 * There is a race condition that a BH gets scheduled
2445 * after sw writes TxE and before hw re-load the last
2446 * descriptor to get the newly chained one.
2447 * Software must keep the last DONE descriptor as a
2448 * holding descriptor - software does so by marking
2449 * it with the STALE flag.
2454 if (list_is_last(&bf_held->list, &txq->axq_q))
2457 bf = list_entry(bf_held->list.next, struct ath_buf,
2461 lastbf = bf->bf_lastbf;
2462 ds = lastbf->bf_desc;
2464 memset(&ts, 0, sizeof(ts));
2465 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2466 if (status == -EINPROGRESS)
2469 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2472 * Remove ath_buf's of the same transmit unit from txq,
2473 * however leave the last descriptor back as the holding
2474 * descriptor for hw.
2476 lastbf->bf_stale = true;
2477 INIT_LIST_HEAD(&bf_head);
2478 if (!list_is_singular(&lastbf->list))
2479 list_cut_position(&bf_head,
2480 &txq->axq_q, lastbf->list.prev);
2483 list_del(&bf_held->list);
2484 ath_tx_return_buffer(sc, bf_held);
2487 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2489 ath_txq_unlock_complete(sc, txq);
2492 void ath_tx_tasklet(struct ath_softc *sc)
2494 struct ath_hw *ah = sc->sc_ah;
2495 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;
2498 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2499 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2500 ath_tx_processq(sc, &sc->tx.txq[i]);
2504 void ath_tx_edma_tasklet(struct ath_softc *sc)
2506 struct ath_tx_status ts;
2507 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2508 struct ath_hw *ah = sc->sc_ah;
2509 struct ath_txq *txq;
2510 struct ath_buf *bf, *lastbf;
2511 struct list_head bf_head;
2512 struct list_head *fifo_list;
2516 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
2519 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2520 if (status == -EINPROGRESS)
2522 if (status == -EIO) {
2523 ath_dbg(common, XMIT, "Error processing tx status\n");
2527 /* Process beacon completions separately */
2528 if (ts.qid == sc->beacon.beaconq) {
2529 sc->beacon.tx_processed = true;
2530 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2534 txq = &sc->tx.txq[ts.qid];
2536 ath_txq_lock(sc, txq);
2538 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2540 fifo_list = &txq->txq_fifo[txq->txq_tailidx];
2541 if (list_empty(fifo_list)) {
2542 ath_txq_unlock(sc, txq);
2546 bf = list_first_entry(fifo_list, struct ath_buf, list);
2548 list_del(&bf->list);
2549 ath_tx_return_buffer(sc, bf);
2550 bf = list_first_entry(fifo_list, struct ath_buf, list);
2553 lastbf = bf->bf_lastbf;
2555 INIT_LIST_HEAD(&bf_head);
2556 if (list_is_last(&lastbf->list, fifo_list)) {
2557 list_splice_tail_init(fifo_list, &bf_head);
2558 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2560 if (!list_empty(&txq->axq_q)) {
2561 struct list_head bf_q;
2563 INIT_LIST_HEAD(&bf_q);
2564 txq->axq_link = NULL;
2565 list_splice_tail_init(&txq->axq_q, &bf_q);
2566 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2569 lastbf->bf_stale = true;
2571 list_cut_position(&bf_head, fifo_list,
2575 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2576 ath_txq_unlock_complete(sc, txq);
2584 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2586 struct ath_descdma *dd = &sc->txsdma;
2587 u8 txs_len = sc->sc_ah->caps.txs_len;
2589 dd->dd_desc_len = size * txs_len;
2590 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
2591 &dd->dd_desc_paddr, GFP_KERNEL);
2598 static int ath_tx_edma_init(struct ath_softc *sc)
2602 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2604 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2605 sc->txsdma.dd_desc_paddr,
2606 ATH_TXSTATUS_RING_SIZE);
2611 int ath_tx_init(struct ath_softc *sc, int nbufs)
2613 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2616 spin_lock_init(&sc->tx.txbuflock);
2618 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2622 "Failed to allocate tx descriptors: %d\n", error);
2626 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2627 "beacon", ATH_BCBUF, 1, 1);
2630 "Failed to allocate beacon descriptors: %d\n", error);
2634 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2636 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2637 error = ath_tx_edma_init(sc);
2642 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2644 struct ath_atx_tid *tid;
2645 struct ath_atx_ac *ac;
2648 for (tidno = 0, tid = &an->tid[tidno];
2649 tidno < IEEE80211_NUM_TIDS;
2653 tid->seq_start = tid->seq_next = 0;
2654 tid->baw_size = WME_MAX_BA;
2655 tid->baw_head = tid->baw_tail = 0;
2657 tid->paused = false;
2658 tid->active = false;
2659 __skb_queue_head_init(&tid->buf_q);
2660 __skb_queue_head_init(&tid->retry_q);
2661 acno = TID_TO_WME_AC(tidno);
2662 tid->ac = &an->ac[acno];
2665 for (acno = 0, ac = &an->ac[acno];
2666 acno < IEEE80211_NUM_ACS; acno++, ac++) {
2668 ac->clear_ps_filter = true;
2669 ac->txq = sc->tx.txq_map[acno];
2670 INIT_LIST_HEAD(&ac->tid_q);
2674 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2676 struct ath_atx_ac *ac;
2677 struct ath_atx_tid *tid;
2678 struct ath_txq *txq;
2681 for (tidno = 0, tid = &an->tid[tidno];
2682 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
2687 ath_txq_lock(sc, txq);
2690 list_del(&tid->list);
2695 list_del(&ac->list);
2696 tid->ac->sched = false;
2699 ath_tid_drain(sc, txq, tid);
2700 tid->active = false;
2702 ath_txq_unlock(sc, txq);