2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define TIME_SYMBOLS(t) ((t) >> 2)
33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
38 static u16 bits_per_symbol[][2] = {
40 { 26, 54 }, /* 0: BPSK */
41 { 52, 108 }, /* 1: QPSK 1/2 */
42 { 78, 162 }, /* 2: QPSK 3/4 */
43 { 104, 216 }, /* 3: 16-QAM 1/2 */
44 { 156, 324 }, /* 4: 16-QAM 3/4 */
45 { 208, 432 }, /* 5: 64-QAM 2/3 */
46 { 234, 486 }, /* 6: 64-QAM 3/4 */
47 { 260, 540 }, /* 7: 64-QAM 5/6 */
50 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
52 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
53 struct ath_atx_tid *tid, struct sk_buff *skb);
54 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
55 int tx_flags, struct ath_txq *txq);
56 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
57 struct ath_txq *txq, struct list_head *bf_q,
58 struct ath_tx_status *ts, int txok);
59 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
60 struct list_head *head, bool internal);
61 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
62 struct ath_tx_status *ts, int nframes, int nbad,
64 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
66 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
68 struct ath_atx_tid *tid,
78 /*********************/
79 /* Aggregation logic */
80 /*********************/
82 void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq)
83 __acquires(&txq->axq_lock)
85 spin_lock_bh(&txq->axq_lock);
88 void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq)
89 __releases(&txq->axq_lock)
91 spin_unlock_bh(&txq->axq_lock);
94 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
95 __releases(&txq->axq_lock)
97 struct sk_buff_head q;
100 __skb_queue_head_init(&q);
101 skb_queue_splice_init(&txq->complete_q, &q);
102 spin_unlock_bh(&txq->axq_lock);
104 while ((skb = __skb_dequeue(&q)))
105 ieee80211_tx_status(sc->hw, skb);
108 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
110 struct ath_atx_ac *ac = tid->ac;
119 list_add_tail(&tid->list, &ac->tid_q);
125 list_add_tail(&ac->list, &txq->axq_acq);
128 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
130 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
131 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
132 sizeof(tx_info->rate_driver_data));
133 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
136 static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
138 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
139 seqno << IEEE80211_SEQ_SEQ_SHIFT);
142 static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta,
145 ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates,
146 ARRAY_SIZE(bf->rates));
149 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
151 struct ath_txq *txq = tid->ac->txq;
154 struct list_head bf_head;
155 struct ath_tx_status ts;
156 struct ath_frame_info *fi;
157 bool sendbar = false;
159 INIT_LIST_HEAD(&bf_head);
161 memset(&ts, 0, sizeof(ts));
163 while ((skb = __skb_dequeue(&tid->buf_q))) {
164 fi = get_frame_info(skb);
168 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
170 ieee80211_free_txskb(sc->hw, skb);
176 list_add_tail(&bf->list, &bf_head);
177 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
178 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
181 ath_set_rates(tid->an->vif, tid->an->sta, bf);
182 ath_tx_send_normal(sc, txq, NULL, skb);
187 ath_txq_unlock(sc, txq);
188 ath_send_bar(tid, tid->seq_start);
189 ath_txq_lock(sc, txq);
193 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
198 index = ATH_BA_INDEX(tid->seq_start, seqno);
199 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
201 __clear_bit(cindex, tid->tx_buf);
203 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
204 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
205 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
206 if (tid->bar_index >= 0)
211 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
216 index = ATH_BA_INDEX(tid->seq_start, seqno);
217 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
218 __set_bit(cindex, tid->tx_buf);
220 if (index >= ((tid->baw_tail - tid->baw_head) &
221 (ATH_TID_MAX_BUFS - 1))) {
222 tid->baw_tail = cindex;
223 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
228 * TODO: For frame(s) that are in the retry state, we will reuse the
229 * sequence number(s) without setting the retry bit. The
230 * alternative is to give up on these and BAR the receiver's window
233 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
234 struct ath_atx_tid *tid)
239 struct list_head bf_head;
240 struct ath_tx_status ts;
241 struct ath_frame_info *fi;
243 memset(&ts, 0, sizeof(ts));
244 INIT_LIST_HEAD(&bf_head);
246 while ((skb = __skb_dequeue(&tid->buf_q))) {
247 fi = get_frame_info(skb);
251 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
255 list_add_tail(&bf->list, &bf_head);
257 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
258 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
261 tid->seq_next = tid->seq_start;
262 tid->baw_tail = tid->baw_head;
266 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
267 struct sk_buff *skb, int count)
269 struct ath_frame_info *fi = get_frame_info(skb);
270 struct ath_buf *bf = fi->bf;
271 struct ieee80211_hdr *hdr;
272 int prev = fi->retries;
274 TX_STAT_INC(txq->axq_qnum, a_retries);
275 fi->retries += count;
280 hdr = (struct ieee80211_hdr *)skb->data;
281 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
282 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
283 sizeof(*hdr), DMA_TO_DEVICE);
286 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
288 struct ath_buf *bf = NULL;
290 spin_lock_bh(&sc->tx.txbuflock);
292 if (unlikely(list_empty(&sc->tx.txbuf))) {
293 spin_unlock_bh(&sc->tx.txbuflock);
297 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
300 spin_unlock_bh(&sc->tx.txbuflock);
305 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
307 spin_lock_bh(&sc->tx.txbuflock);
308 list_add_tail(&bf->list, &sc->tx.txbuf);
309 spin_unlock_bh(&sc->tx.txbuflock);
312 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
316 tbf = ath_tx_get_buffer(sc);
320 ATH_TXBUF_RESET(tbf);
322 tbf->bf_mpdu = bf->bf_mpdu;
323 tbf->bf_buf_addr = bf->bf_buf_addr;
324 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
325 tbf->bf_state = bf->bf_state;
330 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
331 struct ath_tx_status *ts, int txok,
332 int *nframes, int *nbad)
334 struct ath_frame_info *fi;
336 u32 ba[WME_BA_BMP_SIZE >> 5];
343 isaggr = bf_isaggr(bf);
345 seq_st = ts->ts_seqnum;
346 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
350 fi = get_frame_info(bf->bf_mpdu);
351 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
354 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
362 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
363 struct ath_buf *bf, struct list_head *bf_q,
364 struct ath_tx_status *ts, int txok)
366 struct ath_node *an = NULL;
368 struct ieee80211_sta *sta;
369 struct ieee80211_hw *hw = sc->hw;
370 struct ieee80211_hdr *hdr;
371 struct ieee80211_tx_info *tx_info;
372 struct ath_atx_tid *tid = NULL;
373 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
374 struct list_head bf_head;
375 struct sk_buff_head bf_pending;
376 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
377 u32 ba[WME_BA_BMP_SIZE >> 5];
378 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
379 bool rc_update = true, isba;
380 struct ieee80211_tx_rate rates[4];
381 struct ath_frame_info *fi;
384 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
389 hdr = (struct ieee80211_hdr *)skb->data;
391 tx_info = IEEE80211_SKB_CB(skb);
393 memcpy(rates, bf->rates, sizeof(rates));
395 retries = ts->ts_longretry + 1;
396 for (i = 0; i < ts->ts_rateindex; i++)
397 retries += rates[i].count;
401 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
405 INIT_LIST_HEAD(&bf_head);
407 bf_next = bf->bf_next;
409 if (!bf->bf_stale || bf_next != NULL)
410 list_move_tail(&bf->list, &bf_head);
412 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 0);
419 an = (struct ath_node *)sta->drv_priv;
420 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
421 tid = ATH_AN_2_TID(an, tidno);
422 seq_first = tid->seq_start;
423 isba = ts->ts_flags & ATH9K_TX_BA;
426 * The hardware occasionally sends a tx status for the wrong TID.
427 * In this case, the BA status cannot be considered valid and all
428 * subframes need to be retransmitted
430 * Only BlockAcks have a TID and therefore normal Acks cannot be
433 if (isba && tidno != ts->tid)
436 isaggr = bf_isaggr(bf);
437 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
439 if (isaggr && txok) {
440 if (ts->ts_flags & ATH9K_TX_BA) {
441 seq_st = ts->ts_seqnum;
442 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
445 * AR5416 can become deaf/mute when BA
446 * issue happens. Chip needs to be reset.
447 * But AP code may have sychronization issues
448 * when perform internal reset in this routine.
449 * Only enable reset in STA mode for now.
451 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
456 __skb_queue_head_init(&bf_pending);
458 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
460 u16 seqno = bf->bf_state.seqno;
462 txfail = txpending = sendbar = 0;
463 bf_next = bf->bf_next;
466 tx_info = IEEE80211_SKB_CB(skb);
467 fi = get_frame_info(skb);
469 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) {
471 * Outside of the current BlockAck window,
472 * maybe part of a previous session
475 } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
476 /* transmit completion, subframe is
477 * acked by block ack */
479 } else if (!isaggr && txok) {
480 /* transmit completion */
484 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
485 if (txok || !an->sleeping)
486 ath_tx_set_retry(sc, txq, bf->bf_mpdu,
493 bar_index = max_t(int, bar_index,
494 ATH_BA_INDEX(seq_first, seqno));
498 * Make sure the last desc is reclaimed if it
499 * not a holding desc.
501 INIT_LIST_HEAD(&bf_head);
502 if (bf_next != NULL || !bf_last->bf_stale)
503 list_move_tail(&bf->list, &bf_head);
507 * complete the acked-ones/xretried ones; update
510 ath_tx_update_baw(sc, tid, seqno);
512 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
513 memcpy(tx_info->control.rates, rates, sizeof(rates));
514 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
518 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
521 if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) {
522 tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP;
523 ieee80211_sta_eosp(sta);
525 /* retry the un-acked ones */
526 if (bf->bf_next == NULL && bf_last->bf_stale) {
529 tbf = ath_clone_txbuf(sc, bf_last);
531 * Update tx baw and complete the
532 * frame with failed status if we
536 ath_tx_update_baw(sc, tid, seqno);
538 ath_tx_complete_buf(sc, bf, txq,
540 bar_index = max_t(int, bar_index,
541 ATH_BA_INDEX(seq_first, seqno));
549 * Put this buffer to the temporary pending
550 * queue to retain ordering
552 __skb_queue_tail(&bf_pending, skb);
558 /* prepend un-acked frames to the beginning of the pending frame queue */
559 if (!skb_queue_empty(&bf_pending)) {
561 ieee80211_sta_set_buffered(sta, tid->tidno, true);
563 skb_queue_splice(&bf_pending, &tid->buf_q);
565 ath_tx_queue_tid(txq, tid);
567 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
568 tid->ac->clear_ps_filter = true;
572 if (bar_index >= 0) {
573 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
575 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
576 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
578 ath_txq_unlock(sc, txq);
579 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
580 ath_txq_lock(sc, txq);
586 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
589 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
591 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
592 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
595 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
596 struct ath_tx_status *ts, struct ath_buf *bf,
597 struct list_head *bf_head)
599 struct ieee80211_tx_info *info;
602 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
603 flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
604 txq->axq_tx_inprogress = false;
607 if (bf_is_ampdu_not_probing(bf))
608 txq->axq_ampdu_depth--;
610 if (!bf_isampdu(bf)) {
612 info = IEEE80211_SKB_CB(bf->bf_mpdu);
613 memcpy(info->control.rates, bf->rates,
614 sizeof(info->control.rates));
615 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
617 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok);
619 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok);
621 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) && !flush)
622 ath_txq_schedule(sc, txq);
625 static bool ath_lookup_legacy(struct ath_buf *bf)
628 struct ieee80211_tx_info *tx_info;
629 struct ieee80211_tx_rate *rates;
633 tx_info = IEEE80211_SKB_CB(skb);
634 rates = tx_info->control.rates;
636 for (i = 0; i < 4; i++) {
637 if (!rates[i].count || rates[i].idx < 0)
640 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
647 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
648 struct ath_atx_tid *tid)
651 struct ieee80211_tx_info *tx_info;
652 struct ieee80211_tx_rate *rates;
653 u32 max_4ms_framelen, frmlen;
654 u16 aggr_limit, bt_aggr_limit, legacy = 0;
655 int q = tid->ac->txq->mac80211_qnum;
659 tx_info = IEEE80211_SKB_CB(skb);
663 * Find the lowest frame length among the rate series that will have a
664 * 4ms (or TXOP limited) transmit duration.
666 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
668 for (i = 0; i < 4; i++) {
674 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
679 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
684 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
687 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx];
688 max_4ms_framelen = min(max_4ms_framelen, frmlen);
692 * limit aggregate size by the minimum rate if rate selected is
693 * not a probe rate, if rate selected is a probe rate then
694 * avoid aggregation of this packet.
696 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
699 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX);
702 * Override the default aggregation limit for BTCOEX.
704 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen);
706 aggr_limit = bt_aggr_limit;
709 * h/w can accept aggregates up to 16 bit lengths (65535).
710 * The IE, however can hold up to 65536, which shows up here
711 * as zero. Ignore 65536 since we are constrained by hw.
713 if (tid->an->maxampdu)
714 aggr_limit = min(aggr_limit, tid->an->maxampdu);
720 * Returns the number of delimiters to be added to
721 * meet the minimum required mpdudensity.
723 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
724 struct ath_buf *bf, u16 frmlen,
727 #define FIRST_DESC_NDELIMS 60
728 u32 nsymbits, nsymbols;
731 int width, streams, half_gi, ndelim, mindelim;
732 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
734 /* Select standard number of delimiters based on frame length alone */
735 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
738 * If encryption enabled, hardware requires some more padding between
740 * TODO - this could be improved to be dependent on the rate.
741 * The hardware can keep up at lower rates, but not higher rates
743 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
744 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
745 ndelim += ATH_AGGR_ENCRYPTDELIM;
748 * Add delimiter when using RTS/CTS with aggregation
749 * and non enterprise AR9003 card
751 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
752 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
753 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
756 * Convert desired mpdu density from microeconds to bytes based
757 * on highest rate in rate series (i.e. first rate) to determine
758 * required minimum length for subframe. Take into account
759 * whether high rate is 20 or 40Mhz and half or full GI.
761 * If there is no mpdu density restriction, no further calculation
765 if (tid->an->mpdudensity == 0)
768 rix = bf->rates[0].idx;
769 flags = bf->rates[0].flags;
770 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
771 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
774 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
776 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
781 streams = HT_RC_2_STREAMS(rix);
782 nsymbits = bits_per_symbol[rix % 8][width] * streams;
783 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
785 if (frmlen < minlen) {
786 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
787 ndelim = max(mindelim, ndelim);
793 static struct ath_buf *
794 ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq,
795 struct ath_atx_tid *tid)
797 struct ath_frame_info *fi;
803 skb = skb_peek(&tid->buf_q);
807 fi = get_frame_info(skb);
810 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
813 __skb_unlink(skb, &tid->buf_q);
814 ieee80211_free_txskb(sc->hw, skb);
818 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
819 seqno = bf->bf_state.seqno;
821 /* do not step over block-ack window */
822 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno))
825 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
826 struct ath_tx_status ts = {};
827 struct list_head bf_head;
829 INIT_LIST_HEAD(&bf_head);
830 list_add(&bf->list, &bf_head);
831 __skb_unlink(skb, &tid->buf_q);
832 ath_tx_update_baw(sc, tid, seqno);
833 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
845 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
847 struct ath_atx_tid *tid,
848 struct list_head *bf_q,
851 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
852 struct ath_buf *bf, *bf_first = NULL, *bf_prev = NULL;
853 int rl = 0, nframes = 0, ndelim, prev_al = 0;
854 u16 aggr_limit = 0, al = 0, bpad = 0,
855 al_delta, h_baw = tid->baw_size / 2;
856 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
857 struct ieee80211_tx_info *tx_info;
858 struct ath_frame_info *fi;
862 bf = ath_tx_get_tid_subframe(sc, txq, tid);
864 status = ATH_AGGR_BAW_CLOSED;
869 fi = get_frame_info(skb);
875 ath_set_rates(tid->an->vif, tid->an->sta, bf);
876 aggr_limit = ath_lookup_rate(sc, bf, tid);
880 /* do not exceed aggregation limit */
881 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
884 ((aggr_limit < (al + bpad + al_delta + prev_al)) ||
885 ath_lookup_legacy(bf))) {
886 status = ATH_AGGR_LIMITED;
890 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
891 if (nframes && (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE))
894 /* do not exceed subframe limit */
895 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
896 status = ATH_AGGR_LIMITED;
900 /* add padding for previous frame to aggregation length */
901 al += bpad + al_delta;
904 * Get the delimiters needed to meet the MPDU
905 * density for this node.
907 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
909 bpad = PADBYTES(al_delta) + (ndelim << 2);
914 /* link buffers of this frame to the aggregate */
916 ath_tx_addto_baw(sc, tid, bf->bf_state.seqno);
917 bf->bf_state.ndelim = ndelim;
919 __skb_unlink(skb, &tid->buf_q);
920 list_add_tail(&bf->list, bf_q);
922 bf_prev->bf_next = bf;
926 } while (!skb_queue_empty(&tid->buf_q));
936 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
937 * width - 0 for 20 MHz, 1 for 40 MHz
938 * half_gi - to use 4us v/s 3.6 us for symbol time
940 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
941 int width, int half_gi, bool shortPreamble)
943 u32 nbits, nsymbits, duration, nsymbols;
946 /* find number of symbols: PLCP + data */
947 streams = HT_RC_2_STREAMS(rix);
948 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
949 nsymbits = bits_per_symbol[rix % 8][width] * streams;
950 nsymbols = (nbits + nsymbits - 1) / nsymbits;
953 duration = SYMBOL_TIME(nsymbols);
955 duration = SYMBOL_TIME_HALFGI(nsymbols);
957 /* addup duration for legacy/ht training and signal fields */
958 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
963 static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi)
965 int streams = HT_RC_2_STREAMS(mcs);
969 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec);
970 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams;
971 bits -= OFDM_PLCP_BITS;
973 bytes -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
980 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop)
982 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi;
985 /* 4ms is the default (and maximum) duration */
986 if (!txop || txop > 4096)
989 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20];
990 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI];
991 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40];
992 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI];
993 for (mcs = 0; mcs < 32; mcs++) {
994 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false);
995 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true);
996 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false);
997 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true);
1001 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
1002 struct ath_tx_info *info, int len)
1004 struct ath_hw *ah = sc->sc_ah;
1005 struct sk_buff *skb;
1006 struct ieee80211_tx_info *tx_info;
1007 struct ieee80211_tx_rate *rates;
1008 const struct ieee80211_rate *rate;
1009 struct ieee80211_hdr *hdr;
1010 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1015 tx_info = IEEE80211_SKB_CB(skb);
1017 hdr = (struct ieee80211_hdr *)skb->data;
1019 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1020 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
1021 info->rtscts_rate = fi->rtscts_rate;
1023 for (i = 0; i < ARRAY_SIZE(bf->rates); i++) {
1024 bool is_40, is_sgi, is_sp;
1027 if (!rates[i].count || (rates[i].idx < 0))
1031 info->rates[i].Tries = rates[i].count;
1033 if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1034 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1035 info->flags |= ATH9K_TXDESC_RTSENA;
1036 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1037 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1038 info->flags |= ATH9K_TXDESC_CTSENA;
1041 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1042 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
1043 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1044 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1046 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1047 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1048 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1050 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1052 info->rates[i].Rate = rix | 0x80;
1053 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1054 ah->txchainmask, info->rates[i].Rate);
1055 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
1056 is_40, is_sgi, is_sp);
1057 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1058 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
1063 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
1064 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1065 !(rate->flags & IEEE80211_RATE_ERP_G))
1066 phy = WLAN_RC_PHY_CCK;
1068 phy = WLAN_RC_PHY_OFDM;
1070 info->rates[i].Rate = rate->hw_value;
1071 if (rate->hw_value_short) {
1072 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1073 info->rates[i].Rate |= rate->hw_value_short;
1078 if (bf->bf_state.bfs_paprd)
1079 info->rates[i].ChSel = ah->txchainmask;
1081 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1082 ah->txchainmask, info->rates[i].Rate);
1084 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1085 phy, rate->bitrate * 100, len, rix, is_sp);
1088 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1089 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1090 info->flags &= ~ATH9K_TXDESC_RTSENA;
1092 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1093 if (info->flags & ATH9K_TXDESC_RTSENA)
1094 info->flags &= ~ATH9K_TXDESC_CTSENA;
1097 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1099 struct ieee80211_hdr *hdr;
1100 enum ath9k_pkt_type htype;
1103 hdr = (struct ieee80211_hdr *)skb->data;
1104 fc = hdr->frame_control;
1106 if (ieee80211_is_beacon(fc))
1107 htype = ATH9K_PKT_TYPE_BEACON;
1108 else if (ieee80211_is_probe_resp(fc))
1109 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1110 else if (ieee80211_is_atim(fc))
1111 htype = ATH9K_PKT_TYPE_ATIM;
1112 else if (ieee80211_is_pspoll(fc))
1113 htype = ATH9K_PKT_TYPE_PSPOLL;
1115 htype = ATH9K_PKT_TYPE_NORMAL;
1120 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1121 struct ath_txq *txq, int len)
1123 struct ath_hw *ah = sc->sc_ah;
1124 struct ath_buf *bf_first = NULL;
1125 struct ath_tx_info info;
1127 memset(&info, 0, sizeof(info));
1128 info.is_first = true;
1129 info.is_last = true;
1130 info.txpower = MAX_RATE_POWER;
1131 info.qcu = txq->axq_qnum;
1134 struct sk_buff *skb = bf->bf_mpdu;
1135 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1136 struct ath_frame_info *fi = get_frame_info(skb);
1137 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1139 info.type = get_hw_packet_type(skb);
1141 info.link = bf->bf_next->bf_daddr;
1148 info.flags = ATH9K_TXDESC_INTREQ;
1149 if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) ||
1150 txq == sc->tx.uapsdq)
1151 info.flags |= ATH9K_TXDESC_CLRDMASK;
1153 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1154 info.flags |= ATH9K_TXDESC_NOACK;
1155 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1156 info.flags |= ATH9K_TXDESC_LDPC;
1158 if (bf->bf_state.bfs_paprd)
1159 info.flags |= (u32) bf->bf_state.bfs_paprd <<
1160 ATH9K_TXDESC_PAPRD_S;
1162 ath_buf_set_rate(sc, bf, &info, len);
1165 info.buf_addr[0] = bf->bf_buf_addr;
1166 info.buf_len[0] = skb->len;
1167 info.pkt_len = fi->framelen;
1168 info.keyix = fi->keyix;
1169 info.keytype = fi->keytype;
1173 info.aggr = AGGR_BUF_FIRST;
1174 else if (bf == bf_first->bf_lastbf)
1175 info.aggr = AGGR_BUF_LAST;
1177 info.aggr = AGGR_BUF_MIDDLE;
1179 info.ndelim = bf->bf_state.ndelim;
1180 info.aggr_len = len;
1183 if (bf == bf_first->bf_lastbf)
1186 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1191 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1192 struct ath_atx_tid *tid)
1195 enum ATH_AGGR_STATUS status;
1196 struct ieee80211_tx_info *tx_info;
1197 struct list_head bf_q;
1201 if (skb_queue_empty(&tid->buf_q))
1204 INIT_LIST_HEAD(&bf_q);
1206 status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len);
1209 * no frames picked up to be aggregated;
1210 * block-ack window is not open.
1212 if (list_empty(&bf_q))
1215 bf = list_first_entry(&bf_q, struct ath_buf, list);
1216 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
1217 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1219 if (tid->ac->clear_ps_filter) {
1220 tid->ac->clear_ps_filter = false;
1221 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1223 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
1226 /* if only one frame, send as non-aggregate */
1227 if (bf == bf->bf_lastbf) {
1228 aggr_len = get_frame_info(bf->bf_mpdu)->framelen;
1229 bf->bf_state.bf_type = BUF_AMPDU;
1231 TX_STAT_INC(txq->axq_qnum, a_aggr);
1234 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1235 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1236 } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH &&
1237 status != ATH_AGGR_BAW_CLOSED);
1240 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1243 struct ath_atx_tid *txtid;
1244 struct ath_node *an;
1247 an = (struct ath_node *)sta->drv_priv;
1248 txtid = ATH_AN_2_TID(an, tid);
1250 /* update ampdu factor/density, they may have changed. This may happen
1251 * in HT IBSS when a beacon with HT-info is received after the station
1252 * has already been added.
1254 if (sta->ht_cap.ht_supported) {
1255 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
1256 sta->ht_cap.ampdu_factor);
1257 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
1258 an->mpdudensity = density;
1261 txtid->active = true;
1262 txtid->paused = true;
1263 *ssn = txtid->seq_start = txtid->seq_next;
1264 txtid->bar_index = -1;
1266 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1267 txtid->baw_head = txtid->baw_tail = 0;
1272 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1274 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1275 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1276 struct ath_txq *txq = txtid->ac->txq;
1278 ath_txq_lock(sc, txq);
1279 txtid->active = false;
1280 txtid->paused = true;
1281 ath_tx_flush_tid(sc, txtid);
1282 ath_txq_unlock_complete(sc, txq);
1285 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1286 struct ath_node *an)
1288 struct ath_atx_tid *tid;
1289 struct ath_atx_ac *ac;
1290 struct ath_txq *txq;
1294 for (tidno = 0, tid = &an->tid[tidno];
1295 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1303 ath_txq_lock(sc, txq);
1305 buffered = !skb_queue_empty(&tid->buf_q);
1308 list_del(&tid->list);
1312 list_del(&ac->list);
1315 ath_txq_unlock(sc, txq);
1317 ieee80211_sta_set_buffered(sta, tidno, buffered);
1321 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1323 struct ath_atx_tid *tid;
1324 struct ath_atx_ac *ac;
1325 struct ath_txq *txq;
1328 for (tidno = 0, tid = &an->tid[tidno];
1329 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1334 ath_txq_lock(sc, txq);
1335 ac->clear_ps_filter = true;
1337 if (!skb_queue_empty(&tid->buf_q) && !tid->paused) {
1338 ath_tx_queue_tid(txq, tid);
1339 ath_txq_schedule(sc, txq);
1342 ath_txq_unlock_complete(sc, txq);
1346 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta,
1349 struct ath_atx_tid *tid;
1350 struct ath_node *an;
1351 struct ath_txq *txq;
1353 an = (struct ath_node *)sta->drv_priv;
1354 tid = ATH_AN_2_TID(an, tidno);
1357 ath_txq_lock(sc, txq);
1359 tid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
1360 tid->paused = false;
1362 if (!skb_queue_empty(&tid->buf_q)) {
1363 ath_tx_queue_tid(txq, tid);
1364 ath_txq_schedule(sc, txq);
1367 ath_txq_unlock_complete(sc, txq);
1370 void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
1371 struct ieee80211_sta *sta,
1372 u16 tids, int nframes,
1373 enum ieee80211_frame_release_type reason,
1376 struct ath_softc *sc = hw->priv;
1377 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1378 struct ath_txq *txq = sc->tx.uapsdq;
1379 struct ieee80211_tx_info *info;
1380 struct list_head bf_q;
1381 struct ath_buf *bf_tail = NULL, *bf;
1385 INIT_LIST_HEAD(&bf_q);
1386 for (i = 0; tids && nframes; i++, tids >>= 1) {
1387 struct ath_atx_tid *tid;
1392 tid = ATH_AN_2_TID(an, i);
1396 ath_txq_lock(sc, tid->ac->txq);
1397 while (!skb_queue_empty(&tid->buf_q) && nframes > 0) {
1398 bf = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq, tid);
1402 __skb_unlink(bf->bf_mpdu, &tid->buf_q);
1403 list_add_tail(&bf->list, &bf_q);
1404 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1405 ath_tx_addto_baw(sc, tid, bf->bf_state.seqno);
1406 bf->bf_state.bf_type &= ~BUF_AGGR;
1408 bf_tail->bf_next = bf;
1413 TX_STAT_INC(txq->axq_qnum, a_queued_hw);
1415 if (skb_queue_empty(&tid->buf_q))
1416 ieee80211_sta_set_buffered(an->sta, i, false);
1418 ath_txq_unlock_complete(sc, tid->ac->txq);
1421 if (list_empty(&bf_q))
1424 info = IEEE80211_SKB_CB(bf_tail->bf_mpdu);
1425 info->flags |= IEEE80211_TX_STATUS_EOSP;
1427 bf = list_first_entry(&bf_q, struct ath_buf, list);
1428 ath_txq_lock(sc, txq);
1429 ath_tx_fill_desc(sc, bf, txq, 0);
1430 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1431 ath_txq_unlock(sc, txq);
1434 /********************/
1435 /* Queue Management */
1436 /********************/
1438 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1440 struct ath_hw *ah = sc->sc_ah;
1441 struct ath9k_tx_queue_info qi;
1442 static const int subtype_txq_to_hwq[] = {
1443 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE,
1444 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK,
1445 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI,
1446 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO,
1450 memset(&qi, 0, sizeof(qi));
1451 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1452 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1453 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1454 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1455 qi.tqi_physCompBuf = 0;
1458 * Enable interrupts only for EOL and DESC conditions.
1459 * We mark tx descriptors to receive a DESC interrupt
1460 * when a tx queue gets deep; otherwise waiting for the
1461 * EOL to reap descriptors. Note that this is done to
1462 * reduce interrupt load and this only defers reaping
1463 * descriptors, never transmitting frames. Aside from
1464 * reducing interrupts this also permits more concurrency.
1465 * The only potential downside is if the tx queue backs
1466 * up in which case the top half of the kernel may backup
1467 * due to a lack of tx descriptors.
1469 * The UAPSD queue is an exception, since we take a desc-
1470 * based intr on the EOSP frames.
1472 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1473 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
1475 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1476 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1478 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1479 TXQ_FLAG_TXDESCINT_ENABLE;
1481 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1482 if (axq_qnum == -1) {
1484 * NB: don't print a message, this happens
1485 * normally on parts with too few tx queues
1489 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1490 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1492 txq->axq_qnum = axq_qnum;
1493 txq->mac80211_qnum = -1;
1494 txq->axq_link = NULL;
1495 __skb_queue_head_init(&txq->complete_q);
1496 INIT_LIST_HEAD(&txq->axq_q);
1497 INIT_LIST_HEAD(&txq->axq_acq);
1498 spin_lock_init(&txq->axq_lock);
1500 txq->axq_ampdu_depth = 0;
1501 txq->axq_tx_inprogress = false;
1502 sc->tx.txqsetup |= 1<<axq_qnum;
1504 txq->txq_headidx = txq->txq_tailidx = 0;
1505 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1506 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1508 return &sc->tx.txq[axq_qnum];
1511 int ath_txq_update(struct ath_softc *sc, int qnum,
1512 struct ath9k_tx_queue_info *qinfo)
1514 struct ath_hw *ah = sc->sc_ah;
1516 struct ath9k_tx_queue_info qi;
1518 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1520 ath9k_hw_get_txq_props(ah, qnum, &qi);
1521 qi.tqi_aifs = qinfo->tqi_aifs;
1522 qi.tqi_cwmin = qinfo->tqi_cwmin;
1523 qi.tqi_cwmax = qinfo->tqi_cwmax;
1524 qi.tqi_burstTime = qinfo->tqi_burstTime;
1525 qi.tqi_readyTime = qinfo->tqi_readyTime;
1527 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1528 ath_err(ath9k_hw_common(sc->sc_ah),
1529 "Unable to update hardware queue %u!\n", qnum);
1532 ath9k_hw_resettxqueue(ah, qnum);
1538 int ath_cabq_update(struct ath_softc *sc)
1540 struct ath9k_tx_queue_info qi;
1541 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
1542 int qnum = sc->beacon.cabq->axq_qnum;
1544 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1546 * Ensure the readytime % is within the bounds.
1548 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1549 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1550 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1551 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1553 qi.tqi_readyTime = (cur_conf->beacon_interval *
1554 sc->config.cabqReadytime) / 100;
1555 ath_txq_update(sc, qnum, &qi);
1560 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1561 struct list_head *list)
1563 struct ath_buf *bf, *lastbf;
1564 struct list_head bf_head;
1565 struct ath_tx_status ts;
1567 memset(&ts, 0, sizeof(ts));
1568 ts.ts_status = ATH9K_TX_FLUSH;
1569 INIT_LIST_HEAD(&bf_head);
1571 while (!list_empty(list)) {
1572 bf = list_first_entry(list, struct ath_buf, list);
1575 list_del(&bf->list);
1577 ath_tx_return_buffer(sc, bf);
1581 lastbf = bf->bf_lastbf;
1582 list_cut_position(&bf_head, list, &lastbf->list);
1583 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
1588 * Drain a given TX queue (could be Beacon or Data)
1590 * This assumes output has been stopped and
1591 * we do not need to block ath_tx_tasklet.
1593 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq)
1595 ath_txq_lock(sc, txq);
1597 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1598 int idx = txq->txq_tailidx;
1600 while (!list_empty(&txq->txq_fifo[idx])) {
1601 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]);
1603 INCR(idx, ATH_TXFIFO_DEPTH);
1605 txq->txq_tailidx = idx;
1608 txq->axq_link = NULL;
1609 txq->axq_tx_inprogress = false;
1610 ath_drain_txq_list(sc, txq, &txq->axq_q);
1612 ath_txq_unlock_complete(sc, txq);
1615 bool ath_drain_all_txq(struct ath_softc *sc)
1617 struct ath_hw *ah = sc->sc_ah;
1618 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1619 struct ath_txq *txq;
1623 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
1626 ath9k_hw_abort_tx_dma(ah);
1628 /* Check if any queue remains active */
1629 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1630 if (!ATH_TXQ_SETUP(sc, i))
1633 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1638 ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1640 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1641 if (!ATH_TXQ_SETUP(sc, i))
1645 * The caller will resume queues with ieee80211_wake_queues.
1646 * Mark the queue as not stopped to prevent ath_tx_complete
1647 * from waking the queue too early.
1649 txq = &sc->tx.txq[i];
1650 txq->stopped = false;
1651 ath_draintxq(sc, txq);
1657 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1659 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1660 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1663 /* For each axq_acq entry, for each tid, try to schedule packets
1664 * for transmit until ampdu_depth has reached min Q depth.
1666 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1668 struct ath_atx_ac *ac, *ac_tmp, *last_ac;
1669 struct ath_atx_tid *tid, *last_tid;
1671 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags) ||
1672 list_empty(&txq->axq_acq) ||
1673 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1676 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1677 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
1679 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1680 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1681 list_del(&ac->list);
1684 while (!list_empty(&ac->tid_q)) {
1685 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1687 list_del(&tid->list);
1693 ath_tx_sched_aggr(sc, txq, tid);
1696 * add tid to round-robin queue if more frames
1697 * are pending for the tid
1699 if (!skb_queue_empty(&tid->buf_q))
1700 ath_tx_queue_tid(txq, tid);
1702 if (tid == last_tid ||
1703 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1707 if (!list_empty(&ac->tid_q) && !ac->sched) {
1709 list_add_tail(&ac->list, &txq->axq_acq);
1712 if (ac == last_ac ||
1713 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1723 * Insert a chain of ath_buf (descriptors) on a txq and
1724 * assume the descriptors are already chained together by caller.
1726 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1727 struct list_head *head, bool internal)
1729 struct ath_hw *ah = sc->sc_ah;
1730 struct ath_common *common = ath9k_hw_common(ah);
1731 struct ath_buf *bf, *bf_last;
1732 bool puttxbuf = false;
1736 * Insert the frame on the outbound list and
1737 * pass it on to the hardware.
1740 if (list_empty(head))
1743 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1744 bf = list_first_entry(head, struct ath_buf, list);
1745 bf_last = list_entry(head->prev, struct ath_buf, list);
1747 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n",
1748 txq->axq_qnum, txq->axq_depth);
1750 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1751 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
1752 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1755 list_splice_tail_init(head, &txq->axq_q);
1757 if (txq->axq_link) {
1758 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
1759 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n",
1760 txq->axq_qnum, txq->axq_link,
1761 ito64(bf->bf_daddr), bf->bf_desc);
1765 txq->axq_link = bf_last->bf_desc;
1769 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1770 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1771 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n",
1772 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1776 TX_STAT_INC(txq->axq_qnum, txstart);
1777 ath9k_hw_txstart(ah, txq->axq_qnum);
1782 if (bf_is_ampdu_not_probing(bf))
1783 txq->axq_ampdu_depth++;
1787 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_txq *txq,
1788 struct ath_atx_tid *tid, struct sk_buff *skb,
1789 struct ath_tx_control *txctl)
1791 struct ath_frame_info *fi = get_frame_info(skb);
1792 struct list_head bf_head;
1796 * Do not queue to h/w when any of the following conditions is true:
1797 * - there are pending frames in software queue
1798 * - the TID is currently paused for ADDBA/BAR request
1799 * - seqno is not within block-ack window
1800 * - h/w queue depth exceeds low water mark
1802 if ((!skb_queue_empty(&tid->buf_q) || tid->paused ||
1803 !BAW_WITHIN(tid->seq_start, tid->baw_size, tid->seq_next) ||
1804 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) &&
1805 txq != sc->tx.uapsdq) {
1807 * Add this frame to software queue for scheduling later
1810 TX_STAT_INC(txq->axq_qnum, a_queued_sw);
1811 __skb_queue_tail(&tid->buf_q, skb);
1812 if (!txctl->an || !txctl->an->sleeping)
1813 ath_tx_queue_tid(txq, tid);
1817 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
1819 ieee80211_free_txskb(sc->hw, skb);
1823 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1824 bf->bf_state.bf_type = BUF_AMPDU;
1825 INIT_LIST_HEAD(&bf_head);
1826 list_add(&bf->list, &bf_head);
1828 /* Add sub-frame to BAW */
1829 ath_tx_addto_baw(sc, tid, bf->bf_state.seqno);
1831 /* Queue to h/w without aggregation */
1832 TX_STAT_INC(txq->axq_qnum, a_queued_hw);
1834 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
1835 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
1838 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1839 struct ath_atx_tid *tid, struct sk_buff *skb)
1841 struct ath_frame_info *fi = get_frame_info(skb);
1842 struct list_head bf_head;
1847 INIT_LIST_HEAD(&bf_head);
1848 list_add_tail(&bf->list, &bf_head);
1849 bf->bf_state.bf_type = 0;
1853 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
1854 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
1855 TX_STAT_INC(txq->axq_qnum, queued);
1858 static void setup_frame_info(struct ieee80211_hw *hw,
1859 struct ieee80211_sta *sta,
1860 struct sk_buff *skb,
1863 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1864 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1865 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1866 const struct ieee80211_rate *rate;
1867 struct ath_frame_info *fi = get_frame_info(skb);
1868 struct ath_node *an = NULL;
1869 enum ath9k_key_type keytype;
1870 bool short_preamble = false;
1873 * We check if Short Preamble is needed for the CTS rate by
1874 * checking the BSS's global flag.
1875 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1877 if (tx_info->control.vif &&
1878 tx_info->control.vif->bss_conf.use_short_preamble)
1879 short_preamble = true;
1881 rate = ieee80211_get_rts_cts_rate(hw, tx_info);
1882 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
1885 an = (struct ath_node *) sta->drv_priv;
1887 memset(fi, 0, sizeof(*fi));
1889 fi->keyix = hw_key->hw_key_idx;
1890 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
1891 fi->keyix = an->ps_key;
1893 fi->keyix = ATH9K_TXKEYIX_INVALID;
1894 fi->keytype = keytype;
1895 fi->framelen = framelen;
1896 fi->rtscts_rate = rate->hw_value;
1898 fi->rtscts_rate |= rate->hw_value_short;
1901 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
1903 struct ath_hw *ah = sc->sc_ah;
1904 struct ath9k_channel *curchan = ah->curchan;
1906 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) &&
1907 (curchan->channelFlags & CHANNEL_5GHZ) &&
1908 (chainmask == 0x7) && (rate < 0x90))
1910 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
1918 * Assign a descriptor (and sequence number if necessary,
1919 * and map buffer for DMA. Frees skb on error
1921 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
1922 struct ath_txq *txq,
1923 struct ath_atx_tid *tid,
1924 struct sk_buff *skb)
1926 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1927 struct ath_frame_info *fi = get_frame_info(skb);
1928 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1933 bf = ath_tx_get_buffer(sc);
1935 ath_dbg(common, XMIT, "TX buffers are full\n");
1939 ATH_TXBUF_RESET(bf);
1942 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
1943 seqno = tid->seq_next;
1944 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
1947 hdr->seq_ctrl |= cpu_to_le16(fragno);
1949 if (!ieee80211_has_morefrags(hdr->frame_control))
1950 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1952 bf->bf_state.seqno = seqno;
1957 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
1958 skb->len, DMA_TO_DEVICE);
1959 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
1961 bf->bf_buf_addr = 0;
1962 ath_err(ath9k_hw_common(sc->sc_ah),
1963 "dma_mapping_error() on TX\n");
1964 ath_tx_return_buffer(sc, bf);
1973 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
1974 struct ath_tx_control *txctl)
1976 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1977 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1978 struct ieee80211_sta *sta = txctl->sta;
1979 struct ieee80211_vif *vif = info->control.vif;
1980 struct ath_softc *sc = hw->priv;
1981 int frmlen = skb->len + FCS_LEN;
1982 int padpos, padsize;
1984 /* NOTE: sta can be NULL according to net/mac80211.h */
1986 txctl->an = (struct ath_node *)sta->drv_priv;
1988 if (info->control.hw_key)
1989 frmlen += info->control.hw_key->icv_len;
1992 * As a temporary workaround, assign seq# here; this will likely need
1993 * to be cleaned up to work better with Beacon transmission and virtual
1996 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1997 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1998 sc->tx.seq_no += 0x10;
1999 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2000 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2003 if ((vif && vif->type != NL80211_IFTYPE_AP &&
2004 vif->type != NL80211_IFTYPE_AP_VLAN) ||
2005 !ieee80211_is_data(hdr->frame_control))
2006 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
2008 /* Add the padding after the header if this is not already done */
2009 padpos = ieee80211_hdrlen(hdr->frame_control);
2010 padsize = padpos & 3;
2011 if (padsize && skb->len > padpos) {
2012 if (skb_headroom(skb) < padsize)
2015 skb_push(skb, padsize);
2016 memmove(skb->data, skb->data + padsize, padpos);
2019 setup_frame_info(hw, sta, skb, frmlen);
2024 /* Upon failure caller should free skb */
2025 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
2026 struct ath_tx_control *txctl)
2028 struct ieee80211_hdr *hdr;
2029 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2030 struct ieee80211_sta *sta = txctl->sta;
2031 struct ieee80211_vif *vif = info->control.vif;
2032 struct ath_softc *sc = hw->priv;
2033 struct ath_txq *txq = txctl->txq;
2034 struct ath_atx_tid *tid = NULL;
2040 ret = ath_tx_prepare(hw, skb, txctl);
2044 hdr = (struct ieee80211_hdr *) skb->data;
2046 * At this point, the vif, hw_key and sta pointers in the tx control
2047 * info are no longer valid (overwritten by the ath_frame_info data.
2050 q = skb_get_queue_mapping(skb);
2052 ath_txq_lock(sc, txq);
2053 if (txq == sc->tx.txq_map[q] &&
2054 ++txq->pending_frames > sc->tx.txq_max_pending[q] &&
2056 ieee80211_stop_queue(sc->hw, q);
2057 txq->stopped = true;
2060 if (info->flags & IEEE80211_TX_CTL_PS_RESPONSE) {
2061 ath_txq_unlock(sc, txq);
2062 txq = sc->tx.uapsdq;
2063 ath_txq_lock(sc, txq);
2066 if (txctl->an && ieee80211_is_data_qos(hdr->frame_control)) {
2067 tidno = ieee80211_get_qos_ctl(hdr)[0] &
2068 IEEE80211_QOS_CTL_TID_MASK;
2069 tid = ATH_AN_2_TID(txctl->an, tidno);
2071 WARN_ON(tid->ac->txq != txctl->txq);
2074 if ((info->flags & IEEE80211_TX_CTL_AMPDU) && tid) {
2076 * Try aggregation if it's a unicast data frame
2077 * and the destination is HT capable.
2079 ath_tx_send_ampdu(sc, txq, tid, skb, txctl);
2083 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
2086 dev_kfree_skb_any(skb);
2088 ieee80211_free_txskb(sc->hw, skb);
2092 bf->bf_state.bfs_paprd = txctl->paprd;
2095 bf->bf_state.bfs_paprd_timestamp = jiffies;
2097 ath_set_rates(vif, sta, bf);
2098 ath_tx_send_normal(sc, txq, tid, skb);
2101 ath_txq_unlock(sc, txq);
2106 void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2107 struct sk_buff *skb)
2109 struct ath_softc *sc = hw->priv;
2110 struct ath_tx_control txctl = {
2111 .txq = sc->beacon.cabq
2113 struct ath_tx_info info = {};
2114 struct ieee80211_hdr *hdr;
2115 struct ath_buf *bf_tail = NULL;
2122 sc->cur_beacon_conf.beacon_interval * 1000 *
2123 sc->cur_beacon_conf.dtim_period / ATH_BCBUF;
2126 struct ath_frame_info *fi = get_frame_info(skb);
2128 if (ath_tx_prepare(hw, skb, &txctl))
2131 bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb);
2136 ath_set_rates(vif, NULL, bf);
2137 ath_buf_set_rate(sc, bf, &info, fi->framelen);
2138 duration += info.rates[0].PktDuration;
2140 bf_tail->bf_next = bf;
2142 list_add_tail(&bf->list, &bf_q);
2146 if (duration > max_duration)
2149 skb = ieee80211_get_buffered_bc(hw, vif);
2153 ieee80211_free_txskb(hw, skb);
2155 if (list_empty(&bf_q))
2158 bf = list_first_entry(&bf_q, struct ath_buf, list);
2159 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
2161 if (hdr->frame_control & IEEE80211_FCTL_MOREDATA) {
2162 hdr->frame_control &= ~IEEE80211_FCTL_MOREDATA;
2163 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
2164 sizeof(*hdr), DMA_TO_DEVICE);
2167 ath_txq_lock(sc, txctl.txq);
2168 ath_tx_fill_desc(sc, bf, txctl.txq, 0);
2169 ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false);
2170 TX_STAT_INC(txctl.txq->axq_qnum, queued);
2171 ath_txq_unlock(sc, txctl.txq);
2178 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
2179 int tx_flags, struct ath_txq *txq)
2181 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2182 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2183 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
2184 int q, padpos, padsize;
2185 unsigned long flags;
2187 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
2189 if (sc->sc_ah->caldata)
2190 sc->sc_ah->caldata->paprd_packet_sent = true;
2192 if (!(tx_flags & ATH_TX_ERROR))
2193 /* Frame was ACKed */
2194 tx_info->flags |= IEEE80211_TX_STAT_ACK;
2196 padpos = ieee80211_hdrlen(hdr->frame_control);
2197 padsize = padpos & 3;
2198 if (padsize && skb->len>padpos+padsize) {
2200 * Remove MAC header padding before giving the frame back to
2203 memmove(skb->data + padsize, skb->data, padpos);
2204 skb_pull(skb, padsize);
2207 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2208 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
2209 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
2211 "Going back to sleep after having received TX status (0x%lx)\n",
2212 sc->ps_flags & (PS_WAIT_FOR_BEACON |
2214 PS_WAIT_FOR_PSPOLL_DATA |
2215 PS_WAIT_FOR_TX_ACK));
2217 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2219 __skb_queue_tail(&txq->complete_q, skb);
2221 q = skb_get_queue_mapping(skb);
2222 if (txq == sc->tx.uapsdq)
2223 txq = sc->tx.txq_map[q];
2225 if (txq == sc->tx.txq_map[q]) {
2226 if (WARN_ON(--txq->pending_frames < 0))
2227 txq->pending_frames = 0;
2230 txq->pending_frames < sc->tx.txq_max_pending[q]) {
2231 ieee80211_wake_queue(sc->hw, q);
2232 txq->stopped = false;
2237 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
2238 struct ath_txq *txq, struct list_head *bf_q,
2239 struct ath_tx_status *ts, int txok)
2241 struct sk_buff *skb = bf->bf_mpdu;
2242 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2243 unsigned long flags;
2247 tx_flags |= ATH_TX_ERROR;
2249 if (ts->ts_status & ATH9K_TXERR_FILT)
2250 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2252 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2253 bf->bf_buf_addr = 0;
2255 if (bf->bf_state.bfs_paprd) {
2256 if (time_after(jiffies,
2257 bf->bf_state.bfs_paprd_timestamp +
2258 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2259 dev_kfree_skb_any(skb);
2261 complete(&sc->paprd_complete);
2263 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2264 ath_tx_complete(sc, skb, tx_flags, txq);
2266 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2267 * accidentally reference it later.
2272 * Return the list of ath_buf of this mpdu to free queue
2274 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2275 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2276 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2279 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2280 struct ath_tx_status *ts, int nframes, int nbad,
2283 struct sk_buff *skb = bf->bf_mpdu;
2284 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2285 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2286 struct ieee80211_hw *hw = sc->hw;
2287 struct ath_hw *ah = sc->sc_ah;
2291 tx_info->status.ack_signal = ts->ts_rssi;
2293 tx_rateindex = ts->ts_rateindex;
2294 WARN_ON(tx_rateindex >= hw->max_rates);
2296 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2297 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2299 BUG_ON(nbad > nframes);
2301 tx_info->status.ampdu_len = nframes;
2302 tx_info->status.ampdu_ack_len = nframes - nbad;
2304 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2305 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2307 * If an underrun error is seen assume it as an excessive
2308 * retry only if max frame trigger level has been reached
2309 * (2 KB for single stream, and 4 KB for dual stream).
2310 * Adjust the long retry as if the frame was tried
2311 * hw->max_rate_tries times to affect how rate control updates
2312 * PER for the failed rate.
2313 * In case of congestion on the bus penalizing this type of
2314 * underruns should help hardware actually transmit new frames
2315 * successfully by eventually preferring slower rates.
2316 * This itself should also alleviate congestion on the bus.
2318 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2319 ATH9K_TX_DELIM_UNDERRUN)) &&
2320 ieee80211_is_data(hdr->frame_control) &&
2321 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2322 tx_info->status.rates[tx_rateindex].count =
2326 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2327 tx_info->status.rates[i].count = 0;
2328 tx_info->status.rates[i].idx = -1;
2331 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2334 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2336 struct ath_hw *ah = sc->sc_ah;
2337 struct ath_common *common = ath9k_hw_common(ah);
2338 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2339 struct list_head bf_head;
2340 struct ath_desc *ds;
2341 struct ath_tx_status ts;
2344 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n",
2345 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2348 ath_txq_lock(sc, txq);
2350 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
2353 if (list_empty(&txq->axq_q)) {
2354 txq->axq_link = NULL;
2355 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2356 ath_txq_schedule(sc, txq);
2359 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2362 * There is a race condition that a BH gets scheduled
2363 * after sw writes TxE and before hw re-load the last
2364 * descriptor to get the newly chained one.
2365 * Software must keep the last DONE descriptor as a
2366 * holding descriptor - software does so by marking
2367 * it with the STALE flag.
2372 if (list_is_last(&bf_held->list, &txq->axq_q))
2375 bf = list_entry(bf_held->list.next, struct ath_buf,
2379 lastbf = bf->bf_lastbf;
2380 ds = lastbf->bf_desc;
2382 memset(&ts, 0, sizeof(ts));
2383 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2384 if (status == -EINPROGRESS)
2387 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2390 * Remove ath_buf's of the same transmit unit from txq,
2391 * however leave the last descriptor back as the holding
2392 * descriptor for hw.
2394 lastbf->bf_stale = true;
2395 INIT_LIST_HEAD(&bf_head);
2396 if (!list_is_singular(&lastbf->list))
2397 list_cut_position(&bf_head,
2398 &txq->axq_q, lastbf->list.prev);
2401 list_del(&bf_held->list);
2402 ath_tx_return_buffer(sc, bf_held);
2405 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2407 ath_txq_unlock_complete(sc, txq);
2410 void ath_tx_tasklet(struct ath_softc *sc)
2412 struct ath_hw *ah = sc->sc_ah;
2413 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;
2416 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2417 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2418 ath_tx_processq(sc, &sc->tx.txq[i]);
2422 void ath_tx_edma_tasklet(struct ath_softc *sc)
2424 struct ath_tx_status ts;
2425 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2426 struct ath_hw *ah = sc->sc_ah;
2427 struct ath_txq *txq;
2428 struct ath_buf *bf, *lastbf;
2429 struct list_head bf_head;
2430 struct list_head *fifo_list;
2434 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
2437 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2438 if (status == -EINPROGRESS)
2440 if (status == -EIO) {
2441 ath_dbg(common, XMIT, "Error processing tx status\n");
2445 /* Process beacon completions separately */
2446 if (ts.qid == sc->beacon.beaconq) {
2447 sc->beacon.tx_processed = true;
2448 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2452 txq = &sc->tx.txq[ts.qid];
2454 ath_txq_lock(sc, txq);
2456 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2458 fifo_list = &txq->txq_fifo[txq->txq_tailidx];
2459 if (list_empty(fifo_list)) {
2460 ath_txq_unlock(sc, txq);
2464 bf = list_first_entry(fifo_list, struct ath_buf, list);
2466 list_del(&bf->list);
2467 ath_tx_return_buffer(sc, bf);
2468 bf = list_first_entry(fifo_list, struct ath_buf, list);
2471 lastbf = bf->bf_lastbf;
2473 INIT_LIST_HEAD(&bf_head);
2474 if (list_is_last(&lastbf->list, fifo_list)) {
2475 list_splice_tail_init(fifo_list, &bf_head);
2476 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2478 if (!list_empty(&txq->axq_q)) {
2479 struct list_head bf_q;
2481 INIT_LIST_HEAD(&bf_q);
2482 txq->axq_link = NULL;
2483 list_splice_tail_init(&txq->axq_q, &bf_q);
2484 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2487 lastbf->bf_stale = true;
2489 list_cut_position(&bf_head, fifo_list,
2493 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2494 ath_txq_unlock_complete(sc, txq);
2502 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2504 struct ath_descdma *dd = &sc->txsdma;
2505 u8 txs_len = sc->sc_ah->caps.txs_len;
2507 dd->dd_desc_len = size * txs_len;
2508 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
2509 &dd->dd_desc_paddr, GFP_KERNEL);
2516 static int ath_tx_edma_init(struct ath_softc *sc)
2520 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2522 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2523 sc->txsdma.dd_desc_paddr,
2524 ATH_TXSTATUS_RING_SIZE);
2529 int ath_tx_init(struct ath_softc *sc, int nbufs)
2531 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2534 spin_lock_init(&sc->tx.txbuflock);
2536 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2540 "Failed to allocate tx descriptors: %d\n", error);
2544 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2545 "beacon", ATH_BCBUF, 1, 1);
2548 "Failed to allocate beacon descriptors: %d\n", error);
2552 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2554 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2555 error = ath_tx_edma_init(sc);
2560 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2562 struct ath_atx_tid *tid;
2563 struct ath_atx_ac *ac;
2566 for (tidno = 0, tid = &an->tid[tidno];
2567 tidno < IEEE80211_NUM_TIDS;
2571 tid->seq_start = tid->seq_next = 0;
2572 tid->baw_size = WME_MAX_BA;
2573 tid->baw_head = tid->baw_tail = 0;
2575 tid->paused = false;
2576 tid->active = false;
2577 __skb_queue_head_init(&tid->buf_q);
2578 acno = TID_TO_WME_AC(tidno);
2579 tid->ac = &an->ac[acno];
2582 for (acno = 0, ac = &an->ac[acno];
2583 acno < IEEE80211_NUM_ACS; acno++, ac++) {
2585 ac->txq = sc->tx.txq_map[acno];
2586 INIT_LIST_HEAD(&ac->tid_q);
2590 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2592 struct ath_atx_ac *ac;
2593 struct ath_atx_tid *tid;
2594 struct ath_txq *txq;
2597 for (tidno = 0, tid = &an->tid[tidno];
2598 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
2603 ath_txq_lock(sc, txq);
2606 list_del(&tid->list);
2611 list_del(&ac->list);
2612 tid->ac->sched = false;
2615 ath_tid_drain(sc, txq, tid);
2616 tid->active = false;
2618 ath_txq_unlock(sc, txq);