2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define TIME_SYMBOLS(t) ((t) >> 2)
33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
38 static u16 bits_per_symbol[][2] = {
40 { 26, 54 }, /* 0: BPSK */
41 { 52, 108 }, /* 1: QPSK 1/2 */
42 { 78, 162 }, /* 2: QPSK 3/4 */
43 { 104, 216 }, /* 3: 16-QAM 1/2 */
44 { 156, 324 }, /* 4: 16-QAM 3/4 */
45 { 208, 432 }, /* 5: 64-QAM 2/3 */
46 { 234, 486 }, /* 6: 64-QAM 3/4 */
47 { 260, 540 }, /* 7: 64-QAM 5/6 */
50 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
52 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
53 struct ath_atx_tid *tid, struct sk_buff *skb);
54 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
55 int tx_flags, struct ath_txq *txq);
56 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
57 struct ath_txq *txq, struct list_head *bf_q,
58 struct ath_tx_status *ts, int txok);
59 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
60 struct list_head *head, bool internal);
61 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
62 struct ath_tx_status *ts, int nframes, int nbad,
64 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
66 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
68 struct ath_atx_tid *tid,
78 /*********************/
79 /* Aggregation logic */
80 /*********************/
82 void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq)
83 __acquires(&txq->axq_lock)
85 spin_lock_bh(&txq->axq_lock);
88 void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq)
89 __releases(&txq->axq_lock)
91 spin_unlock_bh(&txq->axq_lock);
94 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
95 __releases(&txq->axq_lock)
97 struct sk_buff_head q;
100 __skb_queue_head_init(&q);
101 skb_queue_splice_init(&txq->complete_q, &q);
102 spin_unlock_bh(&txq->axq_lock);
104 while ((skb = __skb_dequeue(&q)))
105 ieee80211_tx_status(sc->hw, skb);
108 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
110 struct ath_atx_ac *ac = tid->ac;
119 list_add_tail(&tid->list, &ac->tid_q);
125 list_add_tail(&ac->list, &txq->axq_acq);
128 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
130 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
131 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
132 sizeof(tx_info->rate_driver_data));
133 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
136 static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
138 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
139 seqno << IEEE80211_SEQ_SEQ_SHIFT);
142 static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta,
145 ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates,
146 ARRAY_SIZE(bf->rates));
149 static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq,
154 q = skb_get_queue_mapping(skb);
155 if (txq == sc->tx.uapsdq)
156 txq = sc->tx.txq_map[q];
158 if (txq != sc->tx.txq_map[q])
161 if (WARN_ON(--txq->pending_frames < 0))
162 txq->pending_frames = 0;
165 txq->pending_frames < sc->tx.txq_max_pending[q]) {
166 ieee80211_wake_queue(sc->hw, q);
167 txq->stopped = false;
171 static struct ath_atx_tid *
172 ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb)
174 struct ieee80211_hdr *hdr;
177 hdr = (struct ieee80211_hdr *) skb->data;
178 if (ieee80211_is_data_qos(hdr->frame_control))
179 tidno = ieee80211_get_qos_ctl(hdr)[0];
181 tidno &= IEEE80211_QOS_CTL_TID_MASK;
182 return ATH_AN_2_TID(an, tidno);
185 static bool ath_tid_has_buffered(struct ath_atx_tid *tid)
187 return !skb_queue_empty(&tid->buf_q) || !skb_queue_empty(&tid->retry_q);
190 static struct sk_buff *ath_tid_dequeue(struct ath_atx_tid *tid)
194 skb = __skb_dequeue(&tid->retry_q);
196 skb = __skb_dequeue(&tid->buf_q);
202 * ath_tx_tid_change_state:
203 * - clears a-mpdu flag of previous session
204 * - force sequence number allocation to fix next BlockAck Window
207 ath_tx_tid_change_state(struct ath_softc *sc, struct ath_atx_tid *tid)
209 struct ath_txq *txq = tid->ac->txq;
210 struct ieee80211_tx_info *tx_info;
211 struct sk_buff *skb, *tskb;
213 struct ath_frame_info *fi;
215 skb_queue_walk_safe(&tid->buf_q, skb, tskb) {
216 fi = get_frame_info(skb);
219 tx_info = IEEE80211_SKB_CB(skb);
220 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU;
225 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
227 __skb_unlink(skb, &tid->buf_q);
228 ath_txq_skb_done(sc, txq, skb);
229 ieee80211_free_txskb(sc->hw, skb);
236 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
238 struct ath_txq *txq = tid->ac->txq;
241 struct list_head bf_head;
242 struct ath_tx_status ts;
243 struct ath_frame_info *fi;
244 bool sendbar = false;
246 INIT_LIST_HEAD(&bf_head);
248 memset(&ts, 0, sizeof(ts));
250 while ((skb = __skb_dequeue(&tid->retry_q))) {
251 fi = get_frame_info(skb);
254 ath_txq_skb_done(sc, txq, skb);
255 ieee80211_free_txskb(sc->hw, skb);
259 if (fi->baw_tracked) {
260 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
264 list_add_tail(&bf->list, &bf_head);
265 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
269 ath_txq_unlock(sc, txq);
270 ath_send_bar(tid, tid->seq_start);
271 ath_txq_lock(sc, txq);
275 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
280 index = ATH_BA_INDEX(tid->seq_start, seqno);
281 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
283 __clear_bit(cindex, tid->tx_buf);
285 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
286 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
287 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
288 if (tid->bar_index >= 0)
293 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
296 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
297 u16 seqno = bf->bf_state.seqno;
300 index = ATH_BA_INDEX(tid->seq_start, seqno);
301 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
302 __set_bit(cindex, tid->tx_buf);
305 if (index >= ((tid->baw_tail - tid->baw_head) &
306 (ATH_TID_MAX_BUFS - 1))) {
307 tid->baw_tail = cindex;
308 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
313 * TODO: For frame(s) that are in the retry state, we will reuse the
314 * sequence number(s) without setting the retry bit. The
315 * alternative is to give up on these and BAR the receiver's window
318 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
319 struct ath_atx_tid *tid)
324 struct list_head bf_head;
325 struct ath_tx_status ts;
326 struct ath_frame_info *fi;
328 memset(&ts, 0, sizeof(ts));
329 INIT_LIST_HEAD(&bf_head);
331 while ((skb = ath_tid_dequeue(tid))) {
332 fi = get_frame_info(skb);
336 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
340 list_add_tail(&bf->list, &bf_head);
342 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
343 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
346 tid->seq_next = tid->seq_start;
347 tid->baw_tail = tid->baw_head;
351 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
352 struct sk_buff *skb, int count)
354 struct ath_frame_info *fi = get_frame_info(skb);
355 struct ath_buf *bf = fi->bf;
356 struct ieee80211_hdr *hdr;
357 int prev = fi->retries;
359 TX_STAT_INC(txq->axq_qnum, a_retries);
360 fi->retries += count;
365 hdr = (struct ieee80211_hdr *)skb->data;
366 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
367 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
368 sizeof(*hdr), DMA_TO_DEVICE);
371 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
373 struct ath_buf *bf = NULL;
375 spin_lock_bh(&sc->tx.txbuflock);
377 if (unlikely(list_empty(&sc->tx.txbuf))) {
378 spin_unlock_bh(&sc->tx.txbuflock);
382 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
385 spin_unlock_bh(&sc->tx.txbuflock);
390 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
392 spin_lock_bh(&sc->tx.txbuflock);
393 list_add_tail(&bf->list, &sc->tx.txbuf);
394 spin_unlock_bh(&sc->tx.txbuflock);
397 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
401 tbf = ath_tx_get_buffer(sc);
405 ATH_TXBUF_RESET(tbf);
407 tbf->bf_mpdu = bf->bf_mpdu;
408 tbf->bf_buf_addr = bf->bf_buf_addr;
409 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
410 tbf->bf_state = bf->bf_state;
415 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
416 struct ath_tx_status *ts, int txok,
417 int *nframes, int *nbad)
419 struct ath_frame_info *fi;
421 u32 ba[WME_BA_BMP_SIZE >> 5];
428 isaggr = bf_isaggr(bf);
430 seq_st = ts->ts_seqnum;
431 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
435 fi = get_frame_info(bf->bf_mpdu);
436 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
439 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
447 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
448 struct ath_buf *bf, struct list_head *bf_q,
449 struct ath_tx_status *ts, int txok)
451 struct ath_node *an = NULL;
453 struct ieee80211_sta *sta;
454 struct ieee80211_hw *hw = sc->hw;
455 struct ieee80211_hdr *hdr;
456 struct ieee80211_tx_info *tx_info;
457 struct ath_atx_tid *tid = NULL;
458 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
459 struct list_head bf_head;
460 struct sk_buff_head bf_pending;
461 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
462 u32 ba[WME_BA_BMP_SIZE >> 5];
463 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
464 bool rc_update = true, isba;
465 struct ieee80211_tx_rate rates[4];
466 struct ath_frame_info *fi;
468 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
473 hdr = (struct ieee80211_hdr *)skb->data;
475 tx_info = IEEE80211_SKB_CB(skb);
477 memcpy(rates, bf->rates, sizeof(rates));
479 retries = ts->ts_longretry + 1;
480 for (i = 0; i < ts->ts_rateindex; i++)
481 retries += rates[i].count;
485 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
489 INIT_LIST_HEAD(&bf_head);
491 bf_next = bf->bf_next;
493 if (!bf->bf_stale || bf_next != NULL)
494 list_move_tail(&bf->list, &bf_head);
496 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 0);
503 an = (struct ath_node *)sta->drv_priv;
504 tid = ath_get_skb_tid(sc, an, skb);
505 seq_first = tid->seq_start;
506 isba = ts->ts_flags & ATH9K_TX_BA;
509 * The hardware occasionally sends a tx status for the wrong TID.
510 * In this case, the BA status cannot be considered valid and all
511 * subframes need to be retransmitted
513 * Only BlockAcks have a TID and therefore normal Acks cannot be
516 if (isba && tid->tidno != ts->tid)
519 isaggr = bf_isaggr(bf);
520 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
522 if (isaggr && txok) {
523 if (ts->ts_flags & ATH9K_TX_BA) {
524 seq_st = ts->ts_seqnum;
525 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
528 * AR5416 can become deaf/mute when BA
529 * issue happens. Chip needs to be reset.
530 * But AP code may have sychronization issues
531 * when perform internal reset in this routine.
532 * Only enable reset in STA mode for now.
534 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
539 __skb_queue_head_init(&bf_pending);
541 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
543 u16 seqno = bf->bf_state.seqno;
545 txfail = txpending = sendbar = 0;
546 bf_next = bf->bf_next;
549 tx_info = IEEE80211_SKB_CB(skb);
550 fi = get_frame_info(skb);
552 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) ||
555 * Outside of the current BlockAck window,
556 * maybe part of a previous session
559 } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
560 /* transmit completion, subframe is
561 * acked by block ack */
563 } else if (!isaggr && txok) {
564 /* transmit completion */
568 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
569 if (txok || !an->sleeping)
570 ath_tx_set_retry(sc, txq, bf->bf_mpdu,
577 bar_index = max_t(int, bar_index,
578 ATH_BA_INDEX(seq_first, seqno));
582 * Make sure the last desc is reclaimed if it
583 * not a holding desc.
585 INIT_LIST_HEAD(&bf_head);
586 if (bf_next != NULL || !bf_last->bf_stale)
587 list_move_tail(&bf->list, &bf_head);
591 * complete the acked-ones/xretried ones; update
594 ath_tx_update_baw(sc, tid, seqno);
596 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
597 memcpy(tx_info->control.rates, rates, sizeof(rates));
598 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
602 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
605 if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) {
606 tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP;
607 ieee80211_sta_eosp(sta);
609 /* retry the un-acked ones */
610 if (bf->bf_next == NULL && bf_last->bf_stale) {
613 tbf = ath_clone_txbuf(sc, bf_last);
615 * Update tx baw and complete the
616 * frame with failed status if we
620 ath_tx_update_baw(sc, tid, seqno);
622 ath_tx_complete_buf(sc, bf, txq,
624 bar_index = max_t(int, bar_index,
625 ATH_BA_INDEX(seq_first, seqno));
633 * Put this buffer to the temporary pending
634 * queue to retain ordering
636 __skb_queue_tail(&bf_pending, skb);
642 /* prepend un-acked frames to the beginning of the pending frame queue */
643 if (!skb_queue_empty(&bf_pending)) {
645 ieee80211_sta_set_buffered(sta, tid->tidno, true);
647 skb_queue_splice_tail(&bf_pending, &tid->retry_q);
649 ath_tx_queue_tid(txq, tid);
651 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
652 tid->ac->clear_ps_filter = true;
656 if (bar_index >= 0) {
657 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
659 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
660 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
662 ath_txq_unlock(sc, txq);
663 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
664 ath_txq_lock(sc, txq);
670 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
673 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
675 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
676 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
679 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
680 struct ath_tx_status *ts, struct ath_buf *bf,
681 struct list_head *bf_head)
683 struct ieee80211_tx_info *info;
686 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
687 flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
688 txq->axq_tx_inprogress = false;
691 if (bf_is_ampdu_not_probing(bf))
692 txq->axq_ampdu_depth--;
694 if (!bf_isampdu(bf)) {
696 info = IEEE80211_SKB_CB(bf->bf_mpdu);
697 memcpy(info->control.rates, bf->rates,
698 sizeof(info->control.rates));
699 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
701 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok);
703 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok);
706 ath_txq_schedule(sc, txq);
709 static bool ath_lookup_legacy(struct ath_buf *bf)
712 struct ieee80211_tx_info *tx_info;
713 struct ieee80211_tx_rate *rates;
717 tx_info = IEEE80211_SKB_CB(skb);
718 rates = tx_info->control.rates;
720 for (i = 0; i < 4; i++) {
721 if (!rates[i].count || rates[i].idx < 0)
724 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
731 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
732 struct ath_atx_tid *tid)
735 struct ieee80211_tx_info *tx_info;
736 struct ieee80211_tx_rate *rates;
737 u32 max_4ms_framelen, frmlen;
738 u16 aggr_limit, bt_aggr_limit, legacy = 0;
739 int q = tid->ac->txq->mac80211_qnum;
743 tx_info = IEEE80211_SKB_CB(skb);
747 * Find the lowest frame length among the rate series that will have a
748 * 4ms (or TXOP limited) transmit duration.
750 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
752 for (i = 0; i < 4; i++) {
758 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
763 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
768 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
771 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx];
772 max_4ms_framelen = min(max_4ms_framelen, frmlen);
776 * limit aggregate size by the minimum rate if rate selected is
777 * not a probe rate, if rate selected is a probe rate then
778 * avoid aggregation of this packet.
780 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
783 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX);
786 * Override the default aggregation limit for BTCOEX.
788 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen);
790 aggr_limit = bt_aggr_limit;
793 * h/w can accept aggregates up to 16 bit lengths (65535).
794 * The IE, however can hold up to 65536, which shows up here
795 * as zero. Ignore 65536 since we are constrained by hw.
797 if (tid->an->maxampdu)
798 aggr_limit = min(aggr_limit, tid->an->maxampdu);
804 * Returns the number of delimiters to be added to
805 * meet the minimum required mpdudensity.
807 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
808 struct ath_buf *bf, u16 frmlen,
811 #define FIRST_DESC_NDELIMS 60
812 u32 nsymbits, nsymbols;
815 int width, streams, half_gi, ndelim, mindelim;
816 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
818 /* Select standard number of delimiters based on frame length alone */
819 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
822 * If encryption enabled, hardware requires some more padding between
824 * TODO - this could be improved to be dependent on the rate.
825 * The hardware can keep up at lower rates, but not higher rates
827 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
828 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
829 ndelim += ATH_AGGR_ENCRYPTDELIM;
832 * Add delimiter when using RTS/CTS with aggregation
833 * and non enterprise AR9003 card
835 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
836 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
837 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
840 * Convert desired mpdu density from microeconds to bytes based
841 * on highest rate in rate series (i.e. first rate) to determine
842 * required minimum length for subframe. Take into account
843 * whether high rate is 20 or 40Mhz and half or full GI.
845 * If there is no mpdu density restriction, no further calculation
849 if (tid->an->mpdudensity == 0)
852 rix = bf->rates[0].idx;
853 flags = bf->rates[0].flags;
854 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
855 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
858 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
860 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
865 streams = HT_RC_2_STREAMS(rix);
866 nsymbits = bits_per_symbol[rix % 8][width] * streams;
867 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
869 if (frmlen < minlen) {
870 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
871 ndelim = max(mindelim, ndelim);
877 static struct ath_buf *
878 ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq,
879 struct ath_atx_tid *tid, struct sk_buff_head **q)
881 struct ieee80211_tx_info *tx_info;
882 struct ath_frame_info *fi;
889 if (skb_queue_empty(*q))
896 fi = get_frame_info(skb);
899 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
902 __skb_unlink(skb, *q);
903 ath_txq_skb_done(sc, txq, skb);
904 ieee80211_free_txskb(sc->hw, skb);
911 tx_info = IEEE80211_SKB_CB(skb);
912 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
913 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
914 bf->bf_state.bf_type = 0;
918 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
919 seqno = bf->bf_state.seqno;
921 /* do not step over block-ack window */
922 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno))
925 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
926 struct ath_tx_status ts = {};
927 struct list_head bf_head;
929 INIT_LIST_HEAD(&bf_head);
930 list_add(&bf->list, &bf_head);
931 __skb_unlink(skb, *q);
932 ath_tx_update_baw(sc, tid, seqno);
933 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
944 ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq,
945 struct ath_atx_tid *tid, struct list_head *bf_q,
946 struct ath_buf *bf_first, struct sk_buff_head *tid_q,
949 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
950 struct ath_buf *bf = bf_first, *bf_prev = NULL;
951 int nframes = 0, ndelim;
952 u16 aggr_limit = 0, al = 0, bpad = 0,
953 al_delta, h_baw = tid->baw_size / 2;
954 struct ieee80211_tx_info *tx_info;
955 struct ath_frame_info *fi;
960 aggr_limit = ath_lookup_rate(sc, bf, tid);
964 fi = get_frame_info(skb);
966 /* do not exceed aggregation limit */
967 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
969 if (aggr_limit < al + bpad + al_delta ||
970 ath_lookup_legacy(bf) || nframes >= h_baw)
973 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
974 if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
975 !(tx_info->flags & IEEE80211_TX_CTL_AMPDU))
979 /* add padding for previous frame to aggregation length */
980 al += bpad + al_delta;
983 * Get the delimiters needed to meet the MPDU
984 * density for this node.
986 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
988 bpad = PADBYTES(al_delta) + (ndelim << 2);
993 /* link buffers of this frame to the aggregate */
994 if (!fi->baw_tracked)
995 ath_tx_addto_baw(sc, tid, bf);
996 bf->bf_state.ndelim = ndelim;
998 __skb_unlink(skb, tid_q);
999 list_add_tail(&bf->list, bf_q);
1001 bf_prev->bf_next = bf;
1005 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1010 } while (ath_tid_has_buffered(tid));
1013 bf->bf_lastbf = bf_prev;
1015 if (bf == bf_prev) {
1016 al = get_frame_info(bf->bf_mpdu)->framelen;
1017 bf->bf_state.bf_type = BUF_AMPDU;
1019 TX_STAT_INC(txq->axq_qnum, a_aggr);
1030 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1031 * width - 0 for 20 MHz, 1 for 40 MHz
1032 * half_gi - to use 4us v/s 3.6 us for symbol time
1034 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1035 int width, int half_gi, bool shortPreamble)
1037 u32 nbits, nsymbits, duration, nsymbols;
1040 /* find number of symbols: PLCP + data */
1041 streams = HT_RC_2_STREAMS(rix);
1042 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1043 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1044 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1047 duration = SYMBOL_TIME(nsymbols);
1049 duration = SYMBOL_TIME_HALFGI(nsymbols);
1051 /* addup duration for legacy/ht training and signal fields */
1052 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1057 static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi)
1059 int streams = HT_RC_2_STREAMS(mcs);
1063 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec);
1064 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams;
1065 bits -= OFDM_PLCP_BITS;
1067 bytes -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1074 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop)
1076 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi;
1079 /* 4ms is the default (and maximum) duration */
1080 if (!txop || txop > 4096)
1083 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20];
1084 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI];
1085 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40];
1086 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI];
1087 for (mcs = 0; mcs < 32; mcs++) {
1088 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false);
1089 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true);
1090 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false);
1091 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true);
1095 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
1096 struct ath_tx_info *info, int len, bool rts)
1098 struct ath_hw *ah = sc->sc_ah;
1099 struct sk_buff *skb;
1100 struct ieee80211_tx_info *tx_info;
1101 struct ieee80211_tx_rate *rates;
1102 const struct ieee80211_rate *rate;
1103 struct ieee80211_hdr *hdr;
1104 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1105 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1110 tx_info = IEEE80211_SKB_CB(skb);
1112 hdr = (struct ieee80211_hdr *)skb->data;
1114 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1115 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
1116 info->rtscts_rate = fi->rtscts_rate;
1118 for (i = 0; i < ARRAY_SIZE(bf->rates); i++) {
1119 bool is_40, is_sgi, is_sp;
1122 if (!rates[i].count || (rates[i].idx < 0))
1126 info->rates[i].Tries = rates[i].count;
1129 * Handle RTS threshold for unaggregated HT frames.
1131 if (bf_isampdu(bf) && !bf_isaggr(bf) &&
1132 (rates[i].flags & IEEE80211_TX_RC_MCS) &&
1133 unlikely(rts_thresh != (u32) -1)) {
1134 if (!rts_thresh || (len > rts_thresh))
1138 if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1139 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1140 info->flags |= ATH9K_TXDESC_RTSENA;
1141 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1142 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1143 info->flags |= ATH9K_TXDESC_CTSENA;
1146 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1147 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
1148 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1149 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1151 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1152 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1153 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1155 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1157 info->rates[i].Rate = rix | 0x80;
1158 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1159 ah->txchainmask, info->rates[i].Rate);
1160 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
1161 is_40, is_sgi, is_sp);
1162 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1163 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
1168 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
1169 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1170 !(rate->flags & IEEE80211_RATE_ERP_G))
1171 phy = WLAN_RC_PHY_CCK;
1173 phy = WLAN_RC_PHY_OFDM;
1175 info->rates[i].Rate = rate->hw_value;
1176 if (rate->hw_value_short) {
1177 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1178 info->rates[i].Rate |= rate->hw_value_short;
1183 if (bf->bf_state.bfs_paprd)
1184 info->rates[i].ChSel = ah->txchainmask;
1186 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1187 ah->txchainmask, info->rates[i].Rate);
1189 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1190 phy, rate->bitrate * 100, len, rix, is_sp);
1193 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1194 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1195 info->flags &= ~ATH9K_TXDESC_RTSENA;
1197 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1198 if (info->flags & ATH9K_TXDESC_RTSENA)
1199 info->flags &= ~ATH9K_TXDESC_CTSENA;
1202 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1204 struct ieee80211_hdr *hdr;
1205 enum ath9k_pkt_type htype;
1208 hdr = (struct ieee80211_hdr *)skb->data;
1209 fc = hdr->frame_control;
1211 if (ieee80211_is_beacon(fc))
1212 htype = ATH9K_PKT_TYPE_BEACON;
1213 else if (ieee80211_is_probe_resp(fc))
1214 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1215 else if (ieee80211_is_atim(fc))
1216 htype = ATH9K_PKT_TYPE_ATIM;
1217 else if (ieee80211_is_pspoll(fc))
1218 htype = ATH9K_PKT_TYPE_PSPOLL;
1220 htype = ATH9K_PKT_TYPE_NORMAL;
1225 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1226 struct ath_txq *txq, int len)
1228 struct ath_hw *ah = sc->sc_ah;
1229 struct ath_buf *bf_first = NULL;
1230 struct ath_tx_info info;
1231 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1234 memset(&info, 0, sizeof(info));
1235 info.is_first = true;
1236 info.is_last = true;
1237 info.txpower = MAX_RATE_POWER;
1238 info.qcu = txq->axq_qnum;
1241 struct sk_buff *skb = bf->bf_mpdu;
1242 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1243 struct ath_frame_info *fi = get_frame_info(skb);
1244 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1246 info.type = get_hw_packet_type(skb);
1248 info.link = bf->bf_next->bf_daddr;
1255 info.flags = ATH9K_TXDESC_INTREQ;
1256 if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) ||
1257 txq == sc->tx.uapsdq)
1258 info.flags |= ATH9K_TXDESC_CLRDMASK;
1260 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1261 info.flags |= ATH9K_TXDESC_NOACK;
1262 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1263 info.flags |= ATH9K_TXDESC_LDPC;
1265 if (bf->bf_state.bfs_paprd)
1266 info.flags |= (u32) bf->bf_state.bfs_paprd <<
1267 ATH9K_TXDESC_PAPRD_S;
1270 * mac80211 doesn't handle RTS threshold for HT because
1271 * the decision has to be taken based on AMPDU length
1272 * and aggregation is done entirely inside ath9k.
1273 * Set the RTS/CTS flag for the first subframe based
1276 if (aggr && (bf == bf_first) &&
1277 unlikely(rts_thresh != (u32) -1)) {
1279 * "len" is the size of the entire AMPDU.
1281 if (!rts_thresh || (len > rts_thresh))
1284 ath_buf_set_rate(sc, bf, &info, len, rts);
1287 info.buf_addr[0] = bf->bf_buf_addr;
1288 info.buf_len[0] = skb->len;
1289 info.pkt_len = fi->framelen;
1290 info.keyix = fi->keyix;
1291 info.keytype = fi->keytype;
1295 info.aggr = AGGR_BUF_FIRST;
1296 else if (bf == bf_first->bf_lastbf)
1297 info.aggr = AGGR_BUF_LAST;
1299 info.aggr = AGGR_BUF_MIDDLE;
1301 info.ndelim = bf->bf_state.ndelim;
1302 info.aggr_len = len;
1305 if (bf == bf_first->bf_lastbf)
1308 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1314 ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq,
1315 struct ath_atx_tid *tid, struct list_head *bf_q,
1316 struct ath_buf *bf_first, struct sk_buff_head *tid_q)
1318 struct ath_buf *bf = bf_first, *bf_prev = NULL;
1319 struct sk_buff *skb;
1323 struct ieee80211_tx_info *tx_info;
1327 __skb_unlink(skb, tid_q);
1328 list_add_tail(&bf->list, bf_q);
1330 bf_prev->bf_next = bf;
1336 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1340 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1341 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1344 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1348 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1349 struct ath_atx_tid *tid)
1352 struct ieee80211_tx_info *tx_info;
1353 struct sk_buff_head *tid_q;
1354 struct list_head bf_q;
1356 bool aggr, last = true;
1359 if (!ath_tid_has_buffered(tid))
1362 INIT_LIST_HEAD(&bf_q);
1364 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1368 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1369 aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU);
1370 if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) ||
1371 (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH))
1374 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1376 last = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf,
1379 ath_tx_form_burst(sc, txq, tid, &bf_q, bf, tid_q);
1381 if (list_empty(&bf_q))
1384 if (tid->ac->clear_ps_filter) {
1385 tid->ac->clear_ps_filter = false;
1386 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1389 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1390 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1394 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1397 struct ath_atx_tid *txtid;
1398 struct ath_node *an;
1401 an = (struct ath_node *)sta->drv_priv;
1402 txtid = ATH_AN_2_TID(an, tid);
1404 /* update ampdu factor/density, they may have changed. This may happen
1405 * in HT IBSS when a beacon with HT-info is received after the station
1406 * has already been added.
1408 if (sta->ht_cap.ht_supported) {
1409 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
1410 sta->ht_cap.ampdu_factor);
1411 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
1412 an->mpdudensity = density;
1415 /* force sequence number allocation for pending frames */
1416 ath_tx_tid_change_state(sc, txtid);
1418 txtid->active = true;
1419 txtid->paused = true;
1420 *ssn = txtid->seq_start = txtid->seq_next;
1421 txtid->bar_index = -1;
1423 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1424 txtid->baw_head = txtid->baw_tail = 0;
1429 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1431 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1432 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1433 struct ath_txq *txq = txtid->ac->txq;
1435 ath_txq_lock(sc, txq);
1436 txtid->active = false;
1437 txtid->paused = false;
1438 ath_tx_flush_tid(sc, txtid);
1439 ath_tx_tid_change_state(sc, txtid);
1440 ath_txq_unlock_complete(sc, txq);
1443 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1444 struct ath_node *an)
1446 struct ath_atx_tid *tid;
1447 struct ath_atx_ac *ac;
1448 struct ath_txq *txq;
1452 for (tidno = 0, tid = &an->tid[tidno];
1453 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1461 ath_txq_lock(sc, txq);
1463 buffered = ath_tid_has_buffered(tid);
1466 list_del(&tid->list);
1470 list_del(&ac->list);
1473 ath_txq_unlock(sc, txq);
1475 ieee80211_sta_set_buffered(sta, tidno, buffered);
1479 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1481 struct ath_atx_tid *tid;
1482 struct ath_atx_ac *ac;
1483 struct ath_txq *txq;
1486 for (tidno = 0, tid = &an->tid[tidno];
1487 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1492 ath_txq_lock(sc, txq);
1493 ac->clear_ps_filter = true;
1495 if (!tid->paused && ath_tid_has_buffered(tid)) {
1496 ath_tx_queue_tid(txq, tid);
1497 ath_txq_schedule(sc, txq);
1500 ath_txq_unlock_complete(sc, txq);
1504 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta,
1507 struct ath_atx_tid *tid;
1508 struct ath_node *an;
1509 struct ath_txq *txq;
1511 an = (struct ath_node *)sta->drv_priv;
1512 tid = ATH_AN_2_TID(an, tidno);
1515 ath_txq_lock(sc, txq);
1517 tid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
1518 tid->paused = false;
1520 if (ath_tid_has_buffered(tid)) {
1521 ath_tx_queue_tid(txq, tid);
1522 ath_txq_schedule(sc, txq);
1525 ath_txq_unlock_complete(sc, txq);
1528 void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
1529 struct ieee80211_sta *sta,
1530 u16 tids, int nframes,
1531 enum ieee80211_frame_release_type reason,
1534 struct ath_softc *sc = hw->priv;
1535 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1536 struct ath_txq *txq = sc->tx.uapsdq;
1537 struct ieee80211_tx_info *info;
1538 struct list_head bf_q;
1539 struct ath_buf *bf_tail = NULL, *bf;
1540 struct sk_buff_head *tid_q;
1544 INIT_LIST_HEAD(&bf_q);
1545 for (i = 0; tids && nframes; i++, tids >>= 1) {
1546 struct ath_atx_tid *tid;
1551 tid = ATH_AN_2_TID(an, i);
1555 ath_txq_lock(sc, tid->ac->txq);
1556 while (nframes > 0) {
1557 bf = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq, tid, &tid_q);
1561 __skb_unlink(bf->bf_mpdu, tid_q);
1562 list_add_tail(&bf->list, &bf_q);
1563 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1564 ath_tx_addto_baw(sc, tid, bf);
1565 bf->bf_state.bf_type &= ~BUF_AGGR;
1567 bf_tail->bf_next = bf;
1572 TX_STAT_INC(txq->axq_qnum, a_queued_hw);
1574 if (!ath_tid_has_buffered(tid))
1575 ieee80211_sta_set_buffered(an->sta, i, false);
1577 ath_txq_unlock_complete(sc, tid->ac->txq);
1580 if (list_empty(&bf_q))
1583 info = IEEE80211_SKB_CB(bf_tail->bf_mpdu);
1584 info->flags |= IEEE80211_TX_STATUS_EOSP;
1586 bf = list_first_entry(&bf_q, struct ath_buf, list);
1587 ath_txq_lock(sc, txq);
1588 ath_tx_fill_desc(sc, bf, txq, 0);
1589 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1590 ath_txq_unlock(sc, txq);
1593 /********************/
1594 /* Queue Management */
1595 /********************/
1597 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1599 struct ath_hw *ah = sc->sc_ah;
1600 struct ath9k_tx_queue_info qi;
1601 static const int subtype_txq_to_hwq[] = {
1602 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE,
1603 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK,
1604 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI,
1605 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO,
1609 memset(&qi, 0, sizeof(qi));
1610 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1611 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1612 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1613 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1614 qi.tqi_physCompBuf = 0;
1617 * Enable interrupts only for EOL and DESC conditions.
1618 * We mark tx descriptors to receive a DESC interrupt
1619 * when a tx queue gets deep; otherwise waiting for the
1620 * EOL to reap descriptors. Note that this is done to
1621 * reduce interrupt load and this only defers reaping
1622 * descriptors, never transmitting frames. Aside from
1623 * reducing interrupts this also permits more concurrency.
1624 * The only potential downside is if the tx queue backs
1625 * up in which case the top half of the kernel may backup
1626 * due to a lack of tx descriptors.
1628 * The UAPSD queue is an exception, since we take a desc-
1629 * based intr on the EOSP frames.
1631 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1632 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
1634 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1635 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1637 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1638 TXQ_FLAG_TXDESCINT_ENABLE;
1640 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1641 if (axq_qnum == -1) {
1643 * NB: don't print a message, this happens
1644 * normally on parts with too few tx queues
1648 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1649 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1651 txq->axq_qnum = axq_qnum;
1652 txq->mac80211_qnum = -1;
1653 txq->axq_link = NULL;
1654 __skb_queue_head_init(&txq->complete_q);
1655 INIT_LIST_HEAD(&txq->axq_q);
1656 INIT_LIST_HEAD(&txq->axq_acq);
1657 spin_lock_init(&txq->axq_lock);
1659 txq->axq_ampdu_depth = 0;
1660 txq->axq_tx_inprogress = false;
1661 sc->tx.txqsetup |= 1<<axq_qnum;
1663 txq->txq_headidx = txq->txq_tailidx = 0;
1664 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1665 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1667 return &sc->tx.txq[axq_qnum];
1670 int ath_txq_update(struct ath_softc *sc, int qnum,
1671 struct ath9k_tx_queue_info *qinfo)
1673 struct ath_hw *ah = sc->sc_ah;
1675 struct ath9k_tx_queue_info qi;
1677 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1679 ath9k_hw_get_txq_props(ah, qnum, &qi);
1680 qi.tqi_aifs = qinfo->tqi_aifs;
1681 qi.tqi_cwmin = qinfo->tqi_cwmin;
1682 qi.tqi_cwmax = qinfo->tqi_cwmax;
1683 qi.tqi_burstTime = qinfo->tqi_burstTime;
1684 qi.tqi_readyTime = qinfo->tqi_readyTime;
1686 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1687 ath_err(ath9k_hw_common(sc->sc_ah),
1688 "Unable to update hardware queue %u!\n", qnum);
1691 ath9k_hw_resettxqueue(ah, qnum);
1697 int ath_cabq_update(struct ath_softc *sc)
1699 struct ath9k_tx_queue_info qi;
1700 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
1701 int qnum = sc->beacon.cabq->axq_qnum;
1703 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1705 * Ensure the readytime % is within the bounds.
1707 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1708 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1709 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1710 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1712 qi.tqi_readyTime = (cur_conf->beacon_interval *
1713 sc->config.cabqReadytime) / 100;
1714 ath_txq_update(sc, qnum, &qi);
1719 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1720 struct list_head *list)
1722 struct ath_buf *bf, *lastbf;
1723 struct list_head bf_head;
1724 struct ath_tx_status ts;
1726 memset(&ts, 0, sizeof(ts));
1727 ts.ts_status = ATH9K_TX_FLUSH;
1728 INIT_LIST_HEAD(&bf_head);
1730 while (!list_empty(list)) {
1731 bf = list_first_entry(list, struct ath_buf, list);
1734 list_del(&bf->list);
1736 ath_tx_return_buffer(sc, bf);
1740 lastbf = bf->bf_lastbf;
1741 list_cut_position(&bf_head, list, &lastbf->list);
1742 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
1747 * Drain a given TX queue (could be Beacon or Data)
1749 * This assumes output has been stopped and
1750 * we do not need to block ath_tx_tasklet.
1752 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq)
1754 ath_txq_lock(sc, txq);
1756 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1757 int idx = txq->txq_tailidx;
1759 while (!list_empty(&txq->txq_fifo[idx])) {
1760 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]);
1762 INCR(idx, ATH_TXFIFO_DEPTH);
1764 txq->txq_tailidx = idx;
1767 txq->axq_link = NULL;
1768 txq->axq_tx_inprogress = false;
1769 ath_drain_txq_list(sc, txq, &txq->axq_q);
1771 ath_txq_unlock_complete(sc, txq);
1774 bool ath_drain_all_txq(struct ath_softc *sc)
1776 struct ath_hw *ah = sc->sc_ah;
1777 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1778 struct ath_txq *txq;
1782 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
1785 ath9k_hw_abort_tx_dma(ah);
1787 /* Check if any queue remains active */
1788 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1789 if (!ATH_TXQ_SETUP(sc, i))
1792 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1797 ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1799 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1800 if (!ATH_TXQ_SETUP(sc, i))
1804 * The caller will resume queues with ieee80211_wake_queues.
1805 * Mark the queue as not stopped to prevent ath_tx_complete
1806 * from waking the queue too early.
1808 txq = &sc->tx.txq[i];
1809 txq->stopped = false;
1810 ath_draintxq(sc, txq);
1816 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1818 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1819 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1822 /* For each axq_acq entry, for each tid, try to schedule packets
1823 * for transmit until ampdu_depth has reached min Q depth.
1825 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1827 struct ath_atx_ac *ac, *ac_tmp, *last_ac;
1828 struct ath_atx_tid *tid, *last_tid;
1830 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags) ||
1831 list_empty(&txq->axq_acq) ||
1832 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1837 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1838 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
1840 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1841 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1842 list_del(&ac->list);
1845 while (!list_empty(&ac->tid_q)) {
1846 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1848 list_del(&tid->list);
1854 ath_tx_sched_aggr(sc, txq, tid);
1857 * add tid to round-robin queue if more frames
1858 * are pending for the tid
1860 if (ath_tid_has_buffered(tid))
1861 ath_tx_queue_tid(txq, tid);
1863 if (tid == last_tid ||
1864 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1868 if (!list_empty(&ac->tid_q) && !ac->sched) {
1870 list_add_tail(&ac->list, &txq->axq_acq);
1873 if (ac == last_ac ||
1874 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1886 * Insert a chain of ath_buf (descriptors) on a txq and
1887 * assume the descriptors are already chained together by caller.
1889 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1890 struct list_head *head, bool internal)
1892 struct ath_hw *ah = sc->sc_ah;
1893 struct ath_common *common = ath9k_hw_common(ah);
1894 struct ath_buf *bf, *bf_last;
1895 bool puttxbuf = false;
1899 * Insert the frame on the outbound list and
1900 * pass it on to the hardware.
1903 if (list_empty(head))
1906 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1907 bf = list_first_entry(head, struct ath_buf, list);
1908 bf_last = list_entry(head->prev, struct ath_buf, list);
1910 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n",
1911 txq->axq_qnum, txq->axq_depth);
1913 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1914 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
1915 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1918 list_splice_tail_init(head, &txq->axq_q);
1920 if (txq->axq_link) {
1921 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
1922 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n",
1923 txq->axq_qnum, txq->axq_link,
1924 ito64(bf->bf_daddr), bf->bf_desc);
1928 txq->axq_link = bf_last->bf_desc;
1932 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1933 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1934 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n",
1935 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1939 TX_STAT_INC(txq->axq_qnum, txstart);
1940 ath9k_hw_txstart(ah, txq->axq_qnum);
1946 if (bf_is_ampdu_not_probing(bf))
1947 txq->axq_ampdu_depth++;
1949 bf = bf->bf_lastbf->bf_next;
1954 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1955 struct ath_atx_tid *tid, struct sk_buff *skb)
1957 struct ath_frame_info *fi = get_frame_info(skb);
1958 struct list_head bf_head;
1963 INIT_LIST_HEAD(&bf_head);
1964 list_add_tail(&bf->list, &bf_head);
1965 bf->bf_state.bf_type = 0;
1969 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
1970 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
1971 TX_STAT_INC(txq->axq_qnum, queued);
1974 static void setup_frame_info(struct ieee80211_hw *hw,
1975 struct ieee80211_sta *sta,
1976 struct sk_buff *skb,
1979 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1980 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1981 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1982 const struct ieee80211_rate *rate;
1983 struct ath_frame_info *fi = get_frame_info(skb);
1984 struct ath_node *an = NULL;
1985 enum ath9k_key_type keytype;
1986 bool short_preamble = false;
1989 * We check if Short Preamble is needed for the CTS rate by
1990 * checking the BSS's global flag.
1991 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1993 if (tx_info->control.vif &&
1994 tx_info->control.vif->bss_conf.use_short_preamble)
1995 short_preamble = true;
1997 rate = ieee80211_get_rts_cts_rate(hw, tx_info);
1998 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
2001 an = (struct ath_node *) sta->drv_priv;
2003 memset(fi, 0, sizeof(*fi));
2005 fi->keyix = hw_key->hw_key_idx;
2006 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
2007 fi->keyix = an->ps_key;
2009 fi->keyix = ATH9K_TXKEYIX_INVALID;
2010 fi->keytype = keytype;
2011 fi->framelen = framelen;
2012 fi->rtscts_rate = rate->hw_value;
2014 fi->rtscts_rate |= rate->hw_value_short;
2017 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
2019 struct ath_hw *ah = sc->sc_ah;
2020 struct ath9k_channel *curchan = ah->curchan;
2022 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) &&
2023 (curchan->channelFlags & CHANNEL_5GHZ) &&
2024 (chainmask == 0x7) && (rate < 0x90))
2026 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
2034 * Assign a descriptor (and sequence number if necessary,
2035 * and map buffer for DMA. Frees skb on error
2037 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
2038 struct ath_txq *txq,
2039 struct ath_atx_tid *tid,
2040 struct sk_buff *skb)
2042 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2043 struct ath_frame_info *fi = get_frame_info(skb);
2044 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2049 bf = ath_tx_get_buffer(sc);
2051 ath_dbg(common, XMIT, "TX buffers are full\n");
2055 ATH_TXBUF_RESET(bf);
2058 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
2059 seqno = tid->seq_next;
2060 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
2063 hdr->seq_ctrl |= cpu_to_le16(fragno);
2065 if (!ieee80211_has_morefrags(hdr->frame_control))
2066 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
2068 bf->bf_state.seqno = seqno;
2073 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
2074 skb->len, DMA_TO_DEVICE);
2075 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
2077 bf->bf_buf_addr = 0;
2078 ath_err(ath9k_hw_common(sc->sc_ah),
2079 "dma_mapping_error() on TX\n");
2080 ath_tx_return_buffer(sc, bf);
2089 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
2090 struct ath_tx_control *txctl)
2092 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2093 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2094 struct ieee80211_sta *sta = txctl->sta;
2095 struct ieee80211_vif *vif = info->control.vif;
2096 struct ath_softc *sc = hw->priv;
2097 int frmlen = skb->len + FCS_LEN;
2098 int padpos, padsize;
2100 /* NOTE: sta can be NULL according to net/mac80211.h */
2102 txctl->an = (struct ath_node *)sta->drv_priv;
2104 if (info->control.hw_key)
2105 frmlen += info->control.hw_key->icv_len;
2108 * As a temporary workaround, assign seq# here; this will likely need
2109 * to be cleaned up to work better with Beacon transmission and virtual
2112 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2113 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2114 sc->tx.seq_no += 0x10;
2115 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2116 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2119 if ((vif && vif->type != NL80211_IFTYPE_AP &&
2120 vif->type != NL80211_IFTYPE_AP_VLAN) ||
2121 !ieee80211_is_data(hdr->frame_control))
2122 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
2124 /* Add the padding after the header if this is not already done */
2125 padpos = ieee80211_hdrlen(hdr->frame_control);
2126 padsize = padpos & 3;
2127 if (padsize && skb->len > padpos) {
2128 if (skb_headroom(skb) < padsize)
2131 skb_push(skb, padsize);
2132 memmove(skb->data, skb->data + padsize, padpos);
2135 setup_frame_info(hw, sta, skb, frmlen);
2140 /* Upon failure caller should free skb */
2141 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
2142 struct ath_tx_control *txctl)
2144 struct ieee80211_hdr *hdr;
2145 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2146 struct ieee80211_sta *sta = txctl->sta;
2147 struct ieee80211_vif *vif = info->control.vif;
2148 struct ath_softc *sc = hw->priv;
2149 struct ath_txq *txq = txctl->txq;
2150 struct ath_atx_tid *tid = NULL;
2155 ret = ath_tx_prepare(hw, skb, txctl);
2159 hdr = (struct ieee80211_hdr *) skb->data;
2161 * At this point, the vif, hw_key and sta pointers in the tx control
2162 * info are no longer valid (overwritten by the ath_frame_info data.
2165 q = skb_get_queue_mapping(skb);
2167 ath_txq_lock(sc, txq);
2168 if (txq == sc->tx.txq_map[q] &&
2169 ++txq->pending_frames > sc->tx.txq_max_pending[q] &&
2171 ieee80211_stop_queue(sc->hw, q);
2172 txq->stopped = true;
2175 if (info->flags & IEEE80211_TX_CTL_PS_RESPONSE) {
2176 ath_txq_unlock(sc, txq);
2177 txq = sc->tx.uapsdq;
2178 ath_txq_lock(sc, txq);
2179 } else if (txctl->an &&
2180 ieee80211_is_data_present(hdr->frame_control)) {
2181 tid = ath_get_skb_tid(sc, txctl->an, skb);
2183 WARN_ON(tid->ac->txq != txctl->txq);
2185 if (info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
2186 tid->ac->clear_ps_filter = true;
2189 * Add this frame to software queue for scheduling later
2192 TX_STAT_INC(txq->axq_qnum, a_queued_sw);
2193 __skb_queue_tail(&tid->buf_q, skb);
2194 if (!txctl->an->sleeping)
2195 ath_tx_queue_tid(txq, tid);
2197 ath_txq_schedule(sc, txq);
2201 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
2203 ath_txq_skb_done(sc, txq, skb);
2205 dev_kfree_skb_any(skb);
2207 ieee80211_free_txskb(sc->hw, skb);
2211 bf->bf_state.bfs_paprd = txctl->paprd;
2214 bf->bf_state.bfs_paprd_timestamp = jiffies;
2216 ath_set_rates(vif, sta, bf);
2217 ath_tx_send_normal(sc, txq, tid, skb);
2220 ath_txq_unlock(sc, txq);
2225 void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2226 struct sk_buff *skb)
2228 struct ath_softc *sc = hw->priv;
2229 struct ath_tx_control txctl = {
2230 .txq = sc->beacon.cabq
2232 struct ath_tx_info info = {};
2233 struct ieee80211_hdr *hdr;
2234 struct ath_buf *bf_tail = NULL;
2241 sc->cur_beacon_conf.beacon_interval * 1000 *
2242 sc->cur_beacon_conf.dtim_period / ATH_BCBUF;
2245 struct ath_frame_info *fi = get_frame_info(skb);
2247 if (ath_tx_prepare(hw, skb, &txctl))
2250 bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb);
2255 ath_set_rates(vif, NULL, bf);
2256 ath_buf_set_rate(sc, bf, &info, fi->framelen, false);
2257 duration += info.rates[0].PktDuration;
2259 bf_tail->bf_next = bf;
2261 list_add_tail(&bf->list, &bf_q);
2265 if (duration > max_duration)
2268 skb = ieee80211_get_buffered_bc(hw, vif);
2272 ieee80211_free_txskb(hw, skb);
2274 if (list_empty(&bf_q))
2277 bf = list_first_entry(&bf_q, struct ath_buf, list);
2278 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
2280 if (hdr->frame_control & IEEE80211_FCTL_MOREDATA) {
2281 hdr->frame_control &= ~IEEE80211_FCTL_MOREDATA;
2282 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
2283 sizeof(*hdr), DMA_TO_DEVICE);
2286 ath_txq_lock(sc, txctl.txq);
2287 ath_tx_fill_desc(sc, bf, txctl.txq, 0);
2288 ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false);
2289 TX_STAT_INC(txctl.txq->axq_qnum, queued);
2290 ath_txq_unlock(sc, txctl.txq);
2297 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
2298 int tx_flags, struct ath_txq *txq)
2300 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2301 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2302 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
2303 int padpos, padsize;
2304 unsigned long flags;
2306 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
2308 if (sc->sc_ah->caldata)
2309 sc->sc_ah->caldata->paprd_packet_sent = true;
2311 if (!(tx_flags & ATH_TX_ERROR))
2312 /* Frame was ACKed */
2313 tx_info->flags |= IEEE80211_TX_STAT_ACK;
2315 padpos = ieee80211_hdrlen(hdr->frame_control);
2316 padsize = padpos & 3;
2317 if (padsize && skb->len>padpos+padsize) {
2319 * Remove MAC header padding before giving the frame back to
2322 memmove(skb->data + padsize, skb->data, padpos);
2323 skb_pull(skb, padsize);
2326 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2327 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
2328 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
2330 "Going back to sleep after having received TX status (0x%lx)\n",
2331 sc->ps_flags & (PS_WAIT_FOR_BEACON |
2333 PS_WAIT_FOR_PSPOLL_DATA |
2334 PS_WAIT_FOR_TX_ACK));
2336 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2338 __skb_queue_tail(&txq->complete_q, skb);
2339 ath_txq_skb_done(sc, txq, skb);
2342 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
2343 struct ath_txq *txq, struct list_head *bf_q,
2344 struct ath_tx_status *ts, int txok)
2346 struct sk_buff *skb = bf->bf_mpdu;
2347 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2348 unsigned long flags;
2352 tx_flags |= ATH_TX_ERROR;
2354 if (ts->ts_status & ATH9K_TXERR_FILT)
2355 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2357 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2358 bf->bf_buf_addr = 0;
2360 if (bf->bf_state.bfs_paprd) {
2361 if (time_after(jiffies,
2362 bf->bf_state.bfs_paprd_timestamp +
2363 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2364 dev_kfree_skb_any(skb);
2366 complete(&sc->paprd_complete);
2368 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2369 ath_tx_complete(sc, skb, tx_flags, txq);
2371 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2372 * accidentally reference it later.
2377 * Return the list of ath_buf of this mpdu to free queue
2379 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2380 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2381 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2384 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2385 struct ath_tx_status *ts, int nframes, int nbad,
2388 struct sk_buff *skb = bf->bf_mpdu;
2389 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2390 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2391 struct ieee80211_hw *hw = sc->hw;
2392 struct ath_hw *ah = sc->sc_ah;
2396 tx_info->status.ack_signal = ts->ts_rssi;
2398 tx_rateindex = ts->ts_rateindex;
2399 WARN_ON(tx_rateindex >= hw->max_rates);
2401 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2402 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2404 BUG_ON(nbad > nframes);
2406 tx_info->status.ampdu_len = nframes;
2407 tx_info->status.ampdu_ack_len = nframes - nbad;
2409 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2410 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2412 * If an underrun error is seen assume it as an excessive
2413 * retry only if max frame trigger level has been reached
2414 * (2 KB for single stream, and 4 KB for dual stream).
2415 * Adjust the long retry as if the frame was tried
2416 * hw->max_rate_tries times to affect how rate control updates
2417 * PER for the failed rate.
2418 * In case of congestion on the bus penalizing this type of
2419 * underruns should help hardware actually transmit new frames
2420 * successfully by eventually preferring slower rates.
2421 * This itself should also alleviate congestion on the bus.
2423 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2424 ATH9K_TX_DELIM_UNDERRUN)) &&
2425 ieee80211_is_data(hdr->frame_control) &&
2426 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2427 tx_info->status.rates[tx_rateindex].count =
2431 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2432 tx_info->status.rates[i].count = 0;
2433 tx_info->status.rates[i].idx = -1;
2436 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2439 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2441 struct ath_hw *ah = sc->sc_ah;
2442 struct ath_common *common = ath9k_hw_common(ah);
2443 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2444 struct list_head bf_head;
2445 struct ath_desc *ds;
2446 struct ath_tx_status ts;
2449 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n",
2450 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2453 ath_txq_lock(sc, txq);
2455 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
2458 if (list_empty(&txq->axq_q)) {
2459 txq->axq_link = NULL;
2460 ath_txq_schedule(sc, txq);
2463 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2466 * There is a race condition that a BH gets scheduled
2467 * after sw writes TxE and before hw re-load the last
2468 * descriptor to get the newly chained one.
2469 * Software must keep the last DONE descriptor as a
2470 * holding descriptor - software does so by marking
2471 * it with the STALE flag.
2476 if (list_is_last(&bf_held->list, &txq->axq_q))
2479 bf = list_entry(bf_held->list.next, struct ath_buf,
2483 lastbf = bf->bf_lastbf;
2484 ds = lastbf->bf_desc;
2486 memset(&ts, 0, sizeof(ts));
2487 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2488 if (status == -EINPROGRESS)
2491 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2494 * Remove ath_buf's of the same transmit unit from txq,
2495 * however leave the last descriptor back as the holding
2496 * descriptor for hw.
2498 lastbf->bf_stale = true;
2499 INIT_LIST_HEAD(&bf_head);
2500 if (!list_is_singular(&lastbf->list))
2501 list_cut_position(&bf_head,
2502 &txq->axq_q, lastbf->list.prev);
2505 list_del(&bf_held->list);
2506 ath_tx_return_buffer(sc, bf_held);
2509 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2511 ath_txq_unlock_complete(sc, txq);
2514 void ath_tx_tasklet(struct ath_softc *sc)
2516 struct ath_hw *ah = sc->sc_ah;
2517 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;
2520 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2521 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2522 ath_tx_processq(sc, &sc->tx.txq[i]);
2526 void ath_tx_edma_tasklet(struct ath_softc *sc)
2528 struct ath_tx_status ts;
2529 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2530 struct ath_hw *ah = sc->sc_ah;
2531 struct ath_txq *txq;
2532 struct ath_buf *bf, *lastbf;
2533 struct list_head bf_head;
2534 struct list_head *fifo_list;
2538 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
2541 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2542 if (status == -EINPROGRESS)
2544 if (status == -EIO) {
2545 ath_dbg(common, XMIT, "Error processing tx status\n");
2549 /* Process beacon completions separately */
2550 if (ts.qid == sc->beacon.beaconq) {
2551 sc->beacon.tx_processed = true;
2552 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2556 txq = &sc->tx.txq[ts.qid];
2558 ath_txq_lock(sc, txq);
2560 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2562 fifo_list = &txq->txq_fifo[txq->txq_tailidx];
2563 if (list_empty(fifo_list)) {
2564 ath_txq_unlock(sc, txq);
2568 bf = list_first_entry(fifo_list, struct ath_buf, list);
2570 list_del(&bf->list);
2571 ath_tx_return_buffer(sc, bf);
2572 bf = list_first_entry(fifo_list, struct ath_buf, list);
2575 lastbf = bf->bf_lastbf;
2577 INIT_LIST_HEAD(&bf_head);
2578 if (list_is_last(&lastbf->list, fifo_list)) {
2579 list_splice_tail_init(fifo_list, &bf_head);
2580 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2582 if (!list_empty(&txq->axq_q)) {
2583 struct list_head bf_q;
2585 INIT_LIST_HEAD(&bf_q);
2586 txq->axq_link = NULL;
2587 list_splice_tail_init(&txq->axq_q, &bf_q);
2588 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2591 lastbf->bf_stale = true;
2593 list_cut_position(&bf_head, fifo_list,
2597 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2598 ath_txq_unlock_complete(sc, txq);
2606 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2608 struct ath_descdma *dd = &sc->txsdma;
2609 u8 txs_len = sc->sc_ah->caps.txs_len;
2611 dd->dd_desc_len = size * txs_len;
2612 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
2613 &dd->dd_desc_paddr, GFP_KERNEL);
2620 static int ath_tx_edma_init(struct ath_softc *sc)
2624 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2626 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2627 sc->txsdma.dd_desc_paddr,
2628 ATH_TXSTATUS_RING_SIZE);
2633 int ath_tx_init(struct ath_softc *sc, int nbufs)
2635 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2638 spin_lock_init(&sc->tx.txbuflock);
2640 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2644 "Failed to allocate tx descriptors: %d\n", error);
2648 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2649 "beacon", ATH_BCBUF, 1, 1);
2652 "Failed to allocate beacon descriptors: %d\n", error);
2656 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2658 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2659 error = ath_tx_edma_init(sc);
2664 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2666 struct ath_atx_tid *tid;
2667 struct ath_atx_ac *ac;
2670 for (tidno = 0, tid = &an->tid[tidno];
2671 tidno < IEEE80211_NUM_TIDS;
2675 tid->seq_start = tid->seq_next = 0;
2676 tid->baw_size = WME_MAX_BA;
2677 tid->baw_head = tid->baw_tail = 0;
2679 tid->paused = false;
2680 tid->active = false;
2681 __skb_queue_head_init(&tid->buf_q);
2682 __skb_queue_head_init(&tid->retry_q);
2683 acno = TID_TO_WME_AC(tidno);
2684 tid->ac = &an->ac[acno];
2687 for (acno = 0, ac = &an->ac[acno];
2688 acno < IEEE80211_NUM_ACS; acno++, ac++) {
2690 ac->clear_ps_filter = true;
2691 ac->txq = sc->tx.txq_map[acno];
2692 INIT_LIST_HEAD(&ac->tid_q);
2696 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2698 struct ath_atx_ac *ac;
2699 struct ath_atx_tid *tid;
2700 struct ath_txq *txq;
2703 for (tidno = 0, tid = &an->tid[tidno];
2704 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
2709 ath_txq_lock(sc, txq);
2712 list_del(&tid->list);
2717 list_del(&ac->list);
2718 tid->ac->sched = false;
2721 ath_tid_drain(sc, txq, tid);
2722 tid->active = false;
2724 ath_txq_unlock(sc, txq);