Pileus Git - ~andy/linux/blob - drivers/net/wireless/ath/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "ath9k.h"
  21 #include "initvals.h"
  22
  23 static int btcoex_enable;
  24 module_param(btcoex_enable, bool, 0);
  25 MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
  26
  27 #define ATH9K_CLOCK_RATE_CCK            22
  28 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
  29 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
  30
  31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
  32 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
  33                               enum ath9k_ht_macmode macmode);
  34 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
  35                               struct ar5416_eeprom_def *pEepData,
  36                               u32 reg, u32 value);
  37 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
  38 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
  39
  40 /********************/
  41 /* Helper Functions */
  42 /********************/
  43
  44 static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
  45 {
  46         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  47
  48         if (!ah->curchan) /* should really check for CCK instead */
  49                 return clks / ATH9K_CLOCK_RATE_CCK;
  50         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  51                 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
  52
  53         return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
  54 }
  55
  56 static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
  57 {
  58         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  59
  60         if (conf_is_ht40(conf))
  61                 return ath9k_hw_mac_usec(ah, clks) / 2;
  62         else
  63                 return ath9k_hw_mac_usec(ah, clks);
  64 }
  65
  66 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
  67 {
  68         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  69
  70         if (!ah->curchan) /* should really check for CCK instead */
  71                 return usecs *ATH9K_CLOCK_RATE_CCK;
  72         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  73                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  74         return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
  75 }
  76
  77 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
  78 {
  79         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  80
  81         if (conf_is_ht40(conf))
  82                 return ath9k_hw_mac_clks(ah, usecs) * 2;
  83         else
  84                 return ath9k_hw_mac_clks(ah, usecs);
  85 }
  86
  87 /*
  88  * Read and write, they both share the same lock. We do this to serialize
  89  * reads and writes on Atheros 802.11n PCI devices only. This is required
  90  * as the FIFO on these devices can only accept sanely 2 requests. After
  91  * that the device goes bananas. Serializing the reads/writes prevents this
  92  * from happening.
  93  */
  94
  95 void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val)
  96 {
  97         if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
  98                 unsigned long flags;
  99                 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
 100                 iowrite32(val, ah->ah_sc->mem + reg_offset);
 101                 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
 102         } else
 103                 iowrite32(val, ah->ah_sc->mem + reg_offset);
 104 }
 105
 106 unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset)
 107 {
 108         u32 val;
 109         if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
 110                 unsigned long flags;
 111                 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
 112                 val = ioread32(ah->ah_sc->mem + reg_offset);
 113                 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
 114         } else
 115                 val = ioread32(ah->ah_sc->mem + reg_offset);
 116         return val;
 117 }
 118
 119 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
 120 {
 121         int i;
 122
 123         BUG_ON(timeout < AH_TIME_QUANTUM);
 124
 125         for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
 126                 if ((REG_READ(ah, reg) & mask) == val)
 127                         return true;
 128
 129                 udelay(AH_TIME_QUANTUM);
 130         }
 131
 132         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
 133                 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
 134                 timeout, reg, REG_READ(ah, reg), mask, val);
 135
 136         return false;
 137 }
 138
 139 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 140 {
 141         u32 retval;
 142         int i;
 143
 144         for (i = 0, retval = 0; i < n; i++) {
 145                 retval = (retval << 1) | (val & 1);
 146                 val >>= 1;
 147         }
 148         return retval;
 149 }
 150
 151 bool ath9k_get_channel_edges(struct ath_hw *ah,
 152                              u16 flags, u16 *low,
 153                              u16 *high)
 154 {
 155         struct ath9k_hw_capabilities *pCap = &ah->caps;
 156
 157         if (flags & CHANNEL_5GHZ) {
 158                 *low = pCap->low_5ghz_chan;
 159                 *high = pCap->high_5ghz_chan;
 160                 return true;
 161         }
 162         if ((flags & CHANNEL_2GHZ)) {
 163                 *low = pCap->low_2ghz_chan;
 164                 *high = pCap->high_2ghz_chan;
 165                 return true;
 166         }
 167         return false;
 168 }
 169
 170 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 171                            const struct ath_rate_table *rates,
 172                            u32 frameLen, u16 rateix,
 173                            bool shortPreamble)
 174 {
 175         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 176         u32 kbps;
 177
 178         kbps = rates->info[rateix].ratekbps;
 179
 180         if (kbps == 0)
 181                 return 0;
 182
 183         switch (rates->info[rateix].phy) {
 184         case WLAN_RC_PHY_CCK:
 185                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 186                 if (shortPreamble && rates->info[rateix].short_preamble)
 187                         phyTime >>= 1;
 188                 numBits = frameLen << 3;
 189                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 190                 break;
 191         case WLAN_RC_PHY_OFDM:
 192                 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
 193                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 194                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 195                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 196                         txTime = OFDM_SIFS_TIME_QUARTER
 197                                 + OFDM_PREAMBLE_TIME_QUARTER
 198                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 199                 } else if (ah->curchan &&
 200                            IS_CHAN_HALF_RATE(ah->curchan)) {
 201                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 202                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 203                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 204                         txTime = OFDM_SIFS_TIME_HALF +
 205                                 OFDM_PREAMBLE_TIME_HALF
 206                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 207                 } else {
 208                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 209                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 210                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 211                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 212                                 + (numSymbols * OFDM_SYMBOL_TIME);
 213                 }
 214                 break;
 215         default:
 216                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 217                         "Unknown phy %u (rate ix %u)\n",
 218                         rates->info[rateix].phy, rateix);
 219                 txTime = 0;
 220                 break;
 221         }
 222
 223         return txTime;
 224 }
 225
 226 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 227                                   struct ath9k_channel *chan,
 228                                   struct chan_centers *centers)
 229 {
 230         int8_t extoff;
 231
 232         if (!IS_CHAN_HT40(chan)) {
 233                 centers->ctl_center = centers->ext_center =
 234                         centers->synth_center = chan->channel;
 235                 return;
 236         }
 237
 238         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 239             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 240                 centers->synth_center =
 241                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 242                 extoff = 1;
 243         } else {
 244                 centers->synth_center =
 245                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 246                 extoff = -1;
 247         }
 248
 249         centers->ctl_center =
 250                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 251         centers->ext_center =
 252                 centers->synth_center + (extoff *
 253                          ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
 254                           HT40_CHANNEL_CENTER_SHIFT : 15));
 255 }
 256
 257 /******************/
 258 /* Chip Revisions */
 259 /******************/
 260
 261 static void ath9k_hw_read_revisions(struct ath_hw *ah)
 262 {
 263         u32 val;
 264
 265         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 266
 267         if (val == 0xFF) {
 268                 val = REG_READ(ah, AR_SREV);
 269                 ah->hw_version.macVersion =
 270                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 271                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
 272                 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 273         } else {
 274                 if (!AR_SREV_9100(ah))
 275                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
 276
 277                 ah->hw_version.macRev = val & AR_SREV_REVISION;
 278
 279                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
 280                         ah->is_pciexpress = true;
 281         }
 282 }
 283
 284 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
 285 {
 286         u32 val;
 287         int i;
 288
 289         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 290
 291         for (i = 0; i < 8; i++)
 292                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 293         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 294         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 295
 296         return ath9k_hw_reverse_bits(val, 8);
 297 }
 298
 299 /************************************/
 300 /* HW Attach, Detach, Init Routines */
 301 /************************************/
 302
 303 static void ath9k_hw_disablepcie(struct ath_hw *ah)
 304 {
 305         if (AR_SREV_9100(ah))
 306                 return;
 307
 308         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 309         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 310         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 311         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 312         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 313         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 314         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 315         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 316         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 317
 318         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 319 }
 320
 321 static bool ath9k_hw_chip_test(struct ath_hw *ah)
 322 {
 323         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
 324         u32 regHold[2];
 325         u32 patternData[4] = { 0x55555555,
 326                                0xaaaaaaaa,
 327                                0x66666666,
 328                                0x99999999 };
 329         int i, j;
 330
 331         for (i = 0; i < 2; i++) {
 332                 u32 addr = regAddr[i];
 333                 u32 wrData, rdData;
 334
 335                 regHold[i] = REG_READ(ah, addr);
 336                 for (j = 0; j < 0x100; j++) {
 337                         wrData = (j << 16) | j;
 338                         REG_WRITE(ah, addr, wrData);
 339                         rdData = REG_READ(ah, addr);
 340                         if (rdData != wrData) {
 341                                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 342                                         "address test failed "
 343                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 344                                         addr, wrData, rdData);
 345                                 return false;
 346                         }
 347                 }
 348                 for (j = 0; j < 4; j++) {
 349                         wrData = patternData[j];
 350                         REG_WRITE(ah, addr, wrData);
 351                         rdData = REG_READ(ah, addr);
 352                         if (wrData != rdData) {
 353                                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 354                                         "address test failed "
 355                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 356                                         addr, wrData, rdData);
 357                                 return false;
 358                         }
 359                 }
 360                 REG_WRITE(ah, regAddr[i], regHold[i]);
 361         }
 362         udelay(100);
 363
 364         return true;
 365 }
 366
 367 static const char *ath9k_hw_devname(u16 devid)
 368 {
 369         switch (devid) {
 370         case AR5416_DEVID_PCI:
 371                 return "Atheros 5416";
 372         case AR5416_DEVID_PCIE:
 373                 return "Atheros 5418";
 374         case AR9160_DEVID_PCI:
 375                 return "Atheros 9160";
 376         case AR5416_AR9100_DEVID:
 377                 return "Atheros 9100";
 378         case AR9280_DEVID_PCI:
 379         case AR9280_DEVID_PCIE:
 380                 return "Atheros 9280";
 381         case AR9285_DEVID_PCIE:
 382                 return "Atheros 9285";
 383         case AR5416_DEVID_AR9287_PCI:
 384         case AR5416_DEVID_AR9287_PCIE:
 385                 return "Atheros 9287";
 386         }
 387
 388         return NULL;
 389 }
 390
 391 static void ath9k_hw_set_defaults(struct ath_hw *ah)
 392 {
 393         int i;
 394
 395         ah->config.dma_beacon_response_time = 2;
 396         ah->config.sw_beacon_response_time = 10;
 397         ah->config.additional_swba_backoff = 0;
 398         ah->config.ack_6mb = 0x0;
 399         ah->config.cwm_ignore_extcca = 0;
 400         ah->config.pcie_powersave_enable = 0;
 401         ah->config.pcie_clock_req = 0;
 402         ah->config.pcie_waen = 0;
 403         ah->config.analog_shiftreg = 1;
 404         ah->config.ht_enable = 1;
 405         ah->config.ofdm_trig_low = 200;
 406         ah->config.ofdm_trig_high = 500;
 407         ah->config.cck_trig_high = 200;
 408         ah->config.cck_trig_low = 100;
 409         ah->config.enable_ani = 1;
 410         ah->config.diversity_control = 0;
 411         ah->config.antenna_switch_swap = 0;
 412
 413         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 414                 ah->config.spurchans[i][0] = AR_NO_SPUR;
 415                 ah->config.spurchans[i][1] = AR_NO_SPUR;
 416         }
 417
 418         ah->config.intr_mitigation = true;
 419
 420         /*
 421          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
 422          * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
 423          * This means we use it for all AR5416 devices, and the few
 424          * minor PCI AR9280 devices out there.
 425          *
 426          * Serialization is required because these devices do not handle
 427          * well the case of two concurrent reads/writes due to the latency
 428          * involved. During one read/write another read/write can be issued
 429          * on another CPU while the previous read/write may still be working
 430          * on our hardware, if we hit this case the hardware poops in a loop.
 431          * We prevent this by serializing reads and writes.
 432          *
 433          * This issue is not present on PCI-Express devices or pre-AR5416
 434          * devices (legacy, 802.11abg).
 435          */
 436         if (num_possible_cpus() > 1)
 437                 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
 438 }
 439
 440 static struct ath_hw *ath9k_hw_newstate(u16 devid, struct ath_softc *sc,
 441                                         int *status)
 442 {
 443         struct ath_hw *ah;
 444
 445         ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
 446         if (ah == NULL) {
 447                 DPRINTF(sc, ATH_DBG_FATAL,
 448                         "Cannot allocate memory for state block\n");
 449                 *status = -ENOMEM;
 450                 return NULL;
 451         }
 452
 453         ah->ah_sc = sc;
 454         ah->hw_version.magic = AR5416_MAGIC;
 455         ah->regulatory.country_code = CTRY_DEFAULT;
 456         ah->hw_version.devid = devid;
 457         ah->hw_version.subvendorid = 0;
 458
 459         ah->ah_flags = 0;
 460         if ((devid == AR5416_AR9100_DEVID))
 461                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
 462         if (!AR_SREV_9100(ah))
 463                 ah->ah_flags = AH_USE_EEPROM;
 464
 465         ah->regulatory.power_limit = MAX_RATE_POWER;
 466         ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX;
 467         ah->atim_window = 0;
 468         ah->diversity_control = ah->config.diversity_control;
 469         ah->antenna_switch_swap =
 470                 ah->config.antenna_switch_swap;
 471         ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 472         ah->beacon_interval = 100;
 473         ah->enable_32kHz_clock = DONT_USE_32KHZ;
 474         ah->slottime = (u32) -1;
 475         ah->acktimeout = (u32) -1;
 476         ah->ctstimeout = (u32) -1;
 477         ah->globaltxtimeout = (u32) -1;
 478
 479         ah->gbeacon_rate = 0;
 480
 481         return ah;
 482 }
 483
 484 static int ath9k_hw_rfattach(struct ath_hw *ah)
 485 {
 486         bool rfStatus = false;
 487         int ecode = 0;
 488
 489         rfStatus = ath9k_hw_init_rf(ah, &ecode);
 490         if (!rfStatus) {
 491                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 492                         "RF setup failed, status: %u\n", ecode);
 493                 return ecode;
 494         }
 495
 496         return 0;
 497 }
 498
 499 static int ath9k_hw_rf_claim(struct ath_hw *ah)
 500 {
 501         u32 val;
 502
 503         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 504
 505         val = ath9k_hw_get_radiorev(ah);
 506         switch (val & AR_RADIO_SREV_MAJOR) {
 507         case 0:
 508                 val = AR_RAD5133_SREV_MAJOR;
 509                 break;
 510         case AR_RAD5133_SREV_MAJOR:
 511         case AR_RAD5122_SREV_MAJOR:
 512         case AR_RAD2133_SREV_MAJOR:
 513         case AR_RAD2122_SREV_MAJOR:
 514                 break;
 515         default:
 516                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 517                         "Radio Chip Rev 0x%02X not supported\n",
 518                         val & AR_RADIO_SREV_MAJOR);
 519                 return -EOPNOTSUPP;
 520         }
 521
 522         ah->hw_version.analog5GhzRev = val;
 523
 524         return 0;
 525 }
 526
 527 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
 528 {
 529         u32 sum;
 530         int i;
 531         u16 eeval;
 532
 533         sum = 0;
 534         for (i = 0; i < 3; i++) {
 535                 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
 536                 sum += eeval;
 537                 ah->macaddr[2 * i] = eeval >> 8;
 538                 ah->macaddr[2 * i + 1] = eeval & 0xff;
 539         }
 540         if (sum == 0 || sum == 0xffff * 3)
 541                 return -EADDRNOTAVAIL;
 542
 543         return 0;
 544 }
 545
 546 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
 547 {
 548         u32 rxgain_type;
 549
 550         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
 551                 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
 552
 553                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 554                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 555                         ar9280Modes_backoff_13db_rxgain_9280_2,
 556                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
 557                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 558                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 559                         ar9280Modes_backoff_23db_rxgain_9280_2,
 560                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
 561                 else
 562                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 563                         ar9280Modes_original_rxgain_9280_2,
 564                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 565         } else {
 566                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 567                         ar9280Modes_original_rxgain_9280_2,
 568                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 569         }
 570 }
 571
 572 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
 573 {
 574         u32 txgain_type;
 575
 576         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
 577                 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 578
 579                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 580                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 581                         ar9280Modes_high_power_tx_gain_9280_2,
 582                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
 583                 else
 584                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 585                         ar9280Modes_original_tx_gain_9280_2,
 586                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 587         } else {
 588                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 589                 ar9280Modes_original_tx_gain_9280_2,
 590                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 591         }
 592 }
 593
 594 static int ath9k_hw_post_attach(struct ath_hw *ah)
 595 {
 596         int ecode;
 597
 598         if (!ath9k_hw_chip_test(ah))
 599                 return -ENODEV;
 600
 601         ecode = ath9k_hw_rf_claim(ah);
 602         if (ecode != 0)
 603                 return ecode;
 604
 605         ecode = ath9k_hw_eeprom_attach(ah);
 606         if (ecode != 0)
 607                 return ecode;
 608
 609         DPRINTF(ah->ah_sc, ATH_DBG_CONFIG, "Eeprom VER: %d, REV: %d\n",
 610                 ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah));
 611
 612         ecode = ath9k_hw_rfattach(ah);
 613         if (ecode != 0)
 614                 return ecode;
 615
 616         if (!AR_SREV_9100(ah)) {
 617                 ath9k_hw_ani_setup(ah);
 618                 ath9k_hw_ani_attach(ah);
 619         }
 620
 621         return 0;
 622 }
 623
 624 static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
 625                                          int *status)
 626 {
 627         struct ath_hw *ah;
 628         int ecode;
 629         u32 i, j;
 630
 631         ah = ath9k_hw_newstate(devid, sc, status);
 632         if (ah == NULL)
 633                 return NULL;
 634
 635         ath9k_hw_set_defaults(ah);
 636
 637         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 638                 DPRINTF(sc, ATH_DBG_FATAL, "Couldn't reset chip\n");
 639                 ecode = -EIO;
 640                 goto bad;
 641         }
 642
 643         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 644                 DPRINTF(sc, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
 645                 ecode = -EIO;
 646                 goto bad;
 647         }
 648
 649         if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
 650                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
 651                     (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
 652                         ah->config.serialize_regmode =
 653                                 SER_REG_MODE_ON;
 654                 } else {
 655                         ah->config.serialize_regmode =
 656                                 SER_REG_MODE_OFF;
 657                 }
 658         }
 659
 660         DPRINTF(sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
 661                 ah->config.serialize_regmode);
 662
 663         if ((ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCI) &&
 664             (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) &&
 665             (ah->hw_version.macVersion != AR_SREV_VERSION_9160) &&
 666             (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) &&
 667             (!AR_SREV_9285(ah)) && (!AR_SREV_9287(ah))) {
 668                 DPRINTF(sc, ATH_DBG_FATAL,
 669                         "Mac Chip Rev 0x%02x.%x is not supported by "
 670                         "this driver\n", ah->hw_version.macVersion,
 671                         ah->hw_version.macRev);
 672                 ecode = -EOPNOTSUPP;
 673                 goto bad;
 674         }
 675
 676         if (AR_SREV_9100(ah)) {
 677                 ah->iq_caldata.calData = &iq_cal_multi_sample;
 678                 ah->supp_cals = IQ_MISMATCH_CAL;
 679                 ah->is_pciexpress = false;
 680         }
 681         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 682
 683         if (AR_SREV_9160_10_OR_LATER(ah)) {
 684                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 685                         ah->iq_caldata.calData = &iq_cal_single_sample;
 686                         ah->adcgain_caldata.calData =
 687                                 &adc_gain_cal_single_sample;
 688                         ah->adcdc_caldata.calData =
 689                                 &adc_dc_cal_single_sample;
 690                         ah->adcdc_calinitdata.calData =
 691                                 &adc_init_dc_cal;
 692                 } else {
 693                         ah->iq_caldata.calData = &iq_cal_multi_sample;
 694                         ah->adcgain_caldata.calData =
 695                                 &adc_gain_cal_multi_sample;
 696                         ah->adcdc_caldata.calData =
 697                                 &adc_dc_cal_multi_sample;
 698                         ah->adcdc_calinitdata.calData =
 699                                 &adc_init_dc_cal;
 700                 }
 701                 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
 702         }
 703
 704         ah->ani_function = ATH9K_ANI_ALL;
 705         if (AR_SREV_9280_10_OR_LATER(ah))
 706                 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 707         if (AR_SREV_9287_11_OR_LATER(ah)) {
 708                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
 709                                 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
 710                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
 711                                 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
 712                 if (ah->config.pcie_clock_req)
 713                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 714                         ar9287PciePhy_clkreq_off_L1_9287_1_1,
 715                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
 716                 else
 717                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 718                         ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
 719                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
 720                                         2);
 721         } else if (AR_SREV_9287_10_OR_LATER(ah)) {
 722                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
 723                                 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
 724                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
 725                                 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
 726
 727                 if (ah->config.pcie_clock_req)
 728                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 729                         ar9287PciePhy_clkreq_off_L1_9287_1_0,
 730                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
 731                 else
 732                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 733                         ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
 734                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
 735                                   2);
 736         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 737
 738
 739                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
 740                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
 741                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
 742                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
 743
 744                 if (ah->config.pcie_clock_req) {
 745                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 746                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
 747                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
 748                 } else {
 749                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 750                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
 751                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
 752                                   2);
 753                 }
 754         } else if (AR_SREV_9285_10_OR_LATER(ah)) {
 755                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
 756                                ARRAY_SIZE(ar9285Modes_9285), 6);
 757                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
 758                                ARRAY_SIZE(ar9285Common_9285), 2);
 759
 760                 if (ah->config.pcie_clock_req) {
 761                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 762                         ar9285PciePhy_clkreq_off_L1_9285,
 763                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
 764                 } else {
 765                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 766                         ar9285PciePhy_clkreq_always_on_L1_9285,
 767                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
 768                 }
 769         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
 770                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
 771                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
 772                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
 773                                ARRAY_SIZE(ar9280Common_9280_2), 2);
 774
 775                 if (ah->config.pcie_clock_req) {
 776                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 777                                ar9280PciePhy_clkreq_off_L1_9280,
 778                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
 779                 } else {
 780                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 781                                ar9280PciePhy_clkreq_always_on_L1_9280,
 782                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
 783                 }
 784                 INIT_INI_ARRAY(&ah->iniModesAdditional,
 785                                ar9280Modes_fast_clock_9280_2,
 786                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
 787         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
 788                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
 789                                ARRAY_SIZE(ar9280Modes_9280), 6);
 790                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
 791                                ARRAY_SIZE(ar9280Common_9280), 2);
 792         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 793                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
 794                                ARRAY_SIZE(ar5416Modes_9160), 6);
 795                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
 796                                ARRAY_SIZE(ar5416Common_9160), 2);
 797                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
 798                                ARRAY_SIZE(ar5416Bank0_9160), 2);
 799                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
 800                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
 801                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
 802                                ARRAY_SIZE(ar5416Bank1_9160), 2);
 803                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
 804                                ARRAY_SIZE(ar5416Bank2_9160), 2);
 805                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
 806                                ARRAY_SIZE(ar5416Bank3_9160), 3);
 807                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
 808                                ARRAY_SIZE(ar5416Bank6_9160), 3);
 809                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
 810                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
 811                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
 812                                ARRAY_SIZE(ar5416Bank7_9160), 2);
 813                 if (AR_SREV_9160_11(ah)) {
 814                         INIT_INI_ARRAY(&ah->iniAddac,
 815                                        ar5416Addac_91601_1,
 816                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
 817                 } else {
 818                         INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
 819                                        ARRAY_SIZE(ar5416Addac_9160), 2);
 820                 }
 821         } else if (AR_SREV_9100_OR_LATER(ah)) {
 822                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
 823                                ARRAY_SIZE(ar5416Modes_9100), 6);
 824                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
 825                                ARRAY_SIZE(ar5416Common_9100), 2);
 826                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
 827                                ARRAY_SIZE(ar5416Bank0_9100), 2);
 828                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
 829                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
 830                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
 831                                ARRAY_SIZE(ar5416Bank1_9100), 2);
 832                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
 833                                ARRAY_SIZE(ar5416Bank2_9100), 2);
 834                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
 835                                ARRAY_SIZE(ar5416Bank3_9100), 3);
 836                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
 837                                ARRAY_SIZE(ar5416Bank6_9100), 3);
 838                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
 839                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 840                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
 841                                ARRAY_SIZE(ar5416Bank7_9100), 2);
 842                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
 843                                ARRAY_SIZE(ar5416Addac_9100), 2);
 844         } else {
 845                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
 846                                ARRAY_SIZE(ar5416Modes), 6);
 847                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
 848                                ARRAY_SIZE(ar5416Common), 2);
 849                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
 850                                ARRAY_SIZE(ar5416Bank0), 2);
 851                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
 852                                ARRAY_SIZE(ar5416BB_RfGain), 3);
 853                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
 854                                ARRAY_SIZE(ar5416Bank1), 2);
 855                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
 856                                ARRAY_SIZE(ar5416Bank2), 2);
 857                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
 858                                ARRAY_SIZE(ar5416Bank3), 3);
 859                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
 860                                ARRAY_SIZE(ar5416Bank6), 3);
 861                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
 862                                ARRAY_SIZE(ar5416Bank6TPC), 3);
 863                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
 864                                ARRAY_SIZE(ar5416Bank7), 2);
 865                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
 866                                ARRAY_SIZE(ar5416Addac), 2);
 867         }
 868
 869         if (ah->is_pciexpress)
 870                 ath9k_hw_configpcipowersave(ah, 0);
 871         else
 872                 ath9k_hw_disablepcie(ah);
 873
 874         ecode = ath9k_hw_post_attach(ah);
 875         if (ecode != 0)
 876                 goto bad;
 877
 878         if (AR_SREV_9287_11(ah))
 879                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 880                 ar9287Modes_rx_gain_9287_1_1,
 881                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
 882         else if (AR_SREV_9287_10(ah))
 883                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 884                 ar9287Modes_rx_gain_9287_1_0,
 885                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
 886         else if (AR_SREV_9280_20(ah))
 887                 ath9k_hw_init_rxgain_ini(ah);
 888
 889         if (AR_SREV_9287_11(ah)) {
 890                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 891                 ar9287Modes_tx_gain_9287_1_1,
 892                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
 893         } else if (AR_SREV_9287_10(ah)) {
 894                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 895                 ar9287Modes_tx_gain_9287_1_0,
 896                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
 897         } else if (AR_SREV_9280_20(ah)) {
 898                 ath9k_hw_init_txgain_ini(ah);
 899         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 900                 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 901
 902                 /* txgain table */
 903                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
 904                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 905                         ar9285Modes_high_power_tx_gain_9285_1_2,
 906                         ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
 907                 } else {
 908                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 909                         ar9285Modes_original_tx_gain_9285_1_2,
 910                         ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
 911                 }
 912
 913         }
 914
 915         ath9k_hw_fill_cap_info(ah);
 916
 917         if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
 918             test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
 919
 920                 /* EEPROM Fixup */
 921                 for (i = 0; i < ah->iniModes.ia_rows; i++) {
 922                         u32 reg = INI_RA(&ah->iniModes, i, 0);
 923
 924                         for (j = 1; j < ah->iniModes.ia_columns; j++) {
 925                                 u32 val = INI_RA(&ah->iniModes, i, j);
 926
 927                                 INI_RA(&ah->iniModes, i, j) =
 928                                         ath9k_hw_ini_fixup(ah,
 929                                                            &ah->eeprom.def,
 930                                                            reg, val);
 931                         }
 932                 }
 933         }
 934
 935         ecode = ath9k_hw_init_macaddr(ah);
 936         if (ecode != 0) {
 937                 DPRINTF(sc, ATH_DBG_FATAL,
 938                         "Failed to initialize MAC address\n");
 939                 goto bad;
 940         }
 941
 942         if (AR_SREV_9285(ah))
 943                 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
 944         else
 945                 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
 946
 947         ath9k_init_nfcal_hist_buffer(ah);
 948
 949         return ah;
 950 bad:
 951         if (ah)
 952                 ath9k_hw_detach(ah);
 953         if (status)
 954                 *status = ecode;
 955
 956         return NULL;
 957 }
 958
 959 static void ath9k_hw_init_bb(struct ath_hw *ah,
 960                              struct ath9k_channel *chan)
 961 {
 962         u32 synthDelay;
 963
 964         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 965         if (IS_CHAN_B(chan))
 966                 synthDelay = (4 * synthDelay) / 22;
 967         else
 968                 synthDelay /= 10;
 969
 970         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 971
 972         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 973 }
 974
 975 static void ath9k_hw_init_qos(struct ath_hw *ah)
 976 {
 977         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
 978         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
 979
 980         REG_WRITE(ah, AR_QOS_NO_ACK,
 981                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
 982                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
 983                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
 984
 985         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
 986         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
 987         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
 988         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
 989         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 990 }
 991
 992 static void ath9k_hw_init_pll(struct ath_hw *ah,
 993                               struct ath9k_channel *chan)
 994 {
 995         u32 pll;
 996
 997         if (AR_SREV_9100(ah)) {
 998                 if (chan && IS_CHAN_5GHZ(chan))
 999                         pll = 0x1450;
1000                 else
1001                         pll = 0x1458;
1002         } else {
1003                 if (AR_SREV_9280_10_OR_LATER(ah)) {
1004                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1005
1006                         if (chan && IS_CHAN_HALF_RATE(chan))
1007                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1008                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1009                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1010
1011                         if (chan && IS_CHAN_5GHZ(chan)) {
1012                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1013
1014
1015                                 if (AR_SREV_9280_20(ah)) {
1016                                         if (((chan->channel % 20) == 0)
1017                                             || ((chan->channel % 10) == 0))
1018                                                 pll = 0x2850;
1019                                         else
1020                                                 pll = 0x142c;
1021                                 }
1022                         } else {
1023                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1024                         }
1025
1026                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1027
1028                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1029
1030                         if (chan && IS_CHAN_HALF_RATE(chan))
1031                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1032                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1033                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1034
1035                         if (chan && IS_CHAN_5GHZ(chan))
1036                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1037                         else
1038                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1039                 } else {
1040                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1041
1042                         if (chan && IS_CHAN_HALF_RATE(chan))
1043                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1044                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1045                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1046
1047                         if (chan && IS_CHAN_5GHZ(chan))
1048                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
1049                         else
1050                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
1051                 }
1052         }
1053         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1054
1055         udelay(RTC_PLL_SETTLE_DELAY);
1056
1057         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1058 }
1059
1060 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1061 {
1062         int rx_chainmask, tx_chainmask;
1063
1064         rx_chainmask = ah->rxchainmask;
1065         tx_chainmask = ah->txchainmask;
1066
1067         switch (rx_chainmask) {
1068         case 0x5:
1069                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1070                             AR_PHY_SWAP_ALT_CHAIN);
1071         case 0x3:
1072                 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
1073                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1074                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1075                         break;
1076                 }
1077         case 0x1:
1078         case 0x2:
1079         case 0x7:
1080                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1081                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1082                 break;
1083         default:
1084                 break;
1085         }
1086
1087         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1088         if (tx_chainmask == 0x5) {
1089                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1090                             AR_PHY_SWAP_ALT_CHAIN);
1091         }
1092         if (AR_SREV_9100(ah))
1093                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1094                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1095 }
1096
1097 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1098                                           enum nl80211_iftype opmode)
1099 {
1100         ah->mask_reg = AR_IMR_TXERR |
1101                 AR_IMR_TXURN |
1102                 AR_IMR_RXERR |
1103                 AR_IMR_RXORN |
1104                 AR_IMR_BCNMISC;
1105
1106         if (ah->config.intr_mitigation)
1107                 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1108         else
1109                 ah->mask_reg |= AR_IMR_RXOK;
1110
1111         ah->mask_reg |= AR_IMR_TXOK;
1112
1113         if (opmode == NL80211_IFTYPE_AP)
1114                 ah->mask_reg |= AR_IMR_MIB;
1115
1116         REG_WRITE(ah, AR_IMR, ah->mask_reg);
1117         REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1118
1119         if (!AR_SREV_9100(ah)) {
1120                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1121                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1122                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1123         }
1124 }
1125
1126 static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1127 {
1128         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1129                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1130                 ah->acktimeout = (u32) -1;
1131                 return false;
1132         } else {
1133                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1134                               AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1135                 ah->acktimeout = us;
1136                 return true;
1137         }
1138 }
1139
1140 static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1141 {
1142         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1143                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1144                 ah->ctstimeout = (u32) -1;
1145                 return false;
1146         } else {
1147                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1148                               AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1149                 ah->ctstimeout = us;
1150                 return true;
1151         }
1152 }
1153
1154 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1155 {
1156         if (tu > 0xFFFF) {
1157                 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1158                         "bad global tx timeout %u\n", tu);
1159                 ah->globaltxtimeout = (u32) -1;
1160                 return false;
1161         } else {
1162                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1163                 ah->globaltxtimeout = tu;
1164                 return true;
1165         }
1166 }
1167
1168 static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1169 {
1170         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1171                 ah->misc_mode);
1172
1173         if (ah->misc_mode != 0)
1174                 REG_WRITE(ah, AR_PCU_MISC,
1175                           REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1176         if (ah->slottime != (u32) -1)
1177                 ath9k_hw_setslottime(ah, ah->slottime);
1178         if (ah->acktimeout != (u32) -1)
1179                 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1180         if (ah->ctstimeout != (u32) -1)
1181                 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1182         if (ah->globaltxtimeout != (u32) -1)
1183                 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1184 }
1185
1186 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1187 {
1188         return vendorid == ATHEROS_VENDOR_ID ?
1189                 ath9k_hw_devname(devid) : NULL;
1190 }
1191
1192 void ath9k_hw_detach(struct ath_hw *ah)
1193 {
1194         if (!AR_SREV_9100(ah))
1195                 ath9k_hw_ani_detach(ah);
1196
1197         ath9k_hw_rfdetach(ah);
1198         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1199         kfree(ah);
1200 }
1201
1202 struct ath_hw *ath9k_hw_attach(u16 devid, struct ath_softc *sc, int *error)
1203 {
1204         struct ath_hw *ah = NULL;
1205
1206         switch (devid) {
1207         case AR5416_DEVID_PCI:
1208         case AR5416_DEVID_PCIE:
1209         case AR5416_AR9100_DEVID:
1210         case AR9160_DEVID_PCI:
1211         case AR9280_DEVID_PCI:
1212         case AR9280_DEVID_PCIE:
1213         case AR9285_DEVID_PCIE:
1214         case AR5416_DEVID_AR9287_PCI:
1215         case AR5416_DEVID_AR9287_PCIE:
1216                 ah = ath9k_hw_do_attach(devid, sc, error);
1217                 break;
1218         default:
1219                 *error = -ENXIO;
1220                 break;
1221         }
1222
1223         return ah;
1224 }
1225
1226 /*******/
1227 /* INI */
1228 /*******/
1229
1230 static void ath9k_hw_override_ini(struct ath_hw *ah,
1231                                   struct ath9k_channel *chan)
1232 {
1233         /*
1234          * Set the RX_ABORT and RX_DIS and clear if off only after
1235          * RXE is set for MAC. This prevents frames with corrupted
1236          * descriptor status.
1237          */
1238         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1239
1240
1241         if (!AR_SREV_5416_20_OR_LATER(ah) ||
1242             AR_SREV_9280_10_OR_LATER(ah))
1243                 return;
1244
1245         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1246 }
1247
1248 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1249                               struct ar5416_eeprom_def *pEepData,
1250                               u32 reg, u32 value)
1251 {
1252         struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1253
1254         switch (ah->hw_version.devid) {
1255         case AR9280_DEVID_PCI:
1256                 if (reg == 0x7894) {
1257                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1258                                 "ini VAL: %x  EEPROM: %x\n", value,
1259                                 (pBase->version & 0xff));
1260
1261                         if ((pBase->version & 0xff) > 0x0a) {
1262                                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1263                                         "PWDCLKIND: %d\n",
1264                                         pBase->pwdclkind);
1265                                 value &= ~AR_AN_TOP2_PWDCLKIND;
1266                                 value |= AR_AN_TOP2_PWDCLKIND &
1267                                         (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1268                         } else {
1269                                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1270                                         "PWDCLKIND Earlier Rev\n");
1271                         }
1272
1273                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1274                                 "final ini VAL: %x\n", value);
1275                 }
1276                 break;
1277         }
1278
1279         return value;
1280 }
1281
1282 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1283                               struct ar5416_eeprom_def *pEepData,
1284                               u32 reg, u32 value)
1285 {
1286         if (ah->eep_map == EEP_MAP_4KBITS)
1287                 return value;
1288         else
1289                 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1290 }
1291
1292 static void ath9k_olc_init(struct ath_hw *ah)
1293 {
1294         u32 i;
1295
1296         for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1297                 ah->originalGain[i] =
1298                         MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1299                                         AR_PHY_TX_GAIN);
1300         ah->PDADCdelta = 0;
1301 }
1302
1303 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1304                               struct ath9k_channel *chan)
1305 {
1306         u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1307
1308         if (IS_CHAN_B(chan))
1309                 ctl |= CTL_11B;
1310         else if (IS_CHAN_G(chan))
1311                 ctl |= CTL_11G;
1312         else
1313                 ctl |= CTL_11A;
1314
1315         return ctl;
1316 }
1317
1318 static int ath9k_hw_process_ini(struct ath_hw *ah,
1319                                 struct ath9k_channel *chan,
1320                                 enum ath9k_ht_macmode macmode)
1321 {
1322         int i, regWrites = 0;
1323         struct ieee80211_channel *channel = chan->chan;
1324         u32 modesIndex, freqIndex;
1325
1326         switch (chan->chanmode) {
1327         case CHANNEL_A:
1328         case CHANNEL_A_HT20:
1329                 modesIndex = 1;
1330                 freqIndex = 1;
1331                 break;
1332         case CHANNEL_A_HT40PLUS:
1333         case CHANNEL_A_HT40MINUS:
1334                 modesIndex = 2;
1335                 freqIndex = 1;
1336                 break;
1337         case CHANNEL_G:
1338         case CHANNEL_G_HT20:
1339         case CHANNEL_B:
1340                 modesIndex = 4;
1341                 freqIndex = 2;
1342                 break;
1343         case CHANNEL_G_HT40PLUS:
1344         case CHANNEL_G_HT40MINUS:
1345                 modesIndex = 3;
1346                 freqIndex = 2;
1347                 break;
1348
1349         default:
1350                 return -EINVAL;
1351         }
1352
1353         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1354         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1355         ah->eep_ops->set_addac(ah, chan);
1356
1357         if (AR_SREV_5416_22_OR_LATER(ah)) {
1358                 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1359         } else {
1360                 struct ar5416IniArray temp;
1361                 u32 addacSize =
1362                         sizeof(u32) * ah->iniAddac.ia_rows *
1363                         ah->iniAddac.ia_columns;
1364
1365                 memcpy(ah->addac5416_21,
1366                        ah->iniAddac.ia_array, addacSize);
1367
1368                 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1369
1370                 temp.ia_array = ah->addac5416_21;
1371                 temp.ia_columns = ah->iniAddac.ia_columns;
1372                 temp.ia_rows = ah->iniAddac.ia_rows;
1373                 REG_WRITE_ARRAY(&temp, 1, regWrites);
1374         }
1375
1376         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1377
1378         for (i = 0; i < ah->iniModes.ia_rows; i++) {
1379                 u32 reg = INI_RA(&ah->iniModes, i, 0);
1380                 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1381
1382                 REG_WRITE(ah, reg, val);
1383
1384                 if (reg >= 0x7800 && reg < 0x78a0
1385                     && ah->config.analog_shiftreg) {
1386                         udelay(100);
1387                 }
1388
1389                 DO_DELAY(regWrites);
1390         }
1391
1392         if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1393                 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1394
1395         if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1396             AR_SREV_9287_10_OR_LATER(ah))
1397                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1398
1399         for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1400                 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1401                 u32 val = INI_RA(&ah->iniCommon, i, 1);
1402
1403                 REG_WRITE(ah, reg, val);
1404
1405                 if (reg >= 0x7800 && reg < 0x78a0
1406                     && ah->config.analog_shiftreg) {
1407                         udelay(100);
1408                 }
1409
1410                 DO_DELAY(regWrites);
1411         }
1412
1413         ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1414
1415         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1416                 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1417                                 regWrites);
1418         }
1419
1420         ath9k_hw_override_ini(ah, chan);
1421         ath9k_hw_set_regs(ah, chan, macmode);
1422         ath9k_hw_init_chain_masks(ah);
1423
1424         if (OLC_FOR_AR9280_20_LATER)
1425                 ath9k_olc_init(ah);
1426
1427         ah->eep_ops->set_txpower(ah, chan,
1428                                  ath9k_regd_get_ctl(&ah->regulatory, chan),
1429                                  channel->max_antenna_gain * 2,
1430                                  channel->max_power * 2,
1431                                  min((u32) MAX_RATE_POWER,
1432                                  (u32) ah->regulatory.power_limit));
1433
1434         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1435                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1436                         "ar5416SetRfRegs failed\n");
1437                 return -EIO;
1438         }
1439
1440         return 0;
1441 }
1442
1443 /****************************************/
1444 /* Reset and Channel Switching Routines */
1445 /****************************************/
1446
1447 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1448 {
1449         u32 rfMode = 0;
1450
1451         if (chan == NULL)
1452                 return;
1453
1454         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1455                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1456
1457         if (!AR_SREV_9280_10_OR_LATER(ah))
1458                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1459                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1460
1461         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1462                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1463
1464         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1465 }
1466
1467 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1468 {
1469         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1470 }
1471
1472 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1473 {
1474         u32 regval;
1475
1476         regval = REG_READ(ah, AR_AHB_MODE);
1477         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1478
1479         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1480         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1481
1482         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1483
1484         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1485         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1486
1487         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1488
1489         if (AR_SREV_9285(ah)) {
1490                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1491                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1492         } else {
1493                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1494                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1495         }
1496 }
1497
1498 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1499 {
1500         u32 val;
1501
1502         val = REG_READ(ah, AR_STA_ID1);
1503         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1504         switch (opmode) {
1505         case NL80211_IFTYPE_AP:
1506                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1507                           | AR_STA_ID1_KSRCH_MODE);
1508                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1509                 break;
1510         case NL80211_IFTYPE_ADHOC:
1511         case NL80211_IFTYPE_MESH_POINT:
1512                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1513                           | AR_STA_ID1_KSRCH_MODE);
1514                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1515                 break;
1516         case NL80211_IFTYPE_STATION:
1517         case NL80211_IFTYPE_MONITOR:
1518                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1519                 break;
1520         }
1521 }
1522
1523 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1524                                                  u32 coef_scaled,
1525                                                  u32 *coef_mantissa,
1526                                                  u32 *coef_exponent)
1527 {
1528         u32 coef_exp, coef_man;
1529
1530         for (coef_exp = 31; coef_exp > 0; coef_exp--)
1531                 if ((coef_scaled >> coef_exp) & 0x1)
1532                         break;
1533
1534         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1535
1536         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1537
1538         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1539         *coef_exponent = coef_exp - 16;
1540 }
1541
1542 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1543                                      struct ath9k_channel *chan)
1544 {
1545         u32 coef_scaled, ds_coef_exp, ds_coef_man;
1546         u32 clockMhzScaled = 0x64000000;
1547         struct chan_centers centers;
1548
1549         if (IS_CHAN_HALF_RATE(chan))
1550                 clockMhzScaled = clockMhzScaled >> 1;
1551         else if (IS_CHAN_QUARTER_RATE(chan))
1552                 clockMhzScaled = clockMhzScaled >> 2;
1553
1554         ath9k_hw_get_channel_centers(ah, chan, &centers);
1555         coef_scaled = clockMhzScaled / centers.synth_center;
1556
1557         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1558                                       &ds_coef_exp);
1559
1560         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1561                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1562         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1563                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1564
1565         coef_scaled = (9 * coef_scaled) / 10;
1566
1567         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1568                                       &ds_coef_exp);
1569
1570         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1571                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1572         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1573                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1574 }
1575
1576 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1577 {
1578         u32 rst_flags;
1579         u32 tmpReg;
1580
1581         if (AR_SREV_9100(ah)) {
1582                 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1583                 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1584                 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1585                 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1586                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1587         }
1588
1589         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1590                   AR_RTC_FORCE_WAKE_ON_INT);
1591
1592         if (AR_SREV_9100(ah)) {
1593                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1594                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1595         } else {
1596                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1597                 if (tmpReg &
1598                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1599                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1600                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1601                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1602                 } else {
1603                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1604                 }
1605
1606                 rst_flags = AR_RTC_RC_MAC_WARM;
1607                 if (type == ATH9K_RESET_COLD)
1608                         rst_flags |= AR_RTC_RC_MAC_COLD;
1609         }
1610
1611         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1612         udelay(50);
1613
1614         REG_WRITE(ah, AR_RTC_RC, 0);
1615         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1616                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1617                         "RTC stuck in MAC reset\n");
1618                 return false;
1619         }
1620
1621         if (!AR_SREV_9100(ah))
1622                 REG_WRITE(ah, AR_RC, 0);
1623
1624         ath9k_hw_init_pll(ah, NULL);
1625
1626         if (AR_SREV_9100(ah))
1627                 udelay(50);
1628
1629         return true;
1630 }
1631
1632 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1633 {
1634         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1635                   AR_RTC_FORCE_WAKE_ON_INT);
1636
1637         REG_WRITE(ah, AR_RTC_RESET, 0);
1638         udelay(2);
1639         REG_WRITE(ah, AR_RTC_RESET, 1);
1640
1641         if (!ath9k_hw_wait(ah,
1642                            AR_RTC_STATUS,
1643                            AR_RTC_STATUS_M,
1644                            AR_RTC_STATUS_ON,
1645                            AH_WAIT_TIMEOUT)) {
1646                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1647                 return false;
1648         }
1649
1650         ath9k_hw_read_revisions(ah);
1651
1652         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1653 }
1654
1655 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1656 {
1657         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1658                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1659
1660         switch (type) {
1661         case ATH9K_RESET_POWER_ON:
1662                 return ath9k_hw_set_reset_power_on(ah);
1663         case ATH9K_RESET_WARM:
1664         case ATH9K_RESET_COLD:
1665                 return ath9k_hw_set_reset(ah, type);
1666         default:
1667                 return false;
1668         }
1669 }
1670
1671 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
1672                               enum ath9k_ht_macmode macmode)
1673 {
1674         u32 phymode;
1675         u32 enableDacFifo = 0;
1676
1677         if (AR_SREV_9285_10_OR_LATER(ah))
1678                 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1679                                          AR_PHY_FC_ENABLE_DAC_FIFO);
1680
1681         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1682                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1683
1684         if (IS_CHAN_HT40(chan)) {
1685                 phymode |= AR_PHY_FC_DYN2040_EN;
1686
1687                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1688                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1689                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1690
1691                 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1692                         phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1693         }
1694         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1695
1696         ath9k_hw_set11nmac2040(ah, macmode);
1697
1698         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1699         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1700 }
1701
1702 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1703                                 struct ath9k_channel *chan)
1704 {
1705         if (OLC_FOR_AR9280_20_LATER) {
1706                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1707                         return false;
1708         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1709                 return false;
1710
1711         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1712                 return false;
1713
1714         ah->chip_fullsleep = false;
1715         ath9k_hw_init_pll(ah, chan);
1716         ath9k_hw_set_rfmode(ah, chan);
1717
1718         return true;
1719 }
1720
1721 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1722                                     struct ath9k_channel *chan,
1723                                     enum ath9k_ht_macmode macmode)
1724 {
1725         struct ieee80211_channel *channel = chan->chan;
1726         u32 synthDelay, qnum;
1727
1728         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1729                 if (ath9k_hw_numtxpending(ah, qnum)) {
1730                         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1731                                 "Transmit frames pending on queue %d\n", qnum);
1732                         return false;
1733                 }
1734         }
1735
1736         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1737         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1738                            AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1739                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1740                         "Could not kill baseband RX\n");
1741                 return false;
1742         }
1743
1744         ath9k_hw_set_regs(ah, chan, macmode);
1745
1746         if (AR_SREV_9280_10_OR_LATER(ah)) {
1747                 ath9k_hw_ar9280_set_channel(ah, chan);
1748         } else {
1749                 if (!(ath9k_hw_set_channel(ah, chan))) {
1750                         DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1751                                 "Failed to set channel\n");
1752                         return false;
1753                 }
1754         }
1755
1756         ah->eep_ops->set_txpower(ah, chan,
1757                              ath9k_regd_get_ctl(&ah->regulatory, chan),
1758                              channel->max_antenna_gain * 2,
1759                              channel->max_power * 2,
1760                              min((u32) MAX_RATE_POWER,
1761                              (u32) ah->regulatory.power_limit));
1762
1763         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1764         if (IS_CHAN_B(chan))
1765                 synthDelay = (4 * synthDelay) / 22;
1766         else
1767                 synthDelay /= 10;
1768
1769         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1770
1771         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1772
1773         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1774                 ath9k_hw_set_delta_slope(ah, chan);
1775
1776         if (AR_SREV_9280_10_OR_LATER(ah))
1777                 ath9k_hw_9280_spur_mitigate(ah, chan);
1778         else
1779                 ath9k_hw_spur_mitigate(ah, chan);
1780
1781         if (!chan->oneTimeCalsDone)
1782                 chan->oneTimeCalsDone = true;
1783
1784         return true;
1785 }
1786
1787 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1788 {
1789         int bb_spur = AR_NO_SPUR;
1790         int freq;
1791         int bin, cur_bin;
1792         int bb_spur_off, spur_subchannel_sd;
1793         int spur_freq_sd;
1794         int spur_delta_phase;
1795         int denominator;
1796         int upper, lower, cur_vit_mask;
1797         int tmp, newVal;
1798         int i;
1799         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1800                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1801         };
1802         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1803                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1804         };
1805         int inc[4] = { 0, 100, 0, 0 };
1806         struct chan_centers centers;
1807
1808         int8_t mask_m[123];
1809         int8_t mask_p[123];
1810         int8_t mask_amt;
1811         int tmp_mask;
1812         int cur_bb_spur;
1813         bool is2GHz = IS_CHAN_2GHZ(chan);
1814
1815         memset(&mask_m, 0, sizeof(int8_t) * 123);
1816         memset(&mask_p, 0, sizeof(int8_t) * 123);
1817
1818         ath9k_hw_get_channel_centers(ah, chan, &centers);
1819         freq = centers.synth_center;
1820
1821         ah->config.spurmode = SPUR_ENABLE_EEPROM;
1822         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1823                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1824
1825                 if (is2GHz)
1826                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1827                 else
1828                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1829
1830                 if (AR_NO_SPUR == cur_bb_spur)
1831                         break;
1832                 cur_bb_spur = cur_bb_spur - freq;
1833
1834                 if (IS_CHAN_HT40(chan)) {
1835                         if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1836                             (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1837                                 bb_spur = cur_bb_spur;
1838                                 break;
1839                         }
1840                 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1841                            (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1842                         bb_spur = cur_bb_spur;
1843                         break;
1844                 }
1845         }
1846
1847         if (AR_NO_SPUR == bb_spur) {
1848                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1849                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1850                 return;
1851         } else {
1852                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1853                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1854         }
1855
1856         bin = bb_spur * 320;
1857
1858         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1859
1860         newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1861                         AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1862                         AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1863                         AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1864         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1865
1866         newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1867                   AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1868                   AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1869                   AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1870                   SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1871         REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1872
1873         if (IS_CHAN_HT40(chan)) {
1874                 if (bb_spur < 0) {
1875                         spur_subchannel_sd = 1;
1876                         bb_spur_off = bb_spur + 10;
1877                 } else {
1878                         spur_subchannel_sd = 0;
1879                         bb_spur_off = bb_spur - 10;
1880                 }
1881         } else {
1882                 spur_subchannel_sd = 0;
1883                 bb_spur_off = bb_spur;
1884         }
1885
1886         if (IS_CHAN_HT40(chan))
1887                 spur_delta_phase =
1888                         ((bb_spur * 262144) /
1889                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1890         else
1891                 spur_delta_phase =
1892                         ((bb_spur * 524288) /
1893                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1894
1895         denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1896         spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1897
1898         newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1899                   SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1900                   SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1901         REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1902
1903         newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1904         REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1905
1906         cur_bin = -6000;
1907         upper = bin + 100;
1908         lower = bin - 100;
1909
1910         for (i = 0; i < 4; i++) {
1911                 int pilot_mask = 0;
1912                 int chan_mask = 0;
1913                 int bp = 0;
1914                 for (bp = 0; bp < 30; bp++) {
1915                         if ((cur_bin > lower) && (cur_bin < upper)) {
1916                                 pilot_mask = pilot_mask | 0x1 << bp;
1917                                 chan_mask = chan_mask | 0x1 << bp;
1918                         }
1919                         cur_bin += 100;
1920                 }
1921                 cur_bin += inc[i];
1922                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1923                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1924         }
1925
1926         cur_vit_mask = 6100;
1927         upper = bin + 120;
1928         lower = bin - 120;
1929
1930         for (i = 0; i < 123; i++) {
1931                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1932
1933                         /* workaround for gcc bug #37014 */
1934                         volatile int tmp_v = abs(cur_vit_mask - bin);
1935
1936                         if (tmp_v < 75)
1937                                 mask_amt = 1;
1938                         else
1939                                 mask_amt = 0;
1940                         if (cur_vit_mask < 0)
1941                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1942                         else
1943                                 mask_p[cur_vit_mask / 100] = mask_amt;
1944                 }
1945                 cur_vit_mask -= 100;
1946         }
1947
1948         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1949                 | (mask_m[48] << 26) | (mask_m[49] << 24)
1950                 | (mask_m[50] << 22) | (mask_m[51] << 20)
1951                 | (mask_m[52] << 18) | (mask_m[53] << 16)
1952                 | (mask_m[54] << 14) | (mask_m[55] << 12)
1953                 | (mask_m[56] << 10) | (mask_m[57] << 8)
1954                 | (mask_m[58] << 6) | (mask_m[59] << 4)
1955                 | (mask_m[60] << 2) | (mask_m[61] << 0);
1956         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1957         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1958
1959         tmp_mask = (mask_m[31] << 28)
1960                 | (mask_m[32] << 26) | (mask_m[33] << 24)
1961                 | (mask_m[34] << 22) | (mask_m[35] << 20)
1962                 | (mask_m[36] << 18) | (mask_m[37] << 16)
1963                 | (mask_m[48] << 14) | (mask_m[39] << 12)
1964                 | (mask_m[40] << 10) | (mask_m[41] << 8)
1965                 | (mask_m[42] << 6) | (mask_m[43] << 4)
1966                 | (mask_m[44] << 2) | (mask_m[45] << 0);
1967         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1968         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1969
1970         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1971                 | (mask_m[18] << 26) | (mask_m[18] << 24)
1972                 | (mask_m[20] << 22) | (mask_m[20] << 20)
1973                 | (mask_m[22] << 18) | (mask_m[22] << 16)
1974                 | (mask_m[24] << 14) | (mask_m[24] << 12)
1975                 | (mask_m[25] << 10) | (mask_m[26] << 8)
1976                 | (mask_m[27] << 6) | (mask_m[28] << 4)
1977                 | (mask_m[29] << 2) | (mask_m[30] << 0);
1978         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1979         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1980
1981         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1982                 | (mask_m[2] << 26) | (mask_m[3] << 24)
1983                 | (mask_m[4] << 22) | (mask_m[5] << 20)
1984                 | (mask_m[6] << 18) | (mask_m[7] << 16)
1985                 | (mask_m[8] << 14) | (mask_m[9] << 12)
1986                 | (mask_m[10] << 10) | (mask_m[11] << 8)
1987                 | (mask_m[12] << 6) | (mask_m[13] << 4)
1988                 | (mask_m[14] << 2) | (mask_m[15] << 0);
1989         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1990         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1991
1992         tmp_mask = (mask_p[15] << 28)
1993                 | (mask_p[14] << 26) | (mask_p[13] << 24)
1994                 | (mask_p[12] << 22) | (mask_p[11] << 20)
1995                 | (mask_p[10] << 18) | (mask_p[9] << 16)
1996                 | (mask_p[8] << 14) | (mask_p[7] << 12)
1997                 | (mask_p[6] << 10) | (mask_p[5] << 8)
1998                 | (mask_p[4] << 6) | (mask_p[3] << 4)
1999                 | (mask_p[2] << 2) | (mask_p[1] << 0);
2000         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2001         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2002
2003         tmp_mask = (mask_p[30] << 28)
2004                 | (mask_p[29] << 26) | (mask_p[28] << 24)
2005                 | (mask_p[27] << 22) | (mask_p[26] << 20)
2006                 | (mask_p[25] << 18) | (mask_p[24] << 16)
2007                 | (mask_p[23] << 14) | (mask_p[22] << 12)
2008                 | (mask_p[21] << 10) | (mask_p[20] << 8)
2009                 | (mask_p[19] << 6) | (mask_p[18] << 4)
2010                 | (mask_p[17] << 2) | (mask_p[16] << 0);
2011         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2012         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2013
2014         tmp_mask = (mask_p[45] << 28)
2015                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2016                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2017                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2018                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2019                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2020                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2021                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2022         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2023         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2024
2025         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2026                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2027                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2028                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2029                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2030                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2031                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2032                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2033         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2034         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2035 }
2036
2037 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
2038 {
2039         int bb_spur = AR_NO_SPUR;
2040         int bin, cur_bin;
2041         int spur_freq_sd;
2042         int spur_delta_phase;
2043         int denominator;
2044         int upper, lower, cur_vit_mask;
2045         int tmp, new;
2046         int i;
2047         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
2048                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2049         };
2050         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2051                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2052         };
2053         int inc[4] = { 0, 100, 0, 0 };
2054
2055         int8_t mask_m[123];
2056         int8_t mask_p[123];
2057         int8_t mask_amt;
2058         int tmp_mask;
2059         int cur_bb_spur;
2060         bool is2GHz = IS_CHAN_2GHZ(chan);
2061
2062         memset(&mask_m, 0, sizeof(int8_t) * 123);
2063         memset(&mask_p, 0, sizeof(int8_t) * 123);
2064
2065         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2066                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
2067                 if (AR_NO_SPUR == cur_bb_spur)
2068                         break;
2069                 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2070                 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2071                         bb_spur = cur_bb_spur;
2072                         break;
2073                 }
2074         }
2075
2076         if (AR_NO_SPUR == bb_spur)
2077                 return;
2078
2079         bin = bb_spur * 32;
2080
2081         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2082         new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2083                      AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2084                      AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2085                      AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2086
2087         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2088
2089         new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2090                AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2091                AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2092                AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2093                SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2094         REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2095
2096         spur_delta_phase = ((bb_spur * 524288) / 100) &
2097                 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2098
2099         denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2100         spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2101
2102         new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2103                SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2104                SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2105         REG_WRITE(ah, AR_PHY_TIMING11, new);
2106
2107         cur_bin = -6000;
2108         upper = bin + 100;
2109         lower = bin - 100;
2110
2111         for (i = 0; i < 4; i++) {
2112                 int pilot_mask = 0;
2113                 int chan_mask = 0;
2114                 int bp = 0;
2115                 for (bp = 0; bp < 30; bp++) {
2116                         if ((cur_bin > lower) && (cur_bin < upper)) {
2117                                 pilot_mask = pilot_mask | 0x1 << bp;
2118                                 chan_mask = chan_mask | 0x1 << bp;
2119                         }
2120                         cur_bin += 100;
2121                 }
2122                 cur_bin += inc[i];
2123                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2124                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2125         }
2126
2127         cur_vit_mask = 6100;
2128         upper = bin + 120;
2129         lower = bin - 120;
2130
2131         for (i = 0; i < 123; i++) {
2132                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2133
2134                         /* workaround for gcc bug #37014 */
2135                         volatile int tmp_v = abs(cur_vit_mask - bin);
2136
2137                         if (tmp_v < 75)
2138                                 mask_amt = 1;
2139                         else
2140                                 mask_amt = 0;
2141                         if (cur_vit_mask < 0)
2142                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2143                         else
2144                                 mask_p[cur_vit_mask / 100] = mask_amt;
2145                 }
2146                 cur_vit_mask -= 100;
2147         }
2148
2149         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2150                 | (mask_m[48] << 26) | (mask_m[49] << 24)
2151                 | (mask_m[50] << 22) | (mask_m[51] << 20)
2152                 | (mask_m[52] << 18) | (mask_m[53] << 16)
2153                 | (mask_m[54] << 14) | (mask_m[55] << 12)
2154                 | (mask_m[56] << 10) | (mask_m[57] << 8)
2155                 | (mask_m[58] << 6) | (mask_m[59] << 4)
2156                 | (mask_m[60] << 2) | (mask_m[61] << 0);
2157         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2158         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2159
2160         tmp_mask = (mask_m[31] << 28)
2161                 | (mask_m[32] << 26) | (mask_m[33] << 24)
2162                 | (mask_m[34] << 22) | (mask_m[35] << 20)
2163                 | (mask_m[36] << 18) | (mask_m[37] << 16)
2164                 | (mask_m[48] << 14) | (mask_m[39] << 12)
2165                 | (mask_m[40] << 10) | (mask_m[41] << 8)
2166                 | (mask_m[42] << 6) | (mask_m[43] << 4)
2167                 | (mask_m[44] << 2) | (mask_m[45] << 0);
2168         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2169         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2170
2171         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2172                 | (mask_m[18] << 26) | (mask_m[18] << 24)
2173                 | (mask_m[20] << 22) | (mask_m[20] << 20)
2174                 | (mask_m[22] << 18) | (mask_m[22] << 16)
2175                 | (mask_m[24] << 14) | (mask_m[24] << 12)
2176                 | (mask_m[25] << 10) | (mask_m[26] << 8)
2177                 | (mask_m[27] << 6) | (mask_m[28] << 4)
2178                 | (mask_m[29] << 2) | (mask_m[30] << 0);
2179         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2180         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2181
2182         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2183                 | (mask_m[2] << 26) | (mask_m[3] << 24)
2184                 | (mask_m[4] << 22) | (mask_m[5] << 20)
2185                 | (mask_m[6] << 18) | (mask_m[7] << 16)
2186                 | (mask_m[8] << 14) | (mask_m[9] << 12)
2187                 | (mask_m[10] << 10) | (mask_m[11] << 8)
2188                 | (mask_m[12] << 6) | (mask_m[13] << 4)
2189                 | (mask_m[14] << 2) | (mask_m[15] << 0);
2190         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2191         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2192
2193         tmp_mask = (mask_p[15] << 28)
2194                 | (mask_p[14] << 26) | (mask_p[13] << 24)
2195                 | (mask_p[12] << 22) | (mask_p[11] << 20)
2196                 | (mask_p[10] << 18) | (mask_p[9] << 16)
2197                 | (mask_p[8] << 14) | (mask_p[7] << 12)
2198                 | (mask_p[6] << 10) | (mask_p[5] << 8)
2199                 | (mask_p[4] << 6) | (mask_p[3] << 4)
2200                 | (mask_p[2] << 2) | (mask_p[1] << 0);
2201         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2202         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2203
2204         tmp_mask = (mask_p[30] << 28)
2205                 | (mask_p[29] << 26) | (mask_p[28] << 24)
2206                 | (mask_p[27] << 22) | (mask_p[26] << 20)
2207                 | (mask_p[25] << 18) | (mask_p[24] << 16)
2208                 | (mask_p[23] << 14) | (mask_p[22] << 12)
2209                 | (mask_p[21] << 10) | (mask_p[20] << 8)
2210                 | (mask_p[19] << 6) | (mask_p[18] << 4)
2211                 | (mask_p[17] << 2) | (mask_p[16] << 0);
2212         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2213         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2214
2215         tmp_mask = (mask_p[45] << 28)
2216                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2217                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2218                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2219                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2220                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2221                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2222                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2223         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2224         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2225
2226         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2227                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2228                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2229                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2230                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2231                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2232                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2233                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2234         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2235         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2236 }
2237
2238 static void ath9k_enable_rfkill(struct ath_hw *ah)
2239 {
2240         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2241                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
2242
2243         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
2244                     AR_GPIO_INPUT_MUX2_RFSILENT);
2245
2246         ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
2247         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
2248 }
2249
2250 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2251                     bool bChannelChange)
2252 {
2253         u32 saveLedState;
2254         struct ath_softc *sc = ah->ah_sc;
2255         struct ath9k_channel *curchan = ah->curchan;
2256         u32 saveDefAntenna;
2257         u32 macStaId1;
2258         int i, rx_chainmask, r;
2259
2260         ah->extprotspacing = sc->ht_extprotspacing;
2261         ah->txchainmask = sc->tx_chainmask;
2262         ah->rxchainmask = sc->rx_chainmask;
2263
2264         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2265                 return -EIO;
2266
2267         if (curchan)
2268                 ath9k_hw_getnf(ah, curchan);
2269
2270         if (bChannelChange &&
2271             (ah->chip_fullsleep != true) &&
2272             (ah->curchan != NULL) &&
2273             (chan->channel != ah->curchan->channel) &&
2274             ((chan->channelFlags & CHANNEL_ALL) ==
2275              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
2276             (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2277                                    !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) {
2278
2279                 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2280                         ath9k_hw_loadnf(ah, ah->curchan);
2281                         ath9k_hw_start_nfcal(ah);
2282                         return 0;
2283                 }
2284         }
2285
2286         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2287         if (saveDefAntenna == 0)
2288                 saveDefAntenna = 1;
2289
2290         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2291
2292         saveLedState = REG_READ(ah, AR_CFG_LED) &
2293                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2294                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2295
2296         ath9k_hw_mark_phy_inactive(ah);
2297
2298         if (!ath9k_hw_chip_reset(ah, chan)) {
2299                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Chip reset failed\n");
2300                 return -EINVAL;
2301         }
2302
2303         if (AR_SREV_9280_10_OR_LATER(ah))
2304                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2305
2306         if (AR_SREV_9287_10_OR_LATER(ah)) {
2307                 /* Enable ASYNC FIFO */
2308                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2309                                 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
2310                 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
2311                 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2312                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2313                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2314                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2315         }
2316         r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2317         if (r)
2318                 return r;
2319
2320         /* Setup MFP options for CCMP */
2321         if (AR_SREV_9280_20_OR_LATER(ah)) {
2322                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2323                  * frames when constructing CCMP AAD. */
2324                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2325                               0xc7ff);
2326                 ah->sw_mgmt_crypto = false;
2327         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2328                 /* Disable hardware crypto for management frames */
2329                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2330                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2331                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2332                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2333                 ah->sw_mgmt_crypto = true;
2334         } else
2335                 ah->sw_mgmt_crypto = true;
2336
2337         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2338                 ath9k_hw_set_delta_slope(ah, chan);
2339
2340         if (AR_SREV_9280_10_OR_LATER(ah))
2341                 ath9k_hw_9280_spur_mitigate(ah, chan);
2342         else
2343                 ath9k_hw_spur_mitigate(ah, chan);
2344
2345         ah->eep_ops->set_board_values(ah, chan);
2346
2347         ath9k_hw_decrease_chain_power(ah, chan);
2348
2349         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
2350         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
2351                   | macStaId1
2352                   | AR_STA_ID1_RTS_USE_DEF
2353                   | (ah->config.
2354                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2355                   | ah->sta_id1_defaults);
2356         ath9k_hw_set_operating_mode(ah, ah->opmode);
2357
2358         REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
2359         REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
2360
2361         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2362
2363         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
2364         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2365                   ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2366
2367         REG_WRITE(ah, AR_ISR, ~0);
2368
2369         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2370
2371         if (AR_SREV_9280_10_OR_LATER(ah))
2372                 ath9k_hw_ar9280_set_channel(ah, chan);
2373         else
2374                 if (!(ath9k_hw_set_channel(ah, chan)))
2375                         return -EIO;
2376
2377         for (i = 0; i < AR_NUM_DCU; i++)
2378                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2379
2380         ah->intr_txqs = 0;
2381         for (i = 0; i < ah->caps.total_queues; i++)
2382                 ath9k_hw_resettxqueue(ah, i);
2383
2384         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2385         ath9k_hw_init_qos(ah);
2386
2387         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2388                 ath9k_enable_rfkill(ah);
2389
2390         ath9k_hw_init_user_settings(ah);
2391
2392         if (AR_SREV_9287_10_OR_LATER(ah)) {
2393                 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2394                           AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2395                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2396                           AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2397                 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2398                           AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2399
2400                 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2401                 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2402
2403                 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2404                             AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2405                 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2406                               AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2407         }
2408         if (AR_SREV_9287_10_OR_LATER(ah)) {
2409                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2410                                 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2411         }
2412
2413         REG_WRITE(ah, AR_STA_ID1,
2414                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2415
2416         ath9k_hw_set_dma(ah);
2417
2418         REG_WRITE(ah, AR_OBS, 8);
2419
2420         if (ah->config.intr_mitigation) {
2421                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2422                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2423         }
2424
2425         ath9k_hw_init_bb(ah, chan);
2426
2427         if (!ath9k_hw_init_cal(ah, chan))
2428                 return -EIO;
2429
2430         rx_chainmask = ah->rxchainmask;
2431         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2432                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2433                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2434         }
2435
2436         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2437
2438         if (AR_SREV_9100(ah)) {
2439                 u32 mask;
2440                 mask = REG_READ(ah, AR_CFG);
2441                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2442                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2443                                 "CFG Byte Swap Set 0x%x\n", mask);
2444                 } else {
2445                         mask =
2446                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2447                         REG_WRITE(ah, AR_CFG, mask);
2448                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2449                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2450                 }
2451         } else {
2452 #ifdef __BIG_ENDIAN
2453                 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2454 #endif
2455         }
2456
2457         return 0;
2458 }
2459
2460 /************************/
2461 /* Key Cache Management */
2462 /************************/
2463
2464 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2465 {
2466         u32 keyType;
2467
2468         if (entry >= ah->caps.keycache_size) {
2469                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2470                         "keychache entry %u out of range\n", entry);
2471                 return false;
2472         }
2473
2474         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2475
2476         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2477         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2478         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2479         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2480         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2481         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2482         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2483         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2484
2485         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2486                 u16 micentry = entry + 64;
2487
2488                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2489                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2490                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2491                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2492
2493         }
2494
2495         if (ah->curchan == NULL)
2496                 return true;
2497
2498         return true;
2499 }
2500
2501 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2502 {
2503         u32 macHi, macLo;
2504
2505         if (entry >= ah->caps.keycache_size) {
2506                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2507                         "keychache entry %u out of range\n", entry);
2508                 return false;
2509         }
2510
2511         if (mac != NULL) {
2512                 macHi = (mac[5] << 8) | mac[4];
2513                 macLo = (mac[3] << 24) |
2514                         (mac[2] << 16) |
2515                         (mac[1] << 8) |
2516                         mac[0];
2517                 macLo >>= 1;
2518                 macLo |= (macHi & 1) << 31;
2519                 macHi >>= 1;
2520         } else {
2521                 macLo = macHi = 0;
2522         }
2523         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2524         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2525
2526         return true;
2527 }
2528
2529 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2530                                  const struct ath9k_keyval *k,
2531                                  const u8 *mac)
2532 {
2533         const struct ath9k_hw_capabilities *pCap = &ah->caps;
2534         u32 key0, key1, key2, key3, key4;
2535         u32 keyType;
2536
2537         if (entry >= pCap->keycache_size) {
2538                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2539                         "keycache entry %u out of range\n", entry);
2540                 return false;
2541         }
2542
2543         switch (k->kv_type) {
2544         case ATH9K_CIPHER_AES_OCB:
2545                 keyType = AR_KEYTABLE_TYPE_AES;
2546                 break;
2547         case ATH9K_CIPHER_AES_CCM:
2548                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2549                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2550                                 "AES-CCM not supported by mac rev 0x%x\n",
2551                                 ah->hw_version.macRev);
2552                         return false;
2553                 }
2554                 keyType = AR_KEYTABLE_TYPE_CCM;
2555                 break;
2556         case ATH9K_CIPHER_TKIP:
2557                 keyType = AR_KEYTABLE_TYPE_TKIP;
2558                 if (ATH9K_IS_MIC_ENABLED(ah)
2559                     && entry + 64 >= pCap->keycache_size) {
2560                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2561                                 "entry %u inappropriate for TKIP\n", entry);
2562                         return false;
2563                 }
2564                 break;
2565         case ATH9K_CIPHER_WEP:
2566                 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2567                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2568                                 "WEP key length %u too small\n", k->kv_len);
2569                         return false;
2570                 }
2571                 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
2572                         keyType = AR_KEYTABLE_TYPE_40;
2573                 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2574                         keyType = AR_KEYTABLE_TYPE_104;
2575                 else
2576                         keyType = AR_KEYTABLE_TYPE_128;
2577                 break;
2578         case ATH9K_CIPHER_CLR:
2579                 keyType = AR_KEYTABLE_TYPE_CLR;
2580                 break;
2581         default:
2582                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2583                         "cipher %u not supported\n", k->kv_type);
2584                 return false;
2585         }
2586
2587         key0 = get_unaligned_le32(k->kv_val + 0);
2588         key1 = get_unaligned_le16(k->kv_val + 4);
2589         key2 = get_unaligned_le32(k->kv_val + 6);
2590         key3 = get_unaligned_le16(k->kv_val + 10);
2591         key4 = get_unaligned_le32(k->kv_val + 12);
2592         if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2593                 key4 &= 0xff;
2594
2595         /*
2596          * Note: Key cache registers access special memory area that requires
2597          * two 32-bit writes to actually update the values in the internal
2598          * memory. Consequently, the exact order and pairs used here must be
2599          * maintained.
2600          */
2601
2602         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2603                 u16 micentry = entry + 64;
2604
2605                 /*
2606                  * Write inverted key[47:0] first to avoid Michael MIC errors
2607                  * on frames that could be sent or received at the same time.
2608                  * The correct key will be written in the end once everything
2609                  * else is ready.
2610                  */
2611                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2612                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2613
2614                 /* Write key[95:48] */
2615                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2616                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2617
2618                 /* Write key[127:96] and key type */
2619                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2620                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2621
2622                 /* Write MAC address for the entry */
2623                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2624
2625                 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2626                         /*
2627                          * TKIP uses two key cache entries:
2628                          * Michael MIC TX/RX keys in the same key cache entry
2629                          * (idx = main index + 64):
2630                          * key0 [31:0] = RX key [31:0]
2631                          * key1 [15:0] = TX key [31:16]
2632                          * key1 [31:16] = reserved
2633                          * key2 [31:0] = RX key [63:32]
2634                          * key3 [15:0] = TX key [15:0]
2635                          * key3 [31:16] = reserved
2636                          * key4 [31:0] = TX key [63:32]
2637                          */
2638                         u32 mic0, mic1, mic2, mic3, mic4;
2639
2640                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2641                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2642                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2643                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2644                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
2645
2646                         /* Write RX[31:0] and TX[31:16] */
2647                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2648                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2649
2650                         /* Write RX[63:32] and TX[15:0] */
2651                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2652                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2653
2654                         /* Write TX[63:32] and keyType(reserved) */
2655                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2656                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2657                                   AR_KEYTABLE_TYPE_CLR);
2658
2659                 } else {
2660                         /*
2661                          * TKIP uses four key cache entries (two for group
2662                          * keys):
2663                          * Michael MIC TX/RX keys are in different key cache
2664                          * entries (idx = main index + 64 for TX and
2665                          * main index + 32 + 96 for RX):
2666                          * key0 [31:0] = TX/RX MIC key [31:0]
2667                          * key1 [31:0] = reserved
2668                          * key2 [31:0] = TX/RX MIC key [63:32]
2669                          * key3 [31:0] = reserved
2670                          * key4 [31:0] = reserved
2671                          *
2672                          * Upper layer code will call this function separately
2673                          * for TX and RX keys when these registers offsets are
2674                          * used.
2675                          */
2676                         u32 mic0, mic2;
2677
2678                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2679                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2680
2681                         /* Write MIC key[31:0] */
2682                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2683                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2684
2685                         /* Write MIC key[63:32] */
2686                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2687                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2688
2689                         /* Write TX[63:32] and keyType(reserved) */
2690                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2691                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2692                                   AR_KEYTABLE_TYPE_CLR);
2693                 }
2694
2695                 /* MAC address registers are reserved for the MIC entry */
2696                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2697                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2698
2699                 /*
2700                  * Write the correct (un-inverted) key[47:0] last to enable
2701                  * TKIP now that all other registers are set with correct
2702                  * values.
2703                  */
2704                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2705                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2706         } else {
2707                 /* Write key[47:0] */
2708                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2709                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2710
2711                 /* Write key[95:48] */
2712                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2713                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2714
2715                 /* Write key[127:96] and key type */
2716                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2717                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2718
2719                 /* Write MAC address for the entry */
2720                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2721         }
2722
2723         return true;
2724 }
2725
2726 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2727 {
2728         if (entry < ah->caps.keycache_size) {
2729                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2730                 if (val & AR_KEYTABLE_VALID)
2731                         return true;
2732         }
2733         return false;
2734 }
2735
2736 /******************************/
2737 /* Power Management (Chipset) */
2738 /******************************/
2739
2740 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2741 {
2742         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2743         if (setChip) {
2744                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2745                             AR_RTC_FORCE_WAKE_EN);
2746                 if (!AR_SREV_9100(ah))
2747                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2748
2749                 REG_CLR_BIT(ah, (AR_RTC_RESET),
2750                             AR_RTC_RESET_EN);
2751         }
2752 }
2753
2754 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2755 {
2756         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2757         if (setChip) {
2758                 struct ath9k_hw_capabilities *pCap = &ah->caps;
2759
2760                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2761                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2762                                   AR_RTC_FORCE_WAKE_ON_INT);
2763                 } else {
2764                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2765                                     AR_RTC_FORCE_WAKE_EN);
2766                 }
2767         }
2768 }
2769
2770 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2771 {
2772         u32 val;
2773         int i;
2774
2775         if (setChip) {
2776                 if ((REG_READ(ah, AR_RTC_STATUS) &
2777                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2778                         if (ath9k_hw_set_reset_reg(ah,
2779                                            ATH9K_RESET_POWER_ON) != true) {
2780                                 return false;
2781                         }
2782                 }
2783                 if (AR_SREV_9100(ah))
2784                         REG_SET_BIT(ah, AR_RTC_RESET,
2785                                     AR_RTC_RESET_EN);
2786
2787                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2788                             AR_RTC_FORCE_WAKE_EN);
2789                 udelay(50);
2790
2791                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2792                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2793                         if (val == AR_RTC_STATUS_ON)
2794                                 break;
2795                         udelay(50);
2796                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2797                                     AR_RTC_FORCE_WAKE_EN);
2798                 }
2799                 if (i == 0) {
2800                         DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2801                                 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2802                         return false;
2803                 }
2804         }
2805
2806         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2807
2808         return true;
2809 }
2810
2811 static bool ath9k_hw_setpower_nolock(struct ath_hw *ah,
2812                                      enum ath9k_power_mode mode)
2813 {
2814         int status = true, setChip = true;
2815         static const char *modes[] = {
2816                 "AWAKE",
2817                 "FULL-SLEEP",
2818                 "NETWORK SLEEP",
2819                 "UNDEFINED"
2820         };
2821
2822         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s -> %s\n",
2823                 modes[ah->power_mode], modes[mode]);
2824
2825         switch (mode) {
2826         case ATH9K_PM_AWAKE:
2827                 status = ath9k_hw_set_power_awake(ah, setChip);
2828                 break;
2829         case ATH9K_PM_FULL_SLEEP:
2830                 ath9k_set_power_sleep(ah, setChip);
2831                 ah->chip_fullsleep = true;
2832                 break;
2833         case ATH9K_PM_NETWORK_SLEEP:
2834                 ath9k_set_power_network_sleep(ah, setChip);
2835                 break;
2836         default:
2837                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2838                         "Unknown power mode %u\n", mode);
2839                 return false;
2840         }
2841         ah->power_mode = mode;
2842
2843         return status;
2844 }
2845
2846 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2847 {
2848         unsigned long flags;
2849         bool ret;
2850
2851         spin_lock_irqsave(&ah->ah_sc->sc_pm_lock, flags);
2852         ret = ath9k_hw_setpower_nolock(ah, mode);
2853         spin_unlock_irqrestore(&ah->ah_sc->sc_pm_lock, flags);
2854
2855         return ret;
2856 }
2857
2858 void ath9k_ps_wakeup(struct ath_softc *sc)
2859 {
2860         unsigned long flags;
2861
2862         spin_lock_irqsave(&sc->sc_pm_lock, flags);
2863         if (++sc->ps_usecount != 1)
2864                 goto unlock;
2865
2866         if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
2867                 ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_AWAKE);
2868
2869  unlock:
2870         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2871 }
2872
2873 void ath9k_ps_restore(struct ath_softc *sc)
2874 {
2875         unsigned long flags;
2876
2877         spin_lock_irqsave(&sc->sc_pm_lock, flags);
2878         if (--sc->ps_usecount != 0)
2879                 goto unlock;
2880
2881         if (sc->ps_enabled &&
2882             !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
2883                               SC_OP_WAIT_FOR_CAB |
2884                               SC_OP_WAIT_FOR_PSPOLL_DATA |
2885                               SC_OP_WAIT_FOR_TX_ACK)))
2886                 ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2887
2888  unlock:
2889         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2890 }
2891
2892 /*
2893  * Helper for ASPM support.
2894  *
2895  * Disable PLL when in L0s as well as receiver clock when in L1.
2896  * This power saving option must be enabled through the SerDes.
2897  *
2898  * Programming the SerDes must go through the same 288 bit serial shift
2899  * register as the other analog registers.  Hence the 9 writes.
2900  */
2901 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
2902 {
2903         u8 i;
2904
2905         if (ah->is_pciexpress != true)
2906                 return;
2907
2908         /* Do not touch SerDes registers */
2909         if (ah->config.pcie_powersave_enable == 2)
2910                 return;
2911
2912         /* Nothing to do on restore for 11N */
2913         if (restore)
2914                 return;
2915
2916         if (AR_SREV_9280_20_OR_LATER(ah)) {
2917                 /*
2918                  * AR9280 2.0 or later chips use SerDes values from the
2919                  * initvals.h initialized depending on chipset during
2920                  * ath9k_hw_do_attach()
2921                  */
2922                 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2923                         REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2924                                   INI_RA(&ah->iniPcieSerdes, i, 1));
2925                 }
2926         } else if (AR_SREV_9280(ah) &&
2927                    (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2928                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2929                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2930
2931                 /* RX shut off when elecidle is asserted */
2932                 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2933                 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2934                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2935
2936                 /* Shut off CLKREQ active in L1 */
2937                 if (ah->config.pcie_clock_req)
2938                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2939                 else
2940                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2941
2942                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2943                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2944                 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2945
2946                 /* Load the new settings */
2947                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2948
2949         } else {
2950                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2951                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2952
2953                 /* RX shut off when elecidle is asserted */
2954                 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2955                 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2956                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2957
2958                 /*
2959                  * Ignore ah->ah_config.pcie_clock_req setting for
2960                  * pre-AR9280 11n
2961                  */
2962                 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2963
2964                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2965                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2966                 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2967
2968                 /* Load the new settings */
2969                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2970         }
2971
2972         udelay(1000);
2973
2974         /* set bit 19 to allow forcing of pcie core into L1 state */
2975         REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2976
2977         /* Several PCIe massages to ensure proper behaviour */
2978         if (ah->config.pcie_waen) {
2979                 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
2980         } else {
2981                 if (AR_SREV_9285(ah))
2982                         REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2983                 /*
2984                  * On AR9280 chips bit 22 of 0x4004 needs to be set to
2985                  * otherwise card may disappear.
2986                  */
2987                 else if (AR_SREV_9280(ah))
2988                         REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
2989                 else
2990                         REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
2991         }
2992 }
2993
2994 /**********************/
2995 /* Interrupt Handling */
2996 /**********************/
2997
2998 bool ath9k_hw_intrpend(struct ath_hw *ah)
2999 {
3000         u32 host_isr;
3001
3002         if (AR_SREV_9100(ah))
3003                 return true;
3004
3005         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
3006         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
3007                 return true;
3008
3009         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
3010         if ((host_isr & AR_INTR_SYNC_DEFAULT)
3011             && (host_isr != AR_INTR_SPURIOUS))
3012                 return true;
3013
3014         return false;
3015 }
3016
3017 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
3018 {
3019         u32 isr = 0;
3020         u32 mask2 = 0;
3021         struct ath9k_hw_capabilities *pCap = &ah->caps;
3022         u32 sync_cause = 0;
3023         bool fatal_int = false;
3024
3025         if (!AR_SREV_9100(ah)) {
3026                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
3027                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
3028                             == AR_RTC_STATUS_ON) {
3029                                 isr = REG_READ(ah, AR_ISR);
3030                         }
3031                 }
3032
3033                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
3034                         AR_INTR_SYNC_DEFAULT;
3035
3036                 *masked = 0;
3037
3038                 if (!isr && !sync_cause)
3039                         return false;
3040         } else {
3041                 *masked = 0;
3042                 isr = REG_READ(ah, AR_ISR);
3043         }
3044
3045         if (isr) {
3046                 if (isr & AR_ISR_BCNMISC) {
3047                         u32 isr2;
3048                         isr2 = REG_READ(ah, AR_ISR_S2);
3049                         if (isr2 & AR_ISR_S2_TIM)
3050                                 mask2 |= ATH9K_INT_TIM;
3051                         if (isr2 & AR_ISR_S2_DTIM)
3052                                 mask2 |= ATH9K_INT_DTIM;
3053                         if (isr2 & AR_ISR_S2_DTIMSYNC)
3054                                 mask2 |= ATH9K_INT_DTIMSYNC;
3055                         if (isr2 & (AR_ISR_S2_CABEND))
3056                                 mask2 |= ATH9K_INT_CABEND;
3057                         if (isr2 & AR_ISR_S2_GTT)
3058                                 mask2 |= ATH9K_INT_GTT;
3059                         if (isr2 & AR_ISR_S2_CST)
3060                                 mask2 |= ATH9K_INT_CST;
3061                         if (isr2 & AR_ISR_S2_TSFOOR)
3062                                 mask2 |= ATH9K_INT_TSFOOR;
3063                 }
3064
3065                 isr = REG_READ(ah, AR_ISR_RAC);
3066                 if (isr == 0xffffffff) {
3067                         *masked = 0;
3068                         return false;
3069                 }
3070
3071                 *masked = isr & ATH9K_INT_COMMON;
3072
3073                 if (ah->config.intr_mitigation) {
3074                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
3075                                 *masked |= ATH9K_INT_RX;
3076                 }
3077
3078                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
3079                         *masked |= ATH9K_INT_RX;
3080                 if (isr &
3081                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
3082                      AR_ISR_TXEOL)) {
3083                         u32 s0_s, s1_s;
3084
3085                         *masked |= ATH9K_INT_TX;
3086
3087                         s0_s = REG_READ(ah, AR_ISR_S0_S);
3088                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
3089                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
3090
3091                         s1_s = REG_READ(ah, AR_ISR_S1_S);
3092                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
3093                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
3094                 }
3095
3096                 if (isr & AR_ISR_RXORN) {
3097                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3098                                 "receive FIFO overrun interrupt\n");
3099                 }
3100
3101                 if (!AR_SREV_9100(ah)) {
3102                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3103                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
3104                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
3105                                         *masked |= ATH9K_INT_TIM_TIMER;
3106                         }
3107                 }
3108
3109                 *masked |= mask2;
3110         }
3111
3112         if (AR_SREV_9100(ah))
3113                 return true;
3114
3115         if (sync_cause) {
3116                 fatal_int =
3117                         (sync_cause &
3118                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
3119                         ? true : false;
3120
3121                 if (fatal_int) {
3122                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
3123                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
3124                                         "received PCI FATAL interrupt\n");
3125                         }
3126                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
3127                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
3128                                         "received PCI PERR interrupt\n");
3129                         }
3130                         *masked |= ATH9K_INT_FATAL;
3131                 }
3132                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
3133                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3134                                 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
3135                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
3136                         REG_WRITE(ah, AR_RC, 0);
3137                         *masked |= ATH9K_INT_FATAL;
3138                 }
3139                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
3140                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3141                                 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
3142                 }
3143
3144                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
3145                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
3146         }
3147
3148         return true;
3149 }
3150
3151 enum ath9k_int ath9k_hw_intrget(struct ath_hw *ah)
3152 {
3153         return ah->mask_reg;
3154 }
3155
3156 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3157 {
3158         u32 omask = ah->mask_reg;
3159         u32 mask, mask2;
3160         struct ath9k_hw_capabilities *pCap = &ah->caps;
3161
3162         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
3163
3164         if (omask & ATH9K_INT_GLOBAL) {
3165                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
3166                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3167                 (void) REG_READ(ah, AR_IER);
3168                 if (!AR_SREV_9100(ah)) {
3169                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3170                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3171
3172                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3173                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3174                 }
3175         }
3176
3177         mask = ints & ATH9K_INT_COMMON;
3178         mask2 = 0;
3179
3180         if (ints & ATH9K_INT_TX) {
3181                 if (ah->txok_interrupt_mask)
3182                         mask |= AR_IMR_TXOK;
3183                 if (ah->txdesc_interrupt_mask)
3184                         mask |= AR_IMR_TXDESC;
3185                 if (ah->txerr_interrupt_mask)
3186                         mask |= AR_IMR_TXERR;
3187                 if (ah->txeol_interrupt_mask)
3188                         mask |= AR_IMR_TXEOL;
3189         }
3190         if (ints & ATH9K_INT_RX) {
3191                 mask |= AR_IMR_RXERR;
3192                 if (ah->config.intr_mitigation)
3193                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3194                 else
3195                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3196                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3197                         mask |= AR_IMR_GENTMR;
3198         }
3199
3200         if (ints & (ATH9K_INT_BMISC)) {
3201                 mask |= AR_IMR_BCNMISC;
3202                 if (ints & ATH9K_INT_TIM)
3203                         mask2 |= AR_IMR_S2_TIM;
3204                 if (ints & ATH9K_INT_DTIM)
3205                         mask2 |= AR_IMR_S2_DTIM;
3206                 if (ints & ATH9K_INT_DTIMSYNC)
3207                         mask2 |= AR_IMR_S2_DTIMSYNC;
3208                 if (ints & ATH9K_INT_CABEND)
3209                         mask2 |= AR_IMR_S2_CABEND;
3210                 if (ints & ATH9K_INT_TSFOOR)
3211                         mask2 |= AR_IMR_S2_TSFOOR;
3212         }
3213
3214         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3215                 mask |= AR_IMR_BCNMISC;
3216                 if (ints & ATH9K_INT_GTT)
3217                         mask2 |= AR_IMR_S2_GTT;
3218                 if (ints & ATH9K_INT_CST)
3219                         mask2 |= AR_IMR_S2_CST;
3220         }
3221
3222         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3223         REG_WRITE(ah, AR_IMR, mask);
3224         mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3225                                            AR_IMR_S2_DTIM |
3226                                            AR_IMR_S2_DTIMSYNC |
3227                                            AR_IMR_S2_CABEND |
3228                                            AR_IMR_S2_CABTO |
3229                                            AR_IMR_S2_TSFOOR |
3230                                            AR_IMR_S2_GTT | AR_IMR_S2_CST);
3231         REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3232         ah->mask_reg = ints;
3233
3234         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3235                 if (ints & ATH9K_INT_TIM_TIMER)
3236                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3237                 else
3238                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3239         }
3240
3241         if (ints & ATH9K_INT_GLOBAL) {
3242                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
3243                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3244                 if (!AR_SREV_9100(ah)) {
3245                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3246                                   AR_INTR_MAC_IRQ);
3247                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3248
3249
3250                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3251                                   AR_INTR_SYNC_DEFAULT);
3252                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
3253                                   AR_INTR_SYNC_DEFAULT);
3254                 }
3255                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3256                          REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3257         }
3258
3259         return omask;
3260 }
3261
3262 /*******************/
3263 /* Beacon Handling */
3264 /*******************/
3265
3266 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3267 {
3268         int flags = 0;
3269
3270         ah->beacon_interval = beacon_period;
3271
3272         switch (ah->opmode) {
3273         case NL80211_IFTYPE_STATION:
3274         case NL80211_IFTYPE_MONITOR:
3275                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3276                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3277                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3278                 flags |= AR_TBTT_TIMER_EN;
3279                 break;
3280         case NL80211_IFTYPE_ADHOC:
3281         case NL80211_IFTYPE_MESH_POINT:
3282                 REG_SET_BIT(ah, AR_TXCFG,
3283                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3284                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3285                           TU_TO_USEC(next_beacon +
3286                                      (ah->atim_window ? ah->
3287                                       atim_window : 1)));
3288                 flags |= AR_NDP_TIMER_EN;
3289         case NL80211_IFTYPE_AP:
3290                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3291                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3292                           TU_TO_USEC(next_beacon -
3293                                      ah->config.
3294                                      dma_beacon_response_time));
3295                 REG_WRITE(ah, AR_NEXT_SWBA,
3296                           TU_TO_USEC(next_beacon -
3297                                      ah->config.
3298                                      sw_beacon_response_time));
3299                 flags |=
3300                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3301                 break;
3302         default:
3303                 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3304                         "%s: unsupported opmode: %d\n",
3305                         __func__, ah->opmode);
3306                 return;
3307                 break;
3308         }
3309
3310         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3311         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3312         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3313         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3314
3315         beacon_period &= ~ATH9K_BEACON_ENA;
3316         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3317                 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3318                 ath9k_hw_reset_tsf(ah);
3319         }
3320
3321         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3322 }
3323
3324 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3325                                     const struct ath9k_beacon_state *bs)
3326 {
3327         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3328         struct ath9k_hw_capabilities *pCap = &ah->caps;
3329
3330         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3331
3332         REG_WRITE(ah, AR_BEACON_PERIOD,
3333                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3334         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3335                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3336
3337         REG_RMW_FIELD(ah, AR_RSSI_THR,
3338                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3339
3340         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3341
3342         if (bs->bs_sleepduration > beaconintval)
3343                 beaconintval = bs->bs_sleepduration;
3344
3345         dtimperiod = bs->bs_dtimperiod;
3346         if (bs->bs_sleepduration > dtimperiod)
3347                 dtimperiod = bs->bs_sleepduration;
3348
3349         if (beaconintval == dtimperiod)
3350                 nextTbtt = bs->bs_nextdtim;
3351         else
3352                 nextTbtt = bs->bs_nexttbtt;
3353
3354         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3355         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3356         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3357         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3358
3359         REG_WRITE(ah, AR_NEXT_DTIM,
3360                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3361         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3362
3363         REG_WRITE(ah, AR_SLEEP1,
3364                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3365                   | AR_SLEEP1_ASSUME_DTIM);
3366
3367         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3368                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3369         else
3370                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3371
3372         REG_WRITE(ah, AR_SLEEP2,
3373                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3374
3375         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3376         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3377
3378         REG_SET_BIT(ah, AR_TIMER_MODE,
3379                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3380                     AR_DTIM_TIMER_EN);
3381
3382         /* TSF Out of Range Threshold */
3383         REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3384 }
3385
3386 /*******************/
3387 /* HW Capabilities */
3388 /*******************/
3389
3390 void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3391 {
3392         struct ath9k_hw_capabilities *pCap = &ah->caps;
3393         u16 capField = 0, eeval;
3394
3395         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3396         ah->regulatory.current_rd = eeval;
3397
3398         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3399         if (AR_SREV_9285_10_OR_LATER(ah))
3400                 eeval |= AR9285_RDEXT_DEFAULT;
3401         ah->regulatory.current_rd_ext = eeval;
3402
3403         capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3404
3405         if (ah->opmode != NL80211_IFTYPE_AP &&
3406             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3407                 if (ah->regulatory.current_rd == 0x64 ||
3408                     ah->regulatory.current_rd == 0x65)
3409                         ah->regulatory.current_rd += 5;
3410                 else if (ah->regulatory.current_rd == 0x41)
3411                         ah->regulatory.current_rd = 0x43;
3412                 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3413                         "regdomain mapped to 0x%x\n", ah->regulatory.current_rd);
3414         }
3415
3416         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3417         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3418
3419         if (eeval & AR5416_OPFLAGS_11A) {
3420                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3421                 if (ah->config.ht_enable) {
3422                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3423                                 set_bit(ATH9K_MODE_11NA_HT20,
3424                                         pCap->wireless_modes);
3425                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3426                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3427                                         pCap->wireless_modes);
3428                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3429                                         pCap->wireless_modes);
3430                         }
3431                 }
3432         }
3433
3434         if (eeval & AR5416_OPFLAGS_11G) {
3435                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3436                 if (ah->config.ht_enable) {
3437                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3438                                 set_bit(ATH9K_MODE_11NG_HT20,
3439                                         pCap->wireless_modes);
3440                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3441                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3442                                         pCap->wireless_modes);
3443                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3444                                         pCap->wireless_modes);
3445                         }
3446                 }
3447         }
3448
3449         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3450         if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3451             !(eeval & AR5416_OPFLAGS_11A))
3452                 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3453         else
3454                 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3455
3456         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3457                 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3458
3459         pCap->low_2ghz_chan = 2312;
3460         pCap->high_2ghz_chan = 2732;
3461
3462         pCap->low_5ghz_chan = 4920;
3463         pCap->high_5ghz_chan = 6100;
3464
3465         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3466         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3467         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3468
3469         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3470         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3471         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3472
3473         if (ah->config.ht_enable)
3474                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3475         else
3476                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3477
3478         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3479         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3480         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3481         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3482
3483         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3484                 pCap->total_queues =
3485                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3486         else
3487                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3488
3489         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3490                 pCap->keycache_size =
3491                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3492         else
3493                 pCap->keycache_size = AR_KEYTABLE_SIZE;
3494
3495         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3496         pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3497
3498         if (AR_SREV_9285_10_OR_LATER(ah))
3499                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3500         else if (AR_SREV_9280_10_OR_LATER(ah))
3501                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3502         else
3503                 pCap->num_gpio_pins = AR_NUM_GPIO;
3504
3505         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3506                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3507                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3508         } else {
3509                 pCap->rts_aggr_limit = (8 * 1024);
3510         }
3511
3512         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3513
3514 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3515         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3516         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3517                 ah->rfkill_gpio =
3518                         MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3519                 ah->rfkill_polarity =
3520                         MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3521
3522                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3523         }
3524 #endif
3525
3526         if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) ||
3527             (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ||
3528             (ah->hw_version.macVersion == AR_SREV_VERSION_9160) ||
3529             (ah->hw_version.macVersion == AR_SREV_VERSION_9100) ||
3530             (ah->hw_version.macVersion == AR_SREV_VERSION_9280) ||
3531             (ah->hw_version.macVersion == AR_SREV_VERSION_9285))
3532                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3533         else
3534                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3535
3536         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3537                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3538         else
3539                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3540
3541         if (ah->regulatory.current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3542                 pCap->reg_cap =
3543                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3544                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3545                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3546                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3547         } else {
3548                 pCap->reg_cap =
3549                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3550                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3551         }
3552
3553         pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3554
3555         pCap->num_antcfg_5ghz =
3556                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3557         pCap->num_antcfg_2ghz =
3558                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3559
3560         if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
3561                 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
3562                 ah->btactive_gpio = 6;
3563                 ah->wlanactive_gpio = 5;
3564         }
3565 }
3566
3567 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3568                             u32 capability, u32 *result)
3569 {
3570         switch (type) {
3571         case ATH9K_CAP_CIPHER:
3572                 switch (capability) {
3573                 case ATH9K_CIPHER_AES_CCM:
3574                 case ATH9K_CIPHER_AES_OCB:
3575                 case ATH9K_CIPHER_TKIP:
3576                 case ATH9K_CIPHER_WEP:
3577                 case ATH9K_CIPHER_MIC:
3578                 case ATH9K_CIPHER_CLR:
3579                         return true;
3580                 default:
3581                         return false;
3582                 }
3583         case ATH9K_CAP_TKIP_MIC:
3584                 switch (capability) {
3585                 case 0:
3586                         return true;
3587                 case 1:
3588                         return (ah->sta_id1_defaults &
3589                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3590                         false;
3591                 }
3592         case ATH9K_CAP_TKIP_SPLIT:
3593                 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3594                         false : true;
3595         case ATH9K_CAP_DIVERSITY:
3596                 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3597                         AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3598                         true : false;
3599         case ATH9K_CAP_MCAST_KEYSRCH:
3600                 switch (capability) {
3601                 case 0:
3602                         return true;
3603                 case 1:
3604                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3605                                 return false;
3606                         } else {
3607                                 return (ah->sta_id1_defaults &
3608                                         AR_STA_ID1_MCAST_KSRCH) ? true :
3609                                         false;
3610                         }
3611                 }
3612                 return false;
3613         case ATH9K_CAP_TXPOW:
3614                 switch (capability) {
3615                 case 0:
3616                         return 0;
3617                 case 1:
3618                         *result = ah->regulatory.power_limit;
3619                         return 0;
3620                 case 2:
3621                         *result = ah->regulatory.max_power_level;
3622                         return 0;
3623                 case 3:
3624                         *result = ah->regulatory.tp_scale;
3625                         return 0;
3626                 }
3627                 return false;
3628         case ATH9K_CAP_DS:
3629                 return (AR_SREV_9280_20_OR_LATER(ah) &&
3630                         (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3631                         ? false : true;
3632         default:
3633                 return false;
3634         }
3635 }
3636
3637 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3638                             u32 capability, u32 setting, int *status)
3639 {
3640         u32 v;
3641
3642         switch (type) {
3643         case ATH9K_CAP_TKIP_MIC:
3644                 if (setting)
3645                         ah->sta_id1_defaults |=
3646                                 AR_STA_ID1_CRPT_MIC_ENABLE;
3647                 else
3648                         ah->sta_id1_defaults &=
3649                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3650                 return true;
3651         case ATH9K_CAP_DIVERSITY:
3652                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3653                 if (setting)
3654                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3655                 else
3656                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3657                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3658                 return true;
3659         case ATH9K_CAP_MCAST_KEYSRCH:
3660                 if (setting)
3661                         ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3662                 else
3663                         ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3664                 return true;
3665         default:
3666                 return false;
3667         }
3668 }
3669
3670 /****************************/
3671 /* GPIO / RFKILL / Antennae */
3672 /****************************/
3673
3674 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3675                                          u32 gpio, u32 type)
3676 {
3677         int addr;
3678         u32 gpio_shift, tmp;
3679
3680         if (gpio > 11)
3681                 addr = AR_GPIO_OUTPUT_MUX3;
3682         else if (gpio > 5)
3683                 addr = AR_GPIO_OUTPUT_MUX2;
3684         else
3685                 addr = AR_GPIO_OUTPUT_MUX1;
3686
3687         gpio_shift = (gpio % 6) * 5;
3688
3689         if (AR_SREV_9280_20_OR_LATER(ah)
3690             || (addr != AR_GPIO_OUTPUT_MUX1)) {
3691                 REG_RMW(ah, addr, (type << gpio_shift),
3692                         (0x1f << gpio_shift));
3693         } else {
3694                 tmp = REG_READ(ah, addr);
3695                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3696                 tmp &= ~(0x1f << gpio_shift);
3697                 tmp |= (type << gpio_shift);
3698                 REG_WRITE(ah, addr, tmp);
3699         }
3700 }
3701
3702 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3703 {
3704         u32 gpio_shift;
3705
3706         ASSERT(gpio < ah->caps.num_gpio_pins);
3707
3708         gpio_shift = gpio << 1;
3709
3710         REG_RMW(ah,
3711                 AR_GPIO_OE_OUT,
3712                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3713                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3714 }
3715
3716 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3717 {
3718 #define MS_REG_READ(x, y) \
3719         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3720
3721         if (gpio >= ah->caps.num_gpio_pins)
3722                 return 0xffffffff;
3723
3724         if (AR_SREV_9287_10_OR_LATER(ah))
3725                 return MS_REG_READ(AR9287, gpio) != 0;
3726         else if (AR_SREV_9285_10_OR_LATER(ah))
3727                 return MS_REG_READ(AR9285, gpio) != 0;
3728         else if (AR_SREV_9280_10_OR_LATER(ah))
3729                 return MS_REG_READ(AR928X, gpio) != 0;
3730         else
3731                 return MS_REG_READ(AR, gpio) != 0;
3732 }
3733
3734 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3735                          u32 ah_signal_type)
3736 {
3737         u32 gpio_shift;
3738
3739         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3740
3741         gpio_shift = 2 * gpio;
3742
3743         REG_RMW(ah,
3744                 AR_GPIO_OE_OUT,
3745                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3746                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3747 }
3748
3749 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3750 {
3751         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3752                 AR_GPIO_BIT(gpio));
3753 }
3754
3755 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3756 {
3757         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3758 }
3759
3760 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3761 {
3762         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3763 }
3764
3765 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3766                                enum ath9k_ant_setting settings,
3767                                struct ath9k_channel *chan,
3768                                u8 *tx_chainmask,
3769                                u8 *rx_chainmask,
3770                                u8 *antenna_cfgd)
3771 {
3772         static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3773
3774         if (AR_SREV_9280(ah)) {
3775                 if (!tx_chainmask_cfg) {
3776
3777                         tx_chainmask_cfg = *tx_chainmask;
3778                         rx_chainmask_cfg = *rx_chainmask;
3779                 }
3780
3781                 switch (settings) {
3782                 case ATH9K_ANT_FIXED_A:
3783                         *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3784                         *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3785                         *antenna_cfgd = true;
3786                         break;
3787                 case ATH9K_ANT_FIXED_B:
3788                         if (ah->caps.tx_chainmask >
3789                             ATH9K_ANTENNA1_CHAINMASK) {
3790                                 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3791                         }
3792                         *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3793                         *antenna_cfgd = true;
3794                         break;
3795                 case ATH9K_ANT_VARIABLE:
3796                         *tx_chainmask = tx_chainmask_cfg;
3797                         *rx_chainmask = rx_chainmask_cfg;
3798                         *antenna_cfgd = true;
3799                         break;
3800                 default:
3801                         break;
3802                 }
3803         } else {
3804                 ah->diversity_control = settings;
3805         }
3806
3807         return true;
3808 }
3809
3810 /*********************/
3811 /* General Operation */
3812 /*********************/
3813
3814 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3815 {
3816         u32 bits = REG_READ(ah, AR_RX_FILTER);
3817         u32 phybits = REG_READ(ah, AR_PHY_ERR);
3818
3819         if (phybits & AR_PHY_ERR_RADAR)
3820                 bits |= ATH9K_RX_FILTER_PHYRADAR;
3821         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3822                 bits |= ATH9K_RX_FILTER_PHYERR;
3823
3824         return bits;
3825 }
3826
3827 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3828 {
3829         u32 phybits;
3830
3831         REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3832         phybits = 0;
3833         if (bits & ATH9K_RX_FILTER_PHYRADAR)
3834                 phybits |= AR_PHY_ERR_RADAR;
3835         if (bits & ATH9K_RX_FILTER_PHYERR)
3836                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3837         REG_WRITE(ah, AR_PHY_ERR, phybits);
3838
3839         if (phybits)
3840                 REG_WRITE(ah, AR_RXCFG,
3841                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3842         else
3843                 REG_WRITE(ah, AR_RXCFG,
3844                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3845 }
3846
3847 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3848 {
3849         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3850 }
3851
3852 bool ath9k_hw_disable(struct ath_hw *ah)
3853 {
3854         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3855                 return false;
3856
3857         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3858 }
3859
3860 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3861 {
3862         struct ath9k_channel *chan = ah->curchan;
3863         struct ieee80211_channel *channel = chan->chan;
3864
3865         ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER);
3866
3867         ah->eep_ops->set_txpower(ah, chan,
3868                                  ath9k_regd_get_ctl(&ah->regulatory, chan),
3869                                  channel->max_antenna_gain * 2,
3870                                  channel->max_power * 2,
3871                                  min((u32) MAX_RATE_POWER,
3872                                  (u32) ah->regulatory.power_limit));
3873 }
3874
3875 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3876 {
3877         memcpy(ah->macaddr, mac, ETH_ALEN);
3878 }
3879
3880 void ath9k_hw_setopmode(struct ath_hw *ah)
3881 {
3882         ath9k_hw_set_operating_mode(ah, ah->opmode);
3883 }
3884
3885 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3886 {
3887         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3888         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3889 }
3890
3891 void ath9k_hw_setbssidmask(struct ath_softc *sc)
3892 {
3893         REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
3894         REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
3895 }
3896
3897 void ath9k_hw_write_associd(struct ath_softc *sc)
3898 {
3899         REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
3900         REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
3901                   ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3902 }
3903
3904 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3905 {
3906         u64 tsf;
3907
3908         tsf = REG_READ(ah, AR_TSF_U32);
3909         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3910
3911         return tsf;
3912 }
3913
3914 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3915 {
3916         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3917         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3918 }
3919
3920 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3921 {
3922         ath9k_ps_wakeup(ah->ah_sc);
3923         if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3924                            AH_TSF_WRITE_TIMEOUT))
3925                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3926                         "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3927
3928         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3929         ath9k_ps_restore(ah->ah_sc);
3930 }
3931
3932 bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3933 {
3934         if (setting)
3935                 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3936         else
3937                 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3938
3939         return true;
3940 }
3941
3942 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
3943 {
3944         if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3945                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3946                 ah->slottime = (u32) -1;
3947                 return false;
3948         } else {
3949                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3950                 ah->slottime = us;
3951                 return true;
3952         }
3953 }
3954
3955 void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
3956 {
3957         u32 macmode;
3958
3959         if (mode == ATH9K_HT_MACMODE_2040 &&
3960             !ah->config.cwm_ignore_extcca)
3961                 macmode = AR_2040_JOINED_RX_CLEAR;
3962         else
3963                 macmode = 0;
3964
3965         REG_WRITE(ah, AR_2040_MODE, macmode);
3966 }
3967
3968 /***************************/
3969 /*  Bluetooth Coexistence  */
3970 /***************************/
3971
3972 void ath9k_hw_btcoex_enable(struct ath_hw *ah)
3973 {
3974         /* connect bt_active to baseband */
3975         REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3976                         (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
3977                          AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
3978
3979         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3980                         AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
3981
3982         /* Set input mux for bt_active to gpio pin */
3983         REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
3984                         AR_GPIO_INPUT_MUX1_BT_ACTIVE,
3985                         ah->btactive_gpio);
3986
3987         /* Configure the desired gpio port for input */
3988         ath9k_hw_cfg_gpio_input(ah, ah->btactive_gpio);
3989
3990         /* Configure the desired GPIO port for TX_FRAME output */
3991         ath9k_hw_cfg_output(ah, ah->wlanactive_gpio,
3992                             AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
3993 }