2 * Copyright (c) 2010-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/export.h>
19 #include "ar9003_phy.h"
21 static const int firstep_table[] =
22 /* level: 0 1 2 3 4 5 6 7 8 */
23 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
25 static const int cycpwrThr1_table[] =
26 /* level: 0 1 2 3 4 5 6 7 8 */
27 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
30 * register values to turn OFDM weak signal detection OFF
32 static const int m1ThreshLow_off = 127;
33 static const int m2ThreshLow_off = 127;
34 static const int m1Thresh_off = 127;
35 static const int m2Thresh_off = 127;
36 static const int m2CountThr_off = 31;
37 static const int m2CountThrLow_off = 63;
38 static const int m1ThreshLowExt_off = 127;
39 static const int m2ThreshLowExt_off = 127;
40 static const int m1ThreshExt_off = 127;
41 static const int m2ThreshExt_off = 127;
44 * ar9003_hw_set_channel - set channel on single-chip device
45 * @ah: atheros hardware structure
48 * This is the function to change channel on single-chip devices, that is
49 * for AR9300 family of chipsets.
51 * This function takes the channel value in MHz and sets
52 * hardware channel value. Assumes writes have been enabled to analog bus.
57 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
61 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
62 * (freq_ref = 40MHz/(24>>amodeRefSel))
64 * For 5GHz channels which are 5MHz spaced,
65 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
68 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
70 u16 bMode, fracMode = 0, aModeRefSel = 0;
71 u32 freq, chan_frac, div, channelSel = 0, reg32 = 0;
72 struct chan_centers centers;
75 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
76 freq = centers.synth_center;
78 if (freq < 4800) { /* 2 GHz, fractional mode */
79 if (AR_SREV_9330(ah)) {
85 channelSel = (freq * 4) / div;
86 chan_frac = (((freq * 4) % div) * 0x20000) / div;
87 channelSel = (channelSel << 17) | chan_frac;
88 } else if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
90 * freq_ref = 40 / (refdiva >> amoderefsel);
91 * where refdiva=1 and amoderefsel=0
92 * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
93 * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
95 channelSel = (freq * 4) / 120;
96 chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
97 channelSel = (channelSel << 17) | chan_frac;
98 } else if (AR_SREV_9340(ah)) {
99 if (ah->is_clk_25mhz) {
100 channelSel = (freq * 2) / 75;
101 chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
102 channelSel = (channelSel << 17) | chan_frac;
104 channelSel = CHANSEL_2G(freq) >> 1;
106 } else if (AR_SREV_9550(ah)) {
107 if (ah->is_clk_25mhz)
112 channelSel = (freq * 4) / div;
113 chan_frac = (((freq * 4) % div) * 0x20000) / div;
114 channelSel = (channelSel << 17) | chan_frac;
116 channelSel = CHANSEL_2G(freq);
121 if ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) &&
123 channelSel = freq / 75;
124 chan_frac = ((freq % 75) * 0x20000) / 75;
125 channelSel = (channelSel << 17) | chan_frac;
127 channelSel = CHANSEL_5G(freq);
128 /* Doubler is ON, so, divide channelSel by 2. */
135 /* Enable fractional mode for all channels */
138 loadSynthChannel = 0;
140 reg32 = (bMode << 29);
141 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
143 /* Enable Long shift Select for Synthesizer */
144 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
145 AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
147 /* Program Synth. setting */
148 reg32 = (channelSel << 2) | (fracMode << 30) |
149 (aModeRefSel << 28) | (loadSynthChannel << 31);
150 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
152 /* Toggle Load Synth channel bit */
153 loadSynthChannel = 1;
154 reg32 = (channelSel << 2) | (fracMode << 30) |
155 (aModeRefSel << 28) | (loadSynthChannel << 31);
156 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
164 * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
165 * @ah: atheros hardware structure
168 * For single-chip solutions. Converts to baseband spur frequency given the
169 * input channel frequency and compute register settings below.
171 * Spur mitigation for MRC CCK
173 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
174 struct ath9k_channel *chan)
176 static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
177 int cur_bb_spur, negative = 0, cck_spur_freq;
179 int range, max_spur_cnts, synth_freq;
180 u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan));
183 * Need to verify range +/- 10 MHz in control channel, otherwise spur
184 * is out-of-band and can be ignored.
187 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
189 if (spur_fbin_ptr[0] == 0) /* No spur */
192 if (IS_CHAN_HT40(chan)) {
194 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
195 AR_PHY_GC_DYN2040_PRI_CH) == 0)
196 synth_freq = chan->channel + 10;
198 synth_freq = chan->channel - 10;
201 synth_freq = chan->channel;
204 range = AR_SREV_9462(ah) ? 5 : 10;
206 synth_freq = chan->channel;
209 for (i = 0; i < max_spur_cnts; i++) {
210 if (AR_SREV_9462(ah) && (i == 0 || i == 3))
214 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
216 cur_bb_spur = ath9k_hw_fbin2freq(spur_fbin_ptr[i],
219 cur_bb_spur = spur_freq[i];
221 cur_bb_spur -= synth_freq;
222 if (cur_bb_spur < 0) {
224 cur_bb_spur = -cur_bb_spur;
226 if (cur_bb_spur < range) {
227 cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
230 cck_spur_freq = -cck_spur_freq;
232 cck_spur_freq = cck_spur_freq & 0xfffff;
234 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
235 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
236 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
237 AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
238 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
239 AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
241 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
242 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
244 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
245 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
252 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
253 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
254 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
255 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
256 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
257 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
260 /* Clean all spur register fields */
261 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
263 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
264 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
265 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
266 AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
267 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
268 AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
269 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
270 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
271 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
272 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
273 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
274 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
275 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
276 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
277 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
278 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
279 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
280 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
282 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
283 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
284 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
285 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
286 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
287 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
288 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
289 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
290 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
291 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
292 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
293 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
294 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
295 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
296 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
297 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
298 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
299 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
300 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
301 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
304 static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
307 int spur_delta_phase,
308 int spur_subchannel_sd,
314 /* OFDM Spur mitigation */
315 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
316 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
317 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
318 AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
319 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
320 AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
321 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
322 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
323 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
324 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
326 if (!(AR_SREV_9565(ah) && range == 10 && synth_freq == 2437))
327 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
328 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
330 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
331 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
332 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
333 AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
334 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
335 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
337 if (!AR_SREV_9340(ah) &&
338 REG_READ_FIELD(ah, AR_PHY_MODE,
339 AR_PHY_MODE_DYNAMIC) == 0x1)
340 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
341 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
343 mask_index = (freq_offset << 4) / 5;
345 mask_index = mask_index - 1;
347 mask_index = mask_index & 0x7f;
349 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
350 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
351 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
352 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
353 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
354 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
355 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
356 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
357 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
358 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
359 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
360 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
361 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
362 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
363 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
364 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
365 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
366 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
367 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
368 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
371 static void ar9003_hw_spur_ofdm_9565(struct ath_hw *ah,
376 mask_index = (freq_offset << 4) / 5;
378 mask_index = mask_index - 1;
380 mask_index = mask_index & 0x7f;
382 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
383 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B,
387 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
388 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A,
391 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
392 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B,
394 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
395 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B, 0xe);
396 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
397 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B, 0xe);
400 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
401 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
404 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
405 struct ath9k_channel *chan,
410 int spur_freq_sd = 0;
411 int spur_subchannel_sd = 0;
412 int spur_delta_phase = 0;
414 if (IS_CHAN_HT40(chan)) {
415 if (freq_offset < 0) {
416 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
417 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
418 spur_subchannel_sd = 1;
420 spur_subchannel_sd = 0;
422 spur_freq_sd = ((freq_offset + 10) << 9) / 11;
425 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
426 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
427 spur_subchannel_sd = 0;
429 spur_subchannel_sd = 1;
431 spur_freq_sd = ((freq_offset - 10) << 9) / 11;
435 spur_delta_phase = (freq_offset << 17) / 5;
438 spur_subchannel_sd = 0;
439 spur_freq_sd = (freq_offset << 9) /11;
440 spur_delta_phase = (freq_offset << 18) / 5;
443 spur_freq_sd = spur_freq_sd & 0x3ff;
444 spur_delta_phase = spur_delta_phase & 0xfffff;
446 ar9003_hw_spur_ofdm(ah,
454 /* Spur mitigation for OFDM */
455 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
456 struct ath9k_channel *chan)
464 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
466 if (IS_CHAN_5GHZ(chan)) {
467 spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
471 spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
475 if (spurChansPtr[0] == 0)
476 return; /* No spur in the mode */
478 if (IS_CHAN_HT40(chan)) {
480 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
481 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
482 synth_freq = chan->channel - 10;
484 synth_freq = chan->channel + 10;
487 synth_freq = chan->channel;
490 ar9003_hw_spur_ofdm_clear(ah);
492 for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
493 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i], mode);
494 freq_offset -= synth_freq;
495 if (abs(freq_offset) < range) {
496 ar9003_hw_spur_ofdm_work(ah, chan, freq_offset,
499 if (AR_SREV_9565(ah) && (i < 4)) {
500 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i + 1],
502 freq_offset -= synth_freq;
503 if (abs(freq_offset) < range)
504 ar9003_hw_spur_ofdm_9565(ah, freq_offset);
512 static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
513 struct ath9k_channel *chan)
515 if (!AR_SREV_9565(ah))
516 ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
517 ar9003_hw_spur_mitigate_ofdm(ah, chan);
520 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
521 struct ath9k_channel *chan)
525 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
527 if (chan && IS_CHAN_HALF_RATE(chan))
528 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
529 else if (chan && IS_CHAN_QUARTER_RATE(chan))
530 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
532 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
537 static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
538 struct ath9k_channel *chan)
541 u32 enableDacFifo = 0;
544 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
546 /* Enable 11n HT, 20 MHz */
547 phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 |
548 AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
550 /* Configure baseband for dynamic 20/40 operation */
551 if (IS_CHAN_HT40(chan)) {
552 phymode |= AR_PHY_GC_DYN2040_EN;
553 /* Configure control (primary) channel at +-10MHz */
554 if (IS_CHAN_HT40PLUS(chan))
555 phymode |= AR_PHY_GC_DYN2040_PRI_CH;
559 /* make sure we preserve INI settings */
560 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
561 /* turn off Green Field detection for STA for now */
562 phymode &= ~AR_PHY_GC_GF_DETECT_EN;
564 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
566 /* Configure MAC for 20/40 operation */
567 ath9k_hw_set11nmac2040(ah);
569 /* global transmit timeout (25 TUs default)*/
570 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
571 /* carrier sense timeout */
572 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
575 static void ar9003_hw_init_bb(struct ath_hw *ah,
576 struct ath9k_channel *chan)
581 * Wait for the frequency synth to settle (synth goes on
582 * via AR_PHY_ACTIVE_EN). Read the phy active delay register.
583 * Value is in 100ns increments.
585 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
587 /* Activate the PHY (includes baseband activate + synthesizer on) */
588 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
589 ath9k_hw_synth_delay(ah, chan, synthDelay);
592 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
594 if (ah->caps.tx_chainmask == 5 || ah->caps.rx_chainmask == 5)
595 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
596 AR_PHY_SWAP_ALT_CHAIN);
598 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
599 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
601 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
604 REG_WRITE(ah, AR_SELFGEN_MASK, tx);
608 * Override INI values with chip specific configuration.
610 static void ar9003_hw_override_ini(struct ath_hw *ah)
615 * Set the RX_ABORT and RX_DIS and clear it only after
616 * RXE is set for MAC. This prevents frames with
617 * corrupted descriptor status.
619 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
622 * For AR9280 and above, there is a new feature that allows
623 * Multicast search based on both MAC Address and Key ID. By default,
624 * this feature is enabled. But since the driver is not using this
625 * feature, we switch it off; otherwise multicast search based on
626 * MAC addr only will fail.
628 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
629 val |= AR_AGG_WEP_ENABLE_FIX |
631 AR_PCU_MISC_MODE2_CFP_IGNORE;
632 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
634 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
635 REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,
636 AR_GLB_SWREG_DISCONT_EN_BT_WLAN);
638 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
639 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))
640 ah->enabled_cals |= TX_IQ_CAL;
642 ah->enabled_cals &= ~TX_IQ_CAL;
644 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
645 ah->enabled_cals |= TX_CL_CAL;
647 ah->enabled_cals &= ~TX_CL_CAL;
651 static void ar9003_hw_prog_ini(struct ath_hw *ah,
652 struct ar5416IniArray *iniArr,
655 unsigned int i, regWrites = 0;
657 /* New INI format: Array may be undefined (pre, core, post arrays) */
658 if (!iniArr->ia_array)
662 * New INI format: Pre, core, and post arrays for a given subsystem
663 * may be modal (> 2 columns) or non-modal (2 columns). Determine if
664 * the array is non-modal and force the column to 1.
666 if (column >= iniArr->ia_columns)
669 for (i = 0; i < iniArr->ia_rows; i++) {
670 u32 reg = INI_RA(iniArr, i, 0);
671 u32 val = INI_RA(iniArr, i, column);
673 REG_WRITE(ah, reg, val);
679 static int ar9550_hw_get_modes_txgain_index(struct ath_hw *ah,
680 struct ath9k_channel *chan)
684 if (IS_CHAN_2GHZ(chan)) {
685 if (IS_CHAN_HT40(chan))
691 if (chan->channel <= 5350)
693 else if ((chan->channel > 5350) && (chan->channel <= 5600))
698 if (IS_CHAN_HT40(chan))
704 static int ar9003_hw_process_ini(struct ath_hw *ah,
705 struct ath9k_channel *chan)
707 unsigned int regWrites = 0, i;
710 if (IS_CHAN_5GHZ(chan))
711 modesIndex = IS_CHAN_HT40(chan) ? 2 : 1;
713 modesIndex = IS_CHAN_HT40(chan) ? 3 : 4;
716 * SOC, MAC, BB, RADIO initvals.
718 for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
719 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
720 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
721 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
722 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
723 if (i == ATH_INI_POST && AR_SREV_9462_20_OR_LATER(ah))
724 ar9003_hw_prog_ini(ah,
725 &ah->ini_radio_post_sys2ant,
732 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
734 if (AR_SREV_9462_20_OR_LATER(ah)) {
736 * CUS217 mix LNA mode.
738 if (ar9003_hw_get_rx_gain_idx(ah) == 2) {
739 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core,
741 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
742 modesIndex, regWrites);
748 if ((ar9003_hw_get_rx_gain_idx(ah) == 2) ||
749 (ar9003_hw_get_rx_gain_idx(ah) == 3)) {
750 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
751 modesIndex, regWrites);
755 if (AR_SREV_9550(ah))
756 REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex,
762 if (AR_SREV_9550(ah)) {
763 int modes_txgain_index;
765 modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan);
766 if (modes_txgain_index < 0)
769 REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index,
772 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
776 * For 5GHz channels requiring Fast Clock, apply
777 * different modal values.
779 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
780 REG_WRITE_ARRAY(&ah->iniModesFastClock,
781 modesIndex, regWrites);
784 * Clock frequency initvals.
786 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
791 if (chan->channel == 2484)
792 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
794 ah->modes_index = modesIndex;
795 ar9003_hw_override_ini(ah);
796 ar9003_hw_set_channel_regs(ah, chan);
797 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
798 ath9k_hw_apply_txpower(ah, chan, false);
803 static void ar9003_hw_set_rfmode(struct ath_hw *ah,
804 struct ath9k_channel *chan)
811 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
812 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
814 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
815 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
816 if (IS_CHAN_QUARTER_RATE(chan))
817 rfMode |= AR_PHY_MODE_QUARTER;
818 if (IS_CHAN_HALF_RATE(chan))
819 rfMode |= AR_PHY_MODE_HALF;
821 if (rfMode & (AR_PHY_MODE_QUARTER | AR_PHY_MODE_HALF))
822 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
823 AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW, 3);
825 REG_WRITE(ah, AR_PHY_MODE, rfMode);
828 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
830 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
833 static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
834 struct ath9k_channel *chan)
836 u32 coef_scaled, ds_coef_exp, ds_coef_man;
837 u32 clockMhzScaled = 0x64000000;
838 struct chan_centers centers;
841 * half and quarter rate can divide the scaled clock by 2 or 4
842 * scale for selected channel bandwidth
844 if (IS_CHAN_HALF_RATE(chan))
845 clockMhzScaled = clockMhzScaled >> 1;
846 else if (IS_CHAN_QUARTER_RATE(chan))
847 clockMhzScaled = clockMhzScaled >> 2;
850 * ALGO -> coef = 1e8/fcarrier*fclock/40;
851 * scaled coef to provide precision for this floating calculation
853 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
854 coef_scaled = clockMhzScaled / centers.synth_center;
856 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
859 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
860 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
861 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
862 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
866 * scaled coeff is 9/10 that of normal coeff
868 coef_scaled = (9 * coef_scaled) / 10;
870 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
874 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
875 AR_PHY_SGI_DSC_MAN, ds_coef_man);
876 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
877 AR_PHY_SGI_DSC_EXP, ds_coef_exp);
880 static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
882 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
883 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
884 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
888 * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
889 * Read the phy active delay register. Value is in 100ns increments.
891 static void ar9003_hw_rfbus_done(struct ath_hw *ah)
893 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
895 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay);
897 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
900 static bool ar9003_hw_ani_control(struct ath_hw *ah,
901 enum ath9k_ani_cmd cmd, int param)
903 struct ath_common *common = ath9k_hw_common(ah);
904 struct ath9k_channel *chan = ah->curchan;
905 struct ar5416AniState *aniState = &ah->ani;
906 int m1ThreshLow, m2ThreshLow;
907 int m1Thresh, m2Thresh;
908 int m2CountThr, m2CountThrLow;
909 int m1ThreshLowExt, m2ThreshLowExt;
910 int m1ThreshExt, m2ThreshExt;
913 switch (cmd & ah->ani_function) {
914 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
916 * on == 1 means ofdm weak signal detection is ON
917 * on == 1 is the default, for less noise immunity
919 * on == 0 means ofdm weak signal detection is OFF
920 * on == 0 means more noise imm
922 u32 on = param ? 1 : 0;
924 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
928 aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
930 aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
932 aniState->iniDef.m1Thresh : m1Thresh_off;
934 aniState->iniDef.m2Thresh : m2Thresh_off;
936 aniState->iniDef.m2CountThr : m2CountThr_off;
938 aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
939 m1ThreshLowExt = on ?
940 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
941 m2ThreshLowExt = on ?
942 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
944 aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
946 aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
948 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
949 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
951 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
952 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
954 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
955 AR_PHY_SFCORR_M1_THRESH,
957 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
958 AR_PHY_SFCORR_M2_THRESH,
960 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
961 AR_PHY_SFCORR_M2COUNT_THR,
963 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
964 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
966 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
967 AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
969 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
970 AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
972 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
973 AR_PHY_SFCORR_EXT_M1_THRESH,
975 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
976 AR_PHY_SFCORR_EXT_M2_THRESH,
980 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
981 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
983 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
984 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
986 if (on != aniState->ofdmWeakSigDetect) {
988 "** ch %d: ofdm weak signal: %s=>%s\n",
990 aniState->ofdmWeakSigDetect ?
994 ah->stats.ast_ani_ofdmon++;
996 ah->stats.ast_ani_ofdmoff++;
997 aniState->ofdmWeakSigDetect = on;
1001 case ATH9K_ANI_FIRSTEP_LEVEL:{
1004 if (level >= ARRAY_SIZE(firstep_table)) {
1005 ath_dbg(common, ANI,
1006 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
1007 level, ARRAY_SIZE(firstep_table));
1012 * make register setting relative to default
1013 * from INI file & cap value
1015 value = firstep_table[level] -
1016 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
1017 aniState->iniDef.firstep;
1018 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1019 value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1020 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1021 value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1022 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1023 AR_PHY_FIND_SIG_FIRSTEP,
1026 * we need to set first step low register too
1027 * make register setting relative to default
1028 * from INI file & cap value
1030 value2 = firstep_table[level] -
1031 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
1032 aniState->iniDef.firstepLow;
1033 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1034 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1035 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1036 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1038 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
1039 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
1041 if (level != aniState->firstepLevel) {
1042 ath_dbg(common, ANI,
1043 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
1045 aniState->firstepLevel,
1047 ATH9K_ANI_FIRSTEP_LVL,
1049 aniState->iniDef.firstep);
1050 ath_dbg(common, ANI,
1051 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
1053 aniState->firstepLevel,
1055 ATH9K_ANI_FIRSTEP_LVL,
1057 aniState->iniDef.firstepLow);
1058 if (level > aniState->firstepLevel)
1059 ah->stats.ast_ani_stepup++;
1060 else if (level < aniState->firstepLevel)
1061 ah->stats.ast_ani_stepdown++;
1062 aniState->firstepLevel = level;
1066 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1069 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
1070 ath_dbg(common, ANI,
1071 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
1072 level, ARRAY_SIZE(cycpwrThr1_table));
1076 * make register setting relative to default
1077 * from INI file & cap value
1079 value = cycpwrThr1_table[level] -
1080 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1081 aniState->iniDef.cycpwrThr1;
1082 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1083 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1084 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1085 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1086 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1087 AR_PHY_TIMING5_CYCPWR_THR1,
1091 * set AR_PHY_EXT_CCA for extension channel
1092 * make register setting relative to default
1093 * from INI file & cap value
1095 value2 = cycpwrThr1_table[level] -
1096 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1097 aniState->iniDef.cycpwrThr1Ext;
1098 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1099 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1100 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1101 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1102 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1103 AR_PHY_EXT_CYCPWR_THR1, value2);
1105 if (level != aniState->spurImmunityLevel) {
1106 ath_dbg(common, ANI,
1107 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1109 aniState->spurImmunityLevel,
1111 ATH9K_ANI_SPUR_IMMUNE_LVL,
1113 aniState->iniDef.cycpwrThr1);
1114 ath_dbg(common, ANI,
1115 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1117 aniState->spurImmunityLevel,
1119 ATH9K_ANI_SPUR_IMMUNE_LVL,
1121 aniState->iniDef.cycpwrThr1Ext);
1122 if (level > aniState->spurImmunityLevel)
1123 ah->stats.ast_ani_spurup++;
1124 else if (level < aniState->spurImmunityLevel)
1125 ah->stats.ast_ani_spurdown++;
1126 aniState->spurImmunityLevel = level;
1130 case ATH9K_ANI_MRC_CCK:{
1132 * is_on == 1 means MRC CCK ON (default, less noise imm)
1133 * is_on == 0 means MRC CCK is OFF (more noise imm)
1135 bool is_on = param ? 1 : 0;
1137 if (ah->caps.rx_chainmask == 1)
1140 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1141 AR_PHY_MRC_CCK_ENABLE, is_on);
1142 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1143 AR_PHY_MRC_CCK_MUX_REG, is_on);
1144 if (is_on != aniState->mrcCCK) {
1145 ath_dbg(common, ANI, "** ch %d: MRC CCK: %s=>%s\n",
1147 aniState->mrcCCK ? "on" : "off",
1148 is_on ? "on" : "off");
1150 ah->stats.ast_ani_ccklow++;
1152 ah->stats.ast_ani_cckhigh++;
1153 aniState->mrcCCK = is_on;
1158 ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
1162 ath_dbg(common, ANI,
1163 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1164 aniState->spurImmunityLevel,
1165 aniState->ofdmWeakSigDetect ? "on" : "off",
1166 aniState->firstepLevel,
1167 aniState->mrcCCK ? "on" : "off",
1168 aniState->listenTime,
1169 aniState->ofdmPhyErrCount,
1170 aniState->cckPhyErrCount);
1174 static void ar9003_hw_do_getnf(struct ath_hw *ah,
1175 int16_t nfarray[NUM_NF_READINGS])
1177 #define AR_PHY_CH_MINCCA_PWR 0x1FF00000
1178 #define AR_PHY_CH_MINCCA_PWR_S 20
1179 #define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
1180 #define AR_PHY_CH_EXT_MINCCA_PWR_S 16
1185 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1186 if (ah->rxchainmask & BIT(i)) {
1187 nf = MS(REG_READ(ah, ah->nf_regs[i]),
1188 AR_PHY_CH_MINCCA_PWR);
1189 nfarray[i] = sign_extend32(nf, 8);
1191 if (IS_CHAN_HT40(ah->curchan)) {
1192 u8 ext_idx = AR9300_MAX_CHAINS + i;
1194 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
1195 AR_PHY_CH_EXT_MINCCA_PWR);
1196 nfarray[ext_idx] = sign_extend32(nf, 8);
1202 static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
1204 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1205 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
1206 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
1207 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1208 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1209 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
1211 if (AR_SREV_9330(ah))
1212 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;
1214 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
1215 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ;
1216 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ;
1217 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ;
1218 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9462_5GHZ;
1223 * Initialize the ANI register values with default (ini) values.
1224 * This routine is called during a (full) hardware reset after
1225 * all the registers are initialised from the INI.
1227 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1229 struct ar5416AniState *aniState;
1230 struct ath_common *common = ath9k_hw_common(ah);
1231 struct ath9k_channel *chan = ah->curchan;
1232 struct ath9k_ani_default *iniDef;
1235 aniState = &ah->ani;
1236 iniDef = &aniState->iniDef;
1238 ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz\n",
1239 ah->hw_version.macVersion,
1240 ah->hw_version.macRev,
1244 val = REG_READ(ah, AR_PHY_SFCORR);
1245 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1246 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1247 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1249 val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1250 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1251 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1252 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1254 val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1255 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1256 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1257 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1258 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1259 iniDef->firstep = REG_READ_FIELD(ah,
1261 AR_PHY_FIND_SIG_FIRSTEP);
1262 iniDef->firstepLow = REG_READ_FIELD(ah,
1263 AR_PHY_FIND_SIG_LOW,
1264 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1265 iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1267 AR_PHY_TIMING5_CYCPWR_THR1);
1268 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1270 AR_PHY_EXT_CYCPWR_THR1);
1272 /* these levels just got reset to defaults by the INI */
1273 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
1274 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
1275 aniState->ofdmWeakSigDetect = true;
1276 aniState->mrcCCK = true;
1279 static void ar9003_hw_set_radar_params(struct ath_hw *ah,
1280 struct ath_hw_radar_conf *conf)
1282 u32 radar_0 = 0, radar_1 = 0;
1285 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1289 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1290 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1291 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1292 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1293 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1294 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1296 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1297 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1298 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1299 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1300 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1302 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1303 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1304 if (conf->ext_channel)
1305 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1307 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1310 static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1312 struct ath_hw_radar_conf *conf = &ah->radar_conf;
1314 conf->fir_power = -28;
1315 conf->radar_rssi = 0;
1316 conf->pulse_height = 10;
1317 conf->pulse_rssi = 24;
1318 conf->pulse_inband = 8;
1319 conf->pulse_maxlen = 255;
1320 conf->pulse_inband_step = 12;
1321 conf->radar_inband = 8;
1324 static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
1325 struct ath_hw_antcomb_conf *antconf)
1329 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1330 antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >>
1331 AR_PHY_ANT_DIV_MAIN_LNACONF_S;
1332 antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >>
1333 AR_PHY_ANT_DIV_ALT_LNACONF_S;
1334 antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >>
1335 AR_PHY_ANT_FAST_DIV_BIAS_S;
1337 if (AR_SREV_9330_11(ah)) {
1338 antconf->lna1_lna2_switch_delta = -1;
1339 antconf->lna1_lna2_delta = -9;
1340 antconf->div_group = 1;
1341 } else if (AR_SREV_9485(ah)) {
1342 antconf->lna1_lna2_switch_delta = -1;
1343 antconf->lna1_lna2_delta = -9;
1344 antconf->div_group = 2;
1345 } else if (AR_SREV_9565(ah)) {
1346 antconf->lna1_lna2_switch_delta = 3;
1347 antconf->lna1_lna2_delta = -9;
1348 antconf->div_group = 3;
1350 antconf->lna1_lna2_switch_delta = -1;
1351 antconf->lna1_lna2_delta = -3;
1352 antconf->div_group = 0;
1356 static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
1357 struct ath_hw_antcomb_conf *antconf)
1361 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1362 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1363 AR_PHY_ANT_DIV_ALT_LNACONF |
1364 AR_PHY_ANT_FAST_DIV_BIAS |
1365 AR_PHY_ANT_DIV_MAIN_GAINTB |
1366 AR_PHY_ANT_DIV_ALT_GAINTB);
1367 regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S)
1368 & AR_PHY_ANT_DIV_MAIN_LNACONF);
1369 regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S)
1370 & AR_PHY_ANT_DIV_ALT_LNACONF);
1371 regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S)
1372 & AR_PHY_ANT_FAST_DIV_BIAS);
1373 regval |= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S)
1374 & AR_PHY_ANT_DIV_MAIN_GAINTB);
1375 regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S)
1376 & AR_PHY_ANT_DIV_ALT_GAINTB);
1378 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1381 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1383 static void ar9003_hw_set_bt_ant_diversity(struct ath_hw *ah, bool enable)
1385 struct ath9k_hw_capabilities *pCap = &ah->caps;
1389 if (!AR_SREV_9485(ah) && !AR_SREV_9565(ah))
1392 if (AR_SREV_9485(ah)) {
1393 regval = ar9003_hw_ant_ctrl_common_2_get(ah,
1394 IS_CHAN_2GHZ(ah->curchan));
1396 regval &= ~AR_SWITCH_TABLE_COM2_ALL;
1397 regval |= ah->config.ant_ctrl_comm2g_switch_enable;
1399 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2,
1400 AR_SWITCH_TABLE_COM2_ALL, regval);
1403 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
1406 * Set MAIN/ALT LNA conf.
1407 * Set MAIN/ALT gain_tb.
1409 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1410 regval &= (~AR_ANT_DIV_CTRL_ALL);
1411 regval |= (ant_div_ctl1 & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
1412 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1414 if (AR_SREV_9485_11_OR_LATER(ah)) {
1416 * Enable LNA diversity.
1418 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1419 regval &= ~AR_PHY_ANT_DIV_LNADIV;
1420 regval |= ((ant_div_ctl1 >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;
1422 regval |= AR_ANT_DIV_ENABLE;
1424 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1427 * Enable fast antenna diversity.
1429 regval = REG_READ(ah, AR_PHY_CCK_DETECT);
1430 regval &= ~AR_FAST_DIV_ENABLE;
1431 regval |= ((ant_div_ctl1 >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;
1433 regval |= AR_FAST_DIV_ENABLE;
1435 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
1437 if (pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) {
1438 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1439 regval &= (~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1440 AR_PHY_ANT_DIV_ALT_LNACONF |
1441 AR_PHY_ANT_DIV_ALT_GAINTB |
1442 AR_PHY_ANT_DIV_MAIN_GAINTB));
1444 * Set MAIN to LNA1 and ALT to LNA2 at the
1447 regval |= (ATH_ANT_DIV_COMB_LNA1 <<
1448 AR_PHY_ANT_DIV_MAIN_LNACONF_S);
1449 regval |= (ATH_ANT_DIV_COMB_LNA2 <<
1450 AR_PHY_ANT_DIV_ALT_LNACONF_S);
1451 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1453 } else if (AR_SREV_9565(ah)) {
1455 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1457 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1458 (1 << AR_PHY_ANT_SW_RX_PROT_S));
1459 REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
1460 AR_FAST_DIV_ENABLE);
1461 REG_SET_BIT(ah, AR_PHY_RESTART,
1462 AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
1463 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV,
1464 AR_BTCOEX_WL_LNADIV_FORCE_ON);
1466 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1468 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1469 (1 << AR_PHY_ANT_SW_RX_PROT_S));
1470 REG_CLR_BIT(ah, AR_PHY_CCK_DETECT,
1471 AR_FAST_DIV_ENABLE);
1472 REG_CLR_BIT(ah, AR_PHY_RESTART,
1473 AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
1474 REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV,
1475 AR_BTCOEX_WL_LNADIV_FORCE_ON);
1477 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1478 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1479 AR_PHY_ANT_DIV_ALT_LNACONF |
1480 AR_PHY_ANT_DIV_MAIN_GAINTB |
1481 AR_PHY_ANT_DIV_ALT_GAINTB);
1482 regval |= (ATH_ANT_DIV_COMB_LNA1 <<
1483 AR_PHY_ANT_DIV_MAIN_LNACONF_S);
1484 regval |= (ATH_ANT_DIV_COMB_LNA2 <<
1485 AR_PHY_ANT_DIV_ALT_LNACONF_S);
1486 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1493 static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
1494 struct ath9k_channel *chan,
1497 unsigned int regWrites = 0;
1500 if (IS_CHAN_5GHZ(chan))
1501 modesIndex = IS_CHAN_HT40(chan) ? 2 : 1;
1503 modesIndex = IS_CHAN_HT40(chan) ? 3 : 4;
1505 if (modesIndex == ah->modes_index) {
1506 *ini_reloaded = false;
1510 ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex);
1511 ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex);
1512 ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex);
1513 ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex);
1515 if (AR_SREV_9462_20_OR_LATER(ah))
1516 ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant,
1519 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1521 if (AR_SREV_9462_20_OR_LATER(ah)) {
1523 * CUS217 mix LNA mode.
1525 if (ar9003_hw_get_rx_gain_idx(ah) == 2) {
1526 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core,
1528 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
1529 modesIndex, regWrites);
1534 * For 5GHz channels requiring Fast Clock, apply
1535 * different modal values.
1537 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1538 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites);
1540 if (AR_SREV_9565(ah))
1541 REG_WRITE_ARRAY(&ah->iniModesFastClock, 1, regWrites);
1546 if (chan->channel == 2484)
1547 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
1549 ah->modes_index = modesIndex;
1550 *ini_reloaded = true;
1553 ar9003_hw_set_rfmode(ah, chan);
1557 static void ar9003_hw_spectral_scan_config(struct ath_hw *ah,
1558 struct ath_spec_scan *param)
1562 if (!param->enabled) {
1563 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1564 AR_PHY_SPECTRAL_SCAN_ENABLE);
1568 REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA);
1569 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE);
1571 /* on AR93xx and newer, count = 0 will make the the chip send
1572 * spectral samples endlessly. Check if this really was intended,
1573 * and fix otherwise.
1575 count = param->count;
1578 else if (param->count == 0)
1581 if (param->short_repeat)
1582 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1583 AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
1585 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1586 AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
1588 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1589 AR_PHY_SPECTRAL_SCAN_COUNT, count);
1590 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1591 AR_PHY_SPECTRAL_SCAN_PERIOD, param->period);
1592 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1593 AR_PHY_SPECTRAL_SCAN_FFT_PERIOD, param->fft_period);
1598 static void ar9003_hw_spectral_scan_trigger(struct ath_hw *ah)
1600 /* Activate spectral scan */
1601 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1602 AR_PHY_SPECTRAL_SCAN_ACTIVE);
1605 static void ar9003_hw_spectral_scan_wait(struct ath_hw *ah)
1607 struct ath_common *common = ath9k_hw_common(ah);
1609 /* Poll for spectral scan complete */
1610 if (!ath9k_hw_wait(ah, AR_PHY_SPECTRAL_SCAN,
1611 AR_PHY_SPECTRAL_SCAN_ACTIVE,
1612 0, AH_WAIT_TIMEOUT)) {
1613 ath_err(common, "spectral scan wait failed\n");
1618 void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1620 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1621 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1622 static const u32 ar9300_cca_regs[6] = {
1631 priv_ops->rf_set_freq = ar9003_hw_set_channel;
1632 priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
1633 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
1634 priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
1635 priv_ops->init_bb = ar9003_hw_init_bb;
1636 priv_ops->process_ini = ar9003_hw_process_ini;
1637 priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1638 priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
1639 priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1640 priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1641 priv_ops->rfbus_done = ar9003_hw_rfbus_done;
1642 priv_ops->ani_control = ar9003_hw_ani_control;
1643 priv_ops->do_getnf = ar9003_hw_do_getnf;
1644 priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
1645 priv_ops->set_radar_params = ar9003_hw_set_radar_params;
1646 priv_ops->fast_chan_change = ar9003_hw_fast_chan_change;
1648 ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
1649 ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
1650 ops->spectral_scan_config = ar9003_hw_spectral_scan_config;
1651 ops->spectral_scan_trigger = ar9003_hw_spectral_scan_trigger;
1652 ops->spectral_scan_wait = ar9003_hw_spectral_scan_wait;
1654 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1655 ops->set_bt_ant_diversity = ar9003_hw_set_bt_ant_diversity;
1658 ar9003_hw_set_nf_limits(ah);
1659 ar9003_hw_set_radar_conf(ah);
1660 memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
1663 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
1665 struct ath_common *common = ath9k_hw_common(ah);
1666 u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms;
1667 u32 val, idle_count;
1670 /* disable IRQ, disable chip-reset for BB panic */
1671 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1672 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &
1673 ~(AR_PHY_WATCHDOG_RST_ENABLE |
1674 AR_PHY_WATCHDOG_IRQ_ENABLE));
1676 /* disable watchdog in non-IDLE mode, disable in IDLE mode */
1677 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1678 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &
1679 ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1680 AR_PHY_WATCHDOG_IDLE_ENABLE));
1682 ath_dbg(common, RESET, "Disabled BB Watchdog\n");
1686 /* enable IRQ, disable chip-reset for BB watchdog */
1687 val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;
1688 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1689 (val | AR_PHY_WATCHDOG_IRQ_ENABLE) &
1690 ~AR_PHY_WATCHDOG_RST_ENABLE);
1692 /* bound limit to 10 secs */
1693 if (idle_tmo_ms > 10000)
1694 idle_tmo_ms = 10000;
1697 * The time unit for watchdog event is 2^15 44/88MHz cycles.
1699 * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick
1700 * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick
1702 * Given we use fast clock now in 5 GHz, these time units should
1703 * be common for both 2 GHz and 5 GHz.
1705 idle_count = (100 * idle_tmo_ms) / 74;
1706 if (ah->curchan && IS_CHAN_HT40(ah->curchan))
1707 idle_count = (100 * idle_tmo_ms) / 37;
1710 * enable watchdog in non-IDLE mode, disable in IDLE mode,
1711 * set idle time-out.
1713 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1714 AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1715 AR_PHY_WATCHDOG_IDLE_MASK |
1716 (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
1718 ath_dbg(common, RESET, "Enabled BB Watchdog timeout (%u ms)\n",
1722 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
1725 * we want to avoid printing in ISR context so we save the
1726 * watchdog status to be printed later in bottom half context.
1728 ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);
1731 * the watchdog timer should reset on status read but to be sure
1732 * sure we write 0 to the watchdog status bit.
1734 REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
1735 ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR);
1738 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
1740 struct ath_common *common = ath9k_hw_common(ah);
1743 if (likely(!(common->debug_mask & ATH_DBG_RESET)))
1746 status = ah->bb_watchdog_last_status;
1747 ath_dbg(common, RESET,
1748 "\n==== BB update: BB status=0x%08x ====\n", status);
1749 ath_dbg(common, RESET,
1750 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1751 MS(status, AR_PHY_WATCHDOG_INFO),
1752 MS(status, AR_PHY_WATCHDOG_DET_HANG),
1753 MS(status, AR_PHY_WATCHDOG_RADAR_SM),
1754 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
1755 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
1756 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
1757 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
1758 MS(status, AR_PHY_WATCHDOG_AGC_SM),
1759 MS(status, AR_PHY_WATCHDOG_SRCH_SM));
1761 ath_dbg(common, RESET, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
1762 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
1763 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
1764 ath_dbg(common, RESET, "** BB mode: BB_gen_controls=0x%08x **\n",
1765 REG_READ(ah, AR_PHY_GEN_CTRL));
1767 #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
1768 if (common->cc_survey.cycles)
1769 ath_dbg(common, RESET,
1770 "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n",
1771 PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
1773 ath_dbg(common, RESET, "==== BB update: done ====\n\n");
1775 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
1777 void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
1781 /* While receiving unsupported rate frame rx state machine
1782 * gets into a state 0xb and if phy_restart happens in that
1783 * state, BB would go hang. If RXSM is in 0xb state after
1784 * first bb panic, ensure to disable the phy_restart.
1786 if (!((MS(ah->bb_watchdog_last_status,
1787 AR_PHY_WATCHDOG_RX_OFDM_SM) == 0xb) ||
1788 ah->bb_hang_rx_ofdm))
1791 ah->bb_hang_rx_ofdm = true;
1792 val = REG_READ(ah, AR_PHY_RESTART);
1793 val &= ~AR_PHY_RESTART_ENA;
1795 REG_WRITE(ah, AR_PHY_RESTART, val);
1797 EXPORT_SYMBOL(ar9003_hw_disable_phy_restart);