Pileus Git - ~andy/linux/blob - drivers/net/wireless/ath/ath9k/ar9003_phy.c

   1 /*
   2  * Copyright (c) 2010-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/export.h>
  18 #include "hw.h"
  19 #include "ar9003_phy.h"
  20
  21 static const int firstep_table[] =
  22 /* level:  0   1   2   3   4   5   6   7   8  */
  23         { -4, -2,  0,  2,  4,  6,  8, 10, 12 }; /* lvl 0-8, default 2 */
  24
  25 static const int cycpwrThr1_table[] =
  26 /* level:  0   1   2   3   4   5   6   7   8  */
  27         { -6, -4, -2,  0,  2,  4,  6,  8 };     /* lvl 0-7, default 3 */
  28
  29 /*
  30  * register values to turn OFDM weak signal detection OFF
  31  */
  32 static const int m1ThreshLow_off = 127;
  33 static const int m2ThreshLow_off = 127;
  34 static const int m1Thresh_off = 127;
  35 static const int m2Thresh_off = 127;
  36 static const int m2CountThr_off =  31;
  37 static const int m2CountThrLow_off =  63;
  38 static const int m1ThreshLowExt_off = 127;
  39 static const int m2ThreshLowExt_off = 127;
  40 static const int m1ThreshExt_off = 127;
  41 static const int m2ThreshExt_off = 127;
  42
  43 /**
  44  * ar9003_hw_set_channel - set channel on single-chip device
  45  * @ah: atheros hardware structure
  46  * @chan:
  47  *
  48  * This is the function to change channel on single-chip devices, that is
  49  * for AR9300 family of chipsets.
  50  *
  51  * This function takes the channel value in MHz and sets
  52  * hardware channel value. Assumes writes have been enabled to analog bus.
  53  *
  54  * Actual Expression,
  55  *
  56  * For 2GHz channel,
  57  * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
  58  * (freq_ref = 40MHz)
  59  *
  60  * For 5GHz channel,
  61  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
  62  * (freq_ref = 40MHz/(24>>amodeRefSel))
  63  *
  64  * For 5GHz channels which are 5MHz spaced,
  65  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
  66  * (freq_ref = 40MHz)
  67  */
  68 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
  69 {
  70         u16 bMode, fracMode = 0, aModeRefSel = 0;
  71         u32 freq, chan_frac, div, channelSel = 0, reg32 = 0;
  72         struct chan_centers centers;
  73         int loadSynthChannel;
  74
  75         ath9k_hw_get_channel_centers(ah, chan, &centers);
  76         freq = centers.synth_center;
  77
  78         if (freq < 4800) {     /* 2 GHz, fractional mode */
  79                 if (AR_SREV_9330(ah)) {
  80                         if (ah->is_clk_25mhz)
  81                                 div = 75;
  82                         else
  83                                 div = 120;
  84
  85                         channelSel = (freq * 4) / div;
  86                         chan_frac = (((freq * 4) % div) * 0x20000) / div;
  87                         channelSel = (channelSel << 17) | chan_frac;
  88                 } else if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
  89                         /*
  90                          * freq_ref = 40 / (refdiva >> amoderefsel);
  91                          * where refdiva=1 and amoderefsel=0
  92                          * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
  93                          * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
  94                          */
  95                         channelSel = (freq * 4) / 120;
  96                         chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
  97                         channelSel = (channelSel << 17) | chan_frac;
  98                 } else if (AR_SREV_9340(ah)) {
  99                         if (ah->is_clk_25mhz) {
 100                                 channelSel = (freq * 2) / 75;
 101                                 chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
 102                                 channelSel = (channelSel << 17) | chan_frac;
 103                         } else {
 104                                 channelSel = CHANSEL_2G(freq) >> 1;
 105                         }
 106                 } else if (AR_SREV_9550(ah)) {
 107                         if (ah->is_clk_25mhz)
 108                                 div = 75;
 109                         else
 110                                 div = 120;
 111
 112                         channelSel = (freq * 4) / div;
 113                         chan_frac = (((freq * 4) % div) * 0x20000) / div;
 114                         channelSel = (channelSel << 17) | chan_frac;
 115                 } else {
 116                         channelSel = CHANSEL_2G(freq);
 117                 }
 118                 /* Set to 2G mode */
 119                 bMode = 1;
 120         } else {
 121                 if ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) &&
 122                     ah->is_clk_25mhz) {
 123                         channelSel = freq / 75;
 124                         chan_frac = ((freq % 75) * 0x20000) / 75;
 125                         channelSel = (channelSel << 17) | chan_frac;
 126                 } else {
 127                         channelSel = CHANSEL_5G(freq);
 128                         /* Doubler is ON, so, divide channelSel by 2. */
 129                         channelSel >>= 1;
 130                 }
 131                 /* Set to 5G mode */
 132                 bMode = 0;
 133         }
 134
 135         /* Enable fractional mode for all channels */
 136         fracMode = 1;
 137         aModeRefSel = 0;
 138         loadSynthChannel = 0;
 139
 140         reg32 = (bMode << 29);
 141         REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
 142
 143         /* Enable Long shift Select for Synthesizer */
 144         REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
 145                       AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
 146
 147         /* Program Synth. setting */
 148         reg32 = (channelSel << 2) | (fracMode << 30) |
 149                 (aModeRefSel << 28) | (loadSynthChannel << 31);
 150         REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
 151
 152         /* Toggle Load Synth channel bit */
 153         loadSynthChannel = 1;
 154         reg32 = (channelSel << 2) | (fracMode << 30) |
 155                 (aModeRefSel << 28) | (loadSynthChannel << 31);
 156         REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
 157
 158         ah->curchan = chan;
 159
 160         return 0;
 161 }
 162
 163 /**
 164  * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
 165  * @ah: atheros hardware structure
 166  * @chan:
 167  *
 168  * For single-chip solutions. Converts to baseband spur frequency given the
 169  * input channel frequency and compute register settings below.
 170  *
 171  * Spur mitigation for MRC CCK
 172  */
 173 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
 174                                             struct ath9k_channel *chan)
 175 {
 176         static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
 177         int cur_bb_spur, negative = 0, cck_spur_freq;
 178         int i;
 179         int range, max_spur_cnts, synth_freq;
 180         u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan));
 181
 182         /*
 183          * Need to verify range +/- 10 MHz in control channel, otherwise spur
 184          * is out-of-band and can be ignored.
 185          */
 186
 187         if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
 188             AR_SREV_9550(ah)) {
 189                 if (spur_fbin_ptr[0] == 0) /* No spur */
 190                         return;
 191                 max_spur_cnts = 5;
 192                 if (IS_CHAN_HT40(chan)) {
 193                         range = 19;
 194                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 195                                            AR_PHY_GC_DYN2040_PRI_CH) == 0)
 196                                 synth_freq = chan->channel + 10;
 197                         else
 198                                 synth_freq = chan->channel - 10;
 199                 } else {
 200                         range = 10;
 201                         synth_freq = chan->channel;
 202                 }
 203         } else {
 204                 range = AR_SREV_9462(ah) ? 5 : 10;
 205                 max_spur_cnts = 4;
 206                 synth_freq = chan->channel;
 207         }
 208
 209         for (i = 0; i < max_spur_cnts; i++) {
 210                 if (AR_SREV_9462(ah) && (i == 0 || i == 3))
 211                         continue;
 212
 213                 negative = 0;
 214                 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
 215                     AR_SREV_9550(ah))
 216                         cur_bb_spur = ath9k_hw_fbin2freq(spur_fbin_ptr[i],
 217                                                          IS_CHAN_2GHZ(chan));
 218                 else
 219                         cur_bb_spur = spur_freq[i];
 220
 221                 cur_bb_spur -= synth_freq;
 222                 if (cur_bb_spur < 0) {
 223                         negative = 1;
 224                         cur_bb_spur = -cur_bb_spur;
 225                 }
 226                 if (cur_bb_spur < range) {
 227                         cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
 228
 229                         if (negative == 1)
 230                                 cck_spur_freq = -cck_spur_freq;
 231
 232                         cck_spur_freq = cck_spur_freq & 0xfffff;
 233
 234                         REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
 235                                       AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
 236                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 237                                       AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
 238                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 239                                       AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
 240                                       0x2);
 241                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 242                                       AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
 243                                       0x1);
 244                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 245                                       AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
 246                                       cck_spur_freq);
 247
 248                         return;
 249                 }
 250         }
 251
 252         REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
 253                       AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
 254         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 255                       AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
 256         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 257                       AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
 258 }
 259
 260 /* Clean all spur register fields */
 261 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
 262 {
 263         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 264                       AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
 265         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 266                       AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
 267         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 268                       AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
 269         REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 270                       AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
 271         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 272                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
 273         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 274                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
 275         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 276                       AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
 277         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 278                       AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
 279         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 280                       AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
 281
 282         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 283                       AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
 284         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 285                       AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
 286         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 287                       AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
 288         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 289                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
 290         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 291                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
 292         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 293                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
 294         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 295                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
 296         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 297                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
 298         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 299                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
 300         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 301                       AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
 302 }
 303
 304 static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
 305                                 int freq_offset,
 306                                 int spur_freq_sd,
 307                                 int spur_delta_phase,
 308                                 int spur_subchannel_sd,
 309                                 int range,
 310                                 int synth_freq)
 311 {
 312         int mask_index = 0;
 313
 314         /* OFDM Spur mitigation */
 315         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 316                  AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
 317         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 318                       AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
 319         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 320                       AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
 321         REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 322                       AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
 323         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 324                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
 325
 326         if (!(AR_SREV_9565(ah) && range == 10 && synth_freq == 2437))
 327                 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 328                               AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
 329
 330         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 331                       AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
 332         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 333                       AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
 334         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 335                       AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
 336
 337         if (REG_READ_FIELD(ah, AR_PHY_MODE,
 338                            AR_PHY_MODE_DYNAMIC) == 0x1)
 339                 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 340                               AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
 341
 342         mask_index = (freq_offset << 4) / 5;
 343         if (mask_index < 0)
 344                 mask_index = mask_index - 1;
 345
 346         mask_index = mask_index & 0x7f;
 347
 348         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 349                       AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
 350         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 351                       AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
 352         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 353                       AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
 354         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 355                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
 356         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 357                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
 358         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 359                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
 360         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 361                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
 362         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 363                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
 364         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 365                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
 366         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 367                       AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
 368 }
 369
 370 static void ar9003_hw_spur_ofdm_9565(struct ath_hw *ah,
 371                                      int freq_offset)
 372 {
 373         int mask_index = 0;
 374
 375         mask_index = (freq_offset << 4) / 5;
 376         if (mask_index < 0)
 377                 mask_index = mask_index - 1;
 378
 379         mask_index = mask_index & 0x7f;
 380
 381         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 382                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B,
 383                       mask_index);
 384
 385         /* A == B */
 386         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
 387                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A,
 388                       mask_index);
 389
 390         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 391                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B,
 392                       mask_index);
 393         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 394                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B, 0xe);
 395         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 396                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B, 0xe);
 397
 398         /* A == B */
 399         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
 400                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
 401 }
 402
 403 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
 404                                      struct ath9k_channel *chan,
 405                                      int freq_offset,
 406                                      int range,
 407                                      int synth_freq)
 408 {
 409         int spur_freq_sd = 0;
 410         int spur_subchannel_sd = 0;
 411         int spur_delta_phase = 0;
 412
 413         if (IS_CHAN_HT40(chan)) {
 414                 if (freq_offset < 0) {
 415                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 416                                            AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
 417                                 spur_subchannel_sd = 1;
 418                         else
 419                                 spur_subchannel_sd = 0;
 420
 421                         spur_freq_sd = ((freq_offset + 10) << 9) / 11;
 422
 423                 } else {
 424                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 425                             AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
 426                                 spur_subchannel_sd = 0;
 427                         else
 428                                 spur_subchannel_sd = 1;
 429
 430                         spur_freq_sd = ((freq_offset - 10) << 9) / 11;
 431
 432                 }
 433
 434                 spur_delta_phase = (freq_offset << 17) / 5;
 435
 436         } else {
 437                 spur_subchannel_sd = 0;
 438                 spur_freq_sd = (freq_offset << 9) /11;
 439                 spur_delta_phase = (freq_offset << 18) / 5;
 440         }
 441
 442         spur_freq_sd = spur_freq_sd & 0x3ff;
 443         spur_delta_phase = spur_delta_phase & 0xfffff;
 444
 445         ar9003_hw_spur_ofdm(ah,
 446                             freq_offset,
 447                             spur_freq_sd,
 448                             spur_delta_phase,
 449                             spur_subchannel_sd,
 450                             range, synth_freq);
 451 }
 452
 453 /* Spur mitigation for OFDM */
 454 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
 455                                          struct ath9k_channel *chan)
 456 {
 457         int synth_freq;
 458         int range = 10;
 459         int freq_offset = 0;
 460         int mode;
 461         u8* spurChansPtr;
 462         unsigned int i;
 463         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
 464
 465         if (IS_CHAN_5GHZ(chan)) {
 466                 spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
 467                 mode = 0;
 468         }
 469         else {
 470                 spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
 471                 mode = 1;
 472         }
 473
 474         if (spurChansPtr[0] == 0)
 475                 return; /* No spur in the mode */
 476
 477         if (IS_CHAN_HT40(chan)) {
 478                 range = 19;
 479                 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 480                                    AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
 481                         synth_freq = chan->channel - 10;
 482                 else
 483                         synth_freq = chan->channel + 10;
 484         } else {
 485                 range = 10;
 486                 synth_freq = chan->channel;
 487         }
 488
 489         ar9003_hw_spur_ofdm_clear(ah);
 490
 491         for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
 492                 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i], mode);
 493                 freq_offset -= synth_freq;
 494                 if (abs(freq_offset) < range) {
 495                         ar9003_hw_spur_ofdm_work(ah, chan, freq_offset,
 496                                                  range, synth_freq);
 497
 498                         if (AR_SREV_9565(ah) && (i < 4)) {
 499                                 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i + 1],
 500                                                                  mode);
 501                                 freq_offset -= synth_freq;
 502                                 if (abs(freq_offset) < range)
 503                                         ar9003_hw_spur_ofdm_9565(ah, freq_offset);
 504                         }
 505
 506                         break;
 507                 }
 508         }
 509 }
 510
 511 static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
 512                                     struct ath9k_channel *chan)
 513 {
 514         if (!AR_SREV_9565(ah))
 515                 ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
 516         ar9003_hw_spur_mitigate_ofdm(ah, chan);
 517 }
 518
 519 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
 520                                          struct ath9k_channel *chan)
 521 {
 522         u32 pll;
 523
 524         pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
 525
 526         if (chan && IS_CHAN_HALF_RATE(chan))
 527                 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
 528         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 529                 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
 530
 531         pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
 532
 533         return pll;
 534 }
 535
 536 static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
 537                                        struct ath9k_channel *chan)
 538 {
 539         u32 phymode;
 540         u32 enableDacFifo = 0;
 541
 542         enableDacFifo =
 543                 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
 544
 545         /* Enable 11n HT, 20 MHz */
 546         phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 |
 547                   AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
 548
 549         /* Configure baseband for dynamic 20/40 operation */
 550         if (IS_CHAN_HT40(chan)) {
 551                 phymode |= AR_PHY_GC_DYN2040_EN;
 552                 /* Configure control (primary) channel at +-10MHz */
 553                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 554                     (chan->chanmode == CHANNEL_G_HT40PLUS))
 555                         phymode |= AR_PHY_GC_DYN2040_PRI_CH;
 556
 557         }
 558
 559         /* make sure we preserve INI settings */
 560         phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
 561         /* turn off Green Field detection for STA for now */
 562         phymode &= ~AR_PHY_GC_GF_DETECT_EN;
 563
 564         REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
 565
 566         /* Configure MAC for 20/40 operation */
 567         ath9k_hw_set11nmac2040(ah);
 568
 569         /* global transmit timeout (25 TUs default)*/
 570         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
 571         /* carrier sense timeout */
 572         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
 573 }
 574
 575 static void ar9003_hw_init_bb(struct ath_hw *ah,
 576                               struct ath9k_channel *chan)
 577 {
 578         u32 synthDelay;
 579
 580         /*
 581          * Wait for the frequency synth to settle (synth goes on
 582          * via AR_PHY_ACTIVE_EN).  Read the phy active delay register.
 583          * Value is in 100ns increments.
 584          */
 585         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 586
 587         /* Activate the PHY (includes baseband activate + synthesizer on) */
 588         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 589         ath9k_hw_synth_delay(ah, chan, synthDelay);
 590 }
 591
 592 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
 593 {
 594         if (ah->caps.tx_chainmask == 5 || ah->caps.rx_chainmask == 5)
 595                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
 596                             AR_PHY_SWAP_ALT_CHAIN);
 597
 598         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
 599         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
 600
 601         if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
 602                 tx = 3;
 603
 604         REG_WRITE(ah, AR_SELFGEN_MASK, tx);
 605 }
 606
 607 /*
 608  * Override INI values with chip specific configuration.
 609  */
 610 static void ar9003_hw_override_ini(struct ath_hw *ah)
 611 {
 612         u32 val;
 613
 614         /*
 615          * Set the RX_ABORT and RX_DIS and clear it only after
 616          * RXE is set for MAC. This prevents frames with
 617          * corrupted descriptor status.
 618          */
 619         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
 620
 621         /*
 622          * For AR9280 and above, there is a new feature that allows
 623          * Multicast search based on both MAC Address and Key ID. By default,
 624          * this feature is enabled. But since the driver is not using this
 625          * feature, we switch it off; otherwise multicast search based on
 626          * MAC addr only will fail.
 627          */
 628         val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
 629         REG_WRITE(ah, AR_PCU_MISC_MODE2,
 630                   val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE);
 631
 632         REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
 633                     AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
 634 }
 635
 636 static void ar9003_hw_prog_ini(struct ath_hw *ah,
 637                                struct ar5416IniArray *iniArr,
 638                                int column)
 639 {
 640         unsigned int i, regWrites = 0;
 641
 642         /* New INI format: Array may be undefined (pre, core, post arrays) */
 643         if (!iniArr->ia_array)
 644                 return;
 645
 646         /*
 647          * New INI format: Pre, core, and post arrays for a given subsystem
 648          * may be modal (> 2 columns) or non-modal (2 columns). Determine if
 649          * the array is non-modal and force the column to 1.
 650          */
 651         if (column >= iniArr->ia_columns)
 652                 column = 1;
 653
 654         for (i = 0; i < iniArr->ia_rows; i++) {
 655                 u32 reg = INI_RA(iniArr, i, 0);
 656                 u32 val = INI_RA(iniArr, i, column);
 657
 658                 REG_WRITE(ah, reg, val);
 659
 660                 DO_DELAY(regWrites);
 661         }
 662 }
 663
 664 static int ar9550_hw_get_modes_txgain_index(struct ath_hw *ah,
 665                                             struct ath9k_channel *chan)
 666 {
 667         int ret;
 668
 669         switch (chan->chanmode) {
 670         case CHANNEL_A:
 671         case CHANNEL_A_HT20:
 672                 if (chan->channel <= 5350)
 673                         ret = 1;
 674                 else if ((chan->channel > 5350) && (chan->channel <= 5600))
 675                         ret = 3;
 676                 else
 677                         ret = 5;
 678                 break;
 679
 680         case CHANNEL_A_HT40PLUS:
 681         case CHANNEL_A_HT40MINUS:
 682                 if (chan->channel <= 5350)
 683                         ret = 2;
 684                 else if ((chan->channel > 5350) && (chan->channel <= 5600))
 685                         ret = 4;
 686                 else
 687                         ret = 6;
 688                 break;
 689
 690         case CHANNEL_G:
 691         case CHANNEL_G_HT20:
 692         case CHANNEL_B:
 693                 ret = 8;
 694                 break;
 695
 696         case CHANNEL_G_HT40PLUS:
 697         case CHANNEL_G_HT40MINUS:
 698                 ret = 7;
 699                 break;
 700
 701         default:
 702                 ret = -EINVAL;
 703         }
 704
 705         return ret;
 706 }
 707
 708 static int ar9003_hw_process_ini(struct ath_hw *ah,
 709                                  struct ath9k_channel *chan)
 710 {
 711         unsigned int regWrites = 0, i;
 712         u32 modesIndex;
 713
 714         switch (chan->chanmode) {
 715         case CHANNEL_A:
 716         case CHANNEL_A_HT20:
 717                 modesIndex = 1;
 718                 break;
 719         case CHANNEL_A_HT40PLUS:
 720         case CHANNEL_A_HT40MINUS:
 721                 modesIndex = 2;
 722                 break;
 723         case CHANNEL_G:
 724         case CHANNEL_G_HT20:
 725         case CHANNEL_B:
 726                 modesIndex = 4;
 727                 break;
 728         case CHANNEL_G_HT40PLUS:
 729         case CHANNEL_G_HT40MINUS:
 730                 modesIndex = 3;
 731                 break;
 732
 733         default:
 734                 return -EINVAL;
 735         }
 736
 737         for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
 738                 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
 739                 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
 740                 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
 741                 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
 742                 if (i == ATH_INI_POST && AR_SREV_9462_20(ah))
 743                         ar9003_hw_prog_ini(ah,
 744                                            &ah->ini_radio_post_sys2ant,
 745                                            modesIndex);
 746         }
 747
 748         REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
 749         if (AR_SREV_9550(ah))
 750                 REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex,
 751                                 regWrites);
 752
 753         if (AR_SREV_9550(ah)) {
 754                 int modes_txgain_index;
 755
 756                 modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan);
 757                 if (modes_txgain_index < 0)
 758                         return -EINVAL;
 759
 760                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index,
 761                                 regWrites);
 762         } else {
 763                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
 764         }
 765
 766         /*
 767          * For 5GHz channels requiring Fast Clock, apply
 768          * different modal values.
 769          */
 770         if (IS_CHAN_A_FAST_CLOCK(ah, chan))
 771                 REG_WRITE_ARRAY(&ah->iniModesFastClock,
 772                                 modesIndex, regWrites);
 773
 774         REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
 775
 776         if (chan->channel == 2484)
 777                 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
 778
 779         if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
 780                 REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,
 781                           AR_GLB_SWREG_DISCONT_EN_BT_WLAN);
 782
 783         ah->modes_index = modesIndex;
 784         ar9003_hw_override_ini(ah);
 785         ar9003_hw_set_channel_regs(ah, chan);
 786         ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
 787         ath9k_hw_apply_txpower(ah, chan, false);
 788
 789         if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
 790                 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
 791                                    AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))
 792                         ah->enabled_cals |= TX_IQ_CAL;
 793                 else
 794                         ah->enabled_cals &= ~TX_IQ_CAL;
 795
 796                 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
 797                         ah->enabled_cals |= TX_CL_CAL;
 798                 else
 799                         ah->enabled_cals &= ~TX_CL_CAL;
 800         }
 801
 802         return 0;
 803 }
 804
 805 static void ar9003_hw_set_rfmode(struct ath_hw *ah,
 806                                  struct ath9k_channel *chan)
 807 {
 808         u32 rfMode = 0;
 809
 810         if (chan == NULL)
 811                 return;
 812
 813         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
 814                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
 815
 816         if (IS_CHAN_A_FAST_CLOCK(ah, chan))
 817                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
 818         if (IS_CHAN_QUARTER_RATE(chan))
 819                 rfMode |= AR_PHY_MODE_QUARTER;
 820         if (IS_CHAN_HALF_RATE(chan))
 821                 rfMode |= AR_PHY_MODE_HALF;
 822
 823         if (rfMode & (AR_PHY_MODE_QUARTER | AR_PHY_MODE_HALF))
 824                 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
 825                               AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW, 3);
 826
 827         REG_WRITE(ah, AR_PHY_MODE, rfMode);
 828 }
 829
 830 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
 831 {
 832         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
 833 }
 834
 835 static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
 836                                       struct ath9k_channel *chan)
 837 {
 838         u32 coef_scaled, ds_coef_exp, ds_coef_man;
 839         u32 clockMhzScaled = 0x64000000;
 840         struct chan_centers centers;
 841
 842         /*
 843          * half and quarter rate can divide the scaled clock by 2 or 4
 844          * scale for selected channel bandwidth
 845          */
 846         if (IS_CHAN_HALF_RATE(chan))
 847                 clockMhzScaled = clockMhzScaled >> 1;
 848         else if (IS_CHAN_QUARTER_RATE(chan))
 849                 clockMhzScaled = clockMhzScaled >> 2;
 850
 851         /*
 852          * ALGO -> coef = 1e8/fcarrier*fclock/40;
 853          * scaled coef to provide precision for this floating calculation
 854          */
 855         ath9k_hw_get_channel_centers(ah, chan, &centers);
 856         coef_scaled = clockMhzScaled / centers.synth_center;
 857
 858         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
 859                                       &ds_coef_exp);
 860
 861         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
 862                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
 863         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
 864                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
 865
 866         /*
 867          * For Short GI,
 868          * scaled coeff is 9/10 that of normal coeff
 869          */
 870         coef_scaled = (9 * coef_scaled) / 10;
 871
 872         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
 873                                       &ds_coef_exp);
 874
 875         /* for short gi */
 876         REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
 877                       AR_PHY_SGI_DSC_MAN, ds_coef_man);
 878         REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
 879                       AR_PHY_SGI_DSC_EXP, ds_coef_exp);
 880 }
 881
 882 static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
 883 {
 884         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
 885         return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
 886                              AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
 887 }
 888
 889 /*
 890  * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
 891  * Read the phy active delay register. Value is in 100ns increments.
 892  */
 893 static void ar9003_hw_rfbus_done(struct ath_hw *ah)
 894 {
 895         u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 896
 897         ath9k_hw_synth_delay(ah, ah->curchan, synthDelay);
 898
 899         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
 900 }
 901
 902 static bool ar9003_hw_ani_control(struct ath_hw *ah,
 903                                   enum ath9k_ani_cmd cmd, int param)
 904 {
 905         struct ath_common *common = ath9k_hw_common(ah);
 906         struct ath9k_channel *chan = ah->curchan;
 907         struct ar5416AniState *aniState = &chan->ani;
 908         s32 value, value2;
 909
 910         switch (cmd & ah->ani_function) {
 911         case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
 912                 /*
 913                  * on == 1 means ofdm weak signal detection is ON
 914                  * on == 1 is the default, for less noise immunity
 915                  *
 916                  * on == 0 means ofdm weak signal detection is OFF
 917                  * on == 0 means more noise imm
 918                  */
 919                 u32 on = param ? 1 : 0;
 920
 921                 if (on)
 922                         REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
 923                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
 924                 else
 925                         REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
 926                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
 927
 928                 if (on != aniState->ofdmWeakSigDetect) {
 929                         ath_dbg(common, ANI,
 930                                 "** ch %d: ofdm weak signal: %s=>%s\n",
 931                                 chan->channel,
 932                                 aniState->ofdmWeakSigDetect ?
 933                                 "on" : "off",
 934                                 on ? "on" : "off");
 935                         if (on)
 936                                 ah->stats.ast_ani_ofdmon++;
 937                         else
 938                                 ah->stats.ast_ani_ofdmoff++;
 939                         aniState->ofdmWeakSigDetect = on;
 940                 }
 941                 break;
 942         }
 943         case ATH9K_ANI_FIRSTEP_LEVEL:{
 944                 u32 level = param;
 945
 946                 if (level >= ARRAY_SIZE(firstep_table)) {
 947                         ath_dbg(common, ANI,
 948                                 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
 949                                 level, ARRAY_SIZE(firstep_table));
 950                         return false;
 951                 }
 952
 953                 /*
 954                  * make register setting relative to default
 955                  * from INI file & cap value
 956                  */
 957                 value = firstep_table[level] -
 958                         firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
 959                         aniState->iniDef.firstep;
 960                 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
 961                         value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
 962                 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
 963                         value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
 964                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
 965                               AR_PHY_FIND_SIG_FIRSTEP,
 966                               value);
 967                 /*
 968                  * we need to set first step low register too
 969                  * make register setting relative to default
 970                  * from INI file & cap value
 971                  */
 972                 value2 = firstep_table[level] -
 973                          firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
 974                          aniState->iniDef.firstepLow;
 975                 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
 976                         value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
 977                 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
 978                         value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
 979
 980                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
 981                               AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
 982
 983                 if (level != aniState->firstepLevel) {
 984                         ath_dbg(common, ANI,
 985                                 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
 986                                 chan->channel,
 987                                 aniState->firstepLevel,
 988                                 level,
 989                                 ATH9K_ANI_FIRSTEP_LVL,
 990                                 value,
 991                                 aniState->iniDef.firstep);
 992                         ath_dbg(common, ANI,
 993                                 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
 994                                 chan->channel,
 995                                 aniState->firstepLevel,
 996                                 level,
 997                                 ATH9K_ANI_FIRSTEP_LVL,
 998                                 value2,
 999                                 aniState->iniDef.firstepLow);
1000                         if (level > aniState->firstepLevel)
1001                                 ah->stats.ast_ani_stepup++;
1002                         else if (level < aniState->firstepLevel)
1003                                 ah->stats.ast_ani_stepdown++;
1004                         aniState->firstepLevel = level;
1005                 }
1006                 break;
1007         }
1008         case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1009                 u32 level = param;
1010
1011                 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
1012                         ath_dbg(common, ANI,
1013                                 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
1014                                 level, ARRAY_SIZE(cycpwrThr1_table));
1015                         return false;
1016                 }
1017                 /*
1018                  * make register setting relative to default
1019                  * from INI file & cap value
1020                  */
1021                 value = cycpwrThr1_table[level] -
1022                         cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1023                         aniState->iniDef.cycpwrThr1;
1024                 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1025                         value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1026                 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1027                         value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1028                 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1029                               AR_PHY_TIMING5_CYCPWR_THR1,
1030                               value);
1031
1032                 /*
1033                  * set AR_PHY_EXT_CCA for extension channel
1034                  * make register setting relative to default
1035                  * from INI file & cap value
1036                  */
1037                 value2 = cycpwrThr1_table[level] -
1038                          cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1039                          aniState->iniDef.cycpwrThr1Ext;
1040                 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1041                         value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1042                 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1043                         value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1044                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1045                               AR_PHY_EXT_CYCPWR_THR1, value2);
1046
1047                 if (level != aniState->spurImmunityLevel) {
1048                         ath_dbg(common, ANI,
1049                                 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1050                                 chan->channel,
1051                                 aniState->spurImmunityLevel,
1052                                 level,
1053                                 ATH9K_ANI_SPUR_IMMUNE_LVL,
1054                                 value,
1055                                 aniState->iniDef.cycpwrThr1);
1056                         ath_dbg(common, ANI,
1057                                 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1058                                 chan->channel,
1059                                 aniState->spurImmunityLevel,
1060                                 level,
1061                                 ATH9K_ANI_SPUR_IMMUNE_LVL,
1062                                 value2,
1063                                 aniState->iniDef.cycpwrThr1Ext);
1064                         if (level > aniState->spurImmunityLevel)
1065                                 ah->stats.ast_ani_spurup++;
1066                         else if (level < aniState->spurImmunityLevel)
1067                                 ah->stats.ast_ani_spurdown++;
1068                         aniState->spurImmunityLevel = level;
1069                 }
1070                 break;
1071         }
1072         case ATH9K_ANI_MRC_CCK:{
1073                 /*
1074                  * is_on == 1 means MRC CCK ON (default, less noise imm)
1075                  * is_on == 0 means MRC CCK is OFF (more noise imm)
1076                  */
1077                 bool is_on = param ? 1 : 0;
1078                 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1079                               AR_PHY_MRC_CCK_ENABLE, is_on);
1080                 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1081                               AR_PHY_MRC_CCK_MUX_REG, is_on);
1082                 if (is_on != aniState->mrcCCK) {
1083                         ath_dbg(common, ANI, "** ch %d: MRC CCK: %s=>%s\n",
1084                                 chan->channel,
1085                                 aniState->mrcCCK ? "on" : "off",
1086                                 is_on ? "on" : "off");
1087                 if (is_on)
1088                         ah->stats.ast_ani_ccklow++;
1089                 else
1090                         ah->stats.ast_ani_cckhigh++;
1091                 aniState->mrcCCK = is_on;
1092                 }
1093         break;
1094         }
1095         case ATH9K_ANI_PRESENT:
1096                 break;
1097         default:
1098                 ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
1099                 return false;
1100         }
1101
1102         ath_dbg(common, ANI,
1103                 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1104                 aniState->spurImmunityLevel,
1105                 aniState->ofdmWeakSigDetect ? "on" : "off",
1106                 aniState->firstepLevel,
1107                 aniState->mrcCCK ? "on" : "off",
1108                 aniState->listenTime,
1109                 aniState->ofdmPhyErrCount,
1110                 aniState->cckPhyErrCount);
1111         return true;
1112 }
1113
1114 static void ar9003_hw_do_getnf(struct ath_hw *ah,
1115                               int16_t nfarray[NUM_NF_READINGS])
1116 {
1117 #define AR_PHY_CH_MINCCA_PWR    0x1FF00000
1118 #define AR_PHY_CH_MINCCA_PWR_S  20
1119 #define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
1120 #define AR_PHY_CH_EXT_MINCCA_PWR_S 16
1121
1122         int16_t nf;
1123         int i;
1124
1125         for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1126                 if (ah->rxchainmask & BIT(i)) {
1127                         nf = MS(REG_READ(ah, ah->nf_regs[i]),
1128                                          AR_PHY_CH_MINCCA_PWR);
1129                         nfarray[i] = sign_extend32(nf, 8);
1130
1131                         if (IS_CHAN_HT40(ah->curchan)) {
1132                                 u8 ext_idx = AR9300_MAX_CHAINS + i;
1133
1134                                 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
1135                                                  AR_PHY_CH_EXT_MINCCA_PWR);
1136                                 nfarray[ext_idx] = sign_extend32(nf, 8);
1137                         }
1138                 }
1139         }
1140 }
1141
1142 static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
1143 {
1144         ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1145         ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
1146         ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
1147         ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1148         ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1149         ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
1150
1151         if (AR_SREV_9330(ah))
1152                 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;
1153
1154         if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
1155                 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ;
1156                 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ;
1157                 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ;
1158                 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9462_5GHZ;
1159         }
1160 }
1161
1162 /*
1163  * Initialize the ANI register values with default (ini) values.
1164  * This routine is called during a (full) hardware reset after
1165  * all the registers are initialised from the INI.
1166  */
1167 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1168 {
1169         struct ar5416AniState *aniState;
1170         struct ath_common *common = ath9k_hw_common(ah);
1171         struct ath9k_channel *chan = ah->curchan;
1172         struct ath9k_ani_default *iniDef;
1173         u32 val;
1174
1175         aniState = &ah->curchan->ani;
1176         iniDef = &aniState->iniDef;
1177
1178         ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
1179                 ah->hw_version.macVersion,
1180                 ah->hw_version.macRev,
1181                 ah->opmode,
1182                 chan->channel,
1183                 chan->channelFlags);
1184
1185         val = REG_READ(ah, AR_PHY_SFCORR);
1186         iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1187         iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1188         iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1189
1190         val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1191         iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1192         iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1193         iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1194
1195         val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1196         iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1197         iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1198         iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1199         iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1200         iniDef->firstep = REG_READ_FIELD(ah,
1201                                          AR_PHY_FIND_SIG,
1202                                          AR_PHY_FIND_SIG_FIRSTEP);
1203         iniDef->firstepLow = REG_READ_FIELD(ah,
1204                                             AR_PHY_FIND_SIG_LOW,
1205                                             AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1206         iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1207                                             AR_PHY_TIMING5,
1208                                             AR_PHY_TIMING5_CYCPWR_THR1);
1209         iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1210                                                AR_PHY_EXT_CCA,
1211                                                AR_PHY_EXT_CYCPWR_THR1);
1212
1213         /* these levels just got reset to defaults by the INI */
1214         aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
1215         aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
1216         aniState->ofdmWeakSigDetect = ATH9K_ANI_USE_OFDM_WEAK_SIG;
1217         aniState->mrcCCK = true;
1218 }
1219
1220 static void ar9003_hw_set_radar_params(struct ath_hw *ah,
1221                                        struct ath_hw_radar_conf *conf)
1222 {
1223         u32 radar_0 = 0, radar_1 = 0;
1224
1225         if (!conf) {
1226                 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1227                 return;
1228         }
1229
1230         radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1231         radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1232         radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1233         radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1234         radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1235         radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1236
1237         radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1238         radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1239         radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1240         radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1241         radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1242
1243         REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1244         REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1245         if (conf->ext_channel)
1246                 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1247         else
1248                 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1249 }
1250
1251 static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1252 {
1253         struct ath_hw_radar_conf *conf = &ah->radar_conf;
1254
1255         conf->fir_power = -28;
1256         conf->radar_rssi = 0;
1257         conf->pulse_height = 10;
1258         conf->pulse_rssi = 24;
1259         conf->pulse_inband = 8;
1260         conf->pulse_maxlen = 255;
1261         conf->pulse_inband_step = 12;
1262         conf->radar_inband = 8;
1263 }
1264
1265 static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
1266                                            struct ath_hw_antcomb_conf *antconf)
1267 {
1268         u32 regval;
1269
1270         regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1271         antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >>
1272                                   AR_PHY_ANT_DIV_MAIN_LNACONF_S;
1273         antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >>
1274                                  AR_PHY_ANT_DIV_ALT_LNACONF_S;
1275         antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >>
1276                                   AR_PHY_ANT_FAST_DIV_BIAS_S;
1277
1278         if (AR_SREV_9330_11(ah)) {
1279                 antconf->lna1_lna2_delta = -9;
1280                 antconf->div_group = 1;
1281         } else if (AR_SREV_9485(ah)) {
1282                 antconf->lna1_lna2_delta = -9;
1283                 antconf->div_group = 2;
1284         } else if (AR_SREV_9565(ah)) {
1285                 antconf->lna1_lna2_delta = -3;
1286                 antconf->div_group = 3;
1287         } else {
1288                 antconf->lna1_lna2_delta = -3;
1289                 antconf->div_group = 0;
1290         }
1291 }
1292
1293 static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
1294                                    struct ath_hw_antcomb_conf *antconf)
1295 {
1296         u32 regval;
1297
1298         regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1299         regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1300                     AR_PHY_ANT_DIV_ALT_LNACONF |
1301                     AR_PHY_ANT_FAST_DIV_BIAS |
1302                     AR_PHY_ANT_DIV_MAIN_GAINTB |
1303                     AR_PHY_ANT_DIV_ALT_GAINTB);
1304         regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S)
1305                    & AR_PHY_ANT_DIV_MAIN_LNACONF);
1306         regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S)
1307                    & AR_PHY_ANT_DIV_ALT_LNACONF);
1308         regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S)
1309                    & AR_PHY_ANT_FAST_DIV_BIAS);
1310         regval |= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S)
1311                    & AR_PHY_ANT_DIV_MAIN_GAINTB);
1312         regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S)
1313                    & AR_PHY_ANT_DIV_ALT_GAINTB);
1314
1315         REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1316 }
1317
1318 static void ar9003_hw_antctrl_shared_chain_lnadiv(struct ath_hw *ah,
1319                                                   bool enable)
1320 {
1321         u8 ant_div_ctl1;
1322         u32 regval;
1323
1324         if (!AR_SREV_9565(ah))
1325                 return;
1326
1327         ah->shared_chain_lnadiv = enable;
1328         ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
1329
1330         regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1331         regval &= (~AR_ANT_DIV_CTRL_ALL);
1332         regval |= (ant_div_ctl1 & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
1333         regval &= ~AR_PHY_ANT_DIV_LNADIV;
1334         regval |= ((ant_div_ctl1 >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;
1335
1336         if (enable)
1337                 regval |= AR_ANT_DIV_ENABLE;
1338
1339         REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1340
1341         regval = REG_READ(ah, AR_PHY_CCK_DETECT);
1342         regval &= ~AR_FAST_DIV_ENABLE;
1343         regval |= ((ant_div_ctl1 >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;
1344
1345         if (enable)
1346                 regval |= AR_FAST_DIV_ENABLE;
1347
1348         REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
1349
1350         if (enable) {
1351                 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1352                             (1 << AR_PHY_ANT_SW_RX_PROT_S));
1353                 if (ah->curchan && IS_CHAN_2GHZ(ah->curchan))
1354                         REG_SET_BIT(ah, AR_PHY_RESTART,
1355                                     AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
1356                 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV,
1357                             AR_BTCOEX_WL_LNADIV_FORCE_ON);
1358         } else {
1359                 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, AR_ANT_DIV_ENABLE);
1360                 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1361                             (1 << AR_PHY_ANT_SW_RX_PROT_S));
1362                 REG_CLR_BIT(ah, AR_PHY_CCK_DETECT, AR_FAST_DIV_ENABLE);
1363                 REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV,
1364                             AR_BTCOEX_WL_LNADIV_FORCE_ON);
1365
1366                 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1367                 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1368                         AR_PHY_ANT_DIV_ALT_LNACONF |
1369                         AR_PHY_ANT_DIV_MAIN_GAINTB |
1370                         AR_PHY_ANT_DIV_ALT_GAINTB);
1371                 regval |= (AR_PHY_ANT_DIV_LNA1 << AR_PHY_ANT_DIV_MAIN_LNACONF_S);
1372                 regval |= (AR_PHY_ANT_DIV_LNA2 << AR_PHY_ANT_DIV_ALT_LNACONF_S);
1373                 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1374         }
1375 }
1376
1377 static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
1378                                       struct ath9k_channel *chan,
1379                                       u8 *ini_reloaded)
1380 {
1381         unsigned int regWrites = 0;
1382         u32 modesIndex;
1383
1384         switch (chan->chanmode) {
1385         case CHANNEL_A:
1386         case CHANNEL_A_HT20:
1387                 modesIndex = 1;
1388                 break;
1389         case CHANNEL_A_HT40PLUS:
1390         case CHANNEL_A_HT40MINUS:
1391                 modesIndex = 2;
1392                 break;
1393         case CHANNEL_G:
1394         case CHANNEL_G_HT20:
1395         case CHANNEL_B:
1396                 modesIndex = 4;
1397                 break;
1398         case CHANNEL_G_HT40PLUS:
1399         case CHANNEL_G_HT40MINUS:
1400                 modesIndex = 3;
1401                 break;
1402
1403         default:
1404                 return -EINVAL;
1405         }
1406
1407         if (modesIndex == ah->modes_index) {
1408                 *ini_reloaded = false;
1409                 goto set_rfmode;
1410         }
1411
1412         ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex);
1413         ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex);
1414         ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex);
1415         ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex);
1416
1417         if (AR_SREV_9462_20(ah))
1418                 ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant,
1419                                    modesIndex);
1420
1421         REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1422
1423         /*
1424          * For 5GHz channels requiring Fast Clock, apply
1425          * different modal values.
1426          */
1427         if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1428                 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites);
1429
1430         if (AR_SREV_9565(ah))
1431                 REG_WRITE_ARRAY(&ah->iniModesFastClock, 1, regWrites);
1432
1433         REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
1434
1435         ah->modes_index = modesIndex;
1436         *ini_reloaded = true;
1437
1438 set_rfmode:
1439         ar9003_hw_set_rfmode(ah, chan);
1440         return 0;
1441 }
1442
1443 static void ar9003_hw_spectral_scan_config(struct ath_hw *ah,
1444                                            struct ath_spec_scan *param)
1445 {
1446         u8 count;
1447
1448         if (!param->enabled) {
1449                 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1450                             AR_PHY_SPECTRAL_SCAN_ENABLE);
1451                 return;
1452         }
1453
1454         REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA);
1455         REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE);
1456
1457         /* on AR93xx and newer, count = 0 will make the the chip send
1458          * spectral samples endlessly. Check if this really was intended,
1459          * and fix otherwise.
1460          */
1461         count = param->count;
1462         if (param->endless)
1463                 count = 0;
1464         else if (param->count == 0)
1465                 count = 1;
1466
1467         if (param->short_repeat)
1468                 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1469                             AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
1470         else
1471                 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1472                             AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
1473
1474         REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1475                       AR_PHY_SPECTRAL_SCAN_COUNT, count);
1476         REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1477                       AR_PHY_SPECTRAL_SCAN_PERIOD, param->period);
1478         REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1479                       AR_PHY_SPECTRAL_SCAN_FFT_PERIOD, param->fft_period);
1480
1481         return;
1482 }
1483
1484 static void ar9003_hw_spectral_scan_trigger(struct ath_hw *ah)
1485 {
1486         /* Activate spectral scan */
1487         REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1488                     AR_PHY_SPECTRAL_SCAN_ACTIVE);
1489 }
1490
1491 static void ar9003_hw_spectral_scan_wait(struct ath_hw *ah)
1492 {
1493         struct ath_common *common = ath9k_hw_common(ah);
1494
1495         /* Poll for spectral scan complete */
1496         if (!ath9k_hw_wait(ah, AR_PHY_SPECTRAL_SCAN,
1497                            AR_PHY_SPECTRAL_SCAN_ACTIVE,
1498                            0, AH_WAIT_TIMEOUT)) {
1499                 ath_err(common, "spectral scan wait failed\n");
1500                 return;
1501         }
1502 }
1503
1504 void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1505 {
1506         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1507         struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1508         static const u32 ar9300_cca_regs[6] = {
1509                 AR_PHY_CCA_0,
1510                 AR_PHY_CCA_1,
1511                 AR_PHY_CCA_2,
1512                 AR_PHY_EXT_CCA,
1513                 AR_PHY_EXT_CCA_1,
1514                 AR_PHY_EXT_CCA_2,
1515         };
1516
1517         priv_ops->rf_set_freq = ar9003_hw_set_channel;
1518         priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
1519         priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
1520         priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
1521         priv_ops->init_bb = ar9003_hw_init_bb;
1522         priv_ops->process_ini = ar9003_hw_process_ini;
1523         priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1524         priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
1525         priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1526         priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1527         priv_ops->rfbus_done = ar9003_hw_rfbus_done;
1528         priv_ops->ani_control = ar9003_hw_ani_control;
1529         priv_ops->do_getnf = ar9003_hw_do_getnf;
1530         priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
1531         priv_ops->set_radar_params = ar9003_hw_set_radar_params;
1532         priv_ops->fast_chan_change = ar9003_hw_fast_chan_change;
1533
1534         ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
1535         ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
1536         ops->antctrl_shared_chain_lnadiv = ar9003_hw_antctrl_shared_chain_lnadiv;
1537         ops->spectral_scan_config = ar9003_hw_spectral_scan_config;
1538         ops->spectral_scan_trigger = ar9003_hw_spectral_scan_trigger;
1539         ops->spectral_scan_wait = ar9003_hw_spectral_scan_wait;
1540
1541         ar9003_hw_set_nf_limits(ah);
1542         ar9003_hw_set_radar_conf(ah);
1543         memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
1544 }
1545
1546 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
1547 {
1548         struct ath_common *common = ath9k_hw_common(ah);
1549         u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms;
1550         u32 val, idle_count;
1551
1552         if (!idle_tmo_ms) {
1553                 /* disable IRQ, disable chip-reset for BB panic */
1554                 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1555                           REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &
1556                           ~(AR_PHY_WATCHDOG_RST_ENABLE |
1557                             AR_PHY_WATCHDOG_IRQ_ENABLE));
1558
1559                 /* disable watchdog in non-IDLE mode, disable in IDLE mode */
1560                 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1561                           REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &
1562                           ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1563                             AR_PHY_WATCHDOG_IDLE_ENABLE));
1564
1565                 ath_dbg(common, RESET, "Disabled BB Watchdog\n");
1566                 return;
1567         }
1568
1569         /* enable IRQ, disable chip-reset for BB watchdog */
1570         val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;
1571         REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1572                   (val | AR_PHY_WATCHDOG_IRQ_ENABLE) &
1573                   ~AR_PHY_WATCHDOG_RST_ENABLE);
1574
1575         /* bound limit to 10 secs */
1576         if (idle_tmo_ms > 10000)
1577                 idle_tmo_ms = 10000;
1578
1579         /*
1580          * The time unit for watchdog event is 2^15 44/88MHz cycles.
1581          *
1582          * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick
1583          * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick
1584          *
1585          * Given we use fast clock now in 5 GHz, these time units should
1586          * be common for both 2 GHz and 5 GHz.
1587          */
1588         idle_count = (100 * idle_tmo_ms) / 74;
1589         if (ah->curchan && IS_CHAN_HT40(ah->curchan))
1590                 idle_count = (100 * idle_tmo_ms) / 37;
1591
1592         /*
1593          * enable watchdog in non-IDLE mode, disable in IDLE mode,
1594          * set idle time-out.
1595          */
1596         REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1597                   AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1598                   AR_PHY_WATCHDOG_IDLE_MASK |
1599                   (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
1600
1601         ath_dbg(common, RESET, "Enabled BB Watchdog timeout (%u ms)\n",
1602                 idle_tmo_ms);
1603 }
1604
1605 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
1606 {
1607         /*
1608          * we want to avoid printing in ISR context so we save the
1609          * watchdog status to be printed later in bottom half context.
1610          */
1611         ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);
1612
1613         /*
1614          * the watchdog timer should reset on status read but to be sure
1615          * sure we write 0 to the watchdog status bit.
1616          */
1617         REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
1618                   ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR);
1619 }
1620
1621 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
1622 {
1623         struct ath_common *common = ath9k_hw_common(ah);
1624         u32 status;
1625
1626         if (likely(!(common->debug_mask & ATH_DBG_RESET)))
1627                 return;
1628
1629         status = ah->bb_watchdog_last_status;
1630         ath_dbg(common, RESET,
1631                 "\n==== BB update: BB status=0x%08x ====\n", status);
1632         ath_dbg(common, RESET,
1633                 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1634                 MS(status, AR_PHY_WATCHDOG_INFO),
1635                 MS(status, AR_PHY_WATCHDOG_DET_HANG),
1636                 MS(status, AR_PHY_WATCHDOG_RADAR_SM),
1637                 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
1638                 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
1639                 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
1640                 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
1641                 MS(status, AR_PHY_WATCHDOG_AGC_SM),
1642                 MS(status, AR_PHY_WATCHDOG_SRCH_SM));
1643
1644         ath_dbg(common, RESET, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
1645                 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
1646                 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
1647         ath_dbg(common, RESET, "** BB mode: BB_gen_controls=0x%08x **\n",
1648                 REG_READ(ah, AR_PHY_GEN_CTRL));
1649
1650 #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
1651         if (common->cc_survey.cycles)
1652                 ath_dbg(common, RESET,
1653                         "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n",
1654                         PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
1655
1656         ath_dbg(common, RESET, "==== BB update: done ====\n\n");
1657 }
1658 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
1659
1660 void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
1661 {
1662         u32 val;
1663
1664         /* While receiving unsupported rate frame rx state machine
1665          * gets into a state 0xb and if phy_restart happens in that
1666          * state, BB would go hang. If RXSM is in 0xb state after
1667          * first bb panic, ensure to disable the phy_restart.
1668          */
1669         if (!((MS(ah->bb_watchdog_last_status,
1670                   AR_PHY_WATCHDOG_RX_OFDM_SM) == 0xb) ||
1671             ah->bb_hang_rx_ofdm))
1672                 return;
1673
1674         ah->bb_hang_rx_ofdm = true;
1675         val = REG_READ(ah, AR_PHY_RESTART);
1676         val &= ~AR_PHY_RESTART_ENA;
1677
1678         REG_WRITE(ah, AR_PHY_RESTART, val);
1679 }
1680 EXPORT_SYMBOL(ar9003_hw_disable_phy_restart);