Pileus Git - ~andy/linux/blob - drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

   1 /*
   2  * Copyright (c) 2010-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <asm/unaligned.h>
  18 #include "hw.h"
  19 #include "ar9003_phy.h"
  20 #include "ar9003_eeprom.h"
  21
  22 #define COMP_HDR_LEN 4
  23 #define COMP_CKSUM_LEN 2
  24
  25 #define LE16(x) __constant_cpu_to_le16(x)
  26 #define LE32(x) __constant_cpu_to_le32(x)
  27
  28 /* Local defines to distinguish between extension and control CTL's */
  29 #define EXT_ADDITIVE (0x8000)
  30 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
  31 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
  32 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
  33 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN     6  /* 10*log10(2)*2 */
  34 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN   9  /* 10*log10(3)*2 */
  35 #define PWRINCR_3_TO_1_CHAIN      9             /* 10*log(3)*2 */
  36 #define PWRINCR_3_TO_2_CHAIN      3             /* floor(10*log(3/2)*2) */
  37 #define PWRINCR_2_TO_1_CHAIN      6             /* 10*log(2)*2 */
  38
  39 #define SUB_NUM_CTL_MODES_AT_5G_40 2    /* excluding HT40, EXT-OFDM */
  40 #define SUB_NUM_CTL_MODES_AT_2G_40 3    /* excluding HT40, EXT-OFDM, EXT-CCK */
  41
  42 #define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6))
  43
  44 #define EEPROM_DATA_LEN_9485    1088
  45
  46 static int ar9003_hw_power_interpolate(int32_t x,
  47                                        int32_t *px, int32_t *py, u_int16_t np);
  48
  49
  50 static const struct ar9300_eeprom ar9300_default = {
  51         .eepromVersion = 2,
  52         .templateVersion = 2,
  53         .macAddr = {0, 2, 3, 4, 5, 6},
  54         .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  55                      0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
  56         .baseEepHeader = {
  57                 .regDmn = { LE16(0), LE16(0x1f) },
  58                 .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
  59                 .opCapFlags = {
  60                         .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
  61                         .eepMisc = 0,
  62                 },
  63                 .rfSilent = 0,
  64                 .blueToothOptions = 0,
  65                 .deviceCap = 0,
  66                 .deviceType = 5, /* takes lower byte in eeprom location */
  67                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
  68                 .params_for_tuning_caps = {0, 0},
  69                 .featureEnable = 0x0c,
  70                  /*
  71                   * bit0 - enable tx temp comp - disabled
  72                   * bit1 - enable tx volt comp - disabled
  73                   * bit2 - enable fastClock - enabled
  74                   * bit3 - enable doubling - enabled
  75                   * bit4 - enable internal regulator - disabled
  76                   * bit5 - enable pa predistortion - disabled
  77                   */
  78                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
  79                 .eepromWriteEnableGpio = 3,
  80                 .wlanDisableGpio = 0,
  81                 .wlanLedGpio = 8,
  82                 .rxBandSelectGpio = 0xff,
  83                 .txrxgain = 0,
  84                 .swreg = 0,
  85          },
  86         .modalHeader2G = {
  87         /* ar9300_modal_eep_header  2g */
  88                 /* 4 idle,t1,t2,b(4 bits per setting) */
  89                 .antCtrlCommon = LE32(0x110),
  90                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
  91                 .antCtrlCommon2 = LE32(0x22222),
  92
  93                 /*
  94                  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
  95                  * rx1, rx12, b (2 bits each)
  96                  */
  97                 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
  98
  99                 /*
 100                  * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
 101                  * for ar9280 (0xa20c/b20c 5:0)
 102                  */
 103                 .xatten1DB = {0, 0, 0},
 104
 105                 /*
 106                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 107                  * for ar9280 (0xa20c/b20c 16:12
 108                  */
 109                 .xatten1Margin = {0, 0, 0},
 110                 .tempSlope = 36,
 111                 .voltSlope = 0,
 112
 113                 /*
 114                  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
 115                  * channels in usual fbin coding format
 116                  */
 117                 .spurChans = {0, 0, 0, 0, 0},
 118
 119                 /*
 120                  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
 121                  * if the register is per chain
 122                  */
 123                 .noiseFloorThreshCh = {-1, 0, 0},
 124                 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 125                 .quick_drop = 0,
 126                 .xpaBiasLvl = 0,
 127                 .txFrameToDataStart = 0x0e,
 128                 .txFrameToPaOn = 0x0e,
 129                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 130                 .antennaGain = 0,
 131                 .switchSettling = 0x2c,
 132                 .adcDesiredSize = -30,
 133                 .txEndToXpaOff = 0,
 134                 .txEndToRxOn = 0x2,
 135                 .txFrameToXpaOn = 0xe,
 136                 .thresh62 = 28,
 137                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
 138                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
 139                 .futureModal = {
 140                         0, 0, 0, 0, 0, 0, 0, 0,
 141                 },
 142          },
 143         .base_ext1 = {
 144                 .ant_div_control = 0,
 145                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
 146         },
 147         .calFreqPier2G = {
 148                 FREQ2FBIN(2412, 1),
 149                 FREQ2FBIN(2437, 1),
 150                 FREQ2FBIN(2472, 1),
 151          },
 152         /* ar9300_cal_data_per_freq_op_loop 2g */
 153         .calPierData2G = {
 154                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 155                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 156                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 157          },
 158         .calTarget_freqbin_Cck = {
 159                 FREQ2FBIN(2412, 1),
 160                 FREQ2FBIN(2484, 1),
 161          },
 162         .calTarget_freqbin_2G = {
 163                 FREQ2FBIN(2412, 1),
 164                 FREQ2FBIN(2437, 1),
 165                 FREQ2FBIN(2472, 1)
 166          },
 167         .calTarget_freqbin_2GHT20 = {
 168                 FREQ2FBIN(2412, 1),
 169                 FREQ2FBIN(2437, 1),
 170                 FREQ2FBIN(2472, 1)
 171          },
 172         .calTarget_freqbin_2GHT40 = {
 173                 FREQ2FBIN(2412, 1),
 174                 FREQ2FBIN(2437, 1),
 175                 FREQ2FBIN(2472, 1)
 176          },
 177         .calTargetPowerCck = {
 178                  /* 1L-5L,5S,11L,11S */
 179                  { {36, 36, 36, 36} },
 180                  { {36, 36, 36, 36} },
 181         },
 182         .calTargetPower2G = {
 183                  /* 6-24,36,48,54 */
 184                  { {32, 32, 28, 24} },
 185                  { {32, 32, 28, 24} },
 186                  { {32, 32, 28, 24} },
 187         },
 188         .calTargetPower2GHT20 = {
 189                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 190                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 191                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 192         },
 193         .calTargetPower2GHT40 = {
 194                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 195                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 196                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 197         },
 198         .ctlIndex_2G =  {
 199                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
 200                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
 201         },
 202         .ctl_freqbin_2G = {
 203                 {
 204                         FREQ2FBIN(2412, 1),
 205                         FREQ2FBIN(2417, 1),
 206                         FREQ2FBIN(2457, 1),
 207                         FREQ2FBIN(2462, 1)
 208                 },
 209                 {
 210                         FREQ2FBIN(2412, 1),
 211                         FREQ2FBIN(2417, 1),
 212                         FREQ2FBIN(2462, 1),
 213                         0xFF,
 214                 },
 215
 216                 {
 217                         FREQ2FBIN(2412, 1),
 218                         FREQ2FBIN(2417, 1),
 219                         FREQ2FBIN(2462, 1),
 220                         0xFF,
 221                 },
 222                 {
 223                         FREQ2FBIN(2422, 1),
 224                         FREQ2FBIN(2427, 1),
 225                         FREQ2FBIN(2447, 1),
 226                         FREQ2FBIN(2452, 1)
 227                 },
 228
 229                 {
 230                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 231                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 232                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 233                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
 234                 },
 235
 236                 {
 237                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 238                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 239                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 240                         0,
 241                 },
 242
 243                 {
 244                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 245                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 246                         FREQ2FBIN(2472, 1),
 247                         0,
 248                 },
 249
 250                 {
 251                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 252                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 253                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 254                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 255                 },
 256
 257                 {
 258                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 259                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 260                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 261                 },
 262
 263                 {
 264                         /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 265                         /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 266                         /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 267                         0
 268                 },
 269
 270                 {
 271                         /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 272                         /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 273                         /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 274                         0
 275                 },
 276
 277                 {
 278                         /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 279                         /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 280                         /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 281                         /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 282                 }
 283          },
 284         .ctlPowerData_2G = {
 285                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 286                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 287                  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
 288
 289                  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
 290                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 291                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 292
 293                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
 294                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 295                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 296
 297                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 298                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
 299                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
 300          },
 301         .modalHeader5G = {
 302                 /* 4 idle,t1,t2,b (4 bits per setting) */
 303                 .antCtrlCommon = LE32(0x110),
 304                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
 305                 .antCtrlCommon2 = LE32(0x22222),
 306                  /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
 307                 .antCtrlChain = {
 308                         LE16(0x000), LE16(0x000), LE16(0x000),
 309                 },
 310                  /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
 311                 .xatten1DB = {0, 0, 0},
 312
 313                 /*
 314                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 315                  * for merlin (0xa20c/b20c 16:12
 316                  */
 317                 .xatten1Margin = {0, 0, 0},
 318                 .tempSlope = 68,
 319                 .voltSlope = 0,
 320                 /* spurChans spur channels in usual fbin coding format */
 321                 .spurChans = {0, 0, 0, 0, 0},
 322                 /* noiseFloorThreshCh Check if the register is per chain */
 323                 .noiseFloorThreshCh = {-1, 0, 0},
 324                 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 325                 .quick_drop = 0,
 326                 .xpaBiasLvl = 0,
 327                 .txFrameToDataStart = 0x0e,
 328                 .txFrameToPaOn = 0x0e,
 329                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 330                 .antennaGain = 0,
 331                 .switchSettling = 0x2d,
 332                 .adcDesiredSize = -30,
 333                 .txEndToXpaOff = 0,
 334                 .txEndToRxOn = 0x2,
 335                 .txFrameToXpaOn = 0xe,
 336                 .thresh62 = 28,
 337                 .papdRateMaskHt20 = LE32(0x0c80c080),
 338                 .papdRateMaskHt40 = LE32(0x0080c080),
 339                 .futureModal = {
 340                         0, 0, 0, 0, 0, 0, 0, 0,
 341                 },
 342          },
 343         .base_ext2 = {
 344                 .tempSlopeLow = 0,
 345                 .tempSlopeHigh = 0,
 346                 .xatten1DBLow = {0, 0, 0},
 347                 .xatten1MarginLow = {0, 0, 0},
 348                 .xatten1DBHigh = {0, 0, 0},
 349                 .xatten1MarginHigh = {0, 0, 0}
 350         },
 351         .calFreqPier5G = {
 352                 FREQ2FBIN(5180, 0),
 353                 FREQ2FBIN(5220, 0),
 354                 FREQ2FBIN(5320, 0),
 355                 FREQ2FBIN(5400, 0),
 356                 FREQ2FBIN(5500, 0),
 357                 FREQ2FBIN(5600, 0),
 358                 FREQ2FBIN(5725, 0),
 359                 FREQ2FBIN(5825, 0)
 360         },
 361         .calPierData5G = {
 362                         {
 363                                 {0, 0, 0, 0, 0},
 364                                 {0, 0, 0, 0, 0},
 365                                 {0, 0, 0, 0, 0},
 366                                 {0, 0, 0, 0, 0},
 367                                 {0, 0, 0, 0, 0},
 368                                 {0, 0, 0, 0, 0},
 369                                 {0, 0, 0, 0, 0},
 370                                 {0, 0, 0, 0, 0},
 371                         },
 372                         {
 373                                 {0, 0, 0, 0, 0},
 374                                 {0, 0, 0, 0, 0},
 375                                 {0, 0, 0, 0, 0},
 376                                 {0, 0, 0, 0, 0},
 377                                 {0, 0, 0, 0, 0},
 378                                 {0, 0, 0, 0, 0},
 379                                 {0, 0, 0, 0, 0},
 380                                 {0, 0, 0, 0, 0},
 381                         },
 382                         {
 383                                 {0, 0, 0, 0, 0},
 384                                 {0, 0, 0, 0, 0},
 385                                 {0, 0, 0, 0, 0},
 386                                 {0, 0, 0, 0, 0},
 387                                 {0, 0, 0, 0, 0},
 388                                 {0, 0, 0, 0, 0},
 389                                 {0, 0, 0, 0, 0},
 390                                 {0, 0, 0, 0, 0},
 391                         },
 392
 393         },
 394         .calTarget_freqbin_5G = {
 395                 FREQ2FBIN(5180, 0),
 396                 FREQ2FBIN(5220, 0),
 397                 FREQ2FBIN(5320, 0),
 398                 FREQ2FBIN(5400, 0),
 399                 FREQ2FBIN(5500, 0),
 400                 FREQ2FBIN(5600, 0),
 401                 FREQ2FBIN(5725, 0),
 402                 FREQ2FBIN(5825, 0)
 403         },
 404         .calTarget_freqbin_5GHT20 = {
 405                 FREQ2FBIN(5180, 0),
 406                 FREQ2FBIN(5240, 0),
 407                 FREQ2FBIN(5320, 0),
 408                 FREQ2FBIN(5500, 0),
 409                 FREQ2FBIN(5700, 0),
 410                 FREQ2FBIN(5745, 0),
 411                 FREQ2FBIN(5725, 0),
 412                 FREQ2FBIN(5825, 0)
 413         },
 414         .calTarget_freqbin_5GHT40 = {
 415                 FREQ2FBIN(5180, 0),
 416                 FREQ2FBIN(5240, 0),
 417                 FREQ2FBIN(5320, 0),
 418                 FREQ2FBIN(5500, 0),
 419                 FREQ2FBIN(5700, 0),
 420                 FREQ2FBIN(5745, 0),
 421                 FREQ2FBIN(5725, 0),
 422                 FREQ2FBIN(5825, 0)
 423          },
 424         .calTargetPower5G = {
 425                 /* 6-24,36,48,54 */
 426                 { {20, 20, 20, 10} },
 427                 { {20, 20, 20, 10} },
 428                 { {20, 20, 20, 10} },
 429                 { {20, 20, 20, 10} },
 430                 { {20, 20, 20, 10} },
 431                 { {20, 20, 20, 10} },
 432                 { {20, 20, 20, 10} },
 433                 { {20, 20, 20, 10} },
 434          },
 435         .calTargetPower5GHT20 = {
 436                 /*
 437                  * 0_8_16,1-3_9-11_17-19,
 438                  * 4,5,6,7,12,13,14,15,20,21,22,23
 439                  */
 440                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 441                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 442                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 443                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 444                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 445                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 446                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 447                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 448          },
 449         .calTargetPower5GHT40 =  {
 450                 /*
 451                  * 0_8_16,1-3_9-11_17-19,
 452                  * 4,5,6,7,12,13,14,15,20,21,22,23
 453                  */
 454                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 455                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 456                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 457                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 458                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 459                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 460                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 461                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 462          },
 463         .ctlIndex_5G =  {
 464                 0x10, 0x16, 0x18, 0x40, 0x46,
 465                 0x48, 0x30, 0x36, 0x38
 466         },
 467         .ctl_freqbin_5G =  {
 468                 {
 469                         /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 470                         /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 471                         /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
 472                         /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
 473                         /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
 474                         /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 475                         /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
 476                         /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
 477                 },
 478                 {
 479                         /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 480                         /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 481                         /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
 482                         /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
 483                         /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
 484                         /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 485                         /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
 486                         /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
 487                 },
 488
 489                 {
 490                         /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
 491                         /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
 492                         /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
 493                         /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
 494                         /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
 495                         /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
 496                         /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
 497                         /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
 498                 },
 499
 500                 {
 501                         /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 502                         /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
 503                         /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
 504                         /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
 505                         /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
 506                         /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 507                         /* Data[3].ctlEdges[6].bChannel */ 0xFF,
 508                         /* Data[3].ctlEdges[7].bChannel */ 0xFF,
 509                 },
 510
 511                 {
 512                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 513                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 514                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
 515                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
 516                         /* Data[4].ctlEdges[4].bChannel */ 0xFF,
 517                         /* Data[4].ctlEdges[5].bChannel */ 0xFF,
 518                         /* Data[4].ctlEdges[6].bChannel */ 0xFF,
 519                         /* Data[4].ctlEdges[7].bChannel */ 0xFF,
 520                 },
 521
 522                 {
 523                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
 524                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
 525                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
 526                         /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
 527                         /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
 528                         /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
 529                         /* Data[5].ctlEdges[6].bChannel */ 0xFF,
 530                         /* Data[5].ctlEdges[7].bChannel */ 0xFF
 531                 },
 532
 533                 {
 534                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 535                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
 536                         /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
 537                         /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
 538                         /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
 539                         /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
 540                         /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
 541                         /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
 542                 },
 543
 544                 {
 545                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 546                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 547                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
 548                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
 549                         /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
 550                         /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 551                         /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
 552                         /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
 553                 },
 554
 555                 {
 556                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
 557                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
 558                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
 559                         /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
 560                         /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
 561                         /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
 562                         /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
 563                         /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
 564                 }
 565          },
 566         .ctlPowerData_5G = {
 567                 {
 568                         {
 569                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 570                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 571                         }
 572                 },
 573                 {
 574                         {
 575                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 576                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 577                         }
 578                 },
 579                 {
 580                         {
 581                                 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
 582                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 583                         }
 584                 },
 585                 {
 586                         {
 587                                 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 588                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
 589                         }
 590                 },
 591                 {
 592                         {
 593                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 594                                 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
 595                         }
 596                 },
 597                 {
 598                         {
 599                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 600                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
 601                         }
 602                 },
 603                 {
 604                         {
 605                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 606                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 607                         }
 608                 },
 609                 {
 610                         {
 611                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
 612                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 613                         }
 614                 },
 615                 {
 616                         {
 617                                 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
 618                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
 619                         }
 620                 },
 621          }
 622 };
 623
 624 static const struct ar9300_eeprom ar9300_x113 = {
 625         .eepromVersion = 2,
 626         .templateVersion = 6,
 627         .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
 628         .custData = {"x113-023-f0000"},
 629         .baseEepHeader = {
 630                 .regDmn = { LE16(0), LE16(0x1f) },
 631                 .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
 632                 .opCapFlags = {
 633                         .opFlags = AR5416_OPFLAGS_11A,
 634                         .eepMisc = 0,
 635                 },
 636                 .rfSilent = 0,
 637                 .blueToothOptions = 0,
 638                 .deviceCap = 0,
 639                 .deviceType = 5, /* takes lower byte in eeprom location */
 640                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
 641                 .params_for_tuning_caps = {0, 0},
 642                 .featureEnable = 0x0d,
 643                  /*
 644                   * bit0 - enable tx temp comp - disabled
 645                   * bit1 - enable tx volt comp - disabled
 646                   * bit2 - enable fastClock - enabled
 647                   * bit3 - enable doubling - enabled
 648                   * bit4 - enable internal regulator - disabled
 649                   * bit5 - enable pa predistortion - disabled
 650                   */
 651                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
 652                 .eepromWriteEnableGpio = 6,
 653                 .wlanDisableGpio = 0,
 654                 .wlanLedGpio = 8,
 655                 .rxBandSelectGpio = 0xff,
 656                 .txrxgain = 0x21,
 657                 .swreg = 0,
 658          },
 659         .modalHeader2G = {
 660         /* ar9300_modal_eep_header  2g */
 661                 /* 4 idle,t1,t2,b(4 bits per setting) */
 662                 .antCtrlCommon = LE32(0x110),
 663                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
 664                 .antCtrlCommon2 = LE32(0x44444),
 665
 666                 /*
 667                  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
 668                  * rx1, rx12, b (2 bits each)
 669                  */
 670                 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
 671
 672                 /*
 673                  * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
 674                  * for ar9280 (0xa20c/b20c 5:0)
 675                  */
 676                 .xatten1DB = {0, 0, 0},
 677
 678                 /*
 679                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 680                  * for ar9280 (0xa20c/b20c 16:12
 681                  */
 682                 .xatten1Margin = {0, 0, 0},
 683                 .tempSlope = 25,
 684                 .voltSlope = 0,
 685
 686                 /*
 687                  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
 688                  * channels in usual fbin coding format
 689                  */
 690                 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
 691
 692                 /*
 693                  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
 694                  * if the register is per chain
 695                  */
 696                 .noiseFloorThreshCh = {-1, 0, 0},
 697                 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 698                 .quick_drop = 0,
 699                 .xpaBiasLvl = 0,
 700                 .txFrameToDataStart = 0x0e,
 701                 .txFrameToPaOn = 0x0e,
 702                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 703                 .antennaGain = 0,
 704                 .switchSettling = 0x2c,
 705                 .adcDesiredSize = -30,
 706                 .txEndToXpaOff = 0,
 707                 .txEndToRxOn = 0x2,
 708                 .txFrameToXpaOn = 0xe,
 709                 .thresh62 = 28,
 710                 .papdRateMaskHt20 = LE32(0x0c80c080),
 711                 .papdRateMaskHt40 = LE32(0x0080c080),
 712                 .futureModal = {
 713                         0, 0, 0, 0, 0, 0, 0, 0,
 714                 },
 715          },
 716          .base_ext1 = {
 717                 .ant_div_control = 0,
 718                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
 719          },
 720         .calFreqPier2G = {
 721                 FREQ2FBIN(2412, 1),
 722                 FREQ2FBIN(2437, 1),
 723                 FREQ2FBIN(2472, 1),
 724          },
 725         /* ar9300_cal_data_per_freq_op_loop 2g */
 726         .calPierData2G = {
 727                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 728                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 729                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 730          },
 731         .calTarget_freqbin_Cck = {
 732                 FREQ2FBIN(2412, 1),
 733                 FREQ2FBIN(2472, 1),
 734          },
 735         .calTarget_freqbin_2G = {
 736                 FREQ2FBIN(2412, 1),
 737                 FREQ2FBIN(2437, 1),
 738                 FREQ2FBIN(2472, 1)
 739          },
 740         .calTarget_freqbin_2GHT20 = {
 741                 FREQ2FBIN(2412, 1),
 742                 FREQ2FBIN(2437, 1),
 743                 FREQ2FBIN(2472, 1)
 744          },
 745         .calTarget_freqbin_2GHT40 = {
 746                 FREQ2FBIN(2412, 1),
 747                 FREQ2FBIN(2437, 1),
 748                 FREQ2FBIN(2472, 1)
 749          },
 750         .calTargetPowerCck = {
 751                  /* 1L-5L,5S,11L,11S */
 752                  { {34, 34, 34, 34} },
 753                  { {34, 34, 34, 34} },
 754         },
 755         .calTargetPower2G = {
 756                  /* 6-24,36,48,54 */
 757                  { {34, 34, 32, 32} },
 758                  { {34, 34, 32, 32} },
 759                  { {34, 34, 32, 32} },
 760         },
 761         .calTargetPower2GHT20 = {
 762                 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
 763                 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
 764                 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
 765         },
 766         .calTargetPower2GHT40 = {
 767                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
 768                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
 769                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
 770         },
 771         .ctlIndex_2G =  {
 772                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
 773                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
 774         },
 775         .ctl_freqbin_2G = {
 776                 {
 777                         FREQ2FBIN(2412, 1),
 778                         FREQ2FBIN(2417, 1),
 779                         FREQ2FBIN(2457, 1),
 780                         FREQ2FBIN(2462, 1)
 781                 },
 782                 {
 783                         FREQ2FBIN(2412, 1),
 784                         FREQ2FBIN(2417, 1),
 785                         FREQ2FBIN(2462, 1),
 786                         0xFF,
 787                 },
 788
 789                 {
 790                         FREQ2FBIN(2412, 1),
 791                         FREQ2FBIN(2417, 1),
 792                         FREQ2FBIN(2462, 1),
 793                         0xFF,
 794                 },
 795                 {
 796                         FREQ2FBIN(2422, 1),
 797                         FREQ2FBIN(2427, 1),
 798                         FREQ2FBIN(2447, 1),
 799                         FREQ2FBIN(2452, 1)
 800                 },
 801
 802                 {
 803                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 804                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 805                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 806                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
 807                 },
 808
 809                 {
 810                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 811                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 812                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 813                         0,
 814                 },
 815
 816                 {
 817                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 818                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 819                         FREQ2FBIN(2472, 1),
 820                         0,
 821                 },
 822
 823                 {
 824                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 825                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 826                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 827                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 828                 },
 829
 830                 {
 831                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 832                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 833                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 834                 },
 835
 836                 {
 837                         /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 838                         /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 839                         /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 840                         0
 841                 },
 842
 843                 {
 844                         /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 845                         /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 846                         /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 847                         0
 848                 },
 849
 850                 {
 851                         /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 852                         /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 853                         /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 854                         /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 855                 }
 856          },
 857         .ctlPowerData_2G = {
 858                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 859                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 860                  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
 861
 862                  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
 863                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 864                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 865
 866                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
 867                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 868                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 869
 870                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 871                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
 872                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
 873          },
 874         .modalHeader5G = {
 875                 /* 4 idle,t1,t2,b (4 bits per setting) */
 876                 .antCtrlCommon = LE32(0x220),
 877                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
 878                 .antCtrlCommon2 = LE32(0x11111),
 879                  /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
 880                 .antCtrlChain = {
 881                         LE16(0x150), LE16(0x150), LE16(0x150),
 882                 },
 883                  /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
 884                 .xatten1DB = {0, 0, 0},
 885
 886                 /*
 887                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 888                  * for merlin (0xa20c/b20c 16:12
 889                  */
 890                 .xatten1Margin = {0, 0, 0},
 891                 .tempSlope = 68,
 892                 .voltSlope = 0,
 893                 /* spurChans spur channels in usual fbin coding format */
 894                 .spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0},
 895                 /* noiseFloorThreshCh Check if the register is per chain */
 896                 .noiseFloorThreshCh = {-1, 0, 0},
 897                 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 898                 .quick_drop = 0,
 899                 .xpaBiasLvl = 0xf,
 900                 .txFrameToDataStart = 0x0e,
 901                 .txFrameToPaOn = 0x0e,
 902                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 903                 .antennaGain = 0,
 904                 .switchSettling = 0x2d,
 905                 .adcDesiredSize = -30,
 906                 .txEndToXpaOff = 0,
 907                 .txEndToRxOn = 0x2,
 908                 .txFrameToXpaOn = 0xe,
 909                 .thresh62 = 28,
 910                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
 911                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
 912                 .futureModal = {
 913                         0, 0, 0, 0, 0, 0, 0, 0,
 914                 },
 915          },
 916         .base_ext2 = {
 917                 .tempSlopeLow = 72,
 918                 .tempSlopeHigh = 105,
 919                 .xatten1DBLow = {0, 0, 0},
 920                 .xatten1MarginLow = {0, 0, 0},
 921                 .xatten1DBHigh = {0, 0, 0},
 922                 .xatten1MarginHigh = {0, 0, 0}
 923          },
 924         .calFreqPier5G = {
 925                 FREQ2FBIN(5180, 0),
 926                 FREQ2FBIN(5240, 0),
 927                 FREQ2FBIN(5320, 0),
 928                 FREQ2FBIN(5400, 0),
 929                 FREQ2FBIN(5500, 0),
 930                 FREQ2FBIN(5600, 0),
 931                 FREQ2FBIN(5745, 0),
 932                 FREQ2FBIN(5785, 0)
 933         },
 934         .calPierData5G = {
 935                         {
 936                                 {0, 0, 0, 0, 0},
 937                                 {0, 0, 0, 0, 0},
 938                                 {0, 0, 0, 0, 0},
 939                                 {0, 0, 0, 0, 0},
 940                                 {0, 0, 0, 0, 0},
 941                                 {0, 0, 0, 0, 0},
 942                                 {0, 0, 0, 0, 0},
 943                                 {0, 0, 0, 0, 0},
 944                         },
 945                         {
 946                                 {0, 0, 0, 0, 0},
 947                                 {0, 0, 0, 0, 0},
 948                                 {0, 0, 0, 0, 0},
 949                                 {0, 0, 0, 0, 0},
 950                                 {0, 0, 0, 0, 0},
 951                                 {0, 0, 0, 0, 0},
 952                                 {0, 0, 0, 0, 0},
 953                                 {0, 0, 0, 0, 0},
 954                         },
 955                         {
 956                                 {0, 0, 0, 0, 0},
 957                                 {0, 0, 0, 0, 0},
 958                                 {0, 0, 0, 0, 0},
 959                                 {0, 0, 0, 0, 0},
 960                                 {0, 0, 0, 0, 0},
 961                                 {0, 0, 0, 0, 0},
 962                                 {0, 0, 0, 0, 0},
 963                                 {0, 0, 0, 0, 0},
 964                         },
 965
 966         },
 967         .calTarget_freqbin_5G = {
 968                 FREQ2FBIN(5180, 0),
 969                 FREQ2FBIN(5220, 0),
 970                 FREQ2FBIN(5320, 0),
 971                 FREQ2FBIN(5400, 0),
 972                 FREQ2FBIN(5500, 0),
 973                 FREQ2FBIN(5600, 0),
 974                 FREQ2FBIN(5745, 0),
 975                 FREQ2FBIN(5785, 0)
 976         },
 977         .calTarget_freqbin_5GHT20 = {
 978                 FREQ2FBIN(5180, 0),
 979                 FREQ2FBIN(5240, 0),
 980                 FREQ2FBIN(5320, 0),
 981                 FREQ2FBIN(5400, 0),
 982                 FREQ2FBIN(5500, 0),
 983                 FREQ2FBIN(5700, 0),
 984                 FREQ2FBIN(5745, 0),
 985                 FREQ2FBIN(5825, 0)
 986         },
 987         .calTarget_freqbin_5GHT40 = {
 988                 FREQ2FBIN(5190, 0),
 989                 FREQ2FBIN(5230, 0),
 990                 FREQ2FBIN(5320, 0),
 991                 FREQ2FBIN(5410, 0),
 992                 FREQ2FBIN(5510, 0),
 993                 FREQ2FBIN(5670, 0),
 994                 FREQ2FBIN(5755, 0),
 995                 FREQ2FBIN(5825, 0)
 996          },
 997         .calTargetPower5G = {
 998                 /* 6-24,36,48,54 */
 999                 { {42, 40, 40, 34} },
1000                 { {42, 40, 40, 34} },
1001                 { {42, 40, 40, 34} },
1002                 { {42, 40, 40, 34} },
1003                 { {42, 40, 40, 34} },
1004                 { {42, 40, 40, 34} },
1005                 { {42, 40, 40, 34} },
1006                 { {42, 40, 40, 34} },
1007          },
1008         .calTargetPower5GHT20 = {
1009                 /*
1010                  * 0_8_16,1-3_9-11_17-19,
1011                  * 4,5,6,7,12,13,14,15,20,21,22,23
1012                  */
1013                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1014                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1015                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1016                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1017                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1018                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1019                 { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} },
1020                 { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} },
1021          },
1022         .calTargetPower5GHT40 =  {
1023                 /*
1024                  * 0_8_16,1-3_9-11_17-19,
1025                  * 4,5,6,7,12,13,14,15,20,21,22,23
1026                  */
1027                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1028                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1029                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1030                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1031                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1032                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1033                 { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} },
1034                 { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} },
1035          },
1036         .ctlIndex_5G =  {
1037                 0x10, 0x16, 0x18, 0x40, 0x46,
1038                 0x48, 0x30, 0x36, 0x38
1039         },
1040         .ctl_freqbin_5G =  {
1041                 {
1042                         /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1043                         /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1044                         /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1045                         /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1046                         /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1047                         /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1048                         /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1049                         /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1050                 },
1051                 {
1052                         /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1053                         /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1054                         /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1055                         /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1056                         /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1057                         /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1058                         /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1059                         /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1060                 },
1061
1062                 {
1063                         /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1064                         /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1065                         /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1066                         /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1067                         /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1068                         /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1069                         /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1070                         /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1071                 },
1072
1073                 {
1074                         /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1075                         /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1076                         /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1077                         /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1078                         /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1079                         /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1080                         /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1081                         /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1082                 },
1083
1084                 {
1085                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1086                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1087                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1088                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1089                         /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1090                         /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1091                         /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1092                         /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1093                 },
1094
1095                 {
1096                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1097                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1098                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1099                         /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1100                         /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1101                         /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1102                         /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1103                         /* Data[5].ctlEdges[7].bChannel */ 0xFF
1104                 },
1105
1106                 {
1107                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1108                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1109                         /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1110                         /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1111                         /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1112                         /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1113                         /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1114                         /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1115                 },
1116
1117                 {
1118                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1119                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1120                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1121                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1122                         /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1123                         /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1124                         /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1125                         /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1126                 },
1127
1128                 {
1129                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1130                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1131                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1132                         /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1133                         /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1134                         /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1135                         /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1136                         /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1137                 }
1138          },
1139         .ctlPowerData_5G = {
1140                 {
1141                         {
1142                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1143                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1144                         }
1145                 },
1146                 {
1147                         {
1148                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1149                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1150                         }
1151                 },
1152                 {
1153                         {
1154                                 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1155                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1156                         }
1157                 },
1158                 {
1159                         {
1160                                 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1161                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1162                         }
1163                 },
1164                 {
1165                         {
1166                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1167                                 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1168                         }
1169                 },
1170                 {
1171                         {
1172                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1173                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1174                         }
1175                 },
1176                 {
1177                         {
1178                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1179                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1180                         }
1181                 },
1182                 {
1183                         {
1184                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1185                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1186                         }
1187                 },
1188                 {
1189                         {
1190                                 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1191                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1192                         }
1193                 },
1194          }
1195 };
1196
1197
1198 static const struct ar9300_eeprom ar9300_h112 = {
1199         .eepromVersion = 2,
1200         .templateVersion = 3,
1201         .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1202         .custData = {"h112-241-f0000"},
1203         .baseEepHeader = {
1204                 .regDmn = { LE16(0), LE16(0x1f) },
1205                 .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
1206                 .opCapFlags = {
1207                         .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
1208                         .eepMisc = 0,
1209                 },
1210                 .rfSilent = 0,
1211                 .blueToothOptions = 0,
1212                 .deviceCap = 0,
1213                 .deviceType = 5, /* takes lower byte in eeprom location */
1214                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1215                 .params_for_tuning_caps = {0, 0},
1216                 .featureEnable = 0x0d,
1217                 /*
1218                  * bit0 - enable tx temp comp - disabled
1219                  * bit1 - enable tx volt comp - disabled
1220                  * bit2 - enable fastClock - enabled
1221                  * bit3 - enable doubling - enabled
1222                  * bit4 - enable internal regulator - disabled
1223                  * bit5 - enable pa predistortion - disabled
1224                  */
1225                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1226                 .eepromWriteEnableGpio = 6,
1227                 .wlanDisableGpio = 0,
1228                 .wlanLedGpio = 8,
1229                 .rxBandSelectGpio = 0xff,
1230                 .txrxgain = 0x10,
1231                 .swreg = 0,
1232         },
1233         .modalHeader2G = {
1234                 /* ar9300_modal_eep_header  2g */
1235                 /* 4 idle,t1,t2,b(4 bits per setting) */
1236                 .antCtrlCommon = LE32(0x110),
1237                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1238                 .antCtrlCommon2 = LE32(0x44444),
1239
1240                 /*
1241                  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
1242                  * rx1, rx12, b (2 bits each)
1243                  */
1244                 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
1245
1246                 /*
1247                  * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
1248                  * for ar9280 (0xa20c/b20c 5:0)
1249                  */
1250                 .xatten1DB = {0, 0, 0},
1251
1252                 /*
1253                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1254                  * for ar9280 (0xa20c/b20c 16:12
1255                  */
1256                 .xatten1Margin = {0, 0, 0},
1257                 .tempSlope = 25,
1258                 .voltSlope = 0,
1259
1260                 /*
1261                  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
1262                  * channels in usual fbin coding format
1263                  */
1264                 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1265
1266                 /*
1267                  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
1268                  * if the register is per chain
1269                  */
1270                 .noiseFloorThreshCh = {-1, 0, 0},
1271                 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
1272                 .quick_drop = 0,
1273                 .xpaBiasLvl = 0,
1274                 .txFrameToDataStart = 0x0e,
1275                 .txFrameToPaOn = 0x0e,
1276                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1277                 .antennaGain = 0,
1278                 .switchSettling = 0x2c,
1279                 .adcDesiredSize = -30,
1280                 .txEndToXpaOff = 0,
1281                 .txEndToRxOn = 0x2,
1282                 .txFrameToXpaOn = 0xe,
1283                 .thresh62 = 28,
1284                 .papdRateMaskHt20 = LE32(0x0c80c080),
1285                 .papdRateMaskHt40 = LE32(0x0080c080),
1286                 .futureModal = {
1287                         0, 0, 0, 0, 0, 0, 0, 0,
1288                 },
1289         },
1290         .base_ext1 = {
1291                 .ant_div_control = 0,
1292                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1293         },
1294         .calFreqPier2G = {
1295                 FREQ2FBIN(2412, 1),
1296                 FREQ2FBIN(2437, 1),
1297                 FREQ2FBIN(2462, 1),
1298         },
1299         /* ar9300_cal_data_per_freq_op_loop 2g */
1300         .calPierData2G = {
1301                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1302                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1303                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1304         },
1305         .calTarget_freqbin_Cck = {
1306                 FREQ2FBIN(2412, 1),
1307                 FREQ2FBIN(2472, 1),
1308         },
1309         .calTarget_freqbin_2G = {
1310                 FREQ2FBIN(2412, 1),
1311                 FREQ2FBIN(2437, 1),
1312                 FREQ2FBIN(2472, 1)
1313         },
1314         .calTarget_freqbin_2GHT20 = {
1315                 FREQ2FBIN(2412, 1),
1316                 FREQ2FBIN(2437, 1),
1317                 FREQ2FBIN(2472, 1)
1318         },
1319         .calTarget_freqbin_2GHT40 = {
1320                 FREQ2FBIN(2412, 1),
1321                 FREQ2FBIN(2437, 1),
1322                 FREQ2FBIN(2472, 1)
1323         },
1324         .calTargetPowerCck = {
1325                 /* 1L-5L,5S,11L,11S */
1326                 { {34, 34, 34, 34} },
1327                 { {34, 34, 34, 34} },
1328         },
1329         .calTargetPower2G = {
1330                 /* 6-24,36,48,54 */
1331                 { {34, 34, 32, 32} },
1332                 { {34, 34, 32, 32} },
1333                 { {34, 34, 32, 32} },
1334         },
1335         .calTargetPower2GHT20 = {
1336                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1337                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1338                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1339         },
1340         .calTargetPower2GHT40 = {
1341                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1342                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1343                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1344         },
1345         .ctlIndex_2G =  {
1346                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1347                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1348         },
1349         .ctl_freqbin_2G = {
1350                 {
1351                         FREQ2FBIN(2412, 1),
1352                         FREQ2FBIN(2417, 1),
1353                         FREQ2FBIN(2457, 1),
1354                         FREQ2FBIN(2462, 1)
1355                 },
1356                 {
1357                         FREQ2FBIN(2412, 1),
1358                         FREQ2FBIN(2417, 1),
1359                         FREQ2FBIN(2462, 1),
1360                         0xFF,
1361                 },
1362
1363                 {
1364                         FREQ2FBIN(2412, 1),
1365                         FREQ2FBIN(2417, 1),
1366                         FREQ2FBIN(2462, 1),
1367                         0xFF,
1368                 },
1369                 {
1370                         FREQ2FBIN(2422, 1),
1371                         FREQ2FBIN(2427, 1),
1372                         FREQ2FBIN(2447, 1),
1373                         FREQ2FBIN(2452, 1)
1374                 },
1375
1376                 {
1377                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1378                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1379                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1380                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
1381                 },
1382
1383                 {
1384                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1385                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1386                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1387                         0,
1388                 },
1389
1390                 {
1391                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1392                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1393                         FREQ2FBIN(2472, 1),
1394                         0,
1395                 },
1396
1397                 {
1398                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1399                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1400                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1401                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1402                 },
1403
1404                 {
1405                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1406                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1407                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1408                 },
1409
1410                 {
1411                         /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1412                         /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1413                         /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1414                         0
1415                 },
1416
1417                 {
1418                         /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1419                         /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1420                         /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1421                         0
1422                 },
1423
1424                 {
1425                         /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1426                         /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1427                         /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1428                         /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1429                 }
1430         },
1431         .ctlPowerData_2G = {
1432                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1433                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1434                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
1435
1436                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
1437                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1438                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1439
1440                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
1441                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1442                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1443
1444                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1445                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
1446                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
1447         },
1448         .modalHeader5G = {
1449                 /* 4 idle,t1,t2,b (4 bits per setting) */
1450                 .antCtrlCommon = LE32(0x220),
1451                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
1452                 .antCtrlCommon2 = LE32(0x44444),
1453                 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
1454                 .antCtrlChain = {
1455                         LE16(0x150), LE16(0x150), LE16(0x150),
1456                 },
1457                 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
1458                 .xatten1DB = {0, 0, 0},
1459
1460                 /*
1461                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1462                  * for merlin (0xa20c/b20c 16:12
1463                  */
1464                 .xatten1Margin = {0, 0, 0},
1465                 .tempSlope = 45,
1466                 .voltSlope = 0,
1467                 /* spurChans spur channels in usual fbin coding format */
1468                 .spurChans = {0, 0, 0, 0, 0},
1469                 /* noiseFloorThreshCh Check if the register is per chain */
1470                 .noiseFloorThreshCh = {-1, 0, 0},
1471                 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
1472                 .quick_drop = 0,
1473                 .xpaBiasLvl = 0,
1474                 .txFrameToDataStart = 0x0e,
1475                 .txFrameToPaOn = 0x0e,
1476                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1477                 .antennaGain = 0,
1478                 .switchSettling = 0x2d,
1479                 .adcDesiredSize = -30,
1480                 .txEndToXpaOff = 0,
1481                 .txEndToRxOn = 0x2,
1482                 .txFrameToXpaOn = 0xe,
1483                 .thresh62 = 28,
1484                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
1485                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
1486                 .futureModal = {
1487                         0, 0, 0, 0, 0, 0, 0, 0,
1488                 },
1489         },
1490         .base_ext2 = {
1491                 .tempSlopeLow = 40,
1492                 .tempSlopeHigh = 50,
1493                 .xatten1DBLow = {0, 0, 0},
1494                 .xatten1MarginLow = {0, 0, 0},
1495                 .xatten1DBHigh = {0, 0, 0},
1496                 .xatten1MarginHigh = {0, 0, 0}
1497         },
1498         .calFreqPier5G = {
1499                 FREQ2FBIN(5180, 0),
1500                 FREQ2FBIN(5220, 0),
1501                 FREQ2FBIN(5320, 0),
1502                 FREQ2FBIN(5400, 0),
1503                 FREQ2FBIN(5500, 0),
1504                 FREQ2FBIN(5600, 0),
1505                 FREQ2FBIN(5700, 0),
1506                 FREQ2FBIN(5785, 0)
1507         },
1508         .calPierData5G = {
1509                 {
1510                         {0, 0, 0, 0, 0},
1511                         {0, 0, 0, 0, 0},
1512                         {0, 0, 0, 0, 0},
1513                         {0, 0, 0, 0, 0},
1514                         {0, 0, 0, 0, 0},
1515                         {0, 0, 0, 0, 0},
1516                         {0, 0, 0, 0, 0},
1517                         {0, 0, 0, 0, 0},
1518                 },
1519                 {
1520                         {0, 0, 0, 0, 0},
1521                         {0, 0, 0, 0, 0},
1522                         {0, 0, 0, 0, 0},
1523                         {0, 0, 0, 0, 0},
1524                         {0, 0, 0, 0, 0},
1525                         {0, 0, 0, 0, 0},
1526                         {0, 0, 0, 0, 0},
1527                         {0, 0, 0, 0, 0},
1528                 },
1529                 {
1530                         {0, 0, 0, 0, 0},
1531                         {0, 0, 0, 0, 0},
1532                         {0, 0, 0, 0, 0},
1533                         {0, 0, 0, 0, 0},
1534                         {0, 0, 0, 0, 0},
1535                         {0, 0, 0, 0, 0},
1536                         {0, 0, 0, 0, 0},
1537                         {0, 0, 0, 0, 0},
1538                 },
1539
1540         },
1541         .calTarget_freqbin_5G = {
1542                 FREQ2FBIN(5180, 0),
1543                 FREQ2FBIN(5240, 0),
1544                 FREQ2FBIN(5320, 0),
1545                 FREQ2FBIN(5400, 0),
1546                 FREQ2FBIN(5500, 0),
1547                 FREQ2FBIN(5600, 0),
1548                 FREQ2FBIN(5700, 0),
1549                 FREQ2FBIN(5825, 0)
1550         },
1551         .calTarget_freqbin_5GHT20 = {
1552                 FREQ2FBIN(5180, 0),
1553                 FREQ2FBIN(5240, 0),
1554                 FREQ2FBIN(5320, 0),
1555                 FREQ2FBIN(5400, 0),
1556                 FREQ2FBIN(5500, 0),
1557                 FREQ2FBIN(5700, 0),
1558                 FREQ2FBIN(5745, 0),
1559                 FREQ2FBIN(5825, 0)
1560         },
1561         .calTarget_freqbin_5GHT40 = {
1562                 FREQ2FBIN(5180, 0),
1563                 FREQ2FBIN(5240, 0),
1564                 FREQ2FBIN(5320, 0),
1565                 FREQ2FBIN(5400, 0),
1566                 FREQ2FBIN(5500, 0),
1567                 FREQ2FBIN(5700, 0),
1568                 FREQ2FBIN(5745, 0),
1569                 FREQ2FBIN(5825, 0)
1570         },
1571         .calTargetPower5G = {
1572                 /* 6-24,36,48,54 */
1573                 { {30, 30, 28, 24} },
1574                 { {30, 30, 28, 24} },
1575                 { {30, 30, 28, 24} },
1576                 { {30, 30, 28, 24} },
1577                 { {30, 30, 28, 24} },
1578                 { {30, 30, 28, 24} },
1579                 { {30, 30, 28, 24} },
1580                 { {30, 30, 28, 24} },
1581         },
1582         .calTargetPower5GHT20 = {
1583                 /*
1584                  * 0_8_16,1-3_9-11_17-19,
1585                  * 4,5,6,7,12,13,14,15,20,21,22,23
1586                  */
1587                 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1588                 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1589                 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1590                 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1591                 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1592                 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1593                 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1594                 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1595         },
1596         .calTargetPower5GHT40 =  {
1597                 /*
1598                  * 0_8_16,1-3_9-11_17-19,
1599                  * 4,5,6,7,12,13,14,15,20,21,22,23
1600                  */
1601                 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1602                 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1603                 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1604                 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1605                 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1606                 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1607                 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1608                 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1609         },
1610         .ctlIndex_5G =  {
1611                 0x10, 0x16, 0x18, 0x40, 0x46,
1612                 0x48, 0x30, 0x36, 0x38
1613         },
1614         .ctl_freqbin_5G =  {
1615                 {
1616                         /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1617                         /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1618                         /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1619                         /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1620                         /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1621                         /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1622                         /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1623                         /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1624                 },
1625                 {
1626                         /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1627                         /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1628                         /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1629                         /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1630                         /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1631                         /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1632                         /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1633                         /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1634                 },
1635
1636                 {
1637                         /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1638                         /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1639                         /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1640                         /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1641                         /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1642                         /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1643                         /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1644                         /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1645                 },
1646
1647                 {
1648                         /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1649                         /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1650                         /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1651                         /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1652                         /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1653                         /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1654                         /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1655                         /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1656                 },
1657
1658                 {
1659                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1660                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1661                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1662                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1663                         /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1664                         /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1665                         /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1666                         /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1667                 },
1668
1669                 {
1670                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1671                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1672                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1673                         /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1674                         /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1675                         /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1676                         /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1677                         /* Data[5].ctlEdges[7].bChannel */ 0xFF
1678                 },
1679
1680                 {
1681                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1682                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1683                         /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1684                         /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1685                         /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1686                         /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1687                         /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1688                         /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1689                 },
1690
1691                 {
1692                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1693                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1694                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1695                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1696                         /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1697                         /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1698                         /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1699                         /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1700                 },
1701
1702                 {
1703                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1704                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1705                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1706                         /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1707                         /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1708                         /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1709                         /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1710                         /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1711                 }
1712         },
1713         .ctlPowerData_5G = {
1714                 {
1715                         {
1716                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1717                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1718                         }
1719                 },
1720                 {
1721                         {
1722                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1723                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1724                         }
1725                 },
1726                 {
1727                         {
1728                                 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1729                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1730                         }
1731                 },
1732                 {
1733                         {
1734                                 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1735                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1736                         }
1737                 },
1738                 {
1739                         {
1740                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1741                                 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1742                         }
1743                 },
1744                 {
1745                         {
1746                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1747                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1748                         }
1749                 },
1750                 {
1751                         {
1752                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1753                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1754                         }
1755                 },
1756                 {
1757                         {
1758                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1759                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1760                         }
1761                 },
1762                 {
1763                         {
1764                                 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1765                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1766                         }
1767                 },
1768         }
1769 };
1770
1771
1772 static const struct ar9300_eeprom ar9300_x112 = {
1773         .eepromVersion = 2,
1774         .templateVersion = 5,
1775         .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1776         .custData = {"x112-041-f0000"},
1777         .baseEepHeader = {
1778                 .regDmn = { LE16(0), LE16(0x1f) },
1779                 .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
1780                 .opCapFlags = {
1781                         .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
1782                         .eepMisc = 0,
1783                 },
1784                 .rfSilent = 0,
1785                 .blueToothOptions = 0,
1786                 .deviceCap = 0,
1787                 .deviceType = 5, /* takes lower byte in eeprom location */
1788                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1789                 .params_for_tuning_caps = {0, 0},
1790                 .featureEnable = 0x0d,
1791                 /*
1792                  * bit0 - enable tx temp comp - disabled
1793                  * bit1 - enable tx volt comp - disabled
1794                  * bit2 - enable fastclock - enabled
1795                  * bit3 - enable doubling - enabled
1796                  * bit4 - enable internal regulator - disabled
1797                  * bit5 - enable pa predistortion - disabled
1798                  */
1799                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1800                 .eepromWriteEnableGpio = 6,
1801                 .wlanDisableGpio = 0,
1802                 .wlanLedGpio = 8,
1803                 .rxBandSelectGpio = 0xff,
1804                 .txrxgain = 0x0,
1805                 .swreg = 0,
1806         },
1807         .modalHeader2G = {
1808                 /* ar9300_modal_eep_header  2g */
1809                 /* 4 idle,t1,t2,b(4 bits per setting) */
1810                 .antCtrlCommon = LE32(0x110),
1811                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1812                 .antCtrlCommon2 = LE32(0x22222),
1813
1814                 /*
1815                  * antCtrlChain[ar9300_max_chains]; 6 idle, t, r,
1816                  * rx1, rx12, b (2 bits each)
1817                  */
1818                 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
1819
1820                 /*
1821                  * xatten1DB[AR9300_max_chains];  3 xatten1_db
1822                  * for ar9280 (0xa20c/b20c 5:0)
1823                  */
1824                 .xatten1DB = {0x1b, 0x1b, 0x1b},
1825
1826                 /*
1827                  * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
1828                  * for ar9280 (0xa20c/b20c 16:12
1829                  */
1830                 .xatten1Margin = {0x15, 0x15, 0x15},
1831                 .tempSlope = 50,
1832                 .voltSlope = 0,
1833
1834                 /*
1835                  * spurChans[OSPrey_eeprom_modal_sPURS]; spur
1836                  * channels in usual fbin coding format
1837                  */
1838                 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1839
1840                 /*
1841                  * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check
1842                  * if the register is per chain
1843                  */
1844                 .noiseFloorThreshCh = {-1, 0, 0},
1845                 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
1846                 .quick_drop = 0,
1847                 .xpaBiasLvl = 0,
1848                 .txFrameToDataStart = 0x0e,
1849                 .txFrameToPaOn = 0x0e,
1850                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1851                 .antennaGain = 0,
1852                 .switchSettling = 0x2c,
1853                 .adcDesiredSize = -30,
1854                 .txEndToXpaOff = 0,
1855                 .txEndToRxOn = 0x2,
1856                 .txFrameToXpaOn = 0xe,
1857                 .thresh62 = 28,
1858                 .papdRateMaskHt20 = LE32(0x0c80c080),
1859                 .papdRateMaskHt40 = LE32(0x0080c080),
1860                 .futureModal = {
1861                         0, 0, 0, 0, 0, 0, 0, 0,
1862                 },
1863         },
1864         .base_ext1 = {
1865                 .ant_div_control = 0,
1866                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1867         },
1868         .calFreqPier2G = {
1869                 FREQ2FBIN(2412, 1),
1870                 FREQ2FBIN(2437, 1),
1871                 FREQ2FBIN(2472, 1),
1872         },
1873         /* ar9300_cal_data_per_freq_op_loop 2g */
1874         .calPierData2G = {
1875                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1876                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1877                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1878         },
1879         .calTarget_freqbin_Cck = {
1880                 FREQ2FBIN(2412, 1),
1881                 FREQ2FBIN(2472, 1),
1882         },
1883         .calTarget_freqbin_2G = {
1884                 FREQ2FBIN(2412, 1),
1885                 FREQ2FBIN(2437, 1),
1886                 FREQ2FBIN(2472, 1)
1887         },
1888         .calTarget_freqbin_2GHT20 = {
1889                 FREQ2FBIN(2412, 1),
1890                 FREQ2FBIN(2437, 1),
1891                 FREQ2FBIN(2472, 1)
1892         },
1893         .calTarget_freqbin_2GHT40 = {
1894                 FREQ2FBIN(2412, 1),
1895                 FREQ2FBIN(2437, 1),
1896                 FREQ2FBIN(2472, 1)
1897         },
1898         .calTargetPowerCck = {
1899                 /* 1L-5L,5S,11L,11s */
1900                 { {38, 38, 38, 38} },
1901                 { {38, 38, 38, 38} },
1902         },
1903         .calTargetPower2G = {
1904                 /* 6-24,36,48,54 */
1905                 { {38, 38, 36, 34} },
1906                 { {38, 38, 36, 34} },
1907                 { {38, 38, 34, 32} },
1908         },
1909         .calTargetPower2GHT20 = {
1910                 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1911                 { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} },
1912                 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1913         },
1914         .calTargetPower2GHT40 = {
1915                 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1916                 { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} },
1917                 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1918         },
1919         .ctlIndex_2G =  {
1920                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1921                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1922         },
1923         .ctl_freqbin_2G = {
1924                 {
1925                         FREQ2FBIN(2412, 1),
1926                         FREQ2FBIN(2417, 1),
1927                         FREQ2FBIN(2457, 1),
1928                         FREQ2FBIN(2462, 1)
1929                 },
1930                 {
1931                         FREQ2FBIN(2412, 1),
1932                         FREQ2FBIN(2417, 1),
1933                         FREQ2FBIN(2462, 1),
1934                         0xFF,
1935                 },
1936
1937                 {
1938                         FREQ2FBIN(2412, 1),
1939                         FREQ2FBIN(2417, 1),
1940                         FREQ2FBIN(2462, 1),
1941                         0xFF,
1942                 },
1943                 {
1944                         FREQ2FBIN(2422, 1),
1945                         FREQ2FBIN(2427, 1),
1946                         FREQ2FBIN(2447, 1),
1947                         FREQ2FBIN(2452, 1)
1948                 },
1949
1950                 {
1951                         /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1952                         /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1953                         /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1954                         /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1),
1955                 },
1956
1957                 {
1958                         /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1959                         /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1960                         /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1961                         0,
1962                 },
1963
1964                 {
1965                         /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1966                         /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1967                         FREQ2FBIN(2472, 1),
1968                         0,
1969                 },
1970
1971                 {
1972                         /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
1973                         /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
1974                         /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
1975                         /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
1976                 },
1977
1978                 {
1979                         /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1980                         /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1981                         /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1982                 },
1983
1984                 {
1985                         /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1986                         /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1987                         /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1988                         0
1989                 },
1990
1991                 {
1992                         /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1993                         /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1994                         /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1995                         0
1996                 },
1997
1998                 {
1999                         /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
2000                         /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
2001                         /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
2002                         /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2003                 }
2004         },
2005         .ctlPowerData_2G = {
2006                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2007                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2008                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
2009
2010                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
2011                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2012                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2013
2014                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2015                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2016                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2017
2018                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2019                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2020                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2021         },
2022         .modalHeader5G = {
2023                 /* 4 idle,t1,t2,b (4 bits per setting) */
2024                 .antCtrlCommon = LE32(0x110),
2025                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2026                 .antCtrlCommon2 = LE32(0x22222),
2027                 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2028                 .antCtrlChain = {
2029                         LE16(0x0), LE16(0x0), LE16(0x0),
2030                 },
2031                 /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */
2032                 .xatten1DB = {0x13, 0x19, 0x17},
2033
2034                 /*
2035                  * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
2036                  * for merlin (0xa20c/b20c 16:12
2037                  */
2038                 .xatten1Margin = {0x19, 0x19, 0x19},
2039                 .tempSlope = 70,
2040                 .voltSlope = 15,
2041                 /* spurChans spur channels in usual fbin coding format */
2042                 .spurChans = {0, 0, 0, 0, 0},
2043                 /* noiseFloorThreshch check if the register is per chain */
2044                 .noiseFloorThreshCh = {-1, 0, 0},
2045                 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
2046                 .quick_drop = 0,
2047                 .xpaBiasLvl = 0,
2048                 .txFrameToDataStart = 0x0e,
2049                 .txFrameToPaOn = 0x0e,
2050                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2051                 .antennaGain = 0,
2052                 .switchSettling = 0x2d,
2053                 .adcDesiredSize = -30,
2054                 .txEndToXpaOff = 0,
2055                 .txEndToRxOn = 0x2,
2056                 .txFrameToXpaOn = 0xe,
2057                 .thresh62 = 28,
2058                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2059                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2060                 .futureModal = {
2061                         0, 0, 0, 0, 0, 0, 0, 0,
2062                 },
2063         },
2064         .base_ext2 = {
2065                 .tempSlopeLow = 72,
2066                 .tempSlopeHigh = 105,
2067                 .xatten1DBLow = {0x10, 0x14, 0x10},
2068                 .xatten1MarginLow = {0x19, 0x19 , 0x19},
2069                 .xatten1DBHigh = {0x1d, 0x20, 0x24},
2070                 .xatten1MarginHigh = {0x10, 0x10, 0x10}
2071         },
2072         .calFreqPier5G = {
2073                 FREQ2FBIN(5180, 0),
2074                 FREQ2FBIN(5220, 0),
2075                 FREQ2FBIN(5320, 0),
2076                 FREQ2FBIN(5400, 0),
2077                 FREQ2FBIN(5500, 0),
2078                 FREQ2FBIN(5600, 0),
2079                 FREQ2FBIN(5700, 0),
2080                 FREQ2FBIN(5785, 0)
2081         },
2082         .calPierData5G = {
2083                 {
2084                         {0, 0, 0, 0, 0},
2085                         {0, 0, 0, 0, 0},
2086                         {0, 0, 0, 0, 0},
2087                         {0, 0, 0, 0, 0},
2088                         {0, 0, 0, 0, 0},
2089                         {0, 0, 0, 0, 0},
2090                         {0, 0, 0, 0, 0},
2091                         {0, 0, 0, 0, 0},
2092                 },
2093                 {
2094                         {0, 0, 0, 0, 0},
2095                         {0, 0, 0, 0, 0},
2096                         {0, 0, 0, 0, 0},
2097                         {0, 0, 0, 0, 0},
2098                         {0, 0, 0, 0, 0},
2099                         {0, 0, 0, 0, 0},
2100                         {0, 0, 0, 0, 0},
2101                         {0, 0, 0, 0, 0},
2102                 },
2103                 {
2104                         {0, 0, 0, 0, 0},
2105                         {0, 0, 0, 0, 0},
2106                         {0, 0, 0, 0, 0},
2107                         {0, 0, 0, 0, 0},
2108                         {0, 0, 0, 0, 0},
2109                         {0, 0, 0, 0, 0},
2110                         {0, 0, 0, 0, 0},
2111                         {0, 0, 0, 0, 0},
2112                 },
2113
2114         },
2115         .calTarget_freqbin_5G = {
2116                 FREQ2FBIN(5180, 0),
2117                 FREQ2FBIN(5220, 0),
2118                 FREQ2FBIN(5320, 0),
2119                 FREQ2FBIN(5400, 0),
2120                 FREQ2FBIN(5500, 0),
2121                 FREQ2FBIN(5600, 0),
2122                 FREQ2FBIN(5725, 0),
2123                 FREQ2FBIN(5825, 0)
2124         },
2125         .calTarget_freqbin_5GHT20 = {
2126                 FREQ2FBIN(5180, 0),
2127                 FREQ2FBIN(5220, 0),
2128                 FREQ2FBIN(5320, 0),
2129                 FREQ2FBIN(5400, 0),
2130                 FREQ2FBIN(5500, 0),
2131                 FREQ2FBIN(5600, 0),
2132                 FREQ2FBIN(5725, 0),
2133                 FREQ2FBIN(5825, 0)
2134         },
2135         .calTarget_freqbin_5GHT40 = {
2136                 FREQ2FBIN(5180, 0),
2137                 FREQ2FBIN(5220, 0),
2138                 FREQ2FBIN(5320, 0),
2139                 FREQ2FBIN(5400, 0),
2140                 FREQ2FBIN(5500, 0),
2141                 FREQ2FBIN(5600, 0),
2142                 FREQ2FBIN(5725, 0),
2143                 FREQ2FBIN(5825, 0)
2144         },
2145         .calTargetPower5G = {
2146                 /* 6-24,36,48,54 */
2147                 { {32, 32, 28, 26} },
2148                 { {32, 32, 28, 26} },
2149                 { {32, 32, 28, 26} },
2150                 { {32, 32, 26, 24} },
2151                 { {32, 32, 26, 24} },
2152                 { {32, 32, 24, 22} },
2153                 { {30, 30, 24, 22} },
2154                 { {30, 30, 24, 22} },
2155         },
2156         .calTargetPower5GHT20 = {
2157                 /*
2158                  * 0_8_16,1-3_9-11_17-19,
2159                  * 4,5,6,7,12,13,14,15,20,21,22,23
2160                  */
2161                 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2162                 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2163                 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2164                 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} },
2165                 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} },
2166                 { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} },
2167                 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2168                 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2169         },
2170         .calTargetPower5GHT40 =  {
2171                 /*
2172                  * 0_8_16,1-3_9-11_17-19,
2173                  * 4,5,6,7,12,13,14,15,20,21,22,23
2174                  */
2175                 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2176                 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2177                 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2178                 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} },
2179                 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} },
2180                 { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2181                 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2182                 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2183         },
2184         .ctlIndex_5G =  {
2185                 0x10, 0x16, 0x18, 0x40, 0x46,
2186                 0x48, 0x30, 0x36, 0x38
2187         },
2188         .ctl_freqbin_5G =  {
2189                 {
2190                         /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2191                         /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2192                         /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2193                         /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2194                         /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0),
2195                         /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2196                         /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2197                         /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2198                 },
2199                 {
2200                         /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2201                         /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2202                         /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2203                         /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2204                         /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0),
2205                         /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2206                         /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2207                         /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2208                 },
2209
2210                 {
2211                         /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2212                         /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2213                         /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2214                         /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0),
2215                         /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0),
2216                         /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0),
2217                         /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0),
2218                         /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0)
2219                 },
2220
2221                 {
2222                         /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2223                         /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2224                         /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0),
2225                         /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0),
2226                         /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2227                         /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2228                         /* Data[3].ctledges[6].bchannel */ 0xFF,
2229                         /* Data[3].ctledges[7].bchannel */ 0xFF,
2230                 },
2231
2232                 {
2233                         /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2234                         /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2235                         /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0),
2236                         /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0),
2237                         /* Data[4].ctledges[4].bchannel */ 0xFF,
2238                         /* Data[4].ctledges[5].bchannel */ 0xFF,
2239                         /* Data[4].ctledges[6].bchannel */ 0xFF,
2240                         /* Data[4].ctledges[7].bchannel */ 0xFF,
2241                 },
2242
2243                 {
2244                         /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2245                         /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0),
2246                         /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0),
2247                         /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2248                         /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0),
2249                         /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2250                         /* Data[5].ctledges[6].bchannel */ 0xFF,
2251                         /* Data[5].ctledges[7].bchannel */ 0xFF
2252                 },
2253
2254                 {
2255                         /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2256                         /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2257                         /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0),
2258                         /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0),
2259                         /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2260                         /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0),
2261                         /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0),
2262                         /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0)
2263                 },
2264
2265                 {
2266                         /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2267                         /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2268                         /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0),
2269                         /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2270                         /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0),
2271                         /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2272                         /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2273                         /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2274                 },
2275
2276                 {
2277                         /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2278                         /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2279                         /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2280                         /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2281                         /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0),
2282                         /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2283                         /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0),
2284                         /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0)
2285                 }
2286         },
2287         .ctlPowerData_5G = {
2288                 {
2289                         {
2290                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2291                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2292                         }
2293                 },
2294                 {
2295                         {
2296                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2297                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2298                         }
2299                 },
2300                 {
2301                         {
2302                                 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2303                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2304                         }
2305                 },
2306                 {
2307                         {
2308                                 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2309                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2310                         }
2311                 },
2312                 {
2313                         {
2314                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2315                                 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2316                         }
2317                 },
2318                 {
2319                         {
2320                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2321                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2322                         }
2323                 },
2324                 {
2325                         {
2326                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2327                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2328                         }
2329                 },
2330                 {
2331                         {
2332                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2333                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2334                         }
2335                 },
2336                 {
2337                         {
2338                                 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2339                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2340                         }
2341                 },
2342         }
2343 };
2344
2345 static const struct ar9300_eeprom ar9300_h116 = {
2346         .eepromVersion = 2,
2347         .templateVersion = 4,
2348         .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
2349         .custData = {"h116-041-f0000"},
2350         .baseEepHeader = {
2351                 .regDmn = { LE16(0), LE16(0x1f) },
2352                 .txrxMask =  0x33, /* 4 bits tx and 4 bits rx */
2353                 .opCapFlags = {
2354                         .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
2355                         .eepMisc = 0,
2356                 },
2357                 .rfSilent = 0,
2358                 .blueToothOptions = 0,
2359                 .deviceCap = 0,
2360                 .deviceType = 5, /* takes lower byte in eeprom location */
2361                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
2362                 .params_for_tuning_caps = {0, 0},
2363                 .featureEnable = 0x0d,
2364                  /*
2365                   * bit0 - enable tx temp comp - disabled
2366                   * bit1 - enable tx volt comp - disabled
2367                   * bit2 - enable fastClock - enabled
2368                   * bit3 - enable doubling - enabled
2369                   * bit4 - enable internal regulator - disabled
2370                   * bit5 - enable pa predistortion - disabled
2371                   */
2372                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
2373                 .eepromWriteEnableGpio = 6,
2374                 .wlanDisableGpio = 0,
2375                 .wlanLedGpio = 8,
2376                 .rxBandSelectGpio = 0xff,
2377                 .txrxgain = 0x10,
2378                 .swreg = 0,
2379          },
2380         .modalHeader2G = {
2381         /* ar9300_modal_eep_header  2g */
2382                 /* 4 idle,t1,t2,b(4 bits per setting) */
2383                 .antCtrlCommon = LE32(0x110),
2384                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
2385                 .antCtrlCommon2 = LE32(0x44444),
2386
2387                 /*
2388                  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
2389                  * rx1, rx12, b (2 bits each)
2390                  */
2391                 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
2392
2393                 /*
2394                  * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
2395                  * for ar9280 (0xa20c/b20c 5:0)
2396                  */
2397                 .xatten1DB = {0x1f, 0x1f, 0x1f},
2398
2399                 /*
2400                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2401                  * for ar9280 (0xa20c/b20c 16:12
2402                  */
2403                 .xatten1Margin = {0x12, 0x12, 0x12},
2404                 .tempSlope = 25,
2405                 .voltSlope = 0,
2406
2407                 /*
2408                  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
2409                  * channels in usual fbin coding format
2410                  */
2411                 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
2412
2413                 /*
2414                  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
2415                  * if the register is per chain
2416                  */
2417                 .noiseFloorThreshCh = {-1, 0, 0},
2418                 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
2419                 .quick_drop = 0,
2420                 .xpaBiasLvl = 0,
2421                 .txFrameToDataStart = 0x0e,
2422                 .txFrameToPaOn = 0x0e,
2423                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2424                 .antennaGain = 0,
2425                 .switchSettling = 0x2c,
2426                 .adcDesiredSize = -30,
2427                 .txEndToXpaOff = 0,
2428                 .txEndToRxOn = 0x2,
2429                 .txFrameToXpaOn = 0xe,
2430                 .thresh62 = 28,
2431                 .papdRateMaskHt20 = LE32(0x0c80C080),
2432                 .papdRateMaskHt40 = LE32(0x0080C080),
2433                 .futureModal = {
2434                         0, 0, 0, 0, 0, 0, 0, 0,
2435                 },
2436          },
2437          .base_ext1 = {
2438                 .ant_div_control = 0,
2439                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
2440          },
2441         .calFreqPier2G = {
2442                 FREQ2FBIN(2412, 1),
2443                 FREQ2FBIN(2437, 1),
2444                 FREQ2FBIN(2462, 1),
2445          },
2446         /* ar9300_cal_data_per_freq_op_loop 2g */
2447         .calPierData2G = {
2448                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2449                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2450                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2451          },
2452         .calTarget_freqbin_Cck = {
2453                 FREQ2FBIN(2412, 1),
2454                 FREQ2FBIN(2472, 1),
2455          },
2456         .calTarget_freqbin_2G = {
2457                 FREQ2FBIN(2412, 1),
2458                 FREQ2FBIN(2437, 1),
2459                 FREQ2FBIN(2472, 1)
2460          },
2461         .calTarget_freqbin_2GHT20 = {
2462                 FREQ2FBIN(2412, 1),
2463                 FREQ2FBIN(2437, 1),
2464                 FREQ2FBIN(2472, 1)
2465          },
2466         .calTarget_freqbin_2GHT40 = {
2467                 FREQ2FBIN(2412, 1),
2468                 FREQ2FBIN(2437, 1),
2469                 FREQ2FBIN(2472, 1)
2470          },
2471         .calTargetPowerCck = {
2472                  /* 1L-5L,5S,11L,11S */
2473                  { {34, 34, 34, 34} },
2474                  { {34, 34, 34, 34} },
2475         },
2476         .calTargetPower2G = {
2477                  /* 6-24,36,48,54 */
2478                  { {34, 34, 32, 32} },
2479                  { {34, 34, 32, 32} },
2480                  { {34, 34, 32, 32} },
2481         },
2482         .calTargetPower2GHT20 = {
2483                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2484                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2485                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2486         },
2487         .calTargetPower2GHT40 = {
2488                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2489                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2490                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2491         },
2492         .ctlIndex_2G =  {
2493                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
2494                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
2495         },
2496         .ctl_freqbin_2G = {
2497                 {
2498                         FREQ2FBIN(2412, 1),
2499                         FREQ2FBIN(2417, 1),
2500                         FREQ2FBIN(2457, 1),
2501                         FREQ2FBIN(2462, 1)
2502                 },
2503                 {
2504                         FREQ2FBIN(2412, 1),
2505                         FREQ2FBIN(2417, 1),
2506                         FREQ2FBIN(2462, 1),
2507                         0xFF,
2508                 },
2509
2510                 {
2511                         FREQ2FBIN(2412, 1),
2512                         FREQ2FBIN(2417, 1),
2513                         FREQ2FBIN(2462, 1),
2514                         0xFF,
2515                 },
2516                 {
2517                         FREQ2FBIN(2422, 1),
2518                         FREQ2FBIN(2427, 1),
2519                         FREQ2FBIN(2447, 1),
2520                         FREQ2FBIN(2452, 1)
2521                 },
2522
2523                 {
2524                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2525                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2526                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2527                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
2528                 },
2529
2530                 {
2531                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2532                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2533                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2534                         0,
2535                 },
2536
2537                 {
2538                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2539                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2540                         FREQ2FBIN(2472, 1),
2541                         0,
2542                 },
2543
2544                 {
2545                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2546                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2547                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2548                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2549                 },
2550
2551                 {
2552                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2553                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2554                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2555                 },
2556
2557                 {
2558                         /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2559                         /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2560                         /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2561                         0
2562                 },
2563
2564                 {
2565                         /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2566                         /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2567                         /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2568                         0
2569                 },
2570
2571                 {
2572                         /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2573                         /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2574                         /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2575                         /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2576                 }
2577          },
2578         .ctlPowerData_2G = {
2579                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2580                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2581                  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
2582
2583                  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
2584                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2585                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2586
2587                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2588                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2589                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2590
2591                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2592                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2593                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2594          },
2595         .modalHeader5G = {
2596                 /* 4 idle,t1,t2,b (4 bits per setting) */
2597                 .antCtrlCommon = LE32(0x220),
2598                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2599                 .antCtrlCommon2 = LE32(0x44444),
2600                  /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2601                 .antCtrlChain = {
2602                         LE16(0x150), LE16(0x150), LE16(0x150),
2603                 },
2604                  /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
2605                 .xatten1DB = {0x19, 0x19, 0x19},
2606
2607                 /*
2608                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2609                  * for merlin (0xa20c/b20c 16:12
2610                  */
2611                 .xatten1Margin = {0x14, 0x14, 0x14},
2612                 .tempSlope = 70,
2613                 .voltSlope = 0,
2614                 /* spurChans spur channels in usual fbin coding format */
2615                 .spurChans = {0, 0, 0, 0, 0},
2616                 /* noiseFloorThreshCh Check if the register is per chain */
2617                 .noiseFloorThreshCh = {-1, 0, 0},
2618                 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
2619                 .quick_drop = 0,
2620                 .xpaBiasLvl = 0,
2621                 .txFrameToDataStart = 0x0e,
2622                 .txFrameToPaOn = 0x0e,
2623                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2624                 .antennaGain = 0,
2625                 .switchSettling = 0x2d,
2626                 .adcDesiredSize = -30,
2627                 .txEndToXpaOff = 0,
2628                 .txEndToRxOn = 0x2,
2629                 .txFrameToXpaOn = 0xe,
2630                 .thresh62 = 28,
2631                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2632                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2633                 .futureModal = {
2634                         0, 0, 0, 0, 0, 0, 0, 0,
2635                 },
2636          },
2637         .base_ext2 = {
2638                 .tempSlopeLow = 35,
2639                 .tempSlopeHigh = 50,
2640                 .xatten1DBLow = {0, 0, 0},
2641                 .xatten1MarginLow = {0, 0, 0},
2642                 .xatten1DBHigh = {0, 0, 0},
2643                 .xatten1MarginHigh = {0, 0, 0}
2644          },
2645         .calFreqPier5G = {
2646                 FREQ2FBIN(5160, 0),
2647                 FREQ2FBIN(5220, 0),
2648                 FREQ2FBIN(5320, 0),
2649                 FREQ2FBIN(5400, 0),
2650                 FREQ2FBIN(5500, 0),
2651                 FREQ2FBIN(5600, 0),
2652                 FREQ2FBIN(5700, 0),
2653                 FREQ2FBIN(5785, 0)
2654         },
2655         .calPierData5G = {
2656                         {
2657                                 {0, 0, 0, 0, 0},
2658                                 {0, 0, 0, 0, 0},
2659                                 {0, 0, 0, 0, 0},
2660                                 {0, 0, 0, 0, 0},
2661                                 {0, 0, 0, 0, 0},
2662                                 {0, 0, 0, 0, 0},
2663                                 {0, 0, 0, 0, 0},
2664                                 {0, 0, 0, 0, 0},
2665                         },
2666                         {
2667                                 {0, 0, 0, 0, 0},
2668                                 {0, 0, 0, 0, 0},
2669                                 {0, 0, 0, 0, 0},
2670                                 {0, 0, 0, 0, 0},
2671                                 {0, 0, 0, 0, 0},
2672                                 {0, 0, 0, 0, 0},
2673                                 {0, 0, 0, 0, 0},
2674                                 {0, 0, 0, 0, 0},
2675                         },
2676                         {
2677                                 {0, 0, 0, 0, 0},
2678                                 {0, 0, 0, 0, 0},
2679                                 {0, 0, 0, 0, 0},
2680                                 {0, 0, 0, 0, 0},
2681                                 {0, 0, 0, 0, 0},
2682                                 {0, 0, 0, 0, 0},
2683                                 {0, 0, 0, 0, 0},
2684                                 {0, 0, 0, 0, 0},
2685                         },
2686
2687         },
2688         .calTarget_freqbin_5G = {
2689                 FREQ2FBIN(5180, 0),
2690                 FREQ2FBIN(5240, 0),
2691                 FREQ2FBIN(5320, 0),
2692                 FREQ2FBIN(5400, 0),
2693                 FREQ2FBIN(5500, 0),
2694                 FREQ2FBIN(5600, 0),
2695                 FREQ2FBIN(5700, 0),
2696                 FREQ2FBIN(5825, 0)
2697         },
2698         .calTarget_freqbin_5GHT20 = {
2699                 FREQ2FBIN(5180, 0),
2700                 FREQ2FBIN(5240, 0),
2701                 FREQ2FBIN(5320, 0),
2702                 FREQ2FBIN(5400, 0),
2703                 FREQ2FBIN(5500, 0),
2704                 FREQ2FBIN(5700, 0),
2705                 FREQ2FBIN(5745, 0),
2706                 FREQ2FBIN(5825, 0)
2707         },
2708         .calTarget_freqbin_5GHT40 = {
2709                 FREQ2FBIN(5180, 0),
2710                 FREQ2FBIN(5240, 0),
2711                 FREQ2FBIN(5320, 0),
2712                 FREQ2FBIN(5400, 0),
2713                 FREQ2FBIN(5500, 0),
2714                 FREQ2FBIN(5700, 0),
2715                 FREQ2FBIN(5745, 0),
2716                 FREQ2FBIN(5825, 0)
2717          },
2718         .calTargetPower5G = {
2719                 /* 6-24,36,48,54 */
2720                 { {30, 30, 28, 24} },
2721                 { {30, 30, 28, 24} },
2722                 { {30, 30, 28, 24} },
2723                 { {30, 30, 28, 24} },
2724                 { {30, 30, 28, 24} },
2725                 { {30, 30, 28, 24} },
2726                 { {30, 30, 28, 24} },
2727                 { {30, 30, 28, 24} },
2728          },
2729         .calTargetPower5GHT20 = {
2730                 /*
2731                  * 0_8_16,1-3_9-11_17-19,
2732                  * 4,5,6,7,12,13,14,15,20,21,22,23
2733                  */
2734                 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2735                 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2736                 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2737                 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2738                 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2739                 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2740                 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2741                 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2742          },
2743         .calTargetPower5GHT40 =  {
2744                 /*
2745                  * 0_8_16,1-3_9-11_17-19,
2746                  * 4,5,6,7,12,13,14,15,20,21,22,23
2747                  */
2748                 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2749                 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2750                 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2751                 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2752                 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2753                 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2754                 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2755                 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2756          },
2757         .ctlIndex_5G =  {
2758                 0x10, 0x16, 0x18, 0x40, 0x46,
2759                 0x48, 0x30, 0x36, 0x38
2760         },
2761         .ctl_freqbin_5G =  {
2762                 {
2763                         /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2764                         /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2765                         /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2766                         /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2767                         /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
2768                         /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2769                         /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2770                         /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2771                 },
2772                 {
2773                         /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2774                         /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2775                         /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2776                         /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2777                         /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
2778                         /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2779                         /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2780                         /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2781                 },
2782
2783                 {
2784                         /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2785                         /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2786                         /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2787                         /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
2788                         /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
2789                         /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
2790                         /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
2791                         /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
2792                 },
2793
2794                 {
2795                         /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2796                         /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2797                         /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
2798                         /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
2799                         /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2800                         /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2801                         /* Data[3].ctlEdges[6].bChannel */ 0xFF,
2802                         /* Data[3].ctlEdges[7].bChannel */ 0xFF,
2803                 },
2804
2805                 {
2806                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2807                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2808                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
2809                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
2810                         /* Data[4].ctlEdges[4].bChannel */ 0xFF,
2811                         /* Data[4].ctlEdges[5].bChannel */ 0xFF,
2812                         /* Data[4].ctlEdges[6].bChannel */ 0xFF,
2813                         /* Data[4].ctlEdges[7].bChannel */ 0xFF,
2814                 },
2815
2816                 {
2817                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2818                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
2819                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
2820                         /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2821                         /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
2822                         /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2823                         /* Data[5].ctlEdges[6].bChannel */ 0xFF,
2824                         /* Data[5].ctlEdges[7].bChannel */ 0xFF
2825                 },
2826
2827                 {
2828                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2829                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2830                         /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
2831                         /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
2832                         /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2833                         /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
2834                         /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
2835                         /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
2836                 },
2837
2838                 {
2839                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2840                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2841                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
2842                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2843                         /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
2844                         /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2845                         /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2846                         /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2847                 },
2848
2849                 {
2850                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2851                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2852                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2853                         /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2854                         /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
2855                         /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2856                         /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
2857                         /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
2858                 }
2859          },
2860         .ctlPowerData_5G = {
2861                 {
2862                         {
2863                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2864                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2865                         }
2866                 },
2867                 {
2868                         {
2869                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2870                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2871                         }
2872                 },
2873                 {
2874                         {
2875                                 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2876                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2877                         }
2878                 },
2879                 {
2880                         {
2881                                 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2882                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2883                         }
2884                 },
2885                 {
2886                         {
2887                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2888                                 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2889                         }
2890                 },
2891                 {
2892                         {
2893                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2894                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2895                         }
2896                 },
2897                 {
2898                         {
2899                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2900                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2901                         }
2902                 },
2903                 {
2904                         {
2905                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2906                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2907                         }
2908                 },
2909                 {
2910                         {
2911                                 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2912                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2913                         }
2914                 },
2915          }
2916 };
2917
2918
2919 static const struct ar9300_eeprom *ar9300_eep_templates[] = {
2920         &ar9300_default,
2921         &ar9300_x112,
2922         &ar9300_h116,
2923         &ar9300_h112,
2924         &ar9300_x113,
2925 };
2926
2927 static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id)
2928 {
2929 #define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
2930         int it;
2931
2932         for (it = 0; it < N_LOOP; it++)
2933                 if (ar9300_eep_templates[it]->templateVersion == id)
2934                         return ar9300_eep_templates[it];
2935         return NULL;
2936 #undef N_LOOP
2937 }
2938
2939
2940 static u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
2941 {
2942         if (fbin == AR5416_BCHAN_UNUSED)
2943                 return fbin;
2944
2945         return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
2946 }
2947
2948 static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah)
2949 {
2950         return 0;
2951 }
2952
2953 static int interpolate(int x, int xa, int xb, int ya, int yb)
2954 {
2955         int bf, factor, plus;
2956
2957         bf = 2 * (yb - ya) * (x - xa) / (xb - xa);
2958         factor = bf / 2;
2959         plus = bf % 2;
2960         return ya + factor + plus;
2961 }
2962
2963 static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
2964                                       enum eeprom_param param)
2965 {
2966         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
2967         struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
2968
2969         switch (param) {
2970         case EEP_MAC_LSW:
2971                 return get_unaligned_be16(eep->macAddr);
2972         case EEP_MAC_MID:
2973                 return get_unaligned_be16(eep->macAddr + 2);
2974         case EEP_MAC_MSW:
2975                 return get_unaligned_be16(eep->macAddr + 4);
2976         case EEP_REG_0:
2977                 return le16_to_cpu(pBase->regDmn[0]);
2978         case EEP_OP_CAP:
2979                 return pBase->deviceCap;
2980         case EEP_OP_MODE:
2981                 return pBase->opCapFlags.opFlags;
2982         case EEP_RF_SILENT:
2983                 return pBase->rfSilent;
2984         case EEP_TX_MASK:
2985                 return (pBase->txrxMask >> 4) & 0xf;
2986         case EEP_RX_MASK:
2987                 return pBase->txrxMask & 0xf;
2988         case EEP_DRIVE_STRENGTH:
2989 #define AR9300_EEP_BASE_DRIV_STRENGTH   0x1
2990                 return pBase->miscConfiguration & AR9300_EEP_BASE_DRIV_STRENGTH;
2991         case EEP_INTERNAL_REGULATOR:
2992                 /* Bit 4 is internal regulator flag */
2993                 return (pBase->featureEnable & 0x10) >> 4;
2994         case EEP_SWREG:
2995                 return le32_to_cpu(pBase->swreg);
2996         case EEP_PAPRD:
2997                 return !!(pBase->featureEnable & BIT(5));
2998         case EEP_CHAIN_MASK_REDUCE:
2999                 return (pBase->miscConfiguration >> 0x3) & 0x1;
3000         case EEP_ANT_DIV_CTL1:
3001                 return eep->base_ext1.ant_div_control;
3002         case EEP_ANTENNA_GAIN_5G:
3003                 return eep->modalHeader5G.antennaGain;
3004         case EEP_ANTENNA_GAIN_2G:
3005                 return eep->modalHeader2G.antennaGain;
3006         case EEP_QUICK_DROP:
3007                 return pBase->miscConfiguration & BIT(1);
3008         default:
3009                 return 0;
3010         }
3011 }
3012
3013 static bool ar9300_eeprom_read_byte(struct ath_common *common, int address,
3014                                     u8 *buffer)
3015 {
3016         u16 val;
3017
3018         if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3019                 return false;
3020
3021         *buffer = (val >> (8 * (address % 2))) & 0xff;
3022         return true;
3023 }
3024
3025 static bool ar9300_eeprom_read_word(struct ath_common *common, int address,
3026                                     u8 *buffer)
3027 {
3028         u16 val;
3029
3030         if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3031                 return false;
3032
3033         buffer[0] = val >> 8;
3034         buffer[1] = val & 0xff;
3035
3036         return true;
3037 }
3038
3039 static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer,
3040                                int count)
3041 {
3042         struct ath_common *common = ath9k_hw_common(ah);
3043         int i;
3044
3045         if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) {
3046                 ath_dbg(common, EEPROM, "eeprom address not in range\n");
3047                 return false;
3048         }
3049
3050         /*
3051          * Since we're reading the bytes in reverse order from a little-endian
3052          * word stream, an even address means we only use the lower half of
3053          * the 16-bit word at that address
3054          */
3055         if (address % 2 == 0) {
3056                 if (!ar9300_eeprom_read_byte(common, address--, buffer++))
3057                         goto error;
3058
3059                 count--;
3060         }
3061
3062         for (i = 0; i < count / 2; i++) {
3063                 if (!ar9300_eeprom_read_word(common, address, buffer))
3064                         goto error;
3065
3066                 address -= 2;
3067                 buffer += 2;
3068         }
3069
3070         if (count % 2)
3071                 if (!ar9300_eeprom_read_byte(common, address, buffer))
3072                         goto error;
3073
3074         return true;
3075
3076 error:
3077         ath_dbg(common, EEPROM, "unable to read eeprom region at offset %d\n",
3078                 address);
3079         return false;
3080 }
3081
3082 static bool ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data)
3083 {
3084         REG_READ(ah, AR9300_OTP_BASE + (4 * addr));
3085
3086         if (!ath9k_hw_wait(ah, AR9300_OTP_STATUS, AR9300_OTP_STATUS_TYPE,
3087                            AR9300_OTP_STATUS_VALID, 1000))
3088                 return false;
3089
3090         *data = REG_READ(ah, AR9300_OTP_READ_DATA);
3091         return true;
3092 }
3093
3094 static bool ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer,
3095                             int count)
3096 {
3097         u32 data;
3098         int i;
3099
3100         for (i = 0; i < count; i++) {
3101                 int offset = 8 * ((address - i) % 4);
3102                 if (!ar9300_otp_read_word(ah, (address - i) / 4, &data))
3103                         return false;
3104
3105                 buffer[i] = (data >> offset) & 0xff;
3106         }
3107
3108         return true;
3109 }
3110
3111
3112 static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference,
3113                                    int *length, int *major, int *minor)
3114 {
3115         unsigned long value[4];
3116
3117         value[0] = best[0];
3118         value[1] = best[1];
3119         value[2] = best[2];
3120         value[3] = best[3];
3121         *code = ((value[0] >> 5) & 0x0007);
3122         *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020);
3123         *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f);
3124         *major = (value[2] & 0x000f);
3125         *minor = (value[3] & 0x00ff);
3126 }
3127
3128 static u16 ar9300_comp_cksum(u8 *data, int dsize)
3129 {
3130         int it, checksum = 0;
3131
3132         for (it = 0; it < dsize; it++) {
3133                 checksum += data[it];
3134                 checksum &= 0xffff;
3135         }
3136
3137         return checksum;
3138 }
3139
3140 static bool ar9300_uncompress_block(struct ath_hw *ah,
3141                                     u8 *mptr,
3142                                     int mdataSize,
3143                                     u8 *block,
3144                                     int size)
3145 {
3146         int it;
3147         int spot;
3148         int offset;
3149         int length;
3150         struct ath_common *common = ath9k_hw_common(ah);
3151
3152         spot = 0;
3153
3154         for (it = 0; it < size; it += (length+2)) {
3155                 offset = block[it];
3156                 offset &= 0xff;
3157                 spot += offset;
3158                 length = block[it+1];
3159                 length &= 0xff;
3160
3161                 if (length > 0 && spot >= 0 && spot+length <= mdataSize) {
3162                         ath_dbg(common, EEPROM,
3163                                 "Restore at %d: spot=%d offset=%d length=%d\n",
3164                                 it, spot, offset, length);
3165                         memcpy(&mptr[spot], &block[it+2], length);
3166                         spot += length;
3167                 } else if (length > 0) {
3168                         ath_dbg(common, EEPROM,
3169                                 "Bad restore at %d: spot=%d offset=%d length=%d\n",
3170                                 it, spot, offset, length);
3171                         return false;
3172                 }
3173         }
3174         return true;
3175 }
3176
3177 static int ar9300_compress_decision(struct ath_hw *ah,
3178                                     int it,
3179                                     int code,
3180                                     int reference,
3181                                     u8 *mptr,
3182                                     u8 *word, int length, int mdata_size)
3183 {
3184         struct ath_common *common = ath9k_hw_common(ah);
3185         const struct ar9300_eeprom *eep = NULL;
3186
3187         switch (code) {
3188         case _CompressNone:
3189                 if (length != mdata_size) {
3190                         ath_dbg(common, EEPROM,
3191                                 "EEPROM structure size mismatch memory=%d eeprom=%d\n",
3192                                 mdata_size, length);
3193                         return -1;
3194                 }
3195                 memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length);
3196                 ath_dbg(common, EEPROM,
3197                         "restored eeprom %d: uncompressed, length %d\n",
3198                         it, length);
3199                 break;
3200         case _CompressBlock:
3201                 if (reference == 0) {
3202                 } else {
3203                         eep = ar9003_eeprom_struct_find_by_id(reference);
3204                         if (eep == NULL) {
3205                                 ath_dbg(common, EEPROM,
3206                                         "can't find reference eeprom struct %d\n",
3207                                         reference);
3208                                 return -1;
3209                         }
3210                         memcpy(mptr, eep, mdata_size);
3211                 }
3212                 ath_dbg(common, EEPROM,
3213                         "restore eeprom %d: block, reference %d, length %d\n",
3214                         it, reference, length);
3215                 ar9300_uncompress_block(ah, mptr, mdata_size,
3216                                         (u8 *) (word + COMP_HDR_LEN), length);
3217                 break;
3218         default:
3219                 ath_dbg(common, EEPROM, "unknown compression code %d\n", code);
3220                 return -1;
3221         }
3222         return 0;
3223 }
3224
3225 typedef bool (*eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer,
3226                                int count);
3227
3228 static bool ar9300_check_header(void *data)
3229 {
3230         u32 *word = data;
3231         return !(*word == 0 || *word == ~0);
3232 }
3233
3234 static bool ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read,
3235                                        int base_addr)
3236 {
3237         u8 header[4];
3238
3239         if (!read(ah, base_addr, header, 4))
3240                 return false;
3241
3242         return ar9300_check_header(header);
3243 }
3244
3245 static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr,
3246                                        int mdata_size)
3247 {
3248         struct ath_common *common = ath9k_hw_common(ah);
3249         u16 *data = (u16 *) mptr;
3250         int i;
3251
3252         for (i = 0; i < mdata_size / 2; i++, data++)
3253                 ath9k_hw_nvram_read(common, i, data);
3254
3255         return 0;
3256 }
3257 /*
3258  * Read the configuration data from the eeprom.
3259  * The data can be put in any specified memory buffer.
3260  *
3261  * Returns -1 on error.
3262  * Returns address of next memory location on success.
3263  */
3264 static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
3265                                           u8 *mptr, int mdata_size)
3266 {
3267 #define MDEFAULT 15
3268 #define MSTATE 100
3269         int cptr;
3270         u8 *word;
3271         int code;
3272         int reference, length, major, minor;
3273         int osize;
3274         int it;
3275         u16 checksum, mchecksum;
3276         struct ath_common *common = ath9k_hw_common(ah);
3277         eeprom_read_op read;
3278
3279         if (ath9k_hw_use_flash(ah))
3280                 return ar9300_eeprom_restore_flash(ah, mptr, mdata_size);
3281
3282         word = kzalloc(2048, GFP_KERNEL);
3283         if (!word)
3284                 return -ENOMEM;
3285
3286         memcpy(mptr, &ar9300_default, mdata_size);
3287
3288         read = ar9300_read_eeprom;
3289         if (AR_SREV_9485(ah))
3290                 cptr = AR9300_BASE_ADDR_4K;
3291         else if (AR_SREV_9330(ah))
3292                 cptr = AR9300_BASE_ADDR_512;
3293         else
3294                 cptr = AR9300_BASE_ADDR;
3295         ath_dbg(common, EEPROM, "Trying EEPROM access at Address 0x%04x\n",
3296                 cptr);
3297         if (ar9300_check_eeprom_header(ah, read, cptr))
3298                 goto found;
3299
3300         cptr = AR9300_BASE_ADDR_512;
3301         ath_dbg(common, EEPROM, "Trying EEPROM access at Address 0x%04x\n",
3302                 cptr);
3303         if (ar9300_check_eeprom_header(ah, read, cptr))
3304                 goto found;
3305
3306         read = ar9300_read_otp;
3307         cptr = AR9300_BASE_ADDR;
3308         ath_dbg(common, EEPROM, "Trying OTP access at Address 0x%04x\n", cptr);
3309         if (ar9300_check_eeprom_header(ah, read, cptr))
3310                 goto found;
3311
3312         cptr = AR9300_BASE_ADDR_512;
3313         ath_dbg(common, EEPROM, "Trying OTP access at Address 0x%04x\n", cptr);
3314         if (ar9300_check_eeprom_header(ah, read, cptr))
3315                 goto found;
3316
3317         goto fail;
3318
3319 found:
3320         ath_dbg(common, EEPROM, "Found valid EEPROM data\n");
3321
3322         for (it = 0; it < MSTATE; it++) {
3323                 if (!read(ah, cptr, word, COMP_HDR_LEN))
3324                         goto fail;
3325
3326                 if (!ar9300_check_header(word))
3327                         break;
3328
3329                 ar9300_comp_hdr_unpack(word, &code, &reference,
3330                                        &length, &major, &minor);
3331                 ath_dbg(common, EEPROM,
3332                         "Found block at %x: code=%d ref=%d length=%d major=%d minor=%d\n",
3333                         cptr, code, reference, length, major, minor);
3334                 if ((!AR_SREV_9485(ah) && length >= 1024) ||
3335                     (AR_SREV_9485(ah) && length > EEPROM_DATA_LEN_9485)) {
3336                         ath_dbg(common, EEPROM, "Skipping bad header\n");
3337                         cptr -= COMP_HDR_LEN;
3338                         continue;
3339                 }
3340
3341                 osize = length;
3342                 read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3343                 checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
3344                 mchecksum = get_unaligned_le16(&word[COMP_HDR_LEN + osize]);
3345                 ath_dbg(common, EEPROM, "checksum %x %x\n",
3346                         checksum, mchecksum);
3347                 if (checksum == mchecksum) {
3348                         ar9300_compress_decision(ah, it, code, reference, mptr,
3349                                                  word, length, mdata_size);
3350                 } else {
3351                         ath_dbg(common, EEPROM,
3352                                 "skipping block with bad checksum\n");
3353                 }
3354                 cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3355         }
3356
3357         kfree(word);
3358         return cptr;
3359
3360 fail:
3361         kfree(word);
3362         return -1;
3363 }
3364
3365 /*
3366  * Restore the configuration structure by reading the eeprom.
3367  * This function destroys any existing in-memory structure
3368  * content.
3369  */
3370 static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)
3371 {
3372         u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep;
3373
3374         if (ar9300_eeprom_restore_internal(ah, mptr,
3375                         sizeof(struct ar9300_eeprom)) < 0)
3376                 return false;
3377
3378         return true;
3379 }
3380
3381 #if defined(CONFIG_ATH9K_DEBUGFS) || defined(CONFIG_ATH9K_HTC_DEBUGFS)
3382 static u32 ar9003_dump_modal_eeprom(char *buf, u32 len, u32 size,
3383                                     struct ar9300_modal_eep_header *modal_hdr)
3384 {
3385         PR_EEP("Chain0 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[0]));
3386         PR_EEP("Chain1 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[1]));
3387         PR_EEP("Chain2 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[2]));
3388         PR_EEP("Ant. Common Control", le32_to_cpu(modal_hdr->antCtrlCommon));
3389         PR_EEP("Ant. Common Control2", le32_to_cpu(modal_hdr->antCtrlCommon2));
3390         PR_EEP("Ant. Gain", modal_hdr->antennaGain);
3391         PR_EEP("Switch Settle", modal_hdr->switchSettling);
3392         PR_EEP("Chain0 xatten1DB", modal_hdr->xatten1DB[0]);
3393         PR_EEP("Chain1 xatten1DB", modal_hdr->xatten1DB[1]);
3394         PR_EEP("Chain2 xatten1DB", modal_hdr->xatten1DB[2]);
3395         PR_EEP("Chain0 xatten1Margin", modal_hdr->xatten1Margin[0]);
3396         PR_EEP("Chain1 xatten1Margin", modal_hdr->xatten1Margin[1]);
3397         PR_EEP("Chain2 xatten1Margin", modal_hdr->xatten1Margin[2]);
3398         PR_EEP("Temp Slope", modal_hdr->tempSlope);
3399         PR_EEP("Volt Slope", modal_hdr->voltSlope);
3400         PR_EEP("spur Channels0", modal_hdr->spurChans[0]);
3401         PR_EEP("spur Channels1", modal_hdr->spurChans[1]);
3402         PR_EEP("spur Channels2", modal_hdr->spurChans[2]);
3403         PR_EEP("spur Channels3", modal_hdr->spurChans[3]);
3404         PR_EEP("spur Channels4", modal_hdr->spurChans[4]);
3405         PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]);
3406         PR_EEP("Chain1 NF Threshold", modal_hdr->noiseFloorThreshCh[1]);
3407         PR_EEP("Chain2 NF Threshold", modal_hdr->noiseFloorThreshCh[2]);
3408         PR_EEP("Quick Drop", modal_hdr->quick_drop);
3409         PR_EEP("txEndToXpaOff", modal_hdr->txEndToXpaOff);
3410         PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl);
3411         PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart);
3412         PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn);
3413         PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn);
3414         PR_EEP("txClip", modal_hdr->txClip);
3415         PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize);
3416
3417         return len;
3418 }
3419
3420 static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
3421                                        u8 *buf, u32 len, u32 size)
3422 {
3423         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3424         struct ar9300_base_eep_hdr *pBase;
3425
3426         if (!dump_base_hdr) {
3427                 len += snprintf(buf + len, size - len,
3428                                 "%20s :\n", "2GHz modal Header");
3429                 len += ar9003_dump_modal_eeprom(buf, len, size,
3430                                                 &eep->modalHeader2G);
3431                 len += snprintf(buf + len, size - len,
3432                                 "%20s :\n", "5GHz modal Header");
3433                 len += ar9003_dump_modal_eeprom(buf, len, size,
3434                                                 &eep->modalHeader5G);
3435                 goto out;
3436         }
3437
3438         pBase = &eep->baseEepHeader;
3439
3440         PR_EEP("EEPROM Version", ah->eeprom.ar9300_eep.eepromVersion);
3441         PR_EEP("RegDomain1", le16_to_cpu(pBase->regDmn[0]));
3442         PR_EEP("RegDomain2", le16_to_cpu(pBase->regDmn[1]));
3443         PR_EEP("TX Mask", (pBase->txrxMask >> 4));
3444         PR_EEP("RX Mask", (pBase->txrxMask & 0x0f));
3445         PR_EEP("Allow 5GHz", !!(pBase->opCapFlags.opFlags &
3446                                 AR5416_OPFLAGS_11A));
3447         PR_EEP("Allow 2GHz", !!(pBase->opCapFlags.opFlags &
3448                                 AR5416_OPFLAGS_11G));
3449         PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags.opFlags &
3450                                         AR5416_OPFLAGS_N_2G_HT20));
3451         PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags.opFlags &
3452                                         AR5416_OPFLAGS_N_2G_HT40));
3453         PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags.opFlags &
3454                                         AR5416_OPFLAGS_N_5G_HT20));
3455         PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags.opFlags &
3456                                         AR5416_OPFLAGS_N_5G_HT40));
3457         PR_EEP("Big Endian", !!(pBase->opCapFlags.eepMisc & 0x01));
3458         PR_EEP("RF Silent", pBase->rfSilent);
3459         PR_EEP("BT option", pBase->blueToothOptions);
3460         PR_EEP("Device Cap", pBase->deviceCap);
3461         PR_EEP("Device Type", pBase->deviceType);
3462         PR_EEP("Power Table Offset", pBase->pwrTableOffset);
3463         PR_EEP("Tuning Caps1", pBase->params_for_tuning_caps[0]);
3464         PR_EEP("Tuning Caps2", pBase->params_for_tuning_caps[1]);
3465         PR_EEP("Enable Tx Temp Comp", !!(pBase->featureEnable & BIT(0)));
3466         PR_EEP("Enable Tx Volt Comp", !!(pBase->featureEnable & BIT(1)));
3467         PR_EEP("Enable fast clock", !!(pBase->featureEnable & BIT(2)));
3468         PR_EEP("Enable doubling", !!(pBase->featureEnable & BIT(3)));
3469         PR_EEP("Internal regulator", !!(pBase->featureEnable & BIT(4)));
3470         PR_EEP("Enable Paprd", !!(pBase->featureEnable & BIT(5)));
3471         PR_EEP("Driver Strength", !!(pBase->miscConfiguration & BIT(0)));
3472         PR_EEP("Quick Drop", !!(pBase->miscConfiguration & BIT(1)));
3473         PR_EEP("Chain mask Reduce", (pBase->miscConfiguration >> 0x3) & 0x1);
3474         PR_EEP("Write enable Gpio", pBase->eepromWriteEnableGpio);
3475         PR_EEP("WLAN Disable Gpio", pBase->wlanDisableGpio);
3476         PR_EEP("WLAN LED Gpio", pBase->wlanLedGpio);
3477         PR_EEP("Rx Band Select Gpio", pBase->rxBandSelectGpio);
3478         PR_EEP("Tx Gain", pBase->txrxgain >> 4);
3479         PR_EEP("Rx Gain", pBase->txrxgain & 0xf);
3480         PR_EEP("SW Reg", le32_to_cpu(pBase->swreg));
3481
3482         len += snprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress",
3483                         ah->eeprom.ar9300_eep.macAddr);
3484 out:
3485         if (len > size)
3486                 len = size;
3487
3488         return len;
3489 }
3490 #else
3491 static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
3492                                        u8 *buf, u32 len, u32 size)
3493 {
3494         return 0;
3495 }
3496 #endif
3497
3498 /* XXX: review hardware docs */
3499 static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah)
3500 {
3501         return ah->eeprom.ar9300_eep.eepromVersion;
3502 }
3503
3504 /* XXX: could be read from the eepromVersion, not sure yet */
3505 static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah)
3506 {
3507         return 0;
3508 }
3509
3510 static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
3511 {
3512         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3513
3514         if (is2ghz)
3515                 return eep->modalHeader2G.xpaBiasLvl;
3516         else
3517                 return eep->modalHeader5G.xpaBiasLvl;
3518 }
3519
3520 static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
3521 {
3522         int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
3523
3524         if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
3525                 REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
3526         else if (AR_SREV_9462(ah))
3527                 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
3528         else {
3529                 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
3530                 REG_RMW_FIELD(ah, AR_CH0_THERM,
3531                                 AR_CH0_THERM_XPABIASLVL_MSB,
3532                                 bias >> 2);
3533                 REG_RMW_FIELD(ah, AR_CH0_THERM,
3534                                 AR_CH0_THERM_XPASHORT2GND, 1);
3535         }
3536 }
3537
3538 static u16 ar9003_switch_com_spdt_get(struct ath_hw *ah, bool is_2ghz)
3539 {
3540         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3541         __le16 val;
3542
3543         if (is_2ghz)
3544                 val = eep->modalHeader2G.switchcomspdt;
3545         else
3546                 val = eep->modalHeader5G.switchcomspdt;
3547         return le16_to_cpu(val);
3548 }
3549
3550
3551 static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
3552 {
3553         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3554         __le32 val;
3555
3556         if (is2ghz)
3557                 val = eep->modalHeader2G.antCtrlCommon;
3558         else
3559                 val = eep->modalHeader5G.antCtrlCommon;
3560         return le32_to_cpu(val);
3561 }
3562
3563 static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz)
3564 {
3565         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3566         __le32 val;
3567
3568         if (is2ghz)
3569                 val = eep->modalHeader2G.antCtrlCommon2;
3570         else
3571                 val = eep->modalHeader5G.antCtrlCommon2;
3572         return le32_to_cpu(val);
3573 }
3574
3575 static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah,
3576                                         int chain,
3577                                         bool is2ghz)
3578 {
3579         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3580         __le16 val = 0;
3581
3582         if (chain >= 0 && chain < AR9300_MAX_CHAINS) {
3583                 if (is2ghz)
3584                         val = eep->modalHeader2G.antCtrlChain[chain];
3585                 else
3586                         val = eep->modalHeader5G.antCtrlChain[chain];
3587         }
3588
3589         return le16_to_cpu(val);
3590 }
3591
3592 static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3593 {
3594         int chain;
3595         u32 regval;
3596         u32 ant_div_ctl1;
3597         static const u32 switch_chain_reg[AR9300_MAX_CHAINS] = {
3598                         AR_PHY_SWITCH_CHAIN_0,
3599                         AR_PHY_SWITCH_CHAIN_1,
3600                         AR_PHY_SWITCH_CHAIN_2,
3601         };
3602
3603         u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
3604
3605         if (AR_SREV_9462(ah)) {
3606                 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3607                                 AR_SWITCH_TABLE_COM_AR9462_ALL, value);
3608         } else
3609                 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3610                               AR_SWITCH_TABLE_COM_ALL, value);
3611
3612
3613         /*
3614          *   AR9462 defines new switch table for BT/WLAN,
3615          *       here's new field name in XXX.ref for both 2G and 5G.
3616          *   Register: [GLB_CONTROL] GLB_CONTROL (@0x20044)
3617          *   15:12   R/W     SWITCH_TABLE_COM_SPDT_WLAN_RX
3618          * SWITCH_TABLE_COM_SPDT_WLAN_RX
3619          *
3620          *   11:8     R/W     SWITCH_TABLE_COM_SPDT_WLAN_TX
3621          * SWITCH_TABLE_COM_SPDT_WLAN_TX
3622          *
3623          *   7:4 R/W  SWITCH_TABLE_COM_SPDT_WLAN_IDLE
3624          * SWITCH_TABLE_COM_SPDT_WLAN_IDLE
3625          */
3626         if (AR_SREV_9462_20_OR_LATER(ah)) {
3627                 value = ar9003_switch_com_spdt_get(ah, is2ghz);
3628                 REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL,
3629                                 AR_SWITCH_TABLE_COM_SPDT_ALL, value);
3630         }
3631
3632         value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
3633         REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
3634
3635         for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
3636                 if ((ah->rxchainmask & BIT(chain)) ||
3637                     (ah->txchainmask & BIT(chain))) {
3638                         value = ar9003_hw_ant_ctrl_chain_get(ah, chain,
3639                                                              is2ghz);
3640                         REG_RMW_FIELD(ah, switch_chain_reg[chain],
3641                                       AR_SWITCH_TABLE_ALL, value);
3642                 }
3643         }
3644
3645         if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3646                 value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);
3647                 /*
3648                  * main_lnaconf, alt_lnaconf, main_tb, alt_tb
3649                  * are the fields present
3650                  */
3651                 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3652                 regval &= (~AR_ANT_DIV_CTRL_ALL);
3653                 regval |= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
3654                 /* enable_lnadiv */
3655                 regval &= (~AR_PHY_9485_ANT_DIV_LNADIV);
3656                 regval |= ((value >> 6) & 0x1) <<
3657                                 AR_PHY_9485_ANT_DIV_LNADIV_S;
3658                 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3659
3660                 /*enable fast_div */
3661                 regval = REG_READ(ah, AR_PHY_CCK_DETECT);
3662                 regval &= (~AR_FAST_DIV_ENABLE);
3663                 regval |= ((value >> 7) & 0x1) <<
3664                                 AR_FAST_DIV_ENABLE_S;
3665                 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
3666                 ant_div_ctl1 =
3667                         ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
3668                 /* check whether antenna diversity is enabled */
3669                 if ((ant_div_ctl1 >> 0x6) == 0x3) {
3670                         regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3671                         /*
3672                          * clear bits 25-30 main_lnaconf, alt_lnaconf,
3673                          * main_tb, alt_tb
3674                          */
3675                         regval &= (~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
3676                                         AR_PHY_9485_ANT_DIV_ALT_LNACONF |
3677                                         AR_PHY_9485_ANT_DIV_ALT_GAINTB |
3678                                         AR_PHY_9485_ANT_DIV_MAIN_GAINTB));
3679                         /* by default use LNA1 for the main antenna */
3680                         regval |= (AR_PHY_9485_ANT_DIV_LNA1 <<
3681                                         AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S);
3682                         regval |= (AR_PHY_9485_ANT_DIV_LNA2 <<
3683                                         AR_PHY_9485_ANT_DIV_ALT_LNACONF_S);
3684                         REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3685                 }
3686
3687
3688         }
3689
3690 }
3691
3692 static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
3693 {
3694         int drive_strength;
3695         unsigned long reg;
3696
3697         drive_strength = ath9k_hw_ar9300_get_eeprom(ah, EEP_DRIVE_STRENGTH);
3698
3699         if (!drive_strength)
3700                 return;
3701
3702         reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1);
3703         reg &= ~0x00ffffc0;
3704         reg |= 0x5 << 21;
3705         reg |= 0x5 << 18;
3706         reg |= 0x5 << 15;
3707         reg |= 0x5 << 12;
3708         reg |= 0x5 << 9;
3709         reg |= 0x5 << 6;
3710         REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg);
3711
3712         reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2);
3713         reg &= ~0xffffffe0;
3714         reg |= 0x5 << 29;
3715         reg |= 0x5 << 26;
3716         reg |= 0x5 << 23;
3717         reg |= 0x5 << 20;
3718         reg |= 0x5 << 17;
3719         reg |= 0x5 << 14;
3720         reg |= 0x5 << 11;
3721         reg |= 0x5 << 8;
3722         reg |= 0x5 << 5;
3723         REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg);
3724
3725         reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4);
3726         reg &= ~0xff800000;
3727         reg |= 0x5 << 29;
3728         reg |= 0x5 << 26;
3729         reg |= 0x5 << 23;
3730         REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
3731 }
3732
3733 static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain,
3734                                      struct ath9k_channel *chan)
3735 {
3736         int f[3], t[3];
3737         u16 value;
3738         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3739
3740         if (chain >= 0 && chain < 3) {
3741                 if (IS_CHAN_2GHZ(chan))
3742                         return eep->modalHeader2G.xatten1DB[chain];
3743                 else if (eep->base_ext2.xatten1DBLow[chain] != 0) {
3744                         t[0] = eep->base_ext2.xatten1DBLow[chain];
3745                         f[0] = 5180;
3746                         t[1] = eep->modalHeader5G.xatten1DB[chain];
3747                         f[1] = 5500;
3748                         t[2] = eep->base_ext2.xatten1DBHigh[chain];
3749                         f[2] = 5785;
3750                         value = ar9003_hw_power_interpolate((s32) chan->channel,
3751                                                             f, t, 3);
3752                         return value;
3753                 } else
3754                         return eep->modalHeader5G.xatten1DB[chain];
3755         }
3756
3757         return 0;
3758 }
3759
3760
3761 static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain,
3762                                             struct ath9k_channel *chan)
3763 {
3764         int f[3], t[3];
3765         u16 value;
3766         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3767
3768         if (chain >= 0 && chain < 3) {
3769                 if (IS_CHAN_2GHZ(chan))
3770                         return eep->modalHeader2G.xatten1Margin[chain];
3771                 else if (eep->base_ext2.xatten1MarginLow[chain] != 0) {
3772                         t[0] = eep->base_ext2.xatten1MarginLow[chain];
3773                         f[0] = 5180;
3774                         t[1] = eep->modalHeader5G.xatten1Margin[chain];
3775                         f[1] = 5500;
3776                         t[2] = eep->base_ext2.xatten1MarginHigh[chain];
3777                         f[2] = 5785;
3778                         value = ar9003_hw_power_interpolate((s32) chan->channel,
3779                                                             f, t, 3);
3780                         return value;
3781                 } else
3782                         return eep->modalHeader5G.xatten1Margin[chain];
3783         }
3784
3785         return 0;
3786 }
3787
3788 static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)
3789 {
3790         int i;
3791         u16 value;
3792         unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0,
3793                                           AR_PHY_EXT_ATTEN_CTL_1,
3794                                           AR_PHY_EXT_ATTEN_CTL_2,
3795                                          };
3796
3797         /* Test value. if 0 then attenuation is unused. Don't load anything. */
3798         for (i = 0; i < 3; i++) {
3799                 if (ah->txchainmask & BIT(i)) {
3800                         value = ar9003_hw_atten_chain_get(ah, i, chan);
3801                         REG_RMW_FIELD(ah, ext_atten_reg[i],
3802                                       AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
3803
3804                         value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
3805                         REG_RMW_FIELD(ah, ext_atten_reg[i],
3806                                       AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN,
3807                                       value);
3808                 }
3809         }
3810 }
3811
3812 static bool is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set)
3813 {
3814         int timeout = 100;
3815
3816         while (pmu_set != REG_READ(ah, pmu_reg)) {
3817                 if (timeout-- == 0)
3818                         return false;
3819                 REG_WRITE(ah, pmu_reg, pmu_set);
3820                 udelay(10);
3821         }
3822
3823         return true;
3824 }
3825
3826 static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
3827 {
3828         int internal_regulator =
3829                 ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
3830         u32 reg_val;
3831
3832         if (internal_regulator) {
3833                 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3834                         int reg_pmu_set;
3835
3836                         reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM;
3837                         REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3838                         if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3839                                 return;
3840
3841                         if (AR_SREV_9330(ah)) {
3842                                 if (ah->is_clk_25mhz) {
3843                                         reg_pmu_set = (3 << 1) | (8 << 4) |
3844                                                       (3 << 8) | (1 << 14) |
3845                                                       (6 << 17) | (1 << 20) |
3846                                                       (3 << 24);
3847                                 } else {
3848                                         reg_pmu_set = (4 << 1)  | (7 << 4) |
3849                                                       (3 << 8)  | (1 << 14) |
3850                                                       (6 << 17) | (1 << 20) |
3851                                                       (3 << 24);
3852                                 }
3853                         } else {
3854                                 reg_pmu_set = (5 << 1) | (7 << 4) |
3855                                               (2 << 8) | (2 << 14) |
3856                                               (6 << 17) | (1 << 20) |
3857                                               (3 << 24) | (1 << 28);
3858                         }
3859
3860                         REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set);
3861                         if (!is_pmu_set(ah, AR_PHY_PMU1, reg_pmu_set))
3862                                 return;
3863
3864                         reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0xFFC00000)
3865                                         | (4 << 26);
3866                         REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3867                         if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3868                                 return;
3869
3870                         reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0x00200000)
3871                                         | (1 << 21);
3872                         REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3873                         if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3874                                 return;
3875                 } else if (AR_SREV_9462(ah)) {
3876                         reg_val = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
3877                         REG_WRITE(ah, AR_PHY_PMU1, reg_val);
3878                 } else {
3879                         /* Internal regulator is ON. Write swreg register. */
3880                         reg_val = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
3881                         REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3882                                   REG_READ(ah, AR_RTC_REG_CONTROL1) &
3883                                   (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
3884                         REG_WRITE(ah, AR_RTC_REG_CONTROL0, reg_val);
3885                         /* Set REG_CONTROL1.SWREG_PROGRAM */
3886                         REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3887                                   REG_READ(ah,
3888                                            AR_RTC_REG_CONTROL1) |
3889                                            AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
3890                 }
3891         } else {
3892                 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3893                         REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0);
3894                         while (REG_READ_FIELD(ah, AR_PHY_PMU2,
3895                                                 AR_PHY_PMU2_PGM))
3896                                 udelay(10);
3897
3898                         REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
3899                         while (!REG_READ_FIELD(ah, AR_PHY_PMU1,
3900                                                 AR_PHY_PMU1_PWD))
3901                                 udelay(10);
3902                         REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0x1);
3903                         while (!REG_READ_FIELD(ah, AR_PHY_PMU2,
3904                                                 AR_PHY_PMU2_PGM))
3905                                 udelay(10);
3906                 } else if (AR_SREV_9462(ah))
3907                         REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
3908                 else {
3909                         reg_val = REG_READ(ah, AR_RTC_SLEEP_CLK) |
3910                                 AR_RTC_FORCE_SWREG_PRD;
3911                         REG_WRITE(ah, AR_RTC_SLEEP_CLK, reg_val);
3912                 }
3913         }
3914
3915 }
3916
3917 static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah)
3918 {
3919         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3920         u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];
3921
3922         if (eep->baseEepHeader.featureEnable & 0x40) {
3923                 tuning_caps_param &= 0x7f;
3924                 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC,
3925                               tuning_caps_param);
3926                 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPOUTDAC,
3927                               tuning_caps_param);
3928         }
3929 }
3930
3931 static void ar9003_hw_quick_drop_apply(struct ath_hw *ah, u16 freq)
3932 {
3933         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3934         int quick_drop = ath9k_hw_ar9300_get_eeprom(ah, EEP_QUICK_DROP);
3935         s32 t[3], f[3] = {5180, 5500, 5785};
3936
3937         if (!quick_drop)
3938                 return;
3939
3940         if (freq < 4000)
3941                 quick_drop = eep->modalHeader2G.quick_drop;
3942         else {
3943                 t[0] = eep->base_ext1.quick_drop_low;
3944                 t[1] = eep->modalHeader5G.quick_drop;
3945                 t[2] = eep->base_ext1.quick_drop_high;
3946                 quick_drop = ar9003_hw_power_interpolate(freq, f, t, 3);
3947         }
3948         REG_RMW_FIELD(ah, AR_PHY_AGC, AR_PHY_AGC_QUICK_DROP, quick_drop);
3949 }
3950
3951 static void ar9003_hw_txend_to_xpa_off_apply(struct ath_hw *ah, u16 freq)
3952 {
3953         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3954         u32 value;
3955
3956         value = (freq < 4000) ? eep->modalHeader2G.txEndToXpaOff :
3957                                 eep->modalHeader5G.txEndToXpaOff;
3958
3959         REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
3960                       AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF, value);
3961         REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
3962                       AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF, value);
3963 }
3964
3965 static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
3966                                              struct ath9k_channel *chan)
3967 {
3968         ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan));
3969         ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
3970         ar9003_hw_drive_strength_apply(ah);
3971         ar9003_hw_atten_apply(ah, chan);
3972         ar9003_hw_quick_drop_apply(ah, chan->channel);
3973         if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah))
3974                 ar9003_hw_internal_regulator_apply(ah);
3975         if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
3976                 ar9003_hw_apply_tuning_caps(ah);
3977         ar9003_hw_txend_to_xpa_off_apply(ah, chan->channel);
3978 }
3979
3980 static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
3981                                       struct ath9k_channel *chan)
3982 {
3983 }
3984
3985 /*
3986  * Returns the interpolated y value corresponding to the specified x value
3987  * from the np ordered pairs of data (px,py).
3988  * The pairs do not have to be in any order.
3989  * If the specified x value is less than any of the px,
3990  * the returned y value is equal to the py for the lowest px.
3991  * If the specified x value is greater than any of the px,
3992  * the returned y value is equal to the py for the highest px.
3993  */
3994 static int ar9003_hw_power_interpolate(int32_t x,
3995                                        int32_t *px, int32_t *py, u_int16_t np)
3996 {
3997         int ip = 0;
3998         int lx = 0, ly = 0, lhave = 0;
3999         int hx = 0, hy = 0, hhave = 0;
4000         int dx = 0;
4001         int y = 0;
4002
4003         lhave = 0;
4004         hhave = 0;
4005
4006         /* identify best lower and higher x calibration measurement */
4007         for (ip = 0; ip < np; ip++) {
4008                 dx = x - px[ip];
4009
4010                 /* this measurement is higher than our desired x */
4011                 if (dx <= 0) {
4012                         if (!hhave || dx > (x - hx)) {
4013                                 /* new best higher x measurement */
4014                                 hx = px[ip];
4015                                 hy = py[ip];
4016                                 hhave = 1;
4017                         }
4018                 }
4019                 /* this measurement is lower than our desired x */
4020                 if (dx >= 0) {
4021                         if (!lhave || dx < (x - lx)) {
4022                                 /* new best lower x measurement */
4023                                 lx = px[ip];
4024                                 ly = py[ip];
4025                                 lhave = 1;
4026                         }
4027                 }
4028         }
4029
4030         /* the low x is good */
4031         if (lhave) {
4032                 /* so is the high x */
4033                 if (hhave) {
4034                         /* they're the same, so just pick one */
4035                         if (hx == lx)
4036                                 y = ly;
4037                         else    /* interpolate  */
4038                                 y = interpolate(x, lx, hx, ly, hy);
4039                 } else          /* only low is good, use it */
4040                         y = ly;
4041         } else if (hhave)       /* only high is good, use it */
4042                 y = hy;
4043         else /* nothing is good,this should never happen unless np=0, ???? */
4044                 y = -(1 << 30);
4045         return y;
4046 }
4047
4048 static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah,
4049                                        u16 rateIndex, u16 freq, bool is2GHz)
4050 {
4051         u16 numPiers, i;
4052         s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
4053         s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
4054         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4055         struct cal_tgt_pow_legacy *pEepromTargetPwr;
4056         u8 *pFreqBin;
4057
4058         if (is2GHz) {
4059                 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
4060                 pEepromTargetPwr = eep->calTargetPower2G;
4061                 pFreqBin = eep->calTarget_freqbin_2G;
4062         } else {
4063                 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
4064                 pEepromTargetPwr = eep->calTargetPower5G;
4065                 pFreqBin = eep->calTarget_freqbin_5G;
4066         }
4067
4068         /*
4069          * create array of channels and targetpower from
4070          * targetpower piers stored on eeprom
4071          */
4072         for (i = 0; i < numPiers; i++) {
4073                 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
4074                 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4075         }
4076
4077         /* interpolate to get target power for given frequency */
4078         return (u8) ar9003_hw_power_interpolate((s32) freq,
4079                                                  freqArray,
4080                                                  targetPowerArray, numPiers);
4081 }
4082
4083 static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah,
4084                                             u16 rateIndex,
4085                                             u16 freq, bool is2GHz)
4086 {
4087         u16 numPiers, i;
4088         s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
4089         s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
4090         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4091         struct cal_tgt_pow_ht *pEepromTargetPwr;
4092         u8 *pFreqBin;
4093
4094         if (is2GHz) {
4095                 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
4096                 pEepromTargetPwr = eep->calTargetPower2GHT20;
4097                 pFreqBin = eep->calTarget_freqbin_2GHT20;
4098         } else {
4099                 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
4100                 pEepromTargetPwr = eep->calTargetPower5GHT20;
4101                 pFreqBin = eep->calTarget_freqbin_5GHT20;
4102         }
4103
4104         /*
4105          * create array of channels and targetpower
4106          * from targetpower piers stored on eeprom
4107          */
4108         for (i = 0; i < numPiers; i++) {
4109                 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
4110                 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4111         }
4112
4113         /* interpolate to get target power for given frequency */
4114         return (u8) ar9003_hw_power_interpolate((s32) freq,
4115                                                  freqArray,
4116                                                  targetPowerArray, numPiers);
4117 }
4118
4119 static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah,
4120                                             u16 rateIndex,
4121                                             u16 freq, bool is2GHz)
4122 {
4123         u16 numPiers, i;
4124         s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS];
4125         s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS];
4126         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4127         struct cal_tgt_pow_ht *pEepromTargetPwr;
4128         u8 *pFreqBin;
4129
4130         if (is2GHz) {
4131                 numPiers = AR9300_NUM_2G_40_TARGET_POWERS;
4132                 pEepromTargetPwr = eep->calTargetPower2GHT40;
4133                 pFreqBin = eep->calTarget_freqbin_2GHT40;
4134         } else {
4135                 numPiers = AR9300_NUM_5G_40_TARGET_POWERS;
4136                 pEepromTargetPwr = eep->calTargetPower5GHT40;
4137                 pFreqBin = eep->calTarget_freqbin_5GHT40;
4138         }
4139
4140         /*
4141          * create array of channels and targetpower from
4142          * targetpower piers stored on eeprom
4143          */
4144         for (i = 0; i < numPiers; i++) {
4145                 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
4146                 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4147         }
4148
4149         /* interpolate to get target power for given frequency */
4150         return (u8) ar9003_hw_power_interpolate((s32) freq,
4151                                                  freqArray,
4152                                                  targetPowerArray, numPiers);
4153 }
4154
4155 static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah,
4156                                            u16 rateIndex, u16 freq)
4157 {
4158         u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i;
4159         s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
4160         s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
4161         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4162         struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck;
4163         u8 *pFreqBin = eep->calTarget_freqbin_Cck;
4164
4165         /*
4166          * create array of channels and targetpower from
4167          * targetpower piers stored on eeprom
4168          */
4169         for (i = 0; i < numPiers; i++) {
4170                 freqArray[i] = FBIN2FREQ(pFreqBin[i], 1);
4171                 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4172         }
4173
4174         /* interpolate to get target power for given frequency */
4175         return (u8) ar9003_hw_power_interpolate((s32) freq,
4176                                                  freqArray,
4177                                                  targetPowerArray, numPiers);
4178 }
4179
4180 /* Set tx power registers to array of values passed in */
4181 static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
4182 {
4183 #define POW_SM(_r, _s)     (((_r) & 0x3f) << (_s))
4184         /* make sure forced gain is not set */
4185         REG_WRITE(ah, AR_PHY_TX_FORCED_GAIN, 0);
4186
4187         /* Write the OFDM power per rate set */
4188
4189         /* 6 (LSB), 9, 12, 18 (MSB) */
4190         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(0),
4191                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
4192                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) |
4193                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
4194                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
4195
4196         /* 24 (LSB), 36, 48, 54 (MSB) */
4197         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(1),
4198                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) |
4199                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) |
4200                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) |
4201                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
4202
4203         /* Write the CCK power per rate set */
4204
4205         /* 1L (LSB), reserved, 2L, 2S (MSB) */
4206         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(2),
4207                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) |
4208                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
4209                   /* POW_SM(txPowerTimes2,  8) | this is reserved for AR9003 */
4210                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0));
4211
4212         /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
4213         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(3),
4214                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) |
4215                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) |
4216                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) |
4217                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
4218             );
4219
4220         /* Write the power for duplicated frames - HT40 */
4221
4222         /* dup40_cck (LSB), dup40_ofdm, ext20_cck, ext20_ofdm (MSB) */
4223         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(8),
4224                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
4225                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
4226                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24],  8) |
4227                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L],  0)
4228             );
4229
4230         /* Write the HT20 power per rate set */
4231
4232         /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
4233         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(4),
4234                   POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) |
4235                   POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) |
4236                   POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) |
4237                   POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0)
4238             );
4239
4240         /* 6 (LSB), 7, 12, 13 (MSB) */
4241         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(5),
4242                   POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) |
4243                   POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) |
4244                   POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) |
4245                   POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0)
4246             );
4247
4248         /* 14 (LSB), 15, 20, 21 */
4249         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(9),
4250                   POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) |
4251                   POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) |
4252                   POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) |
4253                   POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0)
4254             );
4255
4256         /* Mixed HT20 and HT40 rates */
4257
4258         /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
4259         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(10),
4260                   POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) |
4261                   POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) |
4262                   POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) |
4263                   POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0)
4264             );
4265
4266         /*
4267          * Write the HT40 power per rate set
4268          * correct PAR difference between HT40 and HT20/LEGACY
4269          * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB)
4270          */
4271         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(6),
4272                   POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) |
4273                   POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) |
4274                   POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
4275                   POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0)
4276             );
4277
4278         /* 6 (LSB), 7, 12, 13 (MSB) */
4279         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(7),
4280                   POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) |
4281                   POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) |
4282                   POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) |
4283                   POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0)
4284             );
4285
4286         /* 14 (LSB), 15, 20, 21 */
4287         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(11),
4288                   POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) |
4289                   POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) |
4290                   POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) |
4291                   POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0)
4292             );
4293
4294         return 0;
4295 #undef POW_SM
4296 }
4297
4298 static void ar9003_hw_set_target_power_eeprom(struct ath_hw *ah, u16 freq,
4299                                               u8 *targetPowerValT2)
4300 {
4301         /* XXX: hard code for now, need to get from eeprom struct */
4302         u8 ht40PowerIncForPdadc = 0;
4303         bool is2GHz = false;
4304         unsigned int i = 0;
4305         struct ath_common *common = ath9k_hw_common(ah);
4306
4307         if (freq < 4000)
4308                 is2GHz = true;
4309
4310         targetPowerValT2[ALL_TARGET_LEGACY_6_24] =
4311             ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq,
4312                                          is2GHz);
4313         targetPowerValT2[ALL_TARGET_LEGACY_36] =
4314             ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq,
4315                                          is2GHz);
4316         targetPowerValT2[ALL_TARGET_LEGACY_48] =
4317             ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq,
4318                                          is2GHz);
4319         targetPowerValT2[ALL_TARGET_LEGACY_54] =
4320             ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq,
4321                                          is2GHz);
4322         targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] =
4323             ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L,
4324                                              freq);
4325         targetPowerValT2[ALL_TARGET_LEGACY_5S] =
4326             ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq);
4327         targetPowerValT2[ALL_TARGET_LEGACY_11L] =
4328             ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq);
4329         targetPowerValT2[ALL_TARGET_LEGACY_11S] =
4330             ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq);
4331         targetPowerValT2[ALL_TARGET_HT20_0_8_16] =
4332             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4333                                               is2GHz);
4334         targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] =
4335             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4336                                               freq, is2GHz);
4337         targetPowerValT2[ALL_TARGET_HT20_4] =
4338             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4339                                               is2GHz);
4340         targetPowerValT2[ALL_TARGET_HT20_5] =
4341             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4342                                               is2GHz);
4343         targetPowerValT2[ALL_TARGET_HT20_6] =
4344             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4345                                               is2GHz);
4346         targetPowerValT2[ALL_TARGET_HT20_7] =
4347             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4348                                               is2GHz);
4349         targetPowerValT2[ALL_TARGET_HT20_12] =
4350             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4351                                               is2GHz);
4352         targetPowerValT2[ALL_TARGET_HT20_13] =
4353             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4354                                               is2GHz);
4355         targetPowerValT2[ALL_TARGET_HT20_14] =
4356             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4357                                               is2GHz);
4358         targetPowerValT2[ALL_TARGET_HT20_15] =
4359             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4360                                               is2GHz);
4361         targetPowerValT2[ALL_TARGET_HT20_20] =
4362             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4363                                               is2GHz);
4364         targetPowerValT2[ALL_TARGET_HT20_21] =
4365             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4366                                               is2GHz);
4367         targetPowerValT2[ALL_TARGET_HT20_22] =
4368             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4369                                               is2GHz);
4370         targetPowerValT2[ALL_TARGET_HT20_23] =
4371             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4372                                               is2GHz);
4373         targetPowerValT2[ALL_TARGET_HT40_0_8_16] =
4374             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4375                                               is2GHz) + ht40PowerIncForPdadc;
4376         targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] =
4377             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4378                                               freq,
4379                                               is2GHz) + ht40PowerIncForPdadc;
4380         targetPowerValT2[ALL_TARGET_HT40_4] =
4381             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4382                                               is2GHz) + ht40PowerIncForPdadc;
4383         targetPowerValT2[ALL_TARGET_HT40_5] =
4384             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4385                                               is2GHz) + ht40PowerIncForPdadc;
4386         targetPowerValT2[ALL_TARGET_HT40_6] =
4387             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4388                                               is2GHz) + ht40PowerIncForPdadc;
4389         targetPowerValT2[ALL_TARGET_HT40_7] =
4390             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4391                                               is2GHz) + ht40PowerIncForPdadc;
4392         targetPowerValT2[ALL_TARGET_HT40_12] =
4393             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4394                                               is2GHz) + ht40PowerIncForPdadc;
4395         targetPowerValT2[ALL_TARGET_HT40_13] =
4396             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4397                                               is2GHz) + ht40PowerIncForPdadc;
4398         targetPowerValT2[ALL_TARGET_HT40_14] =
4399             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4400                                               is2GHz) + ht40PowerIncForPdadc;
4401         targetPowerValT2[ALL_TARGET_HT40_15] =
4402             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4403                                               is2GHz) + ht40PowerIncForPdadc;
4404         targetPowerValT2[ALL_TARGET_HT40_20] =
4405             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4406                                               is2GHz) + ht40PowerIncForPdadc;
4407         targetPowerValT2[ALL_TARGET_HT40_21] =
4408             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4409                                               is2GHz) + ht40PowerIncForPdadc;
4410         targetPowerValT2[ALL_TARGET_HT40_22] =
4411             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4412                                               is2GHz) + ht40PowerIncForPdadc;
4413         targetPowerValT2[ALL_TARGET_HT40_23] =
4414             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4415                                               is2GHz) + ht40PowerIncForPdadc;
4416
4417         for (i = 0; i < ar9300RateSize; i++) {
4418                 ath_dbg(common, EEPROM, "TPC[%02d] 0x%08x\n",
4419                         i, targetPowerValT2[i]);
4420         }
4421 }
4422
4423 static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
4424                                   int mode,
4425                                   int ipier,
4426                                   int ichain,
4427                                   int *pfrequency,
4428                                   int *pcorrection,
4429                                   int *ptemperature, int *pvoltage)
4430 {
4431         u8 *pCalPier;
4432         struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct;
4433         int is2GHz;
4434         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4435         struct ath_common *common = ath9k_hw_common(ah);
4436
4437         if (ichain >= AR9300_MAX_CHAINS) {
4438                 ath_dbg(common, EEPROM,
4439                         "Invalid chain index, must be less than %d\n",
4440                         AR9300_MAX_CHAINS);
4441                 return -1;
4442         }
4443
4444         if (mode) {             /* 5GHz */
4445                 if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
4446                         ath_dbg(common, EEPROM,
4447                                 "Invalid 5GHz cal pier index, must be less than %d\n",
4448                                 AR9300_NUM_5G_CAL_PIERS);
4449                         return -1;
4450                 }
4451                 pCalPier = &(eep->calFreqPier5G[ipier]);
4452                 pCalPierStruct = &(eep->calPierData5G[ichain][ipier]);
4453                 is2GHz = 0;
4454         } else {
4455                 if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
4456                         ath_dbg(common, EEPROM,
4457                                 "Invalid 2GHz cal pier index, must be less than %d\n",
4458                                 AR9300_NUM_2G_CAL_PIERS);
4459                         return -1;
4460                 }
4461
4462                 pCalPier = &(eep->calFreqPier2G[ipier]);
4463                 pCalPierStruct = &(eep->calPierData2G[ichain][ipier]);
4464                 is2GHz = 1;
4465         }
4466
4467         *pfrequency = FBIN2FREQ(*pCalPier, is2GHz);
4468         *pcorrection = pCalPierStruct->refPower;
4469         *ptemperature = pCalPierStruct->tempMeas;
4470         *pvoltage = pCalPierStruct->voltMeas;
4471
4472         return 0;
4473 }
4474
4475 static int ar9003_hw_power_control_override(struct ath_hw *ah,
4476                                             int frequency,
4477                                             int *correction,
4478                                             int *voltage, int *temperature)
4479 {
4480         int tempSlope = 0;
4481         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4482         int f[3], t[3];
4483
4484         REG_RMW(ah, AR_PHY_TPC_11_B0,
4485                 (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4486                 AR_PHY_TPC_OLPC_GAIN_DELTA);
4487         if (ah->caps.tx_chainmask & BIT(1))
4488                 REG_RMW(ah, AR_PHY_TPC_11_B1,
4489                         (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4490                         AR_PHY_TPC_OLPC_GAIN_DELTA);
4491         if (ah->caps.tx_chainmask & BIT(2))
4492                 REG_RMW(ah, AR_PHY_TPC_11_B2,
4493                         (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4494                         AR_PHY_TPC_OLPC_GAIN_DELTA);
4495
4496         /* enable open loop power control on chip */
4497         REG_RMW(ah, AR_PHY_TPC_6_B0,
4498                 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4499                 AR_PHY_TPC_6_ERROR_EST_MODE);
4500         if (ah->caps.tx_chainmask & BIT(1))
4501                 REG_RMW(ah, AR_PHY_TPC_6_B1,
4502                         (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4503                         AR_PHY_TPC_6_ERROR_EST_MODE);
4504         if (ah->caps.tx_chainmask & BIT(2))
4505                 REG_RMW(ah, AR_PHY_TPC_6_B2,
4506                         (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4507                         AR_PHY_TPC_6_ERROR_EST_MODE);
4508
4509         /*
4510          * enable temperature compensation
4511          * Need to use register names
4512          */
4513         if (frequency < 4000)
4514                 tempSlope = eep->modalHeader2G.tempSlope;
4515         else if (eep->base_ext2.tempSlopeLow != 0) {
4516                 t[0] = eep->base_ext2.tempSlopeLow;
4517                 f[0] = 5180;
4518                 t[1] = eep->modalHeader5G.tempSlope;
4519                 f[1] = 5500;
4520                 t[2] = eep->base_ext2.tempSlopeHigh;
4521                 f[2] = 5785;
4522                 tempSlope = ar9003_hw_power_interpolate((s32) frequency,
4523                                                         f, t, 3);
4524         } else
4525                 tempSlope = eep->modalHeader5G.tempSlope;
4526
4527         REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
4528
4529         if (AR_SREV_9462_20(ah))
4530                 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
4531                               AR_PHY_TPC_19_B1_ALPHA_THERM, tempSlope);
4532
4533
4534         REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE,
4535                       temperature[0]);
4536
4537         return 0;
4538 }
4539
4540 /* Apply the recorded correction values. */
4541 static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
4542 {
4543         int ichain, ipier, npier;
4544         int mode;
4545         int lfrequency[AR9300_MAX_CHAINS],
4546             lcorrection[AR9300_MAX_CHAINS],
4547             ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS];
4548         int hfrequency[AR9300_MAX_CHAINS],
4549             hcorrection[AR9300_MAX_CHAINS],
4550             htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS];
4551         int fdiff;
4552         int correction[AR9300_MAX_CHAINS],
4553             voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS];
4554         int pfrequency, pcorrection, ptemperature, pvoltage;
4555         struct ath_common *common = ath9k_hw_common(ah);
4556
4557         mode = (frequency >= 4000);
4558         if (mode)
4559                 npier = AR9300_NUM_5G_CAL_PIERS;
4560         else
4561                 npier = AR9300_NUM_2G_CAL_PIERS;
4562
4563         for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4564                 lfrequency[ichain] = 0;
4565                 hfrequency[ichain] = 100000;
4566         }
4567         /* identify best lower and higher frequency calibration measurement */
4568         for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4569                 for (ipier = 0; ipier < npier; ipier++) {
4570                         if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain,
4571                                                     &pfrequency, &pcorrection,
4572                                                     &ptemperature, &pvoltage)) {
4573                                 fdiff = frequency - pfrequency;
4574
4575                                 /*
4576                                  * this measurement is higher than
4577                                  * our desired frequency
4578                                  */
4579                                 if (fdiff <= 0) {
4580                                         if (hfrequency[ichain] <= 0 ||
4581                                             hfrequency[ichain] >= 100000 ||
4582                                             fdiff >
4583                                             (frequency - hfrequency[ichain])) {
4584                                                 /*
4585                                                  * new best higher
4586                                                  * frequency measurement
4587                                                  */
4588                                                 hfrequency[ichain] = pfrequency;
4589                                                 hcorrection[ichain] =
4590                                                     pcorrection;
4591                                                 htemperature[ichain] =
4592                                                     ptemperature;
4593                                                 hvoltage[ichain] = pvoltage;
4594                                         }
4595                                 }
4596                                 if (fdiff >= 0) {
4597                                         if (lfrequency[ichain] <= 0
4598                                             || fdiff <
4599                                             (frequency - lfrequency[ichain])) {
4600                                                 /*
4601                                                  * new best lower
4602                                                  * frequency measurement
4603                                                  */
4604                                                 lfrequency[ichain] = pfrequency;
4605                                                 lcorrection[ichain] =
4606                                                     pcorrection;
4607                                                 ltemperature[ichain] =
4608                                                     ptemperature;
4609                                                 lvoltage[ichain] = pvoltage;
4610                                         }
4611                                 }
4612                         }
4613                 }
4614         }
4615
4616         /* interpolate  */
4617         for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4618                 ath_dbg(common, EEPROM, "ch=%d f=%d low=%d %d h=%d %d\n",
4619                         ichain, frequency, lfrequency[ichain],
4620                         lcorrection[ichain], hfrequency[ichain],
4621                         hcorrection[ichain]);
4622                 /* they're the same, so just pick one */
4623                 if (hfrequency[ichain] == lfrequency[ichain]) {
4624                         correction[ichain] = lcorrection[ichain];
4625                         voltage[ichain] = lvoltage[ichain];
4626                         temperature[ichain] = ltemperature[ichain];
4627                 }
4628                 /* the low frequency is good */
4629                 else if (frequency - lfrequency[ichain] < 1000) {
4630                         /* so is the high frequency, interpolate */
4631                         if (hfrequency[ichain] - frequency < 1000) {
4632
4633                                 correction[ichain] = interpolate(frequency,
4634                                                 lfrequency[ichain],
4635                                                 hfrequency[ichain],
4636                                                 lcorrection[ichain],
4637                                                 hcorrection[ichain]);
4638
4639                                 temperature[ichain] = interpolate(frequency,
4640                                                 lfrequency[ichain],
4641                                                 hfrequency[ichain],
4642                                                 ltemperature[ichain],
4643                                                 htemperature[ichain]);
4644
4645                                 voltage[ichain] = interpolate(frequency,
4646                                                 lfrequency[ichain],
4647                                                 hfrequency[ichain],
4648                                                 lvoltage[ichain],
4649                                                 hvoltage[ichain]);
4650                         }
4651                         /* only low is good, use it */
4652                         else {
4653                                 correction[ichain] = lcorrection[ichain];
4654                                 temperature[ichain] = ltemperature[ichain];
4655                                 voltage[ichain] = lvoltage[ichain];
4656                         }
4657                 }
4658                 /* only high is good, use it */
4659                 else if (hfrequency[ichain] - frequency < 1000) {
4660                         correction[ichain] = hcorrection[ichain];
4661                         temperature[ichain] = htemperature[ichain];
4662                         voltage[ichain] = hvoltage[ichain];
4663                 } else {        /* nothing is good, presume 0???? */
4664                         correction[ichain] = 0;
4665                         temperature[ichain] = 0;
4666                         voltage[ichain] = 0;
4667                 }
4668         }
4669
4670         ar9003_hw_power_control_override(ah, frequency, correction, voltage,
4671                                          temperature);
4672
4673         ath_dbg(common, EEPROM,
4674                 "for frequency=%d, calibration correction = %d %d %d\n",
4675                 frequency, correction[0], correction[1], correction[2]);
4676
4677         return 0;
4678 }
4679
4680 static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep,
4681                                            int idx,
4682                                            int edge,
4683                                            bool is2GHz)
4684 {
4685         struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4686         struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4687
4688         if (is2GHz)
4689                 return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge]);
4690         else
4691                 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge]);
4692 }
4693
4694 static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
4695                                              int idx,
4696                                              unsigned int edge,
4697                                              u16 freq,
4698                                              bool is2GHz)
4699 {
4700         struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4701         struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4702
4703         u8 *ctl_freqbin = is2GHz ?
4704                 &eep->ctl_freqbin_2G[idx][0] :
4705                 &eep->ctl_freqbin_5G[idx][0];
4706
4707         if (is2GHz) {
4708                 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq &&
4709                     CTL_EDGE_FLAGS(ctl_2g[idx].ctlEdges[edge - 1]))
4710                         return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge - 1]);
4711         } else {
4712                 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq &&
4713                     CTL_EDGE_FLAGS(ctl_5g[idx].ctlEdges[edge - 1]))
4714                         return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]);
4715         }
4716
4717         return MAX_RATE_POWER;
4718 }
4719
4720 /*
4721  * Find the maximum conformance test limit for the given channel and CTL info
4722  */
4723 static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,
4724                                         u16 freq, int idx, bool is2GHz)
4725 {
4726         u16 twiceMaxEdgePower = MAX_RATE_POWER;
4727         u8 *ctl_freqbin = is2GHz ?
4728                 &eep->ctl_freqbin_2G[idx][0] :
4729                 &eep->ctl_freqbin_5G[idx][0];
4730         u16 num_edges = is2GHz ?
4731                 AR9300_NUM_BAND_EDGES_2G : AR9300_NUM_BAND_EDGES_5G;
4732         unsigned int edge;
4733
4734         /* Get the edge power */
4735         for (edge = 0;
4736              (edge < num_edges) && (ctl_freqbin[edge] != AR5416_BCHAN_UNUSED);
4737              edge++) {
4738                 /*
4739                  * If there's an exact channel match or an inband flag set
4740                  * on the lower channel use the given rdEdgePower
4741                  */
4742                 if (freq == ath9k_hw_fbin2freq(ctl_freqbin[edge], is2GHz)) {
4743                         twiceMaxEdgePower =
4744                                 ar9003_hw_get_direct_edge_power(eep, idx,
4745                                                                 edge, is2GHz);
4746                         break;
4747                 } else if ((edge > 0) &&
4748                            (freq < ath9k_hw_fbin2freq(ctl_freqbin[edge],
4749                                                       is2GHz))) {
4750                         twiceMaxEdgePower =
4751                                 ar9003_hw_get_indirect_edge_power(eep, idx,
4752                                                                   edge, freq,
4753                                                                   is2GHz);
4754                         /*
4755                          * Leave loop - no more affecting edges possible in
4756                          * this monotonic increasing list
4757                          */
4758                         break;
4759                 }
4760         }
4761         return twiceMaxEdgePower;
4762 }
4763
4764 static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
4765                                                struct ath9k_channel *chan,
4766                                                u8 *pPwrArray, u16 cfgCtl,
4767                                                u8 antenna_reduction,
4768                                                u16 powerLimit)
4769 {
4770         struct ath_common *common = ath9k_hw_common(ah);
4771         struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
4772         u16 twiceMaxEdgePower;
4773         int i;
4774         u16 scaledPower = 0, minCtlPower;
4775         static const u16 ctlModesFor11a[] = {
4776                 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
4777         };
4778         static const u16 ctlModesFor11g[] = {
4779                 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT,
4780                 CTL_11G_EXT, CTL_2GHT40
4781         };
4782         u16 numCtlModes;
4783         const u16 *pCtlMode;
4784         u16 ctlMode, freq;
4785         struct chan_centers centers;
4786         u8 *ctlIndex;
4787         u8 ctlNum;
4788         u16 twiceMinEdgePower;
4789         bool is2ghz = IS_CHAN_2GHZ(chan);
4790
4791         ath9k_hw_get_channel_centers(ah, chan, &centers);
4792         scaledPower = powerLimit - antenna_reduction;
4793
4794         /*
4795          * Reduce scaled Power by number of chains active to get
4796          * to per chain tx power level
4797          */
4798         switch (ar5416_get_ntxchains(ah->txchainmask)) {
4799         case 1:
4800                 break;
4801         case 2:
4802                 if (scaledPower > REDUCE_SCALED_POWER_BY_TWO_CHAIN)
4803                         scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
4804                 else
4805                         scaledPower = 0;
4806                 break;
4807         case 3:
4808                 if (scaledPower > REDUCE_SCALED_POWER_BY_THREE_CHAIN)
4809                         scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
4810                 else
4811                         scaledPower = 0;
4812                 break;
4813         }
4814
4815         scaledPower = max((u16)0, scaledPower);
4816
4817         /*
4818          * Get target powers from EEPROM - our baseline for TX Power
4819          */
4820         if (is2ghz) {
4821                 /* Setup for CTL modes */
4822                 /* CTL_11B, CTL_11G, CTL_2GHT20 */
4823                 numCtlModes =
4824                         ARRAY_SIZE(ctlModesFor11g) -
4825                                    SUB_NUM_CTL_MODES_AT_2G_40;
4826                 pCtlMode = ctlModesFor11g;
4827                 if (IS_CHAN_HT40(chan))
4828                         /* All 2G CTL's */
4829                         numCtlModes = ARRAY_SIZE(ctlModesFor11g);
4830         } else {
4831                 /* Setup for CTL modes */
4832                 /* CTL_11A, CTL_5GHT20 */
4833                 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
4834                                          SUB_NUM_CTL_MODES_AT_5G_40;
4835                 pCtlMode = ctlModesFor11a;
4836                 if (IS_CHAN_HT40(chan))
4837                         /* All 5G CTL's */
4838                         numCtlModes = ARRAY_SIZE(ctlModesFor11a);
4839         }
4840
4841         /*
4842          * For MIMO, need to apply regulatory caps individually across
4843          * dynamically running modes: CCK, OFDM, HT20, HT40
4844          *
4845          * The outer loop walks through each possible applicable runtime mode.
4846          * The inner loop walks through each ctlIndex entry in EEPROM.
4847          * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
4848          */
4849         for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
4850                 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
4851                         (pCtlMode[ctlMode] == CTL_2GHT40);
4852                 if (isHt40CtlMode)
4853                         freq = centers.synth_center;
4854                 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
4855                         freq = centers.ext_center;
4856                 else
4857                         freq = centers.ctl_center;
4858
4859                 ath_dbg(common, REGULATORY,
4860                         "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n",
4861                         ctlMode, numCtlModes, isHt40CtlMode,
4862                         (pCtlMode[ctlMode] & EXT_ADDITIVE));
4863
4864                 /* walk through each CTL index stored in EEPROM */
4865                 if (is2ghz) {
4866                         ctlIndex = pEepData->ctlIndex_2G;
4867                         ctlNum = AR9300_NUM_CTLS_2G;
4868                 } else {
4869                         ctlIndex = pEepData->ctlIndex_5G;
4870                         ctlNum = AR9300_NUM_CTLS_5G;
4871                 }
4872
4873                 twiceMaxEdgePower = MAX_RATE_POWER;
4874                 for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) {
4875                         ath_dbg(common, REGULATORY,
4876                                 "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n",
4877                                 i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
4878                                 chan->channel);
4879
4880                                 /*
4881                                  * compare test group from regulatory
4882                                  * channel list with test mode from pCtlMode
4883                                  * list
4884                                  */
4885                                 if ((((cfgCtl & ~CTL_MODE_M) |
4886                                        (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4887                                         ctlIndex[i]) ||
4888                                     (((cfgCtl & ~CTL_MODE_M) |
4889                                        (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4890                                      ((ctlIndex[i] & CTL_MODE_M) |
4891                                        SD_NO_CTL))) {
4892                                         twiceMinEdgePower =
4893                                           ar9003_hw_get_max_edge_power(pEepData,
4894                                                                        freq, i,
4895                                                                        is2ghz);
4896
4897                                         if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL)
4898                                                 /*
4899                                                  * Find the minimum of all CTL
4900                                                  * edge powers that apply to
4901                                                  * this channel
4902                                                  */
4903                                                 twiceMaxEdgePower =
4904                                                         min(twiceMaxEdgePower,
4905                                                             twiceMinEdgePower);
4906                                                 else {
4907                                                         /* specific */
4908                                                         twiceMaxEdgePower =
4909                                                           twiceMinEdgePower;
4910                                                         break;
4911                                                 }
4912                                 }
4913                         }
4914
4915                         minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
4916
4917                         ath_dbg(common, REGULATORY,
4918                                 "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n",
4919                                 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
4920                                 scaledPower, minCtlPower);
4921
4922                         /* Apply ctl mode to correct target power set */
4923                         switch (pCtlMode[ctlMode]) {
4924                         case CTL_11B:
4925                                 for (i = ALL_TARGET_LEGACY_1L_5L;
4926                                      i <= ALL_TARGET_LEGACY_11S; i++)
4927                                         pPwrArray[i] =
4928                                           (u8)min((u16)pPwrArray[i],
4929                                                   minCtlPower);
4930                                 break;
4931                         case CTL_11A:
4932                         case CTL_11G:
4933                                 for (i = ALL_TARGET_LEGACY_6_24;
4934                                      i <= ALL_TARGET_LEGACY_54; i++)
4935                                         pPwrArray[i] =
4936                                           (u8)min((u16)pPwrArray[i],
4937                                                   minCtlPower);
4938                                 break;
4939                         case CTL_5GHT20:
4940                         case CTL_2GHT20:
4941                                 for (i = ALL_TARGET_HT20_0_8_16;
4942                                      i <= ALL_TARGET_HT20_21; i++)
4943                                         pPwrArray[i] =
4944                                           (u8)min((u16)pPwrArray[i],
4945                                                   minCtlPower);
4946                                 pPwrArray[ALL_TARGET_HT20_22] =
4947                                   (u8)min((u16)pPwrArray[ALL_TARGET_HT20_22],
4948                                           minCtlPower);
4949                                 pPwrArray[ALL_TARGET_HT20_23] =
4950                                   (u8)min((u16)pPwrArray[ALL_TARGET_HT20_23],
4951                                            minCtlPower);
4952                                 break;
4953                         case CTL_5GHT40:
4954                         case CTL_2GHT40:
4955                                 for (i = ALL_TARGET_HT40_0_8_16;
4956                                      i <= ALL_TARGET_HT40_23; i++)
4957                                         pPwrArray[i] =
4958                                           (u8)min((u16)pPwrArray[i],
4959                                                   minCtlPower);
4960                                 break;
4961                         default:
4962                             break;
4963                         }
4964         } /* end ctl mode checking */
4965 }
4966
4967 static inline u8 mcsidx_to_tgtpwridx(unsigned int mcs_idx, u8 base_pwridx)
4968 {
4969         u8 mod_idx = mcs_idx % 8;
4970
4971         if (mod_idx <= 3)
4972                 return mod_idx ? (base_pwridx + 1) : base_pwridx;
4973         else
4974                 return base_pwridx + 4 * (mcs_idx / 8) + mod_idx - 2;
4975 }
4976
4977 static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
4978                                         struct ath9k_channel *chan, u16 cfgCtl,
4979                                         u8 twiceAntennaReduction,
4980                                         u8 powerLimit, bool test)
4981 {
4982         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
4983         struct ath_common *common = ath9k_hw_common(ah);
4984         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4985         struct ar9300_modal_eep_header *modal_hdr;
4986         u8 targetPowerValT2[ar9300RateSize];
4987         u8 target_power_val_t2_eep[ar9300RateSize];
4988         unsigned int i = 0, paprd_scale_factor = 0;
4989         u8 pwr_idx, min_pwridx = 0;
4990
4991         ar9003_hw_set_target_power_eeprom(ah, chan->channel, targetPowerValT2);
4992
4993         if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
4994                 if (IS_CHAN_2GHZ(chan))
4995                         modal_hdr = &eep->modalHeader2G;
4996                 else
4997                         modal_hdr = &eep->modalHeader5G;
4998
4999                 ah->paprd_ratemask =
5000                         le32_to_cpu(modal_hdr->papdRateMaskHt20) &
5001                         AR9300_PAPRD_RATE_MASK;
5002
5003                 ah->paprd_ratemask_ht40 =
5004                         le32_to_cpu(modal_hdr->papdRateMaskHt40) &
5005                         AR9300_PAPRD_RATE_MASK;
5006
5007                 paprd_scale_factor = ar9003_get_paprd_scale_factor(ah, chan);
5008                 min_pwridx = IS_CHAN_HT40(chan) ? ALL_TARGET_HT40_0_8_16 :
5009                                                   ALL_TARGET_HT20_0_8_16;
5010
5011                 if (!ah->paprd_table_write_done) {
5012                         memcpy(target_power_val_t2_eep, targetPowerValT2,
5013                                sizeof(targetPowerValT2));
5014                         for (i = 0; i < 24; i++) {
5015                                 pwr_idx = mcsidx_to_tgtpwridx(i, min_pwridx);
5016                                 if (ah->paprd_ratemask & (1 << i)) {
5017                                         if (targetPowerValT2[pwr_idx] &&
5018                                             targetPowerValT2[pwr_idx] ==
5019                                             target_power_val_t2_eep[pwr_idx])
5020                                                 targetPowerValT2[pwr_idx] -=
5021                                                         paprd_scale_factor;
5022                                 }
5023                         }
5024                 }
5025                 memcpy(target_power_val_t2_eep, targetPowerValT2,
5026                        sizeof(targetPowerValT2));
5027         }
5028
5029         ar9003_hw_set_power_per_rate_table(ah, chan,
5030                                            targetPowerValT2, cfgCtl,
5031                                            twiceAntennaReduction,
5032                                            powerLimit);
5033
5034         if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
5035                 for (i = 0; i < ar9300RateSize; i++) {
5036                         if ((ah->paprd_ratemask & (1 << i)) &&
5037                             (abs(targetPowerValT2[i] -
5038                                 target_power_val_t2_eep[i]) >
5039                             paprd_scale_factor)) {
5040                                 ah->paprd_ratemask &= ~(1 << i);
5041                                 ath_dbg(common, EEPROM,
5042                                         "paprd disabled for mcs %d\n", i);
5043                         }
5044                 }
5045         }
5046
5047         regulatory->max_power_level = 0;
5048         for (i = 0; i < ar9300RateSize; i++) {
5049                 if (targetPowerValT2[i] > regulatory->max_power_level)
5050                         regulatory->max_power_level = targetPowerValT2[i];
5051         }
5052
5053         ath9k_hw_update_regulatory_maxpower(ah);
5054
5055         if (test)
5056                 return;
5057
5058         for (i = 0; i < ar9300RateSize; i++) {
5059                 ath_dbg(common, EEPROM, "TPC[%02d] 0x%08x\n",
5060                         i, targetPowerValT2[i]);
5061         }
5062
5063         ah->txpower_limit = regulatory->max_power_level;
5064
5065         /* Write target power array to registers */
5066         ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
5067         ar9003_hw_calibration_apply(ah, chan->channel);
5068
5069         if (IS_CHAN_2GHZ(chan)) {
5070                 if (IS_CHAN_HT40(chan))
5071                         i = ALL_TARGET_HT40_0_8_16;
5072                 else
5073                         i = ALL_TARGET_HT20_0_8_16;
5074         } else {
5075                 if (IS_CHAN_HT40(chan))
5076                         i = ALL_TARGET_HT40_7;
5077                 else
5078                         i = ALL_TARGET_HT20_7;
5079         }
5080         ah->paprd_target_power = targetPowerValT2[i];
5081 }
5082
5083 static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah,
5084                                             u16 i, bool is2GHz)
5085 {
5086         return AR_NO_SPUR;
5087 }
5088
5089 s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah)
5090 {
5091         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5092
5093         return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */
5094 }
5095
5096 s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
5097 {
5098         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5099
5100         return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
5101 }
5102
5103 u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz)
5104 {
5105         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5106
5107         if (is_2ghz)
5108                 return eep->modalHeader2G.spurChans;
5109         else
5110                 return eep->modalHeader5G.spurChans;
5111 }
5112
5113 unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
5114                                            struct ath9k_channel *chan)
5115 {
5116         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5117
5118         if (IS_CHAN_2GHZ(chan))
5119                 return MS(le32_to_cpu(eep->modalHeader2G.papdRateMaskHt20),
5120                           AR9300_PAPRD_SCALE_1);
5121         else {
5122                 if (chan->channel >= 5700)
5123                 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt20),
5124                           AR9300_PAPRD_SCALE_1);
5125                 else if (chan->channel >= 5400)
5126                         return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
5127                                    AR9300_PAPRD_SCALE_2);
5128                 else
5129                         return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
5130                                   AR9300_PAPRD_SCALE_1);
5131         }
5132 }
5133
5134 const struct eeprom_ops eep_ar9300_ops = {
5135         .check_eeprom = ath9k_hw_ar9300_check_eeprom,
5136         .get_eeprom = ath9k_hw_ar9300_get_eeprom,
5137         .fill_eeprom = ath9k_hw_ar9300_fill_eeprom,
5138         .dump_eeprom = ath9k_hw_ar9003_dump_eeprom,
5139         .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
5140         .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
5141         .set_board_values = ath9k_hw_ar9300_set_board_values,
5142         .set_addac = ath9k_hw_ar9300_set_addac,
5143         .set_txpower = ath9k_hw_ar9300_set_txpower,
5144         .get_spur_channel = ath9k_hw_ar9300_get_spur_channel
5145 };