2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/moduleparam.h>
19 #include "ar5008_initvals.h"
20 #include "ar9001_initvals.h"
21 #include "ar9002_initvals.h"
22 #include "ar9002_phy.h"
24 /* General hardware code for the A5008/AR9001/AR9002 hadware families */
26 static int ar9002_hw_init_mode_regs(struct ath_hw *ah)
28 if (AR_SREV_9271(ah)) {
29 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271);
30 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271);
31 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg);
35 if (ah->config.pcie_clock_req)
36 INIT_INI_ARRAY(&ah->iniPcieSerdes,
37 ar9280PciePhy_clkreq_off_L1_9280);
39 INIT_INI_ARRAY(&ah->iniPcieSerdes,
40 ar9280PciePhy_clkreq_always_on_L1_9280);
41 #ifdef CONFIG_PM_SLEEP
42 INIT_INI_ARRAY(&ah->iniPcieSerdesWow,
46 if (AR_SREV_9287_11_OR_LATER(ah)) {
47 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1);
48 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1);
49 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
50 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2);
51 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2);
52 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
53 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2);
54 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2);
56 INIT_INI_ARRAY(&ah->iniModesFastClock,
57 ar9280Modes_fast_clock_9280_2);
58 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
59 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160);
60 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160);
61 if (AR_SREV_9160_11(ah)) {
62 INIT_INI_ARRAY(&ah->iniAddac,
63 ar5416Addac_9160_1_1);
65 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160);
67 } else if (AR_SREV_9100_OR_LATER(ah)) {
68 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100);
69 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100);
70 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100);
71 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100);
73 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes);
74 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common);
75 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC);
76 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac);
79 if (!AR_SREV_9280_20_OR_LATER(ah)) {
80 /* Common for AR5416, AR913x, AR9160 */
81 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain);
83 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0);
84 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1);
85 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2);
86 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3);
87 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7);
89 /* Common for AR5416, AR9160 */
90 if (!AR_SREV_9100(ah))
91 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6);
93 /* Common for AR913x, AR9160 */
94 if (!AR_SREV_5416(ah))
95 INIT_INI_ARRAY(&ah->iniBank6TPC,
99 /* iniAddac needs to be modified for these chips */
100 if (AR_SREV_9160(ah) || !AR_SREV_5416_22_OR_LATER(ah)) {
101 struct ar5416IniArray *addac = &ah->iniAddac;
102 u32 size = sizeof(u32) * addac->ia_rows * addac->ia_columns;
105 data = devm_kzalloc(ah->dev, size, GFP_KERNEL);
109 memcpy(data, addac->ia_array, size);
110 addac->ia_array = data;
112 if (!AR_SREV_5416_22_OR_LATER(ah)) {
113 /* override CLKDRV value */
114 INI_RA(addac, 31,1) = 0;
117 if (AR_SREV_9287_11_OR_LATER(ah)) {
118 INIT_INI_ARRAY(&ah->iniCckfirNormal,
119 ar9287Common_normal_cck_fir_coeff_9287_1_1);
120 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
121 ar9287Common_japan_2484_cck_fir_coeff_9287_1_1);
126 static void ar9280_20_hw_init_rxgain_ini(struct ath_hw *ah)
130 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >=
131 AR5416_EEP_MINOR_VER_17) {
132 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
134 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
135 INIT_INI_ARRAY(&ah->iniModesRxGain,
136 ar9280Modes_backoff_13db_rxgain_9280_2);
137 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
138 INIT_INI_ARRAY(&ah->iniModesRxGain,
139 ar9280Modes_backoff_23db_rxgain_9280_2);
141 INIT_INI_ARRAY(&ah->iniModesRxGain,
142 ar9280Modes_original_rxgain_9280_2);
144 INIT_INI_ARRAY(&ah->iniModesRxGain,
145 ar9280Modes_original_rxgain_9280_2);
149 static void ar9280_20_hw_init_txgain_ini(struct ath_hw *ah, u32 txgain_type)
151 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >=
152 AR5416_EEP_MINOR_VER_19) {
153 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
154 INIT_INI_ARRAY(&ah->iniModesTxGain,
155 ar9280Modes_high_power_tx_gain_9280_2);
157 INIT_INI_ARRAY(&ah->iniModesTxGain,
158 ar9280Modes_original_tx_gain_9280_2);
160 INIT_INI_ARRAY(&ah->iniModesTxGain,
161 ar9280Modes_original_tx_gain_9280_2);
165 static void ar9271_hw_init_txgain_ini(struct ath_hw *ah, u32 txgain_type)
167 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
168 INIT_INI_ARRAY(&ah->iniModesTxGain,
169 ar9271Modes_high_power_tx_gain_9271);
171 INIT_INI_ARRAY(&ah->iniModesTxGain,
172 ar9271Modes_normal_power_tx_gain_9271);
175 static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah)
177 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
179 if (AR_SREV_9287_11_OR_LATER(ah))
180 INIT_INI_ARRAY(&ah->iniModesRxGain,
181 ar9287Modes_rx_gain_9287_1_1);
182 else if (AR_SREV_9280_20(ah))
183 ar9280_20_hw_init_rxgain_ini(ah);
185 if (AR_SREV_9271(ah)) {
186 ar9271_hw_init_txgain_ini(ah, txgain_type);
187 } else if (AR_SREV_9287_11_OR_LATER(ah)) {
188 INIT_INI_ARRAY(&ah->iniModesTxGain,
189 ar9287Modes_tx_gain_9287_1_1);
190 } else if (AR_SREV_9280_20(ah)) {
191 ar9280_20_hw_init_txgain_ini(ah, txgain_type);
192 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
194 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
195 if (AR_SREV_9285E_20(ah)) {
196 INIT_INI_ARRAY(&ah->iniModesTxGain,
197 ar9285Modes_XE2_0_high_power);
199 INIT_INI_ARRAY(&ah->iniModesTxGain,
200 ar9285Modes_high_power_tx_gain_9285_1_2);
203 if (AR_SREV_9285E_20(ah)) {
204 INIT_INI_ARRAY(&ah->iniModesTxGain,
205 ar9285Modes_XE2_0_normal_power);
207 INIT_INI_ARRAY(&ah->iniModesTxGain,
208 ar9285Modes_original_tx_gain_9285_1_2);
215 * Helper for ASPM support.
217 * Disable PLL when in L0s as well as receiver clock when in L1.
218 * This power saving option must be enabled through the SerDes.
220 * Programming the SerDes must go through the same 288 bit serial shift
221 * register as the other analog registers. Hence the 9 writes.
223 static void ar9002_hw_configpcipowersave(struct ath_hw *ah,
229 /* Nothing to do on restore for 11N */
230 if (!power_off /* !restore */) {
231 if (AR_SREV_9280_20_OR_LATER(ah)) {
233 * AR9280 2.0 or later chips use SerDes values from the
234 * initvals.h initialized depending on chipset during
237 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
238 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
239 INI_RA(&ah->iniPcieSerdes, i, 1));
242 ENABLE_REGWRITE_BUFFER(ah);
244 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
245 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
247 /* RX shut off when elecidle is asserted */
248 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
249 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
250 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
253 * Ignore ah->ah_config.pcie_clock_req setting for
256 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
258 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
259 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
260 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
262 /* Load the new settings */
263 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
265 REGWRITE_BUFFER_FLUSH(ah);
272 /* clear bit 19 to disable L1 */
273 REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
275 val = REG_READ(ah, AR_WA);
278 * Set PCIe workaround bits
279 * In AR9280 and AR9285, bit 14 in WA register (disable L1)
280 * should only be set when device enters D3 and be
281 * cleared when device comes back to D0.
283 if (ah->config.pcie_waen) {
284 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
285 val |= AR_WA_D3_L1_DISABLE;
287 if (((AR_SREV_9285(ah) ||
290 (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
292 (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
293 val |= AR_WA_D3_L1_DISABLE;
297 if (AR_SREV_9280(ah) || AR_SREV_9285(ah) || AR_SREV_9287(ah)) {
299 * Disable bit 6 and 7 before entering D3 to
300 * prevent system hang.
302 val &= ~(AR_WA_BIT6 | AR_WA_BIT7);
305 if (AR_SREV_9280(ah))
308 if (AR_SREV_9285E_20(ah))
311 REG_WRITE(ah, AR_WA, val);
313 if (ah->config.pcie_waen) {
314 val = ah->config.pcie_waen;
316 val &= (~AR_WA_D3_L1_DISABLE);
318 if (AR_SREV_9285(ah) ||
321 val = AR9285_WA_DEFAULT;
323 val &= (~AR_WA_D3_L1_DISABLE);
325 else if (AR_SREV_9280(ah)) {
327 * For AR9280 chips, bit 22 of 0x4004
330 val = AR9280_WA_DEFAULT;
332 val &= (~AR_WA_D3_L1_DISABLE);
338 /* WAR for ASPM system hang */
339 if (AR_SREV_9285(ah) || AR_SREV_9287(ah))
340 val |= (AR_WA_BIT6 | AR_WA_BIT7);
342 if (AR_SREV_9285E_20(ah))
345 REG_WRITE(ah, AR_WA, val);
347 /* set bit 19 to allow forcing of pcie core into L1 state */
348 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
352 static int ar9002_hw_get_radiorev(struct ath_hw *ah)
357 ENABLE_REGWRITE_BUFFER(ah);
359 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
360 for (i = 0; i < 8; i++)
361 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
363 REGWRITE_BUFFER_FLUSH(ah);
365 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
366 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
368 return ath9k_hw_reverse_bits(val, 8);
371 int ar9002_hw_rf_claim(struct ath_hw *ah)
375 REG_WRITE(ah, AR_PHY(0), 0x00000007);
377 val = ar9002_hw_get_radiorev(ah);
378 switch (val & AR_RADIO_SREV_MAJOR) {
380 val = AR_RAD5133_SREV_MAJOR;
382 case AR_RAD5133_SREV_MAJOR:
383 case AR_RAD5122_SREV_MAJOR:
384 case AR_RAD2133_SREV_MAJOR:
385 case AR_RAD2122_SREV_MAJOR:
388 ath_err(ath9k_hw_common(ah),
389 "Radio Chip Rev 0x%02X not supported\n",
390 val & AR_RADIO_SREV_MAJOR);
394 ah->hw_version.analog5GhzRev = val;
399 void ar9002_hw_enable_async_fifo(struct ath_hw *ah)
401 if (AR_SREV_9287_13_OR_LATER(ah)) {
402 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
403 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
404 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
405 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
406 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
407 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
408 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
412 /* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */
413 int ar9002_hw_attach_ops(struct ath_hw *ah)
415 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
416 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
419 ret = ar9002_hw_init_mode_regs(ah);
423 priv_ops->init_mode_gain_regs = ar9002_hw_init_mode_gain_regs;
425 ops->config_pci_powersave = ar9002_hw_configpcipowersave;
427 ret = ar5008_hw_attach_phy_ops(ah);
431 if (AR_SREV_9280_20_OR_LATER(ah))
432 ar9002_hw_attach_phy_ops(ah);
434 ar9002_hw_attach_calib_ops(ah);
435 ar9002_hw_attach_mac_ops(ah);
439 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan)
444 switch (chan->chanmode) {
449 case CHANNEL_A_HT40PLUS:
450 case CHANNEL_A_HT40MINUS:
458 case CHANNEL_G_HT40PLUS:
459 case CHANNEL_G_HT40MINUS:
467 ENABLE_REGWRITE_BUFFER(ah);
469 for (i = 0; i < ah->iniModes_9271_ANI_reg.ia_rows; i++) {
470 u32 reg = INI_RA(&ah->iniModes_9271_ANI_reg, i, 0);
471 u32 val = INI_RA(&ah->iniModes_9271_ANI_reg, i, modesIndex);
474 if (reg == AR_PHY_CCK_DETECT) {
475 val_orig = REG_READ(ah, reg);
476 val &= AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK;
477 val_orig &= ~AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK;
479 REG_WRITE(ah, reg, val|val_orig);
481 REG_WRITE(ah, reg, val);
484 REGWRITE_BUFFER_FLUSH(ah);