2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/ethtool.h>
52 #include <linux/uaccess.h>
54 #include <net/ieee80211_radiotap.h>
56 #include <asm/unaligned.h>
62 static u8 ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
63 static int modparam_nohwcrypt;
64 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
65 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
67 static int modparam_all_channels;
68 module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
69 MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
77 MODULE_AUTHOR("Jiri Slaby");
78 MODULE_AUTHOR("Nick Kossifidis");
79 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
80 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
81 MODULE_LICENSE("Dual BSD/GPL");
82 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
86 static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
87 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
88 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
89 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
90 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
91 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
92 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */
93 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */
94 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
102 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
103 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
104 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
107 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
110 static const struct ath5k_srev_name srev_names[] = {
111 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
112 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
113 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
114 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
115 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
116 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
117 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
118 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
119 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
120 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
121 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
122 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
123 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
124 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
125 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
126 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
127 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
128 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
129 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
130 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
131 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
132 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
133 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
134 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
135 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
136 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
137 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
138 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
139 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
140 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
141 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
142 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
143 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
144 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
145 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
146 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
149 static const struct ieee80211_rate ath5k_rates[] = {
151 .hw_value = ATH5K_RATE_CODE_1M, },
153 .hw_value = ATH5K_RATE_CODE_2M,
154 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
155 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
157 .hw_value = ATH5K_RATE_CODE_5_5M,
158 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
159 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
161 .hw_value = ATH5K_RATE_CODE_11M,
162 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
163 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
165 .hw_value = ATH5K_RATE_CODE_6M,
168 .hw_value = ATH5K_RATE_CODE_9M,
171 .hw_value = ATH5K_RATE_CODE_12M,
174 .hw_value = ATH5K_RATE_CODE_18M,
177 .hw_value = ATH5K_RATE_CODE_24M,
180 .hw_value = ATH5K_RATE_CODE_36M,
183 .hw_value = ATH5K_RATE_CODE_48M,
186 .hw_value = ATH5K_RATE_CODE_54M,
192 * Prototypes - PCI stack related functions
194 static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
195 const struct pci_device_id *id);
196 static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
198 static int ath5k_pci_suspend(struct device *dev);
199 static int ath5k_pci_resume(struct device *dev);
201 SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
202 #define ATH5K_PM_OPS (&ath5k_pm_ops)
204 #define ATH5K_PM_OPS NULL
205 #endif /* CONFIG_PM */
207 static struct pci_driver ath5k_pci_driver = {
208 .name = KBUILD_MODNAME,
209 .id_table = ath5k_pci_id_table,
210 .probe = ath5k_pci_probe,
211 .remove = __devexit_p(ath5k_pci_remove),
212 .driver.pm = ATH5K_PM_OPS,
218 * Prototypes - MAC 802.11 stack related functions
220 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
221 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
222 struct ath5k_txq *txq);
223 static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
224 static int ath5k_reset_wake(struct ath5k_softc *sc);
225 static int ath5k_start(struct ieee80211_hw *hw);
226 static void ath5k_stop(struct ieee80211_hw *hw);
227 static int ath5k_add_interface(struct ieee80211_hw *hw,
228 struct ieee80211_vif *vif);
229 static void ath5k_remove_interface(struct ieee80211_hw *hw,
230 struct ieee80211_vif *vif);
231 static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
232 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
233 int mc_count, struct dev_addr_list *mc_list);
234 static void ath5k_configure_filter(struct ieee80211_hw *hw,
235 unsigned int changed_flags,
236 unsigned int *new_flags,
238 static int ath5k_set_key(struct ieee80211_hw *hw,
239 enum set_key_cmd cmd,
240 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
241 struct ieee80211_key_conf *key);
242 static int ath5k_get_stats(struct ieee80211_hw *hw,
243 struct ieee80211_low_level_stats *stats);
244 static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
245 struct ieee80211_tx_queue_stats *stats);
246 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
247 static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
248 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
249 static int ath5k_beacon_update(struct ieee80211_hw *hw,
250 struct ieee80211_vif *vif);
251 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
252 struct ieee80211_vif *vif,
253 struct ieee80211_bss_conf *bss_conf,
255 static void ath5k_sw_scan_start(struct ieee80211_hw *hw);
256 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw);
257 static void ath5k_set_coverage_class(struct ieee80211_hw *hw,
260 static const struct ieee80211_ops ath5k_hw_ops = {
262 .start = ath5k_start,
264 .add_interface = ath5k_add_interface,
265 .remove_interface = ath5k_remove_interface,
266 .config = ath5k_config,
267 .prepare_multicast = ath5k_prepare_multicast,
268 .configure_filter = ath5k_configure_filter,
269 .set_key = ath5k_set_key,
270 .get_stats = ath5k_get_stats,
272 .get_tx_stats = ath5k_get_tx_stats,
273 .get_tsf = ath5k_get_tsf,
274 .set_tsf = ath5k_set_tsf,
275 .reset_tsf = ath5k_reset_tsf,
276 .bss_info_changed = ath5k_bss_info_changed,
277 .sw_scan_start = ath5k_sw_scan_start,
278 .sw_scan_complete = ath5k_sw_scan_complete,
279 .set_coverage_class = ath5k_set_coverage_class,
283 * Prototypes - Internal functions
286 static int ath5k_attach(struct pci_dev *pdev,
287 struct ieee80211_hw *hw);
288 static void ath5k_detach(struct pci_dev *pdev,
289 struct ieee80211_hw *hw);
290 /* Channel/mode setup */
291 static inline short ath5k_ieee2mhz(short chan);
292 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
293 struct ieee80211_channel *channels,
296 static int ath5k_setup_bands(struct ieee80211_hw *hw);
297 static int ath5k_chan_set(struct ath5k_softc *sc,
298 struct ieee80211_channel *chan);
299 static void ath5k_setcurmode(struct ath5k_softc *sc,
301 static void ath5k_mode_setup(struct ath5k_softc *sc);
303 /* Descriptor setup */
304 static int ath5k_desc_alloc(struct ath5k_softc *sc,
305 struct pci_dev *pdev);
306 static void ath5k_desc_free(struct ath5k_softc *sc,
307 struct pci_dev *pdev);
309 static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
310 struct ath5k_buf *bf);
311 static int ath5k_txbuf_setup(struct ath5k_softc *sc,
312 struct ath5k_buf *bf,
313 struct ath5k_txq *txq);
314 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
315 struct ath5k_buf *bf)
320 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
322 dev_kfree_skb_any(bf->skb);
326 static inline void ath5k_rxbuf_free(struct ath5k_softc *sc,
327 struct ath5k_buf *bf)
329 struct ath5k_hw *ah = sc->ah;
330 struct ath_common *common = ath5k_hw_common(ah);
335 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
337 dev_kfree_skb_any(bf->skb);
343 static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
344 int qtype, int subtype);
345 static int ath5k_beaconq_setup(struct ath5k_hw *ah);
346 static int ath5k_beaconq_config(struct ath5k_softc *sc);
347 static void ath5k_txq_drainq(struct ath5k_softc *sc,
348 struct ath5k_txq *txq);
349 static void ath5k_txq_cleanup(struct ath5k_softc *sc);
350 static void ath5k_txq_release(struct ath5k_softc *sc);
352 static int ath5k_rx_start(struct ath5k_softc *sc);
353 static void ath5k_rx_stop(struct ath5k_softc *sc);
354 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
355 struct ath5k_desc *ds,
357 struct ath5k_rx_status *rs);
358 static void ath5k_tasklet_rx(unsigned long data);
360 static void ath5k_tx_processq(struct ath5k_softc *sc,
361 struct ath5k_txq *txq);
362 static void ath5k_tasklet_tx(unsigned long data);
363 /* Beacon handling */
364 static int ath5k_beacon_setup(struct ath5k_softc *sc,
365 struct ath5k_buf *bf);
366 static void ath5k_beacon_send(struct ath5k_softc *sc);
367 static void ath5k_beacon_config(struct ath5k_softc *sc);
368 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
369 static void ath5k_tasklet_beacon(unsigned long data);
371 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
373 u64 tsf = ath5k_hw_get_tsf64(ah);
375 if ((tsf & 0x7fff) < rstamp)
378 return (tsf & ~0x7fff) | rstamp;
381 /* Interrupt handling */
382 static int ath5k_init(struct ath5k_softc *sc);
383 static int ath5k_stop_locked(struct ath5k_softc *sc);
384 static int ath5k_stop_hw(struct ath5k_softc *sc);
385 static irqreturn_t ath5k_intr(int irq, void *dev_id);
386 static void ath5k_tasklet_reset(unsigned long data);
388 static void ath5k_tasklet_calibrate(unsigned long data);
391 * Module init/exit functions
400 ret = pci_register_driver(&ath5k_pci_driver);
402 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
412 pci_unregister_driver(&ath5k_pci_driver);
414 ath5k_debug_finish();
417 module_init(init_ath5k_pci);
418 module_exit(exit_ath5k_pci);
421 /********************\
422 * PCI Initialization *
423 \********************/
426 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
428 const char *name = "xxxxx";
431 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
432 if (srev_names[i].sr_type != type)
435 if ((val & 0xf0) == srev_names[i].sr_val)
436 name = srev_names[i].sr_name;
438 if ((val & 0xff) == srev_names[i].sr_val) {
439 name = srev_names[i].sr_name;
446 static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
448 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
449 return ath5k_hw_reg_read(ah, reg_offset);
452 static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
454 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
455 ath5k_hw_reg_write(ah, val, reg_offset);
458 static const struct ath_ops ath5k_common_ops = {
459 .read = ath5k_ioread32,
460 .write = ath5k_iowrite32,
464 ath5k_pci_probe(struct pci_dev *pdev,
465 const struct pci_device_id *id)
468 struct ath5k_softc *sc;
469 struct ath_common *common;
470 struct ieee80211_hw *hw;
474 ret = pci_enable_device(pdev);
476 dev_err(&pdev->dev, "can't enable device\n");
480 /* XXX 32-bit addressing only */
481 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
483 dev_err(&pdev->dev, "32-bit DMA not available\n");
488 * Cache line size is used to size and align various
489 * structures used to communicate with the hardware.
491 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
494 * Linux 2.4.18 (at least) writes the cache line size
495 * register as a 16-bit wide register which is wrong.
496 * We must have this setup properly for rx buffer
497 * DMA to work so force a reasonable value here if it
500 csz = L1_CACHE_BYTES >> 2;
501 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
504 * The default setting of latency timer yields poor results,
505 * set it to the value used by other systems. It may be worth
506 * tweaking this setting more.
508 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
510 /* Enable bus mastering */
511 pci_set_master(pdev);
514 * Disable the RETRY_TIMEOUT register (0x41) to keep
515 * PCI Tx retries from interfering with C3 CPU state.
517 pci_write_config_byte(pdev, 0x41, 0);
519 ret = pci_request_region(pdev, 0, "ath5k");
521 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
525 mem = pci_iomap(pdev, 0, 0);
527 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
533 * Allocate hw (mac80211 main struct)
534 * and hw->priv (driver private data)
536 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
538 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
543 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
545 /* Initialize driver private data */
546 SET_IEEE80211_DEV(hw, &pdev->dev);
547 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
548 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
549 IEEE80211_HW_SIGNAL_DBM |
550 IEEE80211_HW_NOISE_DBM;
552 hw->wiphy->interface_modes =
553 BIT(NL80211_IFTYPE_AP) |
554 BIT(NL80211_IFTYPE_STATION) |
555 BIT(NL80211_IFTYPE_ADHOC) |
556 BIT(NL80211_IFTYPE_MESH_POINT);
558 hw->extra_tx_headroom = 2;
559 hw->channel_change_time = 5000;
564 ath5k_debug_init_device(sc);
567 * Mark the device as detached to avoid processing
568 * interrupts until setup is complete.
570 __set_bit(ATH_STAT_INVALID, sc->status);
572 sc->iobase = mem; /* So we can unmap it on detach */
573 sc->opmode = NL80211_IFTYPE_STATION;
575 mutex_init(&sc->lock);
576 spin_lock_init(&sc->rxbuflock);
577 spin_lock_init(&sc->txbuflock);
578 spin_lock_init(&sc->block);
580 /* Set private data */
581 pci_set_drvdata(pdev, hw);
583 /* Setup interrupt handler */
584 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
586 ATH5K_ERR(sc, "request_irq failed\n");
590 /*If we passed the test malloc a ath5k_hw struct*/
591 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
594 ATH5K_ERR(sc, "out of memory\n");
599 sc->ah->ah_iobase = sc->iobase;
600 common = ath5k_hw_common(sc->ah);
601 common->ops = &ath5k_common_ops;
604 common->cachelsz = csz << 2; /* convert to bytes */
606 /* Initialize device */
607 ret = ath5k_hw_attach(sc);
612 /* set up multi-rate retry capabilities */
613 if (sc->ah->ah_version == AR5K_AR5212) {
615 hw->max_rate_tries = 11;
618 /* Finish private driver data initialization */
619 ret = ath5k_attach(pdev, hw);
623 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
624 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
626 sc->ah->ah_phy_revision);
628 if (!sc->ah->ah_single_chip) {
629 /* Single chip radio (!RF5111) */
630 if (sc->ah->ah_radio_5ghz_revision &&
631 !sc->ah->ah_radio_2ghz_revision) {
632 /* No 5GHz support -> report 2GHz radio */
633 if (!test_bit(AR5K_MODE_11A,
634 sc->ah->ah_capabilities.cap_mode)) {
635 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
636 ath5k_chip_name(AR5K_VERSION_RAD,
637 sc->ah->ah_radio_5ghz_revision),
638 sc->ah->ah_radio_5ghz_revision);
639 /* No 2GHz support (5110 and some
640 * 5Ghz only cards) -> report 5Ghz radio */
641 } else if (!test_bit(AR5K_MODE_11B,
642 sc->ah->ah_capabilities.cap_mode)) {
643 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
644 ath5k_chip_name(AR5K_VERSION_RAD,
645 sc->ah->ah_radio_5ghz_revision),
646 sc->ah->ah_radio_5ghz_revision);
647 /* Multiband radio */
649 ATH5K_INFO(sc, "RF%s multiband radio found"
651 ath5k_chip_name(AR5K_VERSION_RAD,
652 sc->ah->ah_radio_5ghz_revision),
653 sc->ah->ah_radio_5ghz_revision);
656 /* Multi chip radio (RF5111 - RF2111) ->
657 * report both 2GHz/5GHz radios */
658 else if (sc->ah->ah_radio_5ghz_revision &&
659 sc->ah->ah_radio_2ghz_revision){
660 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
661 ath5k_chip_name(AR5K_VERSION_RAD,
662 sc->ah->ah_radio_5ghz_revision),
663 sc->ah->ah_radio_5ghz_revision);
664 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
665 ath5k_chip_name(AR5K_VERSION_RAD,
666 sc->ah->ah_radio_2ghz_revision),
667 sc->ah->ah_radio_2ghz_revision);
672 /* ready to process interrupts */
673 __clear_bit(ATH_STAT_INVALID, sc->status);
677 ath5k_hw_detach(sc->ah);
679 free_irq(pdev->irq, sc);
683 ieee80211_free_hw(hw);
685 pci_iounmap(pdev, mem);
687 pci_release_region(pdev, 0);
689 pci_disable_device(pdev);
694 static void __devexit
695 ath5k_pci_remove(struct pci_dev *pdev)
697 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
698 struct ath5k_softc *sc = hw->priv;
700 ath5k_debug_finish_device(sc);
701 ath5k_detach(pdev, hw);
702 ath5k_hw_detach(sc->ah);
704 free_irq(pdev->irq, sc);
705 pci_iounmap(pdev, sc->iobase);
706 pci_release_region(pdev, 0);
707 pci_disable_device(pdev);
708 ieee80211_free_hw(hw);
712 static int ath5k_pci_suspend(struct device *dev)
714 struct ieee80211_hw *hw = pci_get_drvdata(to_pci_dev(dev));
715 struct ath5k_softc *sc = hw->priv;
721 static int ath5k_pci_resume(struct device *dev)
723 struct pci_dev *pdev = to_pci_dev(dev);
724 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
725 struct ath5k_softc *sc = hw->priv;
728 * Suspend/Resume resets the PCI configuration space, so we have to
729 * re-disable the RETRY_TIMEOUT register (0x41) to keep
730 * PCI Tx retries from interfering with C3 CPU state
732 pci_write_config_byte(pdev, 0x41, 0);
734 ath5k_led_enable(sc);
737 #endif /* CONFIG_PM */
740 /***********************\
741 * Driver Initialization *
742 \***********************/
744 static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
746 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
747 struct ath5k_softc *sc = hw->priv;
748 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
750 return ath_reg_notifier_apply(wiphy, request, regulatory);
754 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
756 struct ath5k_softc *sc = hw->priv;
757 struct ath5k_hw *ah = sc->ah;
758 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
759 u8 mac[ETH_ALEN] = {};
762 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
765 * Check if the MAC has multi-rate retry support.
766 * We do this by trying to setup a fake extended
767 * descriptor. MAC's that don't have support will
768 * return false w/o doing anything. MAC's that do
769 * support it will return true w/o doing anything.
771 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
775 __set_bit(ATH_STAT_MRRETRY, sc->status);
778 * Collect the channel list. The 802.11 layer
779 * is resposible for filtering this list based
780 * on settings like the phy mode and regulatory
781 * domain restrictions.
783 ret = ath5k_setup_bands(hw);
785 ATH5K_ERR(sc, "can't get channels\n");
789 /* NB: setup here so ath5k_rate_update is happy */
790 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
791 ath5k_setcurmode(sc, AR5K_MODE_11A);
793 ath5k_setcurmode(sc, AR5K_MODE_11B);
796 * Allocate tx+rx descriptors and populate the lists.
798 ret = ath5k_desc_alloc(sc, pdev);
800 ATH5K_ERR(sc, "can't allocate descriptors\n");
805 * Allocate hardware transmit queues: one queue for
806 * beacon frames and one data queue for each QoS
807 * priority. Note that hw functions handle reseting
808 * these queues at the needed time.
810 ret = ath5k_beaconq_setup(ah);
812 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
816 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
817 if (IS_ERR(sc->cabq)) {
818 ATH5K_ERR(sc, "can't setup cab queue\n");
819 ret = PTR_ERR(sc->cabq);
823 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
824 if (IS_ERR(sc->txq)) {
825 ATH5K_ERR(sc, "can't setup xmit queue\n");
826 ret = PTR_ERR(sc->txq);
830 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
831 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
832 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
833 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
834 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
836 ret = ath5k_eeprom_read_mac(ah, mac);
838 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
843 SET_IEEE80211_PERM_ADDR(hw, mac);
844 /* All MAC address bits matter for ACKs */
845 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
846 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
848 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
849 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
851 ATH5K_ERR(sc, "can't initialize regulatory system\n");
855 ret = ieee80211_register_hw(hw);
857 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
861 if (!ath_is_world_regd(regulatory))
862 regulatory_hint(hw->wiphy, regulatory->alpha2);
868 ath5k_txq_release(sc);
870 ath5k_hw_release_tx_queue(ah, sc->bhalq);
872 ath5k_desc_free(sc, pdev);
878 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
880 struct ath5k_softc *sc = hw->priv;
883 * NB: the order of these is important:
884 * o call the 802.11 layer before detaching ath5k_hw to
885 * insure callbacks into the driver to delete global
886 * key cache entries can be handled
887 * o reclaim the tx queue data structures after calling
888 * the 802.11 layer as we'll get called back to reclaim
889 * node state and potentially want to use them
890 * o to cleanup the tx queues the hal is called, so detach
892 * XXX: ??? detach ath5k_hw ???
893 * Other than that, it's straightforward...
895 ieee80211_unregister_hw(hw);
896 ath5k_desc_free(sc, pdev);
897 ath5k_txq_release(sc);
898 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
899 ath5k_unregister_leds(sc);
902 * NB: can't reclaim these until after ieee80211_ifdetach
903 * returns because we'll get called back to reclaim node
904 * state and potentially want to use them.
911 /********************\
912 * Channel/mode setup *
913 \********************/
916 * Convert IEEE channel number to MHz frequency.
919 ath5k_ieee2mhz(short chan)
921 if (chan <= 14 || chan >= 27)
922 return ieee80211chan2mhz(chan);
924 return 2212 + chan * 20;
928 * Returns true for the channel numbers used without all_channels modparam.
930 static bool ath5k_is_standard_channel(short chan)
932 return ((chan <= 14) ||
934 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
936 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
938 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
942 ath5k_copy_channels(struct ath5k_hw *ah,
943 struct ieee80211_channel *channels,
947 unsigned int i, count, size, chfreq, freq, ch;
949 if (!test_bit(mode, ah->ah_modes))
954 case AR5K_MODE_11A_TURBO:
955 /* 1..220, but 2GHz frequencies are filtered by check_channel */
957 chfreq = CHANNEL_5GHZ;
961 case AR5K_MODE_11G_TURBO:
963 chfreq = CHANNEL_2GHZ;
966 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
970 for (i = 0, count = 0; i < size && max > 0; i++) {
972 freq = ath5k_ieee2mhz(ch);
974 /* Check if channel is supported by the chipset */
975 if (!ath5k_channel_ok(ah, freq, chfreq))
978 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
981 /* Write channel info and increment counter */
982 channels[count].center_freq = freq;
983 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
984 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
988 channels[count].hw_value = chfreq | CHANNEL_OFDM;
990 case AR5K_MODE_11A_TURBO:
991 case AR5K_MODE_11G_TURBO:
992 channels[count].hw_value = chfreq |
993 CHANNEL_OFDM | CHANNEL_TURBO;
996 channels[count].hw_value = CHANNEL_B;
1007 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
1011 for (i = 0; i < AR5K_MAX_RATES; i++)
1012 sc->rate_idx[b->band][i] = -1;
1014 for (i = 0; i < b->n_bitrates; i++) {
1015 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
1016 if (b->bitrates[i].hw_value_short)
1017 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
1022 ath5k_setup_bands(struct ieee80211_hw *hw)
1024 struct ath5k_softc *sc = hw->priv;
1025 struct ath5k_hw *ah = sc->ah;
1026 struct ieee80211_supported_band *sband;
1027 int max_c, count_c = 0;
1030 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
1031 max_c = ARRAY_SIZE(sc->channels);
1034 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
1035 sband->band = IEEE80211_BAND_2GHZ;
1036 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
1038 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
1040 memcpy(sband->bitrates, &ath5k_rates[0],
1041 sizeof(struct ieee80211_rate) * 12);
1042 sband->n_bitrates = 12;
1044 sband->channels = sc->channels;
1045 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1046 AR5K_MODE_11G, max_c);
1048 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1049 count_c = sband->n_channels;
1051 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
1053 memcpy(sband->bitrates, &ath5k_rates[0],
1054 sizeof(struct ieee80211_rate) * 4);
1055 sband->n_bitrates = 4;
1057 /* 5211 only supports B rates and uses 4bit rate codes
1058 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
1061 if (ah->ah_version == AR5K_AR5211) {
1062 for (i = 0; i < 4; i++) {
1063 sband->bitrates[i].hw_value =
1064 sband->bitrates[i].hw_value & 0xF;
1065 sband->bitrates[i].hw_value_short =
1066 sband->bitrates[i].hw_value_short & 0xF;
1070 sband->channels = sc->channels;
1071 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1072 AR5K_MODE_11B, max_c);
1074 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1075 count_c = sband->n_channels;
1078 ath5k_setup_rate_idx(sc, sband);
1080 /* 5GHz band, A mode */
1081 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
1082 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1083 sband->band = IEEE80211_BAND_5GHZ;
1084 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
1086 memcpy(sband->bitrates, &ath5k_rates[4],
1087 sizeof(struct ieee80211_rate) * 8);
1088 sband->n_bitrates = 8;
1090 sband->channels = &sc->channels[count_c];
1091 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1092 AR5K_MODE_11A, max_c);
1094 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1096 ath5k_setup_rate_idx(sc, sband);
1098 ath5k_debug_dump_bands(sc);
1104 * Set/change channels. We always reset the chip.
1105 * To accomplish this we must first cleanup any pending DMA,
1106 * then restart stuff after a la ath5k_init.
1108 * Called with sc->lock.
1111 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1113 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1114 sc->curchan->center_freq, chan->center_freq);
1117 * To switch channels clear any pending DMA operations;
1118 * wait long enough for the RX fifo to drain, reset the
1119 * hardware at the new frequency, and then re-enable
1120 * the relevant bits of the h/w.
1122 return ath5k_reset(sc, chan);
1126 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1130 if (mode == AR5K_MODE_11A) {
1131 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1133 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1138 ath5k_mode_setup(struct ath5k_softc *sc)
1140 struct ath5k_hw *ah = sc->ah;
1143 ah->ah_op_mode = sc->opmode;
1145 /* configure rx filter */
1146 rfilt = sc->filter_flags;
1147 ath5k_hw_set_rx_filter(ah, rfilt);
1149 if (ath5k_hw_hasbssidmask(ah))
1150 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1152 /* configure operational mode */
1153 ath5k_hw_set_opmode(ah);
1155 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1159 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1163 /* return base rate on errors */
1164 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
1165 "hw_rix out of bounds: %x\n", hw_rix))
1168 rix = sc->rate_idx[sc->curband->band][hw_rix];
1169 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
1180 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1182 struct ath_common *common = ath5k_hw_common(sc->ah);
1183 struct sk_buff *skb;
1186 * Allocate buffer with headroom_needed space for the
1187 * fake physical layer header at the start.
1189 skb = ath_rxbuf_alloc(common,
1194 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1195 common->rx_bufsize);
1199 *skb_addr = pci_map_single(sc->pdev,
1200 skb->data, common->rx_bufsize,
1201 PCI_DMA_FROMDEVICE);
1202 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1203 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1211 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1213 struct ath5k_hw *ah = sc->ah;
1214 struct sk_buff *skb = bf->skb;
1215 struct ath5k_desc *ds;
1218 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1225 * Setup descriptors. For receive we always terminate
1226 * the descriptor list with a self-linked entry so we'll
1227 * not get overrun under high load (as can happen with a
1228 * 5212 when ANI processing enables PHY error frames).
1230 * To insure the last descriptor is self-linked we create
1231 * each descriptor as self-linked and add it to the end. As
1232 * each additional descriptor is added the previous self-linked
1233 * entry is ``fixed'' naturally. This should be safe even
1234 * if DMA is happening. When processing RX interrupts we
1235 * never remove/process the last, self-linked, entry on the
1236 * descriptor list. This insures the hardware always has
1237 * someplace to write a new frame.
1240 ds->ds_link = bf->daddr; /* link to self */
1241 ds->ds_data = bf->skbaddr;
1242 ah->ah_setup_rx_desc(ah, ds,
1243 skb_tailroom(skb), /* buffer size */
1246 if (sc->rxlink != NULL)
1247 *sc->rxlink = bf->daddr;
1248 sc->rxlink = &ds->ds_link;
1253 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1254 struct ath5k_txq *txq)
1256 struct ath5k_hw *ah = sc->ah;
1257 struct ath5k_desc *ds = bf->desc;
1258 struct sk_buff *skb = bf->skb;
1259 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1260 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1261 struct ieee80211_rate *rate;
1262 unsigned int mrr_rate[3], mrr_tries[3];
1269 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1271 /* XXX endianness */
1272 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1275 rate = ieee80211_get_tx_rate(sc->hw, info);
1277 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
1278 flags |= AR5K_TXDESC_NOACK;
1280 rc_flags = info->control.rates[0].flags;
1281 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1282 rate->hw_value_short : rate->hw_value;
1286 /* FIXME: If we are in g mode and rate is a CCK rate
1287 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1288 * from tx power (value is in dB units already) */
1289 if (info->control.hw_key) {
1290 keyidx = info->control.hw_key->hw_key_idx;
1291 pktlen += info->control.hw_key->icv_len;
1293 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1294 flags |= AR5K_TXDESC_RTSENA;
1295 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1296 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1297 sc->vif, pktlen, info));
1299 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1300 flags |= AR5K_TXDESC_CTSENA;
1301 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1302 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1303 sc->vif, pktlen, info));
1305 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1306 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1307 (sc->power_level * 2),
1309 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
1310 cts_rate, duration);
1314 memset(mrr_rate, 0, sizeof(mrr_rate));
1315 memset(mrr_tries, 0, sizeof(mrr_tries));
1316 for (i = 0; i < 3; i++) {
1317 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1321 mrr_rate[i] = rate->hw_value;
1322 mrr_tries[i] = info->control.rates[i + 1].count;
1325 ah->ah_setup_mrr_tx_desc(ah, ds,
1326 mrr_rate[0], mrr_tries[0],
1327 mrr_rate[1], mrr_tries[1],
1328 mrr_rate[2], mrr_tries[2]);
1331 ds->ds_data = bf->skbaddr;
1333 spin_lock_bh(&txq->lock);
1334 list_add_tail(&bf->list, &txq->q);
1335 sc->tx_stats[txq->qnum].len++;
1336 if (txq->link == NULL) /* is this first packet? */
1337 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
1338 else /* no, so only link it */
1339 *txq->link = bf->daddr;
1341 txq->link = &ds->ds_link;
1342 ath5k_hw_start_tx_dma(ah, txq->qnum);
1344 spin_unlock_bh(&txq->lock);
1348 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1352 /*******************\
1353 * Descriptors setup *
1354 \*******************/
1357 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1359 struct ath5k_desc *ds;
1360 struct ath5k_buf *bf;
1365 /* allocate descriptors */
1366 sc->desc_len = sizeof(struct ath5k_desc) *
1367 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1368 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1369 if (sc->desc == NULL) {
1370 ATH5K_ERR(sc, "can't allocate descriptors\n");
1375 da = sc->desc_daddr;
1376 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1377 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1379 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1380 sizeof(struct ath5k_buf), GFP_KERNEL);
1382 ATH5K_ERR(sc, "can't allocate bufptr\n");
1388 INIT_LIST_HEAD(&sc->rxbuf);
1389 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1392 list_add_tail(&bf->list, &sc->rxbuf);
1395 INIT_LIST_HEAD(&sc->txbuf);
1396 sc->txbuf_len = ATH_TXBUF;
1397 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1398 da += sizeof(*ds)) {
1401 list_add_tail(&bf->list, &sc->txbuf);
1411 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1418 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1420 struct ath5k_buf *bf;
1422 ath5k_txbuf_free(sc, sc->bbuf);
1423 list_for_each_entry(bf, &sc->txbuf, list)
1424 ath5k_txbuf_free(sc, bf);
1425 list_for_each_entry(bf, &sc->rxbuf, list)
1426 ath5k_rxbuf_free(sc, bf);
1428 /* Free memory associated with all descriptors */
1429 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1443 static struct ath5k_txq *
1444 ath5k_txq_setup(struct ath5k_softc *sc,
1445 int qtype, int subtype)
1447 struct ath5k_hw *ah = sc->ah;
1448 struct ath5k_txq *txq;
1449 struct ath5k_txq_info qi = {
1450 .tqi_subtype = subtype,
1451 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1452 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1453 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1458 * Enable interrupts only for EOL and DESC conditions.
1459 * We mark tx descriptors to receive a DESC interrupt
1460 * when a tx queue gets deep; otherwise waiting for the
1461 * EOL to reap descriptors. Note that this is done to
1462 * reduce interrupt load and this only defers reaping
1463 * descriptors, never transmitting frames. Aside from
1464 * reducing interrupts this also permits more concurrency.
1465 * The only potential downside is if the tx queue backs
1466 * up in which case the top half of the kernel may backup
1467 * due to a lack of tx descriptors.
1469 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1470 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1471 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1474 * NB: don't print a message, this happens
1475 * normally on parts with too few tx queues
1477 return ERR_PTR(qnum);
1479 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1480 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1481 qnum, ARRAY_SIZE(sc->txqs));
1482 ath5k_hw_release_tx_queue(ah, qnum);
1483 return ERR_PTR(-EINVAL);
1485 txq = &sc->txqs[qnum];
1489 INIT_LIST_HEAD(&txq->q);
1490 spin_lock_init(&txq->lock);
1493 return &sc->txqs[qnum];
1497 ath5k_beaconq_setup(struct ath5k_hw *ah)
1499 struct ath5k_txq_info qi = {
1500 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1501 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1502 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1503 /* NB: for dynamic turbo, don't enable any other interrupts */
1504 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1507 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1511 ath5k_beaconq_config(struct ath5k_softc *sc)
1513 struct ath5k_hw *ah = sc->ah;
1514 struct ath5k_txq_info qi;
1517 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1520 if (sc->opmode == NL80211_IFTYPE_AP ||
1521 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1523 * Always burst out beacon and CAB traffic
1524 * (aifs = cwmin = cwmax = 0)
1529 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1531 * Adhoc mode; backoff between 0 and (2 * cw_min).
1535 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1538 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1539 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1540 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1542 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1544 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1545 "hardware queue!\n", __func__);
1549 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1553 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1555 struct ath5k_buf *bf, *bf0;
1558 * NB: this assumes output has been stopped and
1559 * we do not need to block ath5k_tx_tasklet
1561 spin_lock_bh(&txq->lock);
1562 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1563 ath5k_debug_printtxbuf(sc, bf);
1565 ath5k_txbuf_free(sc, bf);
1567 spin_lock_bh(&sc->txbuflock);
1568 sc->tx_stats[txq->qnum].len--;
1569 list_move_tail(&bf->list, &sc->txbuf);
1571 spin_unlock_bh(&sc->txbuflock);
1574 spin_unlock_bh(&txq->lock);
1578 * Drain the transmit queues and reclaim resources.
1581 ath5k_txq_cleanup(struct ath5k_softc *sc)
1583 struct ath5k_hw *ah = sc->ah;
1586 /* XXX return value */
1587 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1588 /* don't touch the hardware if marked invalid */
1589 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1590 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1591 ath5k_hw_get_txdp(ah, sc->bhalq));
1592 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1593 if (sc->txqs[i].setup) {
1594 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1595 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1598 ath5k_hw_get_txdp(ah,
1603 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
1605 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1606 if (sc->txqs[i].setup)
1607 ath5k_txq_drainq(sc, &sc->txqs[i]);
1611 ath5k_txq_release(struct ath5k_softc *sc)
1613 struct ath5k_txq *txq = sc->txqs;
1616 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1618 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1631 * Enable the receive h/w following a reset.
1634 ath5k_rx_start(struct ath5k_softc *sc)
1636 struct ath5k_hw *ah = sc->ah;
1637 struct ath_common *common = ath5k_hw_common(ah);
1638 struct ath5k_buf *bf;
1641 common->rx_bufsize = roundup(IEEE80211_MAX_LEN, common->cachelsz);
1643 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1644 common->cachelsz, common->rx_bufsize);
1646 spin_lock_bh(&sc->rxbuflock);
1648 list_for_each_entry(bf, &sc->rxbuf, list) {
1649 ret = ath5k_rxbuf_setup(sc, bf);
1651 spin_unlock_bh(&sc->rxbuflock);
1655 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1656 ath5k_hw_set_rxdp(ah, bf->daddr);
1657 spin_unlock_bh(&sc->rxbuflock);
1659 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1660 ath5k_mode_setup(sc); /* set filters, etc. */
1661 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1669 * Disable the receive h/w in preparation for a reset.
1672 ath5k_rx_stop(struct ath5k_softc *sc)
1674 struct ath5k_hw *ah = sc->ah;
1676 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1677 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1678 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1680 ath5k_debug_printrxbuffs(sc, ah);
1682 sc->rxlink = NULL; /* just in case */
1686 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1687 struct sk_buff *skb, struct ath5k_rx_status *rs)
1689 struct ath5k_hw *ah = sc->ah;
1690 struct ath_common *common = ath5k_hw_common(ah);
1691 struct ieee80211_hdr *hdr = (void *)skb->data;
1692 unsigned int keyix, hlen;
1694 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1695 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1696 return RX_FLAG_DECRYPTED;
1698 /* Apparently when a default key is used to decrypt the packet
1699 the hw does not set the index used to decrypt. In such cases
1700 get the index from the packet. */
1701 hlen = ieee80211_hdrlen(hdr->frame_control);
1702 if (ieee80211_has_protected(hdr->frame_control) &&
1703 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1704 skb->len >= hlen + 4) {
1705 keyix = skb->data[hlen + 3] >> 6;
1707 if (test_bit(keyix, common->keymap))
1708 return RX_FLAG_DECRYPTED;
1716 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1717 struct ieee80211_rx_status *rxs)
1719 struct ath_common *common = ath5k_hw_common(sc->ah);
1722 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1724 if (ieee80211_is_beacon(mgmt->frame_control) &&
1725 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1726 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
1728 * Received an IBSS beacon with the same BSSID. Hardware *must*
1729 * have updated the local TSF. We have to work around various
1730 * hardware bugs, though...
1732 tsf = ath5k_hw_get_tsf64(sc->ah);
1733 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1734 hw_tu = TSF_TO_TU(tsf);
1736 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1737 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1738 (unsigned long long)bc_tstamp,
1739 (unsigned long long)rxs->mactime,
1740 (unsigned long long)(rxs->mactime - bc_tstamp),
1741 (unsigned long long)tsf);
1744 * Sometimes the HW will give us a wrong tstamp in the rx
1745 * status, causing the timestamp extension to go wrong.
1746 * (This seems to happen especially with beacon frames bigger
1747 * than 78 byte (incl. FCS))
1748 * But we know that the receive timestamp must be later than the
1749 * timestamp of the beacon since HW must have synced to that.
1751 * NOTE: here we assume mactime to be after the frame was
1752 * received, not like mac80211 which defines it at the start.
1754 if (bc_tstamp > rxs->mactime) {
1755 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1756 "fixing mactime from %llx to %llx\n",
1757 (unsigned long long)rxs->mactime,
1758 (unsigned long long)tsf);
1763 * Local TSF might have moved higher than our beacon timers,
1764 * in that case we have to update them to continue sending
1765 * beacons. This also takes care of synchronizing beacon sending
1766 * times with other stations.
1768 if (hw_tu >= sc->nexttbtt)
1769 ath5k_beacon_update_timers(sc, bc_tstamp);
1774 ath5k_tasklet_rx(unsigned long data)
1776 struct ieee80211_rx_status *rxs;
1777 struct ath5k_rx_status rs = {};
1778 struct sk_buff *skb, *next_skb;
1779 dma_addr_t next_skb_addr;
1780 struct ath5k_softc *sc = (void *)data;
1781 struct ath5k_hw *ah = sc->ah;
1782 struct ath_common *common = ath5k_hw_common(ah);
1783 struct ath5k_buf *bf;
1784 struct ath5k_desc *ds;
1790 spin_lock(&sc->rxbuflock);
1791 if (list_empty(&sc->rxbuf)) {
1792 ATH5K_WARN(sc, "empty rx buf pool\n");
1798 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1799 BUG_ON(bf->skb == NULL);
1803 /* bail if HW is still using self-linked descriptor */
1804 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1807 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1808 if (unlikely(ret == -EINPROGRESS))
1810 else if (unlikely(ret)) {
1811 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1812 spin_unlock(&sc->rxbuflock);
1816 if (unlikely(rs.rs_more)) {
1817 ATH5K_WARN(sc, "unsupported jumbo\n");
1821 if (unlikely(rs.rs_status)) {
1822 if (rs.rs_status & AR5K_RXERR_PHY)
1824 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
1826 * Decrypt error. If the error occurred
1827 * because there was no hardware key, then
1828 * let the frame through so the upper layers
1829 * can process it. This is necessary for 5210
1830 * parts which have no way to setup a ``clear''
1833 * XXX do key cache faulting
1835 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1836 !(rs.rs_status & AR5K_RXERR_CRC))
1839 if (rs.rs_status & AR5K_RXERR_MIC) {
1840 rx_flag |= RX_FLAG_MMIC_ERROR;
1844 /* let crypto-error packets fall through in MNTR */
1846 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1847 sc->opmode != NL80211_IFTYPE_MONITOR)
1851 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1854 * If we can't replace bf->skb with a new skb under memory
1855 * pressure, just skip this packet
1860 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
1861 PCI_DMA_FROMDEVICE);
1862 skb_put(skb, rs.rs_datalen);
1864 /* The MAC header is padded to have 32-bit boundary if the
1865 * packet payload is non-zero. The general calculation for
1866 * padsize would take into account odd header lengths:
1867 * padsize = (4 - hdrlen % 4) % 4; However, since only
1868 * even-length headers are used, padding can only be 0 or 2
1869 * bytes and we can optimize this a bit. In addition, we must
1870 * not try to remove padding from short control frames that do
1871 * not have payload. */
1872 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1873 padsize = ath5k_pad_size(hdrlen);
1875 memmove(skb->data + padsize, skb->data, hdrlen);
1876 skb_pull(skb, padsize);
1878 rxs = IEEE80211_SKB_RXCB(skb);
1881 * always extend the mac timestamp, since this information is
1882 * also needed for proper IBSS merging.
1884 * XXX: it might be too late to do it here, since rs_tstamp is
1885 * 15bit only. that means TSF extension has to be done within
1886 * 32768usec (about 32ms). it might be necessary to move this to
1887 * the interrupt handler, like it is done in madwifi.
1889 * Unfortunately we don't know when the hardware takes the rx
1890 * timestamp (beginning of phy frame, data frame, end of rx?).
1891 * The only thing we know is that it is hardware specific...
1892 * On AR5213 it seems the rx timestamp is at the end of the
1893 * frame, but i'm not sure.
1895 * NOTE: mac80211 defines mactime at the beginning of the first
1896 * data symbol. Since we don't have any time references it's
1897 * impossible to comply to that. This affects IBSS merge only
1898 * right now, so it's not too bad...
1900 rxs->mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
1901 rxs->flag = rx_flag | RX_FLAG_TSFT;
1903 rxs->freq = sc->curchan->center_freq;
1904 rxs->band = sc->curband->band;
1906 rxs->noise = sc->ah->ah_noise_floor;
1907 rxs->signal = rxs->noise + rs.rs_rssi;
1909 rxs->antenna = rs.rs_antenna;
1910 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1911 rxs->flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
1913 if (rxs->rate_idx >= 0 && rs.rs_rate ==
1914 sc->curband->bitrates[rxs->rate_idx].hw_value_short)
1915 rxs->flag |= RX_FLAG_SHORTPRE;
1917 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1919 /* check beacons in IBSS mode */
1920 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1921 ath5k_check_ibss_tsf(sc, skb, rxs);
1923 ieee80211_rx(sc->hw, skb);
1926 bf->skbaddr = next_skb_addr;
1928 list_move_tail(&bf->list, &sc->rxbuf);
1929 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1931 spin_unlock(&sc->rxbuflock);
1942 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1944 struct ath5k_tx_status ts = {};
1945 struct ath5k_buf *bf, *bf0;
1946 struct ath5k_desc *ds;
1947 struct sk_buff *skb;
1948 struct ieee80211_tx_info *info;
1951 spin_lock(&txq->lock);
1952 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1955 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1956 if (unlikely(ret == -EINPROGRESS))
1958 else if (unlikely(ret)) {
1959 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1965 info = IEEE80211_SKB_CB(skb);
1968 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1971 ieee80211_tx_info_clear_status(info);
1972 for (i = 0; i < 4; i++) {
1973 struct ieee80211_tx_rate *r =
1974 &info->status.rates[i];
1976 if (ts.ts_rate[i]) {
1977 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1978 r->count = ts.ts_retry[i];
1985 /* count the successful attempt as well */
1986 info->status.rates[ts.ts_final_idx].count++;
1988 if (unlikely(ts.ts_status)) {
1989 sc->ll_stats.dot11ACKFailureCount++;
1990 if (ts.ts_status & AR5K_TXERR_FILT)
1991 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1993 info->flags |= IEEE80211_TX_STAT_ACK;
1994 info->status.ack_signal = ts.ts_rssi;
1997 ieee80211_tx_status(sc->hw, skb);
1998 sc->tx_stats[txq->qnum].count++;
2000 spin_lock(&sc->txbuflock);
2001 sc->tx_stats[txq->qnum].len--;
2002 list_move_tail(&bf->list, &sc->txbuf);
2004 spin_unlock(&sc->txbuflock);
2006 if (likely(list_empty(&txq->q)))
2008 spin_unlock(&txq->lock);
2009 if (sc->txbuf_len > ATH_TXBUF / 5)
2010 ieee80211_wake_queues(sc->hw);
2014 ath5k_tasklet_tx(unsigned long data)
2017 struct ath5k_softc *sc = (void *)data;
2019 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
2020 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
2021 ath5k_tx_processq(sc, &sc->txqs[i]);
2030 * Setup the beacon frame for transmit.
2033 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
2035 struct sk_buff *skb = bf->skb;
2036 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2037 struct ath5k_hw *ah = sc->ah;
2038 struct ath5k_desc *ds;
2043 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2045 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2046 "skbaddr %llx\n", skb, skb->data, skb->len,
2047 (unsigned long long)bf->skbaddr);
2048 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
2049 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2054 antenna = ah->ah_tx_ant;
2056 flags = AR5K_TXDESC_NOACK;
2057 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
2058 ds->ds_link = bf->daddr; /* self-linked */
2059 flags |= AR5K_TXDESC_VEOL;
2064 * If we use multiple antennas on AP and use
2065 * the Sectored AP scenario, switch antenna every
2066 * 4 beacons to make sure everybody hears our AP.
2067 * When a client tries to associate, hw will keep
2068 * track of the tx antenna to be used for this client
2069 * automaticaly, based on ACKed packets.
2071 * Note: AP still listens and transmits RTS on the
2072 * default antenna which is supposed to be an omni.
2074 * Note2: On sectored scenarios it's possible to have
2075 * multiple antennas (1omni -the default- and 14 sectors)
2076 * so if we choose to actually support this mode we need
2077 * to allow user to set how many antennas we have and tweak
2078 * the code below to send beacons on all of them.
2080 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
2081 antenna = sc->bsent & 4 ? 2 : 1;
2084 /* FIXME: If we are in g mode and rate is a CCK rate
2085 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
2086 * from tx power (value is in dB units already) */
2087 ds->ds_data = bf->skbaddr;
2088 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
2089 ieee80211_get_hdrlen_from_skb(skb),
2090 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
2091 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2092 1, AR5K_TXKEYIX_INVALID,
2093 antenna, flags, 0, 0);
2099 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2104 * Transmit a beacon frame at SWBA. Dynamic updates to the
2105 * frame contents are done as needed and the slot time is
2106 * also adjusted based on current state.
2108 * This is called from software irq context (beacontq or restq
2109 * tasklets) or user context from ath5k_beacon_config.
2112 ath5k_beacon_send(struct ath5k_softc *sc)
2114 struct ath5k_buf *bf = sc->bbuf;
2115 struct ath5k_hw *ah = sc->ah;
2116 struct sk_buff *skb;
2118 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
2120 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2121 sc->opmode == NL80211_IFTYPE_MONITOR)) {
2122 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2126 * Check if the previous beacon has gone out. If
2127 * not don't don't try to post another, skip this
2128 * period and wait for the next. Missed beacons
2129 * indicate a problem and should not occur. If we
2130 * miss too many consecutive beacons reset the device.
2132 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2134 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2135 "missed %u consecutive beacons\n", sc->bmisscount);
2136 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
2137 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2138 "stuck beacon time (%u missed)\n",
2140 tasklet_schedule(&sc->restq);
2144 if (unlikely(sc->bmisscount != 0)) {
2145 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2146 "resume beacon xmit after %u misses\n",
2152 * Stop any current dma and put the new frame on the queue.
2153 * This should never fail since we check above that no frames
2154 * are still pending on the queue.
2156 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2157 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
2158 /* NB: hw still stops DMA, so proceed */
2161 /* refresh the beacon for AP mode */
2162 if (sc->opmode == NL80211_IFTYPE_AP)
2163 ath5k_beacon_update(sc->hw, sc->vif);
2165 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2166 ath5k_hw_start_tx_dma(ah, sc->bhalq);
2167 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2168 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2170 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2172 ath5k_tx_queue(sc->hw, skb, sc->cabq);
2173 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2181 * ath5k_beacon_update_timers - update beacon timers
2183 * @sc: struct ath5k_softc pointer we are operating on
2184 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2185 * beacon timer update based on the current HW TSF.
2187 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2188 * of a received beacon or the current local hardware TSF and write it to the
2189 * beacon timer registers.
2191 * This is called in a variety of situations, e.g. when a beacon is received,
2192 * when a TSF update has been detected, but also when an new IBSS is created or
2193 * when we otherwise know we have to update the timers, but we keep it in this
2194 * function to have it all together in one place.
2197 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2199 struct ath5k_hw *ah = sc->ah;
2200 u32 nexttbtt, intval, hw_tu, bc_tu;
2203 intval = sc->bintval & AR5K_BEACON_PERIOD;
2204 if (WARN_ON(!intval))
2207 /* beacon TSF converted to TU */
2208 bc_tu = TSF_TO_TU(bc_tsf);
2210 /* current TSF converted to TU */
2211 hw_tsf = ath5k_hw_get_tsf64(ah);
2212 hw_tu = TSF_TO_TU(hw_tsf);
2215 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2218 * no beacons received, called internally.
2219 * just need to refresh timers based on HW TSF.
2221 nexttbtt = roundup(hw_tu + FUDGE, intval);
2222 } else if (bc_tsf == 0) {
2224 * no beacon received, probably called by ath5k_reset_tsf().
2225 * reset TSF to start with 0.
2228 intval |= AR5K_BEACON_RESET_TSF;
2229 } else if (bc_tsf > hw_tsf) {
2231 * beacon received, SW merge happend but HW TSF not yet updated.
2232 * not possible to reconfigure timers yet, but next time we
2233 * receive a beacon with the same BSSID, the hardware will
2234 * automatically update the TSF and then we need to reconfigure
2237 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2238 "need to wait for HW TSF sync\n");
2242 * most important case for beacon synchronization between STA.
2244 * beacon received and HW TSF has been already updated by HW.
2245 * update next TBTT based on the TSF of the beacon, but make
2246 * sure it is ahead of our local TSF timer.
2248 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2252 sc->nexttbtt = nexttbtt;
2254 intval |= AR5K_BEACON_ENA;
2255 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2258 * debugging output last in order to preserve the time critical aspect
2262 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2263 "reconfigured timers based on HW TSF\n");
2264 else if (bc_tsf == 0)
2265 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2266 "reset HW TSF and timers\n");
2268 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2269 "updated timers based on beacon TSF\n");
2271 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2272 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2273 (unsigned long long) bc_tsf,
2274 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2275 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2276 intval & AR5K_BEACON_PERIOD,
2277 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2278 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2283 * ath5k_beacon_config - Configure the beacon queues and interrupts
2285 * @sc: struct ath5k_softc pointer we are operating on
2287 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2288 * interrupts to detect TSF updates only.
2291 ath5k_beacon_config(struct ath5k_softc *sc)
2293 struct ath5k_hw *ah = sc->ah;
2294 unsigned long flags;
2296 spin_lock_irqsave(&sc->block, flags);
2298 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2300 if (sc->enable_beacon) {
2302 * In IBSS mode we use a self-linked tx descriptor and let the
2303 * hardware send the beacons automatically. We have to load it
2305 * We use the SWBA interrupt only to keep track of the beacon
2306 * timers in order to detect automatic TSF updates.
2308 ath5k_beaconq_config(sc);
2310 sc->imask |= AR5K_INT_SWBA;
2312 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2313 if (ath5k_hw_hasveol(ah))
2314 ath5k_beacon_send(sc);
2316 ath5k_beacon_update_timers(sc, -1);
2318 ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
2321 ath5k_hw_set_imr(ah, sc->imask);
2323 spin_unlock_irqrestore(&sc->block, flags);
2326 static void ath5k_tasklet_beacon(unsigned long data)
2328 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2331 * Software beacon alert--time to send a beacon.
2333 * In IBSS mode we use this interrupt just to
2334 * keep track of the next TBTT (target beacon
2335 * transmission time) in order to detect wether
2336 * automatic TSF updates happened.
2338 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2339 /* XXX: only if VEOL suppported */
2340 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2341 sc->nexttbtt += sc->bintval;
2342 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2343 "SWBA nexttbtt: %x hw_tu: %x "
2347 (unsigned long long) tsf);
2349 spin_lock(&sc->block);
2350 ath5k_beacon_send(sc);
2351 spin_unlock(&sc->block);
2356 /********************\
2357 * Interrupt handling *
2358 \********************/
2361 ath5k_init(struct ath5k_softc *sc)
2363 struct ath5k_hw *ah = sc->ah;
2366 mutex_lock(&sc->lock);
2368 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2371 * Stop anything previously setup. This is safe
2372 * no matter this is the first time through or not.
2374 ath5k_stop_locked(sc);
2376 /* Set PHY calibration interval */
2377 ah->ah_cal_intval = ath5k_calinterval;
2380 * The basic interface to setting the hardware in a good
2381 * state is ``reset''. On return the hardware is known to
2382 * be powered up and with interrupts disabled. This must
2383 * be followed by initialization of the appropriate bits
2384 * and then setup of the interrupt mask.
2386 sc->curchan = sc->hw->conf.channel;
2387 sc->curband = &sc->sbands[sc->curchan->band];
2388 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2389 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2390 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_SWI;
2391 ret = ath5k_reset(sc, NULL);
2395 ath5k_rfkill_hw_start(ah);
2398 * Reset the key cache since some parts do not reset the
2399 * contents on initial power up or resume from suspend.
2401 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2402 ath5k_hw_reset_key(ah, i);
2404 /* Set ack to be sent at low bit-rates */
2405 ath5k_hw_set_ack_bitrate_high(ah, false);
2409 mutex_unlock(&sc->lock);
2414 ath5k_stop_locked(struct ath5k_softc *sc)
2416 struct ath5k_hw *ah = sc->ah;
2418 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2419 test_bit(ATH_STAT_INVALID, sc->status));
2422 * Shutdown the hardware and driver:
2423 * stop output from above
2424 * disable interrupts
2426 * turn off the radio
2427 * clear transmit machinery
2428 * clear receive machinery
2429 * drain and release tx queues
2430 * reclaim beacon resources
2431 * power down hardware
2433 * Note that some of this work is not possible if the
2434 * hardware is gone (invalid).
2436 ieee80211_stop_queues(sc->hw);
2438 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2440 ath5k_hw_set_imr(ah, 0);
2441 synchronize_irq(sc->pdev->irq);
2443 ath5k_txq_cleanup(sc);
2444 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2446 ath5k_hw_phy_disable(ah);
2454 * Stop the device, grabbing the top-level lock to protect
2455 * against concurrent entry through ath5k_init (which can happen
2456 * if another thread does a system call and the thread doing the
2457 * stop is preempted).
2460 ath5k_stop_hw(struct ath5k_softc *sc)
2464 mutex_lock(&sc->lock);
2465 ret = ath5k_stop_locked(sc);
2466 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2468 * Don't set the card in full sleep mode!
2470 * a) When the device is in this state it must be carefully
2471 * woken up or references to registers in the PCI clock
2472 * domain may freeze the bus (and system). This varies
2473 * by chip and is mostly an issue with newer parts
2474 * (madwifi sources mentioned srev >= 0x78) that go to
2475 * sleep more quickly.
2477 * b) On older chips full sleep results a weird behaviour
2478 * during wakeup. I tested various cards with srev < 0x78
2479 * and they don't wake up after module reload, a second
2480 * module reload is needed to bring the card up again.
2482 * Until we figure out what's going on don't enable
2483 * full chip reset on any chip (this is what Legacy HAL
2484 * and Sam's HAL do anyway). Instead Perform a full reset
2485 * on the device (same as initial state after attach) and
2486 * leave it idle (keep MAC/BB on warm reset) */
2487 ret = ath5k_hw_on_hold(sc->ah);
2489 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2490 "putting device to sleep\n");
2492 ath5k_txbuf_free(sc, sc->bbuf);
2495 mutex_unlock(&sc->lock);
2497 tasklet_kill(&sc->rxtq);
2498 tasklet_kill(&sc->txtq);
2499 tasklet_kill(&sc->restq);
2500 tasklet_kill(&sc->calib);
2501 tasklet_kill(&sc->beacontq);
2503 ath5k_rfkill_hw_stop(sc->ah);
2509 ath5k_intr(int irq, void *dev_id)
2511 struct ath5k_softc *sc = dev_id;
2512 struct ath5k_hw *ah = sc->ah;
2513 enum ath5k_int status;
2514 unsigned int counter = 1000;
2516 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2517 !ath5k_hw_is_intr_pending(ah)))
2521 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2522 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2524 if (unlikely(status & AR5K_INT_FATAL)) {
2526 * Fatal errors are unrecoverable.
2527 * Typically these are caused by DMA errors.
2529 tasklet_schedule(&sc->restq);
2530 } else if (unlikely(status & AR5K_INT_RXORN)) {
2531 tasklet_schedule(&sc->restq);
2533 if (status & AR5K_INT_SWBA) {
2534 tasklet_hi_schedule(&sc->beacontq);
2536 if (status & AR5K_INT_RXEOL) {
2538 * NB: the hardware should re-read the link when
2539 * RXE bit is written, but it doesn't work at
2540 * least on older hardware revs.
2544 if (status & AR5K_INT_TXURN) {
2545 /* bump tx trigger level */
2546 ath5k_hw_update_tx_triglevel(ah, true);
2548 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2549 tasklet_schedule(&sc->rxtq);
2550 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2551 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
2552 tasklet_schedule(&sc->txtq);
2553 if (status & AR5K_INT_BMISS) {
2556 if (status & AR5K_INT_SWI) {
2557 tasklet_schedule(&sc->calib);
2559 if (status & AR5K_INT_MIB) {
2561 * These stats are also used for ANI i think
2562 * so how about updating them more often ?
2564 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2566 if (status & AR5K_INT_GPIO)
2567 tasklet_schedule(&sc->rf_kill.toggleq);
2570 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
2572 if (unlikely(!counter))
2573 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2575 ath5k_hw_calibration_poll(ah);
2581 ath5k_tasklet_reset(unsigned long data)
2583 struct ath5k_softc *sc = (void *)data;
2585 ath5k_reset_wake(sc);
2589 * Periodically recalibrate the PHY to account
2590 * for temperature/environment changes.
2593 ath5k_tasklet_calibrate(unsigned long data)
2595 struct ath5k_softc *sc = (void *)data;
2596 struct ath5k_hw *ah = sc->ah;
2598 /* Only full calibration for now */
2599 if (ah->ah_swi_mask != AR5K_SWI_FULL_CALIBRATION)
2602 /* Stop queues so that calibration
2603 * doesn't interfere with tx */
2604 ieee80211_stop_queues(sc->hw);
2606 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2607 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2608 sc->curchan->hw_value);
2610 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2612 * Rfgain is out of bounds, reset the chip
2613 * to load new gain values.
2615 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2616 ath5k_reset_wake(sc);
2618 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2619 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2620 ieee80211_frequency_to_channel(
2621 sc->curchan->center_freq));
2623 ah->ah_swi_mask = 0;
2626 ieee80211_wake_queues(sc->hw);
2631 /********************\
2632 * Mac80211 functions *
2633 \********************/
2636 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2638 struct ath5k_softc *sc = hw->priv;
2640 return ath5k_tx_queue(hw, skb, sc->txq);
2643 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
2644 struct ath5k_txq *txq)
2646 struct ath5k_softc *sc = hw->priv;
2647 struct ath5k_buf *bf;
2648 unsigned long flags;
2652 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2654 if (sc->opmode == NL80211_IFTYPE_MONITOR)
2655 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2658 * the hardware expects the header padded to 4 byte boundaries
2659 * if this is not the case we add the padding after the header
2661 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2662 padsize = ath5k_pad_size(hdrlen);
2665 if (skb_headroom(skb) < padsize) {
2666 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2667 " headroom to pad %d\n", hdrlen, padsize);
2670 skb_push(skb, padsize);
2671 memmove(skb->data, skb->data+padsize, hdrlen);
2674 spin_lock_irqsave(&sc->txbuflock, flags);
2675 if (list_empty(&sc->txbuf)) {
2676 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2677 spin_unlock_irqrestore(&sc->txbuflock, flags);
2678 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
2681 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2682 list_del(&bf->list);
2684 if (list_empty(&sc->txbuf))
2685 ieee80211_stop_queues(hw);
2686 spin_unlock_irqrestore(&sc->txbuflock, flags);
2690 if (ath5k_txbuf_setup(sc, bf, txq)) {
2692 spin_lock_irqsave(&sc->txbuflock, flags);
2693 list_add_tail(&bf->list, &sc->txbuf);
2695 spin_unlock_irqrestore(&sc->txbuflock, flags);
2698 return NETDEV_TX_OK;
2701 dev_kfree_skb_any(skb);
2702 return NETDEV_TX_OK;
2706 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2707 * and change to the given channel.
2710 ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
2712 struct ath5k_hw *ah = sc->ah;
2715 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2718 ath5k_hw_set_imr(ah, 0);
2719 ath5k_txq_cleanup(sc);
2723 sc->curband = &sc->sbands[chan->band];
2725 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL);
2727 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2731 ret = ath5k_rx_start(sc);
2733 ATH5K_ERR(sc, "can't start recv logic\n");
2738 * Change channels and update the h/w rate map if we're switching;
2739 * e.g. 11a to 11b/g.
2741 * We may be doing a reset in response to an ioctl that changes the
2742 * channel so update any state that might change as a result.
2746 /* ath5k_chan_change(sc, c); */
2748 ath5k_beacon_config(sc);
2749 /* intrs are enabled by ath5k_beacon_config */
2757 ath5k_reset_wake(struct ath5k_softc *sc)
2761 ret = ath5k_reset(sc, sc->curchan);
2763 ieee80211_wake_queues(sc->hw);
2768 static int ath5k_start(struct ieee80211_hw *hw)
2770 return ath5k_init(hw->priv);
2773 static void ath5k_stop(struct ieee80211_hw *hw)
2775 ath5k_stop_hw(hw->priv);
2778 static int ath5k_add_interface(struct ieee80211_hw *hw,
2779 struct ieee80211_vif *vif)
2781 struct ath5k_softc *sc = hw->priv;
2784 mutex_lock(&sc->lock);
2792 switch (vif->type) {
2793 case NL80211_IFTYPE_AP:
2794 case NL80211_IFTYPE_STATION:
2795 case NL80211_IFTYPE_ADHOC:
2796 case NL80211_IFTYPE_MESH_POINT:
2797 case NL80211_IFTYPE_MONITOR:
2798 sc->opmode = vif->type;
2805 ath5k_hw_set_lladdr(sc->ah, vif->addr);
2806 ath5k_mode_setup(sc);
2810 mutex_unlock(&sc->lock);
2815 ath5k_remove_interface(struct ieee80211_hw *hw,
2816 struct ieee80211_vif *vif)
2818 struct ath5k_softc *sc = hw->priv;
2819 u8 mac[ETH_ALEN] = {};
2821 mutex_lock(&sc->lock);
2825 ath5k_hw_set_lladdr(sc->ah, mac);
2828 mutex_unlock(&sc->lock);
2832 * TODO: Phy disable/diversity etc
2835 ath5k_config(struct ieee80211_hw *hw, u32 changed)
2837 struct ath5k_softc *sc = hw->priv;
2838 struct ath5k_hw *ah = sc->ah;
2839 struct ieee80211_conf *conf = &hw->conf;
2842 mutex_lock(&sc->lock);
2844 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2845 ret = ath5k_chan_set(sc, conf->channel);
2850 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
2851 (sc->power_level != conf->power_level)) {
2852 sc->power_level = conf->power_level;
2855 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
2859 * 1) Move this on config_interface and handle each case
2860 * separately eg. when we have only one STA vif, use
2861 * AR5K_ANTMODE_SINGLE_AP
2863 * 2) Allow the user to change antenna mode eg. when only
2864 * one antenna is present
2866 * 3) Allow the user to set default/tx antenna when possible
2868 * 4) Default mode should handle 90% of the cases, together
2869 * with fixed a/b and single AP modes we should be able to
2870 * handle 99%. Sectored modes are extreme cases and i still
2871 * haven't found a usage for them. If we decide to support them,
2872 * then we must allow the user to set how many tx antennas we
2875 ath5k_hw_set_antenna_mode(ah, AR5K_ANTMODE_DEFAULT);
2878 mutex_unlock(&sc->lock);
2882 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
2883 int mc_count, struct dev_addr_list *mclist)
2892 for (i = 0; i < mc_count; i++) {
2895 /* calculate XOR of eight 6-bit values */
2896 val = get_unaligned_le32(mclist->dmi_addr + 0);
2897 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2898 val = get_unaligned_le32(mclist->dmi_addr + 3);
2899 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2901 mfilt[pos / 32] |= (1 << (pos % 32));
2902 /* XXX: we might be able to just do this instead,
2903 * but not sure, needs testing, if we do use this we'd
2904 * neet to inform below to not reset the mcast */
2905 /* ath5k_hw_set_mcast_filterindex(ah,
2906 * mclist->dmi_addr[5]); */
2907 mclist = mclist->next;
2910 return ((u64)(mfilt[1]) << 32) | mfilt[0];
2913 #define SUPPORTED_FIF_FLAGS \
2914 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2915 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2916 FIF_BCN_PRBRESP_PROMISC
2918 * o always accept unicast, broadcast, and multicast traffic
2919 * o multicast traffic for all BSSIDs will be enabled if mac80211
2921 * o maintain current state of phy ofdm or phy cck error reception.
2922 * If the hardware detects any of these type of errors then
2923 * ath5k_hw_get_rx_filter() will pass to us the respective
2924 * hardware filters to be able to receive these type of frames.
2925 * o probe request frames are accepted only when operating in
2926 * hostap, adhoc, or monitor modes
2927 * o enable promiscuous mode according to the interface state
2929 * - when operating in adhoc mode so the 802.11 layer creates
2930 * node table entries for peers,
2931 * - when operating in station mode for collecting rssi data when
2932 * the station is otherwise quiet, or
2935 static void ath5k_configure_filter(struct ieee80211_hw *hw,
2936 unsigned int changed_flags,
2937 unsigned int *new_flags,
2940 struct ath5k_softc *sc = hw->priv;
2941 struct ath5k_hw *ah = sc->ah;
2942 u32 mfilt[2], rfilt;
2944 mutex_lock(&sc->lock);
2946 mfilt[0] = multicast;
2947 mfilt[1] = multicast >> 32;
2949 /* Only deal with supported flags */
2950 changed_flags &= SUPPORTED_FIF_FLAGS;
2951 *new_flags &= SUPPORTED_FIF_FLAGS;
2953 /* If HW detects any phy or radar errors, leave those filters on.
2954 * Also, always enable Unicast, Broadcasts and Multicast
2955 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2956 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2957 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2958 AR5K_RX_FILTER_MCAST);
2960 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2961 if (*new_flags & FIF_PROMISC_IN_BSS) {
2962 rfilt |= AR5K_RX_FILTER_PROM;
2963 __set_bit(ATH_STAT_PROMISC, sc->status);
2965 __clear_bit(ATH_STAT_PROMISC, sc->status);
2969 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2970 if (*new_flags & FIF_ALLMULTI) {
2975 /* This is the best we can do */
2976 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2977 rfilt |= AR5K_RX_FILTER_PHYERR;
2979 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2980 * and probes for any BSSID, this needs testing */
2981 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2982 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2984 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2985 * set we should only pass on control frames for this
2986 * station. This needs testing. I believe right now this
2987 * enables *all* control frames, which is OK.. but
2988 * but we should see if we can improve on granularity */
2989 if (*new_flags & FIF_CONTROL)
2990 rfilt |= AR5K_RX_FILTER_CONTROL;
2992 /* Additional settings per mode -- this is per ath5k */
2994 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2996 switch (sc->opmode) {
2997 case NL80211_IFTYPE_MESH_POINT:
2998 case NL80211_IFTYPE_MONITOR:
2999 rfilt |= AR5K_RX_FILTER_CONTROL |
3000 AR5K_RX_FILTER_BEACON |
3001 AR5K_RX_FILTER_PROBEREQ |
3002 AR5K_RX_FILTER_PROM;
3004 case NL80211_IFTYPE_AP:
3005 case NL80211_IFTYPE_ADHOC:
3006 rfilt |= AR5K_RX_FILTER_PROBEREQ |
3007 AR5K_RX_FILTER_BEACON;
3009 case NL80211_IFTYPE_STATION:
3011 rfilt |= AR5K_RX_FILTER_BEACON;
3017 ath5k_hw_set_rx_filter(ah, rfilt);
3019 /* Set multicast bits */
3020 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
3021 /* Set the cached hw filter flags, this will alter actually
3023 sc->filter_flags = rfilt;
3025 mutex_unlock(&sc->lock);
3029 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3030 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3031 struct ieee80211_key_conf *key)
3033 struct ath5k_softc *sc = hw->priv;
3034 struct ath5k_hw *ah = sc->ah;
3035 struct ath_common *common = ath5k_hw_common(ah);
3038 if (modparam_nohwcrypt)
3041 if (sc->opmode == NL80211_IFTYPE_AP)
3049 if (sc->ah->ah_aes_support)
3058 mutex_lock(&sc->lock);
3062 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
3063 sta ? sta->addr : NULL);
3065 ATH5K_ERR(sc, "can't set the key\n");
3068 __set_bit(key->keyidx, common->keymap);
3069 key->hw_key_idx = key->keyidx;
3070 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
3071 IEEE80211_KEY_FLAG_GENERATE_MMIC);
3074 ath5k_hw_reset_key(sc->ah, key->keyidx);
3075 __clear_bit(key->keyidx, common->keymap);
3084 mutex_unlock(&sc->lock);
3089 ath5k_get_stats(struct ieee80211_hw *hw,
3090 struct ieee80211_low_level_stats *stats)
3092 struct ath5k_softc *sc = hw->priv;
3093 struct ath5k_hw *ah = sc->ah;
3096 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
3098 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3104 ath5k_get_tx_stats(struct ieee80211_hw *hw,
3105 struct ieee80211_tx_queue_stats *stats)
3107 struct ath5k_softc *sc = hw->priv;
3109 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3115 ath5k_get_tsf(struct ieee80211_hw *hw)
3117 struct ath5k_softc *sc = hw->priv;
3119 return ath5k_hw_get_tsf64(sc->ah);
3123 ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3125 struct ath5k_softc *sc = hw->priv;
3127 ath5k_hw_set_tsf64(sc->ah, tsf);
3131 ath5k_reset_tsf(struct ieee80211_hw *hw)
3133 struct ath5k_softc *sc = hw->priv;
3136 * in IBSS mode we need to update the beacon timers too.
3137 * this will also reset the TSF if we call it with 0
3139 if (sc->opmode == NL80211_IFTYPE_ADHOC)
3140 ath5k_beacon_update_timers(sc, 0);
3142 ath5k_hw_reset_tsf(sc->ah);
3146 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
3147 * this is called only once at config_bss time, for AP we do it every
3148 * SWBA interrupt so that the TIM will reflect buffered frames.
3150 * Called with the beacon lock.
3153 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
3156 struct ath5k_softc *sc = hw->priv;
3157 struct sk_buff *skb;
3159 if (WARN_ON(!vif)) {
3164 skb = ieee80211_beacon_get(hw, vif);
3171 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3173 ath5k_txbuf_free(sc, sc->bbuf);
3174 sc->bbuf->skb = skb;
3175 ret = ath5k_beacon_setup(sc, sc->bbuf);
3177 sc->bbuf->skb = NULL;
3183 set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3185 struct ath5k_softc *sc = hw->priv;
3186 struct ath5k_hw *ah = sc->ah;
3188 rfilt = ath5k_hw_get_rx_filter(ah);
3190 rfilt |= AR5K_RX_FILTER_BEACON;
3192 rfilt &= ~AR5K_RX_FILTER_BEACON;
3193 ath5k_hw_set_rx_filter(ah, rfilt);
3194 sc->filter_flags = rfilt;
3197 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3198 struct ieee80211_vif *vif,
3199 struct ieee80211_bss_conf *bss_conf,
3202 struct ath5k_softc *sc = hw->priv;
3203 struct ath5k_hw *ah = sc->ah;
3204 struct ath_common *common = ath5k_hw_common(ah);
3205 unsigned long flags;
3207 mutex_lock(&sc->lock);
3208 if (WARN_ON(sc->vif != vif))
3211 if (changes & BSS_CHANGED_BSSID) {
3212 /* Cache for later use during resets */
3213 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
3215 ath5k_hw_set_associd(ah);
3219 if (changes & BSS_CHANGED_BEACON_INT)
3220 sc->bintval = bss_conf->beacon_int;
3222 if (changes & BSS_CHANGED_ASSOC) {
3223 sc->assoc = bss_conf->assoc;
3224 if (sc->opmode == NL80211_IFTYPE_STATION)
3225 set_beacon_filter(hw, sc->assoc);
3226 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3227 AR5K_LED_ASSOC : AR5K_LED_INIT);
3228 if (bss_conf->assoc) {
3229 ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3230 "Bss Info ASSOC %d, bssid: %pM\n",
3231 bss_conf->aid, common->curbssid);
3232 common->curaid = bss_conf->aid;
3233 ath5k_hw_set_associd(ah);
3234 /* Once ANI is available you would start it here */
3238 if (changes & BSS_CHANGED_BEACON) {
3239 spin_lock_irqsave(&sc->block, flags);
3240 ath5k_beacon_update(hw, vif);
3241 spin_unlock_irqrestore(&sc->block, flags);
3244 if (changes & BSS_CHANGED_BEACON_ENABLED)
3245 sc->enable_beacon = bss_conf->enable_beacon;
3247 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
3248 BSS_CHANGED_BEACON_INT))
3249 ath5k_beacon_config(sc);
3252 mutex_unlock(&sc->lock);
3255 static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
3257 struct ath5k_softc *sc = hw->priv;
3259 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
3262 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
3264 struct ath5k_softc *sc = hw->priv;
3265 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3266 AR5K_LED_ASSOC : AR5K_LED_INIT);
3270 * ath5k_set_coverage_class - Set IEEE 802.11 coverage class
3272 * @hw: struct ieee80211_hw pointer
3273 * @coverage_class: IEEE 802.11 coverage class number
3275 * Mac80211 callback. Sets slot time, ACK timeout and CTS timeout for given
3276 * coverage class. The values are persistent, they are restored after device
3279 static void ath5k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
3281 struct ath5k_softc *sc = hw->priv;
3283 mutex_lock(&sc->lock);
3284 ath5k_hw_set_coverage_class(sc->ah, coverage_class);
3285 mutex_unlock(&sc->lock);
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