Pileus Git - ~andy/linux/blob - drivers/net/usb/r8152.c

   1 /*
   2  *  Copyright (c) 2013 Realtek Semiconductor Corp. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * version 2 as published by the Free Software Foundation.
   7  *
   8  */
   9
  10 #include <linux/init.h>
  11 #include <linux/signal.h>
  12 #include <linux/slab.h>
  13 #include <linux/module.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/mii.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/usb.h>
  19 #include <linux/crc32.h>
  20 #include <linux/if_vlan.h>
  21 #include <linux/uaccess.h>
  22 #include <linux/list.h>
  23 #include <linux/ip.h>
  24 #include <linux/ipv6.h>
  25
  26 /* Version Information */
  27 #define DRIVER_VERSION "v1.03.0 (2013/12/26)"
  28 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
  29 #define DRIVER_DESC "Realtek RTL8152 Based USB 2.0 Ethernet Adapters"
  30 #define MODULENAME "r8152"
  31
  32 #define R8152_PHY_ID            32
  33
  34 #define PLA_IDR                 0xc000
  35 #define PLA_RCR                 0xc010
  36 #define PLA_RMS                 0xc016
  37 #define PLA_RXFIFO_CTRL0        0xc0a0
  38 #define PLA_RXFIFO_CTRL1        0xc0a4
  39 #define PLA_RXFIFO_CTRL2        0xc0a8
  40 #define PLA_FMC                 0xc0b4
  41 #define PLA_CFG_WOL             0xc0b6
  42 #define PLA_TEREDO_CFG          0xc0bc
  43 #define PLA_MAR                 0xcd00
  44 #define PLA_BACKUP              0xd000
  45 #define PAL_BDC_CR              0xd1a0
  46 #define PLA_TEREDO_TIMER        0xd2cc
  47 #define PLA_REALWOW_TIMER       0xd2e8
  48 #define PLA_LEDSEL              0xdd90
  49 #define PLA_LED_FEATURE         0xdd92
  50 #define PLA_PHYAR               0xde00
  51 #define PLA_BOOT_CTRL           0xe004
  52 #define PLA_GPHY_INTR_IMR       0xe022
  53 #define PLA_EEE_CR              0xe040
  54 #define PLA_EEEP_CR             0xe080
  55 #define PLA_MAC_PWR_CTRL        0xe0c0
  56 #define PLA_MAC_PWR_CTRL2       0xe0ca
  57 #define PLA_MAC_PWR_CTRL3       0xe0cc
  58 #define PLA_MAC_PWR_CTRL4       0xe0ce
  59 #define PLA_WDT6_CTRL           0xe428
  60 #define PLA_TCR0                0xe610
  61 #define PLA_TCR1                0xe612
  62 #define PLA_TXFIFO_CTRL         0xe618
  63 #define PLA_RSTTELLY            0xe800
  64 #define PLA_CR                  0xe813
  65 #define PLA_CRWECR              0xe81c
  66 #define PLA_CONFIG5             0xe822
  67 #define PLA_PHY_PWR             0xe84c
  68 #define PLA_OOB_CTRL            0xe84f
  69 #define PLA_CPCR                0xe854
  70 #define PLA_MISC_0              0xe858
  71 #define PLA_MISC_1              0xe85a
  72 #define PLA_OCP_GPHY_BASE       0xe86c
  73 #define PLA_TELLYCNT            0xe890
  74 #define PLA_SFF_STS_7           0xe8de
  75 #define PLA_PHYSTATUS           0xe908
  76 #define PLA_BP_BA               0xfc26
  77 #define PLA_BP_0                0xfc28
  78 #define PLA_BP_1                0xfc2a
  79 #define PLA_BP_2                0xfc2c
  80 #define PLA_BP_3                0xfc2e
  81 #define PLA_BP_4                0xfc30
  82 #define PLA_BP_5                0xfc32
  83 #define PLA_BP_6                0xfc34
  84 #define PLA_BP_7                0xfc36
  85 #define PLA_BP_EN               0xfc38
  86
  87 #define USB_U2P3_CTRL           0xb460
  88 #define USB_DEV_STAT            0xb808
  89 #define USB_USB_CTRL            0xd406
  90 #define USB_PHY_CTRL            0xd408
  91 #define USB_TX_AGG              0xd40a
  92 #define USB_RX_BUF_TH           0xd40c
  93 #define USB_USB_TIMER           0xd428
  94 #define USB_RX_EARLY_AGG        0xd42c
  95 #define USB_PM_CTRL_STATUS      0xd432
  96 #define USB_TX_DMA              0xd434
  97 #define USB_TOLERANCE           0xd490
  98 #define USB_LPM_CTRL            0xd41a
  99 #define USB_UPS_CTRL            0xd800
 100 #define USB_MISC_0              0xd81a
 101 #define USB_POWER_CUT           0xd80a
 102 #define USB_AFE_CTRL2           0xd824
 103 #define USB_WDT11_CTRL          0xe43c
 104 #define USB_BP_BA               0xfc26
 105 #define USB_BP_0                0xfc28
 106 #define USB_BP_1                0xfc2a
 107 #define USB_BP_2                0xfc2c
 108 #define USB_BP_3                0xfc2e
 109 #define USB_BP_4                0xfc30
 110 #define USB_BP_5                0xfc32
 111 #define USB_BP_6                0xfc34
 112 #define USB_BP_7                0xfc36
 113 #define USB_BP_EN               0xfc38
 114
 115 /* OCP Registers */
 116 #define OCP_ALDPS_CONFIG        0x2010
 117 #define OCP_EEE_CONFIG1         0x2080
 118 #define OCP_EEE_CONFIG2         0x2092
 119 #define OCP_EEE_CONFIG3         0x2094
 120 #define OCP_BASE_MII            0xa400
 121 #define OCP_EEE_AR              0xa41a
 122 #define OCP_EEE_DATA            0xa41c
 123 #define OCP_PHY_STATUS          0xa420
 124 #define OCP_POWER_CFG           0xa430
 125 #define OCP_EEE_CFG             0xa432
 126 #define OCP_SRAM_ADDR           0xa436
 127 #define OCP_SRAM_DATA           0xa438
 128 #define OCP_DOWN_SPEED          0xa442
 129 #define OCP_EEE_CFG2            0xa5d0
 130 #define OCP_ADC_CFG             0xbc06
 131
 132 /* SRAM Register */
 133 #define SRAM_LPF_CFG            0x8012
 134 #define SRAM_10M_AMP1           0x8080
 135 #define SRAM_10M_AMP2           0x8082
 136 #define SRAM_IMPEDANCE          0x8084
 137
 138 /* PLA_RCR */
 139 #define RCR_AAP                 0x00000001
 140 #define RCR_APM                 0x00000002
 141 #define RCR_AM                  0x00000004
 142 #define RCR_AB                  0x00000008
 143 #define RCR_ACPT_ALL            (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
 144
 145 /* PLA_RXFIFO_CTRL0 */
 146 #define RXFIFO_THR1_NORMAL      0x00080002
 147 #define RXFIFO_THR1_OOB         0x01800003
 148
 149 /* PLA_RXFIFO_CTRL1 */
 150 #define RXFIFO_THR2_FULL        0x00000060
 151 #define RXFIFO_THR2_HIGH        0x00000038
 152 #define RXFIFO_THR2_OOB         0x0000004a
 153 #define RXFIFO_THR2_NORMAL      0x00a0
 154
 155 /* PLA_RXFIFO_CTRL2 */
 156 #define RXFIFO_THR3_FULL        0x00000078
 157 #define RXFIFO_THR3_HIGH        0x00000048
 158 #define RXFIFO_THR3_OOB         0x0000005a
 159 #define RXFIFO_THR3_NORMAL      0x0110
 160
 161 /* PLA_TXFIFO_CTRL */
 162 #define TXFIFO_THR_NORMAL       0x00400008
 163 #define TXFIFO_THR_NORMAL2      0x01000008
 164
 165 /* PLA_FMC */
 166 #define FMC_FCR_MCU_EN          0x0001
 167
 168 /* PLA_EEEP_CR */
 169 #define EEEP_CR_EEEP_TX         0x0002
 170
 171 /* PLA_WDT6_CTRL */
 172 #define WDT6_SET_MODE           0x0010
 173
 174 /* PLA_TCR0 */
 175 #define TCR0_TX_EMPTY           0x0800
 176 #define TCR0_AUTO_FIFO          0x0080
 177
 178 /* PLA_TCR1 */
 179 #define VERSION_MASK            0x7cf0
 180
 181 /* PLA_CR */
 182 #define CR_RST                  0x10
 183 #define CR_RE                   0x08
 184 #define CR_TE                   0x04
 185
 186 /* PLA_CRWECR */
 187 #define CRWECR_NORAML           0x00
 188 #define CRWECR_CONFIG           0xc0
 189
 190 /* PLA_OOB_CTRL */
 191 #define NOW_IS_OOB              0x80
 192 #define TXFIFO_EMPTY            0x20
 193 #define RXFIFO_EMPTY            0x10
 194 #define LINK_LIST_READY         0x02
 195 #define DIS_MCU_CLROOB          0x01
 196 #define FIFO_EMPTY              (TXFIFO_EMPTY | RXFIFO_EMPTY)
 197
 198 /* PLA_MISC_1 */
 199 #define RXDY_GATED_EN           0x0008
 200
 201 /* PLA_SFF_STS_7 */
 202 #define RE_INIT_LL              0x8000
 203 #define MCU_BORW_EN             0x4000
 204
 205 /* PLA_CPCR */
 206 #define CPCR_RX_VLAN            0x0040
 207
 208 /* PLA_CFG_WOL */
 209 #define MAGIC_EN                0x0001
 210
 211 /* PLA_TEREDO_CFG */
 212 #define TEREDO_SEL              0x8000
 213 #define TEREDO_WAKE_MASK        0x7f00
 214 #define TEREDO_RS_EVENT_MASK    0x00fe
 215 #define OOB_TEREDO_EN           0x0001
 216
 217 /* PAL_BDC_CR */
 218 #define ALDPS_PROXY_MODE        0x0001
 219
 220 /* PLA_CONFIG5 */
 221 #define LAN_WAKE_EN             0x0002
 222
 223 /* PLA_LED_FEATURE */
 224 #define LED_MODE_MASK           0x0700
 225
 226 /* PLA_PHY_PWR */
 227 #define TX_10M_IDLE_EN          0x0080
 228 #define PFM_PWM_SWITCH          0x0040
 229
 230 /* PLA_MAC_PWR_CTRL */
 231 #define D3_CLK_GATED_EN         0x00004000
 232 #define MCU_CLK_RATIO           0x07010f07
 233 #define MCU_CLK_RATIO_MASK      0x0f0f0f0f
 234 #define ALDPS_SPDWN_RATIO       0x0f87
 235
 236 /* PLA_MAC_PWR_CTRL2 */
 237 #define EEE_SPDWN_RATIO         0x8007
 238
 239 /* PLA_MAC_PWR_CTRL3 */
 240 #define PKT_AVAIL_SPDWN_EN      0x0100
 241 #define SUSPEND_SPDWN_EN        0x0004
 242 #define U1U2_SPDWN_EN           0x0002
 243 #define L1_SPDWN_EN             0x0001
 244
 245 /* PLA_MAC_PWR_CTRL4 */
 246 #define PWRSAVE_SPDWN_EN        0x1000
 247 #define RXDV_SPDWN_EN           0x0800
 248 #define TX10MIDLE_EN            0x0100
 249 #define TP100_SPDWN_EN          0x0020
 250 #define TP500_SPDWN_EN          0x0010
 251 #define TP1000_SPDWN_EN         0x0008
 252 #define EEE_SPDWN_EN            0x0001
 253
 254 /* PLA_GPHY_INTR_IMR */
 255 #define GPHY_STS_MSK            0x0001
 256 #define SPEED_DOWN_MSK          0x0002
 257 #define SPDWN_RXDV_MSK          0x0004
 258 #define SPDWN_LINKCHG_MSK       0x0008
 259
 260 /* PLA_PHYAR */
 261 #define PHYAR_FLAG              0x80000000
 262
 263 /* PLA_EEE_CR */
 264 #define EEE_RX_EN               0x0001
 265 #define EEE_TX_EN               0x0002
 266
 267 /* PLA_BOOT_CTRL */
 268 #define AUTOLOAD_DONE           0x0002
 269
 270 /* USB_DEV_STAT */
 271 #define STAT_SPEED_MASK         0x0006
 272 #define STAT_SPEED_HIGH         0x0000
 273 #define STAT_SPEED_FULL         0x0001
 274
 275 /* USB_TX_AGG */
 276 #define TX_AGG_MAX_THRESHOLD    0x03
 277
 278 /* USB_RX_BUF_TH */
 279 #define RX_THR_SUPPER           0x0c350180
 280 #define RX_THR_HIGH             0x7a120180
 281 #define RX_THR_SLOW             0xffff0180
 282
 283 /* USB_TX_DMA */
 284 #define TEST_MODE_DISABLE       0x00000001
 285 #define TX_SIZE_ADJUST1         0x00000100
 286
 287 /* USB_UPS_CTRL */
 288 #define POWER_CUT               0x0100
 289
 290 /* USB_PM_CTRL_STATUS */
 291 #define RESUME_INDICATE         0x0001
 292
 293 /* USB_USB_CTRL */
 294 #define RX_AGG_DISABLE          0x0010
 295
 296 /* USB_U2P3_CTRL */
 297 #define U2P3_ENABLE             0x0001
 298
 299 /* USB_POWER_CUT */
 300 #define PWR_EN                  0x0001
 301 #define PHASE2_EN               0x0008
 302
 303 /* USB_MISC_0 */
 304 #define PCUT_STATUS             0x0001
 305
 306 /* USB_RX_EARLY_AGG */
 307 #define EARLY_AGG_SUPPER        0x0e832981
 308 #define EARLY_AGG_HIGH          0x0e837a12
 309 #define EARLY_AGG_SLOW          0x0e83ffff
 310
 311 /* USB_WDT11_CTRL */
 312 #define TIMER11_EN              0x0001
 313
 314 /* USB_LPM_CTRL */
 315 #define LPM_TIMER_MASK          0x0c
 316 #define LPM_TIMER_500MS         0x04    /* 500 ms */
 317 #define LPM_TIMER_500US         0x0c    /* 500 us */
 318
 319 /* USB_AFE_CTRL2 */
 320 #define SEN_VAL_MASK            0xf800
 321 #define SEN_VAL_NORMAL          0xa000
 322 #define SEL_RXIDLE              0x0100
 323
 324 /* OCP_ALDPS_CONFIG */
 325 #define ENPWRSAVE               0x8000
 326 #define ENPDNPS                 0x0200
 327 #define LINKENA                 0x0100
 328 #define DIS_SDSAVE              0x0010
 329
 330 /* OCP_PHY_STATUS */
 331 #define PHY_STAT_MASK           0x0007
 332 #define PHY_STAT_LAN_ON         3
 333 #define PHY_STAT_PWRDN          5
 334
 335 /* OCP_POWER_CFG */
 336 #define EEE_CLKDIV_EN           0x8000
 337 #define EN_ALDPS                0x0004
 338 #define EN_10M_PLLOFF           0x0001
 339
 340 /* OCP_EEE_CONFIG1 */
 341 #define RG_TXLPI_MSK_HFDUP      0x8000
 342 #define RG_MATCLR_EN            0x4000
 343 #define EEE_10_CAP              0x2000
 344 #define EEE_NWAY_EN             0x1000
 345 #define TX_QUIET_EN             0x0200
 346 #define RX_QUIET_EN             0x0100
 347 #define SDRISETIME              0x0010  /* bit 4 ~ 6 */
 348 #define RG_RXLPI_MSK_HFDUP      0x0008
 349 #define SDFALLTIME              0x0007  /* bit 0 ~ 2 */
 350
 351 /* OCP_EEE_CONFIG2 */
 352 #define RG_LPIHYS_NUM           0x7000  /* bit 12 ~ 15 */
 353 #define RG_DACQUIET_EN          0x0400
 354 #define RG_LDVQUIET_EN          0x0200
 355 #define RG_CKRSEL               0x0020
 356 #define RG_EEEPRG_EN            0x0010
 357
 358 /* OCP_EEE_CONFIG3 */
 359 #define FST_SNR_EYE_R           0x1500  /* bit 7 ~ 15 */
 360 #define RG_LFS_SEL              0x0060  /* bit 6 ~ 5 */
 361 #define MSK_PH                  0x0006  /* bit 0 ~ 3 */
 362
 363 /* OCP_EEE_AR */
 364 /* bit[15:14] function */
 365 #define FUN_ADDR                0x0000
 366 #define FUN_DATA                0x4000
 367 /* bit[4:0] device addr */
 368 #define DEVICE_ADDR             0x0007
 369
 370 /* OCP_EEE_DATA */
 371 #define EEE_ADDR                0x003C
 372 #define EEE_DATA                0x0002
 373
 374 /* OCP_EEE_CFG */
 375 #define CTAP_SHORT_EN           0x0040
 376 #define EEE10_EN                0x0010
 377
 378 /* OCP_DOWN_SPEED */
 379 #define EN_10M_BGOFF            0x0080
 380
 381 /* OCP_EEE_CFG2 */
 382 #define MY1000_EEE              0x0004
 383 #define MY100_EEE               0x0002
 384
 385 /* OCP_ADC_CFG */
 386 #define CKADSEL_L               0x0100
 387 #define ADC_EN                  0x0080
 388 #define EN_EMI_L                0x0040
 389
 390 /* SRAM_LPF_CFG */
 391 #define LPF_AUTO_TUNE           0x8000
 392
 393 /* SRAM_10M_AMP1 */
 394 #define GDAC_IB_UPALL           0x0008
 395
 396 /* SRAM_10M_AMP2 */
 397 #define AMP_DN                  0x0200
 398
 399 /* SRAM_IMPEDANCE */
 400 #define RX_DRIVING_MASK         0x6000
 401
 402 enum rtl_register_content {
 403         _1000bps        = 0x10,
 404         _100bps         = 0x08,
 405         _10bps          = 0x04,
 406         LINK_STATUS     = 0x02,
 407         FULL_DUP        = 0x01,
 408 };
 409
 410 #define RTL8152_MAX_TX          10
 411 #define RTL8152_MAX_RX          10
 412 #define INTBUFSIZE              2
 413 #define CRC_SIZE                4
 414 #define TX_ALIGN                4
 415 #define RX_ALIGN                8
 416
 417 #define INTR_LINK               0x0004
 418
 419 #define RTL8152_REQT_READ       0xc0
 420 #define RTL8152_REQT_WRITE      0x40
 421 #define RTL8152_REQ_GET_REGS    0x05
 422 #define RTL8152_REQ_SET_REGS    0x05
 423
 424 #define BYTE_EN_DWORD           0xff
 425 #define BYTE_EN_WORD            0x33
 426 #define BYTE_EN_BYTE            0x11
 427 #define BYTE_EN_SIX_BYTES       0x3f
 428 #define BYTE_EN_START_MASK      0x0f
 429 #define BYTE_EN_END_MASK        0xf0
 430
 431 #define RTL8152_RMS             (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
 432 #define RTL8152_TX_TIMEOUT      (HZ)
 433
 434 /* rtl8152 flags */
 435 enum rtl8152_flags {
 436         RTL8152_UNPLUG = 0,
 437         RTL8152_SET_RX_MODE,
 438         WORK_ENABLE,
 439         RTL8152_LINK_CHG,
 440 };
 441
 442 /* Define these values to match your device */
 443 #define VENDOR_ID_REALTEK               0x0bda
 444 #define PRODUCT_ID_RTL8152              0x8152
 445 #define PRODUCT_ID_RTL8153              0x8153
 446
 447 #define VENDOR_ID_SAMSUNG               0x04e8
 448 #define PRODUCT_ID_SAMSUNG              0xa101
 449
 450 #define MCU_TYPE_PLA                    0x0100
 451 #define MCU_TYPE_USB                    0x0000
 452
 453 struct rx_desc {
 454         __le32 opts1;
 455 #define RX_LEN_MASK                     0x7fff
 456         __le32 opts2;
 457         __le32 opts3;
 458         __le32 opts4;
 459         __le32 opts5;
 460         __le32 opts6;
 461 };
 462
 463 struct tx_desc {
 464         __le32 opts1;
 465 #define TX_FS                   (1 << 31) /* First segment of a packet */
 466 #define TX_LS                   (1 << 30) /* Final segment of a packet */
 467 #define TX_LEN_MASK             0x3ffff
 468
 469         __le32 opts2;
 470 #define UDP_CS                  (1 << 31) /* Calculate UDP/IP checksum */
 471 #define TCP_CS                  (1 << 30) /* Calculate TCP/IP checksum */
 472 #define IPV4_CS                 (1 << 29) /* Calculate IPv4 checksum */
 473 #define IPV6_CS                 (1 << 28) /* Calculate IPv6 checksum */
 474 };
 475
 476 struct r8152;
 477
 478 struct rx_agg {
 479         struct list_head list;
 480         struct urb *urb;
 481         struct r8152 *context;
 482         void *buffer;
 483         void *head;
 484 };
 485
 486 struct tx_agg {
 487         struct list_head list;
 488         struct urb *urb;
 489         struct r8152 *context;
 490         void *buffer;
 491         void *head;
 492         u32 skb_num;
 493         u32 skb_len;
 494 };
 495
 496 struct r8152 {
 497         unsigned long flags;
 498         struct usb_device *udev;
 499         struct tasklet_struct tl;
 500         struct usb_interface *intf;
 501         struct net_device *netdev;
 502         struct urb *intr_urb;
 503         struct tx_agg tx_info[RTL8152_MAX_TX];
 504         struct rx_agg rx_info[RTL8152_MAX_RX];
 505         struct list_head rx_done, tx_free;
 506         struct sk_buff_head tx_queue;
 507         spinlock_t rx_lock, tx_lock;
 508         struct delayed_work schedule;
 509         struct mii_if_info mii;
 510
 511         struct rtl_ops {
 512                 void (*init)(struct r8152 *);
 513                 int (*enable)(struct r8152 *);
 514                 void (*disable)(struct r8152 *);
 515                 void (*down)(struct r8152 *);
 516                 void (*unload)(struct r8152 *);
 517         } rtl_ops;
 518
 519         int intr_interval;
 520         u32 msg_enable;
 521         u32 tx_qlen;
 522         u16 ocp_base;
 523         u8 *intr_buff;
 524         u8 version;
 525         u8 speed;
 526 };
 527
 528 enum rtl_version {
 529         RTL_VER_UNKNOWN = 0,
 530         RTL_VER_01,
 531         RTL_VER_02,
 532         RTL_VER_03,
 533         RTL_VER_04,
 534         RTL_VER_05,
 535         RTL_VER_MAX
 536 };
 537
 538 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
 539  * The RTL chips use a 64 element hash table based on the Ethernet CRC.
 540  */
 541 static const int multicast_filter_limit = 32;
 542 static unsigned int rx_buf_sz = 16384;
 543
 544 static
 545 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
 546 {
 547         int ret;
 548         void *tmp;
 549
 550         tmp = kmalloc(size, GFP_KERNEL);
 551         if (!tmp)
 552                 return -ENOMEM;
 553
 554         ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
 555                                RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
 556                                value, index, tmp, size, 500);
 557
 558         memcpy(data, tmp, size);
 559         kfree(tmp);
 560
 561         return ret;
 562 }
 563
 564 static
 565 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
 566 {
 567         int ret;
 568         void *tmp;
 569
 570         tmp = kmalloc(size, GFP_KERNEL);
 571         if (!tmp)
 572                 return -ENOMEM;
 573
 574         memcpy(tmp, data, size);
 575
 576         ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
 577                                RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
 578                                value, index, tmp, size, 500);
 579
 580         kfree(tmp);
 581         return ret;
 582 }
 583
 584 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
 585                                 void *data, u16 type)
 586 {
 587         u16 limit = 64;
 588         int ret = 0;
 589
 590         if (test_bit(RTL8152_UNPLUG, &tp->flags))
 591                 return -ENODEV;
 592
 593         /* both size and indix must be 4 bytes align */
 594         if ((size & 3) || !size || (index & 3) || !data)
 595                 return -EPERM;
 596
 597         if ((u32)index + (u32)size > 0xffff)
 598                 return -EPERM;
 599
 600         while (size) {
 601                 if (size > limit) {
 602                         ret = get_registers(tp, index, type, limit, data);
 603                         if (ret < 0)
 604                                 break;
 605
 606                         index += limit;
 607                         data += limit;
 608                         size -= limit;
 609                 } else {
 610                         ret = get_registers(tp, index, type, size, data);
 611                         if (ret < 0)
 612                                 break;
 613
 614                         index += size;
 615                         data += size;
 616                         size = 0;
 617                         break;
 618                 }
 619         }
 620
 621         return ret;
 622 }
 623
 624 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
 625                                 u16 size, void *data, u16 type)
 626 {
 627         int ret;
 628         u16 byteen_start, byteen_end, byen;
 629         u16 limit = 512;
 630
 631         if (test_bit(RTL8152_UNPLUG, &tp->flags))
 632                 return -ENODEV;
 633
 634         /* both size and indix must be 4 bytes align */
 635         if ((size & 3) || !size || (index & 3) || !data)
 636                 return -EPERM;
 637
 638         if ((u32)index + (u32)size > 0xffff)
 639                 return -EPERM;
 640
 641         byteen_start = byteen & BYTE_EN_START_MASK;
 642         byteen_end = byteen & BYTE_EN_END_MASK;
 643
 644         byen = byteen_start | (byteen_start << 4);
 645         ret = set_registers(tp, index, type | byen, 4, data);
 646         if (ret < 0)
 647                 goto error1;
 648
 649         index += 4;
 650         data += 4;
 651         size -= 4;
 652
 653         if (size) {
 654                 size -= 4;
 655
 656                 while (size) {
 657                         if (size > limit) {
 658                                 ret = set_registers(tp, index,
 659                                         type | BYTE_EN_DWORD,
 660                                         limit, data);
 661                                 if (ret < 0)
 662                                         goto error1;
 663
 664                                 index += limit;
 665                                 data += limit;
 666                                 size -= limit;
 667                         } else {
 668                                 ret = set_registers(tp, index,
 669                                         type | BYTE_EN_DWORD,
 670                                         size, data);
 671                                 if (ret < 0)
 672                                         goto error1;
 673
 674                                 index += size;
 675                                 data += size;
 676                                 size = 0;
 677                                 break;
 678                         }
 679                 }
 680
 681                 byen = byteen_end | (byteen_end >> 4);
 682                 ret = set_registers(tp, index, type | byen, 4, data);
 683                 if (ret < 0)
 684                         goto error1;
 685         }
 686
 687 error1:
 688         return ret;
 689 }
 690
 691 static inline
 692 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
 693 {
 694         return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
 695 }
 696
 697 static inline
 698 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
 699 {
 700         return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
 701 }
 702
 703 static inline
 704 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
 705 {
 706         return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
 707 }
 708
 709 static inline
 710 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
 711 {
 712         return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
 713 }
 714
 715 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
 716 {
 717         __le32 data;
 718
 719         generic_ocp_read(tp, index, sizeof(data), &data, type);
 720
 721         return __le32_to_cpu(data);
 722 }
 723
 724 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
 725 {
 726         __le32 tmp = __cpu_to_le32(data);
 727
 728         generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
 729 }
 730
 731 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
 732 {
 733         u32 data;
 734         __le32 tmp;
 735         u8 shift = index & 2;
 736
 737         index &= ~3;
 738
 739         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
 740
 741         data = __le32_to_cpu(tmp);
 742         data >>= (shift * 8);
 743         data &= 0xffff;
 744
 745         return (u16)data;
 746 }
 747
 748 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
 749 {
 750         u32 mask = 0xffff;
 751         __le32 tmp;
 752         u16 byen = BYTE_EN_WORD;
 753         u8 shift = index & 2;
 754
 755         data &= mask;
 756
 757         if (index & 2) {
 758                 byen <<= shift;
 759                 mask <<= (shift * 8);
 760                 data <<= (shift * 8);
 761                 index &= ~3;
 762         }
 763
 764         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
 765
 766         data |= __le32_to_cpu(tmp) & ~mask;
 767         tmp = __cpu_to_le32(data);
 768
 769         generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
 770 }
 771
 772 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
 773 {
 774         u32 data;
 775         __le32 tmp;
 776         u8 shift = index & 3;
 777
 778         index &= ~3;
 779
 780         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
 781
 782         data = __le32_to_cpu(tmp);
 783         data >>= (shift * 8);
 784         data &= 0xff;
 785
 786         return (u8)data;
 787 }
 788
 789 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
 790 {
 791         u32 mask = 0xff;
 792         __le32 tmp;
 793         u16 byen = BYTE_EN_BYTE;
 794         u8 shift = index & 3;
 795
 796         data &= mask;
 797
 798         if (index & 3) {
 799                 byen <<= shift;
 800                 mask <<= (shift * 8);
 801                 data <<= (shift * 8);
 802                 index &= ~3;
 803         }
 804
 805         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
 806
 807         data |= __le32_to_cpu(tmp) & ~mask;
 808         tmp = __cpu_to_le32(data);
 809
 810         generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
 811 }
 812
 813 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
 814 {
 815         u16 ocp_base, ocp_index;
 816
 817         ocp_base = addr & 0xf000;
 818         if (ocp_base != tp->ocp_base) {
 819                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
 820                 tp->ocp_base = ocp_base;
 821         }
 822
 823         ocp_index = (addr & 0x0fff) | 0xb000;
 824         return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
 825 }
 826
 827 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
 828 {
 829         u16 ocp_base, ocp_index;
 830
 831         ocp_base = addr & 0xf000;
 832         if (ocp_base != tp->ocp_base) {
 833                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
 834                 tp->ocp_base = ocp_base;
 835         }
 836
 837         ocp_index = (addr & 0x0fff) | 0xb000;
 838         ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
 839 }
 840
 841 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
 842 {
 843         ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
 844 }
 845
 846 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
 847 {
 848         return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
 849 }
 850
 851 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
 852 {
 853         ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
 854         ocp_reg_write(tp, OCP_SRAM_DATA, data);
 855 }
 856
 857 static u16 sram_read(struct r8152 *tp, u16 addr)
 858 {
 859         ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
 860         return ocp_reg_read(tp, OCP_SRAM_DATA);
 861 }
 862
 863 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
 864 {
 865         struct r8152 *tp = netdev_priv(netdev);
 866
 867         if (phy_id != R8152_PHY_ID)
 868                 return -EINVAL;
 869
 870         return r8152_mdio_read(tp, reg);
 871 }
 872
 873 static
 874 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
 875 {
 876         struct r8152 *tp = netdev_priv(netdev);
 877
 878         if (phy_id != R8152_PHY_ID)
 879                 return;
 880
 881         r8152_mdio_write(tp, reg, val);
 882 }
 883
 884 static
 885 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
 886
 887 static inline void set_ethernet_addr(struct r8152 *tp)
 888 {
 889         struct net_device *dev = tp->netdev;
 890         u8 node_id[8] = {0};
 891
 892         if (pla_ocp_read(tp, PLA_IDR, sizeof(node_id), node_id) < 0)
 893                 netif_notice(tp, probe, dev, "inet addr fail\n");
 894         else {
 895                 memcpy(dev->dev_addr, node_id, dev->addr_len);
 896                 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
 897         }
 898 }
 899
 900 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
 901 {
 902         struct r8152 *tp = netdev_priv(netdev);
 903         struct sockaddr *addr = p;
 904
 905         if (!is_valid_ether_addr(addr->sa_data))
 906                 return -EADDRNOTAVAIL;
 907
 908         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
 909
 910         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
 911         pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
 912         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
 913
 914         return 0;
 915 }
 916
 917 static struct net_device_stats *rtl8152_get_stats(struct net_device *dev)
 918 {
 919         return &dev->stats;
 920 }
 921
 922 static void read_bulk_callback(struct urb *urb)
 923 {
 924         struct net_device *netdev;
 925         unsigned long flags;
 926         int status = urb->status;
 927         struct rx_agg *agg;
 928         struct r8152 *tp;
 929         int result;
 930
 931         agg = urb->context;
 932         if (!agg)
 933                 return;
 934
 935         tp = agg->context;
 936         if (!tp)
 937                 return;
 938
 939         if (test_bit(RTL8152_UNPLUG, &tp->flags))
 940                 return;
 941
 942         if (!test_bit(WORK_ENABLE, &tp->flags))
 943                 return;
 944
 945         netdev = tp->netdev;
 946
 947         /* When link down, the driver would cancel all bulks. */
 948         /* This avoid the re-submitting bulk */
 949         if (!netif_carrier_ok(netdev))
 950                 return;
 951
 952         switch (status) {
 953         case 0:
 954                 if (urb->actual_length < ETH_ZLEN)
 955                         break;
 956
 957                 spin_lock_irqsave(&tp->rx_lock, flags);
 958                 list_add_tail(&agg->list, &tp->rx_done);
 959                 spin_unlock_irqrestore(&tp->rx_lock, flags);
 960                 tasklet_schedule(&tp->tl);
 961                 return;
 962         case -ESHUTDOWN:
 963                 set_bit(RTL8152_UNPLUG, &tp->flags);
 964                 netif_device_detach(tp->netdev);
 965                 return;
 966         case -ENOENT:
 967                 return; /* the urb is in unlink state */
 968         case -ETIME:
 969                 if (net_ratelimit())
 970                         netdev_warn(netdev, "maybe reset is needed?\n");
 971                 break;
 972         default:
 973                 if (net_ratelimit())
 974                         netdev_warn(netdev, "Rx status %d\n", status);
 975                 break;
 976         }
 977
 978         result = r8152_submit_rx(tp, agg, GFP_ATOMIC);
 979         if (result == -ENODEV) {
 980                 netif_device_detach(tp->netdev);
 981         } else if (result) {
 982                 spin_lock_irqsave(&tp->rx_lock, flags);
 983                 list_add_tail(&agg->list, &tp->rx_done);
 984                 spin_unlock_irqrestore(&tp->rx_lock, flags);
 985                 tasklet_schedule(&tp->tl);
 986         }
 987 }
 988
 989 static void write_bulk_callback(struct urb *urb)
 990 {
 991         struct net_device_stats *stats;
 992         unsigned long flags;
 993         struct tx_agg *agg;
 994         struct r8152 *tp;
 995         int status = urb->status;
 996
 997         agg = urb->context;
 998         if (!agg)
 999                 return;
1000
1001         tp = agg->context;
1002         if (!tp)
1003                 return;
1004
1005         stats = rtl8152_get_stats(tp->netdev);
1006         if (status) {
1007                 if (net_ratelimit())
1008                         netdev_warn(tp->netdev, "Tx status %d\n", status);
1009                 stats->tx_errors += agg->skb_num;
1010         } else {
1011                 stats->tx_packets += agg->skb_num;
1012                 stats->tx_bytes += agg->skb_len;
1013         }
1014
1015         spin_lock_irqsave(&tp->tx_lock, flags);
1016         list_add_tail(&agg->list, &tp->tx_free);
1017         spin_unlock_irqrestore(&tp->tx_lock, flags);
1018
1019         if (!netif_carrier_ok(tp->netdev))
1020                 return;
1021
1022         if (!test_bit(WORK_ENABLE, &tp->flags))
1023                 return;
1024
1025         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1026                 return;
1027
1028         if (!skb_queue_empty(&tp->tx_queue))
1029                 tasklet_schedule(&tp->tl);
1030 }
1031
1032 static void intr_callback(struct urb *urb)
1033 {
1034         struct r8152 *tp;
1035         __le16 *d;
1036         int status = urb->status;
1037         int res;
1038
1039         tp = urb->context;
1040         if (!tp)
1041                 return;
1042
1043         if (!test_bit(WORK_ENABLE, &tp->flags))
1044                 return;
1045
1046         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1047                 return;
1048
1049         switch (status) {
1050         case 0:                 /* success */
1051                 break;
1052         case -ECONNRESET:       /* unlink */
1053         case -ESHUTDOWN:
1054                 netif_device_detach(tp->netdev);
1055         case -ENOENT:
1056                 return;
1057         case -EOVERFLOW:
1058                 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1059                 goto resubmit;
1060         /* -EPIPE:  should clear the halt */
1061         default:
1062                 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1063                 goto resubmit;
1064         }
1065
1066         d = urb->transfer_buffer;
1067         if (INTR_LINK & __le16_to_cpu(d[0])) {
1068                 if (!(tp->speed & LINK_STATUS)) {
1069                         set_bit(RTL8152_LINK_CHG, &tp->flags);
1070                         schedule_delayed_work(&tp->schedule, 0);
1071                 }
1072         } else {
1073                 if (tp->speed & LINK_STATUS) {
1074                         set_bit(RTL8152_LINK_CHG, &tp->flags);
1075                         schedule_delayed_work(&tp->schedule, 0);
1076                 }
1077         }
1078
1079 resubmit:
1080         res = usb_submit_urb(urb, GFP_ATOMIC);
1081         if (res == -ENODEV)
1082                 netif_device_detach(tp->netdev);
1083         else if (res)
1084                 netif_err(tp, intr, tp->netdev,
1085                           "can't resubmit intr, status %d\n", res);
1086 }
1087
1088 static inline void *rx_agg_align(void *data)
1089 {
1090         return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1091 }
1092
1093 static inline void *tx_agg_align(void *data)
1094 {
1095         return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1096 }
1097
1098 static void free_all_mem(struct r8152 *tp)
1099 {
1100         int i;
1101
1102         for (i = 0; i < RTL8152_MAX_RX; i++) {
1103                 if (tp->rx_info[i].urb) {
1104                         usb_free_urb(tp->rx_info[i].urb);
1105                         tp->rx_info[i].urb = NULL;
1106                 }
1107
1108                 if (tp->rx_info[i].buffer) {
1109                         kfree(tp->rx_info[i].buffer);
1110                         tp->rx_info[i].buffer = NULL;
1111                         tp->rx_info[i].head = NULL;
1112                 }
1113         }
1114
1115         for (i = 0; i < RTL8152_MAX_TX; i++) {
1116                 if (tp->tx_info[i].urb) {
1117                         usb_free_urb(tp->tx_info[i].urb);
1118                         tp->tx_info[i].urb = NULL;
1119                 }
1120
1121                 if (tp->tx_info[i].buffer) {
1122                         kfree(tp->tx_info[i].buffer);
1123                         tp->tx_info[i].buffer = NULL;
1124                         tp->tx_info[i].head = NULL;
1125                 }
1126         }
1127
1128         if (tp->intr_urb) {
1129                 usb_free_urb(tp->intr_urb);
1130                 tp->intr_urb = NULL;
1131         }
1132
1133         if (tp->intr_buff) {
1134                 kfree(tp->intr_buff);
1135                 tp->intr_buff = NULL;
1136         }
1137 }
1138
1139 static int alloc_all_mem(struct r8152 *tp)
1140 {
1141         struct net_device *netdev = tp->netdev;
1142         struct usb_interface *intf = tp->intf;
1143         struct usb_host_interface *alt = intf->cur_altsetting;
1144         struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1145         struct urb *urb;
1146         int node, i;
1147         u8 *buf;
1148
1149         node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1150
1151         spin_lock_init(&tp->rx_lock);
1152         spin_lock_init(&tp->tx_lock);
1153         INIT_LIST_HEAD(&tp->rx_done);
1154         INIT_LIST_HEAD(&tp->tx_free);
1155         skb_queue_head_init(&tp->tx_queue);
1156
1157         for (i = 0; i < RTL8152_MAX_RX; i++) {
1158                 buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
1159                 if (!buf)
1160                         goto err1;
1161
1162                 if (buf != rx_agg_align(buf)) {
1163                         kfree(buf);
1164                         buf = kmalloc_node(rx_buf_sz + RX_ALIGN, GFP_KERNEL,
1165                                            node);
1166                         if (!buf)
1167                                 goto err1;
1168                 }
1169
1170                 urb = usb_alloc_urb(0, GFP_KERNEL);
1171                 if (!urb) {
1172                         kfree(buf);
1173                         goto err1;
1174                 }
1175
1176                 INIT_LIST_HEAD(&tp->rx_info[i].list);
1177                 tp->rx_info[i].context = tp;
1178                 tp->rx_info[i].urb = urb;
1179                 tp->rx_info[i].buffer = buf;
1180                 tp->rx_info[i].head = rx_agg_align(buf);
1181         }
1182
1183         for (i = 0; i < RTL8152_MAX_TX; i++) {
1184                 buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
1185                 if (!buf)
1186                         goto err1;
1187
1188                 if (buf != tx_agg_align(buf)) {
1189                         kfree(buf);
1190                         buf = kmalloc_node(rx_buf_sz + TX_ALIGN, GFP_KERNEL,
1191                                            node);
1192                         if (!buf)
1193                                 goto err1;
1194                 }
1195
1196                 urb = usb_alloc_urb(0, GFP_KERNEL);
1197                 if (!urb) {
1198                         kfree(buf);
1199                         goto err1;
1200                 }
1201
1202                 INIT_LIST_HEAD(&tp->tx_info[i].list);
1203                 tp->tx_info[i].context = tp;
1204                 tp->tx_info[i].urb = urb;
1205                 tp->tx_info[i].buffer = buf;
1206                 tp->tx_info[i].head = tx_agg_align(buf);
1207
1208                 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1209         }
1210
1211         tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1212         if (!tp->intr_urb)
1213                 goto err1;
1214
1215         tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1216         if (!tp->intr_buff)
1217                 goto err1;
1218
1219         tp->intr_interval = (int)ep_intr->desc.bInterval;
1220         usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1221                      tp->intr_buff, INTBUFSIZE, intr_callback,
1222                      tp, tp->intr_interval);
1223
1224         return 0;
1225
1226 err1:
1227         free_all_mem(tp);
1228         return -ENOMEM;
1229 }
1230
1231 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1232 {
1233         struct tx_agg *agg = NULL;
1234         unsigned long flags;
1235
1236         spin_lock_irqsave(&tp->tx_lock, flags);
1237         if (!list_empty(&tp->tx_free)) {
1238                 struct list_head *cursor;
1239
1240                 cursor = tp->tx_free.next;
1241                 list_del_init(cursor);
1242                 agg = list_entry(cursor, struct tx_agg, list);
1243         }
1244         spin_unlock_irqrestore(&tp->tx_lock, flags);
1245
1246         return agg;
1247 }
1248
1249 static void
1250 r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, struct sk_buff *skb)
1251 {
1252         memset(desc, 0, sizeof(*desc));
1253
1254         desc->opts1 = cpu_to_le32((skb->len & TX_LEN_MASK) | TX_FS | TX_LS);
1255
1256         if (skb->ip_summed == CHECKSUM_PARTIAL) {
1257                 __be16 protocol;
1258                 u8 ip_protocol;
1259                 u32 opts2 = 0;
1260
1261                 if (skb->protocol == htons(ETH_P_8021Q))
1262                         protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
1263                 else
1264                         protocol = skb->protocol;
1265
1266                 switch (protocol) {
1267                 case htons(ETH_P_IP):
1268                         opts2 |= IPV4_CS;
1269                         ip_protocol = ip_hdr(skb)->protocol;
1270                         break;
1271
1272                 case htons(ETH_P_IPV6):
1273                         opts2 |= IPV6_CS;
1274                         ip_protocol = ipv6_hdr(skb)->nexthdr;
1275                         break;
1276
1277                 default:
1278                         ip_protocol = IPPROTO_RAW;
1279                         break;
1280                 }
1281
1282                 if (ip_protocol == IPPROTO_TCP) {
1283                         opts2 |= TCP_CS;
1284                         opts2 |= (skb_transport_offset(skb) & 0x7fff) << 17;
1285                 } else if (ip_protocol == IPPROTO_UDP) {
1286                         opts2 |= UDP_CS;
1287                 } else {
1288                         WARN_ON_ONCE(1);
1289                 }
1290
1291                 desc->opts2 = cpu_to_le32(opts2);
1292         }
1293 }
1294
1295 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1296 {
1297         int remain;
1298         u8 *tx_data;
1299
1300         tx_data = agg->head;
1301         agg->skb_num = agg->skb_len = 0;
1302         remain = rx_buf_sz;
1303
1304         while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
1305                 struct tx_desc *tx_desc;
1306                 struct sk_buff *skb;
1307                 unsigned int len;
1308
1309                 skb = skb_dequeue(&tp->tx_queue);
1310                 if (!skb)
1311                         break;
1312
1313                 remain -= sizeof(*tx_desc);
1314                 len = skb->len;
1315                 if (remain < len) {
1316                         skb_queue_head(&tp->tx_queue, skb);
1317                         break;
1318                 }
1319
1320                 tx_data = tx_agg_align(tx_data);
1321                 tx_desc = (struct tx_desc *)tx_data;
1322                 tx_data += sizeof(*tx_desc);
1323
1324                 r8152_tx_csum(tp, tx_desc, skb);
1325                 memcpy(tx_data, skb->data, len);
1326                 agg->skb_num++;
1327                 agg->skb_len += len;
1328                 dev_kfree_skb_any(skb);
1329
1330                 tx_data += len;
1331                 remain = rx_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
1332         }
1333
1334         netif_tx_lock(tp->netdev);
1335
1336         if (netif_queue_stopped(tp->netdev) &&
1337             skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1338                 netif_wake_queue(tp->netdev);
1339
1340         netif_tx_unlock(tp->netdev);
1341
1342         usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1343                           agg->head, (int)(tx_data - (u8 *)agg->head),
1344                           (usb_complete_t)write_bulk_callback, agg);
1345
1346         return usb_submit_urb(agg->urb, GFP_ATOMIC);
1347 }
1348
1349 static void rx_bottom(struct r8152 *tp)
1350 {
1351         unsigned long flags;
1352         struct list_head *cursor, *next;
1353
1354         spin_lock_irqsave(&tp->rx_lock, flags);
1355         list_for_each_safe(cursor, next, &tp->rx_done) {
1356                 struct rx_desc *rx_desc;
1357                 struct rx_agg *agg;
1358                 int len_used = 0;
1359                 struct urb *urb;
1360                 u8 *rx_data;
1361                 int ret;
1362
1363                 list_del_init(cursor);
1364                 spin_unlock_irqrestore(&tp->rx_lock, flags);
1365
1366                 agg = list_entry(cursor, struct rx_agg, list);
1367                 urb = agg->urb;
1368                 if (urb->actual_length < ETH_ZLEN)
1369                         goto submit;
1370
1371                 rx_desc = agg->head;
1372                 rx_data = agg->head;
1373                 len_used += sizeof(struct rx_desc);
1374
1375                 while (urb->actual_length > len_used) {
1376                         struct net_device *netdev = tp->netdev;
1377                         struct net_device_stats *stats;
1378                         unsigned int pkt_len;
1379                         struct sk_buff *skb;
1380
1381                         pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1382                         if (pkt_len < ETH_ZLEN)
1383                                 break;
1384
1385                         len_used += pkt_len;
1386                         if (urb->actual_length < len_used)
1387                                 break;
1388
1389                         stats = rtl8152_get_stats(netdev);
1390
1391                         pkt_len -= CRC_SIZE;
1392                         rx_data += sizeof(struct rx_desc);
1393
1394                         skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
1395                         if (!skb) {
1396                                 stats->rx_dropped++;
1397                                 break;
1398                         }
1399                         memcpy(skb->data, rx_data, pkt_len);
1400                         skb_put(skb, pkt_len);
1401                         skb->protocol = eth_type_trans(skb, netdev);
1402                         netif_rx(skb);
1403                         stats->rx_packets++;
1404                         stats->rx_bytes += pkt_len;
1405
1406                         rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
1407                         rx_desc = (struct rx_desc *)rx_data;
1408                         len_used = (int)(rx_data - (u8 *)agg->head);
1409                         len_used += sizeof(struct rx_desc);
1410                 }
1411
1412 submit:
1413                 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1414                 spin_lock_irqsave(&tp->rx_lock, flags);
1415                 if (ret && ret != -ENODEV) {
1416                         list_add_tail(&agg->list, next);
1417                         tasklet_schedule(&tp->tl);
1418                 }
1419         }
1420         spin_unlock_irqrestore(&tp->rx_lock, flags);
1421 }
1422
1423 static void tx_bottom(struct r8152 *tp)
1424 {
1425         int res;
1426
1427         do {
1428                 struct tx_agg *agg;
1429
1430                 if (skb_queue_empty(&tp->tx_queue))
1431                         break;
1432
1433                 agg = r8152_get_tx_agg(tp);
1434                 if (!agg)
1435                         break;
1436
1437                 res = r8152_tx_agg_fill(tp, agg);
1438                 if (res) {
1439                         struct net_device_stats *stats;
1440                         struct net_device *netdev;
1441                         unsigned long flags;
1442
1443                         netdev = tp->netdev;
1444                         stats = rtl8152_get_stats(netdev);
1445
1446                         if (res == -ENODEV) {
1447                                 netif_device_detach(netdev);
1448                         } else {
1449                                 netif_warn(tp, tx_err, netdev,
1450                                            "failed tx_urb %d\n", res);
1451                                 stats->tx_dropped += agg->skb_num;
1452                                 spin_lock_irqsave(&tp->tx_lock, flags);
1453                                 list_add_tail(&agg->list, &tp->tx_free);
1454                                 spin_unlock_irqrestore(&tp->tx_lock, flags);
1455                         }
1456                 }
1457         } while (res == 0);
1458 }
1459
1460 static void bottom_half(unsigned long data)
1461 {
1462         struct r8152 *tp;
1463
1464         tp = (struct r8152 *)data;
1465
1466         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1467                 return;
1468
1469         if (!test_bit(WORK_ENABLE, &tp->flags))
1470                 return;
1471
1472         /* When link down, the driver would cancel all bulks. */
1473         /* This avoid the re-submitting bulk */
1474         if (!netif_carrier_ok(tp->netdev))
1475                 return;
1476
1477         rx_bottom(tp);
1478         tx_bottom(tp);
1479 }
1480
1481 static
1482 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
1483 {
1484         usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
1485                       agg->head, rx_buf_sz,
1486                       (usb_complete_t)read_bulk_callback, agg);
1487
1488         return usb_submit_urb(agg->urb, mem_flags);
1489 }
1490
1491 static void rtl8152_tx_timeout(struct net_device *netdev)
1492 {
1493         struct r8152 *tp = netdev_priv(netdev);
1494         int i;
1495
1496         netif_warn(tp, tx_err, netdev, "Tx timeout\n");
1497         for (i = 0; i < RTL8152_MAX_TX; i++)
1498                 usb_unlink_urb(tp->tx_info[i].urb);
1499 }
1500
1501 static void rtl8152_set_rx_mode(struct net_device *netdev)
1502 {
1503         struct r8152 *tp = netdev_priv(netdev);
1504
1505         if (tp->speed & LINK_STATUS) {
1506                 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
1507                 schedule_delayed_work(&tp->schedule, 0);
1508         }
1509 }
1510
1511 static void _rtl8152_set_rx_mode(struct net_device *netdev)
1512 {
1513         struct r8152 *tp = netdev_priv(netdev);
1514         u32 mc_filter[2];       /* Multicast hash filter */
1515         __le32 tmp[2];
1516         u32 ocp_data;
1517
1518         clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
1519         netif_stop_queue(netdev);
1520         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1521         ocp_data &= ~RCR_ACPT_ALL;
1522         ocp_data |= RCR_AB | RCR_APM;
1523
1524         if (netdev->flags & IFF_PROMISC) {
1525                 /* Unconditionally log net taps. */
1526                 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
1527                 ocp_data |= RCR_AM | RCR_AAP;
1528                 mc_filter[1] = mc_filter[0] = 0xffffffff;
1529         } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
1530                    (netdev->flags & IFF_ALLMULTI)) {
1531                 /* Too many to filter perfectly -- accept all multicasts. */
1532                 ocp_data |= RCR_AM;
1533                 mc_filter[1] = mc_filter[0] = 0xffffffff;
1534         } else {
1535                 struct netdev_hw_addr *ha;
1536
1537                 mc_filter[1] = mc_filter[0] = 0;
1538                 netdev_for_each_mc_addr(ha, netdev) {
1539                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1540                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1541                         ocp_data |= RCR_AM;
1542                 }
1543         }
1544
1545         tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
1546         tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
1547
1548         pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
1549         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1550         netif_wake_queue(netdev);
1551 }
1552
1553 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
1554                                             struct net_device *netdev)
1555 {
1556         struct r8152 *tp = netdev_priv(netdev);
1557
1558         skb_tx_timestamp(skb);
1559
1560         skb_queue_tail(&tp->tx_queue, skb);
1561
1562         if (list_empty(&tp->tx_free) &&
1563             skb_queue_len(&tp->tx_queue) > tp->tx_qlen)
1564                 netif_stop_queue(netdev);
1565
1566         if (!list_empty(&tp->tx_free))
1567                 tasklet_schedule(&tp->tl);
1568
1569         return NETDEV_TX_OK;
1570 }
1571
1572 static void r8152b_reset_packet_filter(struct r8152 *tp)
1573 {
1574         u32     ocp_data;
1575
1576         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
1577         ocp_data &= ~FMC_FCR_MCU_EN;
1578         ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1579         ocp_data |= FMC_FCR_MCU_EN;
1580         ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1581 }
1582
1583 static void rtl8152_nic_reset(struct r8152 *tp)
1584 {
1585         int     i;
1586
1587         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
1588
1589         for (i = 0; i < 1000; i++) {
1590                 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
1591                         break;
1592                 udelay(100);
1593         }
1594 }
1595
1596 static void set_tx_qlen(struct r8152 *tp)
1597 {
1598         struct net_device *netdev = tp->netdev;
1599
1600         tp->tx_qlen = rx_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
1601                                    sizeof(struct tx_desc));
1602 }
1603
1604 static inline u8 rtl8152_get_speed(struct r8152 *tp)
1605 {
1606         return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
1607 }
1608
1609 static void rtl_set_eee_plus(struct r8152 *tp)
1610 {
1611         u32 ocp_data;
1612         u8 speed;
1613
1614         speed = rtl8152_get_speed(tp);
1615         if (speed & _10bps) {
1616                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
1617                 ocp_data |= EEEP_CR_EEEP_TX;
1618                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1619         } else {
1620                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
1621                 ocp_data &= ~EEEP_CR_EEEP_TX;
1622                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1623         }
1624 }
1625
1626 static int rtl_enable(struct r8152 *tp)
1627 {
1628         u32 ocp_data;
1629         int i, ret;
1630
1631         r8152b_reset_packet_filter(tp);
1632
1633         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
1634         ocp_data |= CR_RE | CR_TE;
1635         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
1636
1637         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1638         ocp_data &= ~RXDY_GATED_EN;
1639         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1640
1641         INIT_LIST_HEAD(&tp->rx_done);
1642         ret = 0;
1643         for (i = 0; i < RTL8152_MAX_RX; i++) {
1644                 INIT_LIST_HEAD(&tp->rx_info[i].list);
1645                 ret |= r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
1646         }
1647
1648         return ret;
1649 }
1650
1651 static int rtl8152_enable(struct r8152 *tp)
1652 {
1653         set_tx_qlen(tp);
1654         rtl_set_eee_plus(tp);
1655
1656         return rtl_enable(tp);
1657 }
1658
1659 static void r8153_set_rx_agg(struct r8152 *tp)
1660 {
1661         u8 speed;
1662
1663         speed = rtl8152_get_speed(tp);
1664         if (speed & _1000bps) {
1665                 if (tp->udev->speed == USB_SPEED_SUPER) {
1666                         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
1667                                         RX_THR_SUPPER);
1668                         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
1669                                         EARLY_AGG_SUPPER);
1670                 } else {
1671                         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
1672                                         RX_THR_HIGH);
1673                         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
1674                                         EARLY_AGG_HIGH);
1675                 }
1676         } else {
1677                 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW);
1678                 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
1679                                 EARLY_AGG_SLOW);
1680         }
1681 }
1682
1683 static int rtl8153_enable(struct r8152 *tp)
1684 {
1685         set_tx_qlen(tp);
1686         rtl_set_eee_plus(tp);
1687         r8153_set_rx_agg(tp);
1688
1689         return rtl_enable(tp);
1690 }
1691
1692 static void rtl8152_disable(struct r8152 *tp)
1693 {
1694         struct net_device_stats *stats = rtl8152_get_stats(tp->netdev);
1695         struct sk_buff *skb;
1696         u32 ocp_data;
1697         int i;
1698
1699         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1700         ocp_data &= ~RCR_ACPT_ALL;
1701         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1702
1703         while ((skb = skb_dequeue(&tp->tx_queue))) {
1704                 dev_kfree_skb(skb);
1705                 stats->tx_dropped++;
1706         }
1707
1708         for (i = 0; i < RTL8152_MAX_TX; i++)
1709                 usb_kill_urb(tp->tx_info[i].urb);
1710
1711         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1712         ocp_data |= RXDY_GATED_EN;
1713         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1714
1715         for (i = 0; i < 1000; i++) {
1716                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1717                 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
1718                         break;
1719                 mdelay(1);
1720         }
1721
1722         for (i = 0; i < 1000; i++) {
1723                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
1724                         break;
1725                 mdelay(1);
1726         }
1727
1728         for (i = 0; i < RTL8152_MAX_RX; i++)
1729                 usb_kill_urb(tp->rx_info[i].urb);
1730
1731         rtl8152_nic_reset(tp);
1732 }
1733
1734 static void r8152b_exit_oob(struct r8152 *tp)
1735 {
1736         u32     ocp_data;
1737         int     i;
1738
1739         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1740         ocp_data &= ~RCR_ACPT_ALL;
1741         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1742
1743         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1744         ocp_data |= RXDY_GATED_EN;
1745         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1746
1747         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1748         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
1749
1750         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1751         ocp_data &= ~NOW_IS_OOB;
1752         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
1753
1754         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
1755         ocp_data &= ~MCU_BORW_EN;
1756         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
1757
1758         for (i = 0; i < 1000; i++) {
1759                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1760                 if (ocp_data & LINK_LIST_READY)
1761                         break;
1762                 mdelay(1);
1763         }
1764
1765         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
1766         ocp_data |= RE_INIT_LL;
1767         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
1768
1769         for (i = 0; i < 1000; i++) {
1770                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1771                 if (ocp_data & LINK_LIST_READY)
1772                         break;
1773                 mdelay(1);
1774         }
1775
1776         rtl8152_nic_reset(tp);
1777
1778         /* rx share fifo credit full threshold */
1779         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
1780
1781         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_DEV_STAT);
1782         ocp_data &= STAT_SPEED_MASK;
1783         if (ocp_data == STAT_SPEED_FULL) {
1784                 /* rx share fifo credit near full threshold */
1785                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
1786                                 RXFIFO_THR2_FULL);
1787                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
1788                                 RXFIFO_THR3_FULL);
1789         } else {
1790                 /* rx share fifo credit near full threshold */
1791                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
1792                                 RXFIFO_THR2_HIGH);
1793                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
1794                                 RXFIFO_THR3_HIGH);
1795         }
1796
1797         /* TX share fifo free credit full threshold */
1798         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
1799
1800         ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
1801         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
1802         ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
1803                         TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
1804
1805         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
1806         ocp_data &= ~CPCR_RX_VLAN;
1807         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
1808
1809         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
1810
1811         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
1812         ocp_data |= TCR0_AUTO_FIFO;
1813         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
1814 }
1815
1816 static void r8152b_enter_oob(struct r8152 *tp)
1817 {
1818         u32 ocp_data;
1819         int i;
1820
1821         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1822         ocp_data &= ~NOW_IS_OOB;
1823         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
1824
1825         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
1826         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
1827         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
1828
1829         rtl8152_disable(tp);
1830
1831         for (i = 0; i < 1000; i++) {
1832                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1833                 if (ocp_data & LINK_LIST_READY)
1834                         break;
1835                 mdelay(1);
1836         }
1837
1838         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
1839         ocp_data |= RE_INIT_LL;
1840         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
1841
1842         for (i = 0; i < 1000; i++) {
1843                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1844                 if (ocp_data & LINK_LIST_READY)
1845                         break;
1846                 mdelay(1);
1847         }
1848
1849         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
1850
1851         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
1852         ocp_data |= MAGIC_EN;
1853         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
1854
1855         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
1856         ocp_data |= CPCR_RX_VLAN;
1857         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
1858
1859         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
1860         ocp_data |= ALDPS_PROXY_MODE;
1861         ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
1862
1863         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1864         ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
1865         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
1866
1867         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5, LAN_WAKE_EN);
1868
1869         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1870         ocp_data &= ~RXDY_GATED_EN;
1871         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1872
1873         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1874         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
1875         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1876 }
1877
1878 static void r8152b_disable_aldps(struct r8152 *tp)
1879 {
1880         ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
1881         msleep(20);
1882 }
1883
1884 static inline void r8152b_enable_aldps(struct r8152 *tp)
1885 {
1886         ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
1887                                             LINKENA | DIS_SDSAVE);
1888 }
1889
1890 static void r8153_hw_phy_cfg(struct r8152 *tp)
1891 {
1892         u32 ocp_data;
1893         u16 data;
1894
1895         ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
1896         r8152_mdio_write(tp, MII_BMCR, BMCR_ANENABLE);
1897
1898         if (tp->version == RTL_VER_03) {
1899                 data = ocp_reg_read(tp, OCP_EEE_CFG);
1900                 data &= ~CTAP_SHORT_EN;
1901                 ocp_reg_write(tp, OCP_EEE_CFG, data);
1902         }
1903
1904         data = ocp_reg_read(tp, OCP_POWER_CFG);
1905         data |= EEE_CLKDIV_EN;
1906         ocp_reg_write(tp, OCP_POWER_CFG, data);
1907
1908         data = ocp_reg_read(tp, OCP_DOWN_SPEED);
1909         data |= EN_10M_BGOFF;
1910         ocp_reg_write(tp, OCP_DOWN_SPEED, data);
1911         data = ocp_reg_read(tp, OCP_POWER_CFG);
1912         data |= EN_10M_PLLOFF;
1913         ocp_reg_write(tp, OCP_POWER_CFG, data);
1914         data = sram_read(tp, SRAM_IMPEDANCE);
1915         data &= ~RX_DRIVING_MASK;
1916         sram_write(tp, SRAM_IMPEDANCE, data);
1917
1918         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
1919         ocp_data |= PFM_PWM_SWITCH;
1920         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
1921
1922         data = sram_read(tp, SRAM_LPF_CFG);
1923         data |= LPF_AUTO_TUNE;
1924         sram_write(tp, SRAM_LPF_CFG, data);
1925
1926         data = sram_read(tp, SRAM_10M_AMP1);
1927         data |= GDAC_IB_UPALL;
1928         sram_write(tp, SRAM_10M_AMP1, data);
1929         data = sram_read(tp, SRAM_10M_AMP2);
1930         data |= AMP_DN;
1931         sram_write(tp, SRAM_10M_AMP2, data);
1932 }
1933
1934 static void r8153_u1u2en(struct r8152 *tp, int enable)
1935 {
1936         u8 u1u2[8];
1937
1938         if (enable)
1939                 memset(u1u2, 0xff, sizeof(u1u2));
1940         else
1941                 memset(u1u2, 0x00, sizeof(u1u2));
1942
1943         usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
1944 }
1945
1946 static void r8153_u2p3en(struct r8152 *tp, int enable)
1947 {
1948         u32 ocp_data;
1949
1950         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
1951         if (enable)
1952                 ocp_data |= U2P3_ENABLE;
1953         else
1954                 ocp_data &= ~U2P3_ENABLE;
1955         ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
1956 }
1957
1958 static void r8153_power_cut_en(struct r8152 *tp, int enable)
1959 {
1960         u32 ocp_data;
1961
1962         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
1963         if (enable)
1964                 ocp_data |= PWR_EN | PHASE2_EN;
1965         else
1966                 ocp_data &= ~(PWR_EN | PHASE2_EN);
1967         ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
1968
1969         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1970         ocp_data &= ~PCUT_STATUS;
1971         ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
1972 }
1973
1974 static void r8153_teredo_off(struct r8152 *tp)
1975 {
1976         u32 ocp_data;
1977
1978         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
1979         ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
1980         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
1981
1982         ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
1983         ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
1984         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
1985 }
1986
1987 static void r8153_first_init(struct r8152 *tp)
1988 {
1989         u32 ocp_data;
1990         int i;
1991
1992         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1993         ocp_data |= RXDY_GATED_EN;
1994         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1995
1996         r8153_teredo_off(tp);
1997
1998         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1999         ocp_data &= ~RCR_ACPT_ALL;
2000         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2001
2002         r8153_hw_phy_cfg(tp);
2003
2004         rtl8152_nic_reset(tp);
2005
2006         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2007         ocp_data &= ~NOW_IS_OOB;
2008         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2009
2010         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2011         ocp_data &= ~MCU_BORW_EN;
2012         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2013
2014         for (i = 0; i < 1000; i++) {
2015                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2016                 if (ocp_data & LINK_LIST_READY)
2017                         break;
2018                 mdelay(1);
2019         }
2020
2021         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2022         ocp_data |= RE_INIT_LL;
2023         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2024
2025         for (i = 0; i < 1000; i++) {
2026                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2027                 if (ocp_data & LINK_LIST_READY)
2028                         break;
2029                 mdelay(1);
2030         }
2031
2032         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2033         ocp_data &= ~CPCR_RX_VLAN;
2034         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2035
2036         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2037
2038         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2039         ocp_data |= TCR0_AUTO_FIFO;
2040         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2041
2042         rtl8152_nic_reset(tp);
2043
2044         /* rx share fifo credit full threshold */
2045         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2046         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
2047         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
2048         /* TX share fifo free credit full threshold */
2049         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
2050
2051         // rx aggregation
2052         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2053         ocp_data &= ~RX_AGG_DISABLE;
2054         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2055 }
2056
2057 static void r8153_enter_oob(struct r8152 *tp)
2058 {
2059         u32 ocp_data;
2060         int i;
2061
2062         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2063         ocp_data &= ~NOW_IS_OOB;
2064         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2065
2066         rtl8152_disable(tp);
2067
2068         for (i = 0; i < 1000; i++) {
2069                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2070                 if (ocp_data & LINK_LIST_READY)
2071                         break;
2072                 mdelay(1);
2073         }
2074
2075         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2076         ocp_data |= RE_INIT_LL;
2077         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2078
2079         for (i = 0; i < 1000; i++) {
2080                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2081                 if (ocp_data & LINK_LIST_READY)
2082                         break;
2083                 mdelay(1);
2084         }
2085
2086         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2087
2088         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2089         ocp_data |= MAGIC_EN;
2090         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2091
2092         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2093         ocp_data &= ~TEREDO_WAKE_MASK;
2094         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2095
2096         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2097         ocp_data |= CPCR_RX_VLAN;
2098         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2099
2100         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2101         ocp_data |= ALDPS_PROXY_MODE;
2102         ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2103
2104         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2105         ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2106         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2107
2108         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5, LAN_WAKE_EN);
2109
2110         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2111         ocp_data &= ~RXDY_GATED_EN;
2112         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2113
2114         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2115         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2116         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2117 }
2118
2119 static void r8153_disable_aldps(struct r8152 *tp)
2120 {
2121         u16 data;
2122
2123         data = ocp_reg_read(tp, OCP_POWER_CFG);
2124         data &= ~EN_ALDPS;
2125         ocp_reg_write(tp, OCP_POWER_CFG, data);
2126         msleep(20);
2127 }
2128
2129 static void r8153_enable_aldps(struct r8152 *tp)
2130 {
2131         u16 data;
2132
2133         data = ocp_reg_read(tp, OCP_POWER_CFG);
2134         data |= EN_ALDPS;
2135         ocp_reg_write(tp, OCP_POWER_CFG, data);
2136 }
2137
2138 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
2139 {
2140         u16 bmcr, anar, gbcr;
2141         int ret = 0;
2142
2143         cancel_delayed_work_sync(&tp->schedule);
2144         anar = r8152_mdio_read(tp, MII_ADVERTISE);
2145         anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
2146                   ADVERTISE_100HALF | ADVERTISE_100FULL);
2147         if (tp->mii.supports_gmii) {
2148                 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
2149                 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
2150         } else {
2151                 gbcr = 0;
2152         }
2153
2154         if (autoneg == AUTONEG_DISABLE) {
2155                 if (speed == SPEED_10) {
2156                         bmcr = 0;
2157                         anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2158                 } else if (speed == SPEED_100) {
2159                         bmcr = BMCR_SPEED100;
2160                         anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2161                 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2162                         bmcr = BMCR_SPEED1000;
2163                         gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2164                 } else {
2165                         ret = -EINVAL;
2166                         goto out;
2167                 }
2168
2169                 if (duplex == DUPLEX_FULL)
2170                         bmcr |= BMCR_FULLDPLX;
2171         } else {
2172                 if (speed == SPEED_10) {
2173                         if (duplex == DUPLEX_FULL)
2174                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2175                         else
2176                                 anar |= ADVERTISE_10HALF;
2177                 } else if (speed == SPEED_100) {
2178                         if (duplex == DUPLEX_FULL) {
2179                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2180                                 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2181                         } else {
2182                                 anar |= ADVERTISE_10HALF;
2183                                 anar |= ADVERTISE_100HALF;
2184                         }
2185                 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2186                         if (duplex == DUPLEX_FULL) {
2187                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2188                                 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2189                                 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2190                         } else {
2191                                 anar |= ADVERTISE_10HALF;
2192                                 anar |= ADVERTISE_100HALF;
2193                                 gbcr |= ADVERTISE_1000HALF;
2194                         }
2195                 } else {
2196                         ret = -EINVAL;
2197                         goto out;
2198                 }
2199
2200                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
2201         }
2202
2203         if (tp->mii.supports_gmii)
2204                 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
2205
2206         r8152_mdio_write(tp, MII_ADVERTISE, anar);
2207         r8152_mdio_write(tp, MII_BMCR, bmcr);
2208
2209 out:
2210
2211         return ret;
2212 }
2213
2214 static void rtl8152_down(struct r8152 *tp)
2215 {
2216         u32     ocp_data;
2217
2218         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2219         ocp_data &= ~POWER_CUT;
2220         ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2221
2222         r8152b_disable_aldps(tp);
2223         r8152b_enter_oob(tp);
2224         r8152b_enable_aldps(tp);
2225 }
2226
2227 static void rtl8153_down(struct r8152 *tp)
2228 {
2229         r8153_u1u2en(tp, 0);
2230         r8153_power_cut_en(tp, 0);
2231         r8153_disable_aldps(tp);
2232         r8153_enter_oob(tp);
2233         r8153_enable_aldps(tp);
2234 }
2235
2236 static void set_carrier(struct r8152 *tp)
2237 {
2238         struct net_device *netdev = tp->netdev;
2239         u8 speed;
2240
2241         clear_bit(RTL8152_LINK_CHG, &tp->flags);
2242         speed = rtl8152_get_speed(tp);
2243
2244         if (speed & LINK_STATUS) {
2245                 if (!(tp->speed & LINK_STATUS)) {
2246                         tp->rtl_ops.enable(tp);
2247                         set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2248                         netif_carrier_on(netdev);
2249                 }
2250         } else {
2251                 if (tp->speed & LINK_STATUS) {
2252                         netif_carrier_off(netdev);
2253                         tasklet_disable(&tp->tl);
2254                         tp->rtl_ops.disable(tp);
2255                         tasklet_enable(&tp->tl);
2256                 }
2257         }
2258         tp->speed = speed;
2259 }
2260
2261 static void rtl_work_func_t(struct work_struct *work)
2262 {
2263         struct r8152 *tp = container_of(work, struct r8152, schedule.work);
2264
2265         if (!test_bit(WORK_ENABLE, &tp->flags))
2266                 goto out1;
2267
2268         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2269                 goto out1;
2270
2271         if (test_bit(RTL8152_LINK_CHG, &tp->flags))
2272                 set_carrier(tp);
2273
2274         if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
2275                 _rtl8152_set_rx_mode(tp->netdev);
2276
2277 out1:
2278         return;
2279 }
2280
2281 static int rtl8152_open(struct net_device *netdev)
2282 {
2283         struct r8152 *tp = netdev_priv(netdev);
2284         int res = 0;
2285
2286         res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
2287         if (res) {
2288                 if (res == -ENODEV)
2289                         netif_device_detach(tp->netdev);
2290                 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
2291                            res);
2292                 return res;
2293         }
2294
2295         rtl8152_set_speed(tp, AUTONEG_ENABLE,
2296                           tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
2297                           DUPLEX_FULL);
2298         tp->speed = 0;
2299         netif_carrier_off(netdev);
2300         netif_start_queue(netdev);
2301         set_bit(WORK_ENABLE, &tp->flags);
2302
2303         return res;
2304 }
2305
2306 static int rtl8152_close(struct net_device *netdev)
2307 {
2308         struct r8152 *tp = netdev_priv(netdev);
2309         int res = 0;
2310
2311         usb_kill_urb(tp->intr_urb);
2312         clear_bit(WORK_ENABLE, &tp->flags);
2313         cancel_delayed_work_sync(&tp->schedule);
2314         netif_stop_queue(netdev);
2315         tasklet_disable(&tp->tl);
2316         tp->rtl_ops.disable(tp);
2317         tasklet_enable(&tp->tl);
2318
2319         return res;
2320 }
2321
2322 static void rtl_clear_bp(struct r8152 *tp)
2323 {
2324         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0);
2325         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_2, 0);
2326         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_4, 0);
2327         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_6, 0);
2328         ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_0, 0);
2329         ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_2, 0);
2330         ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_4, 0);
2331         ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_6, 0);
2332         mdelay(3);
2333         ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_BA, 0);
2334         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_BA, 0);
2335 }
2336
2337 static void r8153_clear_bp(struct r8152 *tp)
2338 {
2339         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0);
2340         ocp_write_byte(tp, MCU_TYPE_USB, USB_BP_EN, 0);
2341         rtl_clear_bp(tp);
2342 }
2343
2344 static void r8152b_enable_eee(struct r8152 *tp)
2345 {
2346         u32 ocp_data;
2347
2348         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2349         ocp_data |= EEE_RX_EN | EEE_TX_EN;
2350         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
2351         ocp_reg_write(tp, OCP_EEE_CONFIG1, RG_TXLPI_MSK_HFDUP | RG_MATCLR_EN |
2352                                            EEE_10_CAP | EEE_NWAY_EN |
2353                                            TX_QUIET_EN | RX_QUIET_EN |
2354                                            SDRISETIME | RG_RXLPI_MSK_HFDUP |
2355                                            SDFALLTIME);
2356         ocp_reg_write(tp, OCP_EEE_CONFIG2, RG_LPIHYS_NUM | RG_DACQUIET_EN |
2357                                            RG_LDVQUIET_EN | RG_CKRSEL |
2358                                            RG_EEEPRG_EN);
2359         ocp_reg_write(tp, OCP_EEE_CONFIG3, FST_SNR_EYE_R | RG_LFS_SEL | MSK_PH);
2360         ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | DEVICE_ADDR);
2361         ocp_reg_write(tp, OCP_EEE_DATA, EEE_ADDR);
2362         ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | DEVICE_ADDR);
2363         ocp_reg_write(tp, OCP_EEE_DATA, EEE_DATA);
2364         ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2365 }
2366
2367 static void r8153_enable_eee(struct r8152 *tp)
2368 {
2369         u32 ocp_data;
2370         u16 data;
2371
2372         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2373         ocp_data |= EEE_RX_EN | EEE_TX_EN;
2374         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
2375         data = ocp_reg_read(tp, OCP_EEE_CFG);
2376         data |= EEE10_EN;
2377         ocp_reg_write(tp, OCP_EEE_CFG, data);
2378         data = ocp_reg_read(tp, OCP_EEE_CFG2);
2379         data |= MY1000_EEE | MY100_EEE;
2380         ocp_reg_write(tp, OCP_EEE_CFG2, data);
2381 }
2382
2383 static void r8152b_enable_fc(struct r8152 *tp)
2384 {
2385         u16 anar;
2386
2387         anar = r8152_mdio_read(tp, MII_ADVERTISE);
2388         anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
2389         r8152_mdio_write(tp, MII_ADVERTISE, anar);
2390 }
2391
2392 static void r8152b_hw_phy_cfg(struct r8152 *tp)
2393 {
2394         r8152_mdio_write(tp, MII_BMCR, BMCR_ANENABLE);
2395         r8152b_disable_aldps(tp);
2396 }
2397
2398 static void r8152b_init(struct r8152 *tp)
2399 {
2400         u32 ocp_data;
2401         int i;
2402
2403         rtl_clear_bp(tp);
2404
2405         if (tp->version == RTL_VER_01) {
2406                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
2407                 ocp_data &= ~LED_MODE_MASK;
2408                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
2409         }
2410
2411         r8152b_hw_phy_cfg(tp);
2412
2413         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2414         ocp_data &= ~POWER_CUT;
2415         ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2416
2417         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2418         ocp_data &= ~RESUME_INDICATE;
2419         ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2420
2421         r8152b_exit_oob(tp);
2422
2423         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2424         ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
2425         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2426         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
2427         ocp_data &= ~MCU_CLK_RATIO_MASK;
2428         ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
2429         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
2430         ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
2431                    SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
2432         ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
2433
2434         r8152b_enable_eee(tp);
2435         r8152b_enable_aldps(tp);
2436         r8152b_enable_fc(tp);
2437
2438         r8152_mdio_write(tp, MII_BMCR, BMCR_RESET | BMCR_ANENABLE |
2439                                        BMCR_ANRESTART);
2440         for (i = 0; i < 100; i++) {
2441                 udelay(100);
2442                 if (!(r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET))
2443                         break;
2444         }
2445
2446         /* enable rx aggregation */
2447         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2448         ocp_data &= ~RX_AGG_DISABLE;
2449         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2450 }
2451
2452 static void r8153_init(struct r8152 *tp)
2453 {
2454         u32 ocp_data;
2455         int i;
2456
2457         r8153_u1u2en(tp, 0);
2458
2459         for (i = 0; i < 500; i++) {
2460                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
2461                     AUTOLOAD_DONE)
2462                         break;
2463                 msleep(20);
2464         }
2465
2466         for (i = 0; i < 500; i++) {
2467                 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
2468                 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
2469                         break;
2470                 msleep(20);
2471         }
2472
2473         r8153_u2p3en(tp, 0);
2474
2475         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
2476         ocp_data &= ~TIMER11_EN;
2477         ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
2478
2479         r8153_clear_bp(tp);
2480
2481         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
2482         ocp_data &= ~LED_MODE_MASK;
2483         ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
2484
2485         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL);
2486         ocp_data &= ~LPM_TIMER_MASK;
2487         if (tp->udev->speed == USB_SPEED_SUPER)
2488                 ocp_data |= LPM_TIMER_500US;
2489         else
2490                 ocp_data |= LPM_TIMER_500MS;
2491         ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
2492
2493         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
2494         ocp_data &= ~SEN_VAL_MASK;
2495         ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
2496         ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
2497
2498         r8153_power_cut_en(tp, 0);
2499         r8153_u1u2en(tp, 1);
2500
2501         r8153_first_init(tp);
2502
2503         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO);
2504         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO);
2505         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
2506                        PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
2507                        U1U2_SPDWN_EN | L1_SPDWN_EN);
2508         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
2509                        PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
2510                        TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN |
2511                        EEE_SPDWN_EN);
2512
2513         r8153_enable_eee(tp);
2514         r8153_enable_aldps(tp);
2515         r8152b_enable_fc(tp);
2516
2517         r8152_mdio_write(tp, MII_BMCR, BMCR_RESET | BMCR_ANENABLE |
2518                                        BMCR_ANRESTART);
2519 }
2520
2521 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
2522 {
2523         struct r8152 *tp = usb_get_intfdata(intf);
2524
2525         netif_device_detach(tp->netdev);
2526
2527         if (netif_running(tp->netdev)) {
2528                 clear_bit(WORK_ENABLE, &tp->flags);
2529                 usb_kill_urb(tp->intr_urb);
2530                 cancel_delayed_work_sync(&tp->schedule);
2531                 tasklet_disable(&tp->tl);
2532         }
2533
2534         tp->rtl_ops.down(tp);
2535
2536         return 0;
2537 }
2538
2539 static int rtl8152_resume(struct usb_interface *intf)
2540 {
2541         struct r8152 *tp = usb_get_intfdata(intf);
2542
2543         tp->rtl_ops.init(tp);
2544         netif_device_attach(tp->netdev);
2545         if (netif_running(tp->netdev)) {
2546                 rtl8152_set_speed(tp, AUTONEG_ENABLE,
2547                                 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
2548                                 DUPLEX_FULL);
2549                 tp->speed = 0;
2550                 netif_carrier_off(tp->netdev);
2551                 set_bit(WORK_ENABLE, &tp->flags);
2552                 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
2553                 tasklet_enable(&tp->tl);
2554         }
2555
2556         return 0;
2557 }
2558
2559 static void rtl8152_get_drvinfo(struct net_device *netdev,
2560                                 struct ethtool_drvinfo *info)
2561 {
2562         struct r8152 *tp = netdev_priv(netdev);
2563
2564         strncpy(info->driver, MODULENAME, ETHTOOL_BUSINFO_LEN);
2565         strncpy(info->version, DRIVER_VERSION, ETHTOOL_BUSINFO_LEN);
2566         usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
2567 }
2568
2569 static
2570 int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2571 {
2572         struct r8152 *tp = netdev_priv(netdev);
2573
2574         if (!tp->mii.mdio_read)
2575                 return -EOPNOTSUPP;
2576
2577         return mii_ethtool_gset(&tp->mii, cmd);
2578 }
2579
2580 static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2581 {
2582         struct r8152 *tp = netdev_priv(dev);
2583
2584         return rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
2585 }
2586
2587 static struct ethtool_ops ops = {
2588         .get_drvinfo = rtl8152_get_drvinfo,
2589         .get_settings = rtl8152_get_settings,
2590         .set_settings = rtl8152_set_settings,
2591         .get_link = ethtool_op_get_link,
2592 };
2593
2594 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2595 {
2596         struct r8152 *tp = netdev_priv(netdev);
2597         struct mii_ioctl_data *data = if_mii(rq);
2598         int res = 0;
2599
2600         switch (cmd) {
2601         case SIOCGMIIPHY:
2602                 data->phy_id = R8152_PHY_ID; /* Internal PHY */
2603                 break;
2604
2605         case SIOCGMIIREG:
2606                 data->val_out = r8152_mdio_read(tp, data->reg_num);
2607                 break;
2608
2609         case SIOCSMIIREG:
2610                 if (!capable(CAP_NET_ADMIN)) {
2611                         res = -EPERM;
2612                         break;
2613                 }
2614                 r8152_mdio_write(tp, data->reg_num, data->val_in);
2615                 break;
2616
2617         default:
2618                 res = -EOPNOTSUPP;
2619         }
2620
2621         return res;
2622 }
2623
2624 static const struct net_device_ops rtl8152_netdev_ops = {
2625         .ndo_open               = rtl8152_open,
2626         .ndo_stop               = rtl8152_close,
2627         .ndo_do_ioctl           = rtl8152_ioctl,
2628         .ndo_start_xmit         = rtl8152_start_xmit,
2629         .ndo_tx_timeout         = rtl8152_tx_timeout,
2630         .ndo_set_rx_mode        = rtl8152_set_rx_mode,
2631         .ndo_set_mac_address    = rtl8152_set_mac_address,
2632
2633         .ndo_change_mtu         = eth_change_mtu,
2634         .ndo_validate_addr      = eth_validate_addr,
2635 };
2636
2637 static void r8152b_get_version(struct r8152 *tp)
2638 {
2639         u32     ocp_data;
2640         u16     version;
2641
2642         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
2643         version = (u16)(ocp_data & VERSION_MASK);
2644
2645         switch (version) {
2646         case 0x4c00:
2647                 tp->version = RTL_VER_01;
2648                 break;
2649         case 0x4c10:
2650                 tp->version = RTL_VER_02;
2651                 break;
2652         case 0x5c00:
2653                 tp->version = RTL_VER_03;
2654                 tp->mii.supports_gmii = 1;
2655                 break;
2656         case 0x5c10:
2657                 tp->version = RTL_VER_04;
2658                 tp->mii.supports_gmii = 1;
2659                 break;
2660         case 0x5c20:
2661                 tp->version = RTL_VER_05;
2662                 tp->mii.supports_gmii = 1;
2663                 break;
2664         default:
2665                 netif_info(tp, probe, tp->netdev,
2666                            "Unknown version 0x%04x\n", version);
2667                 break;
2668         }
2669 }
2670
2671 static void rtl8152_unload(struct r8152 *tp)
2672 {
2673         u32     ocp_data;
2674
2675         if (tp->version != RTL_VER_01) {
2676                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2677                 ocp_data |= POWER_CUT;
2678                 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2679         }
2680
2681         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2682         ocp_data &= ~RESUME_INDICATE;
2683         ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2684 }
2685
2686 static void rtl8153_unload(struct r8152 *tp)
2687 {
2688         r8153_power_cut_en(tp, 1);
2689 }
2690
2691 static int rtl_ops_init(struct r8152 *tp, const struct usb_device_id *id)
2692 {
2693         struct rtl_ops *ops = &tp->rtl_ops;
2694         int ret = -ENODEV;
2695
2696         switch (id->idVendor) {
2697         case VENDOR_ID_REALTEK:
2698                 switch (id->idProduct) {
2699                 case PRODUCT_ID_RTL8152:
2700                         ops->init               = r8152b_init;
2701                         ops->enable             = rtl8152_enable;
2702                         ops->disable            = rtl8152_disable;
2703                         ops->down               = rtl8152_down;
2704                         ops->unload             = rtl8152_unload;
2705                         ret = 0;
2706                         break;
2707                 case PRODUCT_ID_RTL8153:
2708                         ops->init               = r8153_init;
2709                         ops->enable             = rtl8153_enable;
2710                         ops->disable            = rtl8152_disable;
2711                         ops->down               = rtl8153_down;
2712                         ops->unload             = rtl8153_unload;
2713                         ret = 0;
2714                         break;
2715                 default:
2716                         break;
2717                 }
2718                 break;
2719
2720         case VENDOR_ID_SAMSUNG:
2721                 switch (id->idProduct) {
2722                 case PRODUCT_ID_SAMSUNG:
2723                         ops->init               = r8153_init;
2724                         ops->enable             = rtl8153_enable;
2725                         ops->disable            = rtl8152_disable;
2726                         ops->down               = rtl8153_down;
2727                         ops->unload             = rtl8153_unload;
2728                         ret = 0;
2729                         break;
2730                 default:
2731                         break;
2732                 }
2733                 break;
2734
2735         default:
2736                 break;
2737         }
2738
2739         if (ret)
2740                 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
2741
2742         return ret;
2743 }
2744
2745 static int rtl8152_probe(struct usb_interface *intf,
2746                          const struct usb_device_id *id)
2747 {
2748         struct usb_device *udev = interface_to_usbdev(intf);
2749         struct r8152 *tp;
2750         struct net_device *netdev;
2751         int ret;
2752
2753         if (udev->actconfig->desc.bConfigurationValue != 1) {
2754                 usb_driver_set_configuration(udev, 1);
2755                 return -ENODEV;
2756         }
2757
2758         netdev = alloc_etherdev(sizeof(struct r8152));
2759         if (!netdev) {
2760                 dev_err(&intf->dev, "Out of memory\n");
2761                 return -ENOMEM;
2762         }
2763
2764         SET_NETDEV_DEV(netdev, &intf->dev);
2765         tp = netdev_priv(netdev);
2766         tp->msg_enable = 0x7FFF;
2767
2768         tp->udev = udev;
2769         tp->netdev = netdev;
2770         tp->intf = intf;
2771
2772         ret = rtl_ops_init(tp, id);
2773         if (ret)
2774                 goto out;
2775
2776         tasklet_init(&tp->tl, bottom_half, (unsigned long)tp);
2777         INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
2778
2779         netdev->netdev_ops = &rtl8152_netdev_ops;
2780         netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
2781
2782         netdev->features |= NETIF_F_IP_CSUM;
2783         netdev->hw_features = NETIF_F_IP_CSUM;
2784         SET_ETHTOOL_OPS(netdev, &ops);
2785
2786         tp->mii.dev = netdev;
2787         tp->mii.mdio_read = read_mii_word;
2788         tp->mii.mdio_write = write_mii_word;
2789         tp->mii.phy_id_mask = 0x3f;
2790         tp->mii.reg_num_mask = 0x1f;
2791         tp->mii.phy_id = R8152_PHY_ID;
2792         tp->mii.supports_gmii = 0;
2793
2794         r8152b_get_version(tp);
2795         tp->rtl_ops.init(tp);
2796         set_ethernet_addr(tp);
2797
2798         ret = alloc_all_mem(tp);
2799         if (ret)
2800                 goto out;
2801
2802         usb_set_intfdata(intf, tp);
2803
2804         ret = register_netdev(netdev);
2805         if (ret != 0) {
2806                 netif_err(tp, probe, netdev, "couldn't register the device\n");
2807                 goto out1;
2808         }
2809
2810         netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
2811
2812         return 0;
2813
2814 out1:
2815         usb_set_intfdata(intf, NULL);
2816 out:
2817         free_netdev(netdev);
2818         return ret;
2819 }
2820
2821 static void rtl8152_disconnect(struct usb_interface *intf)
2822 {
2823         struct r8152 *tp = usb_get_intfdata(intf);
2824
2825         usb_set_intfdata(intf, NULL);
2826         if (tp) {
2827                 set_bit(RTL8152_UNPLUG, &tp->flags);
2828                 tasklet_kill(&tp->tl);
2829                 unregister_netdev(tp->netdev);
2830                 tp->rtl_ops.unload(tp);
2831                 free_all_mem(tp);
2832                 free_netdev(tp->netdev);
2833         }
2834 }
2835
2836 /* table of devices that work with this driver */
2837 static struct usb_device_id rtl8152_table[] = {
2838         {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)},
2839         {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8153)},
2840         {USB_DEVICE(VENDOR_ID_SAMSUNG, PRODUCT_ID_SAMSUNG)},
2841         {}
2842 };
2843
2844 MODULE_DEVICE_TABLE(usb, rtl8152_table);
2845
2846 static struct usb_driver rtl8152_driver = {
2847         .name =         MODULENAME,
2848         .id_table =     rtl8152_table,
2849         .probe =        rtl8152_probe,
2850         .disconnect =   rtl8152_disconnect,
2851         .suspend =      rtl8152_suspend,
2852         .resume =       rtl8152_resume,
2853         .reset_resume = rtl8152_resume,
2854 };
2855
2856 module_usb_driver(rtl8152_driver);
2857
2858 MODULE_AUTHOR(DRIVER_AUTHOR);
2859 MODULE_DESCRIPTION(DRIVER_DESC);
2860 MODULE_LICENSE("GPL");