Pileus Git - ~andy/linux/blob - drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18 #include <linux/config.h>
  19
  20 #include <linux/module.h>
  21 #include <linux/moduleparam.h>
  22 #include <linux/kernel.h>
  23 #include <linux/types.h>
  24 #include <linux/compiler.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/if_vlan.h>
  36 #include <linux/ip.h>
  37 #include <linux/tcp.h>
  38 #include <linux/workqueue.h>
  39
  40 #include <net/checksum.h>
  41
  42 #include <asm/system.h>
  43 #include <asm/io.h>
  44 #include <asm/byteorder.h>
  45 #include <asm/uaccess.h>
  46
  47 #ifdef CONFIG_SPARC64
  48 #include <asm/idprom.h>
  49 #include <asm/oplib.h>
  50 #include <asm/pbm.h>
  51 #endif
  52
  53 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  54 #define TG3_VLAN_TAG_USED 1
  55 #else
  56 #define TG3_VLAN_TAG_USED 0
  57 #endif
  58
  59 #ifdef NETIF_F_TSO
  60 #define TG3_TSO_SUPPORT 1
  61 #else
  62 #define TG3_TSO_SUPPORT 0
  63 #endif
  64
  65 #include "tg3.h"
  66
  67 #define DRV_MODULE_NAME         "tg3"
  68 #define PFX DRV_MODULE_NAME     ": "
  69 #define DRV_MODULE_VERSION      "3.31"
  70 #define DRV_MODULE_RELDATE      "June 8, 2005"
  71
  72 #define TG3_DEF_MAC_MODE        0
  73 #define TG3_DEF_RX_MODE         0
  74 #define TG3_DEF_TX_MODE         0
  75 #define TG3_DEF_MSG_ENABLE        \
  76         (NETIF_MSG_DRV          | \
  77          NETIF_MSG_PROBE        | \
  78          NETIF_MSG_LINK         | \
  79          NETIF_MSG_TIMER        | \
  80          NETIF_MSG_IFDOWN       | \
  81          NETIF_MSG_IFUP         | \
  82          NETIF_MSG_RX_ERR       | \
  83          NETIF_MSG_TX_ERR)
  84
  85 /* length of time before we decide the hardware is borked,
  86  * and dev->tx_timeout() should be called to fix the problem
  87  */
  88 #define TG3_TX_TIMEOUT                  (5 * HZ)
  89
  90 /* hardware minimum and maximum for a single frame's data payload */
  91 #define TG3_MIN_MTU                     60
  92 #define TG3_MAX_MTU(tp) \
  93         (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 9000 : 1500)
  94
  95 /* These numbers seem to be hard coded in the NIC firmware somehow.
  96  * You can't change the ring sizes, but you can change where you place
  97  * them in the NIC onboard memory.
  98  */
  99 #define TG3_RX_RING_SIZE                512
 100 #define TG3_DEF_RX_RING_PENDING         200
 101 #define TG3_RX_JUMBO_RING_SIZE          256
 102 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 103
 104 /* Do not place this n-ring entries value into the tp struct itself,
 105  * we really want to expose these constants to GCC so that modulo et
 106  * al.  operations are done with shifts and masks instead of with
 107  * hw multiply/modulo instructions.  Another solution would be to
 108  * replace things like '% foo' with '& (foo - 1)'.
 109  */
 110 #define TG3_RX_RCB_RING_SIZE(tp)        \
 111         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
 112
 113 #define TG3_TX_RING_SIZE                512
 114 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 115
 116 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 117                                  TG3_RX_RING_SIZE)
 118 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
 119                                  TG3_RX_JUMBO_RING_SIZE)
 120 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 121                                    TG3_RX_RCB_RING_SIZE(tp))
 122 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 123                                  TG3_TX_RING_SIZE)
 124 #define TX_RING_GAP(TP) \
 125         (TG3_TX_RING_SIZE - (TP)->tx_pending)
 126 #define TX_BUFFS_AVAIL(TP)                                              \
 127         (((TP)->tx_cons <= (TP)->tx_prod) ?                             \
 128           (TP)->tx_cons + (TP)->tx_pending - (TP)->tx_prod :            \
 129           (TP)->tx_cons - (TP)->tx_prod - TX_RING_GAP(TP))
 130 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 131
 132 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
 133 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
 134
 135 /* minimum number of free TX descriptors required to wake up TX process */
 136 #define TG3_TX_WAKEUP_THRESH            (TG3_TX_RING_SIZE / 4)
 137
 138 /* number of ETHTOOL_GSTATS u64's */
 139 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 140
 141 #define TG3_NUM_TEST            6
 142
 143 static char version[] __devinitdata =
 144         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 145
 146 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 147 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 148 MODULE_LICENSE("GPL");
 149 MODULE_VERSION(DRV_MODULE_VERSION);
 150
 151 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 152 module_param(tg3_debug, int, 0);
 153 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 154
 155 static struct pci_device_id tg3_pci_tbl[] = {
 156         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700,
 157           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 158         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701,
 159           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 160         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702,
 161           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 162         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703,
 163           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 164         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704,
 165           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 166         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE,
 167           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 168         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705,
 169           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 170         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2,
 171           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 172         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M,
 173           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 174         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2,
 175           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 176         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X,
 177           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 178         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X,
 179           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 180         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S,
 181           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 182         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3,
 183           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 184         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3,
 185           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 186         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782,
 187           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 188         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788,
 189           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 190         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789,
 191           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 192         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901,
 193           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 194         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2,
 195           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 196         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2,
 197           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 198         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F,
 199           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 200         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720,
 201           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 202         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721,
 203           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 204         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750,
 205           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 206         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751,
 207           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 208         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M,
 209           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 210         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M,
 211           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 212         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F,
 213           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 214         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752,
 215           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 216         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M,
 217           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 218         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753,
 219           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 220         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M,
 221           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 222         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F,
 223           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 224         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781,
 225           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 226         { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX,
 227           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 228         { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX,
 229           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 230         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000,
 231           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 232         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001,
 233           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 234         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003,
 235           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 236         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100,
 237           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 238         { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3,
 239           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 240         { 0, }
 241 };
 242
 243 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 244
 245 static struct {
 246         const char string[ETH_GSTRING_LEN];
 247 } ethtool_stats_keys[TG3_NUM_STATS] = {
 248         { "rx_octets" },
 249         { "rx_fragments" },
 250         { "rx_ucast_packets" },
 251         { "rx_mcast_packets" },
 252         { "rx_bcast_packets" },
 253         { "rx_fcs_errors" },
 254         { "rx_align_errors" },
 255         { "rx_xon_pause_rcvd" },
 256         { "rx_xoff_pause_rcvd" },
 257         { "rx_mac_ctrl_rcvd" },
 258         { "rx_xoff_entered" },
 259         { "rx_frame_too_long_errors" },
 260         { "rx_jabbers" },
 261         { "rx_undersize_packets" },
 262         { "rx_in_length_errors" },
 263         { "rx_out_length_errors" },
 264         { "rx_64_or_less_octet_packets" },
 265         { "rx_65_to_127_octet_packets" },
 266         { "rx_128_to_255_octet_packets" },
 267         { "rx_256_to_511_octet_packets" },
 268         { "rx_512_to_1023_octet_packets" },
 269         { "rx_1024_to_1522_octet_packets" },
 270         { "rx_1523_to_2047_octet_packets" },
 271         { "rx_2048_to_4095_octet_packets" },
 272         { "rx_4096_to_8191_octet_packets" },
 273         { "rx_8192_to_9022_octet_packets" },
 274
 275         { "tx_octets" },
 276         { "tx_collisions" },
 277
 278         { "tx_xon_sent" },
 279         { "tx_xoff_sent" },
 280         { "tx_flow_control" },
 281         { "tx_mac_errors" },
 282         { "tx_single_collisions" },
 283         { "tx_mult_collisions" },
 284         { "tx_deferred" },
 285         { "tx_excessive_collisions" },
 286         { "tx_late_collisions" },
 287         { "tx_collide_2times" },
 288         { "tx_collide_3times" },
 289         { "tx_collide_4times" },
 290         { "tx_collide_5times" },
 291         { "tx_collide_6times" },
 292         { "tx_collide_7times" },
 293         { "tx_collide_8times" },
 294         { "tx_collide_9times" },
 295         { "tx_collide_10times" },
 296         { "tx_collide_11times" },
 297         { "tx_collide_12times" },
 298         { "tx_collide_13times" },
 299         { "tx_collide_14times" },
 300         { "tx_collide_15times" },
 301         { "tx_ucast_packets" },
 302         { "tx_mcast_packets" },
 303         { "tx_bcast_packets" },
 304         { "tx_carrier_sense_errors" },
 305         { "tx_discards" },
 306         { "tx_errors" },
 307
 308         { "dma_writeq_full" },
 309         { "dma_write_prioq_full" },
 310         { "rxbds_empty" },
 311         { "rx_discards" },
 312         { "rx_errors" },
 313         { "rx_threshold_hit" },
 314
 315         { "dma_readq_full" },
 316         { "dma_read_prioq_full" },
 317         { "tx_comp_queue_full" },
 318
 319         { "ring_set_send_prod_index" },
 320         { "ring_status_update" },
 321         { "nic_irqs" },
 322         { "nic_avoided_irqs" },
 323         { "nic_tx_threshold_hit" }
 324 };
 325
 326 static struct {
 327         const char string[ETH_GSTRING_LEN];
 328 } ethtool_test_keys[TG3_NUM_TEST] = {
 329         { "nvram test     (online) " },
 330         { "link test      (online) " },
 331         { "register test  (offline)" },
 332         { "memory test    (offline)" },
 333         { "loopback test  (offline)" },
 334         { "interrupt test (offline)" },
 335 };
 336
 337 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 338 {
 339         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) != 0) {
 340                 spin_lock_bh(&tp->indirect_lock);
 341                 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 342                 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 343                 spin_unlock_bh(&tp->indirect_lock);
 344         } else {
 345                 writel(val, tp->regs + off);
 346                 if ((tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG) != 0)
 347                         readl(tp->regs + off);
 348         }
 349 }
 350
 351 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val)
 352 {
 353         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) != 0) {
 354                 spin_lock_bh(&tp->indirect_lock);
 355                 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 356                 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 357                 spin_unlock_bh(&tp->indirect_lock);
 358         } else {
 359                 void __iomem *dest = tp->regs + off;
 360                 writel(val, dest);
 361                 readl(dest);    /* always flush PCI write */
 362         }
 363 }
 364
 365 static inline void _tw32_rx_mbox(struct tg3 *tp, u32 off, u32 val)
 366 {
 367         void __iomem *mbox = tp->regs + off;
 368         writel(val, mbox);
 369         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 370                 readl(mbox);
 371 }
 372
 373 static inline void _tw32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 374 {
 375         void __iomem *mbox = tp->regs + off;
 376         writel(val, mbox);
 377         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 378                 writel(val, mbox);
 379         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 380                 readl(mbox);
 381 }
 382
 383 #define tw32_mailbox(reg, val)  writel(((val) & 0xffffffff), tp->regs + (reg))
 384 #define tw32_rx_mbox(reg, val)  _tw32_rx_mbox(tp, reg, val)
 385 #define tw32_tx_mbox(reg, val)  _tw32_tx_mbox(tp, reg, val)
 386
 387 #define tw32(reg,val)           tg3_write_indirect_reg32(tp,(reg),(val))
 388 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val))
 389 #define tw16(reg,val)           writew(((val) & 0xffff), tp->regs + (reg))
 390 #define tw8(reg,val)            writeb(((val) & 0xff), tp->regs + (reg))
 391 #define tr32(reg)               readl(tp->regs + (reg))
 392 #define tr16(reg)               readw(tp->regs + (reg))
 393 #define tr8(reg)                readb(tp->regs + (reg))
 394
 395 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 396 {
 397         spin_lock_bh(&tp->indirect_lock);
 398         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 399         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 400
 401         /* Always leave this as zero. */
 402         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 403         spin_unlock_bh(&tp->indirect_lock);
 404 }
 405
 406 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 407 {
 408         spin_lock_bh(&tp->indirect_lock);
 409         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 410         pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 411
 412         /* Always leave this as zero. */
 413         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 414         spin_unlock_bh(&tp->indirect_lock);
 415 }
 416
 417 static void tg3_disable_ints(struct tg3 *tp)
 418 {
 419         tw32(TG3PCI_MISC_HOST_CTRL,
 420              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 421         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
 422         tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
 423 }
 424
 425 static inline void tg3_cond_int(struct tg3 *tp)
 426 {
 427         if (tp->hw_status->status & SD_STATUS_UPDATED)
 428                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 429 }
 430
 431 static void tg3_enable_ints(struct tg3 *tp)
 432 {
 433         tw32(TG3PCI_MISC_HOST_CTRL,
 434              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 435         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 436                      (tp->last_tag << 24));
 437         tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
 438         tp->irq_sync = 0;
 439         tg3_cond_int(tp);
 440 }
 441
 442 static inline unsigned int tg3_has_work(struct tg3 *tp)
 443 {
 444         struct tg3_hw_status *sblk = tp->hw_status;
 445         unsigned int work_exists = 0;
 446
 447         /* check for phy events */
 448         if (!(tp->tg3_flags &
 449               (TG3_FLAG_USE_LINKCHG_REG |
 450                TG3_FLAG_POLL_SERDES))) {
 451                 if (sblk->status & SD_STATUS_LINK_CHG)
 452                         work_exists = 1;
 453         }
 454         /* check for RX/TX work to do */
 455         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
 456             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
 457                 work_exists = 1;
 458
 459         return work_exists;
 460 }
 461
 462 /* tg3_restart_ints
 463  *  similar to tg3_enable_ints, but it accurately determines whether there
 464  *  is new work pending and can return without flushing the PIO write
 465  *  which reenables interrupts
 466  */
 467 static void tg3_restart_ints(struct tg3 *tp)
 468 {
 469         tw32(TG3PCI_MISC_HOST_CTRL,
 470                 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 471         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 472                      tp->last_tag << 24);
 473         mmiowb();
 474
 475         /* When doing tagged status, this work check is unnecessary.
 476          * The last_tag we write above tells the chip which piece of
 477          * work we've completed.
 478          */
 479         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 480             tg3_has_work(tp))
 481                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 482                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 483 }
 484
 485 static inline void tg3_netif_stop(struct tg3 *tp)
 486 {
 487         netif_poll_disable(tp->dev);
 488         netif_tx_disable(tp->dev);
 489 }
 490
 491 static inline void tg3_netif_start(struct tg3 *tp)
 492 {
 493         netif_wake_queue(tp->dev);
 494         /* NOTE: unconditional netif_wake_queue is only appropriate
 495          * so long as all callers are assured to have free tx slots
 496          * (such as after tg3_init_hw)
 497          */
 498         netif_poll_enable(tp->dev);
 499         tp->hw_status->status |= SD_STATUS_UPDATED;
 500         tg3_enable_ints(tp);
 501 }
 502
 503 static void tg3_switch_clocks(struct tg3 *tp)
 504 {
 505         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 506         u32 orig_clock_ctrl;
 507
 508         orig_clock_ctrl = clock_ctrl;
 509         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 510                        CLOCK_CTRL_CLKRUN_OENABLE |
 511                        0x1f);
 512         tp->pci_clock_ctrl = clock_ctrl;
 513
 514         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 515                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 516                         tw32_f(TG3PCI_CLOCK_CTRL,
 517                                clock_ctrl | CLOCK_CTRL_625_CORE);
 518                         udelay(40);
 519                 }
 520         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 521                 tw32_f(TG3PCI_CLOCK_CTRL,
 522                      clock_ctrl |
 523                      (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK));
 524                 udelay(40);
 525                 tw32_f(TG3PCI_CLOCK_CTRL,
 526                      clock_ctrl | (CLOCK_CTRL_ALTCLK));
 527                 udelay(40);
 528         }
 529         tw32_f(TG3PCI_CLOCK_CTRL, clock_ctrl);
 530         udelay(40);
 531 }
 532
 533 #define PHY_BUSY_LOOPS  5000
 534
 535 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 536 {
 537         u32 frame_val;
 538         unsigned int loops;
 539         int ret;
 540
 541         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 542                 tw32_f(MAC_MI_MODE,
 543                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 544                 udelay(80);
 545         }
 546
 547         *val = 0x0;
 548
 549         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 550                       MI_COM_PHY_ADDR_MASK);
 551         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 552                       MI_COM_REG_ADDR_MASK);
 553         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 554
 555         tw32_f(MAC_MI_COM, frame_val);
 556
 557         loops = PHY_BUSY_LOOPS;
 558         while (loops != 0) {
 559                 udelay(10);
 560                 frame_val = tr32(MAC_MI_COM);
 561
 562                 if ((frame_val & MI_COM_BUSY) == 0) {
 563                         udelay(5);
 564                         frame_val = tr32(MAC_MI_COM);
 565                         break;
 566                 }
 567                 loops -= 1;
 568         }
 569
 570         ret = -EBUSY;
 571         if (loops != 0) {
 572                 *val = frame_val & MI_COM_DATA_MASK;
 573                 ret = 0;
 574         }
 575
 576         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 577                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 578                 udelay(80);
 579         }
 580
 581         return ret;
 582 }
 583
 584 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 585 {
 586         u32 frame_val;
 587         unsigned int loops;
 588         int ret;
 589
 590         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 591                 tw32_f(MAC_MI_MODE,
 592                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 593                 udelay(80);
 594         }
 595
 596         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 597                       MI_COM_PHY_ADDR_MASK);
 598         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 599                       MI_COM_REG_ADDR_MASK);
 600         frame_val |= (val & MI_COM_DATA_MASK);
 601         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 602
 603         tw32_f(MAC_MI_COM, frame_val);
 604
 605         loops = PHY_BUSY_LOOPS;
 606         while (loops != 0) {
 607                 udelay(10);
 608                 frame_val = tr32(MAC_MI_COM);
 609                 if ((frame_val & MI_COM_BUSY) == 0) {
 610                         udelay(5);
 611                         frame_val = tr32(MAC_MI_COM);
 612                         break;
 613                 }
 614                 loops -= 1;
 615         }
 616
 617         ret = -EBUSY;
 618         if (loops != 0)
 619                 ret = 0;
 620
 621         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 622                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 623                 udelay(80);
 624         }
 625
 626         return ret;
 627 }
 628
 629 static void tg3_phy_set_wirespeed(struct tg3 *tp)
 630 {
 631         u32 val;
 632
 633         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
 634                 return;
 635
 636         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
 637             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
 638                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
 639                              (val | (1 << 15) | (1 << 4)));
 640 }
 641
 642 static int tg3_bmcr_reset(struct tg3 *tp)
 643 {
 644         u32 phy_control;
 645         int limit, err;
 646
 647         /* OK, reset it, and poll the BMCR_RESET bit until it
 648          * clears or we time out.
 649          */
 650         phy_control = BMCR_RESET;
 651         err = tg3_writephy(tp, MII_BMCR, phy_control);
 652         if (err != 0)
 653                 return -EBUSY;
 654
 655         limit = 5000;
 656         while (limit--) {
 657                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 658                 if (err != 0)
 659                         return -EBUSY;
 660
 661                 if ((phy_control & BMCR_RESET) == 0) {
 662                         udelay(40);
 663                         break;
 664                 }
 665                 udelay(10);
 666         }
 667         if (limit <= 0)
 668                 return -EBUSY;
 669
 670         return 0;
 671 }
 672
 673 static int tg3_wait_macro_done(struct tg3 *tp)
 674 {
 675         int limit = 100;
 676
 677         while (limit--) {
 678                 u32 tmp32;
 679
 680                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
 681                         if ((tmp32 & 0x1000) == 0)
 682                                 break;
 683                 }
 684         }
 685         if (limit <= 0)
 686                 return -EBUSY;
 687
 688         return 0;
 689 }
 690
 691 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
 692 {
 693         static const u32 test_pat[4][6] = {
 694         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
 695         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
 696         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
 697         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
 698         };
 699         int chan;
 700
 701         for (chan = 0; chan < 4; chan++) {
 702                 int i;
 703
 704                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 705                              (chan * 0x2000) | 0x0200);
 706                 tg3_writephy(tp, 0x16, 0x0002);
 707
 708                 for (i = 0; i < 6; i++)
 709                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
 710                                      test_pat[chan][i]);
 711
 712                 tg3_writephy(tp, 0x16, 0x0202);
 713                 if (tg3_wait_macro_done(tp)) {
 714                         *resetp = 1;
 715                         return -EBUSY;
 716                 }
 717
 718                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 719                              (chan * 0x2000) | 0x0200);
 720                 tg3_writephy(tp, 0x16, 0x0082);
 721                 if (tg3_wait_macro_done(tp)) {
 722                         *resetp = 1;
 723                         return -EBUSY;
 724                 }
 725
 726                 tg3_writephy(tp, 0x16, 0x0802);
 727                 if (tg3_wait_macro_done(tp)) {
 728                         *resetp = 1;
 729                         return -EBUSY;
 730                 }
 731
 732                 for (i = 0; i < 6; i += 2) {
 733                         u32 low, high;
 734
 735                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
 736                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
 737                             tg3_wait_macro_done(tp)) {
 738                                 *resetp = 1;
 739                                 return -EBUSY;
 740                         }
 741                         low &= 0x7fff;
 742                         high &= 0x000f;
 743                         if (low != test_pat[chan][i] ||
 744                             high != test_pat[chan][i+1]) {
 745                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
 746                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
 747                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
 748
 749                                 return -EBUSY;
 750                         }
 751                 }
 752         }
 753
 754         return 0;
 755 }
 756
 757 static int tg3_phy_reset_chanpat(struct tg3 *tp)
 758 {
 759         int chan;
 760
 761         for (chan = 0; chan < 4; chan++) {
 762                 int i;
 763
 764                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 765                              (chan * 0x2000) | 0x0200);
 766                 tg3_writephy(tp, 0x16, 0x0002);
 767                 for (i = 0; i < 6; i++)
 768                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
 769                 tg3_writephy(tp, 0x16, 0x0202);
 770                 if (tg3_wait_macro_done(tp))
 771                         return -EBUSY;
 772         }
 773
 774         return 0;
 775 }
 776
 777 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
 778 {
 779         u32 reg32, phy9_orig;
 780         int retries, do_phy_reset, err;
 781
 782         retries = 10;
 783         do_phy_reset = 1;
 784         do {
 785                 if (do_phy_reset) {
 786                         err = tg3_bmcr_reset(tp);
 787                         if (err)
 788                                 return err;
 789                         do_phy_reset = 0;
 790                 }
 791
 792                 /* Disable transmitter and interrupt.  */
 793                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
 794                         continue;
 795
 796                 reg32 |= 0x3000;
 797                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 798
 799                 /* Set full-duplex, 1000 mbps.  */
 800                 tg3_writephy(tp, MII_BMCR,
 801                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
 802
 803                 /* Set to master mode.  */
 804                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
 805                         continue;
 806
 807                 tg3_writephy(tp, MII_TG3_CTRL,
 808                              (MII_TG3_CTRL_AS_MASTER |
 809                               MII_TG3_CTRL_ENABLE_AS_MASTER));
 810
 811                 /* Enable SM_DSP_CLOCK and 6dB.  */
 812                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 813
 814                 /* Block the PHY control access.  */
 815                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 816                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
 817
 818                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
 819                 if (!err)
 820                         break;
 821         } while (--retries);
 822
 823         err = tg3_phy_reset_chanpat(tp);
 824         if (err)
 825                 return err;
 826
 827         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 828         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
 829
 830         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
 831         tg3_writephy(tp, 0x16, 0x0000);
 832
 833         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 834             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
 835                 /* Set Extended packet length bit for jumbo frames */
 836                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
 837         }
 838         else {
 839                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 840         }
 841
 842         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
 843
 844         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
 845                 reg32 &= ~0x3000;
 846                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 847         } else if (!err)
 848                 err = -EBUSY;
 849
 850         return err;
 851 }
 852
 853 /* This will reset the tigon3 PHY if there is no valid
 854  * link unless the FORCE argument is non-zero.
 855  */
 856 static int tg3_phy_reset(struct tg3 *tp)
 857 {
 858         u32 phy_status;
 859         int err;
 860
 861         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
 862         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
 863         if (err != 0)
 864                 return -EBUSY;
 865
 866         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 867             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
 868             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
 869                 err = tg3_phy_reset_5703_4_5(tp);
 870                 if (err)
 871                         return err;
 872                 goto out;
 873         }
 874
 875         err = tg3_bmcr_reset(tp);
 876         if (err)
 877                 return err;
 878
 879 out:
 880         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
 881                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 882                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
 883                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
 884                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
 885                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
 886                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 887         }
 888         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
 889                 tg3_writephy(tp, 0x1c, 0x8d68);
 890                 tg3_writephy(tp, 0x1c, 0x8d68);
 891         }
 892         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
 893                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 894                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
 895                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
 896                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
 897                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
 898                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
 899                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
 900                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 901         }
 902         /* Set Extended packet length bit (bit 14) on all chips that */
 903         /* support jumbo frames */
 904         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
 905                 /* Cannot do read-modify-write on 5401 */
 906                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
 907         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
 908                 u32 phy_reg;
 909
 910                 /* Set bit 14 with read-modify-write to preserve other bits */
 911                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
 912                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
 913                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
 914         }
 915
 916         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
 917          * jumbo frames transmission.
 918          */
 919         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
 920                 u32 phy_reg;
 921
 922                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
 923                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
 924                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
 925         }
 926
 927         tg3_phy_set_wirespeed(tp);
 928         return 0;
 929 }
 930
 931 static void tg3_frob_aux_power(struct tg3 *tp)
 932 {
 933         struct tg3 *tp_peer = tp;
 934
 935         if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0)
 936                 return;
 937
 938         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
 939                 tp_peer = pci_get_drvdata(tp->pdev_peer);
 940                 if (!tp_peer)
 941                         BUG();
 942         }
 943
 944
 945         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
 946             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0) {
 947                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
 948                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
 949                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
 950                              (GRC_LCLCTRL_GPIO_OE0 |
 951                               GRC_LCLCTRL_GPIO_OE1 |
 952                               GRC_LCLCTRL_GPIO_OE2 |
 953                               GRC_LCLCTRL_GPIO_OUTPUT0 |
 954                               GRC_LCLCTRL_GPIO_OUTPUT1));
 955                         udelay(100);
 956                 } else {
 957                         u32 no_gpio2;
 958                         u32 grc_local_ctrl;
 959
 960                         if (tp_peer != tp &&
 961                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
 962                                 return;
 963
 964                         /* On 5753 and variants, GPIO2 cannot be used. */
 965                         no_gpio2 = tp->nic_sram_data_cfg &
 966                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
 967
 968                         grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
 969                                          GRC_LCLCTRL_GPIO_OE1 |
 970                                          GRC_LCLCTRL_GPIO_OE2 |
 971                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
 972                                          GRC_LCLCTRL_GPIO_OUTPUT2;
 973                         if (no_gpio2) {
 974                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
 975                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
 976                         }
 977                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
 978                                                 grc_local_ctrl);
 979                         udelay(100);
 980
 981                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
 982
 983                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
 984                                                 grc_local_ctrl);
 985                         udelay(100);
 986
 987                         if (!no_gpio2) {
 988                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
 989                                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
 990                                        grc_local_ctrl);
 991                                 udelay(100);
 992                         }
 993                 }
 994         } else {
 995                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
 996                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
 997                         if (tp_peer != tp &&
 998                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
 999                                 return;
1000
1001                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1002                              (GRC_LCLCTRL_GPIO_OE1 |
1003                               GRC_LCLCTRL_GPIO_OUTPUT1));
1004                         udelay(100);
1005
1006                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1007                              (GRC_LCLCTRL_GPIO_OE1));
1008                         udelay(100);
1009
1010                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1011                              (GRC_LCLCTRL_GPIO_OE1 |
1012                               GRC_LCLCTRL_GPIO_OUTPUT1));
1013                         udelay(100);
1014                 }
1015         }
1016 }
1017
1018 static int tg3_setup_phy(struct tg3 *, int);
1019
1020 #define RESET_KIND_SHUTDOWN     0
1021 #define RESET_KIND_INIT         1
1022 #define RESET_KIND_SUSPEND      2
1023
1024 static void tg3_write_sig_post_reset(struct tg3 *, int);
1025 static int tg3_halt_cpu(struct tg3 *, u32);
1026
1027 static int tg3_set_power_state(struct tg3 *tp, int state)
1028 {
1029         u32 misc_host_ctrl;
1030         u16 power_control, power_caps;
1031         int pm = tp->pm_cap;
1032
1033         /* Make sure register accesses (indirect or otherwise)
1034          * will function correctly.
1035          */
1036         pci_write_config_dword(tp->pdev,
1037                                TG3PCI_MISC_HOST_CTRL,
1038                                tp->misc_host_ctrl);
1039
1040         pci_read_config_word(tp->pdev,
1041                              pm + PCI_PM_CTRL,
1042                              &power_control);
1043         power_control |= PCI_PM_CTRL_PME_STATUS;
1044         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1045         switch (state) {
1046         case 0:
1047                 power_control |= 0;
1048                 pci_write_config_word(tp->pdev,
1049                                       pm + PCI_PM_CTRL,
1050                                       power_control);
1051                 udelay(100);    /* Delay after power state change */
1052
1053                 /* Switch out of Vaux if it is not a LOM */
1054                 if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)) {
1055                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1056                         udelay(100);
1057                 }
1058
1059                 return 0;
1060
1061         case 1:
1062                 power_control |= 1;
1063                 break;
1064
1065         case 2:
1066                 power_control |= 2;
1067                 break;
1068
1069         case 3:
1070                 power_control |= 3;
1071                 break;
1072
1073         default:
1074                 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1075                        "requested.\n",
1076                        tp->dev->name, state);
1077                 return -EINVAL;
1078         };
1079
1080         power_control |= PCI_PM_CTRL_PME_ENABLE;
1081
1082         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1083         tw32(TG3PCI_MISC_HOST_CTRL,
1084              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1085
1086         if (tp->link_config.phy_is_low_power == 0) {
1087                 tp->link_config.phy_is_low_power = 1;
1088                 tp->link_config.orig_speed = tp->link_config.speed;
1089                 tp->link_config.orig_duplex = tp->link_config.duplex;
1090                 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1091         }
1092
1093         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1094                 tp->link_config.speed = SPEED_10;
1095                 tp->link_config.duplex = DUPLEX_HALF;
1096                 tp->link_config.autoneg = AUTONEG_ENABLE;
1097                 tg3_setup_phy(tp, 0);
1098         }
1099
1100         pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1101
1102         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1103                 u32 mac_mode;
1104
1105                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1106                         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1107                         udelay(40);
1108
1109                         mac_mode = MAC_MODE_PORT_MODE_MII;
1110
1111                         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1112                             !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1113                                 mac_mode |= MAC_MODE_LINK_POLARITY;
1114                 } else {
1115                         mac_mode = MAC_MODE_PORT_MODE_TBI;
1116                 }
1117
1118                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1119                         tw32(MAC_LED_CTRL, tp->led_ctrl);
1120
1121                 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1122                      (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1123                         mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1124
1125                 tw32_f(MAC_MODE, mac_mode);
1126                 udelay(100);
1127
1128                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1129                 udelay(10);
1130         }
1131
1132         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1133             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1134              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1135                 u32 base_val;
1136
1137                 base_val = tp->pci_clock_ctrl;
1138                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1139                              CLOCK_CTRL_TXCLK_DISABLE);
1140
1141                 tw32_f(TG3PCI_CLOCK_CTRL, base_val |
1142                      CLOCK_CTRL_ALTCLK |
1143                      CLOCK_CTRL_PWRDOWN_PLL133);
1144                 udelay(40);
1145         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1146                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1147                 u32 newbits1, newbits2;
1148
1149                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1150                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1151                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1152                                     CLOCK_CTRL_TXCLK_DISABLE |
1153                                     CLOCK_CTRL_ALTCLK);
1154                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1155                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1156                         newbits1 = CLOCK_CTRL_625_CORE;
1157                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1158                 } else {
1159                         newbits1 = CLOCK_CTRL_ALTCLK;
1160                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1161                 }
1162
1163                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1);
1164                 udelay(40);
1165
1166                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2);
1167                 udelay(40);
1168
1169                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1170                         u32 newbits3;
1171
1172                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1173                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1174                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1175                                             CLOCK_CTRL_TXCLK_DISABLE |
1176                                             CLOCK_CTRL_44MHZ_CORE);
1177                         } else {
1178                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1179                         }
1180
1181                         tw32_f(TG3PCI_CLOCK_CTRL,
1182                                          tp->pci_clock_ctrl | newbits3);
1183                         udelay(40);
1184                 }
1185         }
1186
1187         tg3_frob_aux_power(tp);
1188
1189         /* Workaround for unstable PLL clock */
1190         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1191             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1192                 u32 val = tr32(0x7d00);
1193
1194                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1195                 tw32(0x7d00, val);
1196                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1197                         tg3_halt_cpu(tp, RX_CPU_BASE);
1198         }
1199
1200         /* Finally, set the new power state. */
1201         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1202         udelay(100);    /* Delay after power state change */
1203
1204         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1205
1206         return 0;
1207 }
1208
1209 static void tg3_link_report(struct tg3 *tp)
1210 {
1211         if (!netif_carrier_ok(tp->dev)) {
1212                 printk(KERN_INFO PFX "%s: Link is down.\n", tp->dev->name);
1213         } else {
1214                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1215                        tp->dev->name,
1216                        (tp->link_config.active_speed == SPEED_1000 ?
1217                         1000 :
1218                         (tp->link_config.active_speed == SPEED_100 ?
1219                          100 : 10)),
1220                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1221                         "full" : "half"));
1222
1223                 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1224                        "%s for RX.\n",
1225                        tp->dev->name,
1226                        (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1227                        (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1228         }
1229 }
1230
1231 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1232 {
1233         u32 new_tg3_flags = 0;
1234         u32 old_rx_mode = tp->rx_mode;
1235         u32 old_tx_mode = tp->tx_mode;
1236
1237         if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1238                 if (local_adv & ADVERTISE_PAUSE_CAP) {
1239                         if (local_adv & ADVERTISE_PAUSE_ASYM) {
1240                                 if (remote_adv & LPA_PAUSE_CAP)
1241                                         new_tg3_flags |=
1242                                                 (TG3_FLAG_RX_PAUSE |
1243                                                 TG3_FLAG_TX_PAUSE);
1244                                 else if (remote_adv & LPA_PAUSE_ASYM)
1245                                         new_tg3_flags |=
1246                                                 (TG3_FLAG_RX_PAUSE);
1247                         } else {
1248                                 if (remote_adv & LPA_PAUSE_CAP)
1249                                         new_tg3_flags |=
1250                                                 (TG3_FLAG_RX_PAUSE |
1251                                                 TG3_FLAG_TX_PAUSE);
1252                         }
1253                 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1254                         if ((remote_adv & LPA_PAUSE_CAP) &&
1255                         (remote_adv & LPA_PAUSE_ASYM))
1256                                 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1257                 }
1258
1259                 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1260                 tp->tg3_flags |= new_tg3_flags;
1261         } else {
1262                 new_tg3_flags = tp->tg3_flags;
1263         }
1264
1265         if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1266                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1267         else
1268                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1269
1270         if (old_rx_mode != tp->rx_mode) {
1271                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1272         }
1273
1274         if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1275                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1276         else
1277                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1278
1279         if (old_tx_mode != tp->tx_mode) {
1280                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1281         }
1282 }
1283
1284 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1285 {
1286         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1287         case MII_TG3_AUX_STAT_10HALF:
1288                 *speed = SPEED_10;
1289                 *duplex = DUPLEX_HALF;
1290                 break;
1291
1292         case MII_TG3_AUX_STAT_10FULL:
1293                 *speed = SPEED_10;
1294                 *duplex = DUPLEX_FULL;
1295                 break;
1296
1297         case MII_TG3_AUX_STAT_100HALF:
1298                 *speed = SPEED_100;
1299                 *duplex = DUPLEX_HALF;
1300                 break;
1301
1302         case MII_TG3_AUX_STAT_100FULL:
1303                 *speed = SPEED_100;
1304                 *duplex = DUPLEX_FULL;
1305                 break;
1306
1307         case MII_TG3_AUX_STAT_1000HALF:
1308                 *speed = SPEED_1000;
1309                 *duplex = DUPLEX_HALF;
1310                 break;
1311
1312         case MII_TG3_AUX_STAT_1000FULL:
1313                 *speed = SPEED_1000;
1314                 *duplex = DUPLEX_FULL;
1315                 break;
1316
1317         default:
1318                 *speed = SPEED_INVALID;
1319                 *duplex = DUPLEX_INVALID;
1320                 break;
1321         };
1322 }
1323
1324 static void tg3_phy_copper_begin(struct tg3 *tp)
1325 {
1326         u32 new_adv;
1327         int i;
1328
1329         if (tp->link_config.phy_is_low_power) {
1330                 /* Entering low power mode.  Disable gigabit and
1331                  * 100baseT advertisements.
1332                  */
1333                 tg3_writephy(tp, MII_TG3_CTRL, 0);
1334
1335                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1336                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1337                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1338                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1339
1340                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1341         } else if (tp->link_config.speed == SPEED_INVALID) {
1342                 tp->link_config.advertising =
1343                         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1344                          ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
1345                          ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
1346                          ADVERTISED_Autoneg | ADVERTISED_MII);
1347
1348                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1349                         tp->link_config.advertising &=
1350                                 ~(ADVERTISED_1000baseT_Half |
1351                                   ADVERTISED_1000baseT_Full);
1352
1353                 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1354                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1355                         new_adv |= ADVERTISE_10HALF;
1356                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1357                         new_adv |= ADVERTISE_10FULL;
1358                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1359                         new_adv |= ADVERTISE_100HALF;
1360                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1361                         new_adv |= ADVERTISE_100FULL;
1362                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1363
1364                 if (tp->link_config.advertising &
1365                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1366                         new_adv = 0;
1367                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1368                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1369                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1370                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1371                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1372                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1373                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1374                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1375                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1376                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1377                 } else {
1378                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1379                 }
1380         } else {
1381                 /* Asking for a specific link mode. */
1382                 if (tp->link_config.speed == SPEED_1000) {
1383                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1384                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1385
1386                         if (tp->link_config.duplex == DUPLEX_FULL)
1387                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1388                         else
1389                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1390                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1391                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1392                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1393                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1394                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1395                 } else {
1396                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1397
1398                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1399                         if (tp->link_config.speed == SPEED_100) {
1400                                 if (tp->link_config.duplex == DUPLEX_FULL)
1401                                         new_adv |= ADVERTISE_100FULL;
1402                                 else
1403                                         new_adv |= ADVERTISE_100HALF;
1404                         } else {
1405                                 if (tp->link_config.duplex == DUPLEX_FULL)
1406                                         new_adv |= ADVERTISE_10FULL;
1407                                 else
1408                                         new_adv |= ADVERTISE_10HALF;
1409                         }
1410                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1411                 }
1412         }
1413
1414         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1415             tp->link_config.speed != SPEED_INVALID) {
1416                 u32 bmcr, orig_bmcr;
1417
1418                 tp->link_config.active_speed = tp->link_config.speed;
1419                 tp->link_config.active_duplex = tp->link_config.duplex;
1420
1421                 bmcr = 0;
1422                 switch (tp->link_config.speed) {
1423                 default:
1424                 case SPEED_10:
1425                         break;
1426
1427                 case SPEED_100:
1428                         bmcr |= BMCR_SPEED100;
1429                         break;
1430
1431                 case SPEED_1000:
1432                         bmcr |= TG3_BMCR_SPEED1000;
1433                         break;
1434                 };
1435
1436                 if (tp->link_config.duplex == DUPLEX_FULL)
1437                         bmcr |= BMCR_FULLDPLX;
1438
1439                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1440                     (bmcr != orig_bmcr)) {
1441                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1442                         for (i = 0; i < 1500; i++) {
1443                                 u32 tmp;
1444
1445                                 udelay(10);
1446                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1447                                     tg3_readphy(tp, MII_BMSR, &tmp))
1448                                         continue;
1449                                 if (!(tmp & BMSR_LSTATUS)) {
1450                                         udelay(40);
1451                                         break;
1452                                 }
1453                         }
1454                         tg3_writephy(tp, MII_BMCR, bmcr);
1455                         udelay(40);
1456                 }
1457         } else {
1458                 tg3_writephy(tp, MII_BMCR,
1459                              BMCR_ANENABLE | BMCR_ANRESTART);
1460         }
1461 }
1462
1463 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1464 {
1465         int err;
1466
1467         /* Turn off tap power management. */
1468         /* Set Extended packet length bit */
1469         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1470
1471         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1472         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1473
1474         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1475         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1476
1477         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1478         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1479
1480         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1481         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1482
1483         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1484         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1485
1486         udelay(40);
1487
1488         return err;
1489 }
1490
1491 static int tg3_copper_is_advertising_all(struct tg3 *tp)
1492 {
1493         u32 adv_reg, all_mask;
1494
1495         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1496                 return 0;
1497
1498         all_mask = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1499                     ADVERTISE_100HALF | ADVERTISE_100FULL);
1500         if ((adv_reg & all_mask) != all_mask)
1501                 return 0;
1502         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1503                 u32 tg3_ctrl;
1504
1505                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1506                         return 0;
1507
1508                 all_mask = (MII_TG3_CTRL_ADV_1000_HALF |
1509                             MII_TG3_CTRL_ADV_1000_FULL);
1510                 if ((tg3_ctrl & all_mask) != all_mask)
1511                         return 0;
1512         }
1513         return 1;
1514 }
1515
1516 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1517 {
1518         int current_link_up;
1519         u32 bmsr, dummy;
1520         u16 current_speed;
1521         u8 current_duplex;
1522         int i, err;
1523
1524         tw32(MAC_EVENT, 0);
1525
1526         tw32_f(MAC_STATUS,
1527              (MAC_STATUS_SYNC_CHANGED |
1528               MAC_STATUS_CFG_CHANGED |
1529               MAC_STATUS_MI_COMPLETION |
1530               MAC_STATUS_LNKSTATE_CHANGED));
1531         udelay(40);
1532
1533         tp->mi_mode = MAC_MI_MODE_BASE;
1534         tw32_f(MAC_MI_MODE, tp->mi_mode);
1535         udelay(80);
1536
1537         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1538
1539         /* Some third-party PHYs need to be reset on link going
1540          * down.
1541          */
1542         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1543              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1544              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1545             netif_carrier_ok(tp->dev)) {
1546                 tg3_readphy(tp, MII_BMSR, &bmsr);
1547                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1548                     !(bmsr & BMSR_LSTATUS))
1549                         force_reset = 1;
1550         }
1551         if (force_reset)
1552                 tg3_phy_reset(tp);
1553
1554         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1555                 tg3_readphy(tp, MII_BMSR, &bmsr);
1556                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1557                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1558                         bmsr = 0;
1559
1560                 if (!(bmsr & BMSR_LSTATUS)) {
1561                         err = tg3_init_5401phy_dsp(tp);
1562                         if (err)
1563                                 return err;
1564
1565                         tg3_readphy(tp, MII_BMSR, &bmsr);
1566                         for (i = 0; i < 1000; i++) {
1567                                 udelay(10);
1568                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1569                                     (bmsr & BMSR_LSTATUS)) {
1570                                         udelay(40);
1571                                         break;
1572                                 }
1573                         }
1574
1575                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1576                             !(bmsr & BMSR_LSTATUS) &&
1577                             tp->link_config.active_speed == SPEED_1000) {
1578                                 err = tg3_phy_reset(tp);
1579                                 if (!err)
1580                                         err = tg3_init_5401phy_dsp(tp);
1581                                 if (err)
1582                                         return err;
1583                         }
1584                 }
1585         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1586                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1587                 /* 5701 {A0,B0} CRC bug workaround */
1588                 tg3_writephy(tp, 0x15, 0x0a75);
1589                 tg3_writephy(tp, 0x1c, 0x8c68);
1590                 tg3_writephy(tp, 0x1c, 0x8d68);
1591                 tg3_writephy(tp, 0x1c, 0x8c68);
1592         }
1593
1594         /* Clear pending interrupts... */
1595         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1596         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1597
1598         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1599                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1600         else
1601                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1602
1603         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1604             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1605                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1606                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
1607                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1608                 else
1609                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1610         }
1611
1612         current_link_up = 0;
1613         current_speed = SPEED_INVALID;
1614         current_duplex = DUPLEX_INVALID;
1615
1616         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1617                 u32 val;
1618
1619                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1620                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1621                 if (!(val & (1 << 10))) {
1622                         val |= (1 << 10);
1623                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1624                         goto relink;
1625                 }
1626         }
1627
1628         bmsr = 0;
1629         for (i = 0; i < 100; i++) {
1630                 tg3_readphy(tp, MII_BMSR, &bmsr);
1631                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1632                     (bmsr & BMSR_LSTATUS))
1633                         break;
1634                 udelay(40);
1635         }
1636
1637         if (bmsr & BMSR_LSTATUS) {
1638                 u32 aux_stat, bmcr;
1639
1640                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1641                 for (i = 0; i < 2000; i++) {
1642                         udelay(10);
1643                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1644                             aux_stat)
1645                                 break;
1646                 }
1647
1648                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1649                                              &current_speed,
1650                                              &current_duplex);
1651
1652                 bmcr = 0;
1653                 for (i = 0; i < 200; i++) {
1654                         tg3_readphy(tp, MII_BMCR, &bmcr);
1655                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
1656                                 continue;
1657                         if (bmcr && bmcr != 0x7fff)
1658                                 break;
1659                         udelay(10);
1660                 }
1661
1662                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1663                         if (bmcr & BMCR_ANENABLE) {
1664                                 current_link_up = 1;
1665
1666                                 /* Force autoneg restart if we are exiting
1667                                  * low power mode.
1668                                  */
1669                                 if (!tg3_copper_is_advertising_all(tp))
1670                                         current_link_up = 0;
1671                         } else {
1672                                 current_link_up = 0;
1673                         }
1674                 } else {
1675                         if (!(bmcr & BMCR_ANENABLE) &&
1676                             tp->link_config.speed == current_speed &&
1677                             tp->link_config.duplex == current_duplex) {
1678                                 current_link_up = 1;
1679                         } else {
1680                                 current_link_up = 0;
1681                         }
1682                 }
1683
1684                 tp->link_config.active_speed = current_speed;
1685                 tp->link_config.active_duplex = current_duplex;
1686         }
1687
1688         if (current_link_up == 1 &&
1689             (tp->link_config.active_duplex == DUPLEX_FULL) &&
1690             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1691                 u32 local_adv, remote_adv;
1692
1693                 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1694                         local_adv = 0;
1695                 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1696
1697                 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1698                         remote_adv = 0;
1699
1700                 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1701
1702                 /* If we are not advertising full pause capability,
1703                  * something is wrong.  Bring the link down and reconfigure.
1704                  */
1705                 if (local_adv != ADVERTISE_PAUSE_CAP) {
1706                         current_link_up = 0;
1707                 } else {
1708                         tg3_setup_flow_control(tp, local_adv, remote_adv);
1709                 }
1710         }
1711 relink:
1712         if (current_link_up == 0) {
1713                 u32 tmp;
1714
1715                 tg3_phy_copper_begin(tp);
1716
1717                 tg3_readphy(tp, MII_BMSR, &tmp);
1718                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1719                     (tmp & BMSR_LSTATUS))
1720                         current_link_up = 1;
1721         }
1722
1723         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1724         if (current_link_up == 1) {
1725                 if (tp->link_config.active_speed == SPEED_100 ||
1726                     tp->link_config.active_speed == SPEED_10)
1727                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1728                 else
1729                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1730         } else
1731                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1732
1733         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1734         if (tp->link_config.active_duplex == DUPLEX_HALF)
1735                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1736
1737         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1738         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1739                 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1740                     (current_link_up == 1 &&
1741                      tp->link_config.active_speed == SPEED_10))
1742                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1743         } else {
1744                 if (current_link_up == 1)
1745                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1746         }
1747
1748         /* ??? Without this setting Netgear GA302T PHY does not
1749          * ??? send/receive packets...
1750          */
1751         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
1752             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
1753                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
1754                 tw32_f(MAC_MI_MODE, tp->mi_mode);
1755                 udelay(80);
1756         }
1757
1758         tw32_f(MAC_MODE, tp->mac_mode);
1759         udelay(40);
1760
1761         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
1762                 /* Polled via timer. */
1763                 tw32_f(MAC_EVENT, 0);
1764         } else {
1765                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
1766         }
1767         udelay(40);
1768
1769         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
1770             current_link_up == 1 &&
1771             tp->link_config.active_speed == SPEED_1000 &&
1772             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
1773              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
1774                 udelay(120);
1775                 tw32_f(MAC_STATUS,
1776                      (MAC_STATUS_SYNC_CHANGED |
1777                       MAC_STATUS_CFG_CHANGED));
1778                 udelay(40);
1779                 tg3_write_mem(tp,
1780                               NIC_SRAM_FIRMWARE_MBOX,
1781                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
1782         }
1783
1784         if (current_link_up != netif_carrier_ok(tp->dev)) {
1785                 if (current_link_up)
1786                         netif_carrier_on(tp->dev);
1787                 else
1788                         netif_carrier_off(tp->dev);
1789                 tg3_link_report(tp);
1790         }
1791
1792         return 0;
1793 }
1794
1795 struct tg3_fiber_aneginfo {
1796         int state;
1797 #define ANEG_STATE_UNKNOWN              0
1798 #define ANEG_STATE_AN_ENABLE            1
1799 #define ANEG_STATE_RESTART_INIT         2
1800 #define ANEG_STATE_RESTART              3
1801 #define ANEG_STATE_DISABLE_LINK_OK      4
1802 #define ANEG_STATE_ABILITY_DETECT_INIT  5
1803 #define ANEG_STATE_ABILITY_DETECT       6
1804 #define ANEG_STATE_ACK_DETECT_INIT      7
1805 #define ANEG_STATE_ACK_DETECT           8
1806 #define ANEG_STATE_COMPLETE_ACK_INIT    9
1807 #define ANEG_STATE_COMPLETE_ACK         10
1808 #define ANEG_STATE_IDLE_DETECT_INIT     11
1809 #define ANEG_STATE_IDLE_DETECT          12
1810 #define ANEG_STATE_LINK_OK              13
1811 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
1812 #define ANEG_STATE_NEXT_PAGE_WAIT       15
1813
1814         u32 flags;
1815 #define MR_AN_ENABLE            0x00000001
1816 #define MR_RESTART_AN           0x00000002
1817 #define MR_AN_COMPLETE          0x00000004
1818 #define MR_PAGE_RX              0x00000008
1819 #define MR_NP_LOADED            0x00000010
1820 #define MR_TOGGLE_TX            0x00000020
1821 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
1822 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
1823 #define MR_LP_ADV_SYM_PAUSE     0x00000100
1824 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
1825 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
1826 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
1827 #define MR_LP_ADV_NEXT_PAGE     0x00001000
1828 #define MR_TOGGLE_RX            0x00002000
1829 #define MR_NP_RX                0x00004000
1830
1831 #define MR_LINK_OK              0x80000000
1832
1833         unsigned long link_time, cur_time;
1834
1835         u32 ability_match_cfg;
1836         int ability_match_count;
1837
1838         char ability_match, idle_match, ack_match;
1839
1840         u32 txconfig, rxconfig;
1841 #define ANEG_CFG_NP             0x00000080
1842 #define ANEG_CFG_ACK            0x00000040
1843 #define ANEG_CFG_RF2            0x00000020
1844 #define ANEG_CFG_RF1            0x00000010
1845 #define ANEG_CFG_PS2            0x00000001
1846 #define ANEG_CFG_PS1            0x00008000
1847 #define ANEG_CFG_HD             0x00004000
1848 #define ANEG_CFG_FD             0x00002000
1849 #define ANEG_CFG_INVAL          0x00001f06
1850
1851 };
1852 #define ANEG_OK         0
1853 #define ANEG_DONE       1
1854 #define ANEG_TIMER_ENAB 2
1855 #define ANEG_FAILED     -1
1856
1857 #define ANEG_STATE_SETTLE_TIME  10000
1858
1859 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
1860                                    struct tg3_fiber_aneginfo *ap)
1861 {
1862         unsigned long delta;
1863         u32 rx_cfg_reg;
1864         int ret;
1865
1866         if (ap->state == ANEG_STATE_UNKNOWN) {
1867                 ap->rxconfig = 0;
1868                 ap->link_time = 0;
1869                 ap->cur_time = 0;
1870                 ap->ability_match_cfg = 0;
1871                 ap->ability_match_count = 0;
1872                 ap->ability_match = 0;
1873                 ap->idle_match = 0;
1874                 ap->ack_match = 0;
1875         }
1876         ap->cur_time++;
1877
1878         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
1879                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
1880
1881                 if (rx_cfg_reg != ap->ability_match_cfg) {
1882                         ap->ability_match_cfg = rx_cfg_reg;
1883                         ap->ability_match = 0;
1884                         ap->ability_match_count = 0;
1885                 } else {
1886                         if (++ap->ability_match_count > 1) {
1887                                 ap->ability_match = 1;
1888                                 ap->ability_match_cfg = rx_cfg_reg;
1889                         }
1890                 }
1891                 if (rx_cfg_reg & ANEG_CFG_ACK)
1892                         ap->ack_match = 1;
1893                 else
1894                         ap->ack_match = 0;
1895
1896                 ap->idle_match = 0;
1897         } else {
1898                 ap->idle_match = 1;
1899                 ap->ability_match_cfg = 0;
1900                 ap->ability_match_count = 0;
1901                 ap->ability_match = 0;
1902                 ap->ack_match = 0;
1903
1904                 rx_cfg_reg = 0;
1905         }
1906
1907         ap->rxconfig = rx_cfg_reg;
1908         ret = ANEG_OK;
1909
1910         switch(ap->state) {
1911         case ANEG_STATE_UNKNOWN:
1912                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
1913                         ap->state = ANEG_STATE_AN_ENABLE;
1914
1915                 /* fallthru */
1916         case ANEG_STATE_AN_ENABLE:
1917                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
1918                 if (ap->flags & MR_AN_ENABLE) {
1919                         ap->link_time = 0;
1920                         ap->cur_time = 0;
1921                         ap->ability_match_cfg = 0;
1922                         ap->ability_match_count = 0;
1923                         ap->ability_match = 0;
1924                         ap->idle_match = 0;
1925                         ap->ack_match = 0;
1926
1927                         ap->state = ANEG_STATE_RESTART_INIT;
1928                 } else {
1929                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
1930                 }
1931                 break;
1932
1933         case ANEG_STATE_RESTART_INIT:
1934                 ap->link_time = ap->cur_time;
1935                 ap->flags &= ~(MR_NP_LOADED);
1936                 ap->txconfig = 0;
1937                 tw32(MAC_TX_AUTO_NEG, 0);
1938                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1939                 tw32_f(MAC_MODE, tp->mac_mode);
1940                 udelay(40);
1941
1942                 ret = ANEG_TIMER_ENAB;
1943                 ap->state = ANEG_STATE_RESTART;
1944
1945                 /* fallthru */
1946         case ANEG_STATE_RESTART:
1947                 delta = ap->cur_time - ap->link_time;
1948                 if (delta > ANEG_STATE_SETTLE_TIME) {
1949                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
1950                 } else {
1951                         ret = ANEG_TIMER_ENAB;
1952                 }
1953                 break;
1954
1955         case ANEG_STATE_DISABLE_LINK_OK:
1956                 ret = ANEG_DONE;
1957                 break;
1958
1959         case ANEG_STATE_ABILITY_DETECT_INIT:
1960                 ap->flags &= ~(MR_TOGGLE_TX);
1961                 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
1962                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1963                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1964                 tw32_f(MAC_MODE, tp->mac_mode);
1965                 udelay(40);
1966
1967                 ap->state = ANEG_STATE_ABILITY_DETECT;
1968                 break;
1969
1970         case ANEG_STATE_ABILITY_DETECT:
1971                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
1972                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
1973                 }
1974                 break;
1975
1976         case ANEG_STATE_ACK_DETECT_INIT:
1977                 ap->txconfig |= ANEG_CFG_ACK;
1978                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1979                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1980                 tw32_f(MAC_MODE, tp->mac_mode);
1981                 udelay(40);
1982
1983                 ap->state = ANEG_STATE_ACK_DETECT;
1984
1985                 /* fallthru */
1986         case ANEG_STATE_ACK_DETECT:
1987                 if (ap->ack_match != 0) {
1988                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
1989                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
1990                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
1991                         } else {
1992                                 ap->state = ANEG_STATE_AN_ENABLE;
1993                         }
1994                 } else if (ap->ability_match != 0 &&
1995                            ap->rxconfig == 0) {
1996                         ap->state = ANEG_STATE_AN_ENABLE;
1997                 }
1998                 break;
1999
2000         case ANEG_STATE_COMPLETE_ACK_INIT:
2001                 if (ap->rxconfig & ANEG_CFG_INVAL) {
2002                         ret = ANEG_FAILED;
2003                         break;
2004                 }
2005                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2006                                MR_LP_ADV_HALF_DUPLEX |
2007                                MR_LP_ADV_SYM_PAUSE |
2008                                MR_LP_ADV_ASYM_PAUSE |
2009                                MR_LP_ADV_REMOTE_FAULT1 |
2010                                MR_LP_ADV_REMOTE_FAULT2 |
2011                                MR_LP_ADV_NEXT_PAGE |
2012                                MR_TOGGLE_RX |
2013                                MR_NP_RX);
2014                 if (ap->rxconfig & ANEG_CFG_FD)
2015                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2016                 if (ap->rxconfig & ANEG_CFG_HD)
2017                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2018                 if (ap->rxconfig & ANEG_CFG_PS1)
2019                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
2020                 if (ap->rxconfig & ANEG_CFG_PS2)
2021                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2022                 if (ap->rxconfig & ANEG_CFG_RF1)
2023                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2024                 if (ap->rxconfig & ANEG_CFG_RF2)
2025                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2026                 if (ap->rxconfig & ANEG_CFG_NP)
2027                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
2028
2029                 ap->link_time = ap->cur_time;
2030
2031                 ap->flags ^= (MR_TOGGLE_TX);
2032                 if (ap->rxconfig & 0x0008)
2033                         ap->flags |= MR_TOGGLE_RX;
2034                 if (ap->rxconfig & ANEG_CFG_NP)
2035                         ap->flags |= MR_NP_RX;
2036                 ap->flags |= MR_PAGE_RX;
2037
2038                 ap->state = ANEG_STATE_COMPLETE_ACK;
2039                 ret = ANEG_TIMER_ENAB;
2040                 break;
2041
2042         case ANEG_STATE_COMPLETE_ACK:
2043                 if (ap->ability_match != 0 &&
2044                     ap->rxconfig == 0) {
2045                         ap->state = ANEG_STATE_AN_ENABLE;
2046                         break;
2047                 }
2048                 delta = ap->cur_time - ap->link_time;
2049                 if (delta > ANEG_STATE_SETTLE_TIME) {
2050                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2051                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2052                         } else {
2053                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2054                                     !(ap->flags & MR_NP_RX)) {
2055                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2056                                 } else {
2057                                         ret = ANEG_FAILED;
2058                                 }
2059                         }
2060                 }
2061                 break;
2062
2063         case ANEG_STATE_IDLE_DETECT_INIT:
2064                 ap->link_time = ap->cur_time;
2065                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2066                 tw32_f(MAC_MODE, tp->mac_mode);
2067                 udelay(40);
2068
2069                 ap->state = ANEG_STATE_IDLE_DETECT;
2070                 ret = ANEG_TIMER_ENAB;
2071                 break;
2072
2073         case ANEG_STATE_IDLE_DETECT:
2074                 if (ap->ability_match != 0 &&
2075                     ap->rxconfig == 0) {
2076                         ap->state = ANEG_STATE_AN_ENABLE;
2077                         break;
2078                 }
2079                 delta = ap->cur_time - ap->link_time;
2080                 if (delta > ANEG_STATE_SETTLE_TIME) {
2081                         /* XXX another gem from the Broadcom driver :( */
2082                         ap->state = ANEG_STATE_LINK_OK;
2083                 }
2084                 break;
2085
2086         case ANEG_STATE_LINK_OK:
2087                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2088                 ret = ANEG_DONE;
2089                 break;
2090
2091         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2092                 /* ??? unimplemented */
2093                 break;
2094
2095         case ANEG_STATE_NEXT_PAGE_WAIT:
2096                 /* ??? unimplemented */
2097                 break;
2098
2099         default:
2100                 ret = ANEG_FAILED;
2101                 break;
2102         };
2103
2104         return ret;
2105 }
2106
2107 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2108 {
2109         int res = 0;
2110         struct tg3_fiber_aneginfo aninfo;
2111         int status = ANEG_FAILED;
2112         unsigned int tick;
2113         u32 tmp;
2114
2115         tw32_f(MAC_TX_AUTO_NEG, 0);
2116
2117         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2118         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2119         udelay(40);
2120
2121         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2122         udelay(40);
2123
2124         memset(&aninfo, 0, sizeof(aninfo));
2125         aninfo.flags |= MR_AN_ENABLE;
2126         aninfo.state = ANEG_STATE_UNKNOWN;
2127         aninfo.cur_time = 0;
2128         tick = 0;
2129         while (++tick < 195000) {
2130                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2131                 if (status == ANEG_DONE || status == ANEG_FAILED)
2132                         break;
2133
2134                 udelay(1);
2135         }
2136
2137         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2138         tw32_f(MAC_MODE, tp->mac_mode);
2139         udelay(40);
2140
2141         *flags = aninfo.flags;
2142
2143         if (status == ANEG_DONE &&
2144             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2145                              MR_LP_ADV_FULL_DUPLEX)))
2146                 res = 1;
2147
2148         return res;
2149 }
2150
2151 static void tg3_init_bcm8002(struct tg3 *tp)
2152 {
2153         u32 mac_status = tr32(MAC_STATUS);
2154         int i;
2155
2156         /* Reset when initting first time or we have a link. */
2157         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2158             !(mac_status & MAC_STATUS_PCS_SYNCED))
2159                 return;
2160
2161         /* Set PLL lock range. */
2162         tg3_writephy(tp, 0x16, 0x8007);
2163
2164         /* SW reset */
2165         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2166
2167         /* Wait for reset to complete. */
2168         /* XXX schedule_timeout() ... */
2169         for (i = 0; i < 500; i++)
2170                 udelay(10);
2171
2172         /* Config mode; select PMA/Ch 1 regs. */
2173         tg3_writephy(tp, 0x10, 0x8411);
2174
2175         /* Enable auto-lock and comdet, select txclk for tx. */
2176         tg3_writephy(tp, 0x11, 0x0a10);
2177
2178         tg3_writephy(tp, 0x18, 0x00a0);
2179         tg3_writephy(tp, 0x16, 0x41ff);
2180
2181         /* Assert and deassert POR. */
2182         tg3_writephy(tp, 0x13, 0x0400);
2183         udelay(40);
2184         tg3_writephy(tp, 0x13, 0x0000);
2185
2186         tg3_writephy(tp, 0x11, 0x0a50);
2187         udelay(40);
2188         tg3_writephy(tp, 0x11, 0x0a10);
2189
2190         /* Wait for signal to stabilize */
2191         /* XXX schedule_timeout() ... */
2192         for (i = 0; i < 15000; i++)
2193                 udelay(10);
2194
2195         /* Deselect the channel register so we can read the PHYID
2196          * later.
2197          */
2198         tg3_writephy(tp, 0x10, 0x8011);
2199 }
2200
2201 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2202 {
2203         u32 sg_dig_ctrl, sg_dig_status;
2204         u32 serdes_cfg, expected_sg_dig_ctrl;
2205         int workaround, port_a;
2206         int current_link_up;
2207
2208         serdes_cfg = 0;
2209         expected_sg_dig_ctrl = 0;
2210         workaround = 0;
2211         port_a = 1;
2212         current_link_up = 0;
2213
2214         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2215             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2216                 workaround = 1;
2217                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2218                         port_a = 0;
2219
2220                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2221                 /* preserve bits 20-23 for voltage regulator */
2222                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2223         }
2224
2225         sg_dig_ctrl = tr32(SG_DIG_CTRL);
2226
2227         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2228                 if (sg_dig_ctrl & (1 << 31)) {
2229                         if (workaround) {
2230                                 u32 val = serdes_cfg;
2231
2232                                 if (port_a)
2233                                         val |= 0xc010000;
2234                                 else
2235                                         val |= 0x4010000;
2236                                 tw32_f(MAC_SERDES_CFG, val);
2237                         }
2238                         tw32_f(SG_DIG_CTRL, 0x01388400);
2239                 }
2240                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2241                         tg3_setup_flow_control(tp, 0, 0);
2242                         current_link_up = 1;
2243                 }
2244                 goto out;
2245         }
2246
2247         /* Want auto-negotiation.  */
2248         expected_sg_dig_ctrl = 0x81388400;
2249
2250         /* Pause capability */
2251         expected_sg_dig_ctrl |= (1 << 11);
2252
2253         /* Asymettric pause */
2254         expected_sg_dig_ctrl |= (1 << 12);
2255
2256         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2257                 if (workaround)
2258                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2259                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2260                 udelay(5);
2261                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2262
2263                 tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2264         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2265                                  MAC_STATUS_SIGNAL_DET)) {
2266                 int i;
2267
2268                 /* Giver time to negotiate (~200ms) */
2269                 for (i = 0; i < 40000; i++) {
2270                         sg_dig_status = tr32(SG_DIG_STATUS);
2271                         if (sg_dig_status & (0x3))
2272                                 break;
2273                         udelay(5);
2274                 }
2275                 mac_status = tr32(MAC_STATUS);
2276
2277                 if ((sg_dig_status & (1 << 1)) &&
2278                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
2279                         u32 local_adv, remote_adv;
2280
2281                         local_adv = ADVERTISE_PAUSE_CAP;
2282                         remote_adv = 0;
2283                         if (sg_dig_status & (1 << 19))
2284                                 remote_adv |= LPA_PAUSE_CAP;
2285                         if (sg_dig_status & (1 << 20))
2286                                 remote_adv |= LPA_PAUSE_ASYM;
2287
2288                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2289                         current_link_up = 1;
2290                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2291                 } else if (!(sg_dig_status & (1 << 1))) {
2292                         if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED)
2293                                 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2294                         else {
2295                                 if (workaround) {
2296                                         u32 val = serdes_cfg;
2297
2298                                         if (port_a)
2299                                                 val |= 0xc010000;
2300                                         else
2301                                                 val |= 0x4010000;
2302
2303                                         tw32_f(MAC_SERDES_CFG, val);
2304                                 }
2305
2306                                 tw32_f(SG_DIG_CTRL, 0x01388400);
2307                                 udelay(40);
2308
2309                                 /* Link parallel detection - link is up */
2310                                 /* only if we have PCS_SYNC and not */
2311                                 /* receiving config code words */
2312                                 mac_status = tr32(MAC_STATUS);
2313                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2314                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
2315                                         tg3_setup_flow_control(tp, 0, 0);
2316                                         current_link_up = 1;
2317                                 }
2318                         }
2319                 }
2320         }
2321
2322 out:
2323         return current_link_up;
2324 }
2325
2326 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2327 {
2328         int current_link_up = 0;
2329
2330         if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2331                 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2332                 goto out;
2333         }
2334
2335         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2336                 u32 flags;
2337                 int i;
2338
2339                 if (fiber_autoneg(tp, &flags)) {
2340                         u32 local_adv, remote_adv;
2341
2342                         local_adv = ADVERTISE_PAUSE_CAP;
2343                         remote_adv = 0;
2344                         if (flags & MR_LP_ADV_SYM_PAUSE)
2345                                 remote_adv |= LPA_PAUSE_CAP;
2346                         if (flags & MR_LP_ADV_ASYM_PAUSE)
2347                                 remote_adv |= LPA_PAUSE_ASYM;
2348
2349                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2350
2351                         tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2352                         current_link_up = 1;
2353                 }
2354                 for (i = 0; i < 30; i++) {
2355                         udelay(20);
2356                         tw32_f(MAC_STATUS,
2357                                (MAC_STATUS_SYNC_CHANGED |
2358                                 MAC_STATUS_CFG_CHANGED));
2359                         udelay(40);
2360                         if ((tr32(MAC_STATUS) &
2361                              (MAC_STATUS_SYNC_CHANGED |
2362                               MAC_STATUS_CFG_CHANGED)) == 0)
2363                                 break;
2364                 }
2365
2366                 mac_status = tr32(MAC_STATUS);
2367                 if (current_link_up == 0 &&
2368                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
2369                     !(mac_status & MAC_STATUS_RCVD_CFG))
2370                         current_link_up = 1;
2371         } else {
2372                 /* Forcing 1000FD link up. */
2373                 current_link_up = 1;
2374                 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2375
2376                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2377                 udelay(40);
2378         }
2379
2380 out:
2381         return current_link_up;
2382 }
2383
2384 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2385 {
2386         u32 orig_pause_cfg;
2387         u16 orig_active_speed;
2388         u8 orig_active_duplex;
2389         u32 mac_status;
2390         int current_link_up;
2391         int i;
2392
2393         orig_pause_cfg =
2394                 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2395                                   TG3_FLAG_TX_PAUSE));
2396         orig_active_speed = tp->link_config.active_speed;
2397         orig_active_duplex = tp->link_config.active_duplex;
2398
2399         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2400             netif_carrier_ok(tp->dev) &&
2401             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2402                 mac_status = tr32(MAC_STATUS);
2403                 mac_status &= (MAC_STATUS_PCS_SYNCED |
2404                                MAC_STATUS_SIGNAL_DET |
2405                                MAC_STATUS_CFG_CHANGED |
2406                                MAC_STATUS_RCVD_CFG);
2407                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2408                                    MAC_STATUS_SIGNAL_DET)) {
2409                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2410                                             MAC_STATUS_CFG_CHANGED));
2411                         return 0;
2412                 }
2413         }
2414
2415         tw32_f(MAC_TX_AUTO_NEG, 0);
2416
2417         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2418         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2419         tw32_f(MAC_MODE, tp->mac_mode);
2420         udelay(40);
2421
2422         if (tp->phy_id == PHY_ID_BCM8002)
2423                 tg3_init_bcm8002(tp);
2424
2425         /* Enable link change event even when serdes polling.  */
2426         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2427         udelay(40);
2428
2429         current_link_up = 0;
2430         mac_status = tr32(MAC_STATUS);
2431
2432         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2433                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2434         else
2435                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2436
2437         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2438         tw32_f(MAC_MODE, tp->mac_mode);
2439         udelay(40);
2440
2441         tp->hw_status->status =
2442                 (SD_STATUS_UPDATED |
2443                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2444
2445         for (i = 0; i < 100; i++) {
2446                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2447                                     MAC_STATUS_CFG_CHANGED));
2448                 udelay(5);
2449                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2450                                          MAC_STATUS_CFG_CHANGED)) == 0)
2451                         break;
2452         }
2453
2454         mac_status = tr32(MAC_STATUS);
2455         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2456                 current_link_up = 0;
2457                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2458                         tw32_f(MAC_MODE, (tp->mac_mode |
2459                                           MAC_MODE_SEND_CONFIGS));
2460                         udelay(1);
2461                         tw32_f(MAC_MODE, tp->mac_mode);
2462                 }
2463         }
2464
2465         if (current_link_up == 1) {
2466                 tp->link_config.active_speed = SPEED_1000;
2467                 tp->link_config.active_duplex = DUPLEX_FULL;
2468                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2469                                     LED_CTRL_LNKLED_OVERRIDE |
2470                                     LED_CTRL_1000MBPS_ON));
2471         } else {
2472                 tp->link_config.active_speed = SPEED_INVALID;
2473                 tp->link_config.active_duplex = DUPLEX_INVALID;
2474                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2475                                     LED_CTRL_LNKLED_OVERRIDE |
2476                                     LED_CTRL_TRAFFIC_OVERRIDE));
2477         }
2478
2479         if (current_link_up != netif_carrier_ok(tp->dev)) {
2480                 if (current_link_up)
2481                         netif_carrier_on(tp->dev);
2482                 else
2483                         netif_carrier_off(tp->dev);
2484                 tg3_link_report(tp);
2485         } else {
2486                 u32 now_pause_cfg =
2487                         tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2488                                          TG3_FLAG_TX_PAUSE);
2489                 if (orig_pause_cfg != now_pause_cfg ||
2490                     orig_active_speed != tp->link_config.active_speed ||
2491                     orig_active_duplex != tp->link_config.active_duplex)
2492                         tg3_link_report(tp);
2493         }
2494
2495         return 0;
2496 }
2497
2498 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2499 {
2500         int err;
2501
2502         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2503                 err = tg3_setup_fiber_phy(tp, force_reset);
2504         } else {
2505                 err = tg3_setup_copper_phy(tp, force_reset);
2506         }
2507
2508         if (tp->link_config.active_speed == SPEED_1000 &&
2509             tp->link_config.active_duplex == DUPLEX_HALF)
2510                 tw32(MAC_TX_LENGTHS,
2511                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2512                       (6 << TX_LENGTHS_IPG_SHIFT) |
2513                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2514         else
2515                 tw32(MAC_TX_LENGTHS,
2516                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2517                       (6 << TX_LENGTHS_IPG_SHIFT) |
2518                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2519
2520         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2521                 if (netif_carrier_ok(tp->dev)) {
2522                         tw32(HOSTCC_STAT_COAL_TICKS,
2523                              tp->coal.stats_block_coalesce_usecs);
2524                 } else {
2525                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
2526                 }
2527         }
2528
2529         return err;
2530 }
2531
2532 /* Tigon3 never reports partial packet sends.  So we do not
2533  * need special logic to handle SKBs that have not had all
2534  * of their frags sent yet, like SunGEM does.
2535  */
2536 static void tg3_tx(struct tg3 *tp)
2537 {
2538         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
2539         u32 sw_idx = tp->tx_cons;
2540
2541         while (sw_idx != hw_idx) {
2542                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
2543                 struct sk_buff *skb = ri->skb;
2544                 int i;
2545
2546                 if (unlikely(skb == NULL))
2547                         BUG();
2548
2549                 pci_unmap_single(tp->pdev,
2550                                  pci_unmap_addr(ri, mapping),
2551                                  skb_headlen(skb),
2552                                  PCI_DMA_TODEVICE);
2553
2554                 ri->skb = NULL;
2555
2556                 sw_idx = NEXT_TX(sw_idx);
2557
2558                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2559                         if (unlikely(sw_idx == hw_idx))
2560                                 BUG();
2561
2562                         ri = &tp->tx_buffers[sw_idx];
2563                         if (unlikely(ri->skb != NULL))
2564                                 BUG();
2565
2566                         pci_unmap_page(tp->pdev,
2567                                        pci_unmap_addr(ri, mapping),
2568                                        skb_shinfo(skb)->frags[i].size,
2569                                        PCI_DMA_TODEVICE);
2570
2571                         sw_idx = NEXT_TX(sw_idx);
2572                 }
2573
2574                 dev_kfree_skb(skb);
2575         }
2576
2577         tp->tx_cons = sw_idx;
2578
2579         if (netif_queue_stopped(tp->dev) &&
2580             (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH))
2581                 netif_wake_queue(tp->dev);
2582 }
2583
2584 /* Returns size of skb allocated or < 0 on error.
2585  *
2586  * We only need to fill in the address because the other members
2587  * of the RX descriptor are invariant, see tg3_init_rings.
2588  *
2589  * Note the purposeful assymetry of cpu vs. chip accesses.  For
2590  * posting buffers we only dirty the first cache line of the RX
2591  * descriptor (containing the address).  Whereas for the RX status
2592  * buffers the cpu only reads the last cacheline of the RX descriptor
2593  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
2594  */
2595 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
2596                             int src_idx, u32 dest_idx_unmasked)
2597 {
2598         struct tg3_rx_buffer_desc *desc;
2599         struct ring_info *map, *src_map;
2600         struct sk_buff *skb;
2601         dma_addr_t mapping;
2602         int skb_size, dest_idx;
2603
2604         src_map = NULL;
2605         switch (opaque_key) {
2606         case RXD_OPAQUE_RING_STD:
2607                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
2608                 desc = &tp->rx_std[dest_idx];
2609                 map = &tp->rx_std_buffers[dest_idx];
2610                 if (src_idx >= 0)
2611                         src_map = &tp->rx_std_buffers[src_idx];
2612                 skb_size = RX_PKT_BUF_SZ;
2613                 break;
2614
2615         case RXD_OPAQUE_RING_JUMBO:
2616                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
2617                 desc = &tp->rx_jumbo[dest_idx];
2618                 map = &tp->rx_jumbo_buffers[dest_idx];
2619                 if (src_idx >= 0)
2620                         src_map = &tp->rx_jumbo_buffers[src_idx];
2621                 skb_size = RX_JUMBO_PKT_BUF_SZ;
2622                 break;
2623
2624         default:
2625                 return -EINVAL;
2626         };
2627
2628         /* Do not overwrite any of the map or rp information
2629          * until we are sure we can commit to a new buffer.
2630          *
2631          * Callers depend upon this behavior and assume that
2632          * we leave everything unchanged if we fail.
2633          */
2634         skb = dev_alloc_skb(skb_size);
2635         if (skb == NULL)
2636                 return -ENOMEM;
2637
2638         skb->dev = tp->dev;
2639         skb_reserve(skb, tp->rx_offset);
2640
2641         mapping = pci_map_single(tp->pdev, skb->data,
2642                                  skb_size - tp->rx_offset,
2643                                  PCI_DMA_FROMDEVICE);
2644
2645         map->skb = skb;
2646         pci_unmap_addr_set(map, mapping, mapping);
2647
2648         if (src_map != NULL)
2649                 src_map->skb = NULL;
2650
2651         desc->addr_hi = ((u64)mapping >> 32);
2652         desc->addr_lo = ((u64)mapping & 0xffffffff);
2653
2654         return skb_size;
2655 }
2656
2657 /* We only need to move over in the address because the other
2658  * members of the RX descriptor are invariant.  See notes above
2659  * tg3_alloc_rx_skb for full details.
2660  */
2661 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
2662                            int src_idx, u32 dest_idx_unmasked)
2663 {
2664         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
2665         struct ring_info *src_map, *dest_map;
2666         int dest_idx;
2667
2668         switch (opaque_key) {
2669         case RXD_OPAQUE_RING_STD:
2670                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
2671                 dest_desc = &tp->rx_std[dest_idx];
2672                 dest_map = &tp->rx_std_buffers[dest_idx];
2673                 src_desc = &tp->rx_std[src_idx];
2674                 src_map = &tp->rx_std_buffers[src_idx];
2675                 break;
2676
2677         case RXD_OPAQUE_RING_JUMBO:
2678                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
2679                 dest_desc = &tp->rx_jumbo[dest_idx];
2680                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
2681                 src_desc = &tp->rx_jumbo[src_idx];
2682                 src_map = &tp->rx_jumbo_buffers[src_idx];
2683                 break;
2684
2685         default:
2686                 return;
2687         };
2688
2689         dest_map->skb = src_map->skb;
2690         pci_unmap_addr_set(dest_map, mapping,
2691                            pci_unmap_addr(src_map, mapping));
2692         dest_desc->addr_hi = src_desc->addr_hi;
2693         dest_desc->addr_lo = src_desc->addr_lo;
2694
2695         src_map->skb = NULL;
2696 }
2697
2698 #if TG3_VLAN_TAG_USED
2699 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
2700 {
2701         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
2702 }
2703 #endif
2704
2705 /* The RX ring scheme is composed of multiple rings which post fresh
2706  * buffers to the chip, and one special ring the chip uses to report
2707  * status back to the host.
2708  *
2709  * The special ring reports the status of received packets to the
2710  * host.  The chip does not write into the original descriptor the
2711  * RX buffer was obtained from.  The chip simply takes the original
2712  * descriptor as provided by the host, updates the status and length
2713  * field, then writes this into the next status ring entry.
2714  *
2715  * Each ring the host uses to post buffers to the chip is described
2716  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
2717  * it is first placed into the on-chip ram.  When the packet's length
2718  * is known, it walks down the TG3_BDINFO entries to select the ring.
2719  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
2720  * which is within the range of the new packet's length is chosen.
2721  *
2722  * The "separate ring for rx status" scheme may sound queer, but it makes
2723  * sense from a cache coherency perspective.  If only the host writes
2724  * to the buffer post rings, and only the chip writes to the rx status
2725  * rings, then cache lines never move beyond shared-modified state.
2726  * If both the host and chip were to write into the same ring, cache line
2727  * eviction could occur since both entities want it in an exclusive state.
2728  */
2729 static int tg3_rx(struct tg3 *tp, int budget)
2730 {
2731         u32 work_mask;
2732         u32 sw_idx = tp->rx_rcb_ptr;
2733         u16 hw_idx;
2734         int received;
2735
2736         hw_idx = tp->hw_status->idx[0].rx_producer;
2737         /*
2738          * We need to order the read of hw_idx and the read of
2739          * the opaque cookie.
2740          */
2741         rmb();
2742         work_mask = 0;
2743         received = 0;
2744         while (sw_idx != hw_idx && budget > 0) {
2745                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
2746                 unsigned int len;
2747                 struct sk_buff *skb;
2748                 dma_addr_t dma_addr;
2749                 u32 opaque_key, desc_idx, *post_ptr;
2750
2751                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
2752                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
2753                 if (opaque_key == RXD_OPAQUE_RING_STD) {
2754                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
2755                                                   mapping);
2756                         skb = tp->rx_std_buffers[desc_idx].skb;
2757                         post_ptr = &tp->rx_std_ptr;
2758                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
2759                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
2760                                                   mapping);
2761                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
2762                         post_ptr = &tp->rx_jumbo_ptr;
2763                 }
2764                 else {
2765                         goto next_pkt_nopost;
2766                 }
2767
2768                 work_mask |= opaque_key;
2769
2770                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
2771                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
2772                 drop_it:
2773                         tg3_recycle_rx(tp, opaque_key,
2774                                        desc_idx, *post_ptr);
2775                 drop_it_no_recycle:
2776                         /* Other statistics kept track of by card. */
2777                         tp->net_stats.rx_dropped++;
2778                         goto next_pkt;
2779                 }
2780
2781                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
2782
2783                 if (len > RX_COPY_THRESHOLD
2784                         && tp->rx_offset == 2
2785                         /* rx_offset != 2 iff this is a 5701 card running
2786                          * in PCI-X mode [see tg3_get_invariants()] */
2787                 ) {
2788                         int skb_size;
2789
2790                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
2791                                                     desc_idx, *post_ptr);
2792                         if (skb_size < 0)
2793                                 goto drop_it;
2794
2795                         pci_unmap_single(tp->pdev, dma_addr,
2796                                          skb_size - tp->rx_offset,
2797                                          PCI_DMA_FROMDEVICE);
2798
2799                         skb_put(skb, len);
2800                 } else {
2801                         struct sk_buff *copy_skb;
2802
2803                         tg3_recycle_rx(tp, opaque_key,
2804                                        desc_idx, *post_ptr);
2805
2806                         copy_skb = dev_alloc_skb(len + 2);
2807                         if (copy_skb == NULL)
2808                                 goto drop_it_no_recycle;
2809
2810                         copy_skb->dev = tp->dev;
2811                         skb_reserve(copy_skb, 2);
2812                         skb_put(copy_skb, len);
2813                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
2814                         memcpy(copy_skb->data, skb->data, len);
2815                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
2816
2817                         /* We'll reuse the original ring buffer. */
2818                         skb = copy_skb;
2819                 }
2820
2821                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
2822                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
2823                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
2824                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
2825                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2826                 else
2827                         skb->ip_summed = CHECKSUM_NONE;
2828
2829                 skb->protocol = eth_type_trans(skb, tp->dev);
2830 #if TG3_VLAN_TAG_USED
2831                 if (tp->vlgrp != NULL &&
2832                     desc->type_flags & RXD_FLAG_VLAN) {
2833                         tg3_vlan_rx(tp, skb,
2834                                     desc->err_vlan & RXD_VLAN_MASK);
2835                 } else
2836 #endif
2837                         netif_receive_skb(skb);
2838
2839                 tp->dev->last_rx = jiffies;
2840                 received++;
2841                 budget--;
2842
2843 next_pkt:
2844                 (*post_ptr)++;
2845 next_pkt_nopost:
2846                 sw_idx++;
2847                 sw_idx %= TG3_RX_RCB_RING_SIZE(tp);
2848
2849                 /* Refresh hw_idx to see if there is new work */
2850                 if (sw_idx == hw_idx) {
2851                         hw_idx = tp->hw_status->idx[0].rx_producer;
2852                         rmb();
2853                 }
2854         }
2855
2856         /* ACK the status ring. */
2857         tp->rx_rcb_ptr = sw_idx;
2858         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
2859
2860         /* Refill RX ring(s). */
2861         if (work_mask & RXD_OPAQUE_RING_STD) {
2862                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
2863                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
2864                              sw_idx);
2865         }
2866         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
2867                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
2868                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
2869                              sw_idx);
2870         }
2871         mmiowb();
2872
2873         return received;
2874 }
2875
2876 static int tg3_poll(struct net_device *netdev, int *budget)
2877 {
2878         struct tg3 *tp = netdev_priv(netdev);
2879         struct tg3_hw_status *sblk = tp->hw_status;
2880         int done;
2881
2882         /* handle link change and other phy events */
2883         if (!(tp->tg3_flags &
2884               (TG3_FLAG_USE_LINKCHG_REG |
2885                TG3_FLAG_POLL_SERDES))) {
2886                 if (sblk->status & SD_STATUS_LINK_CHG) {
2887                         sblk->status = SD_STATUS_UPDATED |
2888                                 (sblk->status & ~SD_STATUS_LINK_CHG);
2889                         spin_lock(&tp->lock);
2890                         tg3_setup_phy(tp, 0);
2891                         spin_unlock(&tp->lock);
2892                 }
2893         }
2894
2895         /* run TX completion thread */
2896         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
2897                 spin_lock(&tp->tx_lock);
2898                 tg3_tx(tp);
2899                 spin_unlock(&tp->tx_lock);
2900         }
2901
2902         /* run RX thread, within the bounds set by NAPI.
2903          * All RX "locking" is done by ensuring outside
2904          * code synchronizes with dev->poll()
2905          */
2906         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
2907                 int orig_budget = *budget;
2908                 int work_done;
2909
2910                 if (orig_budget > netdev->quota)
2911                         orig_budget = netdev->quota;
2912
2913                 work_done = tg3_rx(tp, orig_budget);
2914
2915                 *budget -= work_done;
2916                 netdev->quota -= work_done;
2917         }
2918
2919         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
2920                 tp->last_tag = sblk->status_tag;
2921         rmb();
2922         sblk->status &= ~SD_STATUS_UPDATED;
2923
2924         /* if no more work, tell net stack and NIC we're done */
2925         done = !tg3_has_work(tp);
2926         if (done) {
2927                 spin_lock(&tp->lock);
2928                 netif_rx_complete(netdev);
2929                 tg3_restart_ints(tp);
2930                 spin_unlock(&tp->lock);
2931         }
2932
2933         return (done ? 0 : 1);
2934 }
2935
2936 static void tg3_irq_quiesce(struct tg3 *tp)
2937 {
2938         BUG_ON(tp->irq_sync);
2939
2940         tp->irq_sync = 1;
2941         smp_mb();
2942
2943         synchronize_irq(tp->pdev->irq);
2944 }
2945
2946 static inline int tg3_irq_sync(struct tg3 *tp)
2947 {
2948         return tp->irq_sync;
2949 }
2950
2951 /* Fully shutdown all tg3 driver activity elsewhere in the system.
2952  * If irq_sync is non-zero, then the IRQ handler must be synchronized
2953  * with as well.  Most of the time, this is not necessary except when
2954  * shutting down the device.
2955  */
2956 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
2957 {
2958         if (irq_sync)
2959                 tg3_irq_quiesce(tp);
2960         spin_lock_bh(&tp->lock);
2961         spin_lock(&tp->tx_lock);
2962 }
2963
2964 static inline void tg3_full_unlock(struct tg3 *tp)
2965 {
2966         spin_unlock(&tp->tx_lock);
2967         spin_unlock_bh(&tp->lock);
2968 }
2969
2970 /* MSI ISR - No need to check for interrupt sharing and no need to
2971  * flush status block and interrupt mailbox. PCI ordering rules
2972  * guarantee that MSI will arrive after the status block.
2973  */
2974 static irqreturn_t tg3_msi(int irq, void *dev_id, struct pt_regs *regs)
2975 {
2976         struct net_device *dev = dev_id;
2977         struct tg3 *tp = netdev_priv(dev);
2978         struct tg3_hw_status *sblk = tp->hw_status;
2979
2980         /*
2981          * Writing any value to intr-mbox-0 clears PCI INTA# and
2982          * chip-internal interrupt pending events.
2983          * Writing non-zero to intr-mbox-0 additional tells the
2984          * NIC to stop sending us irqs, engaging "in-intr-handler"
2985          * event coalescing.
2986          */
2987         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
2988         tp->last_tag = sblk->status_tag;
2989         rmb();
2990         if (tg3_irq_sync(tp))
2991                 goto out;
2992         sblk->status &= ~SD_STATUS_UPDATED;
2993         if (likely(tg3_has_work(tp)))
2994                 netif_rx_schedule(dev);         /* schedule NAPI poll */
2995         else {
2996                 /* No work, re-enable interrupts.  */
2997                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
2998                              tp->last_tag << 24);
2999         }
3000 out:
3001         return IRQ_RETVAL(1);
3002 }
3003
3004 static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
3005 {
3006         struct net_device *dev = dev_id;
3007         struct tg3 *tp = netdev_priv(dev);
3008         struct tg3_hw_status *sblk = tp->hw_status;
3009         unsigned int handled = 1;
3010
3011         /* In INTx mode, it is possible for the interrupt to arrive at
3012          * the CPU before the status block posted prior to the interrupt.
3013          * Reading the PCI State register will confirm whether the
3014          * interrupt is ours and will flush the status block.
3015          */
3016         if ((sblk->status & SD_STATUS_UPDATED) ||
3017             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3018                 /*
3019                  * Writing any value to intr-mbox-0 clears PCI INTA# and
3020                  * chip-internal interrupt pending events.
3021                  * Writing non-zero to intr-mbox-0 additional tells the
3022                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3023                  * event coalescing.
3024                  */
3025                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3026                              0x00000001);
3027                 if (tg3_irq_sync(tp))
3028                         goto out;
3029                 sblk->status &= ~SD_STATUS_UPDATED;
3030                 if (likely(tg3_has_work(tp)))
3031                         netif_rx_schedule(dev);         /* schedule NAPI poll */
3032                 else {
3033                         /* No work, shared interrupt perhaps?  re-enable
3034                          * interrupts, and flush that PCI write
3035                          */
3036                         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3037                                 0x00000000);
3038                         tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
3039                 }
3040         } else {        /* shared interrupt */
3041                 handled = 0;
3042         }
3043 out:
3044         return IRQ_RETVAL(handled);
3045 }
3046
3047 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id, struct pt_regs *regs)
3048 {
3049         struct net_device *dev = dev_id;
3050         struct tg3 *tp = netdev_priv(dev);
3051         struct tg3_hw_status *sblk = tp->hw_status;
3052         unsigned int handled = 1;
3053
3054         /* In INTx mode, it is possible for the interrupt to arrive at
3055          * the CPU before the status block posted prior to the interrupt.
3056          * Reading the PCI State register will confirm whether the
3057          * interrupt is ours and will flush the status block.
3058          */
3059         if ((sblk->status & SD_STATUS_UPDATED) ||
3060             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3061                 /*
3062                  * writing any value to intr-mbox-0 clears PCI INTA# and
3063                  * chip-internal interrupt pending events.
3064                  * writing non-zero to intr-mbox-0 additional tells the
3065                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3066                  * event coalescing.
3067                  */
3068                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3069                              0x00000001);
3070                 tp->last_tag = sblk->status_tag;
3071                 rmb();
3072                 if (tg3_irq_sync(tp))
3073                         goto out;
3074                 sblk->status &= ~SD_STATUS_UPDATED;
3075                 if (likely(tg3_has_work(tp)))
3076                         netif_rx_schedule(dev);         /* schedule NAPI poll */
3077                 else {
3078                         /* no work, shared interrupt perhaps?  re-enable
3079                          * interrupts, and flush that PCI write
3080                          */
3081                         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3082                                      tp->last_tag << 24);
3083                         tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
3084                 }
3085         } else {        /* shared interrupt */
3086                 handled = 0;
3087         }
3088 out:
3089         return IRQ_RETVAL(handled);
3090 }
3091
3092 /* ISR for interrupt test */
3093 static irqreturn_t tg3_test_isr(int irq, void *dev_id,
3094                 struct pt_regs *regs)
3095 {
3096         struct net_device *dev = dev_id;
3097         struct tg3 *tp = netdev_priv(dev);
3098         struct tg3_hw_status *sblk = tp->hw_status;
3099
3100         if (sblk->status & SD_STATUS_UPDATED) {
3101                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3102                              0x00000001);
3103                 return IRQ_RETVAL(1);
3104         }
3105         return IRQ_RETVAL(0);
3106 }
3107
3108 static int tg3_init_hw(struct tg3 *);
3109 static int tg3_halt(struct tg3 *, int, int);
3110
3111 #ifdef CONFIG_NET_POLL_CONTROLLER
3112 static void tg3_poll_controller(struct net_device *dev)
3113 {
3114         struct tg3 *tp = netdev_priv(dev);
3115
3116         tg3_interrupt(tp->pdev->irq, dev, NULL);
3117 }
3118 #endif
3119
3120 static void tg3_reset_task(void *_data)
3121 {
3122         struct tg3 *tp = _data;
3123         unsigned int restart_timer;
3124
3125         tg3_netif_stop(tp);
3126
3127         tg3_full_lock(tp, 1);
3128
3129         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3130         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3131
3132         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3133         tg3_init_hw(tp);
3134
3135         tg3_netif_start(tp);
3136
3137         tg3_full_unlock(tp);
3138
3139         if (restart_timer)
3140                 mod_timer(&tp->timer, jiffies + 1);
3141 }
3142
3143 static void tg3_tx_timeout(struct net_device *dev)
3144 {
3145         struct tg3 *tp = netdev_priv(dev);
3146
3147         printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3148                dev->name);
3149
3150         schedule_work(&tp->reset_task);
3151 }
3152
3153 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3154
3155 static int tigon3_4gb_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3156                                        u32 guilty_entry, int guilty_len,
3157                                        u32 last_plus_one, u32 *start, u32 mss)
3158 {
3159         struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3160         dma_addr_t new_addr;
3161         u32 entry = *start;
3162         int i;
3163
3164         if (!new_skb) {
3165                 dev_kfree_skb(skb);
3166                 return -1;
3167         }
3168
3169         /* New SKB is guaranteed to be linear. */
3170         entry = *start;
3171         new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3172                                   PCI_DMA_TODEVICE);
3173         tg3_set_txd(tp, entry, new_addr, new_skb->len,
3174                     (skb->ip_summed == CHECKSUM_HW) ?
3175                     TXD_FLAG_TCPUDP_CSUM : 0, 1 | (mss << 1));
3176         *start = NEXT_TX(entry);
3177
3178         /* Now clean up the sw ring entries. */
3179         i = 0;
3180         while (entry != last_plus_one) {
3181                 int len;
3182
3183                 if (i == 0)
3184                         len = skb_headlen(skb);
3185                 else
3186                         len = skb_shinfo(skb)->frags[i-1].size;
3187                 pci_unmap_single(tp->pdev,
3188                                  pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3189                                  len, PCI_DMA_TODEVICE);
3190                 if (i == 0) {
3191                         tp->tx_buffers[entry].skb = new_skb;
3192                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3193                 } else {
3194                         tp->tx_buffers[entry].skb = NULL;
3195                 }
3196                 entry = NEXT_TX(entry);
3197                 i++;
3198         }
3199
3200         dev_kfree_skb(skb);
3201
3202         return 0;
3203 }
3204
3205 static void tg3_set_txd(struct tg3 *tp, int entry,
3206                         dma_addr_t mapping, int len, u32 flags,
3207                         u32 mss_and_is_end)
3208 {
3209         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3210         int is_end = (mss_and_is_end & 0x1);
3211         u32 mss = (mss_and_is_end >> 1);
3212         u32 vlan_tag = 0;
3213
3214         if (is_end)
3215                 flags |= TXD_FLAG_END;
3216         if (flags & TXD_FLAG_VLAN) {
3217                 vlan_tag = flags >> 16;
3218                 flags &= 0xffff;
3219         }
3220         vlan_tag |= (mss << TXD_MSS_SHIFT);
3221
3222         txd->addr_hi = ((u64) mapping >> 32);
3223         txd->addr_lo = ((u64) mapping & 0xffffffff);
3224         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3225         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3226 }
3227
3228 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3229 {
3230         u32 base = (u32) mapping & 0xffffffff;
3231
3232         return ((base > 0xffffdcc0) &&
3233                 (base + len + 8 < base));
3234 }
3235
3236 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3237 {
3238         struct tg3 *tp = netdev_priv(dev);
3239         dma_addr_t mapping;
3240         unsigned int i;
3241         u32 len, entry, base_flags, mss;
3242         int would_hit_hwbug;
3243
3244         len = skb_headlen(skb);
3245
3246         /* No BH disabling for tx_lock here.  We are running in BH disabled
3247          * context and TX reclaim runs via tp->poll inside of a software
3248          * interrupt.  Furthermore, IRQ processing runs lockless so we have
3249          * no IRQ context deadlocks to worry about either.  Rejoice!
3250          */
3251         if (!spin_trylock(&tp->tx_lock))
3252                 return NETDEV_TX_LOCKED;
3253
3254         /* This is a hard error, log it. */
3255         if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3256                 netif_stop_queue(dev);
3257                 spin_unlock(&tp->tx_lock);
3258                 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
3259                        dev->name);
3260                 return NETDEV_TX_BUSY;
3261         }
3262
3263         entry = tp->tx_prod;
3264         base_flags = 0;
3265         if (skb->ip_summed == CHECKSUM_HW)
3266                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3267 #if TG3_TSO_SUPPORT != 0
3268         mss = 0;
3269         if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3270             (mss = skb_shinfo(skb)->tso_size) != 0) {
3271                 int tcp_opt_len, ip_tcp_len;
3272
3273                 if (skb_header_cloned(skb) &&
3274                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3275                         dev_kfree_skb(skb);
3276                         goto out_unlock;
3277                 }
3278
3279                 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3280                 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
3281
3282                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3283                                TXD_FLAG_CPU_POST_DMA);
3284
3285                 skb->nh.iph->check = 0;
3286                 skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len);
3287                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
3288                         skb->h.th->check = 0;
3289                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
3290                 }
3291                 else {
3292                         skb->h.th->check =
3293                                 ~csum_tcpudp_magic(skb->nh.iph->saddr,
3294                                                    skb->nh.iph->daddr,
3295                                                    0, IPPROTO_TCP, 0);
3296                 }
3297
3298                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
3299                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
3300                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3301                                 int tsflags;
3302
3303                                 tsflags = ((skb->nh.iph->ihl - 5) +
3304                                            (tcp_opt_len >> 2));
3305                                 mss |= (tsflags << 11);
3306                         }
3307                 } else {
3308                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3309                                 int tsflags;
3310
3311                                 tsflags = ((skb->nh.iph->ihl - 5) +
3312                                            (tcp_opt_len >> 2));
3313                                 base_flags |= tsflags << 12;
3314                         }
3315                 }
3316         }
3317 #else
3318         mss = 0;
3319 #endif
3320 #if TG3_VLAN_TAG_USED
3321         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3322                 base_flags |= (TXD_FLAG_VLAN |
3323                                (vlan_tx_tag_get(skb) << 16));
3324 #endif
3325
3326         /* Queue skb data, a.k.a. the main skb fragment. */
3327         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3328
3329         tp->tx_buffers[entry].skb = skb;
3330         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3331
3332         would_hit_hwbug = 0;
3333
3334         if (tg3_4g_overflow_test(mapping, len))
3335                 would_hit_hwbug = entry + 1;
3336
3337         tg3_set_txd(tp, entry, mapping, len, base_flags,
3338                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3339
3340         entry = NEXT_TX(entry);
3341
3342         /* Now loop through additional data fragments, and queue them. */
3343         if (skb_shinfo(skb)->nr_frags > 0) {
3344                 unsigned int i, last;
3345
3346                 last = skb_shinfo(skb)->nr_frags - 1;
3347                 for (i = 0; i <= last; i++) {
3348                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3349
3350                         len = frag->size;
3351                         mapping = pci_map_page(tp->pdev,
3352                                                frag->page,
3353                                                frag->page_offset,
3354                                                len, PCI_DMA_TODEVICE);
3355
3356                         tp->tx_buffers[entry].skb = NULL;
3357                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3358
3359                         if (tg3_4g_overflow_test(mapping, len)) {
3360                                 /* Only one should match. */
3361                                 if (would_hit_hwbug)
3362                                         BUG();
3363                                 would_hit_hwbug = entry + 1;
3364                         }
3365
3366                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
3367                                 tg3_set_txd(tp, entry, mapping, len,
3368                                             base_flags, (i == last)|(mss << 1));
3369                         else
3370                                 tg3_set_txd(tp, entry, mapping, len,
3371                                             base_flags, (i == last));
3372
3373                         entry = NEXT_TX(entry);
3374                 }
3375         }
3376
3377         if (would_hit_hwbug) {
3378                 u32 last_plus_one = entry;
3379                 u32 start;
3380                 unsigned int len = 0;
3381
3382                 would_hit_hwbug -= 1;
3383                 entry = entry - 1 - skb_shinfo(skb)->nr_frags;
3384                 entry &= (TG3_TX_RING_SIZE - 1);
3385                 start = entry;
3386                 i = 0;
3387                 while (entry != last_plus_one) {
3388                         if (i == 0)
3389                                 len = skb_headlen(skb);
3390                         else
3391                                 len = skb_shinfo(skb)->frags[i-1].size;
3392
3393                         if (entry == would_hit_hwbug)
3394                                 break;
3395
3396                         i++;
3397                         entry = NEXT_TX(entry);
3398
3399                 }
3400
3401                 /* If the workaround fails due to memory/mapping
3402                  * failure, silently drop this packet.
3403                  */
3404                 if (tigon3_4gb_hwbug_workaround(tp, skb,
3405                                                 entry, len,
3406                                                 last_plus_one,
3407                                                 &start, mss))
3408                         goto out_unlock;
3409
3410                 entry = start;
3411         }
3412
3413         /* Packets are ready, update Tx producer idx local and on card. */
3414         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3415
3416         tp->tx_prod = entry;
3417         if (TX_BUFFS_AVAIL(tp) <= (MAX_SKB_FRAGS + 1))
3418                 netif_stop_queue(dev);
3419
3420 out_unlock:
3421         mmiowb();
3422         spin_unlock(&tp->tx_lock);
3423
3424         dev->trans_start = jiffies;
3425
3426         return NETDEV_TX_OK;
3427 }
3428
3429 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
3430                                int new_mtu)
3431 {
3432         dev->mtu = new_mtu;
3433
3434         if (new_mtu > ETH_DATA_LEN)
3435                 tp->tg3_flags |= TG3_FLAG_JUMBO_ENABLE;
3436         else
3437                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_ENABLE;
3438 }
3439
3440 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
3441 {
3442         struct tg3 *tp = netdev_priv(dev);
3443
3444         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
3445                 return -EINVAL;
3446
3447         if (!netif_running(dev)) {
3448                 /* We'll just catch it later when the
3449                  * device is up'd.
3450                  */
3451                 tg3_set_mtu(dev, tp, new_mtu);
3452                 return 0;
3453         }
3454
3455         tg3_netif_stop(tp);
3456
3457         tg3_full_lock(tp, 1);
3458
3459         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3460
3461         tg3_set_mtu(dev, tp, new_mtu);
3462
3463         tg3_init_hw(tp);
3464
3465         tg3_netif_start(tp);
3466
3467         tg3_full_unlock(tp);
3468
3469         return 0;
3470 }
3471
3472 /* Free up pending packets in all rx/tx rings.
3473  *
3474  * The chip has been shut down and the driver detached from
3475  * the networking, so no interrupts or new tx packets will
3476  * end up in the driver.  tp->{tx,}lock is not held and we are not
3477  * in an interrupt context and thus may sleep.
3478  */
3479 static void tg3_free_rings(struct tg3 *tp)
3480 {
3481         struct ring_info *rxp;
3482         int i;
3483
3484         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
3485                 rxp = &tp->rx_std_buffers[i];
3486
3487                 if (rxp->skb == NULL)
3488                         continue;
3489                 pci_unmap_single(tp->pdev,
3490                                  pci_unmap_addr(rxp, mapping),
3491                                  RX_PKT_BUF_SZ - tp->rx_offset,
3492                                  PCI_DMA_FROMDEVICE);
3493                 dev_kfree_skb_any(rxp->skb);
3494                 rxp->skb = NULL;
3495         }
3496
3497         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
3498                 rxp = &tp->rx_jumbo_buffers[i];
3499
3500                 if (rxp->skb == NULL)
3501                         continue;
3502                 pci_unmap_single(tp->pdev,
3503                                  pci_unmap_addr(rxp, mapping),
3504                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
3505                                  PCI_DMA_FROMDEVICE);
3506                 dev_kfree_skb_any(rxp->skb);
3507                 rxp->skb = NULL;
3508         }
3509
3510         for (i = 0; i < TG3_TX_RING_SIZE; ) {
3511                 struct tx_ring_info *txp;
3512                 struct sk_buff *skb;
3513                 int j;
3514
3515                 txp = &tp->tx_buffers[i];
3516                 skb = txp->skb;
3517
3518                 if (skb == NULL) {
3519                         i++;
3520                         continue;
3521                 }
3522
3523                 pci_unmap_single(tp->pdev,
3524                                  pci_unmap_addr(txp, mapping),
3525                                  skb_headlen(skb),
3526                                  PCI_DMA_TODEVICE);
3527                 txp->skb = NULL;
3528
3529                 i++;
3530
3531                 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
3532                         txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
3533                         pci_unmap_page(tp->pdev,
3534                                        pci_unmap_addr(txp, mapping),
3535                                        skb_shinfo(skb)->frags[j].size,
3536                                        PCI_DMA_TODEVICE);
3537                         i++;
3538                 }
3539
3540                 dev_kfree_skb_any(skb);
3541         }
3542 }
3543
3544 /* Initialize tx/rx rings for packet processing.
3545  *
3546  * The chip has been shut down and the driver detached from
3547  * the networking, so no interrupts or new tx packets will
3548  * end up in the driver.  tp->{tx,}lock are held and thus
3549  * we may not sleep.
3550  */
3551 static void tg3_init_rings(struct tg3 *tp)
3552 {
3553         u32 i;
3554
3555         /* Free up all the SKBs. */
3556         tg3_free_rings(tp);
3557
3558         /* Zero out all descriptors. */
3559         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
3560         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
3561         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
3562         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
3563
3564         /* Initialize invariants of the rings, we only set this
3565          * stuff once.  This works because the card does not
3566          * write into the rx buffer posting rings.
3567          */
3568         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
3569                 struct tg3_rx_buffer_desc *rxd;
3570
3571                 rxd = &tp->rx_std[i];
3572                 rxd->idx_len = (RX_PKT_BUF_SZ - tp->rx_offset - 64)
3573                         << RXD_LEN_SHIFT;
3574                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
3575                 rxd->opaque = (RXD_OPAQUE_RING_STD |
3576                                (i << RXD_OPAQUE_INDEX_SHIFT));
3577         }
3578
3579         if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) {
3580                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
3581                         struct tg3_rx_buffer_desc *rxd;
3582
3583                         rxd = &tp->rx_jumbo[i];
3584                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
3585                                 << RXD_LEN_SHIFT;
3586                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
3587                                 RXD_FLAG_JUMBO;
3588                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
3589                                (i << RXD_OPAQUE_INDEX_SHIFT));
3590                 }
3591         }
3592
3593         /* Now allocate fresh SKBs for each rx ring. */
3594         for (i = 0; i < tp->rx_pending; i++) {
3595                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD,
3596                                      -1, i) < 0)
3597                         break;
3598         }
3599
3600         if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) {
3601                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
3602                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
3603                                              -1, i) < 0)
3604                                 break;
3605                 }
3606         }
3607 }
3608
3609 /*
3610  * Must not be invoked with interrupt sources disabled and
3611  * the hardware shutdown down.
3612  */
3613 static void tg3_free_consistent(struct tg3 *tp)
3614 {
3615         if (tp->rx_std_buffers) {
3616                 kfree(tp->rx_std_buffers);
3617                 tp->rx_std_buffers = NULL;
3618         }
3619         if (tp->rx_std) {
3620                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
3621                                     tp->rx_std, tp->rx_std_mapping);
3622                 tp->rx_std = NULL;
3623         }
3624         if (tp->rx_jumbo) {
3625                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
3626                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
3627                 tp->rx_jumbo = NULL;
3628         }
3629         if (tp->rx_rcb) {
3630                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
3631                                     tp->rx_rcb, tp->rx_rcb_mapping);
3632                 tp->rx_rcb = NULL;
3633         }
3634         if (tp->tx_ring) {
3635                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
3636                         tp->tx_ring, tp->tx_desc_mapping);
3637                 tp->tx_ring = NULL;
3638         }
3639         if (tp->hw_status) {
3640                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
3641                                     tp->hw_status, tp->status_mapping);
3642                 tp->hw_status = NULL;
3643         }
3644         if (tp->hw_stats) {
3645                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
3646                                     tp->hw_stats, tp->stats_mapping);
3647                 tp->hw_stats = NULL;
3648         }
3649 }
3650
3651 /*
3652  * Must not be invoked with interrupt sources disabled and
3653  * the hardware shutdown down.  Can sleep.
3654  */
3655 static int tg3_alloc_consistent(struct tg3 *tp)
3656 {
3657         tp->rx_std_buffers = kmalloc((sizeof(struct ring_info) *
3658                                       (TG3_RX_RING_SIZE +
3659                                        TG3_RX_JUMBO_RING_SIZE)) +
3660                                      (sizeof(struct tx_ring_info) *
3661                                       TG3_TX_RING_SIZE),
3662                                      GFP_KERNEL);
3663         if (!tp->rx_std_buffers)
3664                 return -ENOMEM;
3665
3666         memset(tp->rx_std_buffers, 0,
3667                (sizeof(struct ring_info) *
3668                 (TG3_RX_RING_SIZE +
3669                  TG3_RX_JUMBO_RING_SIZE)) +
3670                (sizeof(struct tx_ring_info) *
3671                 TG3_TX_RING_SIZE));
3672
3673         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
3674         tp->tx_buffers = (struct tx_ring_info *)
3675                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
3676
3677         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
3678                                           &tp->rx_std_mapping);
3679         if (!tp->rx_std)
3680                 goto err_out;
3681
3682         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
3683                                             &tp->rx_jumbo_mapping);
3684
3685         if (!tp->rx_jumbo)
3686                 goto err_out;
3687
3688         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
3689                                           &tp->rx_rcb_mapping);
3690         if (!tp->rx_rcb)
3691                 goto err_out;
3692
3693         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
3694                                            &tp->tx_desc_mapping);
3695         if (!tp->tx_ring)
3696                 goto err_out;
3697
3698         tp->hw_status = pci_alloc_consistent(tp->pdev,
3699                                              TG3_HW_STATUS_SIZE,
3700                                              &tp->status_mapping);
3701         if (!tp->hw_status)
3702                 goto err_out;
3703
3704         tp->hw_stats = pci_alloc_consistent(tp->pdev,
3705                                             sizeof(struct tg3_hw_stats),
3706                                             &tp->stats_mapping);
3707         if (!tp->hw_stats)
3708                 goto err_out;
3709
3710         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
3711         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
3712
3713         return 0;
3714
3715 err_out:
3716         tg3_free_consistent(tp);
3717         return -ENOMEM;
3718 }
3719
3720 #define MAX_WAIT_CNT 1000
3721
3722 /* To stop a block, clear the enable bit and poll till it
3723  * clears.  tp->lock is held.
3724  */
3725 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
3726 {
3727         unsigned int i;
3728         u32 val;
3729
3730         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
3731                 switch (ofs) {
3732                 case RCVLSC_MODE:
3733                 case DMAC_MODE:
3734                 case MBFREE_MODE:
3735                 case BUFMGR_MODE:
3736                 case MEMARB_MODE:
3737                         /* We can't enable/disable these bits of the
3738                          * 5705/5750, just say success.
3739                          */
3740                         return 0;
3741
3742                 default:
3743                         break;
3744                 };
3745         }
3746
3747         val = tr32(ofs);
3748         val &= ~enable_bit;
3749         tw32_f(ofs, val);
3750
3751         for (i = 0; i < MAX_WAIT_CNT; i++) {
3752                 udelay(100);
3753                 val = tr32(ofs);
3754                 if ((val & enable_bit) == 0)
3755                         break;
3756         }
3757
3758         if (i == MAX_WAIT_CNT && !silent) {
3759                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
3760                        "ofs=%lx enable_bit=%x\n",
3761                        ofs, enable_bit);
3762                 return -ENODEV;
3763         }
3764
3765         return 0;
3766 }
3767
3768 /* tp->lock is held. */
3769 static int tg3_abort_hw(struct tg3 *tp, int silent)
3770 {
3771         int i, err;
3772
3773         tg3_disable_ints(tp);
3774
3775         tp->rx_mode &= ~RX_MODE_ENABLE;
3776         tw32_f(MAC_RX_MODE, tp->rx_mode);
3777         udelay(10);
3778
3779         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
3780         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
3781         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
3782         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
3783         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
3784         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
3785
3786         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
3787         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
3788         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
3789         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
3790         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
3791         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
3792         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
3793
3794         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
3795         tw32_f(MAC_MODE, tp->mac_mode);
3796         udelay(40);
3797
3798         tp->tx_mode &= ~TX_MODE_ENABLE;
3799         tw32_f(MAC_TX_MODE, tp->tx_mode);
3800
3801         for (i = 0; i < MAX_WAIT_CNT; i++) {
3802                 udelay(100);
3803                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
3804                         break;
3805         }
3806         if (i >= MAX_WAIT_CNT) {
3807                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
3808                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
3809                        tp->dev->name, tr32(MAC_TX_MODE));
3810                 err |= -ENODEV;
3811         }
3812
3813         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
3814         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
3815         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
3816
3817         tw32(FTQ_RESET, 0xffffffff);
3818         tw32(FTQ_RESET, 0x00000000);
3819
3820         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
3821         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
3822
3823         if (tp->hw_status)
3824                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
3825         if (tp->hw_stats)
3826                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
3827
3828         return err;
3829 }
3830
3831 /* tp->lock is held. */
3832 static int tg3_nvram_lock(struct tg3 *tp)
3833 {
3834         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
3835                 int i;
3836
3837                 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3838                 for (i = 0; i < 8000; i++) {
3839                         if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3840                                 break;
3841                         udelay(20);
3842                 }
3843                 if (i == 8000)
3844                         return -ENODEV;
3845         }
3846         return 0;
3847 }
3848
3849 /* tp->lock is held. */
3850 static void tg3_nvram_unlock(struct tg3 *tp)
3851 {
3852         if (tp->tg3_flags & TG3_FLAG_NVRAM)
3853                 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3854 }
3855
3856 /* tp->lock is held. */
3857 static void tg3_enable_nvram_access(struct tg3 *tp)
3858 {
3859         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
3860             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
3861                 u32 nvaccess = tr32(NVRAM_ACCESS);
3862
3863                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3864         }
3865 }
3866
3867 /* tp->lock is held. */
3868 static void tg3_disable_nvram_access(struct tg3 *tp)
3869 {
3870         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
3871             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
3872                 u32 nvaccess = tr32(NVRAM_ACCESS);
3873
3874                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3875         }
3876 }
3877
3878 /* tp->lock is held. */
3879 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
3880 {
3881         if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
3882                 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
3883                               NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
3884
3885         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
3886                 switch (kind) {
3887                 case RESET_KIND_INIT:
3888                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3889                                       DRV_STATE_START);
3890                         break;
3891
3892                 case RESET_KIND_SHUTDOWN:
3893                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3894                                       DRV_STATE_UNLOAD);
3895                         break;
3896
3897                 case RESET_KIND_SUSPEND:
3898                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3899                                       DRV_STATE_SUSPEND);
3900                         break;
3901
3902                 default:
3903                         break;
3904                 };
3905         }
3906 }
3907
3908 /* tp->lock is held. */
3909 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
3910 {
3911         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
3912                 switch (kind) {
3913                 case RESET_KIND_INIT:
3914                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3915                                       DRV_STATE_START_DONE);
3916                         break;
3917
3918                 case RESET_KIND_SHUTDOWN:
3919                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3920                                       DRV_STATE_UNLOAD_DONE);
3921                         break;
3922
3923                 default:
3924                         break;
3925                 };
3926         }
3927 }
3928
3929 /* tp->lock is held. */
3930 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
3931 {
3932         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
3933                 switch (kind) {
3934                 case RESET_KIND_INIT:
3935                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3936                                       DRV_STATE_START);
3937                         break;
3938
3939                 case RESET_KIND_SHUTDOWN:
3940                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3941                                       DRV_STATE_UNLOAD);
3942                         break;
3943
3944                 case RESET_KIND_SUSPEND:
3945                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3946                                       DRV_STATE_SUSPEND);
3947                         break;
3948
3949                 default:
3950                         break;
3951                 };
3952         }
3953 }
3954
3955 static void tg3_stop_fw(struct tg3 *);
3956
3957 /* tp->lock is held. */
3958 static int tg3_chip_reset(struct tg3 *tp)
3959 {
3960         u32 val;
3961         u32 flags_save;
3962         int i;
3963
3964         if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
3965                 tg3_nvram_lock(tp);
3966
3967         /*
3968          * We must avoid the readl() that normally takes place.
3969          * It locks machines, causes machine checks, and other
3970          * fun things.  So, temporarily disable the 5701
3971          * hardware workaround, while we do the reset.
3972          */
3973         flags_save = tp->tg3_flags;
3974         tp->tg3_flags &= ~TG3_FLAG_5701_REG_WRITE_BUG;
3975
3976         /* do the reset */
3977         val = GRC_MISC_CFG_CORECLK_RESET;
3978
3979         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
3980                 if (tr32(0x7e2c) == 0x60) {
3981                         tw32(0x7e2c, 0x20);
3982                 }
3983                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
3984                         tw32(GRC_MISC_CFG, (1 << 29));
3985                         val |= (1 << 29);
3986                 }
3987         }
3988
3989         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
3990                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
3991         tw32(GRC_MISC_CFG, val);
3992
3993         /* restore 5701 hardware bug workaround flag */
3994         tp->tg3_flags = flags_save;
3995
3996         /* Unfortunately, we have to delay before the PCI read back.
3997          * Some 575X chips even will not respond to a PCI cfg access
3998          * when the reset command is given to the chip.
3999          *
4000          * How do these hardware designers expect things to work
4001          * properly if the PCI write is posted for a long period
4002          * of time?  It is always necessary to have some method by
4003          * which a register read back can occur to push the write
4004          * out which does the reset.
4005          *
4006          * For most tg3 variants the trick below was working.
4007          * Ho hum...
4008          */
4009         udelay(120);
4010
4011         /* Flush PCI posted writes.  The normal MMIO registers
4012          * are inaccessible at this time so this is the only
4013          * way to make this reliably (actually, this is no longer
4014          * the case, see above).  I tried to use indirect
4015          * register read/write but this upset some 5701 variants.
4016          */
4017         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4018
4019         udelay(120);
4020
4021         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4022                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4023                         int i;
4024                         u32 cfg_val;
4025
4026                         /* Wait for link training to complete.  */
4027                         for (i = 0; i < 5000; i++)
4028                                 udelay(100);
4029
4030                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4031                         pci_write_config_dword(tp->pdev, 0xc4,
4032                                                cfg_val | (1 << 15));
4033                 }
4034                 /* Set PCIE max payload size and clear error status.  */
4035                 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4036         }
4037
4038         /* Re-enable indirect register accesses. */
4039         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4040                                tp->misc_host_ctrl);
4041
4042         /* Set MAX PCI retry to zero. */
4043         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4044         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4045             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4046                 val |= PCISTATE_RETRY_SAME_DMA;
4047         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4048
4049         pci_restore_state(tp->pdev);
4050
4051         /* Make sure PCI-X relaxed ordering bit is clear. */
4052         pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4053         val &= ~PCIX_CAPS_RELAXED_ORDERING;
4054         pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4055
4056         tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
4057
4058         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4059                 tg3_stop_fw(tp);
4060                 tw32(0x5000, 0x400);
4061         }
4062
4063         tw32(GRC_MODE, tp->grc_mode);
4064
4065         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4066                 u32 val = tr32(0xc4);
4067
4068                 tw32(0xc4, val | (1 << 15));
4069         }
4070
4071         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4072             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4073                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4074                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4075                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4076                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4077         }
4078
4079         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4080                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4081                 tw32_f(MAC_MODE, tp->mac_mode);
4082         } else
4083                 tw32_f(MAC_MODE, 0);
4084         udelay(40);
4085
4086         if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) {
4087                 /* Wait for firmware initialization to complete. */
4088                 for (i = 0; i < 100000; i++) {
4089                         tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4090                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4091                                 break;
4092                         udelay(10);
4093                 }
4094                 if (i >= 100000) {
4095                         printk(KERN_ERR PFX "tg3_reset_hw timed out for %s, "
4096                                "firmware will not restart magic=%08x\n",
4097                                tp->dev->name, val);
4098                         return -ENODEV;
4099                 }
4100         }
4101
4102         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4103             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4104                 u32 val = tr32(0x7c00);
4105
4106                 tw32(0x7c00, val | (1 << 25));
4107         }
4108
4109         /* Reprobe ASF enable state.  */
4110         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
4111         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
4112         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
4113         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
4114                 u32 nic_cfg;
4115
4116                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
4117                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
4118                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4119                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
4120                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
4121                 }
4122         }
4123
4124         return 0;
4125 }
4126
4127 /* tp->lock is held. */
4128 static void tg3_stop_fw(struct tg3 *tp)
4129 {
4130         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4131                 u32 val;
4132                 int i;
4133
4134                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4135                 val = tr32(GRC_RX_CPU_EVENT);
4136                 val |= (1 << 14);
4137                 tw32(GRC_RX_CPU_EVENT, val);
4138
4139                 /* Wait for RX cpu to ACK the event.  */
4140                 for (i = 0; i < 100; i++) {
4141                         if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
4142                                 break;
4143                         udelay(1);
4144                 }
4145         }
4146 }
4147
4148 /* tp->lock is held. */
4149 static int tg3_halt(struct tg3 *tp, int kind, int silent)
4150 {
4151         int err;
4152
4153         tg3_stop_fw(tp);
4154
4155         tg3_write_sig_pre_reset(tp, kind);
4156
4157         tg3_abort_hw(tp, silent);
4158         err = tg3_chip_reset(tp);
4159
4160         tg3_write_sig_legacy(tp, kind);
4161         tg3_write_sig_post_reset(tp, kind);
4162
4163         if (err)
4164                 return err;
4165
4166         return 0;
4167 }
4168
4169 #define TG3_FW_RELEASE_MAJOR    0x0
4170 #define TG3_FW_RELASE_MINOR     0x0
4171 #define TG3_FW_RELEASE_FIX      0x0
4172 #define TG3_FW_START_ADDR       0x08000000
4173 #define TG3_FW_TEXT_ADDR        0x08000000
4174 #define TG3_FW_TEXT_LEN         0x9c0
4175 #define TG3_FW_RODATA_ADDR      0x080009c0
4176 #define TG3_FW_RODATA_LEN       0x60
4177 #define TG3_FW_DATA_ADDR        0x08000a40
4178 #define TG3_FW_DATA_LEN         0x20
4179 #define TG3_FW_SBSS_ADDR        0x08000a60
4180 #define TG3_FW_SBSS_LEN         0xc
4181 #define TG3_FW_BSS_ADDR         0x08000a70
4182 #define TG3_FW_BSS_LEN          0x10
4183
4184 static u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
4185         0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
4186         0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
4187         0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
4188         0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
4189         0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
4190         0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
4191         0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
4192         0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
4193         0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
4194         0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
4195         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
4196         0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
4197         0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
4198         0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
4199         0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
4200         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
4201         0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
4202         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
4203         0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
4204         0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
4205         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
4206         0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
4207         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
4208         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4209         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4210         0, 0, 0, 0, 0, 0,
4211         0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
4212         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4213         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4214         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4215         0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
4216         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
4217         0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
4218         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
4219         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4220         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4221         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
4222         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4223         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4224         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4225         0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
4226         0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
4227         0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
4228         0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
4229         0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
4230         0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
4231         0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
4232         0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
4233         0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
4234         0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
4235         0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
4236         0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
4237         0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
4238         0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
4239         0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
4240         0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
4241         0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
4242         0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
4243         0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
4244         0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
4245         0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
4246         0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
4247         0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
4248         0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
4249         0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
4250         0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
4251         0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
4252         0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
4253         0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
4254         0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
4255         0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
4256         0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
4257         0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
4258         0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
4259         0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
4260         0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
4261         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
4262         0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
4263         0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
4264         0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
4265         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
4266         0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
4267         0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
4268         0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
4269         0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
4270         0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
4271         0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
4272         0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
4273         0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
4274         0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
4275         0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
4276 };
4277
4278 static u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
4279         0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
4280         0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
4281         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
4282         0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
4283         0x00000000
4284 };
4285
4286 #if 0 /* All zeros, don't eat up space with it. */
4287 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
4288         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4289         0x00000000, 0x00000000, 0x00000000, 0x00000000
4290 };
4291 #endif
4292
4293 #define RX_CPU_SCRATCH_BASE     0x30000
4294 #define RX_CPU_SCRATCH_SIZE     0x04000
4295 #define TX_CPU_SCRATCH_BASE     0x34000
4296 #define TX_CPU_SCRATCH_SIZE     0x04000
4297
4298 /* tp->lock is held. */
4299 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
4300 {
4301         int i;
4302
4303         if (offset == TX_CPU_BASE &&
4304             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
4305                 BUG();
4306
4307         if (offset == RX_CPU_BASE) {
4308                 for (i = 0; i < 10000; i++) {
4309                         tw32(offset + CPU_STATE, 0xffffffff);
4310                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
4311                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4312                                 break;
4313                 }
4314
4315                 tw32(offset + CPU_STATE, 0xffffffff);
4316                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
4317                 udelay(10);
4318         } else {
4319                 for (i = 0; i < 10000; i++) {
4320                         tw32(offset + CPU_STATE, 0xffffffff);
4321                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
4322                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4323                                 break;
4324                 }
4325         }
4326
4327         if (i >= 10000) {
4328                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
4329                        "and %s CPU\n",
4330                        tp->dev->name,
4331                        (offset == RX_CPU_BASE ? "RX" : "TX"));
4332                 return -ENODEV;
4333         }
4334         return 0;
4335 }
4336
4337 struct fw_info {
4338         unsigned int text_base;
4339         unsigned int text_len;
4340         u32 *text_data;
4341         unsigned int rodata_base;
4342         unsigned int rodata_len;
4343         u32 *rodata_data;
4344         unsigned int data_base;
4345         unsigned int data_len;
4346         u32 *data_data;
4347 };
4348
4349 /* tp->lock is held. */
4350 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
4351                                  int cpu_scratch_size, struct fw_info *info)
4352 {
4353         int err, i;
4354         u32 orig_tg3_flags = tp->tg3_flags;
4355         void (*write_op)(struct tg3 *, u32, u32);
4356
4357         if (cpu_base == TX_CPU_BASE &&
4358             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4359                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
4360                        "TX cpu firmware on %s which is 5705.\n",
4361                        tp->dev->name);
4362                 return -EINVAL;
4363         }
4364
4365         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4366                 write_op = tg3_write_mem;
4367         else
4368                 write_op = tg3_write_indirect_reg32;
4369
4370         /* Force use of PCI config space for indirect register
4371          * write calls.
4372          */
4373         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
4374
4375         /* It is possible that bootcode is still loading at this point.
4376          * Get the nvram lock first before halting the cpu.
4377          */
4378         tg3_nvram_lock(tp);
4379         err = tg3_halt_cpu(tp, cpu_base);
4380         tg3_nvram_unlock(tp);
4381         if (err)
4382                 goto out;
4383
4384         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
4385                 write_op(tp, cpu_scratch_base + i, 0);
4386         tw32(cpu_base + CPU_STATE, 0xffffffff);
4387         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
4388         for (i = 0; i < (info->text_len / sizeof(u32)); i++)
4389                 write_op(tp, (cpu_scratch_base +
4390                               (info->text_base & 0xffff) +
4391                               (i * sizeof(u32))),
4392                          (info->text_data ?
4393                           info->text_data[i] : 0));
4394         for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
4395                 write_op(tp, (cpu_scratch_base +
4396                               (info->rodata_base & 0xffff) +
4397                               (i * sizeof(u32))),
4398                          (info->rodata_data ?
4399                           info->rodata_data[i] : 0));
4400         for (i = 0; i < (info->data_len / sizeof(u32)); i++)
4401                 write_op(tp, (cpu_scratch_base +
4402                               (info->data_base & 0xffff) +
4403                               (i * sizeof(u32))),
4404                          (info->data_data ?
4405                           info->data_data[i] : 0));
4406
4407         err = 0;
4408
4409 out:
4410         tp->tg3_flags = orig_tg3_flags;
4411         return err;
4412 }
4413
4414 /* tp->lock is held. */
4415 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
4416 {
4417         struct fw_info info;
4418         int err, i;
4419
4420         info.text_base = TG3_FW_TEXT_ADDR;
4421         info.text_len = TG3_FW_TEXT_LEN;
4422         info.text_data = &tg3FwText[0];
4423         info.rodata_base = TG3_FW_RODATA_ADDR;
4424         info.rodata_len = TG3_FW_RODATA_LEN;
4425         info.rodata_data = &tg3FwRodata[0];
4426         info.data_base = TG3_FW_DATA_ADDR;
4427         info.data_len = TG3_FW_DATA_LEN;
4428         info.data_data = NULL;
4429
4430         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
4431                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
4432                                     &info);
4433         if (err)
4434                 return err;
4435
4436         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
4437                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
4438                                     &info);
4439         if (err)
4440                 return err;
4441
4442         /* Now startup only the RX cpu. */
4443         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4444         tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
4445
4446         for (i = 0; i < 5; i++) {
4447                 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
4448                         break;
4449                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4450                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
4451                 tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
4452                 udelay(1000);
4453         }
4454         if (i >= 5) {
4455                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
4456                        "to set RX CPU PC, is %08x should be %08x\n",
4457                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
4458                        TG3_FW_TEXT_ADDR);
4459                 return -ENODEV;
4460         }
4461         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4462         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
4463
4464         return 0;
4465 }
4466
4467 #if TG3_TSO_SUPPORT != 0
4468
4469 #define TG3_TSO_FW_RELEASE_MAJOR        0x1
4470 #define TG3_TSO_FW_RELASE_MINOR         0x6
4471 #define TG3_TSO_FW_RELEASE_FIX          0x0
4472 #define TG3_TSO_FW_START_ADDR           0x08000000
4473 #define TG3_TSO_FW_TEXT_ADDR            0x08000000
4474 #define TG3_TSO_FW_TEXT_LEN             0x1aa0
4475 #define TG3_TSO_FW_RODATA_ADDR          0x08001aa0
4476 #define TG3_TSO_FW_RODATA_LEN           0x60
4477 #define TG3_TSO_FW_DATA_ADDR            0x08001b20
4478 #define TG3_TSO_FW_DATA_LEN             0x30
4479 #define TG3_TSO_FW_SBSS_ADDR            0x08001b50
4480 #define TG3_TSO_FW_SBSS_LEN             0x2c
4481 #define TG3_TSO_FW_BSS_ADDR             0x08001b80
4482 #define TG3_TSO_FW_BSS_LEN              0x894
4483
4484 static u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
4485         0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
4486         0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
4487         0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
4488         0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
4489         0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
4490         0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
4491         0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
4492         0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
4493         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
4494         0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
4495         0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
4496         0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
4497         0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
4498         0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
4499         0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
4500         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
4501         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
4502         0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
4503         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4504         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
4505         0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
4506         0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
4507         0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
4508         0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
4509         0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
4510         0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
4511         0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
4512         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
4513         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
4514         0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4515         0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
4516         0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
4517         0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
4518         0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
4519         0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
4520         0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
4521         0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
4522         0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
4523         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4524         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
4525         0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
4526         0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
4527         0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
4528         0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
4529         0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
4530         0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
4531         0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
4532         0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4533         0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
4534         0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4535         0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
4536         0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
4537         0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
4538         0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
4539         0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
4540         0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
4541         0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
4542         0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
4543         0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
4544         0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
4545         0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
4546         0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
4547         0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
4548         0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
4549         0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
4550         0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
4551         0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
4552         0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
4553         0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
4554         0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
4555         0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
4556         0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
4557         0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
4558         0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
4559         0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
4560         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
4561         0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
4562         0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
4563         0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
4564         0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
4565         0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
4566         0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
4567         0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
4568         0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
4569         0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
4570         0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
4571         0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
4572         0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
4573         0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
4574         0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
4575         0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
4576         0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
4577         0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
4578         0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
4579         0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
4580         0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
4581         0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
4582         0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
4583         0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
4584         0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
4585         0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
4586         0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
4587         0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
4588         0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
4589         0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
4590         0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
4591         0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
4592         0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
4593         0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
4594         0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
4595         0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
4596         0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
4597         0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
4598         0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
4599         0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
4600         0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
4601         0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
4602         0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
4603         0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
4604         0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
4605         0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
4606         0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
4607         0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
4608         0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
4609         0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
4610         0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
4611         0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
4612         0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
4613         0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
4614         0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
4615         0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
4616         0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
4617         0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
4618         0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
4619         0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
4620         0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
4621         0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
4622         0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
4623         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
4624         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
4625         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
4626         0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
4627         0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
4628         0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
4629         0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
4630         0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
4631         0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
4632         0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
4633         0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
4634         0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
4635         0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
4636         0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
4637         0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
4638         0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
4639         0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
4640         0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
4641         0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
4642         0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
4643         0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
4644         0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
4645         0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
4646         0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
4647         0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
4648         0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
4649         0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
4650         0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
4651         0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
4652         0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
4653         0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
4654         0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
4655         0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
4656         0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
4657         0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
4658         0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
4659         0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
4660         0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
4661         0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
4662         0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
4663         0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
4664         0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
4665         0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
4666         0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
4667         0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
4668         0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
4669         0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
4670         0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
4671         0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
4672         0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
4673         0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
4674         0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
4675         0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
4676         0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
4677         0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
4678         0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
4679         0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
4680         0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
4681         0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
4682         0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
4683         0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
4684         0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
4685         0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
4686         0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
4687         0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
4688         0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
4689         0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
4690         0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
4691         0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
4692         0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
4693         0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
4694         0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
4695         0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
4696         0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
4697         0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
4698         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
4699         0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
4700         0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
4701         0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
4702         0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
4703         0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
4704         0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
4705         0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
4706         0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
4707         0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
4708         0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
4709         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
4710         0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
4711         0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
4712         0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
4713         0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
4714         0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
4715         0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
4716         0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
4717         0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
4718         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
4719         0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
4720         0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
4721         0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
4722         0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
4723         0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
4724         0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
4725         0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
4726         0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
4727         0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
4728         0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
4729         0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
4730         0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
4731         0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
4732         0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
4733         0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
4734         0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
4735         0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
4736         0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
4737         0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
4738         0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
4739         0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
4740         0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
4741         0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
4742         0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
4743         0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
4744         0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
4745         0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
4746         0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
4747         0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
4748         0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
4749         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
4750         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
4751         0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
4752         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
4753         0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
4754         0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
4755         0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
4756         0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
4757         0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
4758         0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
4759         0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
4760         0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
4761         0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
4762         0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
4763         0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
4764         0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
4765         0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
4766         0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
4767         0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
4768         0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
4769 };
4770
4771 static u32 tg3TsoFwRodata[] = {
4772         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
4773         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
4774         0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
4775         0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
4776         0x00000000,
4777 };
4778
4779 static u32 tg3TsoFwData[] = {
4780         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
4781         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4782         0x00000000,
4783 };
4784
4785 /* 5705 needs a special version of the TSO firmware.  */
4786 #define TG3_TSO5_FW_RELEASE_MAJOR       0x1
4787 #define TG3_TSO5_FW_RELASE_MINOR        0x2
4788 #define TG3_TSO5_FW_RELEASE_FIX         0x0
4789 #define TG3_TSO5_FW_START_ADDR          0x00010000
4790 #define TG3_TSO5_FW_TEXT_ADDR           0x00010000
4791 #define TG3_TSO5_FW_TEXT_LEN            0xe90
4792 #define TG3_TSO5_FW_RODATA_ADDR         0x00010e90
4793 #define TG3_TSO5_FW_RODATA_LEN          0x50
4794 #define TG3_TSO5_FW_DATA_ADDR           0x00010f00
4795 #define TG3_TSO5_FW_DATA_LEN            0x20
4796 #define TG3_TSO5_FW_SBSS_ADDR           0x00010f20
4797 #define TG3_TSO5_FW_SBSS_LEN            0x28
4798 #define TG3_TSO5_FW_BSS_ADDR            0x00010f50
4799 #define TG3_TSO5_FW_BSS_LEN             0x88
4800
4801 static u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
4802         0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
4803         0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
4804         0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
4805         0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
4806         0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
4807         0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
4808         0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4809         0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
4810         0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
4811         0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
4812         0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
4813         0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
4814         0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
4815         0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
4816         0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
4817         0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
4818         0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
4819         0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
4820         0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
4821         0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
4822         0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
4823         0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
4824         0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
4825         0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
4826         0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
4827         0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
4828         0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
4829         0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
4830         0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
4831         0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
4832         0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
4833         0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
4834         0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
4835         0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
4836         0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
4837         0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
4838         0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
4839         0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
4840         0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
4841         0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
4842         0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
4843         0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
4844         0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
4845         0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
4846         0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
4847         0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
4848         0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
4849         0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
4850         0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
4851         0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
4852         0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
4853         0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
4854         0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
4855         0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
4856         0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
4857         0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
4858         0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
4859         0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
4860         0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
4861         0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
4862         0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
4863         0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
4864         0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
4865         0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
4866         0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
4867         0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
4868         0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
4869         0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
4870         0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
4871         0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
4872         0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
4873         0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
4874         0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
4875         0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
4876         0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
4877         0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
4878         0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
4879         0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
4880         0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
4881         0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
4882         0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
4883         0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
4884         0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
4885         0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
4886         0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
4887         0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
4888         0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
4889         0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
4890         0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
4891         0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
4892         0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
4893         0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
4894         0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
4895         0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
4896         0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
4897         0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
4898         0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
4899         0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
4900         0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
4901         0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
4902         0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
4903         0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
4904         0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
4905         0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
4906         0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
4907         0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
4908         0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
4909         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
4910         0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
4911         0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
4912         0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
4913         0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
4914         0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
4915         0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
4916         0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
4917         0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
4918         0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
4919         0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
4920         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
4921         0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
4922         0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
4923         0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
4924         0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
4925         0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4926         0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
4927         0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
4928         0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
4929         0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
4930         0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
4931         0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
4932         0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
4933         0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
4934         0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
4935         0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
4936         0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
4937         0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
4938         0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
4939         0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
4940         0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
4941         0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
4942         0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
4943         0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
4944         0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
4945         0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
4946         0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
4947         0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
4948         0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
4949         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
4950         0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
4951         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
4952         0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
4953         0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
4954         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
4955         0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
4956         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
4957         0x00000000, 0x00000000, 0x00000000,
4958 };
4959
4960 static u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
4961         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
4962         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
4963         0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
4964         0x00000000, 0x00000000, 0x00000000,
4965 };
4966
4967 static u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
4968         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
4969         0x00000000, 0x00000000, 0x00000000,
4970 };
4971
4972 /* tp->lock is held. */
4973 static int tg3_load_tso_firmware(struct tg3 *tp)
4974 {
4975         struct fw_info info;
4976         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
4977         int err, i;
4978
4979         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4980                 return 0;
4981
4982         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4983                 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
4984                 info.text_len = TG3_TSO5_FW_TEXT_LEN;
4985                 info.text_data = &tg3Tso5FwText[0];
4986                 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
4987                 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
4988                 info.rodata_data = &tg3Tso5FwRodata[0];
4989                 info.data_base = TG3_TSO5_FW_DATA_ADDR;
4990                 info.data_len = TG3_TSO5_FW_DATA_LEN;
4991                 info.data_data = &tg3Tso5FwData[0];
4992                 cpu_base = RX_CPU_BASE;
4993                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
4994                 cpu_scratch_size = (info.text_len +
4995                                     info.rodata_len +
4996                                     info.data_len +
4997                                     TG3_TSO5_FW_SBSS_LEN +
4998                                     TG3_TSO5_FW_BSS_LEN);
4999         } else {
5000                 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5001                 info.text_len = TG3_TSO_FW_TEXT_LEN;
5002                 info.text_data = &tg3TsoFwText[0];
5003                 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5004                 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5005                 info.rodata_data = &tg3TsoFwRodata[0];
5006                 info.data_base = TG3_TSO_FW_DATA_ADDR;
5007                 info.data_len = TG3_TSO_FW_DATA_LEN;
5008                 info.data_data = &tg3TsoFwData[0];
5009                 cpu_base = TX_CPU_BASE;
5010                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5011                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5012         }
5013
5014         err = tg3_load_firmware_cpu(tp, cpu_base,
5015                                     cpu_scratch_base, cpu_scratch_size,
5016                                     &info);
5017         if (err)
5018                 return err;
5019
5020         /* Now startup the cpu. */
5021         tw32(cpu_base + CPU_STATE, 0xffffffff);
5022         tw32_f(cpu_base + CPU_PC,    info.text_base);
5023
5024         for (i = 0; i < 5; i++) {
5025                 if (tr32(cpu_base + CPU_PC) == info.text_base)
5026                         break;
5027                 tw32(cpu_base + CPU_STATE, 0xffffffff);
5028                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
5029                 tw32_f(cpu_base + CPU_PC,    info.text_base);
5030                 udelay(1000);
5031         }
5032         if (i >= 5) {
5033                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5034                        "to set CPU PC, is %08x should be %08x\n",
5035                        tp->dev->name, tr32(cpu_base + CPU_PC),
5036                        info.text_base);
5037                 return -ENODEV;
5038         }
5039         tw32(cpu_base + CPU_STATE, 0xffffffff);
5040         tw32_f(cpu_base + CPU_MODE,  0x00000000);
5041         return 0;
5042 }
5043
5044 #endif /* TG3_TSO_SUPPORT != 0 */
5045
5046 /* tp->lock is held. */
5047 static void __tg3_set_mac_addr(struct tg3 *tp)
5048 {
5049         u32 addr_high, addr_low;
5050         int i;
5051
5052         addr_high = ((tp->dev->dev_addr[0] << 8) |
5053                      tp->dev->dev_addr[1]);
5054         addr_low = ((tp->dev->dev_addr[2] << 24) |
5055                     (tp->dev->dev_addr[3] << 16) |
5056                     (tp->dev->dev_addr[4] <<  8) |
5057                     (tp->dev->dev_addr[5] <<  0));
5058         for (i = 0; i < 4; i++) {
5059                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
5060                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
5061         }
5062
5063         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
5064             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5065                 for (i = 0; i < 12; i++) {
5066                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
5067                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
5068                 }
5069         }
5070
5071         addr_high = (tp->dev->dev_addr[0] +
5072                      tp->dev->dev_addr[1] +
5073                      tp->dev->dev_addr[2] +
5074                      tp->dev->dev_addr[3] +
5075                      tp->dev->dev_addr[4] +
5076                      tp->dev->dev_addr[5]) &
5077                 TX_BACKOFF_SEED_MASK;
5078         tw32(MAC_TX_BACKOFF_SEED, addr_high);
5079 }
5080
5081 static int tg3_set_mac_addr(struct net_device *dev, void *p)
5082 {
5083         struct tg3 *tp = netdev_priv(dev);
5084         struct sockaddr *addr = p;
5085
5086         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5087
5088         spin_lock_bh(&tp->lock);
5089         __tg3_set_mac_addr(tp);
5090         spin_unlock_bh(&tp->lock);
5091
5092         return 0;
5093 }
5094
5095 /* tp->lock is held. */
5096 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
5097                            dma_addr_t mapping, u32 maxlen_flags,
5098                            u32 nic_addr)
5099 {
5100         tg3_write_mem(tp,
5101                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
5102                       ((u64) mapping >> 32));
5103         tg3_write_mem(tp,
5104                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
5105                       ((u64) mapping & 0xffffffff));
5106         tg3_write_mem(tp,
5107                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
5108                        maxlen_flags);
5109
5110         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5111                 tg3_write_mem(tp,
5112                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
5113                               nic_addr);
5114 }
5115
5116 static void __tg3_set_rx_mode(struct net_device *);
5117 static void tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
5118 {
5119         tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
5120         tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
5121         tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
5122         tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
5123         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5124                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
5125                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
5126         }
5127         tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
5128         tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
5129         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5130                 u32 val = ec->stats_block_coalesce_usecs;
5131
5132                 if (!netif_carrier_ok(tp->dev))
5133                         val = 0;
5134
5135                 tw32(HOSTCC_STAT_COAL_TICKS, val);
5136         }
5137 }
5138
5139 /* tp->lock is held. */
5140 static int tg3_reset_hw(struct tg3 *tp)
5141 {
5142         u32 val, rdmac_mode;
5143         int i, err, limit;
5144
5145         tg3_disable_ints(tp);
5146
5147         tg3_stop_fw(tp);
5148
5149         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
5150
5151         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
5152                 tg3_abort_hw(tp, 1);
5153         }
5154
5155         err = tg3_chip_reset(tp);
5156         if (err)
5157                 return err;
5158
5159         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
5160
5161         /* This works around an issue with Athlon chipsets on
5162          * B3 tigon3 silicon.  This bit has no effect on any
5163          * other revision.  But do not set this on PCI Express
5164          * chips.
5165          */
5166         if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
5167                 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
5168         tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5169
5170         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5171             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
5172                 val = tr32(TG3PCI_PCISTATE);
5173                 val |= PCISTATE_RETRY_SAME_DMA;
5174                 tw32(TG3PCI_PCISTATE, val);
5175         }
5176
5177         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
5178                 /* Enable some hw fixes.  */
5179                 val = tr32(TG3PCI_MSI_DATA);
5180                 val |= (1 << 26) | (1 << 28) | (1 << 29);
5181                 tw32(TG3PCI_MSI_DATA, val);
5182         }
5183
5184         /* Descriptor ring init may make accesses to the
5185          * NIC SRAM area to setup the TX descriptors, so we
5186          * can only do this after the hardware has been
5187          * successfully reset.
5188          */
5189         tg3_init_rings(tp);
5190
5191         /* This value is determined during the probe time DMA
5192          * engine test, tg3_test_dma.
5193          */
5194         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
5195
5196         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
5197                           GRC_MODE_4X_NIC_SEND_RINGS |
5198                           GRC_MODE_NO_TX_PHDR_CSUM |
5199                           GRC_MODE_NO_RX_PHDR_CSUM);
5200         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
5201         if (tp->tg3_flags & TG3_FLAG_NO_TX_PSEUDO_CSUM)
5202                 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
5203         if (tp->tg3_flags & TG3_FLAG_NO_RX_PSEUDO_CSUM)
5204                 tp->grc_mode |= GRC_MODE_NO_RX_PHDR_CSUM;
5205
5206         tw32(GRC_MODE,
5207              tp->grc_mode |
5208              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
5209
5210         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
5211         val = tr32(GRC_MISC_CFG);
5212         val &= ~0xff;
5213         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
5214         tw32(GRC_MISC_CFG, val);
5215
5216         /* Initialize MBUF/DESC pool. */
5217         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
5218                 /* Do nothing.  */
5219         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
5220                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
5221                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
5222                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
5223                 else
5224                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
5225                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
5226                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
5227         }
5228 #if TG3_TSO_SUPPORT != 0
5229         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5230                 int fw_len;
5231
5232                 fw_len = (TG3_TSO5_FW_TEXT_LEN +
5233                           TG3_TSO5_FW_RODATA_LEN +
5234                           TG3_TSO5_FW_DATA_LEN +
5235                           TG3_TSO5_FW_SBSS_LEN +
5236                           TG3_TSO5_FW_BSS_LEN);
5237                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
5238                 tw32(BUFMGR_MB_POOL_ADDR,
5239                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
5240                 tw32(BUFMGR_MB_POOL_SIZE,
5241                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
5242         }
5243 #endif
5244
5245         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE)) {
5246                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5247                      tp->bufmgr_config.mbuf_read_dma_low_water);
5248                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5249                      tp->bufmgr_config.mbuf_mac_rx_low_water);
5250                 tw32(BUFMGR_MB_HIGH_WATER,
5251                      tp->bufmgr_config.mbuf_high_water);
5252         } else {
5253                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5254                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
5255                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5256                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
5257                 tw32(BUFMGR_MB_HIGH_WATER,
5258                      tp->bufmgr_config.mbuf_high_water_jumbo);
5259         }
5260         tw32(BUFMGR_DMA_LOW_WATER,
5261              tp->bufmgr_config.dma_low_water);
5262         tw32(BUFMGR_DMA_HIGH_WATER,
5263              tp->bufmgr_config.dma_high_water);
5264
5265         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
5266         for (i = 0; i < 2000; i++) {
5267                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
5268                         break;
5269                 udelay(10);
5270         }
5271         if (i >= 2000) {
5272                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
5273                        tp->dev->name);
5274                 return -ENODEV;
5275         }
5276
5277         /* Setup replenish threshold. */
5278         tw32(RCVBDI_STD_THRESH, tp->rx_pending / 8);
5279
5280         /* Initialize TG3_BDINFO's at:
5281          *  RCVDBDI_STD_BD:     standard eth size rx ring
5282          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
5283          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
5284          *
5285          * like so:
5286          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
5287          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
5288          *                              ring attribute flags
5289          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
5290          *
5291          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
5292          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
5293          *
5294          * The size of each ring is fixed in the firmware, but the location is
5295          * configurable.
5296          */
5297         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5298              ((u64) tp->rx_std_mapping >> 32));
5299         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5300              ((u64) tp->rx_std_mapping & 0xffffffff));
5301         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
5302              NIC_SRAM_RX_BUFFER_DESC);
5303
5304         /* Don't even try to program the JUMBO/MINI buffer descriptor
5305          * configs on 5705.
5306          */
5307         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5308                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5309                      RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
5310         } else {
5311                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5312                      RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5313
5314                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
5315                      BDINFO_FLAGS_DISABLED);
5316
5317                 /* Setup replenish threshold. */
5318                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
5319
5320                 if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) {
5321                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5322                              ((u64) tp->rx_jumbo_mapping >> 32));
5323                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5324                              ((u64) tp->rx_jumbo_mapping & 0xffffffff));
5325                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5326                              RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5327                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
5328                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
5329                 } else {
5330                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5331                              BDINFO_FLAGS_DISABLED);
5332                 }
5333
5334         }
5335
5336         /* There is only one send ring on 5705/5750, no need to explicitly
5337          * disable the others.
5338          */
5339         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5340                 /* Clear out send RCB ring in SRAM. */
5341                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
5342                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
5343                                       BDINFO_FLAGS_DISABLED);
5344         }
5345
5346         tp->tx_prod = 0;
5347         tp->tx_cons = 0;
5348         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
5349         tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
5350
5351         tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
5352                        tp->tx_desc_mapping,
5353                        (TG3_TX_RING_SIZE <<
5354                         BDINFO_FLAGS_MAXLEN_SHIFT),
5355                        NIC_SRAM_TX_BUFFER_DESC);
5356
5357         /* There is only one receive return ring on 5705/5750, no need
5358          * to explicitly disable the others.
5359          */
5360         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5361                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
5362                      i += TG3_BDINFO_SIZE) {
5363                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
5364                                       BDINFO_FLAGS_DISABLED);
5365                 }
5366         }
5367
5368         tp->rx_rcb_ptr = 0;
5369         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
5370
5371         tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
5372                        tp->rx_rcb_mapping,
5373                        (TG3_RX_RCB_RING_SIZE(tp) <<
5374                         BDINFO_FLAGS_MAXLEN_SHIFT),
5375                        0);
5376
5377         tp->rx_std_ptr = tp->rx_pending;
5378         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
5379                      tp->rx_std_ptr);
5380
5381         tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) ?
5382                                                 tp->rx_jumbo_pending : 0;
5383         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
5384                      tp->rx_jumbo_ptr);
5385
5386         /* Initialize MAC address and backoff seed. */
5387         __tg3_set_mac_addr(tp);
5388
5389         /* MTU + ethernet header + FCS + optional VLAN tag */
5390         tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
5391
5392         /* The slot time is changed by tg3_setup_phy if we
5393          * run at gigabit with half duplex.
5394          */
5395         tw32(MAC_TX_LENGTHS,
5396              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
5397              (6 << TX_LENGTHS_IPG_SHIFT) |
5398              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
5399
5400         /* Receive rules. */
5401         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
5402         tw32(RCVLPC_CONFIG, 0x0181);
5403
5404         /* Calculate RDMAC_MODE setting early, we need it to determine
5405          * the RCVLPC_STATE_ENABLE mask.
5406          */
5407         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
5408                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
5409                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
5410                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
5411                       RDMAC_MODE_LNGREAD_ENAB);
5412         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
5413                 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
5414
5415         /* If statement applies to 5705 and 5750 PCI devices only */
5416         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
5417              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
5418             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
5419                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
5420                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
5421                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
5422                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
5423                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
5424                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
5425                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
5426                 }
5427         }
5428
5429         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
5430                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
5431
5432 #if TG3_TSO_SUPPORT != 0
5433         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5434                 rdmac_mode |= (1 << 27);
5435 #endif
5436
5437         /* Receive/send statistics. */
5438         if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
5439             (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
5440                 val = tr32(RCVLPC_STATS_ENABLE);
5441                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
5442                 tw32(RCVLPC_STATS_ENABLE, val);
5443         } else {
5444                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
5445         }
5446         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
5447         tw32(SNDDATAI_STATSENAB, 0xffffff);
5448         tw32(SNDDATAI_STATSCTRL,
5449              (SNDDATAI_SCTRL_ENABLE |
5450               SNDDATAI_SCTRL_FASTUPD));
5451
5452         /* Setup host coalescing engine. */
5453         tw32(HOSTCC_MODE, 0);
5454         for (i = 0; i < 2000; i++) {
5455                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
5456                         break;
5457                 udelay(10);
5458         }
5459
5460         tg3_set_coalesce(tp, &tp->coal);
5461
5462         /* set status block DMA address */
5463         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
5464              ((u64) tp->status_mapping >> 32));
5465         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
5466              ((u64) tp->status_mapping & 0xffffffff));
5467
5468         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5469                 /* Status/statistics block address.  See tg3_timer,
5470                  * the tg3_periodic_fetch_stats call there, and
5471                  * tg3_get_stats to see how this works for 5705/5750 chips.
5472                  */
5473                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
5474                      ((u64) tp->stats_mapping >> 32));
5475                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
5476                      ((u64) tp->stats_mapping & 0xffffffff));
5477                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
5478                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
5479         }
5480
5481         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
5482
5483         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
5484         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
5485         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5486                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
5487
5488         /* Clear statistics/status block in chip, and status block in ram. */
5489         for (i = NIC_SRAM_STATS_BLK;
5490              i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
5491              i += sizeof(u32)) {
5492                 tg3_write_mem(tp, i, 0);
5493                 udelay(40);
5494         }
5495         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5496
5497         tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
5498                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
5499         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
5500         udelay(40);
5501
5502         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
5503          * If TG3_FLAG_EEPROM_WRITE_PROT is set, we should read the
5504          * register to preserve the GPIO settings for LOMs. The GPIOs,
5505          * whether used as inputs or outputs, are set by boot code after
5506          * reset.
5507          */
5508         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
5509                 u32 gpio_mask;
5510
5511                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE2 |
5512                             GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT2;
5513
5514                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
5515                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
5516                                      GRC_LCLCTRL_GPIO_OUTPUT3;
5517
5518                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
5519
5520                 /* GPIO1 must be driven high for eeprom write protect */
5521                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
5522                                        GRC_LCLCTRL_GPIO_OUTPUT1);
5523         }
5524         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
5525         udelay(100);
5526
5527         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
5528         tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
5529         tp->last_tag = 0;
5530
5531         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5532                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
5533                 udelay(40);
5534         }
5535
5536         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
5537                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
5538                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
5539                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
5540                WDMAC_MODE_LNGREAD_ENAB);
5541
5542         /* If statement applies to 5705 and 5750 PCI devices only */
5543         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
5544              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
5545             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
5546                 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
5547                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
5548                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
5549                         /* nothing */
5550                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
5551                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
5552                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
5553                         val |= WDMAC_MODE_RX_ACCEL;
5554                 }
5555         }
5556
5557         tw32_f(WDMAC_MODE, val);
5558         udelay(40);
5559
5560         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
5561                 val = tr32(TG3PCI_X_CAPS);
5562                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
5563                         val &= ~PCIX_CAPS_BURST_MASK;
5564                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
5565                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5566                         val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
5567                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
5568                         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
5569                                 val |= (tp->split_mode_max_reqs <<
5570                                         PCIX_CAPS_SPLIT_SHIFT);
5571                 }
5572                 tw32(TG3PCI_X_CAPS, val);
5573         }
5574
5575         tw32_f(RDMAC_MODE, rdmac_mode);
5576         udelay(40);
5577
5578         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
5579         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5580                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
5581         tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
5582         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
5583         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
5584         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
5585         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
5586 #if TG3_TSO_SUPPORT != 0
5587         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5588                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
5589 #endif
5590         tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
5591         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
5592
5593         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
5594                 err = tg3_load_5701_a0_firmware_fix(tp);
5595                 if (err)
5596                         return err;
5597         }
5598
5599 #if TG3_TSO_SUPPORT != 0
5600         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5601                 err = tg3_load_tso_firmware(tp);
5602                 if (err)
5603                         return err;
5604         }
5605 #endif
5606
5607         tp->tx_mode = TX_MODE_ENABLE;
5608         tw32_f(MAC_TX_MODE, tp->tx_mode);
5609         udelay(100);
5610
5611         tp->rx_mode = RX_MODE_ENABLE;
5612         tw32_f(MAC_RX_MODE, tp->rx_mode);
5613         udelay(10);
5614
5615         if (tp->link_config.phy_is_low_power) {
5616                 tp->link_config.phy_is_low_power = 0;
5617                 tp->link_config.speed = tp->link_config.orig_speed;
5618                 tp->link_config.duplex = tp->link_config.orig_duplex;
5619                 tp->link_config.autoneg = tp->link_config.orig_autoneg;
5620         }
5621
5622         tp->mi_mode = MAC_MI_MODE_BASE;
5623         tw32_f(MAC_MI_MODE, tp->mi_mode);
5624         udelay(80);
5625
5626         tw32(MAC_LED_CTRL, tp->led_ctrl);
5627
5628         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
5629         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5630                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
5631                 udelay(10);
5632         }
5633         tw32_f(MAC_RX_MODE, tp->rx_mode);
5634         udelay(10);
5635
5636         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5637                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
5638                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
5639                         /* Set drive transmission level to 1.2V  */
5640                         /* only if the signal pre-emphasis bit is not set  */
5641                         val = tr32(MAC_SERDES_CFG);
5642                         val &= 0xfffff000;
5643                         val |= 0x880;
5644                         tw32(MAC_SERDES_CFG, val);
5645                 }
5646                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
5647                         tw32(MAC_SERDES_CFG, 0x616000);
5648         }
5649
5650         /* Prevent chip from dropping frames when flow control
5651          * is enabled.
5652          */
5653         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
5654
5655         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
5656             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
5657                 /* Use hardware link auto-negotiation */
5658                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
5659         }
5660
5661         err = tg3_setup_phy(tp, 1);
5662         if (err)
5663                 return err;
5664
5665         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
5666                 u32 tmp;
5667
5668                 /* Clear CRC stats. */
5669                 if (!tg3_readphy(tp, 0x1e, &tmp)) {
5670                         tg3_writephy(tp, 0x1e, tmp | 0x8000);
5671                         tg3_readphy(tp, 0x14, &tmp);
5672                 }
5673         }
5674
5675         __tg3_set_rx_mode(tp->dev);
5676
5677         /* Initialize receive rules. */
5678         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
5679         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
5680         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
5681         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
5682
5683         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5684                 limit = 8;
5685         else
5686                 limit = 16;
5687         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
5688                 limit -= 4;
5689         switch (limit) {
5690         case 16:
5691                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
5692         case 15:
5693                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
5694         case 14:
5695                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
5696         case 13:
5697                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
5698         case 12:
5699                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
5700         case 11:
5701                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
5702         case 10:
5703                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
5704         case 9:
5705                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
5706         case 8:
5707                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
5708         case 7:
5709                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
5710         case 6:
5711                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
5712         case 5:
5713                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
5714         case 4:
5715                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
5716         case 3:
5717                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
5718         case 2:
5719         case 1:
5720
5721         default:
5722                 break;
5723         };
5724
5725         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
5726
5727         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
5728                 tg3_enable_ints(tp);
5729
5730         return 0;
5731 }
5732
5733 /* Called at device open time to get the chip ready for
5734  * packet processing.  Invoked with tp->lock held.
5735  */
5736 static int tg3_init_hw(struct tg3 *tp)
5737 {
5738         int err;
5739
5740         /* Force the chip into D0. */
5741         err = tg3_set_power_state(tp, 0);
5742         if (err)
5743                 goto out;
5744
5745         tg3_switch_clocks(tp);
5746
5747         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
5748
5749         err = tg3_reset_hw(tp);
5750
5751 out:
5752         return err;
5753 }
5754
5755 #define TG3_STAT_ADD32(PSTAT, REG) \
5756 do {    u32 __val = tr32(REG); \
5757         (PSTAT)->low += __val; \
5758         if ((PSTAT)->low < __val) \
5759                 (PSTAT)->high += 1; \
5760 } while (0)
5761
5762 static void tg3_periodic_fetch_stats(struct tg3 *tp)
5763 {
5764         struct tg3_hw_stats *sp = tp->hw_stats;
5765
5766         if (!netif_carrier_ok(tp->dev))
5767                 return;
5768
5769         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
5770         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
5771         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
5772         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
5773         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
5774         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
5775         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
5776         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
5777         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
5778         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
5779         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
5780         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
5781         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
5782
5783         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
5784         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
5785         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
5786         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
5787         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
5788         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
5789         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
5790         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
5791         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
5792         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
5793         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
5794         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
5795         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
5796         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
5797 }
5798
5799 static void tg3_timer(unsigned long __opaque)
5800 {
5801         struct tg3 *tp = (struct tg3 *) __opaque;
5802
5803         spin_lock(&tp->lock);
5804
5805         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
5806                 /* All of this garbage is because when using non-tagged
5807                  * IRQ status the mailbox/status_block protocol the chip
5808                  * uses with the cpu is race prone.
5809                  */
5810                 if (tp->hw_status->status & SD_STATUS_UPDATED) {
5811                         tw32(GRC_LOCAL_CTRL,
5812                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
5813                 } else {
5814                         tw32(HOSTCC_MODE, tp->coalesce_mode |
5815                              (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
5816                 }
5817
5818                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
5819                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
5820                         spin_unlock(&tp->lock);
5821                         schedule_work(&tp->reset_task);
5822                         return;
5823                 }
5824         }
5825
5826         /* This part only runs once per second. */
5827         if (!--tp->timer_counter) {
5828                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5829                         tg3_periodic_fetch_stats(tp);
5830
5831                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
5832                         u32 mac_stat;
5833                         int phy_event;
5834
5835                         mac_stat = tr32(MAC_STATUS);
5836
5837                         phy_event = 0;
5838                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
5839                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
5840                                         phy_event = 1;
5841                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
5842                                 phy_event = 1;
5843
5844                         if (phy_event)
5845                                 tg3_setup_phy(tp, 0);
5846                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
5847                         u32 mac_stat = tr32(MAC_STATUS);
5848                         int need_setup = 0;
5849
5850                         if (netif_carrier_ok(tp->dev) &&
5851                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
5852                                 need_setup = 1;
5853                         }
5854                         if (! netif_carrier_ok(tp->dev) &&
5855                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
5856                                          MAC_STATUS_SIGNAL_DET))) {
5857                                 need_setup = 1;
5858                         }
5859                         if (need_setup) {
5860                                 tw32_f(MAC_MODE,
5861                                      (tp->mac_mode &
5862                                       ~MAC_MODE_PORT_MODE_MASK));
5863                                 udelay(40);
5864                                 tw32_f(MAC_MODE, tp->mac_mode);
5865                                 udelay(40);
5866                                 tg3_setup_phy(tp, 0);
5867                         }
5868                 }
5869
5870                 tp->timer_counter = tp->timer_multiplier;
5871         }
5872
5873         /* Heartbeat is only sent once every 120 seconds.  */
5874         if (!--tp->asf_counter) {
5875                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5876                         u32 val;
5877
5878                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_ALIVE);
5879                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
5880                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 3);
5881                         val = tr32(GRC_RX_CPU_EVENT);
5882                         val |= (1 << 14);
5883                         tw32(GRC_RX_CPU_EVENT, val);
5884                 }
5885                 tp->asf_counter = tp->asf_multiplier;
5886         }
5887
5888         spin_unlock(&tp->lock);
5889
5890         tp->timer.expires = jiffies + tp->timer_offset;
5891         add_timer(&tp->timer);
5892 }
5893
5894 static int tg3_test_interrupt(struct tg3 *tp)
5895 {
5896         struct net_device *dev = tp->dev;
5897         int err, i;
5898         u32 int_mbox = 0;
5899
5900         if (!netif_running(dev))
5901                 return -ENODEV;
5902
5903         tg3_disable_ints(tp);
5904
5905         free_irq(tp->pdev->irq, dev);
5906
5907         err = request_irq(tp->pdev->irq, tg3_test_isr,
5908                           SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
5909         if (err)
5910                 return err;
5911
5912         tg3_enable_ints(tp);
5913
5914         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
5915                HOSTCC_MODE_NOW);
5916
5917         for (i = 0; i < 5; i++) {
5918                 int_mbox = tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
5919                 if (int_mbox != 0)
5920                         break;
5921                 msleep(10);
5922         }
5923
5924         tg3_disable_ints(tp);
5925
5926         free_irq(tp->pdev->irq, dev);
5927
5928         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
5929                 err = request_irq(tp->pdev->irq, tg3_msi,
5930                                   SA_SAMPLE_RANDOM, dev->name, dev);
5931         else {
5932                 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
5933                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
5934                         fn = tg3_interrupt_tagged;
5935                 err = request_irq(tp->pdev->irq, fn,
5936                                   SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
5937         }
5938
5939         if (err)
5940                 return err;
5941
5942         if (int_mbox != 0)
5943                 return 0;
5944
5945         return -EIO;
5946 }
5947
5948 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
5949  * successfully restored
5950  */
5951 static int tg3_test_msi(struct tg3 *tp)
5952 {
5953         struct net_device *dev = tp->dev;
5954         int err;
5955         u16 pci_cmd;
5956
5957         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
5958                 return 0;
5959
5960         /* Turn off SERR reporting in case MSI terminates with Master
5961          * Abort.
5962          */
5963         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
5964         pci_write_config_word(tp->pdev, PCI_COMMAND,
5965                               pci_cmd & ~PCI_COMMAND_SERR);
5966
5967         err = tg3_test_interrupt(tp);
5968
5969         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
5970
5971         if (!err)
5972                 return 0;
5973
5974         /* other failures */
5975         if (err != -EIO)
5976                 return err;
5977
5978         /* MSI test failed, go back to INTx mode */
5979         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
5980                "switching to INTx mode. Please report this failure to "
5981                "the PCI maintainer and include system chipset information.\n",
5982                        tp->dev->name);
5983
5984         free_irq(tp->pdev->irq, dev);
5985         pci_disable_msi(tp->pdev);
5986
5987         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
5988
5989         {
5990                 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
5991                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
5992                         fn = tg3_interrupt_tagged;
5993
5994                 err = request_irq(tp->pdev->irq, fn,
5995                                   SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
5996         }
5997         if (err)
5998                 return err;
5999
6000         /* Need to reset the chip because the MSI cycle may have terminated
6001          * with Master Abort.
6002          */
6003         tg3_full_lock(tp, 1);
6004
6005         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6006         err = tg3_init_hw(tp);
6007
6008         tg3_full_unlock(tp);
6009
6010         if (err)
6011                 free_irq(tp->pdev->irq, dev);
6012
6013         return err;
6014 }
6015
6016 static int tg3_open(struct net_device *dev)
6017 {
6018         struct tg3 *tp = netdev_priv(dev);
6019         int err;
6020
6021         tg3_full_lock(tp, 0);
6022
6023         tg3_disable_ints(tp);
6024         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
6025
6026         tg3_full_unlock(tp);
6027
6028         /* The placement of this call is tied
6029          * to the setup and use of Host TX descriptors.
6030          */
6031         err = tg3_alloc_consistent(tp);
6032         if (err)
6033                 return err;
6034
6035         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
6036             (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
6037             (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX)) {
6038                 /* All MSI supporting chips should support tagged
6039                  * status.  Assert that this is the case.
6040                  */
6041                 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6042                         printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
6043                                "Not using MSI.\n", tp->dev->name);
6044                 } else if (pci_enable_msi(tp->pdev) == 0) {
6045                         u32 msi_mode;
6046
6047                         msi_mode = tr32(MSGINT_MODE);
6048                         tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
6049                         tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
6050                 }
6051         }
6052         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
6053                 err = request_irq(tp->pdev->irq, tg3_msi,
6054                                   SA_SAMPLE_RANDOM, dev->name, dev);
6055         else {
6056                 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
6057                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6058                         fn = tg3_interrupt_tagged;
6059
6060                 err = request_irq(tp->pdev->irq, fn,
6061                                   SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
6062         }
6063
6064         if (err) {
6065                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6066                         pci_disable_msi(tp->pdev);
6067                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6068                 }
6069                 tg3_free_consistent(tp);
6070                 return err;
6071         }
6072
6073         tg3_full_lock(tp, 0);
6074
6075         err = tg3_init_hw(tp);
6076         if (err) {
6077                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6078                 tg3_free_rings(tp);
6079         } else {
6080                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6081                         tp->timer_offset = HZ;
6082                 else
6083                         tp->timer_offset = HZ / 10;
6084
6085                 BUG_ON(tp->timer_offset > HZ);
6086                 tp->timer_counter = tp->timer_multiplier =
6087                         (HZ / tp->timer_offset);
6088                 tp->asf_counter = tp->asf_multiplier =
6089                         ((HZ / tp->timer_offset) * 120);
6090
6091                 init_timer(&tp->timer);
6092                 tp->timer.expires = jiffies + tp->timer_offset;
6093                 tp->timer.data = (unsigned long) tp;
6094                 tp->timer.function = tg3_timer;
6095         }
6096
6097         tg3_full_unlock(tp);
6098
6099         if (err) {
6100                 free_irq(tp->pdev->irq, dev);
6101                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6102                         pci_disable_msi(tp->pdev);
6103                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6104                 }
6105                 tg3_free_consistent(tp);
6106                 return err;
6107         }
6108
6109         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6110                 err = tg3_test_msi(tp);
6111
6112                 if (err) {
6113                         tg3_full_lock(tp, 0);
6114
6115                         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6116                                 pci_disable_msi(tp->pdev);
6117                                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6118                         }
6119                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6120                         tg3_free_rings(tp);
6121                         tg3_free_consistent(tp);
6122
6123                         tg3_full_unlock(tp);
6124
6125                         return err;
6126                 }
6127         }
6128
6129         tg3_full_lock(tp, 0);
6130
6131         add_timer(&tp->timer);
6132         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
6133         tg3_enable_ints(tp);
6134
6135         tg3_full_unlock(tp);
6136
6137         netif_start_queue(dev);
6138
6139         return 0;
6140 }
6141
6142 #if 0
6143 /*static*/ void tg3_dump_state(struct tg3 *tp)
6144 {
6145         u32 val32, val32_2, val32_3, val32_4, val32_5;
6146         u16 val16;
6147         int i;
6148
6149         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
6150         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
6151         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
6152                val16, val32);
6153
6154         /* MAC block */
6155         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
6156                tr32(MAC_MODE), tr32(MAC_STATUS));
6157         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
6158                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
6159         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
6160                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
6161         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
6162                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
6163
6164         /* Send data initiator control block */
6165         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
6166                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
6167         printk("       SNDDATAI_STATSCTRL[%08x]\n",
6168                tr32(SNDDATAI_STATSCTRL));
6169
6170         /* Send data completion control block */
6171         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
6172
6173         /* Send BD ring selector block */
6174         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
6175                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
6176
6177         /* Send BD initiator control block */
6178         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
6179                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
6180
6181         /* Send BD completion control block */
6182         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
6183
6184         /* Receive list placement control block */
6185         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
6186                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
6187         printk("       RCVLPC_STATSCTRL[%08x]\n",
6188                tr32(RCVLPC_STATSCTRL));
6189
6190         /* Receive data and receive BD initiator control block */
6191         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
6192                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
6193
6194         /* Receive data completion control block */
6195         printk("DEBUG: RCVDCC_MODE[%08x]\n",
6196                tr32(RCVDCC_MODE));
6197
6198         /* Receive BD initiator control block */
6199         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
6200                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
6201
6202         /* Receive BD completion control block */
6203         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
6204                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
6205
6206         /* Receive list selector control block */
6207         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
6208                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
6209
6210         /* Mbuf cluster free block */
6211         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
6212                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
6213
6214         /* Host coalescing control block */
6215         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
6216                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
6217         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
6218                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6219                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6220         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
6221                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6222                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6223         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
6224                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
6225         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
6226                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
6227
6228         /* Memory arbiter control block */
6229         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
6230                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
6231
6232         /* Buffer manager control block */
6233         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
6234                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
6235         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
6236                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
6237         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
6238                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
6239                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
6240                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
6241
6242         /* Read DMA control block */
6243         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
6244                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
6245
6246         /* Write DMA control block */
6247         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
6248                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
6249
6250         /* DMA completion block */
6251         printk("DEBUG: DMAC_MODE[%08x]\n",
6252                tr32(DMAC_MODE));
6253
6254         /* GRC block */
6255         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
6256                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
6257         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
6258                tr32(GRC_LOCAL_CTRL));
6259
6260         /* TG3_BDINFOs */
6261         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
6262                tr32(RCVDBDI_JUMBO_BD + 0x0),
6263                tr32(RCVDBDI_JUMBO_BD + 0x4),
6264                tr32(RCVDBDI_JUMBO_BD + 0x8),
6265                tr32(RCVDBDI_JUMBO_BD + 0xc));
6266         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
6267                tr32(RCVDBDI_STD_BD + 0x0),
6268                tr32(RCVDBDI_STD_BD + 0x4),
6269                tr32(RCVDBDI_STD_BD + 0x8),
6270                tr32(RCVDBDI_STD_BD + 0xc));
6271         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
6272                tr32(RCVDBDI_MINI_BD + 0x0),
6273                tr32(RCVDBDI_MINI_BD + 0x4),
6274                tr32(RCVDBDI_MINI_BD + 0x8),
6275                tr32(RCVDBDI_MINI_BD + 0xc));
6276
6277         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
6278         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
6279         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
6280         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
6281         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
6282                val32, val32_2, val32_3, val32_4);
6283
6284         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
6285         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
6286         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
6287         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
6288         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
6289                val32, val32_2, val32_3, val32_4);
6290
6291         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
6292         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
6293         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
6294         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
6295         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
6296         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
6297                val32, val32_2, val32_3, val32_4, val32_5);
6298
6299         /* SW status block */
6300         printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6301                tp->hw_status->status,
6302                tp->hw_status->status_tag,
6303                tp->hw_status->rx_jumbo_consumer,
6304                tp->hw_status->rx_consumer,
6305                tp->hw_status->rx_mini_consumer,
6306                tp->hw_status->idx[0].rx_producer,
6307                tp->hw_status->idx[0].tx_consumer);
6308
6309         /* SW statistics block */
6310         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
6311                ((u32 *)tp->hw_stats)[0],
6312                ((u32 *)tp->hw_stats)[1],
6313                ((u32 *)tp->hw_stats)[2],
6314                ((u32 *)tp->hw_stats)[3]);
6315
6316         /* Mailboxes */
6317         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
6318                tr32(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
6319                tr32(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
6320                tr32(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
6321                tr32(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
6322
6323         /* NIC side send descriptors. */
6324         for (i = 0; i < 6; i++) {
6325                 unsigned long txd;
6326
6327                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
6328                         + (i * sizeof(struct tg3_tx_buffer_desc));
6329                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
6330                        i,
6331                        readl(txd + 0x0), readl(txd + 0x4),
6332                        readl(txd + 0x8), readl(txd + 0xc));
6333         }
6334
6335         /* NIC side RX descriptors. */
6336         for (i = 0; i < 6; i++) {
6337                 unsigned long rxd;
6338
6339                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
6340                         + (i * sizeof(struct tg3_rx_buffer_desc));
6341                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
6342                        i,
6343                        readl(rxd + 0x0), readl(rxd + 0x4),
6344                        readl(rxd + 0x8), readl(rxd + 0xc));
6345                 rxd += (4 * sizeof(u32));
6346                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
6347                        i,
6348                        readl(rxd + 0x0), readl(rxd + 0x4),
6349                        readl(rxd + 0x8), readl(rxd + 0xc));
6350         }
6351
6352         for (i = 0; i < 6; i++) {
6353                 unsigned long rxd;
6354
6355                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
6356                         + (i * sizeof(struct tg3_rx_buffer_desc));
6357                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
6358                        i,
6359                        readl(rxd + 0x0), readl(rxd + 0x4),
6360                        readl(rxd + 0x8), readl(rxd + 0xc));
6361                 rxd += (4 * sizeof(u32));
6362                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
6363                        i,
6364                        readl(rxd + 0x0), readl(rxd + 0x4),
6365                        readl(rxd + 0x8), readl(rxd + 0xc));
6366         }
6367 }
6368 #endif
6369
6370 static struct net_device_stats *tg3_get_stats(struct net_device *);
6371 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
6372
6373 static int tg3_close(struct net_device *dev)
6374 {
6375         struct tg3 *tp = netdev_priv(dev);
6376
6377         netif_stop_queue(dev);
6378
6379         del_timer_sync(&tp->timer);
6380
6381         tg3_full_lock(tp, 1);
6382 #if 0
6383         tg3_dump_state(tp);
6384 #endif
6385
6386         tg3_disable_ints(tp);
6387
6388         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6389         tg3_free_rings(tp);
6390         tp->tg3_flags &=
6391                 ~(TG3_FLAG_INIT_COMPLETE |
6392                   TG3_FLAG_GOT_SERDES_FLOWCTL);
6393         netif_carrier_off(tp->dev);
6394
6395         tg3_full_unlock(tp);
6396
6397         free_irq(tp->pdev->irq, dev);
6398         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6399                 pci_disable_msi(tp->pdev);
6400                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6401         }
6402
6403         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
6404                sizeof(tp->net_stats_prev));
6405         memcpy(&tp->estats_prev, tg3_get_estats(tp),
6406                sizeof(tp->estats_prev));
6407
6408         tg3_free_consistent(tp);
6409
6410         return 0;
6411 }
6412
6413 static inline unsigned long get_stat64(tg3_stat64_t *val)
6414 {
6415         unsigned long ret;
6416
6417 #if (BITS_PER_LONG == 32)
6418         ret = val->low;
6419 #else
6420         ret = ((u64)val->high << 32) | ((u64)val->low);
6421 #endif
6422         return ret;
6423 }
6424
6425 static unsigned long calc_crc_errors(struct tg3 *tp)
6426 {
6427         struct tg3_hw_stats *hw_stats = tp->hw_stats;
6428
6429         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6430             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
6431              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
6432                 u32 val;
6433
6434                 spin_lock_bh(&tp->lock);
6435                 if (!tg3_readphy(tp, 0x1e, &val)) {
6436                         tg3_writephy(tp, 0x1e, val | 0x8000);
6437                         tg3_readphy(tp, 0x14, &val);
6438                 } else
6439                         val = 0;
6440                 spin_unlock_bh(&tp->lock);
6441
6442                 tp->phy_crc_errors += val;
6443
6444                 return tp->phy_crc_errors;
6445         }
6446
6447         return get_stat64(&hw_stats->rx_fcs_errors);
6448 }
6449
6450 #define ESTAT_ADD(member) \
6451         estats->member =        old_estats->member + \
6452                                 get_stat64(&hw_stats->member)
6453
6454 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
6455 {
6456         struct tg3_ethtool_stats *estats = &tp->estats;
6457         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
6458         struct tg3_hw_stats *hw_stats = tp->hw_stats;
6459
6460         if (!hw_stats)
6461                 return old_estats;
6462
6463         ESTAT_ADD(rx_octets);
6464         ESTAT_ADD(rx_fragments);
6465         ESTAT_ADD(rx_ucast_packets);
6466         ESTAT_ADD(rx_mcast_packets);
6467         ESTAT_ADD(rx_bcast_packets);
6468         ESTAT_ADD(rx_fcs_errors);
6469         ESTAT_ADD(rx_align_errors);
6470         ESTAT_ADD(rx_xon_pause_rcvd);
6471         ESTAT_ADD(rx_xoff_pause_rcvd);
6472         ESTAT_ADD(rx_mac_ctrl_rcvd);
6473         ESTAT_ADD(rx_xoff_entered);
6474         ESTAT_ADD(rx_frame_too_long_errors);
6475         ESTAT_ADD(rx_jabbers);
6476         ESTAT_ADD(rx_undersize_packets);
6477         ESTAT_ADD(rx_in_length_errors);
6478         ESTAT_ADD(rx_out_length_errors);
6479         ESTAT_ADD(rx_64_or_less_octet_packets);
6480         ESTAT_ADD(rx_65_to_127_octet_packets);
6481         ESTAT_ADD(rx_128_to_255_octet_packets);
6482         ESTAT_ADD(rx_256_to_511_octet_packets);
6483         ESTAT_ADD(rx_512_to_1023_octet_packets);
6484         ESTAT_ADD(rx_1024_to_1522_octet_packets);
6485         ESTAT_ADD(rx_1523_to_2047_octet_packets);
6486         ESTAT_ADD(rx_2048_to_4095_octet_packets);
6487         ESTAT_ADD(rx_4096_to_8191_octet_packets);
6488         ESTAT_ADD(rx_8192_to_9022_octet_packets);
6489
6490         ESTAT_ADD(tx_octets);
6491         ESTAT_ADD(tx_collisions);
6492         ESTAT_ADD(tx_xon_sent);
6493         ESTAT_ADD(tx_xoff_sent);
6494         ESTAT_ADD(tx_flow_control);
6495         ESTAT_ADD(tx_mac_errors);
6496         ESTAT_ADD(tx_single_collisions);
6497         ESTAT_ADD(tx_mult_collisions);
6498         ESTAT_ADD(tx_deferred);
6499         ESTAT_ADD(tx_excessive_collisions);
6500         ESTAT_ADD(tx_late_collisions);
6501         ESTAT_ADD(tx_collide_2times);
6502         ESTAT_ADD(tx_collide_3times);
6503         ESTAT_ADD(tx_collide_4times);
6504         ESTAT_ADD(tx_collide_5times);
6505         ESTAT_ADD(tx_collide_6times);
6506         ESTAT_ADD(tx_collide_7times);
6507         ESTAT_ADD(tx_collide_8times);
6508         ESTAT_ADD(tx_collide_9times);
6509         ESTAT_ADD(tx_collide_10times);
6510         ESTAT_ADD(tx_collide_11times);
6511         ESTAT_ADD(tx_collide_12times);
6512         ESTAT_ADD(tx_collide_13times);
6513         ESTAT_ADD(tx_collide_14times);
6514         ESTAT_ADD(tx_collide_15times);
6515         ESTAT_ADD(tx_ucast_packets);
6516         ESTAT_ADD(tx_mcast_packets);
6517         ESTAT_ADD(tx_bcast_packets);
6518         ESTAT_ADD(tx_carrier_sense_errors);
6519         ESTAT_ADD(tx_discards);
6520         ESTAT_ADD(tx_errors);
6521
6522         ESTAT_ADD(dma_writeq_full);
6523         ESTAT_ADD(dma_write_prioq_full);
6524         ESTAT_ADD(rxbds_empty);
6525         ESTAT_ADD(rx_discards);
6526         ESTAT_ADD(rx_errors);
6527         ESTAT_ADD(rx_threshold_hit);
6528
6529         ESTAT_ADD(dma_readq_full);
6530         ESTAT_ADD(dma_read_prioq_full);
6531         ESTAT_ADD(tx_comp_queue_full);
6532
6533         ESTAT_ADD(ring_set_send_prod_index);
6534         ESTAT_ADD(ring_status_update);
6535         ESTAT_ADD(nic_irqs);
6536         ESTAT_ADD(nic_avoided_irqs);
6537         ESTAT_ADD(nic_tx_threshold_hit);
6538
6539         return estats;
6540 }
6541
6542 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
6543 {
6544         struct tg3 *tp = netdev_priv(dev);
6545         struct net_device_stats *stats = &tp->net_stats;
6546         struct net_device_stats *old_stats = &tp->net_stats_prev;
6547         struct tg3_hw_stats *hw_stats = tp->hw_stats;
6548
6549         if (!hw_stats)
6550                 return old_stats;
6551
6552         stats->rx_packets = old_stats->rx_packets +
6553                 get_stat64(&hw_stats->rx_ucast_packets) +
6554                 get_stat64(&hw_stats->rx_mcast_packets) +
6555                 get_stat64(&hw_stats->rx_bcast_packets);
6556
6557         stats->tx_packets = old_stats->tx_packets +
6558                 get_stat64(&hw_stats->tx_ucast_packets) +
6559                 get_stat64(&hw_stats->tx_mcast_packets) +
6560                 get_stat64(&hw_stats->tx_bcast_packets);
6561
6562         stats->rx_bytes = old_stats->rx_bytes +
6563                 get_stat64(&hw_stats->rx_octets);
6564         stats->tx_bytes = old_stats->tx_bytes +
6565                 get_stat64(&hw_stats->tx_octets);
6566
6567         stats->rx_errors = old_stats->rx_errors +
6568                 get_stat64(&hw_stats->rx_errors) +
6569                 get_stat64(&hw_stats->rx_discards);
6570         stats->tx_errors = old_stats->tx_errors +
6571                 get_stat64(&hw_stats->tx_errors) +
6572                 get_stat64(&hw_stats->tx_mac_errors) +
6573                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
6574                 get_stat64(&hw_stats->tx_discards);
6575
6576         stats->multicast = old_stats->multicast +
6577                 get_stat64(&hw_stats->rx_mcast_packets);
6578         stats->collisions = old_stats->collisions +
6579                 get_stat64(&hw_stats->tx_collisions);
6580
6581         stats->rx_length_errors = old_stats->rx_length_errors +
6582                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
6583                 get_stat64(&hw_stats->rx_undersize_packets);
6584
6585         stats->rx_over_errors = old_stats->rx_over_errors +
6586                 get_stat64(&hw_stats->rxbds_empty);
6587         stats->rx_frame_errors = old_stats->rx_frame_errors +
6588                 get_stat64(&hw_stats->rx_align_errors);
6589         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
6590                 get_stat64(&hw_stats->tx_discards);
6591         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
6592                 get_stat64(&hw_stats->tx_carrier_sense_errors);
6593
6594         stats->rx_crc_errors = old_stats->rx_crc_errors +
6595                 calc_crc_errors(tp);
6596
6597         return stats;
6598 }
6599
6600 static inline u32 calc_crc(unsigned char *buf, int len)
6601 {
6602         u32 reg;
6603         u32 tmp;
6604         int j, k;
6605
6606         reg = 0xffffffff;
6607
6608         for (j = 0; j < len; j++) {
6609                 reg ^= buf[j];
6610
6611                 for (k = 0; k < 8; k++) {
6612                         tmp = reg & 0x01;
6613
6614                         reg >>= 1;
6615
6616                         if (tmp) {
6617                                 reg ^= 0xedb88320;
6618                         }
6619                 }
6620         }
6621
6622         return ~reg;
6623 }
6624
6625 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
6626 {
6627         /* accept or reject all multicast frames */
6628         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
6629         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
6630         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
6631         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
6632 }
6633
6634 static void __tg3_set_rx_mode(struct net_device *dev)
6635 {
6636         struct tg3 *tp = netdev_priv(dev);
6637         u32 rx_mode;
6638
6639         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
6640                                   RX_MODE_KEEP_VLAN_TAG);
6641
6642         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
6643          * flag clear.
6644          */
6645 #if TG3_VLAN_TAG_USED
6646         if (!tp->vlgrp &&
6647             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
6648                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
6649 #else
6650         /* By definition, VLAN is disabled always in this
6651          * case.
6652          */
6653         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
6654                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
6655 #endif
6656
6657         if (dev->flags & IFF_PROMISC) {
6658                 /* Promiscuous mode. */
6659                 rx_mode |= RX_MODE_PROMISC;
6660         } else if (dev->flags & IFF_ALLMULTI) {
6661                 /* Accept all multicast. */
6662                 tg3_set_multi (tp, 1);
6663         } else if (dev->mc_count < 1) {
6664                 /* Reject all multicast. */
6665                 tg3_set_multi (tp, 0);
6666         } else {
6667                 /* Accept one or more multicast(s). */
6668                 struct dev_mc_list *mclist;
6669                 unsigned int i;
6670                 u32 mc_filter[4] = { 0, };
6671                 u32 regidx;
6672                 u32 bit;
6673                 u32 crc;
6674
6675                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
6676                      i++, mclist = mclist->next) {
6677
6678                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
6679                         bit = ~crc & 0x7f;
6680                         regidx = (bit & 0x60) >> 5;
6681                         bit &= 0x1f;
6682                         mc_filter[regidx] |= (1 << bit);
6683                 }
6684
6685                 tw32(MAC_HASH_REG_0, mc_filter[0]);
6686                 tw32(MAC_HASH_REG_1, mc_filter[1]);
6687                 tw32(MAC_HASH_REG_2, mc_filter[2]);
6688                 tw32(MAC_HASH_REG_3, mc_filter[3]);
6689         }
6690
6691         if (rx_mode != tp->rx_mode) {
6692                 tp->rx_mode = rx_mode;
6693                 tw32_f(MAC_RX_MODE, rx_mode);
6694                 udelay(10);
6695         }
6696 }
6697
6698 static void tg3_set_rx_mode(struct net_device *dev)
6699 {
6700         struct tg3 *tp = netdev_priv(dev);
6701
6702         tg3_full_lock(tp, 0);
6703         __tg3_set_rx_mode(dev);
6704         tg3_full_unlock(tp);
6705 }
6706
6707 #define TG3_REGDUMP_LEN         (32 * 1024)
6708
6709 static int tg3_get_regs_len(struct net_device *dev)
6710 {
6711         return TG3_REGDUMP_LEN;
6712 }
6713
6714 static void tg3_get_regs(struct net_device *dev,
6715                 struct ethtool_regs *regs, void *_p)
6716 {
6717         u32 *p = _p;
6718         struct tg3 *tp = netdev_priv(dev);
6719         u8 *orig_p = _p;
6720         int i;
6721
6722         regs->version = 0;
6723
6724         memset(p, 0, TG3_REGDUMP_LEN);
6725
6726         tg3_full_lock(tp, 0);
6727
6728 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
6729 #define GET_REG32_LOOP(base,len)                \
6730 do {    p = (u32 *)(orig_p + (base));           \
6731         for (i = 0; i < len; i += 4)            \
6732                 __GET_REG32((base) + i);        \
6733 } while (0)
6734 #define GET_REG32_1(reg)                        \
6735 do {    p = (u32 *)(orig_p + (reg));            \
6736         __GET_REG32((reg));                     \
6737 } while (0)
6738
6739         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
6740         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
6741         GET_REG32_LOOP(MAC_MODE, 0x4f0);
6742         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
6743         GET_REG32_1(SNDDATAC_MODE);
6744         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
6745         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
6746         GET_REG32_1(SNDBDC_MODE);
6747         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
6748         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
6749         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
6750         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
6751         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
6752         GET_REG32_1(RCVDCC_MODE);
6753         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
6754         GET_REG32_LOOP(RCVCC_MODE, 0x14);
6755         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
6756         GET_REG32_1(MBFREE_MODE);
6757         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
6758         GET_REG32_LOOP(MEMARB_MODE, 0x10);
6759         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
6760         GET_REG32_LOOP(RDMAC_MODE, 0x08);
6761         GET_REG32_LOOP(WDMAC_MODE, 0x08);
6762         GET_REG32_LOOP(RX_CPU_BASE, 0x280);
6763         GET_REG32_LOOP(TX_CPU_BASE, 0x280);
6764         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
6765         GET_REG32_LOOP(FTQ_RESET, 0x120);
6766         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
6767         GET_REG32_1(DMAC_MODE);
6768         GET_REG32_LOOP(GRC_MODE, 0x4c);
6769         if (tp->tg3_flags & TG3_FLAG_NVRAM)
6770                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
6771
6772 #undef __GET_REG32
6773 #undef GET_REG32_LOOP
6774 #undef GET_REG32_1
6775
6776         tg3_full_unlock(tp);
6777 }
6778
6779 static int tg3_get_eeprom_len(struct net_device *dev)
6780 {
6781         struct tg3 *tp = netdev_priv(dev);
6782
6783         return tp->nvram_size;
6784 }
6785
6786 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
6787
6788 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
6789 {
6790         struct tg3 *tp = netdev_priv(dev);
6791         int ret;
6792         u8  *pd;
6793         u32 i, offset, len, val, b_offset, b_count;
6794
6795         offset = eeprom->offset;
6796         len = eeprom->len;
6797         eeprom->len = 0;
6798
6799         eeprom->magic = TG3_EEPROM_MAGIC;
6800
6801         if (offset & 3) {
6802                 /* adjustments to start on required 4 byte boundary */
6803                 b_offset = offset & 3;
6804                 b_count = 4 - b_offset;
6805                 if (b_count > len) {
6806                         /* i.e. offset=1 len=2 */
6807                         b_count = len;
6808                 }
6809                 ret = tg3_nvram_read(tp, offset-b_offset, &val);
6810                 if (ret)
6811                         return ret;
6812                 val = cpu_to_le32(val);
6813                 memcpy(data, ((char*)&val) + b_offset, b_count);
6814                 len -= b_count;
6815                 offset += b_count;
6816                 eeprom->len += b_count;
6817         }
6818
6819         /* read bytes upto the last 4 byte boundary */
6820         pd = &data[eeprom->len];
6821         for (i = 0; i < (len - (len & 3)); i += 4) {
6822                 ret = tg3_nvram_read(tp, offset + i, &val);
6823                 if (ret) {
6824                         eeprom->len += i;
6825                         return ret;
6826                 }
6827                 val = cpu_to_le32(val);
6828                 memcpy(pd + i, &val, 4);
6829         }
6830         eeprom->len += i;
6831
6832         if (len & 3) {
6833                 /* read last bytes not ending on 4 byte boundary */
6834                 pd = &data[eeprom->len];
6835                 b_count = len & 3;
6836                 b_offset = offset + len - b_count;
6837                 ret = tg3_nvram_read(tp, b_offset, &val);
6838                 if (ret)
6839                         return ret;
6840                 val = cpu_to_le32(val);
6841                 memcpy(pd, ((char*)&val), b_count);
6842                 eeprom->len += b_count;
6843         }
6844         return 0;
6845 }
6846
6847 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
6848
6849 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
6850 {
6851         struct tg3 *tp = netdev_priv(dev);
6852         int ret;
6853         u32 offset, len, b_offset, odd_len, start, end;
6854         u8 *buf;
6855
6856         if (eeprom->magic != TG3_EEPROM_MAGIC)
6857                 return -EINVAL;
6858
6859         offset = eeprom->offset;
6860         len = eeprom->len;
6861
6862         if ((b_offset = (offset & 3))) {
6863                 /* adjustments to start on required 4 byte boundary */
6864                 ret = tg3_nvram_read(tp, offset-b_offset, &start);
6865                 if (ret)
6866                         return ret;
6867                 start = cpu_to_le32(start);
6868                 len += b_offset;
6869                 offset &= ~3;
6870                 if (len < 4)
6871                         len = 4;
6872         }
6873
6874         odd_len = 0;
6875         if (len & 3) {
6876                 /* adjustments to end on required 4 byte boundary */
6877                 odd_len = 1;
6878                 len = (len + 3) & ~3;
6879                 ret = tg3_nvram_read(tp, offset+len-4, &end);
6880                 if (ret)
6881                         return ret;
6882                 end = cpu_to_le32(end);
6883         }
6884
6885         buf = data;
6886         if (b_offset || odd_len) {
6887                 buf = kmalloc(len, GFP_KERNEL);
6888                 if (buf == 0)
6889                         return -ENOMEM;
6890                 if (b_offset)
6891                         memcpy(buf, &start, 4);
6892                 if (odd_len)
6893                         memcpy(buf+len-4, &end, 4);
6894                 memcpy(buf + b_offset, data, eeprom->len);
6895         }
6896
6897         ret = tg3_nvram_write_block(tp, offset, len, buf);
6898
6899         if (buf != data)
6900                 kfree(buf);
6901
6902         return ret;
6903 }
6904
6905 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6906 {
6907         struct tg3 *tp = netdev_priv(dev);
6908
6909         cmd->supported = (SUPPORTED_Autoneg);
6910
6911         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
6912                 cmd->supported |= (SUPPORTED_1000baseT_Half |
6913                                    SUPPORTED_1000baseT_Full);
6914
6915         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES))
6916                 cmd->supported |= (SUPPORTED_100baseT_Half |
6917                                   SUPPORTED_100baseT_Full |
6918                                   SUPPORTED_10baseT_Half |
6919                                   SUPPORTED_10baseT_Full |
6920                                   SUPPORTED_MII);
6921         else
6922                 cmd->supported |= SUPPORTED_FIBRE;
6923
6924         cmd->advertising = tp->link_config.advertising;
6925         if (netif_running(dev)) {
6926                 cmd->speed = tp->link_config.active_speed;
6927                 cmd->duplex = tp->link_config.active_duplex;
6928         }
6929         cmd->port = 0;
6930         cmd->phy_address = PHY_ADDR;
6931         cmd->transceiver = 0;
6932         cmd->autoneg = tp->link_config.autoneg;
6933         cmd->maxtxpkt = 0;
6934         cmd->maxrxpkt = 0;
6935         return 0;
6936 }
6937
6938 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6939 {
6940         struct tg3 *tp = netdev_priv(dev);
6941
6942         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6943                 /* These are the only valid advertisement bits allowed.  */
6944                 if (cmd->autoneg == AUTONEG_ENABLE &&
6945                     (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
6946                                           ADVERTISED_1000baseT_Full |
6947                                           ADVERTISED_Autoneg |
6948                                           ADVERTISED_FIBRE)))
6949                         return -EINVAL;
6950         }
6951
6952         tg3_full_lock(tp, 0);
6953
6954         tp->link_config.autoneg = cmd->autoneg;
6955         if (cmd->autoneg == AUTONEG_ENABLE) {
6956                 tp->link_config.advertising = cmd->advertising;
6957                 tp->link_config.speed = SPEED_INVALID;
6958                 tp->link_config.duplex = DUPLEX_INVALID;
6959         } else {
6960                 tp->link_config.advertising = 0;
6961                 tp->link_config.speed = cmd->speed;
6962                 tp->link_config.duplex = cmd->duplex;
6963         }
6964
6965         if (netif_running(dev))
6966                 tg3_setup_phy(tp, 1);
6967
6968         tg3_full_unlock(tp);
6969
6970         return 0;
6971 }
6972
6973 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6974 {
6975         struct tg3 *tp = netdev_priv(dev);
6976
6977         strcpy(info->driver, DRV_MODULE_NAME);
6978         strcpy(info->version, DRV_MODULE_VERSION);
6979         strcpy(info->bus_info, pci_name(tp->pdev));
6980 }
6981
6982 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6983 {
6984         struct tg3 *tp = netdev_priv(dev);
6985
6986         wol->supported = WAKE_MAGIC;
6987         wol->wolopts = 0;
6988         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
6989                 wol->wolopts = WAKE_MAGIC;
6990         memset(&wol->sopass, 0, sizeof(wol->sopass));
6991 }
6992
6993 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6994 {
6995         struct tg3 *tp = netdev_priv(dev);
6996
6997         if (wol->wolopts & ~WAKE_MAGIC)
6998                 return -EINVAL;
6999         if ((wol->wolopts & WAKE_MAGIC) &&
7000             tp->tg3_flags2 & TG3_FLG2_PHY_SERDES &&
7001             !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
7002                 return -EINVAL;
7003
7004         spin_lock_bh(&tp->lock);
7005         if (wol->wolopts & WAKE_MAGIC)
7006                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
7007         else
7008                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
7009         spin_unlock_bh(&tp->lock);
7010
7011         return 0;
7012 }
7013
7014 static u32 tg3_get_msglevel(struct net_device *dev)
7015 {
7016         struct tg3 *tp = netdev_priv(dev);
7017         return tp->msg_enable;
7018 }
7019
7020 static void tg3_set_msglevel(struct net_device *dev, u32 value)
7021 {
7022         struct tg3 *tp = netdev_priv(dev);
7023         tp->msg_enable = value;
7024 }
7025
7026 #if TG3_TSO_SUPPORT != 0
7027 static int tg3_set_tso(struct net_device *dev, u32 value)
7028 {
7029         struct tg3 *tp = netdev_priv(dev);
7030
7031         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7032                 if (value)
7033                         return -EINVAL;
7034                 return 0;
7035         }
7036         return ethtool_op_set_tso(dev, value);
7037 }
7038 #endif
7039
7040 static int tg3_nway_reset(struct net_device *dev)
7041 {
7042         struct tg3 *tp = netdev_priv(dev);
7043         u32 bmcr;
7044         int r;
7045
7046         if (!netif_running(dev))
7047                 return -EAGAIN;
7048
7049         spin_lock_bh(&tp->lock);
7050         r = -EINVAL;
7051         tg3_readphy(tp, MII_BMCR, &bmcr);
7052         if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
7053             (bmcr & BMCR_ANENABLE)) {
7054                 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART);
7055                 r = 0;
7056         }
7057         spin_unlock_bh(&tp->lock);
7058
7059         return r;
7060 }
7061
7062 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7063 {
7064         struct tg3 *tp = netdev_priv(dev);
7065
7066         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
7067         ering->rx_mini_max_pending = 0;
7068         ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
7069
7070         ering->rx_pending = tp->rx_pending;
7071         ering->rx_mini_pending = 0;
7072         ering->rx_jumbo_pending = tp->rx_jumbo_pending;
7073         ering->tx_pending = tp->tx_pending;
7074 }
7075
7076 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7077 {
7078         struct tg3 *tp = netdev_priv(dev);
7079
7080         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
7081             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
7082             (ering->tx_pending > TG3_TX_RING_SIZE - 1))
7083                 return -EINVAL;
7084
7085         if (netif_running(dev))
7086                 tg3_netif_stop(tp);
7087
7088         tg3_full_lock(tp, 0);
7089
7090         tp->rx_pending = ering->rx_pending;
7091
7092         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
7093             tp->rx_pending > 63)
7094                 tp->rx_pending = 63;
7095         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
7096         tp->tx_pending = ering->tx_pending;
7097
7098         if (netif_running(dev)) {
7099                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7100                 tg3_init_hw(tp);
7101                 tg3_netif_start(tp);
7102         }
7103
7104         tg3_full_unlock(tp);
7105
7106         return 0;
7107 }
7108
7109 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7110 {
7111         struct tg3 *tp = netdev_priv(dev);
7112
7113         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
7114         epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
7115         epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
7116 }
7117
7118 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7119 {
7120         struct tg3 *tp = netdev_priv(dev);
7121
7122         if (netif_running(dev))
7123                 tg3_netif_stop(tp);
7124
7125         tg3_full_lock(tp, 1);
7126
7127         if (epause->autoneg)
7128                 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
7129         else
7130                 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
7131         if (epause->rx_pause)
7132                 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
7133         else
7134                 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
7135         if (epause->tx_pause)
7136                 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
7137         else
7138                 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
7139
7140         if (netif_running(dev)) {
7141                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7142                 tg3_init_hw(tp);
7143                 tg3_netif_start(tp);
7144         }
7145
7146         tg3_full_unlock(tp);
7147
7148         return 0;
7149 }
7150
7151 static u32 tg3_get_rx_csum(struct net_device *dev)
7152 {
7153         struct tg3 *tp = netdev_priv(dev);
7154         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
7155 }
7156
7157 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
7158 {
7159         struct tg3 *tp = netdev_priv(dev);
7160
7161         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7162                 if (data != 0)
7163                         return -EINVAL;
7164                 return 0;
7165         }
7166
7167         spin_lock_bh(&tp->lock);
7168         if (data)
7169                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
7170         else
7171                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
7172         spin_unlock_bh(&tp->lock);
7173
7174         return 0;
7175 }
7176
7177 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
7178 {
7179         struct tg3 *tp = netdev_priv(dev);
7180
7181         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7182                 if (data != 0)
7183                         return -EINVAL;
7184                 return 0;
7185         }
7186
7187         if (data)
7188                 dev->features |= NETIF_F_IP_CSUM;
7189         else
7190                 dev->features &= ~NETIF_F_IP_CSUM;
7191
7192         return 0;
7193 }
7194
7195 static int tg3_get_stats_count (struct net_device *dev)
7196 {
7197         return TG3_NUM_STATS;
7198 }
7199
7200 static int tg3_get_test_count (struct net_device *dev)
7201 {
7202         return TG3_NUM_TEST;
7203 }
7204
7205 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
7206 {
7207         switch (stringset) {
7208         case ETH_SS_STATS:
7209                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
7210                 break;
7211         case ETH_SS_TEST:
7212                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
7213                 break;
7214         default:
7215                 WARN_ON(1);     /* we need a WARN() */
7216                 break;
7217         }
7218 }
7219
7220 static void tg3_get_ethtool_stats (struct net_device *dev,
7221                                    struct ethtool_stats *estats, u64 *tmp_stats)
7222 {
7223         struct tg3 *tp = netdev_priv(dev);
7224         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
7225 }
7226
7227 #define NVRAM_TEST_SIZE 0x100
7228
7229 static int tg3_test_nvram(struct tg3 *tp)
7230 {
7231         u32 *buf, csum;
7232         int i, j, err = 0;
7233
7234         buf = kmalloc(NVRAM_TEST_SIZE, GFP_KERNEL);
7235         if (buf == NULL)
7236                 return -ENOMEM;
7237
7238         for (i = 0, j = 0; i < NVRAM_TEST_SIZE; i += 4, j++) {
7239                 u32 val;
7240
7241                 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
7242                         break;
7243                 buf[j] = cpu_to_le32(val);
7244         }
7245         if (i < NVRAM_TEST_SIZE)
7246                 goto out;
7247
7248         err = -EIO;
7249         if (cpu_to_be32(buf[0]) != TG3_EEPROM_MAGIC)
7250                 goto out;
7251
7252         /* Bootstrap checksum at offset 0x10 */
7253         csum = calc_crc((unsigned char *) buf, 0x10);
7254         if(csum != cpu_to_le32(buf[0x10/4]))
7255                 goto out;
7256
7257         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
7258         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
7259         if (csum != cpu_to_le32(buf[0xfc/4]))
7260                  goto out;
7261
7262         err = 0;
7263
7264 out:
7265         kfree(buf);
7266         return err;
7267 }
7268
7269 #define TG3_SERDES_TIMEOUT_SEC  2
7270 #define TG3_COPPER_TIMEOUT_SEC  6
7271
7272 static int tg3_test_link(struct tg3 *tp)
7273 {
7274         int i, max;
7275
7276         if (!netif_running(tp->dev))
7277                 return -ENODEV;
7278
7279         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7280                 max = TG3_SERDES_TIMEOUT_SEC;
7281         else
7282                 max = TG3_COPPER_TIMEOUT_SEC;
7283
7284         for (i = 0; i < max; i++) {
7285                 if (netif_carrier_ok(tp->dev))
7286                         return 0;
7287
7288                 if (msleep_interruptible(1000))
7289                         break;
7290         }
7291
7292         return -EIO;
7293 }
7294
7295 /* Only test the commonly used registers */
7296 static int tg3_test_registers(struct tg3 *tp)
7297 {
7298         int i, is_5705;
7299         u32 offset, read_mask, write_mask, val, save_val, read_val;
7300         static struct {
7301                 u16 offset;
7302                 u16 flags;
7303 #define TG3_FL_5705     0x1
7304 #define TG3_FL_NOT_5705 0x2
7305 #define TG3_FL_NOT_5788 0x4
7306                 u32 read_mask;
7307                 u32 write_mask;
7308         } reg_tbl[] = {
7309                 /* MAC Control Registers */
7310                 { MAC_MODE, TG3_FL_NOT_5705,
7311                         0x00000000, 0x00ef6f8c },
7312                 { MAC_MODE, TG3_FL_5705,
7313                         0x00000000, 0x01ef6b8c },
7314                 { MAC_STATUS, TG3_FL_NOT_5705,
7315                         0x03800107, 0x00000000 },
7316                 { MAC_STATUS, TG3_FL_5705,
7317                         0x03800100, 0x00000000 },
7318                 { MAC_ADDR_0_HIGH, 0x0000,
7319                         0x00000000, 0x0000ffff },
7320                 { MAC_ADDR_0_LOW, 0x0000,
7321                         0x00000000, 0xffffffff },
7322                 { MAC_RX_MTU_SIZE, 0x0000,
7323                         0x00000000, 0x0000ffff },
7324                 { MAC_TX_MODE, 0x0000,
7325                         0x00000000, 0x00000070 },
7326                 { MAC_TX_LENGTHS, 0x0000,
7327                         0x00000000, 0x00003fff },
7328                 { MAC_RX_MODE, TG3_FL_NOT_5705,
7329                         0x00000000, 0x000007fc },
7330                 { MAC_RX_MODE, TG3_FL_5705,
7331                         0x00000000, 0x000007dc },
7332                 { MAC_HASH_REG_0, 0x0000,
7333                         0x00000000, 0xffffffff },
7334                 { MAC_HASH_REG_1, 0x0000,
7335                         0x00000000, 0xffffffff },
7336                 { MAC_HASH_REG_2, 0x0000,
7337                         0x00000000, 0xffffffff },
7338                 { MAC_HASH_REG_3, 0x0000,
7339                         0x00000000, 0xffffffff },
7340
7341                 /* Receive Data and Receive BD Initiator Control Registers. */
7342                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
7343                         0x00000000, 0xffffffff },
7344                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
7345                         0x00000000, 0xffffffff },
7346                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
7347                         0x00000000, 0x00000003 },
7348                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
7349                         0x00000000, 0xffffffff },
7350                 { RCVDBDI_STD_BD+0, 0x0000,
7351                         0x00000000, 0xffffffff },
7352                 { RCVDBDI_STD_BD+4, 0x0000,
7353                         0x00000000, 0xffffffff },
7354                 { RCVDBDI_STD_BD+8, 0x0000,
7355                         0x00000000, 0xffff0002 },
7356                 { RCVDBDI_STD_BD+0xc, 0x0000,
7357                         0x00000000, 0xffffffff },
7358
7359                 /* Receive BD Initiator Control Registers. */
7360                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
7361                         0x00000000, 0xffffffff },
7362                 { RCVBDI_STD_THRESH, TG3_FL_5705,
7363                         0x00000000, 0x000003ff },
7364                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
7365                         0x00000000, 0xffffffff },
7366
7367                 /* Host Coalescing Control Registers. */
7368                 { HOSTCC_MODE, TG3_FL_NOT_5705,
7369                         0x00000000, 0x00000004 },
7370                 { HOSTCC_MODE, TG3_FL_5705,
7371                         0x00000000, 0x000000f6 },
7372                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
7373                         0x00000000, 0xffffffff },
7374                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
7375                         0x00000000, 0x000003ff },
7376                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
7377                         0x00000000, 0xffffffff },
7378                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
7379                         0x00000000, 0x000003ff },
7380                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
7381                         0x00000000, 0xffffffff },
7382                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
7383                         0x00000000, 0x000000ff },
7384                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
7385                         0x00000000, 0xffffffff },
7386                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
7387                         0x00000000, 0x000000ff },
7388                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
7389                         0x00000000, 0xffffffff },
7390                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
7391                         0x00000000, 0xffffffff },
7392                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
7393                         0x00000000, 0xffffffff },
7394                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
7395                         0x00000000, 0x000000ff },
7396                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
7397                         0x00000000, 0xffffffff },
7398                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
7399                         0x00000000, 0x000000ff },
7400                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
7401                         0x00000000, 0xffffffff },
7402                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
7403                         0x00000000, 0xffffffff },
7404                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
7405                         0x00000000, 0xffffffff },
7406                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
7407                         0x00000000, 0xffffffff },
7408                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
7409                         0x00000000, 0xffffffff },
7410                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
7411                         0xffffffff, 0x00000000 },
7412                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
7413                         0xffffffff, 0x00000000 },
7414
7415                 /* Buffer Manager Control Registers. */
7416                 { BUFMGR_MB_POOL_ADDR, 0x0000,
7417                         0x00000000, 0x007fff80 },
7418                 { BUFMGR_MB_POOL_SIZE, 0x0000,
7419                         0x00000000, 0x007fffff },
7420                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
7421                         0x00000000, 0x0000003f },
7422                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
7423                         0x00000000, 0x000001ff },
7424                 { BUFMGR_MB_HIGH_WATER, 0x0000,
7425                         0x00000000, 0x000001ff },
7426                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
7427                         0xffffffff, 0x00000000 },
7428                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
7429                         0xffffffff, 0x00000000 },
7430
7431                 /* Mailbox Registers */
7432                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
7433                         0x00000000, 0x000001ff },
7434                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
7435                         0x00000000, 0x000001ff },
7436                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
7437                         0x00000000, 0x000007ff },
7438                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
7439                         0x00000000, 0x000001ff },
7440
7441                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
7442         };
7443
7444         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7445                 is_5705 = 1;
7446         else
7447                 is_5705 = 0;
7448
7449         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
7450                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
7451                         continue;
7452
7453                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
7454                         continue;
7455
7456                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7457                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
7458                         continue;
7459
7460                 offset = (u32) reg_tbl[i].offset;
7461                 read_mask = reg_tbl[i].read_mask;
7462                 write_mask = reg_tbl[i].write_mask;
7463
7464                 /* Save the original register content */
7465                 save_val = tr32(offset);
7466
7467                 /* Determine the read-only value. */
7468                 read_val = save_val & read_mask;
7469
7470                 /* Write zero to the register, then make sure the read-only bits
7471                  * are not changed and the read/write bits are all zeros.
7472                  */
7473                 tw32(offset, 0);
7474
7475                 val = tr32(offset);
7476
7477                 /* Test the read-only and read/write bits. */
7478                 if (((val & read_mask) != read_val) || (val & write_mask))
7479                         goto out;
7480
7481                 /* Write ones to all the bits defined by RdMask and WrMask, then
7482                  * make sure the read-only bits are not changed and the
7483                  * read/write bits are all ones.
7484                  */
7485                 tw32(offset, read_mask | write_mask);
7486
7487                 val = tr32(offset);
7488
7489                 /* Test the read-only bits. */
7490                 if ((val & read_mask) != read_val)
7491                         goto out;
7492
7493                 /* Test the read/write bits. */
7494                 if ((val & write_mask) != write_mask)
7495                         goto out;
7496
7497                 tw32(offset, save_val);
7498         }
7499
7500         return 0;
7501
7502 out:
7503         printk(KERN_ERR PFX "Register test failed at offset %x\n", offset);
7504         tw32(offset, save_val);
7505         return -EIO;
7506 }
7507
7508 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
7509 {
7510         static u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7511         int i;
7512         u32 j;
7513
7514         for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
7515                 for (j = 0; j < len; j += 4) {
7516                         u32 val;
7517
7518                         tg3_write_mem(tp, offset + j, test_pattern[i]);
7519                         tg3_read_mem(tp, offset + j, &val);
7520                         if (val != test_pattern[i])
7521                                 return -EIO;
7522                 }
7523         }
7524         return 0;
7525 }
7526
7527 static int tg3_test_memory(struct tg3 *tp)
7528 {
7529         static struct mem_entry {
7530                 u32 offset;
7531                 u32 len;
7532         } mem_tbl_570x[] = {
7533                 { 0x00000000, 0x01000},
7534                 { 0x00002000, 0x1c000},
7535                 { 0xffffffff, 0x00000}
7536         }, mem_tbl_5705[] = {
7537                 { 0x00000100, 0x0000c},
7538                 { 0x00000200, 0x00008},
7539                 { 0x00000b50, 0x00400},
7540                 { 0x00004000, 0x00800},
7541                 { 0x00006000, 0x01000},
7542                 { 0x00008000, 0x02000},
7543                 { 0x00010000, 0x0e000},
7544                 { 0xffffffff, 0x00000}
7545         };
7546         struct mem_entry *mem_tbl;
7547         int err = 0;
7548         int i;
7549
7550         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7551                 mem_tbl = mem_tbl_5705;
7552         else
7553                 mem_tbl = mem_tbl_570x;
7554
7555         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
7556                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
7557                     mem_tbl[i].len)) != 0)
7558                         break;
7559         }
7560
7561         return err;
7562 }
7563
7564 static int tg3_test_loopback(struct tg3 *tp)
7565 {
7566         u32 mac_mode, send_idx, rx_start_idx, rx_idx, tx_idx, opaque_key;
7567         u32 desc_idx;
7568         struct sk_buff *skb, *rx_skb;
7569         u8 *tx_data;
7570         dma_addr_t map;
7571         int num_pkts, tx_len, rx_len, i, err;
7572         struct tg3_rx_buffer_desc *desc;
7573
7574         if (!netif_running(tp->dev))
7575                 return -ENODEV;
7576
7577         err = -EIO;
7578
7579         tg3_abort_hw(tp, 1);
7580
7581         /* Clearing this flag to keep interrupts disabled */
7582         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7583         tg3_reset_hw(tp);
7584
7585         mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
7586                    MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY |
7587                    MAC_MODE_PORT_MODE_GMII;
7588         tw32(MAC_MODE, mac_mode);
7589
7590         tx_len = 1514;
7591         skb = dev_alloc_skb(tx_len);
7592         tx_data = skb_put(skb, tx_len);
7593         memcpy(tx_data, tp->dev->dev_addr, 6);
7594         memset(tx_data + 6, 0x0, 8);
7595
7596         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
7597
7598         for (i = 14; i < tx_len; i++)
7599                 tx_data[i] = (u8) (i & 0xff);
7600
7601         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
7602
7603         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7604              HOSTCC_MODE_NOW);
7605
7606         udelay(10);
7607
7608         rx_start_idx = tp->hw_status->idx[0].rx_producer;
7609
7610         send_idx = 0;
7611         num_pkts = 0;
7612
7613         tg3_set_txd(tp, send_idx, map, tx_len, 0, 1);
7614
7615         send_idx++;
7616         num_pkts++;
7617
7618         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, send_idx);
7619         tr32(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
7620
7621         udelay(10);
7622
7623         for (i = 0; i < 10; i++) {
7624                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7625                        HOSTCC_MODE_NOW);
7626
7627                 udelay(10);
7628
7629                 tx_idx = tp->hw_status->idx[0].tx_consumer;
7630                 rx_idx = tp->hw_status->idx[0].rx_producer;
7631                 if ((tx_idx == send_idx) &&
7632                     (rx_idx == (rx_start_idx + num_pkts)))
7633                         break;
7634         }
7635
7636         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
7637         dev_kfree_skb(skb);
7638
7639         if (tx_idx != send_idx)
7640                 goto out;
7641
7642         if (rx_idx != rx_start_idx + num_pkts)
7643                 goto out;
7644
7645         desc = &tp->rx_rcb[rx_start_idx];
7646         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
7647         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
7648         if (opaque_key != RXD_OPAQUE_RING_STD)
7649                 goto out;
7650
7651         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
7652             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
7653                 goto out;
7654
7655         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
7656         if (rx_len != tx_len)
7657                 goto out;
7658
7659         rx_skb = tp->rx_std_buffers[desc_idx].skb;
7660
7661         map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
7662         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
7663
7664         for (i = 14; i < tx_len; i++) {
7665                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
7666                         goto out;
7667         }
7668         err = 0;
7669
7670         /* tg3_free_rings will unmap and free the rx_skb */
7671 out:
7672         return err;
7673 }
7674
7675 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
7676                           u64 *data)
7677 {
7678         struct tg3 *tp = netdev_priv(dev);
7679
7680         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
7681
7682         if (tg3_test_nvram(tp) != 0) {
7683                 etest->flags |= ETH_TEST_FL_FAILED;
7684                 data[0] = 1;
7685         }
7686         if (tg3_test_link(tp) != 0) {
7687                 etest->flags |= ETH_TEST_FL_FAILED;
7688                 data[1] = 1;
7689         }
7690         if (etest->flags & ETH_TEST_FL_OFFLINE) {
7691                 if (netif_running(dev))
7692                         tg3_netif_stop(tp);
7693
7694                 tg3_full_lock(tp, 1);
7695
7696                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
7697                 tg3_nvram_lock(tp);
7698                 tg3_halt_cpu(tp, RX_CPU_BASE);
7699                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7700                         tg3_halt_cpu(tp, TX_CPU_BASE);
7701                 tg3_nvram_unlock(tp);
7702
7703                 if (tg3_test_registers(tp) != 0) {
7704                         etest->flags |= ETH_TEST_FL_FAILED;
7705                         data[2] = 1;
7706                 }
7707                 if (tg3_test_memory(tp) != 0) {
7708                         etest->flags |= ETH_TEST_FL_FAILED;
7709                         data[3] = 1;
7710                 }
7711                 if (tg3_test_loopback(tp) != 0) {
7712                         etest->flags |= ETH_TEST_FL_FAILED;
7713                         data[4] = 1;
7714                 }
7715
7716                 tg3_full_unlock(tp);
7717
7718                 if (tg3_test_interrupt(tp) != 0) {
7719                         etest->flags |= ETH_TEST_FL_FAILED;
7720                         data[5] = 1;
7721                 }
7722
7723                 tg3_full_lock(tp, 0);
7724
7725                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7726                 if (netif_running(dev)) {
7727                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7728                         tg3_init_hw(tp);
7729                         tg3_netif_start(tp);
7730                 }
7731
7732                 tg3_full_unlock(tp);
7733         }
7734 }
7735
7736 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7737 {
7738         struct mii_ioctl_data *data = if_mii(ifr);
7739         struct tg3 *tp = netdev_priv(dev);
7740         int err;
7741
7742         switch(cmd) {
7743         case SIOCGMIIPHY:
7744                 data->phy_id = PHY_ADDR;
7745
7746                 /* fallthru */
7747         case SIOCGMIIREG: {
7748                 u32 mii_regval;
7749
7750                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7751                         break;                  /* We have no PHY */
7752
7753                 spin_lock_bh(&tp->lock);
7754                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
7755                 spin_unlock_bh(&tp->lock);
7756
7757                 data->val_out = mii_regval;
7758
7759                 return err;
7760         }
7761
7762         case SIOCSMIIREG:
7763                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7764                         break;                  /* We have no PHY */
7765
7766                 if (!capable(CAP_NET_ADMIN))
7767                         return -EPERM;
7768
7769                 spin_lock_bh(&tp->lock);
7770                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
7771                 spin_unlock_bh(&tp->lock);
7772
7773                 return err;
7774
7775         default:
7776                 /* do nothing */
7777                 break;
7778         }
7779         return -EOPNOTSUPP;
7780 }
7781
7782 #if TG3_VLAN_TAG_USED
7783 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
7784 {
7785         struct tg3 *tp = netdev_priv(dev);
7786
7787         tg3_full_lock(tp, 0);
7788
7789         tp->vlgrp = grp;
7790
7791         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
7792         __tg3_set_rx_mode(dev);
7793
7794         tg3_full_unlock(tp);
7795 }
7796
7797 static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
7798 {
7799         struct tg3 *tp = netdev_priv(dev);
7800
7801         tg3_full_lock(tp, 0);
7802         if (tp->vlgrp)
7803                 tp->vlgrp->vlan_devices[vid] = NULL;
7804         tg3_full_unlock(tp);
7805 }
7806 #endif
7807
7808 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
7809 {
7810         struct tg3 *tp = netdev_priv(dev);
7811
7812         memcpy(ec, &tp->coal, sizeof(*ec));
7813         return 0;
7814 }
7815
7816 static struct ethtool_ops tg3_ethtool_ops = {
7817         .get_settings           = tg3_get_settings,
7818         .set_settings           = tg3_set_settings,
7819         .get_drvinfo            = tg3_get_drvinfo,
7820         .get_regs_len           = tg3_get_regs_len,
7821         .get_regs               = tg3_get_regs,
7822         .get_wol                = tg3_get_wol,
7823         .set_wol                = tg3_set_wol,
7824         .get_msglevel           = tg3_get_msglevel,
7825         .set_msglevel           = tg3_set_msglevel,
7826         .nway_reset             = tg3_nway_reset,
7827         .get_link               = ethtool_op_get_link,
7828         .get_eeprom_len         = tg3_get_eeprom_len,
7829         .get_eeprom             = tg3_get_eeprom,
7830         .set_eeprom             = tg3_set_eeprom,
7831         .get_ringparam          = tg3_get_ringparam,
7832         .set_ringparam          = tg3_set_ringparam,
7833         .get_pauseparam         = tg3_get_pauseparam,
7834         .set_pauseparam         = tg3_set_pauseparam,
7835         .get_rx_csum            = tg3_get_rx_csum,
7836         .set_rx_csum            = tg3_set_rx_csum,
7837         .get_tx_csum            = ethtool_op_get_tx_csum,
7838         .set_tx_csum            = tg3_set_tx_csum,
7839         .get_sg                 = ethtool_op_get_sg,
7840         .set_sg                 = ethtool_op_set_sg,
7841 #if TG3_TSO_SUPPORT != 0
7842         .get_tso                = ethtool_op_get_tso,
7843         .set_tso                = tg3_set_tso,
7844 #endif
7845         .self_test_count        = tg3_get_test_count,
7846         .self_test              = tg3_self_test,
7847         .get_strings            = tg3_get_strings,
7848         .get_stats_count        = tg3_get_stats_count,
7849         .get_ethtool_stats      = tg3_get_ethtool_stats,
7850         .get_coalesce           = tg3_get_coalesce,
7851 };
7852
7853 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
7854 {
7855         u32 cursize, val;
7856
7857         tp->nvram_size = EEPROM_CHIP_SIZE;
7858
7859         if (tg3_nvram_read(tp, 0, &val) != 0)
7860                 return;
7861
7862         if (swab32(val) != TG3_EEPROM_MAGIC)
7863                 return;
7864
7865         /*
7866          * Size the chip by reading offsets at increasing powers of two.
7867          * When we encounter our validation signature, we know the addressing
7868          * has wrapped around, and thus have our chip size.
7869          */
7870         cursize = 0x800;
7871
7872         while (cursize < tp->nvram_size) {
7873                 if (tg3_nvram_read(tp, cursize, &val) != 0)
7874                         return;
7875
7876                 if (swab32(val) == TG3_EEPROM_MAGIC)
7877                         break;
7878
7879                 cursize <<= 1;
7880         }
7881
7882         tp->nvram_size = cursize;
7883 }
7884
7885 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
7886 {
7887         u32 val;
7888
7889         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
7890                 if (val != 0) {
7891                         tp->nvram_size = (val >> 16) * 1024;
7892                         return;
7893                 }
7894         }
7895         tp->nvram_size = 0x20000;
7896 }
7897
7898 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
7899 {
7900         u32 nvcfg1;
7901
7902         nvcfg1 = tr32(NVRAM_CFG1);
7903         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
7904                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
7905         }
7906         else {
7907                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
7908                 tw32(NVRAM_CFG1, nvcfg1);
7909         }
7910
7911         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7912                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
7913                         case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
7914                                 tp->nvram_jedecnum = JEDEC_ATMEL;
7915                                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
7916                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7917                                 break;
7918                         case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
7919                                 tp->nvram_jedecnum = JEDEC_ATMEL;
7920                                 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
7921                                 break;
7922                         case FLASH_VENDOR_ATMEL_EEPROM:
7923                                 tp->nvram_jedecnum = JEDEC_ATMEL;
7924                                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
7925                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7926                                 break;
7927                         case FLASH_VENDOR_ST:
7928                                 tp->nvram_jedecnum = JEDEC_ST;
7929                                 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
7930                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7931                                 break;
7932                         case FLASH_VENDOR_SAIFUN:
7933                                 tp->nvram_jedecnum = JEDEC_SAIFUN;
7934                                 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
7935                                 break;
7936                         case FLASH_VENDOR_SST_SMALL:
7937                         case FLASH_VENDOR_SST_LARGE:
7938                                 tp->nvram_jedecnum = JEDEC_SST;
7939                                 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
7940                                 break;
7941                 }
7942         }
7943         else {
7944                 tp->nvram_jedecnum = JEDEC_ATMEL;
7945                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
7946                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7947         }
7948 }
7949
7950 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
7951 {
7952         u32 nvcfg1;
7953
7954         nvcfg1 = tr32(NVRAM_CFG1);
7955
7956         /* NVRAM protection for TPM */
7957         if (nvcfg1 & (1 << 27))
7958                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
7959
7960         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
7961                 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
7962                 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
7963                         tp->nvram_jedecnum = JEDEC_ATMEL;
7964                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7965                         break;
7966                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
7967                         tp->nvram_jedecnum = JEDEC_ATMEL;
7968                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7969                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
7970                         break;
7971                 case FLASH_5752VENDOR_ST_M45PE10:
7972                 case FLASH_5752VENDOR_ST_M45PE20:
7973                 case FLASH_5752VENDOR_ST_M45PE40:
7974                         tp->nvram_jedecnum = JEDEC_ST;
7975                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7976                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
7977                         break;
7978         }
7979
7980         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
7981                 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
7982                         case FLASH_5752PAGE_SIZE_256:
7983                                 tp->nvram_pagesize = 256;
7984                                 break;
7985                         case FLASH_5752PAGE_SIZE_512:
7986                                 tp->nvram_pagesize = 512;
7987                                 break;
7988                         case FLASH_5752PAGE_SIZE_1K:
7989                                 tp->nvram_pagesize = 1024;
7990                                 break;
7991                         case FLASH_5752PAGE_SIZE_2K:
7992                                 tp->nvram_pagesize = 2048;
7993                                 break;
7994                         case FLASH_5752PAGE_SIZE_4K:
7995                                 tp->nvram_pagesize = 4096;
7996                                 break;
7997                         case FLASH_5752PAGE_SIZE_264:
7998                                 tp->nvram_pagesize = 264;
7999                                 break;
8000                 }
8001         }
8002         else {
8003                 /* For eeprom, set pagesize to maximum eeprom size */
8004                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
8005
8006                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
8007                 tw32(NVRAM_CFG1, nvcfg1);
8008         }
8009 }
8010
8011 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
8012 static void __devinit tg3_nvram_init(struct tg3 *tp)
8013 {
8014         int j;
8015
8016         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X)
8017                 return;
8018
8019         tw32_f(GRC_EEPROM_ADDR,
8020              (EEPROM_ADDR_FSM_RESET |
8021               (EEPROM_DEFAULT_CLOCK_PERIOD <<
8022                EEPROM_ADDR_CLKPERD_SHIFT)));
8023
8024         /* XXX schedule_timeout() ... */
8025         for (j = 0; j < 100; j++)
8026                 udelay(10);
8027
8028         /* Enable seeprom accesses. */
8029         tw32_f(GRC_LOCAL_CTRL,
8030              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
8031         udelay(100);
8032
8033         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
8034             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
8035                 tp->tg3_flags |= TG3_FLAG_NVRAM;
8036
8037                 tg3_enable_nvram_access(tp);
8038
8039                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8040                         tg3_get_5752_nvram_info(tp);
8041                 else
8042                         tg3_get_nvram_info(tp);
8043
8044                 tg3_get_nvram_size(tp);
8045
8046                 tg3_disable_nvram_access(tp);
8047
8048         } else {
8049                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
8050
8051                 tg3_get_eeprom_size(tp);
8052         }
8053 }
8054
8055 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
8056                                         u32 offset, u32 *val)
8057 {
8058         u32 tmp;
8059         int i;
8060
8061         if (offset > EEPROM_ADDR_ADDR_MASK ||
8062             (offset % 4) != 0)
8063                 return -EINVAL;
8064
8065         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
8066                                         EEPROM_ADDR_DEVID_MASK |
8067                                         EEPROM_ADDR_READ);
8068         tw32(GRC_EEPROM_ADDR,
8069              tmp |
8070              (0 << EEPROM_ADDR_DEVID_SHIFT) |
8071              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
8072               EEPROM_ADDR_ADDR_MASK) |
8073              EEPROM_ADDR_READ | EEPROM_ADDR_START);
8074
8075         for (i = 0; i < 10000; i++) {
8076                 tmp = tr32(GRC_EEPROM_ADDR);
8077
8078                 if (tmp & EEPROM_ADDR_COMPLETE)
8079                         break;
8080                 udelay(100);
8081         }
8082         if (!(tmp & EEPROM_ADDR_COMPLETE))
8083                 return -EBUSY;
8084
8085         *val = tr32(GRC_EEPROM_DATA);
8086         return 0;
8087 }
8088
8089 #define NVRAM_CMD_TIMEOUT 10000
8090
8091 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
8092 {
8093         int i;
8094
8095         tw32(NVRAM_CMD, nvram_cmd);
8096         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
8097                 udelay(10);
8098                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
8099                         udelay(10);
8100                         break;
8101                 }
8102         }
8103         if (i == NVRAM_CMD_TIMEOUT) {
8104                 return -EBUSY;
8105         }
8106         return 0;
8107 }
8108
8109 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
8110 {
8111         int ret;
8112
8113         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
8114                 printk(KERN_ERR PFX "Attempt to do nvram_read on Sun 570X\n");
8115                 return -EINVAL;
8116         }
8117
8118         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
8119                 return tg3_nvram_read_using_eeprom(tp, offset, val);
8120
8121         if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
8122                 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
8123                 (tp->nvram_jedecnum == JEDEC_ATMEL)) {
8124
8125                 offset = ((offset / tp->nvram_pagesize) <<
8126                           ATMEL_AT45DB0X1B_PAGE_POS) +
8127                         (offset % tp->nvram_pagesize);
8128         }
8129
8130         if (offset > NVRAM_ADDR_MSK)
8131                 return -EINVAL;
8132
8133         tg3_nvram_lock(tp);
8134
8135         tg3_enable_nvram_access(tp);
8136
8137         tw32(NVRAM_ADDR, offset);
8138         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
8139                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
8140
8141         if (ret == 0)
8142                 *val = swab32(tr32(NVRAM_RDDATA));
8143
8144         tg3_nvram_unlock(tp);
8145
8146         tg3_disable_nvram_access(tp);
8147
8148         return ret;
8149 }
8150
8151 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
8152                                     u32 offset, u32 len, u8 *buf)
8153 {
8154         int i, j, rc = 0;
8155         u32 val;
8156
8157         for (i = 0; i < len; i += 4) {
8158                 u32 addr, data;
8159
8160                 addr = offset + i;
8161
8162                 memcpy(&data, buf + i, 4);
8163
8164                 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
8165
8166                 val = tr32(GRC_EEPROM_ADDR);
8167                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
8168
8169                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
8170                         EEPROM_ADDR_READ);
8171                 tw32(GRC_EEPROM_ADDR, val |
8172                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
8173                         (addr & EEPROM_ADDR_ADDR_MASK) |
8174                         EEPROM_ADDR_START |
8175                         EEPROM_ADDR_WRITE);
8176
8177                 for (j = 0; j < 10000; j++) {
8178                         val = tr32(GRC_EEPROM_ADDR);
8179
8180                         if (val & EEPROM_ADDR_COMPLETE)
8181                                 break;
8182                         udelay(100);
8183                 }
8184                 if (!(val & EEPROM_ADDR_COMPLETE)) {
8185                         rc = -EBUSY;
8186                         break;
8187                 }
8188         }
8189
8190         return rc;
8191 }
8192
8193 /* offset and length are dword aligned */
8194 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
8195                 u8 *buf)
8196 {
8197         int ret = 0;
8198         u32 pagesize = tp->nvram_pagesize;
8199         u32 pagemask = pagesize - 1;
8200         u32 nvram_cmd;
8201         u8 *tmp;
8202
8203         tmp = kmalloc(pagesize, GFP_KERNEL);
8204         if (tmp == NULL)
8205                 return -ENOMEM;
8206
8207         while (len) {
8208                 int j;
8209                 u32 phy_addr, page_off, size;
8210
8211                 phy_addr = offset & ~pagemask;
8212
8213                 for (j = 0; j < pagesize; j += 4) {
8214                         if ((ret = tg3_nvram_read(tp, phy_addr + j,
8215                                                 (u32 *) (tmp + j))))
8216                                 break;
8217                 }
8218                 if (ret)
8219                         break;
8220
8221                 page_off = offset & pagemask;
8222                 size = pagesize;
8223                 if (len < size)
8224                         size = len;
8225
8226                 len -= size;
8227
8228                 memcpy(tmp + page_off, buf, size);
8229
8230                 offset = offset + (pagesize - page_off);
8231
8232                 tg3_enable_nvram_access(tp);
8233
8234                 /*
8235                  * Before we can erase the flash page, we need
8236                  * to issue a special "write enable" command.
8237                  */
8238                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8239
8240                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8241                         break;
8242
8243                 /* Erase the target page */
8244                 tw32(NVRAM_ADDR, phy_addr);
8245
8246                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
8247                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
8248
8249                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8250                         break;
8251
8252                 /* Issue another write enable to start the write. */
8253                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8254
8255                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8256                         break;
8257
8258                 for (j = 0; j < pagesize; j += 4) {
8259                         u32 data;
8260
8261                         data = *((u32 *) (tmp + j));
8262                         tw32(NVRAM_WRDATA, cpu_to_be32(data));
8263
8264                         tw32(NVRAM_ADDR, phy_addr + j);
8265
8266                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
8267                                 NVRAM_CMD_WR;
8268
8269                         if (j == 0)
8270                                 nvram_cmd |= NVRAM_CMD_FIRST;
8271                         else if (j == (pagesize - 4))
8272                                 nvram_cmd |= NVRAM_CMD_LAST;
8273
8274                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
8275                                 break;
8276                 }
8277                 if (ret)
8278                         break;
8279         }
8280
8281         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8282         tg3_nvram_exec_cmd(tp, nvram_cmd);
8283
8284         kfree(tmp);
8285
8286         return ret;
8287 }
8288
8289 /* offset and length are dword aligned */
8290 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
8291                 u8 *buf)
8292 {
8293         int i, ret = 0;
8294
8295         for (i = 0; i < len; i += 4, offset += 4) {
8296                 u32 data, page_off, phy_addr, nvram_cmd;
8297
8298                 memcpy(&data, buf + i, 4);
8299                 tw32(NVRAM_WRDATA, cpu_to_be32(data));
8300
8301                 page_off = offset % tp->nvram_pagesize;
8302
8303                 if ((tp->tg3_flags2 & TG3_FLG2_FLASH) &&
8304                         (tp->nvram_jedecnum == JEDEC_ATMEL)) {
8305
8306                         phy_addr = ((offset / tp->nvram_pagesize) <<
8307                                     ATMEL_AT45DB0X1B_PAGE_POS) + page_off;
8308                 }
8309                 else {
8310                         phy_addr = offset;
8311                 }
8312
8313                 tw32(NVRAM_ADDR, phy_addr);
8314
8315                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
8316
8317                 if ((page_off == 0) || (i == 0))
8318                         nvram_cmd |= NVRAM_CMD_FIRST;
8319                 else if (page_off == (tp->nvram_pagesize - 4))
8320                         nvram_cmd |= NVRAM_CMD_LAST;
8321
8322                 if (i == (len - 4))
8323                         nvram_cmd |= NVRAM_CMD_LAST;
8324
8325                 if ((tp->nvram_jedecnum == JEDEC_ST) &&
8326                         (nvram_cmd & NVRAM_CMD_FIRST)) {
8327
8328                         if ((ret = tg3_nvram_exec_cmd(tp,
8329                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
8330                                 NVRAM_CMD_DONE)))
8331
8332                                 break;
8333                 }
8334                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
8335                         /* We always do complete word writes to eeprom. */
8336                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
8337                 }
8338
8339                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
8340                         break;
8341         }
8342         return ret;
8343 }
8344
8345 /* offset and length are dword aligned */
8346 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
8347 {
8348         int ret;
8349
8350         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
8351                 printk(KERN_ERR PFX "Attempt to do nvram_write on Sun 570X\n");
8352                 return -EINVAL;
8353         }
8354
8355         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
8356                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
8357                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
8358                 udelay(40);
8359         }
8360
8361         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
8362                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
8363         }
8364         else {
8365                 u32 grc_mode;
8366
8367                 tg3_nvram_lock(tp);
8368
8369                 tg3_enable_nvram_access(tp);
8370                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
8371                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
8372                         tw32(NVRAM_WRITE1, 0x406);
8373
8374                 grc_mode = tr32(GRC_MODE);
8375                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
8376
8377                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
8378                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
8379
8380                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
8381                                 buf);
8382                 }
8383                 else {
8384                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
8385                                 buf);
8386                 }
8387
8388                 grc_mode = tr32(GRC_MODE);
8389                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
8390
8391                 tg3_disable_nvram_access(tp);
8392                 tg3_nvram_unlock(tp);
8393         }
8394
8395         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
8396                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8397                 udelay(40);
8398         }
8399
8400         return ret;
8401 }
8402
8403 struct subsys_tbl_ent {
8404         u16 subsys_vendor, subsys_devid;
8405         u32 phy_id;
8406 };
8407
8408 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
8409         /* Broadcom boards. */
8410         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
8411         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
8412         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
8413         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
8414         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
8415         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
8416         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
8417         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
8418         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
8419         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
8420         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
8421
8422         /* 3com boards. */
8423         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
8424         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
8425         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
8426         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
8427         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
8428
8429         /* DELL boards. */
8430         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
8431         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
8432         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
8433         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
8434
8435         /* Compaq boards. */
8436         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
8437         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
8438         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
8439         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
8440         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
8441
8442         /* IBM boards. */
8443         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
8444 };
8445
8446 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
8447 {
8448         int i;
8449
8450         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
8451                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
8452                      tp->pdev->subsystem_vendor) &&
8453                     (subsys_id_to_phy_id[i].subsys_devid ==
8454                      tp->pdev->subsystem_device))
8455                         return &subsys_id_to_phy_id[i];
8456         }
8457         return NULL;
8458 }
8459
8460 /* Since this function may be called in D3-hot power state during
8461  * tg3_init_one(), only config cycles are allowed.
8462  */
8463 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
8464 {
8465         u32 val;
8466
8467         /* Make sure register accesses (indirect or otherwise)
8468          * will function correctly.
8469          */
8470         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8471                                tp->misc_host_ctrl);
8472
8473         tp->phy_id = PHY_ID_INVALID;
8474         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
8475
8476         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
8477         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
8478                 u32 nic_cfg, led_cfg;
8479                 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
8480                 int eeprom_phy_serdes = 0;
8481
8482                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
8483                 tp->nic_sram_data_cfg = nic_cfg;
8484
8485                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
8486                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
8487                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
8488                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
8489                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
8490                     (ver > 0) && (ver < 0x100))
8491                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
8492
8493                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
8494                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
8495                         eeprom_phy_serdes = 1;
8496
8497                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
8498                 if (nic_phy_id != 0) {
8499                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
8500                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
8501
8502                         eeprom_phy_id  = (id1 >> 16) << 10;
8503                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
8504                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
8505                 } else
8506                         eeprom_phy_id = 0;
8507
8508                 tp->phy_id = eeprom_phy_id;
8509                 if (eeprom_phy_serdes)
8510                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
8511
8512                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8513                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
8514                                     SHASTA_EXT_LED_MODE_MASK);
8515                 else
8516                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
8517
8518                 switch (led_cfg) {
8519                 default:
8520                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
8521                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
8522                         break;
8523
8524                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
8525                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
8526                         break;
8527
8528                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
8529                         tp->led_ctrl = LED_CTRL_MODE_MAC;
8530
8531                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
8532                          * read on some older 5700/5701 bootcode.
8533                          */
8534                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
8535                             ASIC_REV_5700 ||
8536                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
8537                             ASIC_REV_5701)
8538                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
8539
8540                         break;
8541
8542                 case SHASTA_EXT_LED_SHARED:
8543                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
8544                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
8545                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
8546                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
8547                                                  LED_CTRL_MODE_PHY_2);
8548                         break;
8549
8550                 case SHASTA_EXT_LED_MAC:
8551                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
8552                         break;
8553
8554                 case SHASTA_EXT_LED_COMBO:
8555                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
8556                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
8557                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
8558                                                  LED_CTRL_MODE_PHY_2);
8559                         break;
8560
8561                 };
8562
8563                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8564                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
8565                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
8566                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
8567
8568                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
8569                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
8570                     (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP))
8571                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
8572
8573                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
8574                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
8575                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8576                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
8577                 }
8578                 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
8579                         tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
8580
8581                 if (cfg2 & (1 << 17))
8582                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
8583
8584                 /* serdes signal pre-emphasis in register 0x590 set by */
8585                 /* bootcode if bit 18 is set */
8586                 if (cfg2 & (1 << 18))
8587                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8588         }
8589 }
8590
8591 static int __devinit tg3_phy_probe(struct tg3 *tp)
8592 {
8593         u32 hw_phy_id_1, hw_phy_id_2;
8594         u32 hw_phy_id, hw_phy_id_masked;
8595         int err;
8596
8597         /* Reading the PHY ID register can conflict with ASF
8598          * firwmare access to the PHY hardware.
8599          */
8600         err = 0;
8601         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
8602                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
8603         } else {
8604                 /* Now read the physical PHY_ID from the chip and verify
8605                  * that it is sane.  If it doesn't look good, we fall back
8606                  * to either the hard-coded table based PHY_ID and failing
8607                  * that the value found in the eeprom area.
8608                  */
8609                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
8610                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
8611
8612                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
8613                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
8614                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
8615
8616                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
8617         }
8618
8619         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
8620                 tp->phy_id = hw_phy_id;
8621                 if (hw_phy_id_masked == PHY_ID_BCM8002)
8622                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
8623         } else {
8624                 if (tp->phy_id != PHY_ID_INVALID) {
8625                         /* Do nothing, phy ID already set up in
8626                          * tg3_get_eeprom_hw_cfg().
8627                          */
8628                 } else {
8629                         struct subsys_tbl_ent *p;
8630
8631                         /* No eeprom signature?  Try the hardcoded
8632                          * subsys device table.
8633                          */
8634                         p = lookup_by_subsys(tp);
8635                         if (!p)
8636                                 return -ENODEV;
8637
8638                         tp->phy_id = p->phy_id;
8639                         if (!tp->phy_id ||
8640                             tp->phy_id == PHY_ID_BCM8002)
8641                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
8642                 }
8643         }
8644
8645         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8646             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
8647                 u32 bmsr, adv_reg, tg3_ctrl;
8648
8649                 tg3_readphy(tp, MII_BMSR, &bmsr);
8650                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
8651                     (bmsr & BMSR_LSTATUS))
8652                         goto skip_phy_reset;
8653
8654                 err = tg3_phy_reset(tp);
8655                 if (err)
8656                         return err;
8657
8658                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
8659                            ADVERTISE_100HALF | ADVERTISE_100FULL |
8660                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
8661                 tg3_ctrl = 0;
8662                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
8663                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
8664                                     MII_TG3_CTRL_ADV_1000_FULL);
8665                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
8666                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
8667                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
8668                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
8669                 }
8670
8671                 if (!tg3_copper_is_advertising_all(tp)) {
8672                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
8673
8674                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8675                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
8676
8677                         tg3_writephy(tp, MII_BMCR,
8678                                      BMCR_ANENABLE | BMCR_ANRESTART);
8679                 }
8680                 tg3_phy_set_wirespeed(tp);
8681
8682                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
8683                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8684                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
8685         }
8686
8687 skip_phy_reset:
8688         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
8689                 err = tg3_init_5401phy_dsp(tp);
8690                 if (err)
8691                         return err;
8692         }
8693
8694         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
8695                 err = tg3_init_5401phy_dsp(tp);
8696         }
8697
8698         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8699                 tp->link_config.advertising =
8700                         (ADVERTISED_1000baseT_Half |
8701                          ADVERTISED_1000baseT_Full |
8702                          ADVERTISED_Autoneg |
8703                          ADVERTISED_FIBRE);
8704         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8705                 tp->link_config.advertising &=
8706                         ~(ADVERTISED_1000baseT_Half |
8707                           ADVERTISED_1000baseT_Full);
8708
8709         return err;
8710 }
8711
8712 static void __devinit tg3_read_partno(struct tg3 *tp)
8713 {
8714         unsigned char vpd_data[256];
8715         int i;
8716
8717         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
8718                 /* Sun decided not to put the necessary bits in the
8719                  * NVRAM of their onboard tg3 parts :(
8720                  */
8721                 strcpy(tp->board_part_number, "Sun 570X");
8722                 return;
8723         }
8724
8725         for (i = 0; i < 256; i += 4) {
8726                 u32 tmp;
8727
8728                 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
8729                         goto out_not_found;
8730
8731                 vpd_data[i + 0] = ((tmp >>  0) & 0xff);
8732                 vpd_data[i + 1] = ((tmp >>  8) & 0xff);
8733                 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
8734                 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
8735         }
8736
8737         /* Now parse and find the part number. */
8738         for (i = 0; i < 256; ) {
8739                 unsigned char val = vpd_data[i];
8740                 int block_end;
8741
8742                 if (val == 0x82 || val == 0x91) {
8743                         i = (i + 3 +
8744                              (vpd_data[i + 1] +
8745                               (vpd_data[i + 2] << 8)));
8746                         continue;
8747                 }
8748
8749                 if (val != 0x90)
8750                         goto out_not_found;
8751
8752                 block_end = (i + 3 +
8753                              (vpd_data[i + 1] +
8754                               (vpd_data[i + 2] << 8)));
8755                 i += 3;
8756                 while (i < block_end) {
8757                         if (vpd_data[i + 0] == 'P' &&
8758                             vpd_data[i + 1] == 'N') {
8759                                 int partno_len = vpd_data[i + 2];
8760
8761                                 if (partno_len > 24)
8762                                         goto out_not_found;
8763
8764                                 memcpy(tp->board_part_number,
8765                                        &vpd_data[i + 3],
8766                                        partno_len);
8767
8768                                 /* Success. */
8769                                 return;
8770                         }
8771                 }
8772
8773                 /* Part number not found. */
8774                 goto out_not_found;
8775         }
8776
8777 out_not_found:
8778         strcpy(tp->board_part_number, "none");
8779 }
8780
8781 #ifdef CONFIG_SPARC64
8782 static int __devinit tg3_is_sun_570X(struct tg3 *tp)
8783 {
8784         struct pci_dev *pdev = tp->pdev;
8785         struct pcidev_cookie *pcp = pdev->sysdata;
8786
8787         if (pcp != NULL) {
8788                 int node = pcp->prom_node;
8789                 u32 venid;
8790                 int err;
8791
8792                 err = prom_getproperty(node, "subsystem-vendor-id",
8793                                        (char *) &venid, sizeof(venid));
8794                 if (err == 0 || err == -1)
8795                         return 0;
8796                 if (venid == PCI_VENDOR_ID_SUN)
8797                         return 1;
8798         }
8799         return 0;
8800 }
8801 #endif
8802
8803 static int __devinit tg3_get_invariants(struct tg3 *tp)
8804 {
8805         static struct pci_device_id write_reorder_chipsets[] = {
8806                 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
8807                              PCI_DEVICE_ID_INTEL_82801AA_8) },
8808                 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
8809                              PCI_DEVICE_ID_INTEL_82801AB_8) },
8810                 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
8811                              PCI_DEVICE_ID_INTEL_82801BA_11) },
8812                 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
8813                              PCI_DEVICE_ID_INTEL_82801BA_6) },
8814                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
8815                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
8816                 { },
8817         };
8818         u32 misc_ctrl_reg;
8819         u32 cacheline_sz_reg;
8820         u32 pci_state_reg, grc_misc_cfg;
8821         u32 val;
8822         u16 pci_cmd;
8823         int err;
8824
8825 #ifdef CONFIG_SPARC64
8826         if (tg3_is_sun_570X(tp))
8827                 tp->tg3_flags2 |= TG3_FLG2_SUN_570X;
8828 #endif
8829
8830         /* If we have an AMD 762 or Intel ICH/ICH0/ICH2 chipset, write
8831          * reordering to the mailbox registers done by the host
8832          * controller can cause major troubles.  We read back from
8833          * every mailbox register write to force the writes to be
8834          * posted to the chip in order.
8835          */
8836         if (pci_dev_present(write_reorder_chipsets))
8837                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
8838
8839         /* Force memory write invalidate off.  If we leave it on,
8840          * then on 5700_BX chips we have to enable a workaround.
8841          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
8842          * to match the cacheline size.  The Broadcom driver have this
8843          * workaround but turns MWI off all the times so never uses
8844          * it.  This seems to suggest that the workaround is insufficient.
8845          */
8846         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8847         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
8848         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8849
8850         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
8851          * has the register indirect write enable bit set before
8852          * we try to access any of the MMIO registers.  It is also
8853          * critical that the PCI-X hw workaround situation is decided
8854          * before that as well.
8855          */
8856         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8857                               &misc_ctrl_reg);
8858
8859         tp->pci_chip_rev_id = (misc_ctrl_reg >>
8860                                MISC_HOST_CTRL_CHIPREV_SHIFT);
8861
8862         /* Wrong chip ID in 5752 A0. This code can be removed later
8863          * as A0 is not in production.
8864          */
8865         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
8866                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
8867
8868         /* Initialize misc host control in PCI block. */
8869         tp->misc_host_ctrl |= (misc_ctrl_reg &
8870                                MISC_HOST_CTRL_CHIPREV);
8871         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8872                                tp->misc_host_ctrl);
8873
8874         pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
8875                               &cacheline_sz_reg);
8876
8877         tp->pci_cacheline_sz = (cacheline_sz_reg >>  0) & 0xff;
8878         tp->pci_lat_timer    = (cacheline_sz_reg >>  8) & 0xff;
8879         tp->pci_hdr_type     = (cacheline_sz_reg >> 16) & 0xff;
8880         tp->pci_bist         = (cacheline_sz_reg >> 24) & 0xff;
8881
8882         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
8883             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8884                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
8885
8886         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
8887             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
8888                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
8889
8890         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8891                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO;
8892
8893         if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
8894                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
8895
8896         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
8897             tp->pci_lat_timer < 64) {
8898                 tp->pci_lat_timer = 64;
8899
8900                 cacheline_sz_reg  = ((tp->pci_cacheline_sz & 0xff) <<  0);
8901                 cacheline_sz_reg |= ((tp->pci_lat_timer    & 0xff) <<  8);
8902                 cacheline_sz_reg |= ((tp->pci_hdr_type     & 0xff) << 16);
8903                 cacheline_sz_reg |= ((tp->pci_bist         & 0xff) << 24);
8904
8905                 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
8906                                        cacheline_sz_reg);
8907         }
8908
8909         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
8910                               &pci_state_reg);
8911
8912         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
8913                 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
8914
8915                 /* If this is a 5700 BX chipset, and we are in PCI-X
8916                  * mode, enable register write workaround.
8917                  *
8918                  * The workaround is to use indirect register accesses
8919                  * for all chip writes not to mailbox registers.
8920                  */
8921                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
8922                         u32 pm_reg;
8923                         u16 pci_cmd;
8924
8925                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
8926
8927                         /* The chip can have it's power management PCI config
8928                          * space registers clobbered due to this bug.
8929                          * So explicitly force the chip into D0 here.
8930                          */
8931                         pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
8932                                               &pm_reg);
8933                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
8934                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
8935                         pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
8936                                                pm_reg);
8937
8938                         /* Also, force SERR#/PERR# in PCI command. */
8939                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8940                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
8941                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8942                 }
8943         }
8944
8945         /* Back to back register writes can cause problems on this chip,
8946          * the workaround is to read back all reg writes except those to
8947          * mailbox regs.  See tg3_write_indirect_reg32().
8948          *
8949          * PCI Express 5750_A0 rev chips need this workaround too.
8950          */
8951         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
8952             ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
8953              tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
8954                 tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
8955
8956         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
8957                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
8958         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
8959                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
8960
8961         /* Chip-specific fixup from Broadcom driver */
8962         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
8963             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
8964                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
8965                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
8966         }
8967
8968         /* Get eeprom hw config before calling tg3_set_power_state().
8969          * In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be
8970          * determined before calling tg3_set_power_state() so that
8971          * we know whether or not to switch out of Vaux power.
8972          * When the flag is set, it means that GPIO1 is used for eeprom
8973          * write protect and also implies that it is a LOM where GPIOs
8974          * are not used to switch power.
8975          */
8976         tg3_get_eeprom_hw_cfg(tp);
8977
8978         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
8979          * GPIO1 driven high will bring 5700's external PHY out of reset.
8980          * It is also used as eeprom write protect on LOMs.
8981          */
8982         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
8983         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
8984             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
8985                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8986                                        GRC_LCLCTRL_GPIO_OUTPUT1);
8987         /* Unused GPIO3 must be driven as output on 5752 because there
8988          * are no pull-up resistors on unused GPIO pins.
8989          */
8990         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8991                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
8992
8993         /* Force the chip into D0. */
8994         err = tg3_set_power_state(tp, 0);
8995         if (err) {
8996                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
8997                        pci_name(tp->pdev));
8998                 return err;
8999         }
9000
9001         /* 5700 B0 chips do not support checksumming correctly due
9002          * to hardware bugs.
9003          */
9004         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
9005                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
9006
9007         /* Pseudo-header checksum is done by hardware logic and not
9008          * the offload processers, so make the chip do the pseudo-
9009          * header checksums on receive.  For transmit it is more
9010          * convenient to do the pseudo-header checksum in software
9011          * as Linux does that on transmit for us in all cases.
9012          */
9013         tp->tg3_flags |= TG3_FLAG_NO_TX_PSEUDO_CSUM;
9014         tp->tg3_flags &= ~TG3_FLAG_NO_RX_PSEUDO_CSUM;
9015
9016         /* Derive initial jumbo mode from MTU assigned in
9017          * ether_setup() via the alloc_etherdev() call
9018          */
9019         if (tp->dev->mtu > ETH_DATA_LEN)
9020                 tp->tg3_flags |= TG3_FLAG_JUMBO_ENABLE;
9021
9022         /* Determine WakeOnLan speed to use. */
9023         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9024             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
9025             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
9026             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
9027                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
9028         } else {
9029                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
9030         }
9031
9032         /* A few boards don't want Ethernet@WireSpeed phy feature */
9033         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
9034             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
9035              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
9036              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)))
9037                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
9038
9039         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
9040             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
9041                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
9042         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
9043                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
9044
9045         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
9046                 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
9047
9048         tp->coalesce_mode = 0;
9049         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
9050             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
9051                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
9052
9053         /* Initialize MAC MI mode, polling disabled. */
9054         tw32_f(MAC_MI_MODE, tp->mi_mode);
9055         udelay(80);
9056
9057         /* Initialize data/descriptor byte/word swapping. */
9058         val = tr32(GRC_MODE);
9059         val &= GRC_MODE_HOST_STACKUP;
9060         tw32(GRC_MODE, val | tp->grc_mode);
9061
9062         tg3_switch_clocks(tp);
9063
9064         /* Clear this out for sanity. */
9065         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
9066
9067         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
9068                               &pci_state_reg);
9069         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
9070             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
9071                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
9072
9073                 if (chiprevid == CHIPREV_ID_5701_A0 ||
9074                     chiprevid == CHIPREV_ID_5701_B0 ||
9075                     chiprevid == CHIPREV_ID_5701_B2 ||
9076                     chiprevid == CHIPREV_ID_5701_B5) {
9077                         void __iomem *sram_base;
9078
9079                         /* Write some dummy words into the SRAM status block
9080                          * area, see if it reads back correctly.  If the return
9081                          * value is bad, force enable the PCIX workaround.
9082                          */
9083                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
9084
9085                         writel(0x00000000, sram_base);
9086                         writel(0x00000000, sram_base + 4);
9087                         writel(0xffffffff, sram_base + 4);
9088                         if (readl(sram_base) != 0x00000000)
9089                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
9090                 }
9091         }
9092
9093         udelay(50);
9094         tg3_nvram_init(tp);
9095
9096         grc_misc_cfg = tr32(GRC_MISC_CFG);
9097         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
9098
9099         /* Broadcom's driver says that CIOBE multisplit has a bug */
9100 #if 0
9101         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
9102             grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
9103                 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
9104                 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
9105         }
9106 #endif
9107         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
9108             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
9109              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
9110                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
9111
9112         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9113             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
9114                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
9115         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
9116                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
9117                                       HOSTCC_MODE_CLRTICK_TXBD);
9118
9119                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
9120                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9121                                        tp->misc_host_ctrl);
9122         }
9123
9124         /* these are limited to 10/100 only */
9125         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
9126              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
9127             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
9128              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
9129              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
9130               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
9131               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
9132             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
9133              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
9134               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F)))
9135                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
9136
9137         err = tg3_phy_probe(tp);
9138         if (err) {
9139                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
9140                        pci_name(tp->pdev), err);
9141                 /* ... but do not return immediately ... */
9142         }
9143
9144         tg3_read_partno(tp);
9145
9146         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
9147                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
9148         } else {
9149                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
9150                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
9151                 else
9152                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
9153         }
9154
9155         /* 5700 {AX,BX} chips have a broken status block link
9156          * change bit implementation, so we must use the
9157          * status register in those cases.
9158          */
9159         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
9160                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
9161         else
9162                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
9163
9164         /* The led_ctrl is set during tg3_phy_probe, here we might
9165          * have to force the link status polling mechanism based
9166          * upon subsystem IDs.
9167          */
9168         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
9169             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
9170                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
9171                                   TG3_FLAG_USE_LINKCHG_REG);
9172         }
9173
9174         /* For all SERDES we poll the MAC status register. */
9175         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9176                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
9177         else
9178                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
9179
9180         /* 5700 BX chips need to have their TX producer index mailboxes
9181          * written twice to workaround a bug.
9182          */
9183         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
9184                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
9185         else
9186                 tp->tg3_flags &= ~TG3_FLAG_TXD_MBOX_HWBUG;
9187
9188         /* It seems all chips can get confused if TX buffers
9189          * straddle the 4GB address boundary in some cases.
9190          */
9191         tp->dev->hard_start_xmit = tg3_start_xmit;
9192
9193         tp->rx_offset = 2;
9194         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
9195             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
9196                 tp->rx_offset = 0;
9197
9198         /* By default, disable wake-on-lan.  User can change this
9199          * using ETHTOOL_SWOL.
9200          */
9201         tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9202
9203         return err;
9204 }
9205
9206 #ifdef CONFIG_SPARC64
9207 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
9208 {
9209         struct net_device *dev = tp->dev;
9210         struct pci_dev *pdev = tp->pdev;
9211         struct pcidev_cookie *pcp = pdev->sysdata;
9212
9213         if (pcp != NULL) {
9214                 int node = pcp->prom_node;
9215
9216                 if (prom_getproplen(node, "local-mac-address") == 6) {
9217                         prom_getproperty(node, "local-mac-address",
9218                                          dev->dev_addr, 6);
9219                         return 0;
9220                 }
9221         }
9222         return -ENODEV;
9223 }
9224
9225 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
9226 {
9227         struct net_device *dev = tp->dev;
9228
9229         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
9230         return 0;
9231 }
9232 #endif
9233
9234 static int __devinit tg3_get_device_address(struct tg3 *tp)
9235 {
9236         struct net_device *dev = tp->dev;
9237         u32 hi, lo, mac_offset;
9238
9239 #ifdef CONFIG_SPARC64
9240         if (!tg3_get_macaddr_sparc(tp))
9241                 return 0;
9242 #endif
9243
9244         mac_offset = 0x7c;
9245         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
9246             !(tp->tg3_flags & TG3_FLG2_SUN_570X)) {
9247                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
9248                         mac_offset = 0xcc;
9249                 if (tg3_nvram_lock(tp))
9250                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
9251                 else
9252                         tg3_nvram_unlock(tp);
9253         }
9254
9255         /* First try to get it from MAC address mailbox. */
9256         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
9257         if ((hi >> 16) == 0x484b) {
9258                 dev->dev_addr[0] = (hi >>  8) & 0xff;
9259                 dev->dev_addr[1] = (hi >>  0) & 0xff;
9260
9261                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
9262                 dev->dev_addr[2] = (lo >> 24) & 0xff;
9263                 dev->dev_addr[3] = (lo >> 16) & 0xff;
9264                 dev->dev_addr[4] = (lo >>  8) & 0xff;
9265                 dev->dev_addr[5] = (lo >>  0) & 0xff;
9266         }
9267         /* Next, try NVRAM. */
9268         else if (!(tp->tg3_flags & TG3_FLG2_SUN_570X) &&
9269                  !tg3_nvram_read(tp, mac_offset + 0, &hi) &&
9270                  !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
9271                 dev->dev_addr[0] = ((hi >> 16) & 0xff);
9272                 dev->dev_addr[1] = ((hi >> 24) & 0xff);
9273                 dev->dev_addr[2] = ((lo >>  0) & 0xff);
9274                 dev->dev_addr[3] = ((lo >>  8) & 0xff);
9275                 dev->dev_addr[4] = ((lo >> 16) & 0xff);
9276                 dev->dev_addr[5] = ((lo >> 24) & 0xff);
9277         }
9278         /* Finally just fetch it out of the MAC control regs. */
9279         else {
9280                 hi = tr32(MAC_ADDR_0_HIGH);
9281                 lo = tr32(MAC_ADDR_0_LOW);
9282
9283                 dev->dev_addr[5] = lo & 0xff;
9284                 dev->dev_addr[4] = (lo >> 8) & 0xff;
9285                 dev->dev_addr[3] = (lo >> 16) & 0xff;
9286                 dev->dev_addr[2] = (lo >> 24) & 0xff;
9287                 dev->dev_addr[1] = hi & 0xff;
9288                 dev->dev_addr[0] = (hi >> 8) & 0xff;
9289         }
9290
9291         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
9292 #ifdef CONFIG_SPARC64
9293                 if (!tg3_get_default_macaddr_sparc(tp))
9294                         return 0;
9295 #endif
9296                 return -EINVAL;
9297         }
9298         return 0;
9299 }
9300
9301 #define BOUNDARY_SINGLE_CACHELINE       1
9302 #define BOUNDARY_MULTI_CACHELINE        2
9303
9304 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
9305 {
9306         int cacheline_size;
9307         u8 byte;
9308         int goal;
9309
9310         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
9311         if (byte == 0)
9312                 cacheline_size = 1024;
9313         else
9314                 cacheline_size = (int) byte * 4;
9315
9316         /* On 5703 and later chips, the boundary bits have no
9317          * effect.
9318          */
9319         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9320             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
9321             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
9322                 goto out;
9323
9324 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
9325         goal = BOUNDARY_MULTI_CACHELINE;
9326 #else
9327 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
9328         goal = BOUNDARY_SINGLE_CACHELINE;
9329 #else
9330         goal = 0;
9331 #endif
9332 #endif
9333
9334         if (!goal)
9335                 goto out;
9336
9337         /* PCI controllers on most RISC systems tend to disconnect
9338          * when a device tries to burst across a cache-line boundary.
9339          * Therefore, letting tg3 do so just wastes PCI bandwidth.
9340          *
9341          * Unfortunately, for PCI-E there are only limited
9342          * write-side controls for this, and thus for reads
9343          * we will still get the disconnects.  We'll also waste
9344          * these PCI cycles for both read and write for chips
9345          * other than 5700 and 5701 which do not implement the
9346          * boundary bits.
9347          */
9348         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
9349             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
9350                 switch (cacheline_size) {
9351                 case 16:
9352                 case 32:
9353                 case 64:
9354                 case 128:
9355                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
9356                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
9357                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
9358                         } else {
9359                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
9360                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
9361                         }
9362                         break;
9363
9364                 case 256:
9365                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
9366                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
9367                         break;
9368
9369                 default:
9370                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
9371                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
9372                         break;
9373                 };
9374         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
9375                 switch (cacheline_size) {
9376                 case 16:
9377                 case 32:
9378                 case 64:
9379                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
9380                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
9381                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
9382                                 break;
9383                         }
9384                         /* fallthrough */
9385                 case 128:
9386                 default:
9387                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
9388                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
9389                         break;
9390                 };
9391         } else {
9392                 switch (cacheline_size) {
9393                 case 16:
9394                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
9395                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
9396                                         DMA_RWCTRL_WRITE_BNDRY_16);
9397                                 break;
9398                         }
9399                         /* fallthrough */
9400                 case 32:
9401                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
9402                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
9403                                         DMA_RWCTRL_WRITE_BNDRY_32);
9404                                 break;
9405                         }
9406                         /* fallthrough */
9407                 case 64:
9408                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
9409                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
9410                                         DMA_RWCTRL_WRITE_BNDRY_64);
9411                                 break;
9412                         }
9413                         /* fallthrough */
9414                 case 128:
9415                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
9416                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
9417                                         DMA_RWCTRL_WRITE_BNDRY_128);
9418                                 break;
9419                         }
9420                         /* fallthrough */
9421                 case 256:
9422                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
9423                                 DMA_RWCTRL_WRITE_BNDRY_256);
9424                         break;
9425                 case 512:
9426                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
9427                                 DMA_RWCTRL_WRITE_BNDRY_512);
9428                         break;
9429                 case 1024:
9430                 default:
9431                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
9432                                 DMA_RWCTRL_WRITE_BNDRY_1024);
9433                         break;
9434                 };
9435         }
9436
9437 out:
9438         return val;
9439 }
9440
9441 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
9442 {
9443         struct tg3_internal_buffer_desc test_desc;
9444         u32 sram_dma_descs;
9445         int i, ret;
9446
9447         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
9448
9449         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
9450         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
9451         tw32(RDMAC_STATUS, 0);
9452         tw32(WDMAC_STATUS, 0);
9453
9454         tw32(BUFMGR_MODE, 0);
9455         tw32(FTQ_RESET, 0);
9456
9457         test_desc.addr_hi = ((u64) buf_dma) >> 32;
9458         test_desc.addr_lo = buf_dma & 0xffffffff;
9459         test_desc.nic_mbuf = 0x00002100;
9460         test_desc.len = size;
9461
9462         /*
9463          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
9464          * the *second* time the tg3 driver was getting loaded after an
9465          * initial scan.
9466          *
9467          * Broadcom tells me:
9468          *   ...the DMA engine is connected to the GRC block and a DMA
9469          *   reset may affect the GRC block in some unpredictable way...
9470          *   The behavior of resets to individual blocks has not been tested.
9471          *
9472          * Broadcom noted the GRC reset will also reset all sub-components.
9473          */
9474         if (to_device) {
9475                 test_desc.cqid_sqid = (13 << 8) | 2;
9476
9477                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
9478                 udelay(40);
9479         } else {
9480                 test_desc.cqid_sqid = (16 << 8) | 7;
9481
9482                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
9483                 udelay(40);
9484         }
9485         test_desc.flags = 0x00000005;
9486
9487         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
9488                 u32 val;
9489
9490                 val = *(((u32 *)&test_desc) + i);
9491                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
9492                                        sram_dma_descs + (i * sizeof(u32)));
9493                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
9494         }
9495         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
9496
9497         if (to_device) {
9498                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
9499         } else {
9500                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
9501         }
9502
9503         ret = -ENODEV;
9504         for (i = 0; i < 40; i++) {
9505                 u32 val;
9506
9507                 if (to_device)
9508                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
9509                 else
9510                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
9511                 if ((val & 0xffff) == sram_dma_descs) {
9512                         ret = 0;
9513                         break;
9514                 }
9515
9516                 udelay(100);
9517         }
9518
9519         return ret;
9520 }
9521
9522 #define TEST_BUFFER_SIZE        0x2000
9523
9524 static int __devinit tg3_test_dma(struct tg3 *tp)
9525 {
9526         dma_addr_t buf_dma;
9527         u32 *buf, saved_dma_rwctrl;
9528         int ret;
9529
9530         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
9531         if (!buf) {
9532                 ret = -ENOMEM;
9533                 goto out_nofree;
9534         }
9535
9536         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
9537                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
9538
9539         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
9540
9541         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
9542                 /* DMA read watermark not used on PCIE */
9543                 tp->dma_rwctrl |= 0x00180000;
9544         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
9545                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
9546                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
9547                         tp->dma_rwctrl |= 0x003f0000;
9548                 else
9549                         tp->dma_rwctrl |= 0x003f000f;
9550         } else {
9551                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
9552                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9553                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
9554
9555                         if (ccval == 0x6 || ccval == 0x7)
9556                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
9557
9558                         /* Set bit 23 to enable PCIX hw bug fix */
9559                         tp->dma_rwctrl |= 0x009f0000;
9560                 } else {
9561                         tp->dma_rwctrl |= 0x001b000f;
9562                 }
9563         }
9564
9565         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
9566             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
9567                 tp->dma_rwctrl &= 0xfffffff0;
9568
9569         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9570             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
9571                 /* Remove this if it causes problems for some boards. */
9572                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
9573
9574                 /* On 5700/5701 chips, we need to set this bit.
9575                  * Otherwise the chip will issue cacheline transactions
9576                  * to streamable DMA memory with not all the byte
9577                  * enables turned on.  This is an error on several
9578                  * RISC PCI controllers, in particular sparc64.
9579                  *
9580                  * On 5703/5704 chips, this bit has been reassigned
9581                  * a different meaning.  In particular, it is used
9582                  * on those chips to enable a PCI-X workaround.
9583                  */
9584                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
9585         }
9586
9587         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9588
9589 #if 0
9590         /* Unneeded, already done by tg3_get_invariants.  */
9591         tg3_switch_clocks(tp);
9592 #endif
9593
9594         ret = 0;
9595         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9596             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
9597                 goto out;
9598
9599         /* It is best to perform DMA test with maximum write burst size
9600          * to expose the 5700/5701 write DMA bug.
9601          */
9602         saved_dma_rwctrl = tp->dma_rwctrl;
9603         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
9604         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9605
9606         while (1) {
9607                 u32 *p = buf, i;
9608
9609                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
9610                         p[i] = i;
9611
9612                 /* Send the buffer to the chip. */
9613                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
9614                 if (ret) {
9615                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
9616                         break;
9617                 }
9618
9619 #if 0
9620                 /* validate data reached card RAM correctly. */
9621                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
9622                         u32 val;
9623                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
9624                         if (le32_to_cpu(val) != p[i]) {
9625                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
9626                                 /* ret = -ENODEV here? */
9627                         }
9628                         p[i] = 0;
9629                 }
9630 #endif
9631                 /* Now read it back. */
9632                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
9633                 if (ret) {
9634                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
9635
9636                         break;
9637                 }
9638
9639                 /* Verify it. */
9640                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
9641                         if (p[i] == i)
9642                                 continue;
9643
9644                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
9645                             DMA_RWCTRL_WRITE_BNDRY_16) {
9646                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
9647                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
9648                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9649                                 break;
9650                         } else {
9651                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
9652                                 ret = -ENODEV;
9653                                 goto out;
9654                         }
9655                 }
9656
9657                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
9658                         /* Success. */
9659                         ret = 0;
9660                         break;
9661                 }
9662         }
9663         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
9664             DMA_RWCTRL_WRITE_BNDRY_16) {
9665                 static struct pci_device_id dma_wait_state_chipsets[] = {
9666                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
9667                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
9668                         { },
9669                 };
9670
9671                 /* DMA test passed without adjusting DMA boundary,
9672                  * now look for chipsets that are known to expose the
9673                  * DMA bug without failing the test.
9674                  */
9675                 if (pci_dev_present(dma_wait_state_chipsets)) {
9676                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
9677                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
9678                 }
9679                 else
9680                         /* Safe to use the calculated DMA boundary. */
9681                         tp->dma_rwctrl = saved_dma_rwctrl;
9682
9683                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9684         }
9685
9686 out:
9687         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
9688 out_nofree:
9689         return ret;
9690 }
9691
9692 static void __devinit tg3_init_link_config(struct tg3 *tp)
9693 {
9694         tp->link_config.advertising =
9695                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
9696                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
9697                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
9698                  ADVERTISED_Autoneg | ADVERTISED_MII);
9699         tp->link_config.speed = SPEED_INVALID;
9700         tp->link_config.duplex = DUPLEX_INVALID;
9701         tp->link_config.autoneg = AUTONEG_ENABLE;
9702         netif_carrier_off(tp->dev);
9703         tp->link_config.active_speed = SPEED_INVALID;
9704         tp->link_config.active_duplex = DUPLEX_INVALID;
9705         tp->link_config.phy_is_low_power = 0;
9706         tp->link_config.orig_speed = SPEED_INVALID;
9707         tp->link_config.orig_duplex = DUPLEX_INVALID;
9708         tp->link_config.orig_autoneg = AUTONEG_INVALID;
9709 }
9710
9711 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
9712 {
9713         tp->bufmgr_config.mbuf_read_dma_low_water =
9714                 DEFAULT_MB_RDMA_LOW_WATER;
9715         tp->bufmgr_config.mbuf_mac_rx_low_water =
9716                 DEFAULT_MB_MACRX_LOW_WATER;
9717         tp->bufmgr_config.mbuf_high_water =
9718                 DEFAULT_MB_HIGH_WATER;
9719
9720         tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
9721                 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
9722         tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
9723                 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
9724         tp->bufmgr_config.mbuf_high_water_jumbo =
9725                 DEFAULT_MB_HIGH_WATER_JUMBO;
9726
9727         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
9728         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
9729 }
9730
9731 static char * __devinit tg3_phy_string(struct tg3 *tp)
9732 {
9733         switch (tp->phy_id & PHY_ID_MASK) {
9734         case PHY_ID_BCM5400:    return "5400";
9735         case PHY_ID_BCM5401:    return "5401";
9736         case PHY_ID_BCM5411:    return "5411";
9737         case PHY_ID_BCM5701:    return "5701";
9738         case PHY_ID_BCM5703:    return "5703";
9739         case PHY_ID_BCM5704:    return "5704";
9740         case PHY_ID_BCM5705:    return "5705";
9741         case PHY_ID_BCM5750:    return "5750";
9742         case PHY_ID_BCM5752:    return "5752";
9743         case PHY_ID_BCM8002:    return "8002/serdes";
9744         case 0:                 return "serdes";
9745         default:                return "unknown";
9746         };
9747 }
9748
9749 static struct pci_dev * __devinit tg3_find_5704_peer(struct tg3 *tp)
9750 {
9751         struct pci_dev *peer;
9752         unsigned int func, devnr = tp->pdev->devfn & ~7;
9753
9754         for (func = 0; func < 8; func++) {
9755                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
9756                 if (peer && peer != tp->pdev)
9757                         break;
9758                 pci_dev_put(peer);
9759         }
9760         if (!peer || peer == tp->pdev)
9761                 BUG();
9762
9763         /*
9764          * We don't need to keep the refcount elevated; there's no way
9765          * to remove one half of this device without removing the other
9766          */
9767         pci_dev_put(peer);
9768
9769         return peer;
9770 }
9771
9772 static void __devinit tg3_init_coal(struct tg3 *tp)
9773 {
9774         struct ethtool_coalesce *ec = &tp->coal;
9775
9776         memset(ec, 0, sizeof(*ec));
9777         ec->cmd = ETHTOOL_GCOALESCE;
9778         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
9779         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
9780         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
9781         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
9782         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
9783         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
9784         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
9785         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
9786         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
9787
9788         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
9789                                  HOSTCC_MODE_CLRTICK_TXBD)) {
9790                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
9791                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
9792                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
9793                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
9794         }
9795 }
9796
9797 static int __devinit tg3_init_one(struct pci_dev *pdev,
9798                                   const struct pci_device_id *ent)
9799 {
9800         static int tg3_version_printed = 0;
9801         unsigned long tg3reg_base, tg3reg_len;
9802         struct net_device *dev;
9803         struct tg3 *tp;
9804         int i, err, pci_using_dac, pm_cap;
9805
9806         if (tg3_version_printed++ == 0)
9807                 printk(KERN_INFO "%s", version);
9808
9809         err = pci_enable_device(pdev);
9810         if (err) {
9811                 printk(KERN_ERR PFX "Cannot enable PCI device, "
9812                        "aborting.\n");
9813                 return err;
9814         }
9815
9816         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9817                 printk(KERN_ERR PFX "Cannot find proper PCI device "
9818                        "base address, aborting.\n");
9819                 err = -ENODEV;
9820                 goto err_out_disable_pdev;
9821         }
9822
9823         err = pci_request_regions(pdev, DRV_MODULE_NAME);
9824         if (err) {
9825                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
9826                        "aborting.\n");
9827                 goto err_out_disable_pdev;
9828         }
9829
9830         pci_set_master(pdev);
9831
9832         /* Find power-management capability. */
9833         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
9834         if (pm_cap == 0) {
9835                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
9836                        "aborting.\n");
9837                 err = -EIO;
9838                 goto err_out_free_res;
9839         }
9840
9841         /* Configure DMA attributes. */
9842         err = pci_set_dma_mask(pdev, 0xffffffffffffffffULL);
9843         if (!err) {
9844                 pci_using_dac = 1;
9845                 err = pci_set_consistent_dma_mask(pdev, 0xffffffffffffffffULL);
9846                 if (err < 0) {
9847                         printk(KERN_ERR PFX "Unable to obtain 64 bit DMA "
9848                                "for consistent allocations\n");
9849                         goto err_out_free_res;
9850                 }
9851         } else {
9852                 err = pci_set_dma_mask(pdev, 0xffffffffULL);
9853                 if (err) {
9854                         printk(KERN_ERR PFX "No usable DMA configuration, "
9855                                "aborting.\n");
9856                         goto err_out_free_res;
9857                 }
9858                 pci_using_dac = 0;
9859         }
9860
9861         tg3reg_base = pci_resource_start(pdev, 0);
9862         tg3reg_len = pci_resource_len(pdev, 0);
9863
9864         dev = alloc_etherdev(sizeof(*tp));
9865         if (!dev) {
9866                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
9867                 err = -ENOMEM;
9868                 goto err_out_free_res;
9869         }
9870
9871         SET_MODULE_OWNER(dev);
9872         SET_NETDEV_DEV(dev, &pdev->dev);
9873
9874         if (pci_using_dac)
9875                 dev->features |= NETIF_F_HIGHDMA;
9876         dev->features |= NETIF_F_LLTX;
9877 #if TG3_VLAN_TAG_USED
9878         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
9879         dev->vlan_rx_register = tg3_vlan_rx_register;
9880         dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
9881 #endif
9882
9883         tp = netdev_priv(dev);
9884         tp->pdev = pdev;
9885         tp->dev = dev;
9886         tp->pm_cap = pm_cap;
9887         tp->mac_mode = TG3_DEF_MAC_MODE;
9888         tp->rx_mode = TG3_DEF_RX_MODE;
9889         tp->tx_mode = TG3_DEF_TX_MODE;
9890         tp->mi_mode = MAC_MI_MODE_BASE;
9891         if (tg3_debug > 0)
9892                 tp->msg_enable = tg3_debug;
9893         else
9894                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
9895
9896         /* The word/byte swap controls here control register access byte
9897          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
9898          * setting below.
9899          */
9900         tp->misc_host_ctrl =
9901                 MISC_HOST_CTRL_MASK_PCI_INT |
9902                 MISC_HOST_CTRL_WORD_SWAP |
9903                 MISC_HOST_CTRL_INDIR_ACCESS |
9904                 MISC_HOST_CTRL_PCISTATE_RW;
9905
9906         /* The NONFRM (non-frame) byte/word swap controls take effect
9907          * on descriptor entries, anything which isn't packet data.
9908          *
9909          * The StrongARM chips on the board (one for tx, one for rx)
9910          * are running in big-endian mode.
9911          */
9912         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
9913                         GRC_MODE_WSWAP_NONFRM_DATA);
9914 #ifdef __BIG_ENDIAN
9915         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
9916 #endif
9917         spin_lock_init(&tp->lock);
9918         spin_lock_init(&tp->tx_lock);
9919         spin_lock_init(&tp->indirect_lock);
9920         INIT_WORK(&tp->reset_task, tg3_reset_task, tp);
9921
9922         tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
9923         if (tp->regs == 0UL) {
9924                 printk(KERN_ERR PFX "Cannot map device registers, "
9925                        "aborting.\n");
9926                 err = -ENOMEM;
9927                 goto err_out_free_dev;
9928         }
9929
9930         tg3_init_link_config(tp);
9931
9932         tg3_init_bufmgr_config(tp);
9933
9934         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
9935         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
9936         tp->tx_pending = TG3_DEF_TX_RING_PENDING;
9937
9938         dev->open = tg3_open;
9939         dev->stop = tg3_close;
9940         dev->get_stats = tg3_get_stats;
9941         dev->set_multicast_list = tg3_set_rx_mode;
9942         dev->set_mac_address = tg3_set_mac_addr;
9943         dev->do_ioctl = tg3_ioctl;
9944         dev->tx_timeout = tg3_tx_timeout;
9945         dev->poll = tg3_poll;
9946         dev->ethtool_ops = &tg3_ethtool_ops;
9947         dev->weight = 64;
9948         dev->watchdog_timeo = TG3_TX_TIMEOUT;
9949         dev->change_mtu = tg3_change_mtu;
9950         dev->irq = pdev->irq;
9951 #ifdef CONFIG_NET_POLL_CONTROLLER
9952         dev->poll_controller = tg3_poll_controller;
9953 #endif
9954
9955         err = tg3_get_invariants(tp);
9956         if (err) {
9957                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
9958                        "aborting.\n");
9959                 goto err_out_iounmap;
9960         }
9961
9962         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9963                 tp->bufmgr_config.mbuf_read_dma_low_water =
9964                         DEFAULT_MB_RDMA_LOW_WATER_5705;
9965                 tp->bufmgr_config.mbuf_mac_rx_low_water =
9966                         DEFAULT_MB_MACRX_LOW_WATER_5705;
9967                 tp->bufmgr_config.mbuf_high_water =
9968                         DEFAULT_MB_HIGH_WATER_5705;
9969         }
9970
9971 #if TG3_TSO_SUPPORT != 0
9972         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
9973                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
9974         }
9975         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9976             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
9977             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
9978             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
9979                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
9980         } else {
9981                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
9982         }
9983
9984         /* TSO is off by default, user can enable using ethtool.  */
9985 #if 0
9986         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)
9987                 dev->features |= NETIF_F_TSO;
9988 #endif
9989
9990 #endif
9991
9992         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
9993             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
9994             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
9995                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
9996                 tp->rx_pending = 63;
9997         }
9998
9999         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
10000                 tp->pdev_peer = tg3_find_5704_peer(tp);
10001
10002         err = tg3_get_device_address(tp);
10003         if (err) {
10004                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
10005                        "aborting.\n");
10006                 goto err_out_iounmap;
10007         }
10008
10009         /*
10010          * Reset chip in case UNDI or EFI driver did not shutdown
10011          * DMA self test will enable WDMAC and we'll see (spurious)
10012          * pending DMA on the PCI bus at that point.
10013          */
10014         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
10015             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
10016                 pci_save_state(tp->pdev);
10017                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
10018                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10019         }
10020
10021         err = tg3_test_dma(tp);
10022         if (err) {
10023                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
10024                 goto err_out_iounmap;
10025         }
10026
10027         /* Tigon3 can do ipv4 only... and some chips have buggy
10028          * checksumming.
10029          */
10030         if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
10031                 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
10032                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10033         } else
10034                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10035
10036         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
10037                 dev->features &= ~NETIF_F_HIGHDMA;
10038
10039         /* flow control autonegotiation is default behavior */
10040         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10041
10042         tg3_init_coal(tp);
10043
10044         err = register_netdev(dev);
10045         if (err) {
10046                 printk(KERN_ERR PFX "Cannot register net device, "
10047                        "aborting.\n");
10048                 goto err_out_iounmap;
10049         }
10050
10051         pci_set_drvdata(pdev, dev);
10052
10053         /* Now that we have fully setup the chip, save away a snapshot
10054          * of the PCI config space.  We need to restore this after
10055          * GRC_MISC_CFG core clock resets and some resume events.
10056          */
10057         pci_save_state(tp->pdev);
10058
10059         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (PCI%s:%s:%s) %sBaseT Ethernet ",
10060                dev->name,
10061                tp->board_part_number,
10062                tp->pci_chip_rev_id,
10063                tg3_phy_string(tp),
10064                ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "X" : ""),
10065                ((tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED) ?
10066                 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "133MHz" : "66MHz") :
10067                 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "100MHz" : "33MHz")),
10068                ((tp->tg3_flags & TG3_FLAG_PCI_32BIT) ? "32-bit" : "64-bit"),
10069                (tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100" : "10/100/1000");
10070
10071         for (i = 0; i < 6; i++)
10072                 printk("%2.2x%c", dev->dev_addr[i],
10073                        i == 5 ? '\n' : ':');
10074
10075         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
10076                "MIirq[%d] ASF[%d] Split[%d] WireSpeed[%d] "
10077                "TSOcap[%d] \n",
10078                dev->name,
10079                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
10080                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
10081                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
10082                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
10083                (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
10084                (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
10085                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
10086         printk(KERN_INFO "%s: dma_rwctrl[%08x]\n",
10087                dev->name, tp->dma_rwctrl);
10088
10089         return 0;
10090
10091 err_out_iounmap:
10092         iounmap(tp->regs);
10093
10094 err_out_free_dev:
10095         free_netdev(dev);
10096
10097 err_out_free_res:
10098         pci_release_regions(pdev);
10099
10100 err_out_disable_pdev:
10101         pci_disable_device(pdev);
10102         pci_set_drvdata(pdev, NULL);
10103         return err;
10104 }
10105
10106 static void __devexit tg3_remove_one(struct pci_dev *pdev)
10107 {
10108         struct net_device *dev = pci_get_drvdata(pdev);
10109
10110         if (dev) {
10111                 struct tg3 *tp = netdev_priv(dev);
10112
10113                 unregister_netdev(dev);
10114                 iounmap(tp->regs);
10115                 free_netdev(dev);
10116                 pci_release_regions(pdev);
10117                 pci_disable_device(pdev);
10118                 pci_set_drvdata(pdev, NULL);
10119         }
10120 }
10121
10122 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
10123 {
10124         struct net_device *dev = pci_get_drvdata(pdev);
10125         struct tg3 *tp = netdev_priv(dev);
10126         int err;
10127
10128         if (!netif_running(dev))
10129                 return 0;
10130
10131         tg3_netif_stop(tp);
10132
10133         del_timer_sync(&tp->timer);
10134
10135         tg3_full_lock(tp, 1);
10136         tg3_disable_ints(tp);
10137         tg3_full_unlock(tp);
10138
10139         netif_device_detach(dev);
10140
10141         tg3_full_lock(tp, 0);
10142         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10143         tg3_full_unlock(tp);
10144
10145         err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
10146         if (err) {
10147                 tg3_full_lock(tp, 0);
10148
10149                 tg3_init_hw(tp);
10150
10151                 tp->timer.expires = jiffies + tp->timer_offset;
10152                 add_timer(&tp->timer);
10153
10154                 netif_device_attach(dev);
10155                 tg3_netif_start(tp);
10156
10157                 tg3_full_unlock(tp);
10158         }
10159
10160         return err;
10161 }
10162
10163 static int tg3_resume(struct pci_dev *pdev)
10164 {
10165         struct net_device *dev = pci_get_drvdata(pdev);
10166         struct tg3 *tp = netdev_priv(dev);
10167         int err;
10168
10169         if (!netif_running(dev))
10170                 return 0;
10171
10172         pci_restore_state(tp->pdev);
10173
10174         err = tg3_set_power_state(tp, 0);
10175         if (err)
10176                 return err;
10177
10178         netif_device_attach(dev);
10179
10180         tg3_full_lock(tp, 0);
10181
10182         tg3_init_hw(tp);
10183
10184         tp->timer.expires = jiffies + tp->timer_offset;
10185         add_timer(&tp->timer);
10186
10187         tg3_enable_ints(tp);
10188
10189         tg3_netif_start(tp);
10190
10191         tg3_full_unlock(tp);
10192
10193         return 0;
10194 }
10195
10196 static struct pci_driver tg3_driver = {
10197         .name           = DRV_MODULE_NAME,
10198         .id_table       = tg3_pci_tbl,
10199         .probe          = tg3_init_one,
10200         .remove         = __devexit_p(tg3_remove_one),
10201         .suspend        = tg3_suspend,
10202         .resume         = tg3_resume
10203 };
10204
10205 static int __init tg3_init(void)
10206 {
10207         return pci_module_init(&tg3_driver);
10208 }
10209
10210 static void __exit tg3_cleanup(void)
10211 {
10212         pci_unregister_driver(&tg3_driver);
10213 }
10214
10215 module_init(tg3_init);
10216 module_exit(tg3_cleanup);