Pileus Git - ~andy/linux/blob - drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2009 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 #include <linux/brcmphy.h>
  37 #include <linux/if_vlan.h>
  38 #include <linux/ip.h>
  39 #include <linux/tcp.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/prefetch.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/firmware.h>
  44
  45 #include <net/checksum.h>
  46 #include <net/ip.h>
  47
  48 #include <asm/system.h>
  49 #include <asm/io.h>
  50 #include <asm/byteorder.h>
  51 #include <asm/uaccess.h>
  52
  53 #ifdef CONFIG_SPARC
  54 #include <asm/idprom.h>
  55 #include <asm/prom.h>
  56 #endif
  57
  58 #define BAR_0   0
  59 #define BAR_2   2
  60
  61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  62 #define TG3_VLAN_TAG_USED 1
  63 #else
  64 #define TG3_VLAN_TAG_USED 0
  65 #endif
  66
  67 #include "tg3.h"
  68
  69 #define DRV_MODULE_NAME         "tg3"
  70 #define PFX DRV_MODULE_NAME     ": "
  71 #define DRV_MODULE_VERSION      "3.99"
  72 #define DRV_MODULE_RELDATE      "April 20, 2009"
  73
  74 #define TG3_DEF_MAC_MODE        0
  75 #define TG3_DEF_RX_MODE         0
  76 #define TG3_DEF_TX_MODE         0
  77 #define TG3_DEF_MSG_ENABLE        \
  78         (NETIF_MSG_DRV          | \
  79          NETIF_MSG_PROBE        | \
  80          NETIF_MSG_LINK         | \
  81          NETIF_MSG_TIMER        | \
  82          NETIF_MSG_IFDOWN       | \
  83          NETIF_MSG_IFUP         | \
  84          NETIF_MSG_RX_ERR       | \
  85          NETIF_MSG_TX_ERR)
  86
  87 /* length of time before we decide the hardware is borked,
  88  * and dev->tx_timeout() should be called to fix the problem
  89  */
  90 #define TG3_TX_TIMEOUT                  (5 * HZ)
  91
  92 /* hardware minimum and maximum for a single frame's data payload */
  93 #define TG3_MIN_MTU                     60
  94 #define TG3_MAX_MTU(tp) \
  95         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
  96
  97 /* These numbers seem to be hard coded in the NIC firmware somehow.
  98  * You can't change the ring sizes, but you can change where you place
  99  * them in the NIC onboard memory.
 100  */
 101 #define TG3_RX_RING_SIZE                512
 102 #define TG3_DEF_RX_RING_PENDING         200
 103 #define TG3_RX_JUMBO_RING_SIZE          256
 104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 105
 106 /* Do not place this n-ring entries value into the tp struct itself,
 107  * we really want to expose these constants to GCC so that modulo et
 108  * al.  operations are done with shifts and masks instead of with
 109  * hw multiply/modulo instructions.  Another solution would be to
 110  * replace things like '% foo' with '& (foo - 1)'.
 111  */
 112 #define TG3_RX_RCB_RING_SIZE(tp)        \
 113         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
 114
 115 #define TG3_TX_RING_SIZE                512
 116 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 117
 118 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 119                                  TG3_RX_RING_SIZE)
 120 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
 121                                  TG3_RX_JUMBO_RING_SIZE)
 122 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 123                                    TG3_RX_RCB_RING_SIZE(tp))
 124 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 125                                  TG3_TX_RING_SIZE)
 126 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 127
 128 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
 129 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
 130
 131 /* minimum number of free TX descriptors required to wake up TX process */
 132 #define TG3_TX_WAKEUP_THRESH(tp)                ((tp)->tx_pending / 4)
 133
 134 #define TG3_RAW_IP_ALIGN 2
 135
 136 /* number of ETHTOOL_GSTATS u64's */
 137 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 138
 139 #define TG3_NUM_TEST            6
 140
 141 #define FIRMWARE_TG3            "tigon/tg3.bin"
 142 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 143 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 144
 145 static char version[] __devinitdata =
 146         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 147
 148 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 149 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 150 MODULE_LICENSE("GPL");
 151 MODULE_VERSION(DRV_MODULE_VERSION);
 152 MODULE_FIRMWARE(FIRMWARE_TG3);
 153 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 154 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 155
 156
 157 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 158 module_param(tg3_debug, int, 0);
 159 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 160
 161 static struct pci_device_id tg3_pci_tbl[] = {
 162         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 163         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 164         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 165         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 166         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 167         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 168         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 169         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 170         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 171         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5785)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 234         {}
 235 };
 236
 237 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 238
 239 static const struct {
 240         const char string[ETH_GSTRING_LEN];
 241 } ethtool_stats_keys[TG3_NUM_STATS] = {
 242         { "rx_octets" },
 243         { "rx_fragments" },
 244         { "rx_ucast_packets" },
 245         { "rx_mcast_packets" },
 246         { "rx_bcast_packets" },
 247         { "rx_fcs_errors" },
 248         { "rx_align_errors" },
 249         { "rx_xon_pause_rcvd" },
 250         { "rx_xoff_pause_rcvd" },
 251         { "rx_mac_ctrl_rcvd" },
 252         { "rx_xoff_entered" },
 253         { "rx_frame_too_long_errors" },
 254         { "rx_jabbers" },
 255         { "rx_undersize_packets" },
 256         { "rx_in_length_errors" },
 257         { "rx_out_length_errors" },
 258         { "rx_64_or_less_octet_packets" },
 259         { "rx_65_to_127_octet_packets" },
 260         { "rx_128_to_255_octet_packets" },
 261         { "rx_256_to_511_octet_packets" },
 262         { "rx_512_to_1023_octet_packets" },
 263         { "rx_1024_to_1522_octet_packets" },
 264         { "rx_1523_to_2047_octet_packets" },
 265         { "rx_2048_to_4095_octet_packets" },
 266         { "rx_4096_to_8191_octet_packets" },
 267         { "rx_8192_to_9022_octet_packets" },
 268
 269         { "tx_octets" },
 270         { "tx_collisions" },
 271
 272         { "tx_xon_sent" },
 273         { "tx_xoff_sent" },
 274         { "tx_flow_control" },
 275         { "tx_mac_errors" },
 276         { "tx_single_collisions" },
 277         { "tx_mult_collisions" },
 278         { "tx_deferred" },
 279         { "tx_excessive_collisions" },
 280         { "tx_late_collisions" },
 281         { "tx_collide_2times" },
 282         { "tx_collide_3times" },
 283         { "tx_collide_4times" },
 284         { "tx_collide_5times" },
 285         { "tx_collide_6times" },
 286         { "tx_collide_7times" },
 287         { "tx_collide_8times" },
 288         { "tx_collide_9times" },
 289         { "tx_collide_10times" },
 290         { "tx_collide_11times" },
 291         { "tx_collide_12times" },
 292         { "tx_collide_13times" },
 293         { "tx_collide_14times" },
 294         { "tx_collide_15times" },
 295         { "tx_ucast_packets" },
 296         { "tx_mcast_packets" },
 297         { "tx_bcast_packets" },
 298         { "tx_carrier_sense_errors" },
 299         { "tx_discards" },
 300         { "tx_errors" },
 301
 302         { "dma_writeq_full" },
 303         { "dma_write_prioq_full" },
 304         { "rxbds_empty" },
 305         { "rx_discards" },
 306         { "rx_errors" },
 307         { "rx_threshold_hit" },
 308
 309         { "dma_readq_full" },
 310         { "dma_read_prioq_full" },
 311         { "tx_comp_queue_full" },
 312
 313         { "ring_set_send_prod_index" },
 314         { "ring_status_update" },
 315         { "nic_irqs" },
 316         { "nic_avoided_irqs" },
 317         { "nic_tx_threshold_hit" }
 318 };
 319
 320 static const struct {
 321         const char string[ETH_GSTRING_LEN];
 322 } ethtool_test_keys[TG3_NUM_TEST] = {
 323         { "nvram test     (online) " },
 324         { "link test      (online) " },
 325         { "register test  (offline)" },
 326         { "memory test    (offline)" },
 327         { "loopback test  (offline)" },
 328         { "interrupt test (offline)" },
 329 };
 330
 331 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 332 {
 333         writel(val, tp->regs + off);
 334 }
 335
 336 static u32 tg3_read32(struct tg3 *tp, u32 off)
 337 {
 338         return (readl(tp->regs + off));
 339 }
 340
 341 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 342 {
 343         writel(val, tp->aperegs + off);
 344 }
 345
 346 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 347 {
 348         return (readl(tp->aperegs + off));
 349 }
 350
 351 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 352 {
 353         unsigned long flags;
 354
 355         spin_lock_irqsave(&tp->indirect_lock, flags);
 356         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 357         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 358         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 359 }
 360
 361 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 362 {
 363         writel(val, tp->regs + off);
 364         readl(tp->regs + off);
 365 }
 366
 367 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 368 {
 369         unsigned long flags;
 370         u32 val;
 371
 372         spin_lock_irqsave(&tp->indirect_lock, flags);
 373         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 374         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 375         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 376         return val;
 377 }
 378
 379 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 380 {
 381         unsigned long flags;
 382
 383         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 384                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 385                                        TG3_64BIT_REG_LOW, val);
 386                 return;
 387         }
 388         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 389                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 390                                        TG3_64BIT_REG_LOW, val);
 391                 return;
 392         }
 393
 394         spin_lock_irqsave(&tp->indirect_lock, flags);
 395         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 396         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 397         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 398
 399         /* In indirect mode when disabling interrupts, we also need
 400          * to clear the interrupt bit in the GRC local ctrl register.
 401          */
 402         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 403             (val == 0x1)) {
 404                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 405                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 406         }
 407 }
 408
 409 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 410 {
 411         unsigned long flags;
 412         u32 val;
 413
 414         spin_lock_irqsave(&tp->indirect_lock, flags);
 415         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 416         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 417         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 418         return val;
 419 }
 420
 421 /* usec_wait specifies the wait time in usec when writing to certain registers
 422  * where it is unsafe to read back the register without some delay.
 423  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 424  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 425  */
 426 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 427 {
 428         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 429             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 430                 /* Non-posted methods */
 431                 tp->write32(tp, off, val);
 432         else {
 433                 /* Posted method */
 434                 tg3_write32(tp, off, val);
 435                 if (usec_wait)
 436                         udelay(usec_wait);
 437                 tp->read32(tp, off);
 438         }
 439         /* Wait again after the read for the posted method to guarantee that
 440          * the wait time is met.
 441          */
 442         if (usec_wait)
 443                 udelay(usec_wait);
 444 }
 445
 446 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 447 {
 448         tp->write32_mbox(tp, off, val);
 449         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 450             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 451                 tp->read32_mbox(tp, off);
 452 }
 453
 454 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 455 {
 456         void __iomem *mbox = tp->regs + off;
 457         writel(val, mbox);
 458         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 459                 writel(val, mbox);
 460         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 461                 readl(mbox);
 462 }
 463
 464 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 465 {
 466         return (readl(tp->regs + off + GRCMBOX_BASE));
 467 }
 468
 469 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 470 {
 471         writel(val, tp->regs + off + GRCMBOX_BASE);
 472 }
 473
 474 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 475 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 476 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 477 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 478 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 479
 480 #define tw32(reg,val)           tp->write32(tp, reg, val)
 481 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 482 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 483 #define tr32(reg)               tp->read32(tp, reg)
 484
 485 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 486 {
 487         unsigned long flags;
 488
 489         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 490             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 491                 return;
 492
 493         spin_lock_irqsave(&tp->indirect_lock, flags);
 494         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 495                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 496                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 497
 498                 /* Always leave this as zero. */
 499                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 500         } else {
 501                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 502                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 503
 504                 /* Always leave this as zero. */
 505                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 506         }
 507         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 508 }
 509
 510 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 511 {
 512         unsigned long flags;
 513
 514         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 515             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 516                 *val = 0;
 517                 return;
 518         }
 519
 520         spin_lock_irqsave(&tp->indirect_lock, flags);
 521         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 522                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 523                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 524
 525                 /* Always leave this as zero. */
 526                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 527         } else {
 528                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 529                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 530
 531                 /* Always leave this as zero. */
 532                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 533         }
 534         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 535 }
 536
 537 static void tg3_ape_lock_init(struct tg3 *tp)
 538 {
 539         int i;
 540
 541         /* Make sure the driver hasn't any stale locks. */
 542         for (i = 0; i < 8; i++)
 543                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
 544                                 APE_LOCK_GRANT_DRIVER);
 545 }
 546
 547 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 548 {
 549         int i, off;
 550         int ret = 0;
 551         u32 status;
 552
 553         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 554                 return 0;
 555
 556         switch (locknum) {
 557                 case TG3_APE_LOCK_GRC:
 558                 case TG3_APE_LOCK_MEM:
 559                         break;
 560                 default:
 561                         return -EINVAL;
 562         }
 563
 564         off = 4 * locknum;
 565
 566         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
 567
 568         /* Wait for up to 1 millisecond to acquire lock. */
 569         for (i = 0; i < 100; i++) {
 570                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
 571                 if (status == APE_LOCK_GRANT_DRIVER)
 572                         break;
 573                 udelay(10);
 574         }
 575
 576         if (status != APE_LOCK_GRANT_DRIVER) {
 577                 /* Revoke the lock request. */
 578                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
 579                                 APE_LOCK_GRANT_DRIVER);
 580
 581                 ret = -EBUSY;
 582         }
 583
 584         return ret;
 585 }
 586
 587 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 588 {
 589         int off;
 590
 591         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 592                 return;
 593
 594         switch (locknum) {
 595                 case TG3_APE_LOCK_GRC:
 596                 case TG3_APE_LOCK_MEM:
 597                         break;
 598                 default:
 599                         return;
 600         }
 601
 602         off = 4 * locknum;
 603         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
 604 }
 605
 606 static void tg3_disable_ints(struct tg3 *tp)
 607 {
 608         tw32(TG3PCI_MISC_HOST_CTRL,
 609              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 610         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
 611 }
 612
 613 static inline void tg3_cond_int(struct tg3 *tp)
 614 {
 615         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 616             (tp->hw_status->status & SD_STATUS_UPDATED))
 617                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 618         else
 619                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 620                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 621 }
 622
 623 static void tg3_enable_ints(struct tg3 *tp)
 624 {
 625         tp->irq_sync = 0;
 626         wmb();
 627
 628         tw32(TG3PCI_MISC_HOST_CTRL,
 629              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 630         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 631                        (tp->last_tag << 24));
 632         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 633                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 634                                (tp->last_tag << 24));
 635         tg3_cond_int(tp);
 636 }
 637
 638 static inline unsigned int tg3_has_work(struct tg3 *tp)
 639 {
 640         struct tg3_hw_status *sblk = tp->hw_status;
 641         unsigned int work_exists = 0;
 642
 643         /* check for phy events */
 644         if (!(tp->tg3_flags &
 645               (TG3_FLAG_USE_LINKCHG_REG |
 646                TG3_FLAG_POLL_SERDES))) {
 647                 if (sblk->status & SD_STATUS_LINK_CHG)
 648                         work_exists = 1;
 649         }
 650         /* check for RX/TX work to do */
 651         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
 652             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
 653                 work_exists = 1;
 654
 655         return work_exists;
 656 }
 657
 658 /* tg3_restart_ints
 659  *  similar to tg3_enable_ints, but it accurately determines whether there
 660  *  is new work pending and can return without flushing the PIO write
 661  *  which reenables interrupts
 662  */
 663 static void tg3_restart_ints(struct tg3 *tp)
 664 {
 665         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 666                      tp->last_tag << 24);
 667         mmiowb();
 668
 669         /* When doing tagged status, this work check is unnecessary.
 670          * The last_tag we write above tells the chip which piece of
 671          * work we've completed.
 672          */
 673         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 674             tg3_has_work(tp))
 675                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 676                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 677 }
 678
 679 static inline void tg3_netif_stop(struct tg3 *tp)
 680 {
 681         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 682         napi_disable(&tp->napi);
 683         netif_tx_disable(tp->dev);
 684 }
 685
 686 static inline void tg3_netif_start(struct tg3 *tp)
 687 {
 688         netif_wake_queue(tp->dev);
 689         /* NOTE: unconditional netif_wake_queue is only appropriate
 690          * so long as all callers are assured to have free tx slots
 691          * (such as after tg3_init_hw)
 692          */
 693         napi_enable(&tp->napi);
 694         tp->hw_status->status |= SD_STATUS_UPDATED;
 695         tg3_enable_ints(tp);
 696 }
 697
 698 static void tg3_switch_clocks(struct tg3 *tp)
 699 {
 700         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 701         u32 orig_clock_ctrl;
 702
 703         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 704             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 705                 return;
 706
 707         orig_clock_ctrl = clock_ctrl;
 708         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 709                        CLOCK_CTRL_CLKRUN_OENABLE |
 710                        0x1f);
 711         tp->pci_clock_ctrl = clock_ctrl;
 712
 713         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 714                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 715                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 716                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 717                 }
 718         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 719                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 720                             clock_ctrl |
 721                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 722                             40);
 723                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 724                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 725                             40);
 726         }
 727         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 728 }
 729
 730 #define PHY_BUSY_LOOPS  5000
 731
 732 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 733 {
 734         u32 frame_val;
 735         unsigned int loops;
 736         int ret;
 737
 738         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 739                 tw32_f(MAC_MI_MODE,
 740                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 741                 udelay(80);
 742         }
 743
 744         *val = 0x0;
 745
 746         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 747                       MI_COM_PHY_ADDR_MASK);
 748         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 749                       MI_COM_REG_ADDR_MASK);
 750         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 751
 752         tw32_f(MAC_MI_COM, frame_val);
 753
 754         loops = PHY_BUSY_LOOPS;
 755         while (loops != 0) {
 756                 udelay(10);
 757                 frame_val = tr32(MAC_MI_COM);
 758
 759                 if ((frame_val & MI_COM_BUSY) == 0) {
 760                         udelay(5);
 761                         frame_val = tr32(MAC_MI_COM);
 762                         break;
 763                 }
 764                 loops -= 1;
 765         }
 766
 767         ret = -EBUSY;
 768         if (loops != 0) {
 769                 *val = frame_val & MI_COM_DATA_MASK;
 770                 ret = 0;
 771         }
 772
 773         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 774                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 775                 udelay(80);
 776         }
 777
 778         return ret;
 779 }
 780
 781 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 782 {
 783         u32 frame_val;
 784         unsigned int loops;
 785         int ret;
 786
 787         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
 788             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 789                 return 0;
 790
 791         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 792                 tw32_f(MAC_MI_MODE,
 793                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 794                 udelay(80);
 795         }
 796
 797         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 798                       MI_COM_PHY_ADDR_MASK);
 799         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 800                       MI_COM_REG_ADDR_MASK);
 801         frame_val |= (val & MI_COM_DATA_MASK);
 802         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 803
 804         tw32_f(MAC_MI_COM, frame_val);
 805
 806         loops = PHY_BUSY_LOOPS;
 807         while (loops != 0) {
 808                 udelay(10);
 809                 frame_val = tr32(MAC_MI_COM);
 810                 if ((frame_val & MI_COM_BUSY) == 0) {
 811                         udelay(5);
 812                         frame_val = tr32(MAC_MI_COM);
 813                         break;
 814                 }
 815                 loops -= 1;
 816         }
 817
 818         ret = -EBUSY;
 819         if (loops != 0)
 820                 ret = 0;
 821
 822         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 823                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 824                 udelay(80);
 825         }
 826
 827         return ret;
 828 }
 829
 830 static int tg3_bmcr_reset(struct tg3 *tp)
 831 {
 832         u32 phy_control;
 833         int limit, err;
 834
 835         /* OK, reset it, and poll the BMCR_RESET bit until it
 836          * clears or we time out.
 837          */
 838         phy_control = BMCR_RESET;
 839         err = tg3_writephy(tp, MII_BMCR, phy_control);
 840         if (err != 0)
 841                 return -EBUSY;
 842
 843         limit = 5000;
 844         while (limit--) {
 845                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 846                 if (err != 0)
 847                         return -EBUSY;
 848
 849                 if ((phy_control & BMCR_RESET) == 0) {
 850                         udelay(40);
 851                         break;
 852                 }
 853                 udelay(10);
 854         }
 855         if (limit < 0)
 856                 return -EBUSY;
 857
 858         return 0;
 859 }
 860
 861 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 862 {
 863         struct tg3 *tp = bp->priv;
 864         u32 val;
 865
 866         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
 867                 return -EAGAIN;
 868
 869         if (tg3_readphy(tp, reg, &val))
 870                 return -EIO;
 871
 872         return val;
 873 }
 874
 875 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 876 {
 877         struct tg3 *tp = bp->priv;
 878
 879         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
 880                 return -EAGAIN;
 881
 882         if (tg3_writephy(tp, reg, val))
 883                 return -EIO;
 884
 885         return 0;
 886 }
 887
 888 static int tg3_mdio_reset(struct mii_bus *bp)
 889 {
 890         return 0;
 891 }
 892
 893 static void tg3_mdio_config_5785(struct tg3 *tp)
 894 {
 895         u32 val;
 896         struct phy_device *phydev;
 897
 898         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
 899         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 900         case TG3_PHY_ID_BCM50610:
 901                 val = MAC_PHYCFG2_50610_LED_MODES;
 902                 break;
 903         case TG3_PHY_ID_BCMAC131:
 904                 val = MAC_PHYCFG2_AC131_LED_MODES;
 905                 break;
 906         case TG3_PHY_ID_RTL8211C:
 907                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 908                 break;
 909         case TG3_PHY_ID_RTL8201E:
 910                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 911                 break;
 912         default:
 913                 return;
 914         }
 915
 916         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 917                 tw32(MAC_PHYCFG2, val);
 918
 919                 val = tr32(MAC_PHYCFG1);
 920                 val &= ~MAC_PHYCFG1_RGMII_INT;
 921                 tw32(MAC_PHYCFG1, val);
 922
 923                 return;
 924         }
 925
 926         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
 927                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 928                        MAC_PHYCFG2_FMODE_MASK_MASK |
 929                        MAC_PHYCFG2_GMODE_MASK_MASK |
 930                        MAC_PHYCFG2_ACT_MASK_MASK   |
 931                        MAC_PHYCFG2_QUAL_MASK_MASK |
 932                        MAC_PHYCFG2_INBAND_ENABLE;
 933
 934         tw32(MAC_PHYCFG2, val);
 935
 936         val = tr32(MAC_PHYCFG1) & ~(MAC_PHYCFG1_RGMII_EXT_RX_DEC |
 937                                     MAC_PHYCFG1_RGMII_SND_STAT_EN);
 938         if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {
 939                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 940                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
 941                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 942                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
 943         }
 944         tw32(MAC_PHYCFG1, val | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV);
 945
 946         val = tr32(MAC_EXT_RGMII_MODE);
 947         val &= ~(MAC_RGMII_MODE_RX_INT_B |
 948                  MAC_RGMII_MODE_RX_QUALITY |
 949                  MAC_RGMII_MODE_RX_ACTIVITY |
 950                  MAC_RGMII_MODE_RX_ENG_DET |
 951                  MAC_RGMII_MODE_TX_ENABLE |
 952                  MAC_RGMII_MODE_TX_LOWPWR |
 953                  MAC_RGMII_MODE_TX_RESET);
 954         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
 955                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 956                         val |= MAC_RGMII_MODE_RX_INT_B |
 957                                MAC_RGMII_MODE_RX_QUALITY |
 958                                MAC_RGMII_MODE_RX_ACTIVITY |
 959                                MAC_RGMII_MODE_RX_ENG_DET;
 960                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 961                         val |= MAC_RGMII_MODE_TX_ENABLE |
 962                                MAC_RGMII_MODE_TX_LOWPWR |
 963                                MAC_RGMII_MODE_TX_RESET;
 964         }
 965         tw32(MAC_EXT_RGMII_MODE, val);
 966 }
 967
 968 static void tg3_mdio_start(struct tg3 *tp)
 969 {
 970         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
 971                 mutex_lock(&tp->mdio_bus->mdio_lock);
 972                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
 973                 mutex_unlock(&tp->mdio_bus->mdio_lock);
 974         }
 975
 976         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
 977         tw32_f(MAC_MI_MODE, tp->mi_mode);
 978         udelay(80);
 979
 980         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
 981             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
 982                 tg3_mdio_config_5785(tp);
 983 }
 984
 985 static void tg3_mdio_stop(struct tg3 *tp)
 986 {
 987         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
 988                 mutex_lock(&tp->mdio_bus->mdio_lock);
 989                 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
 990                 mutex_unlock(&tp->mdio_bus->mdio_lock);
 991         }
 992 }
 993
 994 static int tg3_mdio_init(struct tg3 *tp)
 995 {
 996         int i;
 997         u32 reg;
 998         struct phy_device *phydev;
 999
1000         tg3_mdio_start(tp);
1001
1002         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1003             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1004                 return 0;
1005
1006         tp->mdio_bus = mdiobus_alloc();
1007         if (tp->mdio_bus == NULL)
1008                 return -ENOMEM;
1009
1010         tp->mdio_bus->name     = "tg3 mdio bus";
1011         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1012                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1013         tp->mdio_bus->priv     = tp;
1014         tp->mdio_bus->parent   = &tp->pdev->dev;
1015         tp->mdio_bus->read     = &tg3_mdio_read;
1016         tp->mdio_bus->write    = &tg3_mdio_write;
1017         tp->mdio_bus->reset    = &tg3_mdio_reset;
1018         tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
1019         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1020
1021         for (i = 0; i < PHY_MAX_ADDR; i++)
1022                 tp->mdio_bus->irq[i] = PHY_POLL;
1023
1024         /* The bus registration will look for all the PHYs on the mdio bus.
1025          * Unfortunately, it does not ensure the PHY is powered up before
1026          * accessing the PHY ID registers.  A chip reset is the
1027          * quickest way to bring the device back to an operational state..
1028          */
1029         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1030                 tg3_bmcr_reset(tp);
1031
1032         i = mdiobus_register(tp->mdio_bus);
1033         if (i) {
1034                 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1035                         tp->dev->name, i);
1036                 mdiobus_free(tp->mdio_bus);
1037                 return i;
1038         }
1039
1040         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1041
1042         if (!phydev || !phydev->drv) {
1043                 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1044                 mdiobus_unregister(tp->mdio_bus);
1045                 mdiobus_free(tp->mdio_bus);
1046                 return -ENODEV;
1047         }
1048
1049         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1050         case TG3_PHY_ID_BCM57780:
1051                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1052                 break;
1053         case TG3_PHY_ID_BCM50610:
1054                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1055                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1056                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1057                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1058                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1059                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1060                 /* fallthru */
1061         case TG3_PHY_ID_RTL8211C:
1062                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1063                 break;
1064         case TG3_PHY_ID_RTL8201E:
1065         case TG3_PHY_ID_BCMAC131:
1066                 phydev->interface = PHY_INTERFACE_MODE_MII;
1067                 break;
1068         }
1069
1070         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1071
1072         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1073                 tg3_mdio_config_5785(tp);
1074
1075         return 0;
1076 }
1077
1078 static void tg3_mdio_fini(struct tg3 *tp)
1079 {
1080         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1081                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1082                 mdiobus_unregister(tp->mdio_bus);
1083                 mdiobus_free(tp->mdio_bus);
1084                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1085         }
1086 }
1087
1088 /* tp->lock is held. */
1089 static inline void tg3_generate_fw_event(struct tg3 *tp)
1090 {
1091         u32 val;
1092
1093         val = tr32(GRC_RX_CPU_EVENT);
1094         val |= GRC_RX_CPU_DRIVER_EVENT;
1095         tw32_f(GRC_RX_CPU_EVENT, val);
1096
1097         tp->last_event_jiffies = jiffies;
1098 }
1099
1100 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1101
1102 /* tp->lock is held. */
1103 static void tg3_wait_for_event_ack(struct tg3 *tp)
1104 {
1105         int i;
1106         unsigned int delay_cnt;
1107         long time_remain;
1108
1109         /* If enough time has passed, no wait is necessary. */
1110         time_remain = (long)(tp->last_event_jiffies + 1 +
1111                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1112                       (long)jiffies;
1113         if (time_remain < 0)
1114                 return;
1115
1116         /* Check if we can shorten the wait time. */
1117         delay_cnt = jiffies_to_usecs(time_remain);
1118         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1119                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1120         delay_cnt = (delay_cnt >> 3) + 1;
1121
1122         for (i = 0; i < delay_cnt; i++) {
1123                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1124                         break;
1125                 udelay(8);
1126         }
1127 }
1128
1129 /* tp->lock is held. */
1130 static void tg3_ump_link_report(struct tg3 *tp)
1131 {
1132         u32 reg;
1133         u32 val;
1134
1135         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1136             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1137                 return;
1138
1139         tg3_wait_for_event_ack(tp);
1140
1141         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1142
1143         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1144
1145         val = 0;
1146         if (!tg3_readphy(tp, MII_BMCR, &reg))
1147                 val = reg << 16;
1148         if (!tg3_readphy(tp, MII_BMSR, &reg))
1149                 val |= (reg & 0xffff);
1150         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1151
1152         val = 0;
1153         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1154                 val = reg << 16;
1155         if (!tg3_readphy(tp, MII_LPA, &reg))
1156                 val |= (reg & 0xffff);
1157         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1158
1159         val = 0;
1160         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1161                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1162                         val = reg << 16;
1163                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1164                         val |= (reg & 0xffff);
1165         }
1166         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1167
1168         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1169                 val = reg << 16;
1170         else
1171                 val = 0;
1172         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1173
1174         tg3_generate_fw_event(tp);
1175 }
1176
1177 static void tg3_link_report(struct tg3 *tp)
1178 {
1179         if (!netif_carrier_ok(tp->dev)) {
1180                 if (netif_msg_link(tp))
1181                         printk(KERN_INFO PFX "%s: Link is down.\n",
1182                                tp->dev->name);
1183                 tg3_ump_link_report(tp);
1184         } else if (netif_msg_link(tp)) {
1185                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1186                        tp->dev->name,
1187                        (tp->link_config.active_speed == SPEED_1000 ?
1188                         1000 :
1189                         (tp->link_config.active_speed == SPEED_100 ?
1190                          100 : 10)),
1191                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1192                         "full" : "half"));
1193
1194                 printk(KERN_INFO PFX
1195                        "%s: Flow control is %s for TX and %s for RX.\n",
1196                        tp->dev->name,
1197                        (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1198                        "on" : "off",
1199                        (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1200                        "on" : "off");
1201                 tg3_ump_link_report(tp);
1202         }
1203 }
1204
1205 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1206 {
1207         u16 miireg;
1208
1209         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1210                 miireg = ADVERTISE_PAUSE_CAP;
1211         else if (flow_ctrl & FLOW_CTRL_TX)
1212                 miireg = ADVERTISE_PAUSE_ASYM;
1213         else if (flow_ctrl & FLOW_CTRL_RX)
1214                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1215         else
1216                 miireg = 0;
1217
1218         return miireg;
1219 }
1220
1221 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1222 {
1223         u16 miireg;
1224
1225         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1226                 miireg = ADVERTISE_1000XPAUSE;
1227         else if (flow_ctrl & FLOW_CTRL_TX)
1228                 miireg = ADVERTISE_1000XPSE_ASYM;
1229         else if (flow_ctrl & FLOW_CTRL_RX)
1230                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1231         else
1232                 miireg = 0;
1233
1234         return miireg;
1235 }
1236
1237 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1238 {
1239         u8 cap = 0;
1240
1241         if (lcladv & ADVERTISE_1000XPAUSE) {
1242                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1243                         if (rmtadv & LPA_1000XPAUSE)
1244                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1245                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1246                                 cap = FLOW_CTRL_RX;
1247                 } else {
1248                         if (rmtadv & LPA_1000XPAUSE)
1249                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1250                 }
1251         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1252                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1253                         cap = FLOW_CTRL_TX;
1254         }
1255
1256         return cap;
1257 }
1258
1259 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1260 {
1261         u8 autoneg;
1262         u8 flowctrl = 0;
1263         u32 old_rx_mode = tp->rx_mode;
1264         u32 old_tx_mode = tp->tx_mode;
1265
1266         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1267                 autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
1268         else
1269                 autoneg = tp->link_config.autoneg;
1270
1271         if (autoneg == AUTONEG_ENABLE &&
1272             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1273                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1274                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1275                 else
1276                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1277         } else
1278                 flowctrl = tp->link_config.flowctrl;
1279
1280         tp->link_config.active_flowctrl = flowctrl;
1281
1282         if (flowctrl & FLOW_CTRL_RX)
1283                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1284         else
1285                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1286
1287         if (old_rx_mode != tp->rx_mode)
1288                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1289
1290         if (flowctrl & FLOW_CTRL_TX)
1291                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1292         else
1293                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1294
1295         if (old_tx_mode != tp->tx_mode)
1296                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1297 }
1298
1299 static void tg3_adjust_link(struct net_device *dev)
1300 {
1301         u8 oldflowctrl, linkmesg = 0;
1302         u32 mac_mode, lcl_adv, rmt_adv;
1303         struct tg3 *tp = netdev_priv(dev);
1304         struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1305
1306         spin_lock(&tp->lock);
1307
1308         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1309                                     MAC_MODE_HALF_DUPLEX);
1310
1311         oldflowctrl = tp->link_config.active_flowctrl;
1312
1313         if (phydev->link) {
1314                 lcl_adv = 0;
1315                 rmt_adv = 0;
1316
1317                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1318                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1319                 else
1320                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1321
1322                 if (phydev->duplex == DUPLEX_HALF)
1323                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1324                 else {
1325                         lcl_adv = tg3_advert_flowctrl_1000T(
1326                                   tp->link_config.flowctrl);
1327
1328                         if (phydev->pause)
1329                                 rmt_adv = LPA_PAUSE_CAP;
1330                         if (phydev->asym_pause)
1331                                 rmt_adv |= LPA_PAUSE_ASYM;
1332                 }
1333
1334                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1335         } else
1336                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1337
1338         if (mac_mode != tp->mac_mode) {
1339                 tp->mac_mode = mac_mode;
1340                 tw32_f(MAC_MODE, tp->mac_mode);
1341                 udelay(40);
1342         }
1343
1344         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1345                 if (phydev->speed == SPEED_10)
1346                         tw32(MAC_MI_STAT,
1347                              MAC_MI_STAT_10MBPS_MODE |
1348                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1349                 else
1350                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1351         }
1352
1353         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1354                 tw32(MAC_TX_LENGTHS,
1355                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1356                       (6 << TX_LENGTHS_IPG_SHIFT) |
1357                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1358         else
1359                 tw32(MAC_TX_LENGTHS,
1360                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1361                       (6 << TX_LENGTHS_IPG_SHIFT) |
1362                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1363
1364         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1365             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1366             phydev->speed != tp->link_config.active_speed ||
1367             phydev->duplex != tp->link_config.active_duplex ||
1368             oldflowctrl != tp->link_config.active_flowctrl)
1369             linkmesg = 1;
1370
1371         tp->link_config.active_speed = phydev->speed;
1372         tp->link_config.active_duplex = phydev->duplex;
1373
1374         spin_unlock(&tp->lock);
1375
1376         if (linkmesg)
1377                 tg3_link_report(tp);
1378 }
1379
1380 static int tg3_phy_init(struct tg3 *tp)
1381 {
1382         struct phy_device *phydev;
1383
1384         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1385                 return 0;
1386
1387         /* Bring the PHY back to a known state. */
1388         tg3_bmcr_reset(tp);
1389
1390         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1391
1392         /* Attach the MAC to the PHY. */
1393         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1394                              phydev->dev_flags, phydev->interface);
1395         if (IS_ERR(phydev)) {
1396                 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1397                 return PTR_ERR(phydev);
1398         }
1399
1400         /* Mask with MAC supported features. */
1401         switch (phydev->interface) {
1402         case PHY_INTERFACE_MODE_GMII:
1403         case PHY_INTERFACE_MODE_RGMII:
1404                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1405                         phydev->supported &= (PHY_GBIT_FEATURES |
1406                                               SUPPORTED_Pause |
1407                                               SUPPORTED_Asym_Pause);
1408                         break;
1409                 }
1410                 /* fallthru */
1411         case PHY_INTERFACE_MODE_MII:
1412                 phydev->supported &= (PHY_BASIC_FEATURES |
1413                                       SUPPORTED_Pause |
1414                                       SUPPORTED_Asym_Pause);
1415                 break;
1416         default:
1417                 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1418                 return -EINVAL;
1419         }
1420
1421         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1422
1423         phydev->advertising = phydev->supported;
1424
1425         return 0;
1426 }
1427
1428 static void tg3_phy_start(struct tg3 *tp)
1429 {
1430         struct phy_device *phydev;
1431
1432         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1433                 return;
1434
1435         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1436
1437         if (tp->link_config.phy_is_low_power) {
1438                 tp->link_config.phy_is_low_power = 0;
1439                 phydev->speed = tp->link_config.orig_speed;
1440                 phydev->duplex = tp->link_config.orig_duplex;
1441                 phydev->autoneg = tp->link_config.orig_autoneg;
1442                 phydev->advertising = tp->link_config.orig_advertising;
1443         }
1444
1445         phy_start(phydev);
1446
1447         phy_start_aneg(phydev);
1448 }
1449
1450 static void tg3_phy_stop(struct tg3 *tp)
1451 {
1452         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1453                 return;
1454
1455         phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
1456 }
1457
1458 static void tg3_phy_fini(struct tg3 *tp)
1459 {
1460         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1461                 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1462                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1463         }
1464 }
1465
1466 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1467 {
1468         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1469         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1470 }
1471
1472 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1473 {
1474         u32 reg;
1475
1476         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1477             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
1478                 return;
1479
1480         reg = MII_TG3_MISC_SHDW_WREN |
1481               MII_TG3_MISC_SHDW_SCR5_SEL |
1482               MII_TG3_MISC_SHDW_SCR5_LPED |
1483               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1484               MII_TG3_MISC_SHDW_SCR5_SDTL |
1485               MII_TG3_MISC_SHDW_SCR5_C125OE;
1486         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1487                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1488
1489         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1490
1491
1492         reg = MII_TG3_MISC_SHDW_WREN |
1493               MII_TG3_MISC_SHDW_APD_SEL |
1494               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1495         if (enable)
1496                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1497
1498         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1499 }
1500
1501 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1502 {
1503         u32 phy;
1504
1505         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1506             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1507                 return;
1508
1509         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1510                 u32 ephy;
1511
1512                 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
1513                         tg3_writephy(tp, MII_TG3_EPHY_TEST,
1514                                      ephy | MII_TG3_EPHY_SHADOW_EN);
1515                         if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
1516                                 if (enable)
1517                                         phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
1518                                 else
1519                                         phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
1520                                 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
1521                         }
1522                         tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
1523                 }
1524         } else {
1525                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1526                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1527                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1528                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1529                         if (enable)
1530                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1531                         else
1532                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1533                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1534                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1535                 }
1536         }
1537 }
1538
1539 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1540 {
1541         u32 val;
1542
1543         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1544                 return;
1545
1546         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1547             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1548                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1549                              (val | (1 << 15) | (1 << 4)));
1550 }
1551
1552 static void tg3_phy_apply_otp(struct tg3 *tp)
1553 {
1554         u32 otp, phy;
1555
1556         if (!tp->phy_otp)
1557                 return;
1558
1559         otp = tp->phy_otp;
1560
1561         /* Enable SM_DSP clock and tx 6dB coding. */
1562         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1563               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1564               MII_TG3_AUXCTL_ACTL_TX_6DB;
1565         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1566
1567         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1568         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1569         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1570
1571         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1572               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1573         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1574
1575         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1576         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1577         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1578
1579         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1580         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1581
1582         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1583         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1584
1585         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1586               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1587         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1588
1589         /* Turn off SM_DSP clock. */
1590         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1591               MII_TG3_AUXCTL_ACTL_TX_6DB;
1592         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1593 }
1594
1595 static int tg3_wait_macro_done(struct tg3 *tp)
1596 {
1597         int limit = 100;
1598
1599         while (limit--) {
1600                 u32 tmp32;
1601
1602                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1603                         if ((tmp32 & 0x1000) == 0)
1604                                 break;
1605                 }
1606         }
1607         if (limit < 0)
1608                 return -EBUSY;
1609
1610         return 0;
1611 }
1612
1613 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1614 {
1615         static const u32 test_pat[4][6] = {
1616         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1617         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1618         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1619         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1620         };
1621         int chan;
1622
1623         for (chan = 0; chan < 4; chan++) {
1624                 int i;
1625
1626                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1627                              (chan * 0x2000) | 0x0200);
1628                 tg3_writephy(tp, 0x16, 0x0002);
1629
1630                 for (i = 0; i < 6; i++)
1631                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1632                                      test_pat[chan][i]);
1633
1634                 tg3_writephy(tp, 0x16, 0x0202);
1635                 if (tg3_wait_macro_done(tp)) {
1636                         *resetp = 1;
1637                         return -EBUSY;
1638                 }
1639
1640                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1641                              (chan * 0x2000) | 0x0200);
1642                 tg3_writephy(tp, 0x16, 0x0082);
1643                 if (tg3_wait_macro_done(tp)) {
1644                         *resetp = 1;
1645                         return -EBUSY;
1646                 }
1647
1648                 tg3_writephy(tp, 0x16, 0x0802);
1649                 if (tg3_wait_macro_done(tp)) {
1650                         *resetp = 1;
1651                         return -EBUSY;
1652                 }
1653
1654                 for (i = 0; i < 6; i += 2) {
1655                         u32 low, high;
1656
1657                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1658                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1659                             tg3_wait_macro_done(tp)) {
1660                                 *resetp = 1;
1661                                 return -EBUSY;
1662                         }
1663                         low &= 0x7fff;
1664                         high &= 0x000f;
1665                         if (low != test_pat[chan][i] ||
1666                             high != test_pat[chan][i+1]) {
1667                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1668                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1669                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1670
1671                                 return -EBUSY;
1672                         }
1673                 }
1674         }
1675
1676         return 0;
1677 }
1678
1679 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1680 {
1681         int chan;
1682
1683         for (chan = 0; chan < 4; chan++) {
1684                 int i;
1685
1686                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1687                              (chan * 0x2000) | 0x0200);
1688                 tg3_writephy(tp, 0x16, 0x0002);
1689                 for (i = 0; i < 6; i++)
1690                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1691                 tg3_writephy(tp, 0x16, 0x0202);
1692                 if (tg3_wait_macro_done(tp))
1693                         return -EBUSY;
1694         }
1695
1696         return 0;
1697 }
1698
1699 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1700 {
1701         u32 reg32, phy9_orig;
1702         int retries, do_phy_reset, err;
1703
1704         retries = 10;
1705         do_phy_reset = 1;
1706         do {
1707                 if (do_phy_reset) {
1708                         err = tg3_bmcr_reset(tp);
1709                         if (err)
1710                                 return err;
1711                         do_phy_reset = 0;
1712                 }
1713
1714                 /* Disable transmitter and interrupt.  */
1715                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1716                         continue;
1717
1718                 reg32 |= 0x3000;
1719                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1720
1721                 /* Set full-duplex, 1000 mbps.  */
1722                 tg3_writephy(tp, MII_BMCR,
1723                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1724
1725                 /* Set to master mode.  */
1726                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1727                         continue;
1728
1729                 tg3_writephy(tp, MII_TG3_CTRL,
1730                              (MII_TG3_CTRL_AS_MASTER |
1731                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1732
1733                 /* Enable SM_DSP_CLOCK and 6dB.  */
1734                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1735
1736                 /* Block the PHY control access.  */
1737                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1738                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1739
1740                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1741                 if (!err)
1742                         break;
1743         } while (--retries);
1744
1745         err = tg3_phy_reset_chanpat(tp);
1746         if (err)
1747                 return err;
1748
1749         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1750         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1751
1752         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1753         tg3_writephy(tp, 0x16, 0x0000);
1754
1755         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1756             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1757                 /* Set Extended packet length bit for jumbo frames */
1758                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1759         }
1760         else {
1761                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1762         }
1763
1764         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1765
1766         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1767                 reg32 &= ~0x3000;
1768                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1769         } else if (!err)
1770                 err = -EBUSY;
1771
1772         return err;
1773 }
1774
1775 /* This will reset the tigon3 PHY if there is no valid
1776  * link unless the FORCE argument is non-zero.
1777  */
1778 static int tg3_phy_reset(struct tg3 *tp)
1779 {
1780         u32 cpmuctrl;
1781         u32 phy_status;
1782         int err;
1783
1784         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1785                 u32 val;
1786
1787                 val = tr32(GRC_MISC_CFG);
1788                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1789                 udelay(40);
1790         }
1791         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1792         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1793         if (err != 0)
1794                 return -EBUSY;
1795
1796         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1797                 netif_carrier_off(tp->dev);
1798                 tg3_link_report(tp);
1799         }
1800
1801         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1802             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1803             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1804                 err = tg3_phy_reset_5703_4_5(tp);
1805                 if (err)
1806                         return err;
1807                 goto out;
1808         }
1809
1810         cpmuctrl = 0;
1811         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1812             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1813                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1814                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1815                         tw32(TG3_CPMU_CTRL,
1816                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1817         }
1818
1819         err = tg3_bmcr_reset(tp);
1820         if (err)
1821                 return err;
1822
1823         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1824                 u32 phy;
1825
1826                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1827                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1828
1829                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1830         }
1831
1832         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1833             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1834                 u32 val;
1835
1836                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1837                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1838                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1839                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1840                         udelay(40);
1841                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1842                 }
1843         }
1844
1845         tg3_phy_apply_otp(tp);
1846
1847         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1848                 tg3_phy_toggle_apd(tp, true);
1849         else
1850                 tg3_phy_toggle_apd(tp, false);
1851
1852 out:
1853         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1854                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1855                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1856                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1857                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1858                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1859                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1860         }
1861         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1862                 tg3_writephy(tp, 0x1c, 0x8d68);
1863                 tg3_writephy(tp, 0x1c, 0x8d68);
1864         }
1865         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1866                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1867                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1868                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1869                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1870                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1871                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1872                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1873                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1874         }
1875         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1876                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1877                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1878                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1879                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1880                         tg3_writephy(tp, MII_TG3_TEST1,
1881                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1882                 } else
1883                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1884                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1885         }
1886         /* Set Extended packet length bit (bit 14) on all chips that */
1887         /* support jumbo frames */
1888         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1889                 /* Cannot do read-modify-write on 5401 */
1890                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1891         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1892                 u32 phy_reg;
1893
1894                 /* Set bit 14 with read-modify-write to preserve other bits */
1895                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1896                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1897                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1898         }
1899
1900         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1901          * jumbo frames transmission.
1902          */
1903         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1904                 u32 phy_reg;
1905
1906                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1907                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1908                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1909         }
1910
1911         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1912                 /* adjust output voltage */
1913                 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1914         }
1915
1916         tg3_phy_toggle_automdix(tp, 1);
1917         tg3_phy_set_wirespeed(tp);
1918         return 0;
1919 }
1920
1921 static void tg3_frob_aux_power(struct tg3 *tp)
1922 {
1923         struct tg3 *tp_peer = tp;
1924
1925         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1926                 return;
1927
1928         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1929             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1930                 struct net_device *dev_peer;
1931
1932                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1933                 /* remove_one() may have been run on the peer. */
1934                 if (!dev_peer)
1935                         tp_peer = tp;
1936                 else
1937                         tp_peer = netdev_priv(dev_peer);
1938         }
1939
1940         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1941             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1942             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1943             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1944                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1945                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1946                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1947                                     (GRC_LCLCTRL_GPIO_OE0 |
1948                                      GRC_LCLCTRL_GPIO_OE1 |
1949                                      GRC_LCLCTRL_GPIO_OE2 |
1950                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1951                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1952                                     100);
1953                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
1954                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
1955                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1956                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1957                                              GRC_LCLCTRL_GPIO_OE1 |
1958                                              GRC_LCLCTRL_GPIO_OE2 |
1959                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
1960                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
1961                                              tp->grc_local_ctrl;
1962                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1963
1964                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
1965                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1966
1967                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
1968                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1969                 } else {
1970                         u32 no_gpio2;
1971                         u32 grc_local_ctrl = 0;
1972
1973                         if (tp_peer != tp &&
1974                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1975                                 return;
1976
1977                         /* Workaround to prevent overdrawing Amps. */
1978                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1979                             ASIC_REV_5714) {
1980                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1981                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1982                                             grc_local_ctrl, 100);
1983                         }
1984
1985                         /* On 5753 and variants, GPIO2 cannot be used. */
1986                         no_gpio2 = tp->nic_sram_data_cfg &
1987                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1988
1989                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1990                                          GRC_LCLCTRL_GPIO_OE1 |
1991                                          GRC_LCLCTRL_GPIO_OE2 |
1992                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1993                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1994                         if (no_gpio2) {
1995                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1996                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
1997                         }
1998                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1999                                                     grc_local_ctrl, 100);
2000
2001                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2002
2003                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2004                                                     grc_local_ctrl, 100);
2005
2006                         if (!no_gpio2) {
2007                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2008                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2009                                             grc_local_ctrl, 100);
2010                         }
2011                 }
2012         } else {
2013                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2014                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2015                         if (tp_peer != tp &&
2016                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2017                                 return;
2018
2019                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2020                                     (GRC_LCLCTRL_GPIO_OE1 |
2021                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2022
2023                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2024                                     GRC_LCLCTRL_GPIO_OE1, 100);
2025
2026                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2027                                     (GRC_LCLCTRL_GPIO_OE1 |
2028                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2029                 }
2030         }
2031 }
2032
2033 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2034 {
2035         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2036                 return 1;
2037         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2038                 if (speed != SPEED_10)
2039                         return 1;
2040         } else if (speed == SPEED_10)
2041                 return 1;
2042
2043         return 0;
2044 }
2045
2046 static int tg3_setup_phy(struct tg3 *, int);
2047
2048 #define RESET_KIND_SHUTDOWN     0
2049 #define RESET_KIND_INIT         1
2050 #define RESET_KIND_SUSPEND      2
2051
2052 static void tg3_write_sig_post_reset(struct tg3 *, int);
2053 static int tg3_halt_cpu(struct tg3 *, u32);
2054
2055 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2056 {
2057         u32 val;
2058
2059         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2060                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2061                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2062                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2063
2064                         sg_dig_ctrl |=
2065                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2066                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2067                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2068                 }
2069                 return;
2070         }
2071
2072         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2073                 tg3_bmcr_reset(tp);
2074                 val = tr32(GRC_MISC_CFG);
2075                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2076                 udelay(40);
2077                 return;
2078         } else if (do_low_power) {
2079                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2080                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2081
2082                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2083                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2084                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2085                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2086                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2087         }
2088
2089         /* The PHY should not be powered down on some chips because
2090          * of bugs.
2091          */
2092         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2093             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2094             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2095              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2096                 return;
2097
2098         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2099             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2100                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2101                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2102                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2103                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2104         }
2105
2106         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2107 }
2108
2109 /* tp->lock is held. */
2110 static int tg3_nvram_lock(struct tg3 *tp)
2111 {
2112         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2113                 int i;
2114
2115                 if (tp->nvram_lock_cnt == 0) {
2116                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2117                         for (i = 0; i < 8000; i++) {
2118                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2119                                         break;
2120                                 udelay(20);
2121                         }
2122                         if (i == 8000) {
2123                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2124                                 return -ENODEV;
2125                         }
2126                 }
2127                 tp->nvram_lock_cnt++;
2128         }
2129         return 0;
2130 }
2131
2132 /* tp->lock is held. */
2133 static void tg3_nvram_unlock(struct tg3 *tp)
2134 {
2135         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2136                 if (tp->nvram_lock_cnt > 0)
2137                         tp->nvram_lock_cnt--;
2138                 if (tp->nvram_lock_cnt == 0)
2139                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2140         }
2141 }
2142
2143 /* tp->lock is held. */
2144 static void tg3_enable_nvram_access(struct tg3 *tp)
2145 {
2146         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2147             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2148                 u32 nvaccess = tr32(NVRAM_ACCESS);
2149
2150                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2151         }
2152 }
2153
2154 /* tp->lock is held. */
2155 static void tg3_disable_nvram_access(struct tg3 *tp)
2156 {
2157         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2158             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2159                 u32 nvaccess = tr32(NVRAM_ACCESS);
2160
2161                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2162         }
2163 }
2164
2165 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2166                                         u32 offset, u32 *val)
2167 {
2168         u32 tmp;
2169         int i;
2170
2171         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2172                 return -EINVAL;
2173
2174         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2175                                         EEPROM_ADDR_DEVID_MASK |
2176                                         EEPROM_ADDR_READ);
2177         tw32(GRC_EEPROM_ADDR,
2178              tmp |
2179              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2180              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2181               EEPROM_ADDR_ADDR_MASK) |
2182              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2183
2184         for (i = 0; i < 1000; i++) {
2185                 tmp = tr32(GRC_EEPROM_ADDR);
2186
2187                 if (tmp & EEPROM_ADDR_COMPLETE)
2188                         break;
2189                 msleep(1);
2190         }
2191         if (!(tmp & EEPROM_ADDR_COMPLETE))
2192                 return -EBUSY;
2193
2194         tmp = tr32(GRC_EEPROM_DATA);
2195
2196         /*
2197          * The data will always be opposite the native endian
2198          * format.  Perform a blind byteswap to compensate.
2199          */
2200         *val = swab32(tmp);
2201
2202         return 0;
2203 }
2204
2205 #define NVRAM_CMD_TIMEOUT 10000
2206
2207 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2208 {
2209         int i;
2210
2211         tw32(NVRAM_CMD, nvram_cmd);
2212         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2213                 udelay(10);
2214                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2215                         udelay(10);
2216                         break;
2217                 }
2218         }
2219
2220         if (i == NVRAM_CMD_TIMEOUT)
2221                 return -EBUSY;
2222
2223         return 0;
2224 }
2225
2226 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2227 {
2228         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2229             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2230             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2231            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2232             (tp->nvram_jedecnum == JEDEC_ATMEL))
2233
2234                 addr = ((addr / tp->nvram_pagesize) <<
2235                         ATMEL_AT45DB0X1B_PAGE_POS) +
2236                        (addr % tp->nvram_pagesize);
2237
2238         return addr;
2239 }
2240
2241 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2242 {
2243         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2244             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2245             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2246            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2247             (tp->nvram_jedecnum == JEDEC_ATMEL))
2248
2249                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2250                         tp->nvram_pagesize) +
2251                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2252
2253         return addr;
2254 }
2255
2256 /* NOTE: Data read in from NVRAM is byteswapped according to
2257  * the byteswapping settings for all other register accesses.
2258  * tg3 devices are BE devices, so on a BE machine, the data
2259  * returned will be exactly as it is seen in NVRAM.  On a LE
2260  * machine, the 32-bit value will be byteswapped.
2261  */
2262 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2263 {
2264         int ret;
2265
2266         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2267                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2268
2269         offset = tg3_nvram_phys_addr(tp, offset);
2270
2271         if (offset > NVRAM_ADDR_MSK)
2272                 return -EINVAL;
2273
2274         ret = tg3_nvram_lock(tp);
2275         if (ret)
2276                 return ret;
2277
2278         tg3_enable_nvram_access(tp);
2279
2280         tw32(NVRAM_ADDR, offset);
2281         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2282                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2283
2284         if (ret == 0)
2285                 *val = tr32(NVRAM_RDDATA);
2286
2287         tg3_disable_nvram_access(tp);
2288
2289         tg3_nvram_unlock(tp);
2290
2291         return ret;
2292 }
2293
2294 /* Ensures NVRAM data is in bytestream format. */
2295 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2296 {
2297         u32 v;
2298         int res = tg3_nvram_read(tp, offset, &v);
2299         if (!res)
2300                 *val = cpu_to_be32(v);
2301         return res;
2302 }
2303
2304 /* tp->lock is held. */
2305 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2306 {
2307         u32 addr_high, addr_low;
2308         int i;
2309
2310         addr_high = ((tp->dev->dev_addr[0] << 8) |
2311                      tp->dev->dev_addr[1]);
2312         addr_low = ((tp->dev->dev_addr[2] << 24) |
2313                     (tp->dev->dev_addr[3] << 16) |
2314                     (tp->dev->dev_addr[4] <<  8) |
2315                     (tp->dev->dev_addr[5] <<  0));
2316         for (i = 0; i < 4; i++) {
2317                 if (i == 1 && skip_mac_1)
2318                         continue;
2319                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2320                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2321         }
2322
2323         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2324             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2325                 for (i = 0; i < 12; i++) {
2326                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2327                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2328                 }
2329         }
2330
2331         addr_high = (tp->dev->dev_addr[0] +
2332                      tp->dev->dev_addr[1] +
2333                      tp->dev->dev_addr[2] +
2334                      tp->dev->dev_addr[3] +
2335                      tp->dev->dev_addr[4] +
2336                      tp->dev->dev_addr[5]) &
2337                 TX_BACKOFF_SEED_MASK;
2338         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2339 }
2340
2341 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2342 {
2343         u32 misc_host_ctrl;
2344         bool device_should_wake, do_low_power;
2345
2346         /* Make sure register accesses (indirect or otherwise)
2347          * will function correctly.
2348          */
2349         pci_write_config_dword(tp->pdev,
2350                                TG3PCI_MISC_HOST_CTRL,
2351                                tp->misc_host_ctrl);
2352
2353         switch (state) {
2354         case PCI_D0:
2355                 pci_enable_wake(tp->pdev, state, false);
2356                 pci_set_power_state(tp->pdev, PCI_D0);
2357
2358                 /* Switch out of Vaux if it is a NIC */
2359                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2360                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2361
2362                 return 0;
2363
2364         case PCI_D1:
2365         case PCI_D2:
2366         case PCI_D3hot:
2367                 break;
2368
2369         default:
2370                 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2371                         tp->dev->name, state);
2372                 return -EINVAL;
2373         }
2374
2375         /* Restore the CLKREQ setting. */
2376         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2377                 u16 lnkctl;
2378
2379                 pci_read_config_word(tp->pdev,
2380                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2381                                      &lnkctl);
2382                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2383                 pci_write_config_word(tp->pdev,
2384                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2385                                       lnkctl);
2386         }
2387
2388         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2389         tw32(TG3PCI_MISC_HOST_CTRL,
2390              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2391
2392         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2393                              device_may_wakeup(&tp->pdev->dev) &&
2394                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2395
2396         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2397                 do_low_power = false;
2398                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2399                     !tp->link_config.phy_is_low_power) {
2400                         struct phy_device *phydev;
2401                         u32 phyid, advertising;
2402
2403                         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
2404
2405                         tp->link_config.phy_is_low_power = 1;
2406
2407                         tp->link_config.orig_speed = phydev->speed;
2408                         tp->link_config.orig_duplex = phydev->duplex;
2409                         tp->link_config.orig_autoneg = phydev->autoneg;
2410                         tp->link_config.orig_advertising = phydev->advertising;
2411
2412                         advertising = ADVERTISED_TP |
2413                                       ADVERTISED_Pause |
2414                                       ADVERTISED_Autoneg |
2415                                       ADVERTISED_10baseT_Half;
2416
2417                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2418                             device_should_wake) {
2419                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2420                                         advertising |=
2421                                                 ADVERTISED_100baseT_Half |
2422                                                 ADVERTISED_100baseT_Full |
2423                                                 ADVERTISED_10baseT_Full;
2424                                 else
2425                                         advertising |= ADVERTISED_10baseT_Full;
2426                         }
2427
2428                         phydev->advertising = advertising;
2429
2430                         phy_start_aneg(phydev);
2431
2432                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2433                         if (phyid != TG3_PHY_ID_BCMAC131) {
2434                                 phyid &= TG3_PHY_OUI_MASK;
2435                                 if (phyid == TG3_PHY_OUI_1 ||
2436                                     phyid == TG3_PHY_OUI_2 ||
2437                                     phyid == TG3_PHY_OUI_3)
2438                                         do_low_power = true;
2439                         }
2440                 }
2441         } else {
2442                 do_low_power = true;
2443
2444                 if (tp->link_config.phy_is_low_power == 0) {
2445                         tp->link_config.phy_is_low_power = 1;
2446                         tp->link_config.orig_speed = tp->link_config.speed;
2447                         tp->link_config.orig_duplex = tp->link_config.duplex;
2448                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2449                 }
2450
2451                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2452                         tp->link_config.speed = SPEED_10;
2453                         tp->link_config.duplex = DUPLEX_HALF;
2454                         tp->link_config.autoneg = AUTONEG_ENABLE;
2455                         tg3_setup_phy(tp, 0);
2456                 }
2457         }
2458
2459         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2460                 u32 val;
2461
2462                 val = tr32(GRC_VCPU_EXT_CTRL);
2463                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2464         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2465                 int i;
2466                 u32 val;
2467
2468                 for (i = 0; i < 200; i++) {
2469                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2470                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2471                                 break;
2472                         msleep(1);
2473                 }
2474         }
2475         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2476                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2477                                                      WOL_DRV_STATE_SHUTDOWN |
2478                                                      WOL_DRV_WOL |
2479                                                      WOL_SET_MAGIC_PKT);
2480
2481         if (device_should_wake) {
2482                 u32 mac_mode;
2483
2484                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2485                         if (do_low_power) {
2486                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2487                                 udelay(40);
2488                         }
2489
2490                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2491                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2492                         else
2493                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2494
2495                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2496                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2497                             ASIC_REV_5700) {
2498                                 u32 speed = (tp->tg3_flags &
2499                                              TG3_FLAG_WOL_SPEED_100MB) ?
2500                                              SPEED_100 : SPEED_10;
2501                                 if (tg3_5700_link_polarity(tp, speed))
2502                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2503                                 else
2504                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2505                         }
2506                 } else {
2507                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2508                 }
2509
2510                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2511                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2512
2513                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2514                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2515                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2516                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2517                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2518                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2519
2520                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2521                         mac_mode |= tp->mac_mode &
2522                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2523                         if (mac_mode & MAC_MODE_APE_TX_EN)
2524                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2525                 }
2526
2527                 tw32_f(MAC_MODE, mac_mode);
2528                 udelay(100);
2529
2530                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2531                 udelay(10);
2532         }
2533
2534         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2535             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2536              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2537                 u32 base_val;
2538
2539                 base_val = tp->pci_clock_ctrl;
2540                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2541                              CLOCK_CTRL_TXCLK_DISABLE);
2542
2543                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2544                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2545         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2546                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2547                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2548                 /* do nothing */
2549         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2550                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2551                 u32 newbits1, newbits2;
2552
2553                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2554                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2555                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2556                                     CLOCK_CTRL_TXCLK_DISABLE |
2557                                     CLOCK_CTRL_ALTCLK);
2558                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2559                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2560                         newbits1 = CLOCK_CTRL_625_CORE;
2561                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2562                 } else {
2563                         newbits1 = CLOCK_CTRL_ALTCLK;
2564                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2565                 }
2566
2567                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2568                             40);
2569
2570                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2571                             40);
2572
2573                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2574                         u32 newbits3;
2575
2576                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2577                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2578                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2579                                             CLOCK_CTRL_TXCLK_DISABLE |
2580                                             CLOCK_CTRL_44MHZ_CORE);
2581                         } else {
2582                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2583                         }
2584
2585                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2586                                     tp->pci_clock_ctrl | newbits3, 40);
2587                 }
2588         }
2589
2590         if (!(device_should_wake) &&
2591             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2592                 tg3_power_down_phy(tp, do_low_power);
2593
2594         tg3_frob_aux_power(tp);
2595
2596         /* Workaround for unstable PLL clock */
2597         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2598             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2599                 u32 val = tr32(0x7d00);
2600
2601                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2602                 tw32(0x7d00, val);
2603                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2604                         int err;
2605
2606                         err = tg3_nvram_lock(tp);
2607                         tg3_halt_cpu(tp, RX_CPU_BASE);
2608                         if (!err)
2609                                 tg3_nvram_unlock(tp);
2610                 }
2611         }
2612
2613         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2614
2615         if (device_should_wake)
2616                 pci_enable_wake(tp->pdev, state, true);
2617
2618         /* Finally, set the new power state. */
2619         pci_set_power_state(tp->pdev, state);
2620
2621         return 0;
2622 }
2623
2624 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2625 {
2626         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2627         case MII_TG3_AUX_STAT_10HALF:
2628                 *speed = SPEED_10;
2629                 *duplex = DUPLEX_HALF;
2630                 break;
2631
2632         case MII_TG3_AUX_STAT_10FULL:
2633                 *speed = SPEED_10;
2634                 *duplex = DUPLEX_FULL;
2635                 break;
2636
2637         case MII_TG3_AUX_STAT_100HALF:
2638                 *speed = SPEED_100;
2639                 *duplex = DUPLEX_HALF;
2640                 break;
2641
2642         case MII_TG3_AUX_STAT_100FULL:
2643                 *speed = SPEED_100;
2644                 *duplex = DUPLEX_FULL;
2645                 break;
2646
2647         case MII_TG3_AUX_STAT_1000HALF:
2648                 *speed = SPEED_1000;
2649                 *duplex = DUPLEX_HALF;
2650                 break;
2651
2652         case MII_TG3_AUX_STAT_1000FULL:
2653                 *speed = SPEED_1000;
2654                 *duplex = DUPLEX_FULL;
2655                 break;
2656
2657         default:
2658                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2659                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2660                                  SPEED_10;
2661                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2662                                   DUPLEX_HALF;
2663                         break;
2664                 }
2665                 *speed = SPEED_INVALID;
2666                 *duplex = DUPLEX_INVALID;
2667                 break;
2668         }
2669 }
2670
2671 static void tg3_phy_copper_begin(struct tg3 *tp)
2672 {
2673         u32 new_adv;
2674         int i;
2675
2676         if (tp->link_config.phy_is_low_power) {
2677                 /* Entering low power mode.  Disable gigabit and
2678                  * 100baseT advertisements.
2679                  */
2680                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2681
2682                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2683                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2684                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2685                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2686
2687                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2688         } else if (tp->link_config.speed == SPEED_INVALID) {
2689                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2690                         tp->link_config.advertising &=
2691                                 ~(ADVERTISED_1000baseT_Half |
2692                                   ADVERTISED_1000baseT_Full);
2693
2694                 new_adv = ADVERTISE_CSMA;
2695                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2696                         new_adv |= ADVERTISE_10HALF;
2697                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2698                         new_adv |= ADVERTISE_10FULL;
2699                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2700                         new_adv |= ADVERTISE_100HALF;
2701                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2702                         new_adv |= ADVERTISE_100FULL;
2703
2704                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2705
2706                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2707
2708                 if (tp->link_config.advertising &
2709                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2710                         new_adv = 0;
2711                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2712                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2713                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2714                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2715                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2716                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2717                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2718                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2719                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2720                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2721                 } else {
2722                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2723                 }
2724         } else {
2725                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2726                 new_adv |= ADVERTISE_CSMA;
2727
2728                 /* Asking for a specific link mode. */
2729                 if (tp->link_config.speed == SPEED_1000) {
2730                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2731
2732                         if (tp->link_config.duplex == DUPLEX_FULL)
2733                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2734                         else
2735                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2736                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2737                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2738                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2739                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2740                 } else {
2741                         if (tp->link_config.speed == SPEED_100) {
2742                                 if (tp->link_config.duplex == DUPLEX_FULL)
2743                                         new_adv |= ADVERTISE_100FULL;
2744                                 else
2745                                         new_adv |= ADVERTISE_100HALF;
2746                         } else {
2747                                 if (tp->link_config.duplex == DUPLEX_FULL)
2748                                         new_adv |= ADVERTISE_10FULL;
2749                                 else
2750                                         new_adv |= ADVERTISE_10HALF;
2751                         }
2752                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2753
2754                         new_adv = 0;
2755                 }
2756
2757                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2758         }
2759
2760         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2761             tp->link_config.speed != SPEED_INVALID) {
2762                 u32 bmcr, orig_bmcr;
2763
2764                 tp->link_config.active_speed = tp->link_config.speed;
2765                 tp->link_config.active_duplex = tp->link_config.duplex;
2766
2767                 bmcr = 0;
2768                 switch (tp->link_config.speed) {
2769                 default:
2770                 case SPEED_10:
2771                         break;
2772
2773                 case SPEED_100:
2774                         bmcr |= BMCR_SPEED100;
2775                         break;
2776
2777                 case SPEED_1000:
2778                         bmcr |= TG3_BMCR_SPEED1000;
2779                         break;
2780                 }
2781
2782                 if (tp->link_config.duplex == DUPLEX_FULL)
2783                         bmcr |= BMCR_FULLDPLX;
2784
2785                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2786                     (bmcr != orig_bmcr)) {
2787                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2788                         for (i = 0; i < 1500; i++) {
2789                                 u32 tmp;
2790
2791                                 udelay(10);
2792                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2793                                     tg3_readphy(tp, MII_BMSR, &tmp))
2794                                         continue;
2795                                 if (!(tmp & BMSR_LSTATUS)) {
2796                                         udelay(40);
2797                                         break;
2798                                 }
2799                         }
2800                         tg3_writephy(tp, MII_BMCR, bmcr);
2801                         udelay(40);
2802                 }
2803         } else {
2804                 tg3_writephy(tp, MII_BMCR,
2805                              BMCR_ANENABLE | BMCR_ANRESTART);
2806         }
2807 }
2808
2809 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2810 {
2811         int err;
2812
2813         /* Turn off tap power management. */
2814         /* Set Extended packet length bit */
2815         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2816
2817         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2818         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2819
2820         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2821         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2822
2823         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2824         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2825
2826         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2827         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2828
2829         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2830         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2831
2832         udelay(40);
2833
2834         return err;
2835 }
2836
2837 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2838 {
2839         u32 adv_reg, all_mask = 0;
2840
2841         if (mask & ADVERTISED_10baseT_Half)
2842                 all_mask |= ADVERTISE_10HALF;
2843         if (mask & ADVERTISED_10baseT_Full)
2844                 all_mask |= ADVERTISE_10FULL;
2845         if (mask & ADVERTISED_100baseT_Half)
2846                 all_mask |= ADVERTISE_100HALF;
2847         if (mask & ADVERTISED_100baseT_Full)
2848                 all_mask |= ADVERTISE_100FULL;
2849
2850         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2851                 return 0;
2852
2853         if ((adv_reg & all_mask) != all_mask)
2854                 return 0;
2855         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2856                 u32 tg3_ctrl;
2857
2858                 all_mask = 0;
2859                 if (mask & ADVERTISED_1000baseT_Half)
2860                         all_mask |= ADVERTISE_1000HALF;
2861                 if (mask & ADVERTISED_1000baseT_Full)
2862                         all_mask |= ADVERTISE_1000FULL;
2863
2864                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2865                         return 0;
2866
2867                 if ((tg3_ctrl & all_mask) != all_mask)
2868                         return 0;
2869         }
2870         return 1;
2871 }
2872
2873 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2874 {
2875         u32 curadv, reqadv;
2876
2877         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2878                 return 1;
2879
2880         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2881         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2882
2883         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2884                 if (curadv != reqadv)
2885                         return 0;
2886
2887                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2888                         tg3_readphy(tp, MII_LPA, rmtadv);
2889         } else {
2890                 /* Reprogram the advertisement register, even if it
2891                  * does not affect the current link.  If the link
2892                  * gets renegotiated in the future, we can save an
2893                  * additional renegotiation cycle by advertising
2894                  * it correctly in the first place.
2895                  */
2896                 if (curadv != reqadv) {
2897                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2898                                      ADVERTISE_PAUSE_ASYM);
2899                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2900                 }
2901         }
2902
2903         return 1;
2904 }
2905
2906 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2907 {
2908         int current_link_up;
2909         u32 bmsr, dummy;
2910         u32 lcl_adv, rmt_adv;
2911         u16 current_speed;
2912         u8 current_duplex;
2913         int i, err;
2914
2915         tw32(MAC_EVENT, 0);
2916
2917         tw32_f(MAC_STATUS,
2918              (MAC_STATUS_SYNC_CHANGED |
2919               MAC_STATUS_CFG_CHANGED |
2920               MAC_STATUS_MI_COMPLETION |
2921               MAC_STATUS_LNKSTATE_CHANGED));
2922         udelay(40);
2923
2924         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2925                 tw32_f(MAC_MI_MODE,
2926                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2927                 udelay(80);
2928         }
2929
2930         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2931
2932         /* Some third-party PHYs need to be reset on link going
2933          * down.
2934          */
2935         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2936              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2937              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2938             netif_carrier_ok(tp->dev)) {
2939                 tg3_readphy(tp, MII_BMSR, &bmsr);
2940                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2941                     !(bmsr & BMSR_LSTATUS))
2942                         force_reset = 1;
2943         }
2944         if (force_reset)
2945                 tg3_phy_reset(tp);
2946
2947         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2948                 tg3_readphy(tp, MII_BMSR, &bmsr);
2949                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2950                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2951                         bmsr = 0;
2952
2953                 if (!(bmsr & BMSR_LSTATUS)) {
2954                         err = tg3_init_5401phy_dsp(tp);
2955                         if (err)
2956                                 return err;
2957
2958                         tg3_readphy(tp, MII_BMSR, &bmsr);
2959                         for (i = 0; i < 1000; i++) {
2960                                 udelay(10);
2961                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2962                                     (bmsr & BMSR_LSTATUS)) {
2963                                         udelay(40);
2964                                         break;
2965                                 }
2966                         }
2967
2968                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
2969                             !(bmsr & BMSR_LSTATUS) &&
2970                             tp->link_config.active_speed == SPEED_1000) {
2971                                 err = tg3_phy_reset(tp);
2972                                 if (!err)
2973                                         err = tg3_init_5401phy_dsp(tp);
2974                                 if (err)
2975                                         return err;
2976                         }
2977                 }
2978         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2979                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2980                 /* 5701 {A0,B0} CRC bug workaround */
2981                 tg3_writephy(tp, 0x15, 0x0a75);
2982                 tg3_writephy(tp, 0x1c, 0x8c68);
2983                 tg3_writephy(tp, 0x1c, 0x8d68);
2984                 tg3_writephy(tp, 0x1c, 0x8c68);
2985         }
2986
2987         /* Clear pending interrupts... */
2988         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2989         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2990
2991         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
2992                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
2993         else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
2994                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
2995
2996         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2997             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2998                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
2999                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3000                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3001                 else
3002                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3003         }
3004
3005         current_link_up = 0;
3006         current_speed = SPEED_INVALID;
3007         current_duplex = DUPLEX_INVALID;
3008
3009         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3010                 u32 val;
3011
3012                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3013                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3014                 if (!(val & (1 << 10))) {
3015                         val |= (1 << 10);
3016                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3017                         goto relink;
3018                 }
3019         }
3020
3021         bmsr = 0;
3022         for (i = 0; i < 100; i++) {
3023                 tg3_readphy(tp, MII_BMSR, &bmsr);
3024                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3025                     (bmsr & BMSR_LSTATUS))
3026                         break;
3027                 udelay(40);
3028         }
3029
3030         if (bmsr & BMSR_LSTATUS) {
3031                 u32 aux_stat, bmcr;
3032
3033                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3034                 for (i = 0; i < 2000; i++) {
3035                         udelay(10);
3036                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3037                             aux_stat)
3038                                 break;
3039                 }
3040
3041                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3042                                              &current_speed,
3043                                              &current_duplex);
3044
3045                 bmcr = 0;
3046                 for (i = 0; i < 200; i++) {
3047                         tg3_readphy(tp, MII_BMCR, &bmcr);
3048                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3049                                 continue;
3050                         if (bmcr && bmcr != 0x7fff)
3051                                 break;
3052                         udelay(10);
3053                 }
3054
3055                 lcl_adv = 0;
3056                 rmt_adv = 0;
3057
3058                 tp->link_config.active_speed = current_speed;
3059                 tp->link_config.active_duplex = current_duplex;
3060
3061                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3062                         if ((bmcr & BMCR_ANENABLE) &&
3063                             tg3_copper_is_advertising_all(tp,
3064                                                 tp->link_config.advertising)) {
3065                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3066                                                                   &rmt_adv))
3067                                         current_link_up = 1;
3068                         }
3069                 } else {
3070                         if (!(bmcr & BMCR_ANENABLE) &&
3071                             tp->link_config.speed == current_speed &&
3072                             tp->link_config.duplex == current_duplex &&
3073                             tp->link_config.flowctrl ==
3074                             tp->link_config.active_flowctrl) {
3075                                 current_link_up = 1;
3076                         }
3077                 }
3078
3079                 if (current_link_up == 1 &&
3080                     tp->link_config.active_duplex == DUPLEX_FULL)
3081                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3082         }
3083
3084 relink:
3085         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3086                 u32 tmp;
3087
3088                 tg3_phy_copper_begin(tp);
3089
3090                 tg3_readphy(tp, MII_BMSR, &tmp);
3091                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3092                     (tmp & BMSR_LSTATUS))
3093                         current_link_up = 1;
3094         }
3095
3096         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3097         if (current_link_up == 1) {
3098                 if (tp->link_config.active_speed == SPEED_100 ||
3099                     tp->link_config.active_speed == SPEED_10)
3100                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3101                 else
3102                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3103         } else
3104                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3105
3106         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3107         if (tp->link_config.active_duplex == DUPLEX_HALF)
3108                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3109
3110         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3111                 if (current_link_up == 1 &&
3112                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3113                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3114                 else
3115                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3116         }
3117
3118         /* ??? Without this setting Netgear GA302T PHY does not
3119          * ??? send/receive packets...
3120          */
3121         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3122             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3123                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3124                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3125                 udelay(80);
3126         }
3127
3128         tw32_f(MAC_MODE, tp->mac_mode);
3129         udelay(40);
3130
3131         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3132                 /* Polled via timer. */
3133                 tw32_f(MAC_EVENT, 0);
3134         } else {
3135                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3136         }
3137         udelay(40);
3138
3139         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3140             current_link_up == 1 &&
3141             tp->link_config.active_speed == SPEED_1000 &&
3142             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3143              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3144                 udelay(120);
3145                 tw32_f(MAC_STATUS,
3146                      (MAC_STATUS_SYNC_CHANGED |
3147                       MAC_STATUS_CFG_CHANGED));
3148                 udelay(40);
3149                 tg3_write_mem(tp,
3150                               NIC_SRAM_FIRMWARE_MBOX,
3151                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3152         }
3153
3154         /* Prevent send BD corruption. */
3155         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3156                 u16 oldlnkctl, newlnkctl;
3157
3158                 pci_read_config_word(tp->pdev,
3159                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3160                                      &oldlnkctl);
3161                 if (tp->link_config.active_speed == SPEED_100 ||
3162                     tp->link_config.active_speed == SPEED_10)
3163                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3164                 else
3165                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3166                 if (newlnkctl != oldlnkctl)
3167                         pci_write_config_word(tp->pdev,
3168                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3169                                               newlnkctl);
3170         } else if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
3171                 u32 newreg, oldreg = tr32(TG3_PCIE_LNKCTL);
3172                 if (tp->link_config.active_speed == SPEED_100 ||
3173                     tp->link_config.active_speed == SPEED_10)
3174                         newreg = oldreg & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3175                 else
3176                         newreg = oldreg | TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3177                 if (newreg != oldreg)
3178                         tw32(TG3_PCIE_LNKCTL, newreg);
3179         }
3180
3181         if (current_link_up != netif_carrier_ok(tp->dev)) {
3182                 if (current_link_up)
3183                         netif_carrier_on(tp->dev);
3184                 else
3185                         netif_carrier_off(tp->dev);
3186                 tg3_link_report(tp);
3187         }
3188
3189         return 0;
3190 }
3191
3192 struct tg3_fiber_aneginfo {
3193         int state;
3194 #define ANEG_STATE_UNKNOWN              0
3195 #define ANEG_STATE_AN_ENABLE            1
3196 #define ANEG_STATE_RESTART_INIT         2
3197 #define ANEG_STATE_RESTART              3
3198 #define ANEG_STATE_DISABLE_LINK_OK      4
3199 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3200 #define ANEG_STATE_ABILITY_DETECT       6
3201 #define ANEG_STATE_ACK_DETECT_INIT      7
3202 #define ANEG_STATE_ACK_DETECT           8
3203 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3204 #define ANEG_STATE_COMPLETE_ACK         10
3205 #define ANEG_STATE_IDLE_DETECT_INIT     11
3206 #define ANEG_STATE_IDLE_DETECT          12
3207 #define ANEG_STATE_LINK_OK              13
3208 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3209 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3210
3211         u32 flags;
3212 #define MR_AN_ENABLE            0x00000001
3213 #define MR_RESTART_AN           0x00000002
3214 #define MR_AN_COMPLETE          0x00000004
3215 #define MR_PAGE_RX              0x00000008
3216 #define MR_NP_LOADED            0x00000010
3217 #define MR_TOGGLE_TX            0x00000020
3218 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3219 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3220 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3221 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3222 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3223 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3224 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3225 #define MR_TOGGLE_RX            0x00002000
3226 #define MR_NP_RX                0x00004000
3227
3228 #define MR_LINK_OK              0x80000000
3229
3230         unsigned long link_time, cur_time;
3231
3232         u32 ability_match_cfg;
3233         int ability_match_count;
3234
3235         char ability_match, idle_match, ack_match;
3236
3237         u32 txconfig, rxconfig;
3238 #define ANEG_CFG_NP             0x00000080
3239 #define ANEG_CFG_ACK            0x00000040
3240 #define ANEG_CFG_RF2            0x00000020
3241 #define ANEG_CFG_RF1            0x00000010
3242 #define ANEG_CFG_PS2            0x00000001
3243 #define ANEG_CFG_PS1            0x00008000
3244 #define ANEG_CFG_HD             0x00004000
3245 #define ANEG_CFG_FD             0x00002000
3246 #define ANEG_CFG_INVAL          0x00001f06
3247
3248 };
3249 #define ANEG_OK         0
3250 #define ANEG_DONE       1
3251 #define ANEG_TIMER_ENAB 2
3252 #define ANEG_FAILED     -1
3253
3254 #define ANEG_STATE_SETTLE_TIME  10000
3255
3256 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3257                                    struct tg3_fiber_aneginfo *ap)
3258 {
3259         u16 flowctrl;
3260         unsigned long delta;
3261         u32 rx_cfg_reg;
3262         int ret;
3263
3264         if (ap->state == ANEG_STATE_UNKNOWN) {
3265                 ap->rxconfig = 0;
3266                 ap->link_time = 0;
3267                 ap->cur_time = 0;
3268                 ap->ability_match_cfg = 0;
3269                 ap->ability_match_count = 0;
3270                 ap->ability_match = 0;
3271                 ap->idle_match = 0;
3272                 ap->ack_match = 0;
3273         }
3274         ap->cur_time++;
3275
3276         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3277                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3278
3279                 if (rx_cfg_reg != ap->ability_match_cfg) {
3280                         ap->ability_match_cfg = rx_cfg_reg;
3281                         ap->ability_match = 0;
3282                         ap->ability_match_count = 0;
3283                 } else {
3284                         if (++ap->ability_match_count > 1) {
3285                                 ap->ability_match = 1;
3286                                 ap->ability_match_cfg = rx_cfg_reg;
3287                         }
3288                 }
3289                 if (rx_cfg_reg & ANEG_CFG_ACK)
3290                         ap->ack_match = 1;
3291                 else
3292                         ap->ack_match = 0;
3293
3294                 ap->idle_match = 0;
3295         } else {
3296                 ap->idle_match = 1;
3297                 ap->ability_match_cfg = 0;
3298                 ap->ability_match_count = 0;
3299                 ap->ability_match = 0;
3300                 ap->ack_match = 0;
3301
3302                 rx_cfg_reg = 0;
3303         }
3304
3305         ap->rxconfig = rx_cfg_reg;
3306         ret = ANEG_OK;
3307
3308         switch(ap->state) {
3309         case ANEG_STATE_UNKNOWN:
3310                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3311                         ap->state = ANEG_STATE_AN_ENABLE;
3312
3313                 /* fallthru */
3314         case ANEG_STATE_AN_ENABLE:
3315                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3316                 if (ap->flags & MR_AN_ENABLE) {
3317                         ap->link_time = 0;
3318                         ap->cur_time = 0;
3319                         ap->ability_match_cfg = 0;
3320                         ap->ability_match_count = 0;
3321                         ap->ability_match = 0;
3322                         ap->idle_match = 0;
3323                         ap->ack_match = 0;
3324
3325                         ap->state = ANEG_STATE_RESTART_INIT;
3326                 } else {
3327                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3328                 }
3329                 break;
3330
3331         case ANEG_STATE_RESTART_INIT:
3332                 ap->link_time = ap->cur_time;
3333                 ap->flags &= ~(MR_NP_LOADED);
3334                 ap->txconfig = 0;
3335                 tw32(MAC_TX_AUTO_NEG, 0);
3336                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3337                 tw32_f(MAC_MODE, tp->mac_mode);
3338                 udelay(40);
3339
3340                 ret = ANEG_TIMER_ENAB;
3341                 ap->state = ANEG_STATE_RESTART;
3342
3343                 /* fallthru */
3344         case ANEG_STATE_RESTART:
3345                 delta = ap->cur_time - ap->link_time;
3346                 if (delta > ANEG_STATE_SETTLE_TIME) {
3347                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3348                 } else {
3349                         ret = ANEG_TIMER_ENAB;
3350                 }
3351                 break;
3352
3353         case ANEG_STATE_DISABLE_LINK_OK:
3354                 ret = ANEG_DONE;
3355                 break;
3356
3357         case ANEG_STATE_ABILITY_DETECT_INIT:
3358                 ap->flags &= ~(MR_TOGGLE_TX);
3359                 ap->txconfig = ANEG_CFG_FD;
3360                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3361                 if (flowctrl & ADVERTISE_1000XPAUSE)
3362                         ap->txconfig |= ANEG_CFG_PS1;
3363                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3364                         ap->txconfig |= ANEG_CFG_PS2;
3365                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3366                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3367                 tw32_f(MAC_MODE, tp->mac_mode);
3368                 udelay(40);
3369
3370                 ap->state = ANEG_STATE_ABILITY_DETECT;
3371                 break;
3372
3373         case ANEG_STATE_ABILITY_DETECT:
3374                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3375                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3376                 }
3377                 break;
3378
3379         case ANEG_STATE_ACK_DETECT_INIT:
3380                 ap->txconfig |= ANEG_CFG_ACK;
3381                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3382                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3383                 tw32_f(MAC_MODE, tp->mac_mode);
3384                 udelay(40);
3385
3386                 ap->state = ANEG_STATE_ACK_DETECT;
3387
3388                 /* fallthru */
3389         case ANEG_STATE_ACK_DETECT:
3390                 if (ap->ack_match != 0) {
3391                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3392                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3393                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3394                         } else {
3395                                 ap->state = ANEG_STATE_AN_ENABLE;
3396                         }
3397                 } else if (ap->ability_match != 0 &&
3398                            ap->rxconfig == 0) {
3399                         ap->state = ANEG_STATE_AN_ENABLE;
3400                 }
3401                 break;
3402
3403         case ANEG_STATE_COMPLETE_ACK_INIT:
3404                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3405                         ret = ANEG_FAILED;
3406                         break;
3407                 }
3408                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3409                                MR_LP_ADV_HALF_DUPLEX |
3410                                MR_LP_ADV_SYM_PAUSE |
3411                                MR_LP_ADV_ASYM_PAUSE |
3412                                MR_LP_ADV_REMOTE_FAULT1 |
3413                                MR_LP_ADV_REMOTE_FAULT2 |
3414                                MR_LP_ADV_NEXT_PAGE |
3415                                MR_TOGGLE_RX |
3416                                MR_NP_RX);
3417                 if (ap->rxconfig & ANEG_CFG_FD)
3418                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3419                 if (ap->rxconfig & ANEG_CFG_HD)
3420                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3421                 if (ap->rxconfig & ANEG_CFG_PS1)
3422                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3423                 if (ap->rxconfig & ANEG_CFG_PS2)
3424                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3425                 if (ap->rxconfig & ANEG_CFG_RF1)
3426                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3427                 if (ap->rxconfig & ANEG_CFG_RF2)
3428                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3429                 if (ap->rxconfig & ANEG_CFG_NP)
3430                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3431
3432                 ap->link_time = ap->cur_time;
3433
3434                 ap->flags ^= (MR_TOGGLE_TX);
3435                 if (ap->rxconfig & 0x0008)
3436                         ap->flags |= MR_TOGGLE_RX;
3437                 if (ap->rxconfig & ANEG_CFG_NP)
3438                         ap->flags |= MR_NP_RX;
3439                 ap->flags |= MR_PAGE_RX;
3440
3441                 ap->state = ANEG_STATE_COMPLETE_ACK;
3442                 ret = ANEG_TIMER_ENAB;
3443                 break;
3444
3445         case ANEG_STATE_COMPLETE_ACK:
3446                 if (ap->ability_match != 0 &&
3447                     ap->rxconfig == 0) {
3448                         ap->state = ANEG_STATE_AN_ENABLE;
3449                         break;
3450                 }
3451                 delta = ap->cur_time - ap->link_time;
3452                 if (delta > ANEG_STATE_SETTLE_TIME) {
3453                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3454                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3455                         } else {
3456                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3457                                     !(ap->flags & MR_NP_RX)) {
3458                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3459                                 } else {
3460                                         ret = ANEG_FAILED;
3461                                 }
3462                         }
3463                 }
3464                 break;
3465
3466         case ANEG_STATE_IDLE_DETECT_INIT:
3467                 ap->link_time = ap->cur_time;
3468                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3469                 tw32_f(MAC_MODE, tp->mac_mode);
3470                 udelay(40);
3471
3472                 ap->state = ANEG_STATE_IDLE_DETECT;
3473                 ret = ANEG_TIMER_ENAB;
3474                 break;
3475
3476         case ANEG_STATE_IDLE_DETECT:
3477                 if (ap->ability_match != 0 &&
3478                     ap->rxconfig == 0) {
3479                         ap->state = ANEG_STATE_AN_ENABLE;
3480                         break;
3481                 }
3482                 delta = ap->cur_time - ap->link_time;
3483                 if (delta > ANEG_STATE_SETTLE_TIME) {
3484                         /* XXX another gem from the Broadcom driver :( */
3485                         ap->state = ANEG_STATE_LINK_OK;
3486                 }
3487                 break;
3488
3489         case ANEG_STATE_LINK_OK:
3490                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3491                 ret = ANEG_DONE;
3492                 break;
3493
3494         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3495                 /* ??? unimplemented */
3496                 break;
3497
3498         case ANEG_STATE_NEXT_PAGE_WAIT:
3499                 /* ??? unimplemented */
3500                 break;
3501
3502         default:
3503                 ret = ANEG_FAILED;
3504                 break;
3505         }
3506
3507         return ret;
3508 }
3509
3510 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3511 {
3512         int res = 0;
3513         struct tg3_fiber_aneginfo aninfo;
3514         int status = ANEG_FAILED;
3515         unsigned int tick;
3516         u32 tmp;
3517
3518         tw32_f(MAC_TX_AUTO_NEG, 0);
3519
3520         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3521         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3522         udelay(40);
3523
3524         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3525         udelay(40);
3526
3527         memset(&aninfo, 0, sizeof(aninfo));
3528         aninfo.flags |= MR_AN_ENABLE;
3529         aninfo.state = ANEG_STATE_UNKNOWN;
3530         aninfo.cur_time = 0;
3531         tick = 0;
3532         while (++tick < 195000) {
3533                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3534                 if (status == ANEG_DONE || status == ANEG_FAILED)
3535                         break;
3536
3537                 udelay(1);
3538         }
3539
3540         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3541         tw32_f(MAC_MODE, tp->mac_mode);
3542         udelay(40);
3543
3544         *txflags = aninfo.txconfig;
3545         *rxflags = aninfo.flags;
3546
3547         if (status == ANEG_DONE &&
3548             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3549                              MR_LP_ADV_FULL_DUPLEX)))
3550                 res = 1;
3551
3552         return res;
3553 }
3554
3555 static void tg3_init_bcm8002(struct tg3 *tp)
3556 {
3557         u32 mac_status = tr32(MAC_STATUS);
3558         int i;
3559
3560         /* Reset when initting first time or we have a link. */
3561         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3562             !(mac_status & MAC_STATUS_PCS_SYNCED))
3563                 return;
3564
3565         /* Set PLL lock range. */
3566         tg3_writephy(tp, 0x16, 0x8007);
3567
3568         /* SW reset */
3569         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3570
3571         /* Wait for reset to complete. */
3572         /* XXX schedule_timeout() ... */
3573         for (i = 0; i < 500; i++)
3574                 udelay(10);
3575
3576         /* Config mode; select PMA/Ch 1 regs. */
3577         tg3_writephy(tp, 0x10, 0x8411);
3578
3579         /* Enable auto-lock and comdet, select txclk for tx. */
3580         tg3_writephy(tp, 0x11, 0x0a10);
3581
3582         tg3_writephy(tp, 0x18, 0x00a0);
3583         tg3_writephy(tp, 0x16, 0x41ff);
3584
3585         /* Assert and deassert POR. */
3586         tg3_writephy(tp, 0x13, 0x0400);
3587         udelay(40);
3588         tg3_writephy(tp, 0x13, 0x0000);
3589
3590         tg3_writephy(tp, 0x11, 0x0a50);
3591         udelay(40);
3592         tg3_writephy(tp, 0x11, 0x0a10);
3593
3594         /* Wait for signal to stabilize */
3595         /* XXX schedule_timeout() ... */
3596         for (i = 0; i < 15000; i++)
3597                 udelay(10);
3598
3599         /* Deselect the channel register so we can read the PHYID
3600          * later.
3601          */
3602         tg3_writephy(tp, 0x10, 0x8011);
3603 }
3604
3605 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3606 {
3607         u16 flowctrl;
3608         u32 sg_dig_ctrl, sg_dig_status;
3609         u32 serdes_cfg, expected_sg_dig_ctrl;
3610         int workaround, port_a;
3611         int current_link_up;
3612
3613         serdes_cfg = 0;
3614         expected_sg_dig_ctrl = 0;
3615         workaround = 0;
3616         port_a = 1;
3617         current_link_up = 0;
3618
3619         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3620             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3621                 workaround = 1;
3622                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3623                         port_a = 0;
3624
3625                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3626                 /* preserve bits 20-23 for voltage regulator */
3627                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3628         }
3629
3630         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3631
3632         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3633                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3634                         if (workaround) {
3635                                 u32 val = serdes_cfg;
3636
3637                                 if (port_a)
3638                                         val |= 0xc010000;
3639                                 else
3640                                         val |= 0x4010000;
3641                                 tw32_f(MAC_SERDES_CFG, val);
3642                         }
3643
3644                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3645                 }
3646                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3647                         tg3_setup_flow_control(tp, 0, 0);
3648                         current_link_up = 1;
3649                 }
3650                 goto out;
3651         }
3652
3653         /* Want auto-negotiation.  */
3654         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3655
3656         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3657         if (flowctrl & ADVERTISE_1000XPAUSE)
3658                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3659         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3660                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3661
3662         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3663                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3664                     tp->serdes_counter &&
3665                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3666                                     MAC_STATUS_RCVD_CFG)) ==
3667                      MAC_STATUS_PCS_SYNCED)) {
3668                         tp->serdes_counter--;
3669                         current_link_up = 1;
3670                         goto out;
3671                 }
3672 restart_autoneg:
3673                 if (workaround)
3674                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3675                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3676                 udelay(5);
3677                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3678
3679                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3680                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3681         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3682                                  MAC_STATUS_SIGNAL_DET)) {
3683                 sg_dig_status = tr32(SG_DIG_STATUS);
3684                 mac_status = tr32(MAC_STATUS);
3685
3686                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3687                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3688                         u32 local_adv = 0, remote_adv = 0;
3689
3690                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3691                                 local_adv |= ADVERTISE_1000XPAUSE;
3692                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3693                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3694
3695                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3696                                 remote_adv |= LPA_1000XPAUSE;
3697                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3698                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3699
3700                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3701                         current_link_up = 1;
3702                         tp->serdes_counter = 0;
3703                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3704                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3705                         if (tp->serdes_counter)
3706                                 tp->serdes_counter--;
3707                         else {
3708                                 if (workaround) {
3709                                         u32 val = serdes_cfg;
3710
3711                                         if (port_a)
3712                                                 val |= 0xc010000;
3713                                         else
3714                                                 val |= 0x4010000;
3715
3716                                         tw32_f(MAC_SERDES_CFG, val);
3717                                 }
3718
3719                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3720                                 udelay(40);
3721
3722                                 /* Link parallel detection - link is up */
3723                                 /* only if we have PCS_SYNC and not */
3724                                 /* receiving config code words */
3725                                 mac_status = tr32(MAC_STATUS);
3726                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3727                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3728                                         tg3_setup_flow_control(tp, 0, 0);
3729                                         current_link_up = 1;
3730                                         tp->tg3_flags2 |=
3731                                                 TG3_FLG2_PARALLEL_DETECT;
3732                                         tp->serdes_counter =
3733                                                 SERDES_PARALLEL_DET_TIMEOUT;
3734                                 } else
3735                                         goto restart_autoneg;
3736                         }
3737                 }
3738         } else {
3739                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3740                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3741         }
3742
3743 out:
3744         return current_link_up;
3745 }
3746
3747 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3748 {
3749         int current_link_up = 0;
3750
3751         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3752                 goto out;
3753
3754         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3755                 u32 txflags, rxflags;
3756                 int i;
3757
3758                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3759                         u32 local_adv = 0, remote_adv = 0;
3760
3761                         if (txflags & ANEG_CFG_PS1)
3762                                 local_adv |= ADVERTISE_1000XPAUSE;
3763                         if (txflags & ANEG_CFG_PS2)
3764                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3765
3766                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3767                                 remote_adv |= LPA_1000XPAUSE;
3768                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3769                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3770
3771                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3772
3773                         current_link_up = 1;
3774                 }
3775                 for (i = 0; i < 30; i++) {
3776                         udelay(20);
3777                         tw32_f(MAC_STATUS,
3778                                (MAC_STATUS_SYNC_CHANGED |
3779                                 MAC_STATUS_CFG_CHANGED));
3780                         udelay(40);
3781                         if ((tr32(MAC_STATUS) &
3782                              (MAC_STATUS_SYNC_CHANGED |
3783                               MAC_STATUS_CFG_CHANGED)) == 0)
3784                                 break;
3785                 }
3786
3787                 mac_status = tr32(MAC_STATUS);
3788                 if (current_link_up == 0 &&
3789                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3790                     !(mac_status & MAC_STATUS_RCVD_CFG))
3791                         current_link_up = 1;
3792         } else {
3793                 tg3_setup_flow_control(tp, 0, 0);
3794
3795                 /* Forcing 1000FD link up. */
3796                 current_link_up = 1;
3797
3798                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3799                 udelay(40);
3800
3801                 tw32_f(MAC_MODE, tp->mac_mode);
3802                 udelay(40);
3803         }
3804
3805 out:
3806         return current_link_up;
3807 }
3808
3809 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3810 {
3811         u32 orig_pause_cfg;
3812         u16 orig_active_speed;
3813         u8 orig_active_duplex;
3814         u32 mac_status;
3815         int current_link_up;
3816         int i;
3817
3818         orig_pause_cfg = tp->link_config.active_flowctrl;
3819         orig_active_speed = tp->link_config.active_speed;
3820         orig_active_duplex = tp->link_config.active_duplex;
3821
3822         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3823             netif_carrier_ok(tp->dev) &&
3824             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3825                 mac_status = tr32(MAC_STATUS);
3826                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3827                                MAC_STATUS_SIGNAL_DET |
3828                                MAC_STATUS_CFG_CHANGED |
3829                                MAC_STATUS_RCVD_CFG);
3830                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3831                                    MAC_STATUS_SIGNAL_DET)) {
3832                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3833                                             MAC_STATUS_CFG_CHANGED));
3834                         return 0;
3835                 }
3836         }
3837
3838         tw32_f(MAC_TX_AUTO_NEG, 0);
3839
3840         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3841         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3842         tw32_f(MAC_MODE, tp->mac_mode);
3843         udelay(40);
3844
3845         if (tp->phy_id == PHY_ID_BCM8002)
3846                 tg3_init_bcm8002(tp);
3847
3848         /* Enable link change event even when serdes polling.  */
3849         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3850         udelay(40);
3851
3852         current_link_up = 0;
3853         mac_status = tr32(MAC_STATUS);
3854
3855         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3856                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3857         else
3858                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3859
3860         tp->hw_status->status =
3861                 (SD_STATUS_UPDATED |
3862                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3863
3864         for (i = 0; i < 100; i++) {
3865                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3866                                     MAC_STATUS_CFG_CHANGED));
3867                 udelay(5);
3868                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3869                                          MAC_STATUS_CFG_CHANGED |
3870                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3871                         break;
3872         }
3873
3874         mac_status = tr32(MAC_STATUS);
3875         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3876                 current_link_up = 0;
3877                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3878                     tp->serdes_counter == 0) {
3879                         tw32_f(MAC_MODE, (tp->mac_mode |
3880                                           MAC_MODE_SEND_CONFIGS));
3881                         udelay(1);
3882                         tw32_f(MAC_MODE, tp->mac_mode);
3883                 }
3884         }
3885
3886         if (current_link_up == 1) {
3887                 tp->link_config.active_speed = SPEED_1000;
3888                 tp->link_config.active_duplex = DUPLEX_FULL;
3889                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3890                                     LED_CTRL_LNKLED_OVERRIDE |
3891                                     LED_CTRL_1000MBPS_ON));
3892         } else {
3893                 tp->link_config.active_speed = SPEED_INVALID;
3894                 tp->link_config.active_duplex = DUPLEX_INVALID;
3895                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3896                                     LED_CTRL_LNKLED_OVERRIDE |
3897                                     LED_CTRL_TRAFFIC_OVERRIDE));
3898         }
3899
3900         if (current_link_up != netif_carrier_ok(tp->dev)) {
3901                 if (current_link_up)
3902                         netif_carrier_on(tp->dev);
3903                 else
3904                         netif_carrier_off(tp->dev);
3905                 tg3_link_report(tp);
3906         } else {
3907                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
3908                 if (orig_pause_cfg != now_pause_cfg ||
3909                     orig_active_speed != tp->link_config.active_speed ||
3910                     orig_active_duplex != tp->link_config.active_duplex)
3911                         tg3_link_report(tp);
3912         }
3913
3914         return 0;
3915 }
3916
3917 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3918 {
3919         int current_link_up, err = 0;
3920         u32 bmsr, bmcr;
3921         u16 current_speed;
3922         u8 current_duplex;
3923         u32 local_adv, remote_adv;
3924
3925         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3926         tw32_f(MAC_MODE, tp->mac_mode);
3927         udelay(40);
3928
3929         tw32(MAC_EVENT, 0);
3930
3931         tw32_f(MAC_STATUS,
3932              (MAC_STATUS_SYNC_CHANGED |
3933               MAC_STATUS_CFG_CHANGED |
3934               MAC_STATUS_MI_COMPLETION |
3935               MAC_STATUS_LNKSTATE_CHANGED));
3936         udelay(40);
3937
3938         if (force_reset)
3939                 tg3_phy_reset(tp);
3940
3941         current_link_up = 0;
3942         current_speed = SPEED_INVALID;
3943         current_duplex = DUPLEX_INVALID;
3944
3945         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3946         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3947         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3948                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3949                         bmsr |= BMSR_LSTATUS;
3950                 else
3951                         bmsr &= ~BMSR_LSTATUS;
3952         }
3953
3954         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3955
3956         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
3957             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3958                 /* do nothing, just check for link up at the end */
3959         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3960                 u32 adv, new_adv;
3961
3962                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3963                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
3964                                   ADVERTISE_1000XPAUSE |
3965                                   ADVERTISE_1000XPSE_ASYM |
3966                                   ADVERTISE_SLCT);
3967
3968                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3969
3970                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
3971                         new_adv |= ADVERTISE_1000XHALF;
3972                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
3973                         new_adv |= ADVERTISE_1000XFULL;
3974
3975                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
3976                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
3977                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
3978                         tg3_writephy(tp, MII_BMCR, bmcr);
3979
3980                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3981                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
3982                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3983
3984                         return err;
3985                 }
3986         } else {
3987                 u32 new_bmcr;
3988
3989                 bmcr &= ~BMCR_SPEED1000;
3990                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
3991
3992                 if (tp->link_config.duplex == DUPLEX_FULL)
3993                         new_bmcr |= BMCR_FULLDPLX;
3994
3995                 if (new_bmcr != bmcr) {
3996                         /* BMCR_SPEED1000 is a reserved bit that needs
3997                          * to be set on write.
3998                          */
3999                         new_bmcr |= BMCR_SPEED1000;
4000
4001                         /* Force a linkdown */
4002                         if (netif_carrier_ok(tp->dev)) {
4003                                 u32 adv;
4004
4005                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4006                                 adv &= ~(ADVERTISE_1000XFULL |
4007                                          ADVERTISE_1000XHALF |
4008                                          ADVERTISE_SLCT);
4009                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4010                                 tg3_writephy(tp, MII_BMCR, bmcr |
4011                                                            BMCR_ANRESTART |
4012                                                            BMCR_ANENABLE);
4013                                 udelay(10);
4014                                 netif_carrier_off(tp->dev);
4015                         }
4016                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4017                         bmcr = new_bmcr;
4018                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4019                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4020                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4021                             ASIC_REV_5714) {
4022                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4023                                         bmsr |= BMSR_LSTATUS;
4024                                 else
4025                                         bmsr &= ~BMSR_LSTATUS;
4026                         }
4027                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4028                 }
4029         }
4030
4031         if (bmsr & BMSR_LSTATUS) {
4032                 current_speed = SPEED_1000;
4033                 current_link_up = 1;
4034                 if (bmcr & BMCR_FULLDPLX)
4035                         current_duplex = DUPLEX_FULL;
4036                 else
4037                         current_duplex = DUPLEX_HALF;
4038
4039                 local_adv = 0;
4040                 remote_adv = 0;
4041
4042                 if (bmcr & BMCR_ANENABLE) {
4043                         u32 common;
4044
4045                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4046                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4047                         common = local_adv & remote_adv;
4048                         if (common & (ADVERTISE_1000XHALF |
4049                                       ADVERTISE_1000XFULL)) {
4050                                 if (common & ADVERTISE_1000XFULL)
4051                                         current_duplex = DUPLEX_FULL;
4052                                 else
4053                                         current_duplex = DUPLEX_HALF;
4054                         }
4055                         else
4056                                 current_link_up = 0;
4057                 }
4058         }
4059
4060         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4061                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4062
4063         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4064         if (tp->link_config.active_duplex == DUPLEX_HALF)
4065                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4066
4067         tw32_f(MAC_MODE, tp->mac_mode);
4068         udelay(40);
4069
4070         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4071
4072         tp->link_config.active_speed = current_speed;
4073         tp->link_config.active_duplex = current_duplex;
4074
4075         if (current_link_up != netif_carrier_ok(tp->dev)) {
4076                 if (current_link_up)
4077                         netif_carrier_on(tp->dev);
4078                 else {
4079                         netif_carrier_off(tp->dev);
4080                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4081                 }
4082                 tg3_link_report(tp);
4083         }
4084         return err;
4085 }
4086
4087 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4088 {
4089         if (tp->serdes_counter) {
4090                 /* Give autoneg time to complete. */
4091                 tp->serdes_counter--;
4092                 return;
4093         }
4094         if (!netif_carrier_ok(tp->dev) &&
4095             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4096                 u32 bmcr;
4097
4098                 tg3_readphy(tp, MII_BMCR, &bmcr);
4099                 if (bmcr & BMCR_ANENABLE) {
4100                         u32 phy1, phy2;
4101
4102                         /* Select shadow register 0x1f */
4103                         tg3_writephy(tp, 0x1c, 0x7c00);
4104                         tg3_readphy(tp, 0x1c, &phy1);
4105
4106                         /* Select expansion interrupt status register */
4107                         tg3_writephy(tp, 0x17, 0x0f01);
4108                         tg3_readphy(tp, 0x15, &phy2);
4109                         tg3_readphy(tp, 0x15, &phy2);
4110
4111                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4112                                 /* We have signal detect and not receiving
4113                                  * config code words, link is up by parallel
4114                                  * detection.
4115                                  */
4116
4117                                 bmcr &= ~BMCR_ANENABLE;
4118                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4119                                 tg3_writephy(tp, MII_BMCR, bmcr);
4120                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4121                         }
4122                 }
4123         }
4124         else if (netif_carrier_ok(tp->dev) &&
4125                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4126                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4127                 u32 phy2;
4128
4129                 /* Select expansion interrupt status register */
4130                 tg3_writephy(tp, 0x17, 0x0f01);
4131                 tg3_readphy(tp, 0x15, &phy2);
4132                 if (phy2 & 0x20) {
4133                         u32 bmcr;
4134
4135                         /* Config code words received, turn on autoneg. */
4136                         tg3_readphy(tp, MII_BMCR, &bmcr);
4137                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4138
4139                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4140
4141                 }
4142         }
4143 }
4144
4145 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4146 {
4147         int err;
4148
4149         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4150                 err = tg3_setup_fiber_phy(tp, force_reset);
4151         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4152                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4153         } else {
4154                 err = tg3_setup_copper_phy(tp, force_reset);
4155         }
4156
4157         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4158                 u32 val, scale;
4159
4160                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4161                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4162                         scale = 65;
4163                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4164                         scale = 6;
4165                 else
4166                         scale = 12;
4167
4168                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4169                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4170                 tw32(GRC_MISC_CFG, val);
4171         }
4172
4173         if (tp->link_config.active_speed == SPEED_1000 &&
4174             tp->link_config.active_duplex == DUPLEX_HALF)
4175                 tw32(MAC_TX_LENGTHS,
4176                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4177                       (6 << TX_LENGTHS_IPG_SHIFT) |
4178                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4179         else
4180                 tw32(MAC_TX_LENGTHS,
4181                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4182                       (6 << TX_LENGTHS_IPG_SHIFT) |
4183                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4184
4185         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4186                 if (netif_carrier_ok(tp->dev)) {
4187                         tw32(HOSTCC_STAT_COAL_TICKS,
4188                              tp->coal.stats_block_coalesce_usecs);
4189                 } else {
4190                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4191                 }
4192         }
4193
4194         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4195                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4196                 if (!netif_carrier_ok(tp->dev))
4197                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4198                               tp->pwrmgmt_thresh;
4199                 else
4200                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4201                 tw32(PCIE_PWR_MGMT_THRESH, val);
4202         }
4203
4204         return err;
4205 }
4206
4207 /* This is called whenever we suspect that the system chipset is re-
4208  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4209  * is bogus tx completions. We try to recover by setting the
4210  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4211  * in the workqueue.
4212  */
4213 static void tg3_tx_recover(struct tg3 *tp)
4214 {
4215         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4216                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4217
4218         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4219                "mapped I/O cycles to the network device, attempting to "
4220                "recover. Please report the problem to the driver maintainer "
4221                "and include system chipset information.\n", tp->dev->name);
4222
4223         spin_lock(&tp->lock);
4224         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4225         spin_unlock(&tp->lock);
4226 }
4227
4228 static inline u32 tg3_tx_avail(struct tg3 *tp)
4229 {
4230         smp_mb();
4231         return (tp->tx_pending -
4232                 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
4233 }
4234
4235 /* Tigon3 never reports partial packet sends.  So we do not
4236  * need special logic to handle SKBs that have not had all
4237  * of their frags sent yet, like SunGEM does.
4238  */
4239 static void tg3_tx(struct tg3 *tp)
4240 {
4241         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
4242         u32 sw_idx = tp->tx_cons;
4243
4244         while (sw_idx != hw_idx) {
4245                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
4246                 struct sk_buff *skb = ri->skb;
4247                 int i, tx_bug = 0;
4248
4249                 if (unlikely(skb == NULL)) {
4250                         tg3_tx_recover(tp);
4251                         return;
4252                 }
4253
4254                 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
4255
4256                 ri->skb = NULL;
4257
4258                 sw_idx = NEXT_TX(sw_idx);
4259
4260                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4261                         ri = &tp->tx_buffers[sw_idx];
4262                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4263                                 tx_bug = 1;
4264                         sw_idx = NEXT_TX(sw_idx);
4265                 }
4266
4267                 dev_kfree_skb(skb);
4268
4269                 if (unlikely(tx_bug)) {
4270                         tg3_tx_recover(tp);
4271                         return;
4272                 }
4273         }
4274
4275         tp->tx_cons = sw_idx;
4276
4277         /* Need to make the tx_cons update visible to tg3_start_xmit()
4278          * before checking for netif_queue_stopped().  Without the
4279          * memory barrier, there is a small possibility that tg3_start_xmit()
4280          * will miss it and cause the queue to be stopped forever.
4281          */
4282         smp_mb();
4283
4284         if (unlikely(netif_queue_stopped(tp->dev) &&
4285                      (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
4286                 netif_tx_lock(tp->dev);
4287                 if (netif_queue_stopped(tp->dev) &&
4288                     (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
4289                         netif_wake_queue(tp->dev);
4290                 netif_tx_unlock(tp->dev);
4291         }
4292 }
4293
4294 /* Returns size of skb allocated or < 0 on error.
4295  *
4296  * We only need to fill in the address because the other members
4297  * of the RX descriptor are invariant, see tg3_init_rings.
4298  *
4299  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4300  * posting buffers we only dirty the first cache line of the RX
4301  * descriptor (containing the address).  Whereas for the RX status
4302  * buffers the cpu only reads the last cacheline of the RX descriptor
4303  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4304  */
4305 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
4306                             int src_idx, u32 dest_idx_unmasked)
4307 {
4308         struct tg3_rx_buffer_desc *desc;
4309         struct ring_info *map, *src_map;
4310         struct sk_buff *skb;
4311         dma_addr_t mapping;
4312         int skb_size, dest_idx;
4313
4314         src_map = NULL;
4315         switch (opaque_key) {
4316         case RXD_OPAQUE_RING_STD:
4317                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4318                 desc = &tp->rx_std[dest_idx];
4319                 map = &tp->rx_std_buffers[dest_idx];
4320                 if (src_idx >= 0)
4321                         src_map = &tp->rx_std_buffers[src_idx];
4322                 skb_size = tp->rx_pkt_buf_sz;
4323                 break;
4324
4325         case RXD_OPAQUE_RING_JUMBO:
4326                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4327                 desc = &tp->rx_jumbo[dest_idx];
4328                 map = &tp->rx_jumbo_buffers[dest_idx];
4329                 if (src_idx >= 0)
4330                         src_map = &tp->rx_jumbo_buffers[src_idx];
4331                 skb_size = RX_JUMBO_PKT_BUF_SZ;
4332                 break;
4333
4334         default:
4335                 return -EINVAL;
4336         }
4337
4338         /* Do not overwrite any of the map or rp information
4339          * until we are sure we can commit to a new buffer.
4340          *
4341          * Callers depend upon this behavior and assume that
4342          * we leave everything unchanged if we fail.
4343          */
4344         skb = netdev_alloc_skb(tp->dev, skb_size);
4345         if (skb == NULL)
4346                 return -ENOMEM;
4347
4348         skb_reserve(skb, tp->rx_offset);
4349
4350         mapping = pci_map_single(tp->pdev, skb->data,
4351                                  skb_size - tp->rx_offset,
4352                                  PCI_DMA_FROMDEVICE);
4353
4354         map->skb = skb;
4355         pci_unmap_addr_set(map, mapping, mapping);
4356
4357         if (src_map != NULL)
4358                 src_map->skb = NULL;
4359
4360         desc->addr_hi = ((u64)mapping >> 32);
4361         desc->addr_lo = ((u64)mapping & 0xffffffff);
4362
4363         return skb_size;
4364 }
4365
4366 /* We only need to move over in the address because the other
4367  * members of the RX descriptor are invariant.  See notes above
4368  * tg3_alloc_rx_skb for full details.
4369  */
4370 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
4371                            int src_idx, u32 dest_idx_unmasked)
4372 {
4373         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4374         struct ring_info *src_map, *dest_map;
4375         int dest_idx;
4376
4377         switch (opaque_key) {
4378         case RXD_OPAQUE_RING_STD:
4379                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4380                 dest_desc = &tp->rx_std[dest_idx];
4381                 dest_map = &tp->rx_std_buffers[dest_idx];
4382                 src_desc = &tp->rx_std[src_idx];
4383                 src_map = &tp->rx_std_buffers[src_idx];
4384                 break;
4385
4386         case RXD_OPAQUE_RING_JUMBO:
4387                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4388                 dest_desc = &tp->rx_jumbo[dest_idx];
4389                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
4390                 src_desc = &tp->rx_jumbo[src_idx];
4391                 src_map = &tp->rx_jumbo_buffers[src_idx];
4392                 break;
4393
4394         default:
4395                 return;
4396         }
4397
4398         dest_map->skb = src_map->skb;
4399         pci_unmap_addr_set(dest_map, mapping,
4400                            pci_unmap_addr(src_map, mapping));
4401         dest_desc->addr_hi = src_desc->addr_hi;
4402         dest_desc->addr_lo = src_desc->addr_lo;
4403
4404         src_map->skb = NULL;
4405 }
4406
4407 #if TG3_VLAN_TAG_USED
4408 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
4409 {
4410         return vlan_gro_receive(&tp->napi, tp->vlgrp, vlan_tag, skb);
4411 }
4412 #endif
4413
4414 /* The RX ring scheme is composed of multiple rings which post fresh
4415  * buffers to the chip, and one special ring the chip uses to report
4416  * status back to the host.
4417  *
4418  * The special ring reports the status of received packets to the
4419  * host.  The chip does not write into the original descriptor the
4420  * RX buffer was obtained from.  The chip simply takes the original
4421  * descriptor as provided by the host, updates the status and length
4422  * field, then writes this into the next status ring entry.
4423  *
4424  * Each ring the host uses to post buffers to the chip is described
4425  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4426  * it is first placed into the on-chip ram.  When the packet's length
4427  * is known, it walks down the TG3_BDINFO entries to select the ring.
4428  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4429  * which is within the range of the new packet's length is chosen.
4430  *
4431  * The "separate ring for rx status" scheme may sound queer, but it makes
4432  * sense from a cache coherency perspective.  If only the host writes
4433  * to the buffer post rings, and only the chip writes to the rx status
4434  * rings, then cache lines never move beyond shared-modified state.
4435  * If both the host and chip were to write into the same ring, cache line
4436  * eviction could occur since both entities want it in an exclusive state.
4437  */
4438 static int tg3_rx(struct tg3 *tp, int budget)
4439 {
4440         u32 work_mask, rx_std_posted = 0;
4441         u32 sw_idx = tp->rx_rcb_ptr;
4442         u16 hw_idx;
4443         int received;
4444
4445         hw_idx = tp->hw_status->idx[0].rx_producer;
4446         /*
4447          * We need to order the read of hw_idx and the read of
4448          * the opaque cookie.
4449          */
4450         rmb();
4451         work_mask = 0;
4452         received = 0;
4453         while (sw_idx != hw_idx && budget > 0) {
4454                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
4455                 unsigned int len;
4456                 struct sk_buff *skb;
4457                 dma_addr_t dma_addr;
4458                 u32 opaque_key, desc_idx, *post_ptr;
4459
4460                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4461                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4462                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4463                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
4464                                                   mapping);
4465                         skb = tp->rx_std_buffers[desc_idx].skb;
4466                         post_ptr = &tp->rx_std_ptr;
4467                         rx_std_posted++;
4468                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4469                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
4470                                                   mapping);
4471                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
4472                         post_ptr = &tp->rx_jumbo_ptr;
4473                 }
4474                 else {
4475                         goto next_pkt_nopost;
4476                 }
4477
4478                 work_mask |= opaque_key;
4479
4480                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4481                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4482                 drop_it:
4483                         tg3_recycle_rx(tp, opaque_key,
4484                                        desc_idx, *post_ptr);
4485                 drop_it_no_recycle:
4486                         /* Other statistics kept track of by card. */
4487                         tp->net_stats.rx_dropped++;
4488                         goto next_pkt;
4489                 }
4490
4491                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4492                       ETH_FCS_LEN;
4493
4494                 if (len > RX_COPY_THRESHOLD
4495                         && tp->rx_offset == NET_IP_ALIGN
4496                         /* rx_offset will likely not equal NET_IP_ALIGN
4497                          * if this is a 5701 card running in PCI-X mode
4498                          * [see tg3_get_invariants()]
4499                          */
4500                 ) {
4501                         int skb_size;
4502
4503                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
4504                                                     desc_idx, *post_ptr);
4505                         if (skb_size < 0)
4506                                 goto drop_it;
4507
4508                         pci_unmap_single(tp->pdev, dma_addr,
4509                                          skb_size - tp->rx_offset,
4510                                          PCI_DMA_FROMDEVICE);
4511
4512                         skb_put(skb, len);
4513                 } else {
4514                         struct sk_buff *copy_skb;
4515
4516                         tg3_recycle_rx(tp, opaque_key,
4517                                        desc_idx, *post_ptr);
4518
4519                         copy_skb = netdev_alloc_skb(tp->dev,
4520                                                     len + TG3_RAW_IP_ALIGN);
4521                         if (copy_skb == NULL)
4522                                 goto drop_it_no_recycle;
4523
4524                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4525                         skb_put(copy_skb, len);
4526                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4527                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4528                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4529
4530                         /* We'll reuse the original ring buffer. */
4531                         skb = copy_skb;
4532                 }
4533
4534                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4535                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4536                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4537                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4538                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4539                 else
4540                         skb->ip_summed = CHECKSUM_NONE;
4541
4542                 skb->protocol = eth_type_trans(skb, tp->dev);
4543
4544                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4545                     skb->protocol != htons(ETH_P_8021Q)) {
4546                         dev_kfree_skb(skb);
4547                         goto next_pkt;
4548                 }
4549
4550 #if TG3_VLAN_TAG_USED
4551                 if (tp->vlgrp != NULL &&
4552                     desc->type_flags & RXD_FLAG_VLAN) {
4553                         tg3_vlan_rx(tp, skb,
4554                                     desc->err_vlan & RXD_VLAN_MASK);
4555                 } else
4556 #endif
4557                         napi_gro_receive(&tp->napi, skb);
4558
4559                 received++;
4560                 budget--;
4561
4562 next_pkt:
4563                 (*post_ptr)++;
4564
4565                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4566                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4567
4568                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4569                                      TG3_64BIT_REG_LOW, idx);
4570                         work_mask &= ~RXD_OPAQUE_RING_STD;
4571                         rx_std_posted = 0;
4572                 }
4573 next_pkt_nopost:
4574                 sw_idx++;
4575                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4576
4577                 /* Refresh hw_idx to see if there is new work */
4578                 if (sw_idx == hw_idx) {
4579                         hw_idx = tp->hw_status->idx[0].rx_producer;
4580                         rmb();
4581                 }
4582         }
4583
4584         /* ACK the status ring. */
4585         tp->rx_rcb_ptr = sw_idx;
4586         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
4587
4588         /* Refill RX ring(s). */
4589         if (work_mask & RXD_OPAQUE_RING_STD) {
4590                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
4591                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4592                              sw_idx);
4593         }
4594         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4595                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
4596                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4597                              sw_idx);
4598         }
4599         mmiowb();
4600
4601         return received;
4602 }
4603
4604 static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
4605 {
4606         struct tg3_hw_status *sblk = tp->hw_status;
4607
4608         /* handle link change and other phy events */
4609         if (!(tp->tg3_flags &
4610               (TG3_FLAG_USE_LINKCHG_REG |
4611                TG3_FLAG_POLL_SERDES))) {
4612                 if (sblk->status & SD_STATUS_LINK_CHG) {
4613                         sblk->status = SD_STATUS_UPDATED |
4614                                 (sblk->status & ~SD_STATUS_LINK_CHG);
4615                         spin_lock(&tp->lock);
4616                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4617                                 tw32_f(MAC_STATUS,
4618                                      (MAC_STATUS_SYNC_CHANGED |
4619                                       MAC_STATUS_CFG_CHANGED |
4620                                       MAC_STATUS_MI_COMPLETION |
4621                                       MAC_STATUS_LNKSTATE_CHANGED));
4622                                 udelay(40);
4623                         } else
4624                                 tg3_setup_phy(tp, 0);
4625                         spin_unlock(&tp->lock);
4626                 }
4627         }
4628
4629         /* run TX completion thread */
4630         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
4631                 tg3_tx(tp);
4632                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4633                         return work_done;
4634         }
4635
4636         /* run RX thread, within the bounds set by NAPI.
4637          * All RX "locking" is done by ensuring outside
4638          * code synchronizes with tg3->napi.poll()
4639          */
4640         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
4641                 work_done += tg3_rx(tp, budget - work_done);
4642
4643         return work_done;
4644 }
4645
4646 static int tg3_poll(struct napi_struct *napi, int budget)
4647 {
4648         struct tg3 *tp = container_of(napi, struct tg3, napi);
4649         int work_done = 0;
4650         struct tg3_hw_status *sblk = tp->hw_status;
4651
4652         while (1) {
4653                 work_done = tg3_poll_work(tp, work_done, budget);
4654
4655                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4656                         goto tx_recovery;
4657
4658                 if (unlikely(work_done >= budget))
4659                         break;
4660
4661                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4662                         /* tp->last_tag is used in tg3_restart_ints() below
4663                          * to tell the hw how much work has been processed,
4664                          * so we must read it before checking for more work.
4665                          */
4666                         tp->last_tag = sblk->status_tag;
4667                         tp->last_irq_tag = tp->last_tag;
4668                         rmb();
4669                 } else
4670                         sblk->status &= ~SD_STATUS_UPDATED;
4671
4672                 if (likely(!tg3_has_work(tp))) {
4673                         napi_complete(napi);
4674                         tg3_restart_ints(tp);
4675                         break;
4676                 }
4677         }
4678
4679         return work_done;
4680
4681 tx_recovery:
4682         /* work_done is guaranteed to be less than budget. */
4683         napi_complete(napi);
4684         schedule_work(&tp->reset_task);
4685         return work_done;
4686 }
4687
4688 static void tg3_irq_quiesce(struct tg3 *tp)
4689 {
4690         BUG_ON(tp->irq_sync);
4691
4692         tp->irq_sync = 1;
4693         smp_mb();
4694
4695         synchronize_irq(tp->pdev->irq);
4696 }
4697
4698 static inline int tg3_irq_sync(struct tg3 *tp)
4699 {
4700         return tp->irq_sync;
4701 }
4702
4703 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4704  * If irq_sync is non-zero, then the IRQ handler must be synchronized
4705  * with as well.  Most of the time, this is not necessary except when
4706  * shutting down the device.
4707  */
4708 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4709 {
4710         spin_lock_bh(&tp->lock);
4711         if (irq_sync)
4712                 tg3_irq_quiesce(tp);
4713 }
4714
4715 static inline void tg3_full_unlock(struct tg3 *tp)
4716 {
4717         spin_unlock_bh(&tp->lock);
4718 }
4719
4720 /* One-shot MSI handler - Chip automatically disables interrupt
4721  * after sending MSI so driver doesn't have to do it.
4722  */
4723 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4724 {
4725         struct net_device *dev = dev_id;
4726         struct tg3 *tp = netdev_priv(dev);
4727
4728         prefetch(tp->hw_status);
4729         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4730
4731         if (likely(!tg3_irq_sync(tp)))
4732                 napi_schedule(&tp->napi);
4733
4734         return IRQ_HANDLED;
4735 }
4736
4737 /* MSI ISR - No need to check for interrupt sharing and no need to
4738  * flush status block and interrupt mailbox. PCI ordering rules
4739  * guarantee that MSI will arrive after the status block.
4740  */
4741 static irqreturn_t tg3_msi(int irq, void *dev_id)
4742 {
4743         struct net_device *dev = dev_id;
4744         struct tg3 *tp = netdev_priv(dev);
4745
4746         prefetch(tp->hw_status);
4747         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4748         /*
4749          * Writing any value to intr-mbox-0 clears PCI INTA# and
4750          * chip-internal interrupt pending events.
4751          * Writing non-zero to intr-mbox-0 additional tells the
4752          * NIC to stop sending us irqs, engaging "in-intr-handler"
4753          * event coalescing.
4754          */
4755         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4756         if (likely(!tg3_irq_sync(tp)))
4757                 napi_schedule(&tp->napi);
4758
4759         return IRQ_RETVAL(1);
4760 }
4761
4762 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4763 {
4764         struct net_device *dev = dev_id;
4765         struct tg3 *tp = netdev_priv(dev);
4766         struct tg3_hw_status *sblk = tp->hw_status;
4767         unsigned int handled = 1;
4768
4769         /* In INTx mode, it is possible for the interrupt to arrive at
4770          * the CPU before the status block posted prior to the interrupt.
4771          * Reading the PCI State register will confirm whether the
4772          * interrupt is ours and will flush the status block.
4773          */
4774         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4775                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4776                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4777                         handled = 0;
4778                         goto out;
4779                 }
4780         }
4781
4782         /*
4783          * Writing any value to intr-mbox-0 clears PCI INTA# and
4784          * chip-internal interrupt pending events.
4785          * Writing non-zero to intr-mbox-0 additional tells the
4786          * NIC to stop sending us irqs, engaging "in-intr-handler"
4787          * event coalescing.
4788          *
4789          * Flush the mailbox to de-assert the IRQ immediately to prevent
4790          * spurious interrupts.  The flush impacts performance but
4791          * excessive spurious interrupts can be worse in some cases.
4792          */
4793         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4794         if (tg3_irq_sync(tp))
4795                 goto out;
4796         sblk->status &= ~SD_STATUS_UPDATED;
4797         if (likely(tg3_has_work(tp))) {
4798                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4799                 napi_schedule(&tp->napi);
4800         } else {
4801                 /* No work, shared interrupt perhaps?  re-enable
4802                  * interrupts, and flush that PCI write
4803                  */
4804                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4805                                0x00000000);
4806         }
4807 out:
4808         return IRQ_RETVAL(handled);
4809 }
4810
4811 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4812 {
4813         struct net_device *dev = dev_id;
4814         struct tg3 *tp = netdev_priv(dev);
4815         struct tg3_hw_status *sblk = tp->hw_status;
4816         unsigned int handled = 1;
4817
4818         /* In INTx mode, it is possible for the interrupt to arrive at
4819          * the CPU before the status block posted prior to the interrupt.
4820          * Reading the PCI State register will confirm whether the
4821          * interrupt is ours and will flush the status block.
4822          */
4823         if (unlikely(sblk->status_tag == tp->last_irq_tag)) {
4824                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4825                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4826                         handled = 0;
4827                         goto out;
4828                 }
4829         }
4830
4831         /*
4832          * writing any value to intr-mbox-0 clears PCI INTA# and
4833          * chip-internal interrupt pending events.
4834          * writing non-zero to intr-mbox-0 additional tells the
4835          * NIC to stop sending us irqs, engaging "in-intr-handler"
4836          * event coalescing.
4837          *
4838          * Flush the mailbox to de-assert the IRQ immediately to prevent
4839          * spurious interrupts.  The flush impacts performance but
4840          * excessive spurious interrupts can be worse in some cases.
4841          */
4842         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4843
4844         /*
4845          * In a shared interrupt configuration, sometimes other devices'
4846          * interrupts will scream.  We record the current status tag here
4847          * so that the above check can report that the screaming interrupts
4848          * are unhandled.  Eventually they will be silenced.
4849          */
4850         tp->last_irq_tag = sblk->status_tag;
4851
4852         if (tg3_irq_sync(tp))
4853                 goto out;
4854
4855         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4856
4857         napi_schedule(&tp->napi);
4858
4859 out:
4860         return IRQ_RETVAL(handled);
4861 }
4862
4863 /* ISR for interrupt test */
4864 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4865 {
4866         struct net_device *dev = dev_id;
4867         struct tg3 *tp = netdev_priv(dev);
4868         struct tg3_hw_status *sblk = tp->hw_status;
4869
4870         if ((sblk->status & SD_STATUS_UPDATED) ||
4871             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4872                 tg3_disable_ints(tp);
4873                 return IRQ_RETVAL(1);
4874         }
4875         return IRQ_RETVAL(0);
4876 }
4877
4878 static int tg3_init_hw(struct tg3 *, int);
4879 static int tg3_halt(struct tg3 *, int, int);
4880
4881 /* Restart hardware after configuration changes, self-test, etc.
4882  * Invoked with tp->lock held.
4883  */
4884 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4885         __releases(tp->lock)
4886         __acquires(tp->lock)
4887 {
4888         int err;
4889
4890         err = tg3_init_hw(tp, reset_phy);
4891         if (err) {
4892                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4893                        "aborting.\n", tp->dev->name);
4894                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4895                 tg3_full_unlock(tp);
4896                 del_timer_sync(&tp->timer);
4897                 tp->irq_sync = 0;
4898                 napi_enable(&tp->napi);
4899                 dev_close(tp->dev);
4900                 tg3_full_lock(tp, 0);
4901         }
4902         return err;
4903 }
4904
4905 #ifdef CONFIG_NET_POLL_CONTROLLER
4906 static void tg3_poll_controller(struct net_device *dev)
4907 {
4908         struct tg3 *tp = netdev_priv(dev);
4909
4910         tg3_interrupt(tp->pdev->irq, dev);
4911 }
4912 #endif
4913
4914 static void tg3_reset_task(struct work_struct *work)
4915 {
4916         struct tg3 *tp = container_of(work, struct tg3, reset_task);
4917         int err;
4918         unsigned int restart_timer;
4919
4920         tg3_full_lock(tp, 0);
4921
4922         if (!netif_running(tp->dev)) {
4923                 tg3_full_unlock(tp);
4924                 return;
4925         }
4926
4927         tg3_full_unlock(tp);
4928
4929         tg3_phy_stop(tp);
4930
4931         tg3_netif_stop(tp);
4932
4933         tg3_full_lock(tp, 1);
4934
4935         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4936         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4937
4938         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4939                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4940                 tp->write32_rx_mbox = tg3_write_flush_reg32;
4941                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4942                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4943         }
4944
4945         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
4946         err = tg3_init_hw(tp, 1);
4947         if (err)
4948                 goto out;
4949
4950         tg3_netif_start(tp);
4951
4952         if (restart_timer)
4953                 mod_timer(&tp->timer, jiffies + 1);
4954
4955 out:
4956         tg3_full_unlock(tp);
4957
4958         if (!err)
4959                 tg3_phy_start(tp);
4960 }
4961
4962 static void tg3_dump_short_state(struct tg3 *tp)
4963 {
4964         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
4965                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
4966         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
4967                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
4968 }
4969
4970 static void tg3_tx_timeout(struct net_device *dev)
4971 {
4972         struct tg3 *tp = netdev_priv(dev);
4973
4974         if (netif_msg_tx_err(tp)) {
4975                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
4976                        dev->name);
4977                 tg3_dump_short_state(tp);
4978         }
4979
4980         schedule_work(&tp->reset_task);
4981 }
4982
4983 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
4984 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
4985 {
4986         u32 base = (u32) mapping & 0xffffffff;
4987
4988         return ((base > 0xffffdcc0) &&
4989                 (base + len + 8 < base));
4990 }
4991
4992 /* Test for DMA addresses > 40-bit */
4993 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
4994                                           int len)
4995 {
4996 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
4997         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
4998                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
4999         return 0;
5000 #else
5001         return 0;
5002 #endif
5003 }
5004
5005 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
5006
5007 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5008 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
5009                                        u32 last_plus_one, u32 *start,
5010                                        u32 base_flags, u32 mss)
5011 {
5012         struct sk_buff *new_skb;
5013         dma_addr_t new_addr = 0;
5014         u32 entry = *start;
5015         int i, ret = 0;
5016
5017         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5018                 new_skb = skb_copy(skb, GFP_ATOMIC);
5019         else {
5020                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5021
5022                 new_skb = skb_copy_expand(skb,
5023                                           skb_headroom(skb) + more_headroom,
5024                                           skb_tailroom(skb), GFP_ATOMIC);
5025         }
5026
5027         if (!new_skb) {
5028                 ret = -1;
5029         } else {
5030                 /* New SKB is guaranteed to be linear. */
5031                 entry = *start;
5032                 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
5033                 new_addr = skb_shinfo(new_skb)->dma_head;
5034
5035                 /* Make sure new skb does not cross any 4G boundaries.
5036                  * Drop the packet if it does.
5037                  */
5038                 if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) {
5039                         if (!ret)
5040                                 skb_dma_unmap(&tp->pdev->dev, new_skb,
5041                                               DMA_TO_DEVICE);
5042                         ret = -1;
5043                         dev_kfree_skb(new_skb);
5044                         new_skb = NULL;
5045                 } else {
5046                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
5047                                     base_flags, 1 | (mss << 1));
5048                         *start = NEXT_TX(entry);
5049                 }
5050         }
5051
5052         /* Now clean up the sw ring entries. */
5053         i = 0;
5054         while (entry != last_plus_one) {
5055                 if (i == 0) {
5056                         tp->tx_buffers[entry].skb = new_skb;
5057                 } else {
5058                         tp->tx_buffers[entry].skb = NULL;
5059                 }
5060                 entry = NEXT_TX(entry);
5061                 i++;
5062         }
5063
5064         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5065         dev_kfree_skb(skb);
5066
5067         return ret;
5068 }
5069
5070 static void tg3_set_txd(struct tg3 *tp, int entry,
5071                         dma_addr_t mapping, int len, u32 flags,
5072                         u32 mss_and_is_end)
5073 {
5074         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
5075         int is_end = (mss_and_is_end & 0x1);
5076         u32 mss = (mss_and_is_end >> 1);
5077         u32 vlan_tag = 0;
5078
5079         if (is_end)
5080                 flags |= TXD_FLAG_END;
5081         if (flags & TXD_FLAG_VLAN) {
5082                 vlan_tag = flags >> 16;
5083                 flags &= 0xffff;
5084         }
5085         vlan_tag |= (mss << TXD_MSS_SHIFT);
5086
5087         txd->addr_hi = ((u64) mapping >> 32);
5088         txd->addr_lo = ((u64) mapping & 0xffffffff);
5089         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5090         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5091 }
5092
5093 /* hard_start_xmit for devices that don't have any bugs and
5094  * support TG3_FLG2_HW_TSO_2 only.
5095  */
5096 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
5097 {
5098         struct tg3 *tp = netdev_priv(dev);
5099         u32 len, entry, base_flags, mss;
5100         struct skb_shared_info *sp;
5101         dma_addr_t mapping;
5102
5103         len = skb_headlen(skb);
5104
5105         /* We are running in BH disabled context with netif_tx_lock
5106          * and TX reclaim runs via tp->napi.poll inside of a software
5107          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5108          * no IRQ context deadlocks to worry about either.  Rejoice!
5109          */
5110         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5111                 if (!netif_queue_stopped(dev)) {
5112                         netif_stop_queue(dev);
5113
5114                         /* This is a hard error, log it. */
5115                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5116                                "queue awake!\n", dev->name);
5117                 }
5118                 return NETDEV_TX_BUSY;
5119         }
5120
5121         entry = tp->tx_prod;
5122         base_flags = 0;
5123         mss = 0;
5124         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5125                 int tcp_opt_len, ip_tcp_len;
5126
5127                 if (skb_header_cloned(skb) &&
5128                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5129                         dev_kfree_skb(skb);
5130                         goto out_unlock;
5131                 }
5132
5133                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5134                         mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
5135                 else {
5136                         struct iphdr *iph = ip_hdr(skb);
5137
5138                         tcp_opt_len = tcp_optlen(skb);
5139                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5140
5141                         iph->check = 0;
5142                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5143                         mss |= (ip_tcp_len + tcp_opt_len) << 9;
5144                 }
5145
5146                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5147                                TXD_FLAG_CPU_POST_DMA);
5148
5149                 tcp_hdr(skb)->check = 0;
5150
5151         }
5152         else if (skb->ip_summed == CHECKSUM_PARTIAL)
5153                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5154 #if TG3_VLAN_TAG_USED
5155         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5156                 base_flags |= (TXD_FLAG_VLAN |
5157                                (vlan_tx_tag_get(skb) << 16));
5158 #endif
5159
5160         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5161                 dev_kfree_skb(skb);
5162                 goto out_unlock;
5163         }
5164
5165         sp = skb_shinfo(skb);
5166
5167         mapping = sp->dma_head;
5168
5169         tp->tx_buffers[entry].skb = skb;
5170
5171         tg3_set_txd(tp, entry, mapping, len, base_flags,
5172                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5173
5174         entry = NEXT_TX(entry);
5175
5176         /* Now loop through additional data fragments, and queue them. */
5177         if (skb_shinfo(skb)->nr_frags > 0) {
5178                 unsigned int i, last;
5179
5180                 last = skb_shinfo(skb)->nr_frags - 1;
5181                 for (i = 0; i <= last; i++) {
5182                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5183
5184                         len = frag->size;
5185                         mapping = sp->dma_maps[i];
5186                         tp->tx_buffers[entry].skb = NULL;
5187
5188                         tg3_set_txd(tp, entry, mapping, len,
5189                                     base_flags, (i == last) | (mss << 1));
5190
5191                         entry = NEXT_TX(entry);
5192                 }
5193         }
5194
5195         /* Packets are ready, update Tx producer idx local and on card. */
5196         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5197
5198         tp->tx_prod = entry;
5199         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5200                 netif_stop_queue(dev);
5201                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5202                         netif_wake_queue(tp->dev);
5203         }
5204
5205 out_unlock:
5206         mmiowb();
5207
5208         return NETDEV_TX_OK;
5209 }
5210
5211 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
5212
5213 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5214  * TSO header is greater than 80 bytes.
5215  */
5216 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5217 {
5218         struct sk_buff *segs, *nskb;
5219
5220         /* Estimate the number of fragments in the worst case */
5221         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
5222                 netif_stop_queue(tp->dev);
5223                 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
5224                         return NETDEV_TX_BUSY;
5225
5226                 netif_wake_queue(tp->dev);
5227         }
5228
5229         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5230         if (IS_ERR(segs))
5231                 goto tg3_tso_bug_end;
5232
5233         do {
5234                 nskb = segs;
5235                 segs = segs->next;
5236                 nskb->next = NULL;
5237                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5238         } while (segs);
5239
5240 tg3_tso_bug_end:
5241         dev_kfree_skb(skb);
5242
5243         return NETDEV_TX_OK;
5244 }
5245
5246 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5247  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5248  */
5249 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
5250 {
5251         struct tg3 *tp = netdev_priv(dev);
5252         u32 len, entry, base_flags, mss;
5253         struct skb_shared_info *sp;
5254         int would_hit_hwbug;
5255         dma_addr_t mapping;
5256
5257         len = skb_headlen(skb);
5258
5259         /* We are running in BH disabled context with netif_tx_lock
5260          * and TX reclaim runs via tp->napi.poll inside of a software
5261          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5262          * no IRQ context deadlocks to worry about either.  Rejoice!
5263          */
5264         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5265                 if (!netif_queue_stopped(dev)) {
5266                         netif_stop_queue(dev);
5267
5268                         /* This is a hard error, log it. */
5269                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5270                                "queue awake!\n", dev->name);
5271                 }
5272                 return NETDEV_TX_BUSY;
5273         }
5274
5275         entry = tp->tx_prod;
5276         base_flags = 0;
5277         if (skb->ip_summed == CHECKSUM_PARTIAL)
5278                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5279         mss = 0;
5280         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5281                 struct iphdr *iph;
5282                 int tcp_opt_len, ip_tcp_len, hdr_len;
5283
5284                 if (skb_header_cloned(skb) &&
5285                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5286                         dev_kfree_skb(skb);
5287                         goto out_unlock;
5288                 }
5289
5290                 tcp_opt_len = tcp_optlen(skb);
5291                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5292
5293                 hdr_len = ip_tcp_len + tcp_opt_len;
5294                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5295                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5296                         return (tg3_tso_bug(tp, skb));
5297
5298                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5299                                TXD_FLAG_CPU_POST_DMA);
5300
5301                 iph = ip_hdr(skb);
5302                 iph->check = 0;
5303                 iph->tot_len = htons(mss + hdr_len);
5304                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5305                         tcp_hdr(skb)->check = 0;
5306                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5307                 } else
5308                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5309                                                                  iph->daddr, 0,
5310                                                                  IPPROTO_TCP,
5311                                                                  0);
5312
5313                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
5314                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
5315                         if (tcp_opt_len || iph->ihl > 5) {
5316                                 int tsflags;
5317
5318                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5319                                 mss |= (tsflags << 11);
5320                         }
5321                 } else {
5322                         if (tcp_opt_len || iph->ihl > 5) {
5323                                 int tsflags;
5324
5325                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5326                                 base_flags |= tsflags << 12;
5327                         }
5328                 }
5329         }
5330 #if TG3_VLAN_TAG_USED
5331         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5332                 base_flags |= (TXD_FLAG_VLAN |
5333                                (vlan_tx_tag_get(skb) << 16));
5334 #endif
5335
5336         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5337                 dev_kfree_skb(skb);
5338                 goto out_unlock;
5339         }
5340
5341         sp = skb_shinfo(skb);
5342
5343         mapping = sp->dma_head;
5344
5345         tp->tx_buffers[entry].skb = skb;
5346
5347         would_hit_hwbug = 0;
5348
5349         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5350                 would_hit_hwbug = 1;
5351         else if (tg3_4g_overflow_test(mapping, len))
5352                 would_hit_hwbug = 1;
5353
5354         tg3_set_txd(tp, entry, mapping, len, base_flags,
5355                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5356
5357         entry = NEXT_TX(entry);
5358
5359         /* Now loop through additional data fragments, and queue them. */
5360         if (skb_shinfo(skb)->nr_frags > 0) {
5361                 unsigned int i, last;
5362
5363                 last = skb_shinfo(skb)->nr_frags - 1;
5364                 for (i = 0; i <= last; i++) {
5365                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5366
5367                         len = frag->size;
5368                         mapping = sp->dma_maps[i];
5369
5370                         tp->tx_buffers[entry].skb = NULL;
5371
5372                         if (tg3_4g_overflow_test(mapping, len))
5373                                 would_hit_hwbug = 1;
5374
5375                         if (tg3_40bit_overflow_test(tp, mapping, len))
5376                                 would_hit_hwbug = 1;
5377
5378                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5379                                 tg3_set_txd(tp, entry, mapping, len,
5380                                             base_flags, (i == last)|(mss << 1));
5381                         else
5382                                 tg3_set_txd(tp, entry, mapping, len,
5383                                             base_flags, (i == last));
5384
5385                         entry = NEXT_TX(entry);
5386                 }
5387         }
5388
5389         if (would_hit_hwbug) {
5390                 u32 last_plus_one = entry;
5391                 u32 start;
5392
5393                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5394                 start &= (TG3_TX_RING_SIZE - 1);
5395
5396                 /* If the workaround fails due to memory/mapping
5397                  * failure, silently drop this packet.
5398                  */
5399                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
5400                                                 &start, base_flags, mss))
5401                         goto out_unlock;
5402
5403                 entry = start;
5404         }
5405
5406         /* Packets are ready, update Tx producer idx local and on card. */
5407         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5408
5409         tp->tx_prod = entry;
5410         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5411                 netif_stop_queue(dev);
5412                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5413                         netif_wake_queue(tp->dev);
5414         }
5415
5416 out_unlock:
5417         mmiowb();
5418
5419         return NETDEV_TX_OK;
5420 }
5421
5422 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5423                                int new_mtu)
5424 {
5425         dev->mtu = new_mtu;
5426
5427         if (new_mtu > ETH_DATA_LEN) {
5428                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5429                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5430                         ethtool_op_set_tso(dev, 0);
5431                 }
5432                 else
5433                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5434         } else {
5435                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5436                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5437                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5438         }
5439 }
5440
5441 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5442 {
5443         struct tg3 *tp = netdev_priv(dev);
5444         int err;
5445
5446         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5447                 return -EINVAL;
5448
5449         if (!netif_running(dev)) {
5450                 /* We'll just catch it later when the
5451                  * device is up'd.
5452                  */
5453                 tg3_set_mtu(dev, tp, new_mtu);
5454                 return 0;
5455         }
5456
5457         tg3_phy_stop(tp);
5458
5459         tg3_netif_stop(tp);
5460
5461         tg3_full_lock(tp, 1);
5462
5463         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5464
5465         tg3_set_mtu(dev, tp, new_mtu);
5466
5467         err = tg3_restart_hw(tp, 0);
5468
5469         if (!err)
5470                 tg3_netif_start(tp);
5471
5472         tg3_full_unlock(tp);
5473
5474         if (!err)
5475                 tg3_phy_start(tp);
5476
5477         return err;
5478 }
5479
5480 /* Free up pending packets in all rx/tx rings.
5481  *
5482  * The chip has been shut down and the driver detached from
5483  * the networking, so no interrupts or new tx packets will
5484  * end up in the driver.  tp->{tx,}lock is not held and we are not
5485  * in an interrupt context and thus may sleep.
5486  */
5487 static void tg3_free_rings(struct tg3 *tp)
5488 {
5489         struct ring_info *rxp;
5490         int i;
5491
5492         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5493                 rxp = &tp->rx_std_buffers[i];
5494
5495                 if (rxp->skb == NULL)
5496                         continue;
5497                 pci_unmap_single(tp->pdev,
5498                                  pci_unmap_addr(rxp, mapping),
5499                                  tp->rx_pkt_buf_sz - tp->rx_offset,
5500                                  PCI_DMA_FROMDEVICE);
5501                 dev_kfree_skb_any(rxp->skb);
5502                 rxp->skb = NULL;
5503         }
5504
5505         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5506                 rxp = &tp->rx_jumbo_buffers[i];
5507
5508                 if (rxp->skb == NULL)
5509                         continue;
5510                 pci_unmap_single(tp->pdev,
5511                                  pci_unmap_addr(rxp, mapping),
5512                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
5513                                  PCI_DMA_FROMDEVICE);
5514                 dev_kfree_skb_any(rxp->skb);
5515                 rxp->skb = NULL;
5516         }
5517
5518         for (i = 0; i < TG3_TX_RING_SIZE; ) {
5519                 struct tx_ring_info *txp;
5520                 struct sk_buff *skb;
5521
5522                 txp = &tp->tx_buffers[i];
5523                 skb = txp->skb;
5524
5525                 if (skb == NULL) {
5526                         i++;
5527                         continue;
5528                 }
5529
5530                 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5531
5532                 txp->skb = NULL;
5533
5534                 i += skb_shinfo(skb)->nr_frags + 1;
5535
5536                 dev_kfree_skb_any(skb);
5537         }
5538 }
5539
5540 /* Initialize tx/rx rings for packet processing.
5541  *
5542  * The chip has been shut down and the driver detached from
5543  * the networking, so no interrupts or new tx packets will
5544  * end up in the driver.  tp->{tx,}lock are held and thus
5545  * we may not sleep.
5546  */
5547 static int tg3_init_rings(struct tg3 *tp)
5548 {
5549         u32 i;
5550
5551         /* Free up all the SKBs. */
5552         tg3_free_rings(tp);
5553
5554         /* Zero out all descriptors. */
5555         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
5556         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
5557         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5558         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
5559
5560         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
5561         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5562             (tp->dev->mtu > ETH_DATA_LEN))
5563                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
5564
5565         /* Initialize invariants of the rings, we only set this
5566          * stuff once.  This works because the card does not
5567          * write into the rx buffer posting rings.
5568          */
5569         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5570                 struct tg3_rx_buffer_desc *rxd;
5571
5572                 rxd = &tp->rx_std[i];
5573                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
5574                         << RXD_LEN_SHIFT;
5575                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5576                 rxd->opaque = (RXD_OPAQUE_RING_STD |
5577                                (i << RXD_OPAQUE_INDEX_SHIFT));
5578         }
5579
5580         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5581                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5582                         struct tg3_rx_buffer_desc *rxd;
5583
5584                         rxd = &tp->rx_jumbo[i];
5585                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
5586                                 << RXD_LEN_SHIFT;
5587                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5588                                 RXD_FLAG_JUMBO;
5589                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5590                                (i << RXD_OPAQUE_INDEX_SHIFT));
5591                 }
5592         }
5593
5594         /* Now allocate fresh SKBs for each rx ring. */
5595         for (i = 0; i < tp->rx_pending; i++) {
5596                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5597                         printk(KERN_WARNING PFX
5598                                "%s: Using a smaller RX standard ring, "
5599                                "only %d out of %d buffers were allocated "
5600                                "successfully.\n",
5601                                tp->dev->name, i, tp->rx_pending);
5602                         if (i == 0)
5603                                 return -ENOMEM;
5604                         tp->rx_pending = i;
5605                         break;
5606                 }
5607         }
5608
5609         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5610                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5611                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
5612                                              -1, i) < 0) {
5613                                 printk(KERN_WARNING PFX
5614                                        "%s: Using a smaller RX jumbo ring, "
5615                                        "only %d out of %d buffers were "
5616                                        "allocated successfully.\n",
5617                                        tp->dev->name, i, tp->rx_jumbo_pending);
5618                                 if (i == 0) {
5619                                         tg3_free_rings(tp);
5620                                         return -ENOMEM;
5621                                 }
5622                                 tp->rx_jumbo_pending = i;
5623                                 break;
5624                         }
5625                 }
5626         }
5627         return 0;
5628 }
5629
5630 /*
5631  * Must not be invoked with interrupt sources disabled and
5632  * the hardware shutdown down.
5633  */
5634 static void tg3_free_consistent(struct tg3 *tp)
5635 {
5636         kfree(tp->rx_std_buffers);
5637         tp->rx_std_buffers = NULL;
5638         if (tp->rx_std) {
5639                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5640                                     tp->rx_std, tp->rx_std_mapping);
5641                 tp->rx_std = NULL;
5642         }
5643         if (tp->rx_jumbo) {
5644                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5645                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
5646                 tp->rx_jumbo = NULL;
5647         }
5648         if (tp->rx_rcb) {
5649                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5650                                     tp->rx_rcb, tp->rx_rcb_mapping);
5651                 tp->rx_rcb = NULL;
5652         }
5653         if (tp->tx_ring) {
5654                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5655                         tp->tx_ring, tp->tx_desc_mapping);
5656                 tp->tx_ring = NULL;
5657         }
5658         if (tp->hw_status) {
5659                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5660                                     tp->hw_status, tp->status_mapping);
5661                 tp->hw_status = NULL;
5662         }
5663         if (tp->hw_stats) {
5664                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5665                                     tp->hw_stats, tp->stats_mapping);
5666                 tp->hw_stats = NULL;
5667         }
5668 }
5669
5670 /*
5671  * Must not be invoked with interrupt sources disabled and
5672  * the hardware shutdown down.  Can sleep.
5673  */
5674 static int tg3_alloc_consistent(struct tg3 *tp)
5675 {
5676         tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
5677                                       (TG3_RX_RING_SIZE +
5678                                        TG3_RX_JUMBO_RING_SIZE)) +
5679                                      (sizeof(struct tx_ring_info) *
5680                                       TG3_TX_RING_SIZE),
5681                                      GFP_KERNEL);
5682         if (!tp->rx_std_buffers)
5683                 return -ENOMEM;
5684
5685         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
5686         tp->tx_buffers = (struct tx_ring_info *)
5687                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
5688
5689         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5690                                           &tp->rx_std_mapping);
5691         if (!tp->rx_std)
5692                 goto err_out;
5693
5694         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5695                                             &tp->rx_jumbo_mapping);
5696
5697         if (!tp->rx_jumbo)
5698                 goto err_out;
5699
5700         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5701                                           &tp->rx_rcb_mapping);
5702         if (!tp->rx_rcb)
5703                 goto err_out;
5704
5705         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5706                                            &tp->tx_desc_mapping);
5707         if (!tp->tx_ring)
5708                 goto err_out;
5709
5710         tp->hw_status = pci_alloc_consistent(tp->pdev,
5711                                              TG3_HW_STATUS_SIZE,
5712                                              &tp->status_mapping);
5713         if (!tp->hw_status)
5714                 goto err_out;
5715
5716         tp->hw_stats = pci_alloc_consistent(tp->pdev,
5717                                             sizeof(struct tg3_hw_stats),
5718                                             &tp->stats_mapping);
5719         if (!tp->hw_stats)
5720                 goto err_out;
5721
5722         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5723         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5724
5725         return 0;
5726
5727 err_out:
5728         tg3_free_consistent(tp);
5729         return -ENOMEM;
5730 }
5731
5732 #define MAX_WAIT_CNT 1000
5733
5734 /* To stop a block, clear the enable bit and poll till it
5735  * clears.  tp->lock is held.
5736  */
5737 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
5738 {
5739         unsigned int i;
5740         u32 val;
5741
5742         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5743                 switch (ofs) {
5744                 case RCVLSC_MODE:
5745                 case DMAC_MODE:
5746                 case MBFREE_MODE:
5747                 case BUFMGR_MODE:
5748                 case MEMARB_MODE:
5749                         /* We can't enable/disable these bits of the
5750                          * 5705/5750, just say success.
5751                          */
5752                         return 0;
5753
5754                 default:
5755                         break;
5756                 }
5757         }
5758
5759         val = tr32(ofs);
5760         val &= ~enable_bit;
5761         tw32_f(ofs, val);
5762
5763         for (i = 0; i < MAX_WAIT_CNT; i++) {
5764                 udelay(100);
5765                 val = tr32(ofs);
5766                 if ((val & enable_bit) == 0)
5767                         break;
5768         }
5769
5770         if (i == MAX_WAIT_CNT && !silent) {
5771                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5772                        "ofs=%lx enable_bit=%x\n",
5773                        ofs, enable_bit);
5774                 return -ENODEV;
5775         }
5776
5777         return 0;
5778 }
5779
5780 /* tp->lock is held. */
5781 static int tg3_abort_hw(struct tg3 *tp, int silent)
5782 {
5783         int i, err;
5784
5785         tg3_disable_ints(tp);
5786
5787         tp->rx_mode &= ~RX_MODE_ENABLE;
5788         tw32_f(MAC_RX_MODE, tp->rx_mode);
5789         udelay(10);
5790
5791         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5792         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5793         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5794         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5795         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5796         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5797
5798         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5799         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5800         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5801         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5802         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5803         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5804         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
5805
5806         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5807         tw32_f(MAC_MODE, tp->mac_mode);
5808         udelay(40);
5809
5810         tp->tx_mode &= ~TX_MODE_ENABLE;
5811         tw32_f(MAC_TX_MODE, tp->tx_mode);
5812
5813         for (i = 0; i < MAX_WAIT_CNT; i++) {
5814                 udelay(100);
5815                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5816                         break;
5817         }
5818         if (i >= MAX_WAIT_CNT) {
5819                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5820                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5821                        tp->dev->name, tr32(MAC_TX_MODE));
5822                 err |= -ENODEV;
5823         }
5824
5825         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
5826         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5827         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
5828
5829         tw32(FTQ_RESET, 0xffffffff);
5830         tw32(FTQ_RESET, 0x00000000);
5831
5832         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5833         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
5834
5835         if (tp->hw_status)
5836                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5837         if (tp->hw_stats)
5838                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5839
5840         return err;
5841 }
5842
5843 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5844 {
5845         int i;
5846         u32 apedata;
5847
5848         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5849         if (apedata != APE_SEG_SIG_MAGIC)
5850                 return;
5851
5852         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
5853         if (!(apedata & APE_FW_STATUS_READY))
5854                 return;
5855
5856         /* Wait for up to 1 millisecond for APE to service previous event. */
5857         for (i = 0; i < 10; i++) {
5858                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5859                         return;
5860
5861                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5862
5863                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5864                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5865                                         event | APE_EVENT_STATUS_EVENT_PENDING);
5866
5867                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5868
5869                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5870                         break;
5871
5872                 udelay(100);
5873         }
5874
5875         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5876                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5877 }
5878
5879 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5880 {
5881         u32 event;
5882         u32 apedata;
5883
5884         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5885                 return;
5886
5887         switch (kind) {
5888                 case RESET_KIND_INIT:
5889                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5890                                         APE_HOST_SEG_SIG_MAGIC);
5891                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5892                                         APE_HOST_SEG_LEN_MAGIC);
5893                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5894                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5895                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
5896                                         APE_HOST_DRIVER_ID_MAGIC);
5897                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
5898                                         APE_HOST_BEHAV_NO_PHYLOCK);
5899
5900                         event = APE_EVENT_STATUS_STATE_START;
5901                         break;
5902                 case RESET_KIND_SHUTDOWN:
5903                         /* With the interface we are currently using,
5904                          * APE does not track driver state.  Wiping
5905                          * out the HOST SEGMENT SIGNATURE forces
5906                          * the APE to assume OS absent status.
5907                          */
5908                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
5909
5910                         event = APE_EVENT_STATUS_STATE_UNLOAD;
5911                         break;
5912                 case RESET_KIND_SUSPEND:
5913                         event = APE_EVENT_STATUS_STATE_SUSPEND;
5914                         break;
5915                 default:
5916                         return;
5917         }
5918
5919         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
5920
5921         tg3_ape_send_event(tp, event);
5922 }
5923
5924 /* tp->lock is held. */
5925 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
5926 {
5927         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
5928                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
5929
5930         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5931                 switch (kind) {
5932                 case RESET_KIND_INIT:
5933                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5934                                       DRV_STATE_START);
5935                         break;
5936
5937                 case RESET_KIND_SHUTDOWN:
5938                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5939                                       DRV_STATE_UNLOAD);
5940                         break;
5941
5942                 case RESET_KIND_SUSPEND:
5943                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5944                                       DRV_STATE_SUSPEND);
5945                         break;
5946
5947                 default:
5948                         break;
5949                 }
5950         }
5951
5952         if (kind == RESET_KIND_INIT ||
5953             kind == RESET_KIND_SUSPEND)
5954                 tg3_ape_driver_state_change(tp, kind);
5955 }
5956
5957 /* tp->lock is held. */
5958 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
5959 {
5960         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5961                 switch (kind) {
5962                 case RESET_KIND_INIT:
5963                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5964                                       DRV_STATE_START_DONE);
5965                         break;
5966
5967                 case RESET_KIND_SHUTDOWN:
5968                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5969                                       DRV_STATE_UNLOAD_DONE);
5970                         break;
5971
5972                 default:
5973                         break;
5974                 }
5975         }
5976
5977         if (kind == RESET_KIND_SHUTDOWN)
5978                 tg3_ape_driver_state_change(tp, kind);
5979 }
5980
5981 /* tp->lock is held. */
5982 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
5983 {
5984         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5985                 switch (kind) {
5986                 case RESET_KIND_INIT:
5987                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5988                                       DRV_STATE_START);
5989                         break;
5990
5991                 case RESET_KIND_SHUTDOWN:
5992                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5993                                       DRV_STATE_UNLOAD);
5994                         break;
5995
5996                 case RESET_KIND_SUSPEND:
5997                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5998                                       DRV_STATE_SUSPEND);
5999                         break;
6000
6001                 default:
6002                         break;
6003                 }
6004         }
6005 }
6006
6007 static int tg3_poll_fw(struct tg3 *tp)
6008 {
6009         int i;
6010         u32 val;
6011
6012         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6013                 /* Wait up to 20ms for init done. */
6014                 for (i = 0; i < 200; i++) {
6015                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6016                                 return 0;
6017                         udelay(100);
6018                 }
6019                 return -ENODEV;
6020         }
6021
6022         /* Wait for firmware initialization to complete. */
6023         for (i = 0; i < 100000; i++) {
6024                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6025                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6026                         break;
6027                 udelay(10);
6028         }
6029
6030         /* Chip might not be fitted with firmware.  Some Sun onboard
6031          * parts are configured like that.  So don't signal the timeout
6032          * of the above loop as an error, but do report the lack of
6033          * running firmware once.
6034          */
6035         if (i >= 100000 &&
6036             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6037                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6038
6039                 printk(KERN_INFO PFX "%s: No firmware running.\n",
6040                        tp->dev->name);
6041         }
6042
6043         return 0;
6044 }
6045
6046 /* Save PCI command register before chip reset */
6047 static void tg3_save_pci_state(struct tg3 *tp)
6048 {
6049         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6050 }
6051
6052 /* Restore PCI state after chip reset */
6053 static void tg3_restore_pci_state(struct tg3 *tp)
6054 {
6055         u32 val;
6056
6057         /* Re-enable indirect register accesses. */
6058         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6059                                tp->misc_host_ctrl);
6060
6061         /* Set MAX PCI retry to zero. */
6062         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6063         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6064             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6065                 val |= PCISTATE_RETRY_SAME_DMA;
6066         /* Allow reads and writes to the APE register and memory space. */
6067         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6068                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6069                        PCISTATE_ALLOW_APE_SHMEM_WR;
6070         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6071
6072         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6073
6074         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6075                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6076                         pcie_set_readrq(tp->pdev, 4096);
6077                 else {
6078                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6079                                               tp->pci_cacheline_sz);
6080                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6081                                               tp->pci_lat_timer);
6082                 }
6083         }
6084
6085         /* Make sure PCI-X relaxed ordering bit is clear. */
6086         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6087                 u16 pcix_cmd;
6088
6089                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6090                                      &pcix_cmd);
6091                 pcix_cmd &= ~PCI_X_CMD_ERO;
6092                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6093                                       pcix_cmd);
6094         }
6095
6096         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6097
6098                 /* Chip reset on 5780 will reset MSI enable bit,
6099                  * so need to restore it.
6100                  */
6101                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6102                         u16 ctrl;
6103
6104                         pci_read_config_word(tp->pdev,
6105                                              tp->msi_cap + PCI_MSI_FLAGS,
6106                                              &ctrl);
6107                         pci_write_config_word(tp->pdev,
6108                                               tp->msi_cap + PCI_MSI_FLAGS,
6109                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6110                         val = tr32(MSGINT_MODE);
6111                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6112                 }
6113         }
6114 }
6115
6116 static void tg3_stop_fw(struct tg3 *);
6117
6118 /* tp->lock is held. */
6119 static int tg3_chip_reset(struct tg3 *tp)
6120 {
6121         u32 val;
6122         void (*write_op)(struct tg3 *, u32, u32);
6123         int err;
6124
6125         tg3_nvram_lock(tp);
6126
6127         tg3_mdio_stop(tp);
6128
6129         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6130
6131         /* No matching tg3_nvram_unlock() after this because
6132          * chip reset below will undo the nvram lock.
6133          */
6134         tp->nvram_lock_cnt = 0;
6135
6136         /* GRC_MISC_CFG core clock reset will clear the memory
6137          * enable bit in PCI register 4 and the MSI enable bit
6138          * on some chips, so we save relevant registers here.
6139          */
6140         tg3_save_pci_state(tp);
6141
6142         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6143             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6144                 tw32(GRC_FASTBOOT_PC, 0);
6145
6146         /*
6147          * We must avoid the readl() that normally takes place.
6148          * It locks machines, causes machine checks, and other
6149          * fun things.  So, temporarily disable the 5701
6150          * hardware workaround, while we do the reset.
6151          */
6152         write_op = tp->write32;
6153         if (write_op == tg3_write_flush_reg32)
6154                 tp->write32 = tg3_write32;
6155
6156         /* Prevent the irq handler from reading or writing PCI registers
6157          * during chip reset when the memory enable bit in the PCI command
6158          * register may be cleared.  The chip does not generate interrupt
6159          * at this time, but the irq handler may still be called due to irq
6160          * sharing or irqpoll.
6161          */
6162         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6163         if (tp->hw_status) {
6164                 tp->hw_status->status = 0;
6165                 tp->hw_status->status_tag = 0;
6166         }
6167         tp->last_tag = 0;
6168         tp->last_irq_tag = 0;
6169         smp_mb();
6170         synchronize_irq(tp->pdev->irq);
6171
6172         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6173                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6174                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6175         }
6176
6177         /* do the reset */
6178         val = GRC_MISC_CFG_CORECLK_RESET;
6179
6180         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6181                 if (tr32(0x7e2c) == 0x60) {
6182                         tw32(0x7e2c, 0x20);
6183                 }
6184                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6185                         tw32(GRC_MISC_CFG, (1 << 29));
6186                         val |= (1 << 29);
6187                 }
6188         }
6189
6190         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6191                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6192                 tw32(GRC_VCPU_EXT_CTRL,
6193                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6194         }
6195
6196         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6197                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6198         tw32(GRC_MISC_CFG, val);
6199
6200         /* restore 5701 hardware bug workaround write method */
6201         tp->write32 = write_op;
6202
6203         /* Unfortunately, we have to delay before the PCI read back.
6204          * Some 575X chips even will not respond to a PCI cfg access
6205          * when the reset command is given to the chip.
6206          *
6207          * How do these hardware designers expect things to work
6208          * properly if the PCI write is posted for a long period
6209          * of time?  It is always necessary to have some method by
6210          * which a register read back can occur to push the write
6211          * out which does the reset.
6212          *
6213          * For most tg3 variants the trick below was working.
6214          * Ho hum...
6215          */
6216         udelay(120);
6217
6218         /* Flush PCI posted writes.  The normal MMIO registers
6219          * are inaccessible at this time so this is the only
6220          * way to make this reliably (actually, this is no longer
6221          * the case, see above).  I tried to use indirect
6222          * register read/write but this upset some 5701 variants.
6223          */
6224         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6225
6226         udelay(120);
6227
6228         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6229                 u16 val16;
6230
6231                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6232                         int i;
6233                         u32 cfg_val;
6234
6235                         /* Wait for link training to complete.  */
6236                         for (i = 0; i < 5000; i++)
6237                                 udelay(100);
6238
6239                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6240                         pci_write_config_dword(tp->pdev, 0xc4,
6241                                                cfg_val | (1 << 15));
6242                 }
6243
6244                 /* Clear the "no snoop" and "relaxed ordering" bits. */
6245                 pci_read_config_word(tp->pdev,
6246                                      tp->pcie_cap + PCI_EXP_DEVCTL,
6247                                      &val16);
6248                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6249                            PCI_EXP_DEVCTL_NOSNOOP_EN);
6250                 /*
6251                  * Older PCIe devices only support the 128 byte
6252                  * MPS setting.  Enforce the restriction.
6253                  */
6254                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6255                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6256                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6257                 pci_write_config_word(tp->pdev,
6258                                       tp->pcie_cap + PCI_EXP_DEVCTL,
6259                                       val16);
6260
6261                 pcie_set_readrq(tp->pdev, 4096);
6262
6263                 /* Clear error status */
6264                 pci_write_config_word(tp->pdev,
6265                                       tp->pcie_cap + PCI_EXP_DEVSTA,
6266                                       PCI_EXP_DEVSTA_CED |
6267                                       PCI_EXP_DEVSTA_NFED |
6268                                       PCI_EXP_DEVSTA_FED |
6269                                       PCI_EXP_DEVSTA_URD);
6270         }
6271
6272         tg3_restore_pci_state(tp);
6273
6274         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6275
6276         val = 0;
6277         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6278                 val = tr32(MEMARB_MODE);
6279         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6280
6281         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6282                 tg3_stop_fw(tp);
6283                 tw32(0x5000, 0x400);
6284         }
6285
6286         tw32(GRC_MODE, tp->grc_mode);
6287
6288         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6289                 val = tr32(0xc4);
6290
6291                 tw32(0xc4, val | (1 << 15));
6292         }
6293
6294         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6295             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6296                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6297                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6298                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6299                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6300         }
6301
6302         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6303                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6304                 tw32_f(MAC_MODE, tp->mac_mode);
6305         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6306                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6307                 tw32_f(MAC_MODE, tp->mac_mode);
6308         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6309                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6310                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6311                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6312                 tw32_f(MAC_MODE, tp->mac_mode);
6313         } else
6314                 tw32_f(MAC_MODE, 0);
6315         udelay(40);
6316
6317         tg3_mdio_start(tp);
6318
6319         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6320
6321         err = tg3_poll_fw(tp);
6322         if (err)
6323                 return err;
6324
6325         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6326             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6327                 val = tr32(0x7c00);
6328
6329                 tw32(0x7c00, val | (1 << 25));
6330         }
6331
6332         /* Reprobe ASF enable state.  */
6333         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6334         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6335         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6336         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6337                 u32 nic_cfg;
6338
6339                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6340                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6341                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
6342                         tp->last_event_jiffies = jiffies;
6343                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
6344                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6345                 }
6346         }
6347
6348         return 0;
6349 }
6350
6351 /* tp->lock is held. */
6352 static void tg3_stop_fw(struct tg3 *tp)
6353 {
6354         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6355            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
6356                 /* Wait for RX cpu to ACK the previous event. */
6357                 tg3_wait_for_event_ack(tp);
6358
6359                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
6360
6361                 tg3_generate_fw_event(tp);
6362
6363                 /* Wait for RX cpu to ACK this event. */
6364                 tg3_wait_for_event_ack(tp);
6365         }
6366 }
6367
6368 /* tp->lock is held. */
6369 static int tg3_halt(struct tg3 *tp, int kind, int silent)
6370 {
6371         int err;
6372
6373         tg3_stop_fw(tp);
6374
6375         tg3_write_sig_pre_reset(tp, kind);
6376
6377         tg3_abort_hw(tp, silent);
6378         err = tg3_chip_reset(tp);
6379
6380         __tg3_set_mac_addr(tp, 0);
6381
6382         tg3_write_sig_legacy(tp, kind);
6383         tg3_write_sig_post_reset(tp, kind);
6384
6385         if (err)
6386                 return err;
6387
6388         return 0;
6389 }
6390
6391 #define RX_CPU_SCRATCH_BASE     0x30000
6392 #define RX_CPU_SCRATCH_SIZE     0x04000
6393 #define TX_CPU_SCRATCH_BASE     0x34000
6394 #define TX_CPU_SCRATCH_SIZE     0x04000
6395
6396 /* tp->lock is held. */
6397 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6398 {
6399         int i;
6400
6401         BUG_ON(offset == TX_CPU_BASE &&
6402             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
6403
6404         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6405                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6406
6407                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6408                 return 0;
6409         }
6410         if (offset == RX_CPU_BASE) {
6411                 for (i = 0; i < 10000; i++) {
6412                         tw32(offset + CPU_STATE, 0xffffffff);
6413                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6414                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6415                                 break;
6416                 }
6417
6418                 tw32(offset + CPU_STATE, 0xffffffff);
6419                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
6420                 udelay(10);
6421         } else {
6422                 for (i = 0; i < 10000; i++) {
6423                         tw32(offset + CPU_STATE, 0xffffffff);
6424                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6425                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6426                                 break;
6427                 }
6428         }
6429
6430         if (i >= 10000) {
6431                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6432                        "and %s CPU\n",
6433                        tp->dev->name,
6434                        (offset == RX_CPU_BASE ? "RX" : "TX"));
6435                 return -ENODEV;
6436         }
6437
6438         /* Clear firmware's nvram arbitration. */
6439         if (tp->tg3_flags & TG3_FLAG_NVRAM)
6440                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
6441         return 0;
6442 }
6443
6444 struct fw_info {
6445         unsigned int fw_base;
6446         unsigned int fw_len;
6447         const __be32 *fw_data;
6448 };
6449
6450 /* tp->lock is held. */
6451 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6452                                  int cpu_scratch_size, struct fw_info *info)
6453 {
6454         int err, lock_err, i;
6455         void (*write_op)(struct tg3 *, u32, u32);
6456
6457         if (cpu_base == TX_CPU_BASE &&
6458             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6459                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6460                        "TX cpu firmware on %s which is 5705.\n",
6461                        tp->dev->name);
6462                 return -EINVAL;
6463         }
6464
6465         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6466                 write_op = tg3_write_mem;
6467         else
6468                 write_op = tg3_write_indirect_reg32;
6469
6470         /* It is possible that bootcode is still loading at this point.
6471          * Get the nvram lock first before halting the cpu.
6472          */
6473         lock_err = tg3_nvram_lock(tp);
6474         err = tg3_halt_cpu(tp, cpu_base);
6475         if (!lock_err)
6476                 tg3_nvram_unlock(tp);
6477         if (err)
6478                 goto out;
6479
6480         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6481                 write_op(tp, cpu_scratch_base + i, 0);
6482         tw32(cpu_base + CPU_STATE, 0xffffffff);
6483         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
6484         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
6485                 write_op(tp, (cpu_scratch_base +
6486                               (info->fw_base & 0xffff) +
6487                               (i * sizeof(u32))),
6488                               be32_to_cpu(info->fw_data[i]));
6489
6490         err = 0;
6491
6492 out:
6493         return err;
6494 }
6495
6496 /* tp->lock is held. */
6497 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6498 {
6499         struct fw_info info;
6500         const __be32 *fw_data;
6501         int err, i;
6502
6503         fw_data = (void *)tp->fw->data;
6504
6505         /* Firmware blob starts with version numbers, followed by
6506            start address and length. We are setting complete length.
6507            length = end_address_of_bss - start_address_of_text.
6508            Remainder is the blob to be loaded contiguously
6509            from start address. */
6510
6511         info.fw_base = be32_to_cpu(fw_data[1]);
6512         info.fw_len = tp->fw->size - 12;
6513         info.fw_data = &fw_data[3];
6514
6515         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6516                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6517                                     &info);
6518         if (err)
6519                 return err;
6520
6521         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6522                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6523                                     &info);
6524         if (err)
6525                 return err;
6526
6527         /* Now startup only the RX cpu. */
6528         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6529         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6530
6531         for (i = 0; i < 5; i++) {
6532                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
6533                         break;
6534                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6535                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
6536                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6537                 udelay(1000);
6538         }
6539         if (i >= 5) {
6540                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6541                        "to set RX CPU PC, is %08x should be %08x\n",
6542                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
6543                        info.fw_base);
6544                 return -ENODEV;
6545         }
6546         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6547         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
6548
6549         return 0;
6550 }
6551
6552 /* 5705 needs a special version of the TSO firmware.  */
6553
6554 /* tp->lock is held. */
6555 static int tg3_load_tso_firmware(struct tg3 *tp)
6556 {
6557         struct fw_info info;
6558         const __be32 *fw_data;
6559         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6560         int err, i;
6561
6562         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6563                 return 0;
6564
6565         fw_data = (void *)tp->fw->data;
6566
6567         /* Firmware blob starts with version numbers, followed by
6568            start address and length. We are setting complete length.
6569            length = end_address_of_bss - start_address_of_text.
6570            Remainder is the blob to be loaded contiguously
6571            from start address. */
6572
6573         info.fw_base = be32_to_cpu(fw_data[1]);
6574         cpu_scratch_size = tp->fw_len;
6575         info.fw_len = tp->fw->size - 12;
6576         info.fw_data = &fw_data[3];
6577
6578         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6579                 cpu_base = RX_CPU_BASE;
6580                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6581         } else {
6582                 cpu_base = TX_CPU_BASE;
6583                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6584                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6585         }
6586
6587         err = tg3_load_firmware_cpu(tp, cpu_base,
6588                                     cpu_scratch_base, cpu_scratch_size,
6589                                     &info);
6590         if (err)
6591                 return err;
6592
6593         /* Now startup the cpu. */
6594         tw32(cpu_base + CPU_STATE, 0xffffffff);
6595         tw32_f(cpu_base + CPU_PC, info.fw_base);
6596
6597         for (i = 0; i < 5; i++) {
6598                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
6599                         break;
6600                 tw32(cpu_base + CPU_STATE, 0xffffffff);
6601                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
6602                 tw32_f(cpu_base + CPU_PC, info.fw_base);
6603                 udelay(1000);
6604         }
6605         if (i >= 5) {
6606                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6607                        "to set CPU PC, is %08x should be %08x\n",
6608                        tp->dev->name, tr32(cpu_base + CPU_PC),
6609                        info.fw_base);
6610                 return -ENODEV;
6611         }
6612         tw32(cpu_base + CPU_STATE, 0xffffffff);
6613         tw32_f(cpu_base + CPU_MODE,  0x00000000);
6614         return 0;
6615 }
6616
6617
6618 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6619 {
6620         struct tg3 *tp = netdev_priv(dev);
6621         struct sockaddr *addr = p;
6622         int err = 0, skip_mac_1 = 0;
6623
6624         if (!is_valid_ether_addr(addr->sa_data))
6625                 return -EINVAL;
6626
6627         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6628
6629         if (!netif_running(dev))
6630                 return 0;
6631
6632         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6633                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6634
6635                 addr0_high = tr32(MAC_ADDR_0_HIGH);
6636                 addr0_low = tr32(MAC_ADDR_0_LOW);
6637                 addr1_high = tr32(MAC_ADDR_1_HIGH);
6638                 addr1_low = tr32(MAC_ADDR_1_LOW);
6639
6640                 /* Skip MAC addr 1 if ASF is using it. */
6641                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6642                     !(addr1_high == 0 && addr1_low == 0))
6643                         skip_mac_1 = 1;
6644         }
6645         spin_lock_bh(&tp->lock);
6646         __tg3_set_mac_addr(tp, skip_mac_1);
6647         spin_unlock_bh(&tp->lock);
6648
6649         return err;
6650 }
6651
6652 /* tp->lock is held. */
6653 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6654                            dma_addr_t mapping, u32 maxlen_flags,
6655                            u32 nic_addr)
6656 {
6657         tg3_write_mem(tp,
6658                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6659                       ((u64) mapping >> 32));
6660         tg3_write_mem(tp,
6661                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6662                       ((u64) mapping & 0xffffffff));
6663         tg3_write_mem(tp,
6664                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6665                        maxlen_flags);
6666
6667         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6668                 tg3_write_mem(tp,
6669                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6670                               nic_addr);
6671 }
6672
6673 static void __tg3_set_rx_mode(struct net_device *);
6674 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6675 {
6676         tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6677         tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6678         tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6679         tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6680         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6681                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6682                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6683         }
6684         tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6685         tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6686         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6687                 u32 val = ec->stats_block_coalesce_usecs;
6688
6689                 if (!netif_carrier_ok(tp->dev))
6690                         val = 0;
6691
6692                 tw32(HOSTCC_STAT_COAL_TICKS, val);
6693         }
6694 }
6695
6696 /* tp->lock is held. */
6697 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6698 {
6699         u32 val, rdmac_mode;
6700         int i, err, limit;
6701
6702         tg3_disable_ints(tp);
6703
6704         tg3_stop_fw(tp);
6705
6706         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6707
6708         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6709                 tg3_abort_hw(tp, 1);
6710         }
6711
6712         if (reset_phy &&
6713             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
6714                 tg3_phy_reset(tp);
6715
6716         err = tg3_chip_reset(tp);
6717         if (err)
6718                 return err;
6719
6720         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6721
6722         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
6723                 val = tr32(TG3_CPMU_CTRL);
6724                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
6725                 tw32(TG3_CPMU_CTRL, val);
6726
6727                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
6728                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
6729                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
6730                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
6731
6732                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
6733                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
6734                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
6735                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
6736
6737                 val = tr32(TG3_CPMU_HST_ACC);
6738                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
6739                 val |= CPMU_HST_ACC_MACCLK_6_25;
6740                 tw32(TG3_CPMU_HST_ACC, val);
6741         }
6742
6743         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6744                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
6745                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
6746                        PCIE_PWR_MGMT_L1_THRESH_4MS;
6747                 tw32(PCIE_PWR_MGMT_THRESH, val);
6748
6749                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
6750                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
6751
6752                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
6753         }
6754
6755         if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
6756                 val = tr32(TG3_PCIE_LNKCTL);
6757                 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG)
6758                         val |= TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
6759                 else
6760                         val &= ~TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
6761                 tw32(TG3_PCIE_LNKCTL, val);
6762         }
6763
6764         /* This works around an issue with Athlon chipsets on
6765          * B3 tigon3 silicon.  This bit has no effect on any
6766          * other revision.  But do not set this on PCI Express
6767          * chips and don't even touch the clocks if the CPMU is present.
6768          */
6769         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
6770                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6771                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6772                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6773         }
6774
6775         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6776             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6777                 val = tr32(TG3PCI_PCISTATE);
6778                 val |= PCISTATE_RETRY_SAME_DMA;
6779                 tw32(TG3PCI_PCISTATE, val);
6780         }
6781
6782         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6783                 /* Allow reads and writes to the
6784                  * APE register and memory space.
6785                  */
6786                 val = tr32(TG3PCI_PCISTATE);
6787                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6788                        PCISTATE_ALLOW_APE_SHMEM_WR;
6789                 tw32(TG3PCI_PCISTATE, val);
6790         }
6791
6792         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6793                 /* Enable some hw fixes.  */
6794                 val = tr32(TG3PCI_MSI_DATA);
6795                 val |= (1 << 26) | (1 << 28) | (1 << 29);
6796                 tw32(TG3PCI_MSI_DATA, val);
6797         }
6798
6799         /* Descriptor ring init may make accesses to the
6800          * NIC SRAM area to setup the TX descriptors, so we
6801          * can only do this after the hardware has been
6802          * successfully reset.
6803          */
6804         err = tg3_init_rings(tp);
6805         if (err)
6806                 return err;
6807
6808         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
6809             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
6810                 /* This value is determined during the probe time DMA
6811                  * engine test, tg3_test_dma.
6812                  */
6813                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6814         }
6815
6816         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6817                           GRC_MODE_4X_NIC_SEND_RINGS |
6818                           GRC_MODE_NO_TX_PHDR_CSUM |
6819                           GRC_MODE_NO_RX_PHDR_CSUM);
6820         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
6821
6822         /* Pseudo-header checksum is done by hardware logic and not
6823          * the offload processers, so make the chip do the pseudo-
6824          * header checksums on receive.  For transmit it is more
6825          * convenient to do the pseudo-header checksum in software
6826          * as Linux does that on transmit for us in all cases.
6827          */
6828         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
6829
6830         tw32(GRC_MODE,
6831              tp->grc_mode |
6832              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6833
6834         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
6835         val = tr32(GRC_MISC_CFG);
6836         val &= ~0xff;
6837         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6838         tw32(GRC_MISC_CFG, val);
6839
6840         /* Initialize MBUF/DESC pool. */
6841         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6842                 /* Do nothing.  */
6843         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6844                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6845                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6846                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6847                 else
6848                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6849                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6850                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6851         }
6852         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6853                 int fw_len;
6854
6855                 fw_len = tp->fw_len;
6856                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6857                 tw32(BUFMGR_MB_POOL_ADDR,
6858                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6859                 tw32(BUFMGR_MB_POOL_SIZE,
6860                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6861         }
6862
6863         if (tp->dev->mtu <= ETH_DATA_LEN) {
6864                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6865                      tp->bufmgr_config.mbuf_read_dma_low_water);
6866                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6867                      tp->bufmgr_config.mbuf_mac_rx_low_water);
6868                 tw32(BUFMGR_MB_HIGH_WATER,
6869                      tp->bufmgr_config.mbuf_high_water);
6870         } else {
6871                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6872                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6873                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6874                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6875                 tw32(BUFMGR_MB_HIGH_WATER,
6876                      tp->bufmgr_config.mbuf_high_water_jumbo);
6877         }
6878         tw32(BUFMGR_DMA_LOW_WATER,
6879              tp->bufmgr_config.dma_low_water);
6880         tw32(BUFMGR_DMA_HIGH_WATER,
6881              tp->bufmgr_config.dma_high_water);
6882
6883         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6884         for (i = 0; i < 2000; i++) {
6885                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6886                         break;
6887                 udelay(10);
6888         }
6889         if (i >= 2000) {
6890                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6891                        tp->dev->name);
6892                 return -ENODEV;
6893         }
6894
6895         /* Setup replenish threshold. */
6896         val = tp->rx_pending / 8;
6897         if (val == 0)
6898                 val = 1;
6899         else if (val > tp->rx_std_max_post)
6900                 val = tp->rx_std_max_post;
6901         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6902                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6903                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6904
6905                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6906                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6907         }
6908
6909         tw32(RCVBDI_STD_THRESH, val);
6910
6911         /* Initialize TG3_BDINFO's at:
6912          *  RCVDBDI_STD_BD:     standard eth size rx ring
6913          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
6914          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
6915          *
6916          * like so:
6917          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
6918          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
6919          *                              ring attribute flags
6920          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
6921          *
6922          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6923          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6924          *
6925          * The size of each ring is fixed in the firmware, but the location is
6926          * configurable.
6927          */
6928         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6929              ((u64) tp->rx_std_mapping >> 32));
6930         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6931              ((u64) tp->rx_std_mapping & 0xffffffff));
6932         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6933              NIC_SRAM_RX_BUFFER_DESC);
6934
6935         /* Don't even try to program the JUMBO/MINI buffer descriptor
6936          * configs on 5705.
6937          */
6938         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6939                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6940                      RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6941         } else {
6942                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6943                      RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6944
6945                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6946                      BDINFO_FLAGS_DISABLED);
6947
6948                 /* Setup replenish threshold. */
6949                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6950
6951                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6952                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6953                              ((u64) tp->rx_jumbo_mapping >> 32));
6954                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6955                              ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6956                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6957                              RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6958                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6959                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6960                 } else {
6961                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6962                              BDINFO_FLAGS_DISABLED);
6963                 }
6964
6965         }
6966
6967         /* There is only one send ring on 5705/5750, no need to explicitly
6968          * disable the others.
6969          */
6970         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6971                 /* Clear out send RCB ring in SRAM. */
6972                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6973                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6974                                       BDINFO_FLAGS_DISABLED);
6975         }
6976
6977         tp->tx_prod = 0;
6978         tp->tx_cons = 0;
6979         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6980         tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6981
6982         tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6983                        tp->tx_desc_mapping,
6984                        (TG3_TX_RING_SIZE <<
6985                         BDINFO_FLAGS_MAXLEN_SHIFT),
6986                        NIC_SRAM_TX_BUFFER_DESC);
6987
6988         /* There is only one receive return ring on 5705/5750, no need
6989          * to explicitly disable the others.
6990          */
6991         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6992                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6993                      i += TG3_BDINFO_SIZE) {
6994                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6995                                       BDINFO_FLAGS_DISABLED);
6996                 }
6997         }
6998
6999         tp->rx_rcb_ptr = 0;
7000         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
7001
7002         tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
7003                        tp->rx_rcb_mapping,
7004                        (TG3_RX_RCB_RING_SIZE(tp) <<
7005                         BDINFO_FLAGS_MAXLEN_SHIFT),
7006                        0);
7007
7008         tp->rx_std_ptr = tp->rx_pending;
7009         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
7010                      tp->rx_std_ptr);
7011
7012         tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7013                                                 tp->rx_jumbo_pending : 0;
7014         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
7015                      tp->rx_jumbo_ptr);
7016
7017         /* Initialize MAC address and backoff seed. */
7018         __tg3_set_mac_addr(tp, 0);
7019
7020         /* MTU + ethernet header + FCS + optional VLAN tag */
7021         tw32(MAC_RX_MTU_SIZE,
7022              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7023
7024         /* The slot time is changed by tg3_setup_phy if we
7025          * run at gigabit with half duplex.
7026          */
7027         tw32(MAC_TX_LENGTHS,
7028              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7029              (6 << TX_LENGTHS_IPG_SHIFT) |
7030              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7031
7032         /* Receive rules. */
7033         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7034         tw32(RCVLPC_CONFIG, 0x0181);
7035
7036         /* Calculate RDMAC_MODE setting early, we need it to determine
7037          * the RCVLPC_STATE_ENABLE mask.
7038          */
7039         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7040                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7041                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7042                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7043                       RDMAC_MODE_LNGREAD_ENAB);
7044
7045         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7046             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7047             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7048                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7049                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7050                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7051
7052         /* If statement applies to 5705 and 5750 PCI devices only */
7053         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7054              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7055             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7056                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7057                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7058                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7059                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7060                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7061                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7062                 }
7063         }
7064
7065         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7066                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7067
7068         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7069                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7070
7071         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7072             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7073                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7074
7075         /* Receive/send statistics. */
7076         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7077                 val = tr32(RCVLPC_STATS_ENABLE);
7078                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7079                 tw32(RCVLPC_STATS_ENABLE, val);
7080         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7081                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7082                 val = tr32(RCVLPC_STATS_ENABLE);
7083                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7084                 tw32(RCVLPC_STATS_ENABLE, val);
7085         } else {
7086                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7087         }
7088         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7089         tw32(SNDDATAI_STATSENAB, 0xffffff);
7090         tw32(SNDDATAI_STATSCTRL,
7091              (SNDDATAI_SCTRL_ENABLE |
7092               SNDDATAI_SCTRL_FASTUPD));
7093
7094         /* Setup host coalescing engine. */
7095         tw32(HOSTCC_MODE, 0);
7096         for (i = 0; i < 2000; i++) {
7097                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7098                         break;
7099                 udelay(10);
7100         }
7101
7102         __tg3_set_coalesce(tp, &tp->coal);
7103
7104         /* set status block DMA address */
7105         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7106              ((u64) tp->status_mapping >> 32));
7107         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7108              ((u64) tp->status_mapping & 0xffffffff));
7109
7110         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7111                 /* Status/statistics block address.  See tg3_timer,
7112                  * the tg3_periodic_fetch_stats call there, and
7113                  * tg3_get_stats to see how this works for 5705/5750 chips.
7114                  */
7115                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7116                      ((u64) tp->stats_mapping >> 32));
7117                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7118                      ((u64) tp->stats_mapping & 0xffffffff));
7119                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7120                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7121         }
7122
7123         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7124
7125         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7126         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7127         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7128                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7129
7130         /* Clear statistics/status block in chip, and status block in ram. */
7131         for (i = NIC_SRAM_STATS_BLK;
7132              i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7133              i += sizeof(u32)) {
7134                 tg3_write_mem(tp, i, 0);
7135                 udelay(40);
7136         }
7137         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
7138
7139         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7140                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7141                 /* reset to prevent losing 1st rx packet intermittently */
7142                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7143                 udelay(10);
7144         }
7145
7146         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7147                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7148         else
7149                 tp->mac_mode = 0;
7150         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7151                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7152         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7153             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7154             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7155                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7156         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7157         udelay(40);
7158
7159         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7160          * If TG3_FLG2_IS_NIC is zero, we should read the
7161          * register to preserve the GPIO settings for LOMs. The GPIOs,
7162          * whether used as inputs or outputs, are set by boot code after
7163          * reset.
7164          */
7165         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7166                 u32 gpio_mask;
7167
7168                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7169                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7170                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7171
7172                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7173                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7174                                      GRC_LCLCTRL_GPIO_OUTPUT3;
7175
7176                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7177                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7178
7179                 tp->grc_local_ctrl &= ~gpio_mask;
7180                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7181
7182                 /* GPIO1 must be driven high for eeprom write protect */
7183                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7184                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7185                                                GRC_LCLCTRL_GPIO_OUTPUT1);
7186         }
7187         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7188         udelay(100);
7189
7190         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
7191
7192         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7193                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7194                 udelay(40);
7195         }
7196
7197         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7198                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7199                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7200                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7201                WDMAC_MODE_LNGREAD_ENAB);
7202
7203         /* If statement applies to 5705 and 5750 PCI devices only */
7204         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7205              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7206             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7207                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
7208                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7209                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7210                         /* nothing */
7211                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7212                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7213                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7214                         val |= WDMAC_MODE_RX_ACCEL;
7215                 }
7216         }
7217
7218         /* Enable host coalescing bug fix */
7219         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7220                 val |= WDMAC_MODE_STATUS_TAG_FIX;
7221
7222         tw32_f(WDMAC_MODE, val);
7223         udelay(40);
7224
7225         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7226                 u16 pcix_cmd;
7227
7228                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7229                                      &pcix_cmd);
7230                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7231                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7232                         pcix_cmd |= PCI_X_CMD_READ_2K;
7233                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7234                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7235                         pcix_cmd |= PCI_X_CMD_READ_2K;
7236                 }
7237                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7238                                       pcix_cmd);
7239         }
7240
7241         tw32_f(RDMAC_MODE, rdmac_mode);
7242         udelay(40);
7243
7244         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7245         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7246                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7247
7248         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7249                 tw32(SNDDATAC_MODE,
7250                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7251         else
7252                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7253
7254         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7255         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7256         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7257         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7258         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7259                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7260         tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7261         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7262
7263         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7264                 err = tg3_load_5701_a0_firmware_fix(tp);
7265                 if (err)
7266                         return err;
7267         }
7268
7269         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7270                 err = tg3_load_tso_firmware(tp);
7271                 if (err)
7272                         return err;
7273         }
7274
7275         tp->tx_mode = TX_MODE_ENABLE;
7276         tw32_f(MAC_TX_MODE, tp->tx_mode);
7277         udelay(100);
7278
7279         tp->rx_mode = RX_MODE_ENABLE;
7280         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7281                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7282
7283         tw32_f(MAC_RX_MODE, tp->rx_mode);
7284         udelay(10);
7285
7286         tw32(MAC_LED_CTRL, tp->led_ctrl);
7287
7288         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7289         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7290                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7291                 udelay(10);
7292         }
7293         tw32_f(MAC_RX_MODE, tp->rx_mode);
7294         udelay(10);
7295
7296         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7297                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7298                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7299                         /* Set drive transmission level to 1.2V  */
7300                         /* only if the signal pre-emphasis bit is not set  */
7301                         val = tr32(MAC_SERDES_CFG);
7302                         val &= 0xfffff000;
7303                         val |= 0x880;
7304                         tw32(MAC_SERDES_CFG, val);
7305                 }
7306                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7307                         tw32(MAC_SERDES_CFG, 0x616000);
7308         }
7309
7310         /* Prevent chip from dropping frames when flow control
7311          * is enabled.
7312          */
7313         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7314
7315         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7316             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7317                 /* Use hardware link auto-negotiation */
7318                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7319         }
7320
7321         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7322             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7323                 u32 tmp;
7324
7325                 tmp = tr32(SERDES_RX_CTRL);
7326                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7327                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7328                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7329                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7330         }
7331
7332         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7333                 if (tp->link_config.phy_is_low_power) {
7334                         tp->link_config.phy_is_low_power = 0;
7335                         tp->link_config.speed = tp->link_config.orig_speed;
7336                         tp->link_config.duplex = tp->link_config.orig_duplex;
7337                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
7338                 }
7339
7340                 err = tg3_setup_phy(tp, 0);
7341                 if (err)
7342                         return err;
7343
7344                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7345                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
7346                         u32 tmp;
7347
7348                         /* Clear CRC stats. */
7349                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7350                                 tg3_writephy(tp, MII_TG3_TEST1,
7351                                              tmp | MII_TG3_TEST1_CRC_EN);
7352                                 tg3_readphy(tp, 0x14, &tmp);
7353                         }
7354                 }
7355         }
7356
7357         __tg3_set_rx_mode(tp->dev);
7358
7359         /* Initialize receive rules. */
7360         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
7361         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7362         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
7363         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7364
7365         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7366             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7367                 limit = 8;
7368         else
7369                 limit = 16;
7370         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7371                 limit -= 4;
7372         switch (limit) {
7373         case 16:
7374                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
7375         case 15:
7376                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
7377         case 14:
7378                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
7379         case 13:
7380                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
7381         case 12:
7382                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
7383         case 11:
7384                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
7385         case 10:
7386                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
7387         case 9:
7388                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
7389         case 8:
7390                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
7391         case 7:
7392                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
7393         case 6:
7394                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
7395         case 5:
7396                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
7397         case 4:
7398                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
7399         case 3:
7400                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
7401         case 2:
7402         case 1:
7403
7404         default:
7405                 break;
7406         }
7407
7408         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7409                 /* Write our heartbeat update interval to APE. */
7410                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7411                                 APE_HOST_HEARTBEAT_INT_DISABLE);
7412
7413         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7414
7415         return 0;
7416 }
7417
7418 /* Called at device open time to get the chip ready for
7419  * packet processing.  Invoked with tp->lock held.
7420  */
7421 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7422 {
7423         tg3_switch_clocks(tp);
7424
7425         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7426
7427         return tg3_reset_hw(tp, reset_phy);
7428 }
7429
7430 #define TG3_STAT_ADD32(PSTAT, REG) \
7431 do {    u32 __val = tr32(REG); \
7432         (PSTAT)->low += __val; \
7433         if ((PSTAT)->low < __val) \
7434                 (PSTAT)->high += 1; \
7435 } while (0)
7436
7437 static void tg3_periodic_fetch_stats(struct tg3 *tp)
7438 {
7439         struct tg3_hw_stats *sp = tp->hw_stats;
7440
7441         if (!netif_carrier_ok(tp->dev))
7442                 return;
7443
7444         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7445         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7446         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7447         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7448         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7449         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7450         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7451         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7452         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7453         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7454         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7455         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7456         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7457
7458         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7459         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7460         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7461         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7462         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7463         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7464         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7465         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7466         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7467         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7468         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7469         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7470         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7471         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
7472
7473         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7474         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7475         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
7476 }
7477
7478 static void tg3_timer(unsigned long __opaque)
7479 {
7480         struct tg3 *tp = (struct tg3 *) __opaque;
7481
7482         if (tp->irq_sync)
7483                 goto restart_timer;
7484
7485         spin_lock(&tp->lock);
7486
7487         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7488                 /* All of this garbage is because when using non-tagged
7489                  * IRQ status the mailbox/status_block protocol the chip
7490                  * uses with the cpu is race prone.
7491                  */
7492                 if (tp->hw_status->status & SD_STATUS_UPDATED) {
7493                         tw32(GRC_LOCAL_CTRL,
7494                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7495                 } else {
7496                         tw32(HOSTCC_MODE, tp->coalesce_mode |
7497                              (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
7498                 }
7499
7500                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7501                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
7502                         spin_unlock(&tp->lock);
7503                         schedule_work(&tp->reset_task);
7504                         return;
7505                 }
7506         }
7507
7508         /* This part only runs once per second. */
7509         if (!--tp->timer_counter) {
7510                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7511                         tg3_periodic_fetch_stats(tp);
7512
7513                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7514                         u32 mac_stat;
7515                         int phy_event;
7516
7517                         mac_stat = tr32(MAC_STATUS);
7518
7519                         phy_event = 0;
7520                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7521                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7522                                         phy_event = 1;
7523                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7524                                 phy_event = 1;
7525
7526                         if (phy_event)
7527                                 tg3_setup_phy(tp, 0);
7528                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7529                         u32 mac_stat = tr32(MAC_STATUS);
7530                         int need_setup = 0;
7531
7532                         if (netif_carrier_ok(tp->dev) &&
7533                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7534                                 need_setup = 1;
7535                         }
7536                         if (! netif_carrier_ok(tp->dev) &&
7537                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
7538                                          MAC_STATUS_SIGNAL_DET))) {
7539                                 need_setup = 1;
7540                         }
7541                         if (need_setup) {
7542                                 if (!tp->serdes_counter) {
7543                                         tw32_f(MAC_MODE,
7544                                              (tp->mac_mode &
7545                                               ~MAC_MODE_PORT_MODE_MASK));
7546                                         udelay(40);
7547                                         tw32_f(MAC_MODE, tp->mac_mode);
7548                                         udelay(40);
7549                                 }
7550                                 tg3_setup_phy(tp, 0);
7551                         }
7552                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7553                         tg3_serdes_parallel_detect(tp);
7554
7555                 tp->timer_counter = tp->timer_multiplier;
7556         }
7557
7558         /* Heartbeat is only sent once every 2 seconds.
7559          *
7560          * The heartbeat is to tell the ASF firmware that the host
7561          * driver is still alive.  In the event that the OS crashes,
7562          * ASF needs to reset the hardware to free up the FIFO space
7563          * that may be filled with rx packets destined for the host.
7564          * If the FIFO is full, ASF will no longer function properly.
7565          *
7566          * Unintended resets have been reported on real time kernels
7567          * where the timer doesn't run on time.  Netpoll will also have
7568          * same problem.
7569          *
7570          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7571          * to check the ring condition when the heartbeat is expiring
7572          * before doing the reset.  This will prevent most unintended
7573          * resets.
7574          */
7575         if (!--tp->asf_counter) {
7576                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7577                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7578                         tg3_wait_for_event_ack(tp);
7579
7580                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
7581                                       FWCMD_NICDRV_ALIVE3);
7582                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
7583                         /* 5 seconds timeout */
7584                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
7585
7586                         tg3_generate_fw_event(tp);
7587                 }
7588                 tp->asf_counter = tp->asf_multiplier;
7589         }
7590
7591         spin_unlock(&tp->lock);
7592
7593 restart_timer:
7594         tp->timer.expires = jiffies + tp->timer_offset;
7595         add_timer(&tp->timer);
7596 }
7597
7598 static int tg3_request_irq(struct tg3 *tp)
7599 {
7600         irq_handler_t fn;
7601         unsigned long flags;
7602         struct net_device *dev = tp->dev;
7603
7604         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7605                 fn = tg3_msi;
7606                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7607                         fn = tg3_msi_1shot;
7608                 flags = IRQF_SAMPLE_RANDOM;
7609         } else {
7610                 fn = tg3_interrupt;
7611                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7612                         fn = tg3_interrupt_tagged;
7613                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
7614         }
7615         return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
7616 }
7617
7618 static int tg3_test_interrupt(struct tg3 *tp)
7619 {
7620         struct net_device *dev = tp->dev;
7621         int err, i, intr_ok = 0;
7622
7623         if (!netif_running(dev))
7624                 return -ENODEV;
7625
7626         tg3_disable_ints(tp);
7627
7628         free_irq(tp->pdev->irq, dev);
7629
7630         err = request_irq(tp->pdev->irq, tg3_test_isr,
7631                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
7632         if (err)
7633                 return err;
7634
7635         tp->hw_status->status &= ~SD_STATUS_UPDATED;
7636         tg3_enable_ints(tp);
7637
7638         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7639                HOSTCC_MODE_NOW);
7640
7641         for (i = 0; i < 5; i++) {
7642                 u32 int_mbox, misc_host_ctrl;
7643
7644                 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
7645                                         TG3_64BIT_REG_LOW);
7646                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7647
7648                 if ((int_mbox != 0) ||
7649                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7650                         intr_ok = 1;
7651                         break;
7652                 }
7653
7654                 msleep(10);
7655         }
7656
7657         tg3_disable_ints(tp);
7658
7659         free_irq(tp->pdev->irq, dev);
7660
7661         err = tg3_request_irq(tp);
7662
7663         if (err)
7664                 return err;
7665
7666         if (intr_ok)
7667                 return 0;
7668
7669         return -EIO;
7670 }
7671
7672 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7673  * successfully restored
7674  */
7675 static int tg3_test_msi(struct tg3 *tp)
7676 {
7677         struct net_device *dev = tp->dev;
7678         int err;
7679         u16 pci_cmd;
7680
7681         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7682                 return 0;
7683
7684         /* Turn off SERR reporting in case MSI terminates with Master
7685          * Abort.
7686          */
7687         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7688         pci_write_config_word(tp->pdev, PCI_COMMAND,
7689                               pci_cmd & ~PCI_COMMAND_SERR);
7690
7691         err = tg3_test_interrupt(tp);
7692
7693         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7694
7695         if (!err)
7696                 return 0;
7697
7698         /* other failures */
7699         if (err != -EIO)
7700                 return err;
7701
7702         /* MSI test failed, go back to INTx mode */
7703         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7704                "switching to INTx mode. Please report this failure to "
7705                "the PCI maintainer and include system chipset information.\n",
7706                        tp->dev->name);
7707
7708         free_irq(tp->pdev->irq, dev);
7709         pci_disable_msi(tp->pdev);
7710
7711         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7712
7713         err = tg3_request_irq(tp);
7714         if (err)
7715                 return err;
7716
7717         /* Need to reset the chip because the MSI cycle may have terminated
7718          * with Master Abort.
7719          */
7720         tg3_full_lock(tp, 1);
7721
7722         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7723         err = tg3_init_hw(tp, 1);
7724
7725         tg3_full_unlock(tp);
7726
7727         if (err)
7728                 free_irq(tp->pdev->irq, dev);
7729
7730         return err;
7731 }
7732
7733 static int tg3_request_firmware(struct tg3 *tp)
7734 {
7735         const __be32 *fw_data;
7736
7737         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
7738                 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
7739                        tp->dev->name, tp->fw_needed);
7740                 return -ENOENT;
7741         }
7742
7743         fw_data = (void *)tp->fw->data;
7744
7745         /* Firmware blob starts with version numbers, followed by
7746          * start address and _full_ length including BSS sections
7747          * (which must be longer than the actual data, of course
7748          */
7749
7750         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
7751         if (tp->fw_len < (tp->fw->size - 12)) {
7752                 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
7753                        tp->dev->name, tp->fw_len, tp->fw_needed);
7754                 release_firmware(tp->fw);
7755                 tp->fw = NULL;
7756                 return -EINVAL;
7757         }
7758
7759         /* We no longer need firmware; we have it. */
7760         tp->fw_needed = NULL;
7761         return 0;
7762 }
7763
7764 static int tg3_open(struct net_device *dev)
7765 {
7766         struct tg3 *tp = netdev_priv(dev);
7767         int err;
7768
7769         if (tp->fw_needed) {
7770                 err = tg3_request_firmware(tp);
7771                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7772                         if (err)
7773                                 return err;
7774                 } else if (err) {
7775                         printk(KERN_WARNING "%s: TSO capability disabled.\n",
7776                                tp->dev->name);
7777                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
7778                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7779                         printk(KERN_NOTICE "%s: TSO capability restored.\n",
7780                                tp->dev->name);
7781                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
7782                 }
7783         }
7784
7785         netif_carrier_off(tp->dev);
7786
7787         err = tg3_set_power_state(tp, PCI_D0);
7788         if (err)
7789                 return err;
7790
7791         tg3_full_lock(tp, 0);
7792
7793         tg3_disable_ints(tp);
7794         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7795
7796         tg3_full_unlock(tp);
7797
7798         /* The placement of this call is tied
7799          * to the setup and use of Host TX descriptors.
7800          */
7801         err = tg3_alloc_consistent(tp);
7802         if (err)
7803                 return err;
7804
7805         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
7806                 /* All MSI supporting chips should support tagged
7807                  * status.  Assert that this is the case.
7808                  */
7809                 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7810                         printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7811                                "Not using MSI.\n", tp->dev->name);
7812                 } else if (pci_enable_msi(tp->pdev) == 0) {
7813                         u32 msi_mode;
7814
7815                         msi_mode = tr32(MSGINT_MODE);
7816                         tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7817                         tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7818                 }
7819         }
7820         err = tg3_request_irq(tp);
7821
7822         if (err) {
7823                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7824                         pci_disable_msi(tp->pdev);
7825                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7826                 }
7827                 tg3_free_consistent(tp);
7828                 return err;
7829         }
7830
7831         napi_enable(&tp->napi);
7832
7833         tg3_full_lock(tp, 0);
7834
7835         err = tg3_init_hw(tp, 1);
7836         if (err) {
7837                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7838                 tg3_free_rings(tp);
7839         } else {
7840                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7841                         tp->timer_offset = HZ;
7842                 else
7843                         tp->timer_offset = HZ / 10;
7844
7845                 BUG_ON(tp->timer_offset > HZ);
7846                 tp->timer_counter = tp->timer_multiplier =
7847                         (HZ / tp->timer_offset);
7848                 tp->asf_counter = tp->asf_multiplier =
7849                         ((HZ / tp->timer_offset) * 2);
7850
7851                 init_timer(&tp->timer);
7852                 tp->timer.expires = jiffies + tp->timer_offset;
7853                 tp->timer.data = (unsigned long) tp;
7854                 tp->timer.function = tg3_timer;
7855         }
7856
7857         tg3_full_unlock(tp);
7858
7859         if (err) {
7860                 napi_disable(&tp->napi);
7861                 free_irq(tp->pdev->irq, dev);
7862                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7863                         pci_disable_msi(tp->pdev);
7864                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7865                 }
7866                 tg3_free_consistent(tp);
7867                 return err;
7868         }
7869
7870         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7871                 err = tg3_test_msi(tp);
7872
7873                 if (err) {
7874                         tg3_full_lock(tp, 0);
7875
7876                         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7877                                 pci_disable_msi(tp->pdev);
7878                                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7879                         }
7880                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7881                         tg3_free_rings(tp);
7882                         tg3_free_consistent(tp);
7883
7884                         tg3_full_unlock(tp);
7885
7886                         napi_disable(&tp->napi);
7887
7888                         return err;
7889                 }
7890
7891                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7892                         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
7893                                 u32 val = tr32(PCIE_TRANSACTION_CFG);
7894
7895                                 tw32(PCIE_TRANSACTION_CFG,
7896                                      val | PCIE_TRANS_CFG_1SHOT_MSI);
7897                         }
7898                 }
7899         }
7900
7901         tg3_phy_start(tp);
7902
7903         tg3_full_lock(tp, 0);
7904
7905         add_timer(&tp->timer);
7906         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7907         tg3_enable_ints(tp);
7908
7909         tg3_full_unlock(tp);
7910
7911         netif_start_queue(dev);
7912
7913         return 0;
7914 }
7915
7916 #if 0
7917 /*static*/ void tg3_dump_state(struct tg3 *tp)
7918 {
7919         u32 val32, val32_2, val32_3, val32_4, val32_5;
7920         u16 val16;
7921         int i;
7922
7923         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7924         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7925         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7926                val16, val32);
7927
7928         /* MAC block */
7929         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7930                tr32(MAC_MODE), tr32(MAC_STATUS));
7931         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7932                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7933         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7934                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7935         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7936                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7937
7938         /* Send data initiator control block */
7939         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7940                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7941         printk("       SNDDATAI_STATSCTRL[%08x]\n",
7942                tr32(SNDDATAI_STATSCTRL));
7943
7944         /* Send data completion control block */
7945         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7946
7947         /* Send BD ring selector block */
7948         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7949                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7950
7951         /* Send BD initiator control block */
7952         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7953                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7954
7955         /* Send BD completion control block */
7956         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7957
7958         /* Receive list placement control block */
7959         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7960                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7961         printk("       RCVLPC_STATSCTRL[%08x]\n",
7962                tr32(RCVLPC_STATSCTRL));
7963
7964         /* Receive data and receive BD initiator control block */
7965         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7966                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7967
7968         /* Receive data completion control block */
7969         printk("DEBUG: RCVDCC_MODE[%08x]\n",
7970                tr32(RCVDCC_MODE));
7971
7972         /* Receive BD initiator control block */
7973         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7974                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7975
7976         /* Receive BD completion control block */
7977         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7978                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7979
7980         /* Receive list selector control block */
7981         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7982                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7983
7984         /* Mbuf cluster free block */
7985         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7986                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7987
7988         /* Host coalescing control block */
7989         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7990                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7991         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7992                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7993                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7994         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7995                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7996                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7997         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7998                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7999         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8000                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8001
8002         /* Memory arbiter control block */
8003         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8004                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8005
8006         /* Buffer manager control block */
8007         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8008                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8009         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8010                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8011         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8012                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8013                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8014                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8015
8016         /* Read DMA control block */
8017         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8018                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8019
8020         /* Write DMA control block */
8021         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8022                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8023
8024         /* DMA completion block */
8025         printk("DEBUG: DMAC_MODE[%08x]\n",
8026                tr32(DMAC_MODE));
8027
8028         /* GRC block */
8029         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8030                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8031         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8032                tr32(GRC_LOCAL_CTRL));
8033
8034         /* TG3_BDINFOs */
8035         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8036                tr32(RCVDBDI_JUMBO_BD + 0x0),
8037                tr32(RCVDBDI_JUMBO_BD + 0x4),
8038                tr32(RCVDBDI_JUMBO_BD + 0x8),
8039                tr32(RCVDBDI_JUMBO_BD + 0xc));
8040         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8041                tr32(RCVDBDI_STD_BD + 0x0),
8042                tr32(RCVDBDI_STD_BD + 0x4),
8043                tr32(RCVDBDI_STD_BD + 0x8),
8044                tr32(RCVDBDI_STD_BD + 0xc));
8045         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8046                tr32(RCVDBDI_MINI_BD + 0x0),
8047                tr32(RCVDBDI_MINI_BD + 0x4),
8048                tr32(RCVDBDI_MINI_BD + 0x8),
8049                tr32(RCVDBDI_MINI_BD + 0xc));
8050
8051         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8052         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8053         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8054         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8055         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8056                val32, val32_2, val32_3, val32_4);
8057
8058         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8059         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8060         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8061         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8062         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8063                val32, val32_2, val32_3, val32_4);
8064
8065         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8066         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8067         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8068         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8069         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8070         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8071                val32, val32_2, val32_3, val32_4, val32_5);
8072
8073         /* SW status block */
8074         printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8075                tp->hw_status->status,
8076                tp->hw_status->status_tag,
8077                tp->hw_status->rx_jumbo_consumer,
8078                tp->hw_status->rx_consumer,
8079                tp->hw_status->rx_mini_consumer,
8080                tp->hw_status->idx[0].rx_producer,
8081                tp->hw_status->idx[0].tx_consumer);
8082
8083         /* SW statistics block */
8084         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8085                ((u32 *)tp->hw_stats)[0],
8086                ((u32 *)tp->hw_stats)[1],
8087                ((u32 *)tp->hw_stats)[2],
8088                ((u32 *)tp->hw_stats)[3]);
8089
8090         /* Mailboxes */
8091         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8092                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8093                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8094                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8095                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
8096
8097         /* NIC side send descriptors. */
8098         for (i = 0; i < 6; i++) {
8099                 unsigned long txd;
8100
8101                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8102                         + (i * sizeof(struct tg3_tx_buffer_desc));
8103                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8104                        i,
8105                        readl(txd + 0x0), readl(txd + 0x4),
8106                        readl(txd + 0x8), readl(txd + 0xc));
8107         }
8108
8109         /* NIC side RX descriptors. */
8110         for (i = 0; i < 6; i++) {
8111                 unsigned long rxd;
8112
8113                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8114                         + (i * sizeof(struct tg3_rx_buffer_desc));
8115                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8116                        i,
8117                        readl(rxd + 0x0), readl(rxd + 0x4),
8118                        readl(rxd + 0x8), readl(rxd + 0xc));
8119                 rxd += (4 * sizeof(u32));
8120                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8121                        i,
8122                        readl(rxd + 0x0), readl(rxd + 0x4),
8123                        readl(rxd + 0x8), readl(rxd + 0xc));
8124         }
8125
8126         for (i = 0; i < 6; i++) {
8127                 unsigned long rxd;
8128
8129                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8130                         + (i * sizeof(struct tg3_rx_buffer_desc));
8131                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8132                        i,
8133                        readl(rxd + 0x0), readl(rxd + 0x4),
8134                        readl(rxd + 0x8), readl(rxd + 0xc));
8135                 rxd += (4 * sizeof(u32));
8136                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8137                        i,
8138                        readl(rxd + 0x0), readl(rxd + 0x4),
8139                        readl(rxd + 0x8), readl(rxd + 0xc));
8140         }
8141 }
8142 #endif
8143
8144 static struct net_device_stats *tg3_get_stats(struct net_device *);
8145 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8146
8147 static int tg3_close(struct net_device *dev)
8148 {
8149         struct tg3 *tp = netdev_priv(dev);
8150
8151         napi_disable(&tp->napi);
8152         cancel_work_sync(&tp->reset_task);
8153
8154         netif_stop_queue(dev);
8155
8156         del_timer_sync(&tp->timer);
8157
8158         tg3_full_lock(tp, 1);
8159 #if 0
8160         tg3_dump_state(tp);
8161 #endif
8162
8163         tg3_disable_ints(tp);
8164
8165         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8166         tg3_free_rings(tp);
8167         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8168
8169         tg3_full_unlock(tp);
8170
8171         free_irq(tp->pdev->irq, dev);
8172         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8173                 pci_disable_msi(tp->pdev);
8174                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8175         }
8176
8177         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8178                sizeof(tp->net_stats_prev));
8179         memcpy(&tp->estats_prev, tg3_get_estats(tp),
8180                sizeof(tp->estats_prev));
8181
8182         tg3_free_consistent(tp);
8183
8184         tg3_set_power_state(tp, PCI_D3hot);
8185
8186         netif_carrier_off(tp->dev);
8187
8188         return 0;
8189 }
8190
8191 static inline unsigned long get_stat64(tg3_stat64_t *val)
8192 {
8193         unsigned long ret;
8194
8195 #if (BITS_PER_LONG == 32)
8196         ret = val->low;
8197 #else
8198         ret = ((u64)val->high << 32) | ((u64)val->low);
8199 #endif
8200         return ret;
8201 }
8202
8203 static inline u64 get_estat64(tg3_stat64_t *val)
8204 {
8205        return ((u64)val->high << 32) | ((u64)val->low);
8206 }
8207
8208 static unsigned long calc_crc_errors(struct tg3 *tp)
8209 {
8210         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8211
8212         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8213             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8214              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
8215                 u32 val;
8216
8217                 spin_lock_bh(&tp->lock);
8218                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8219                         tg3_writephy(tp, MII_TG3_TEST1,
8220                                      val | MII_TG3_TEST1_CRC_EN);
8221                         tg3_readphy(tp, 0x14, &val);
8222                 } else
8223                         val = 0;
8224                 spin_unlock_bh(&tp->lock);
8225
8226                 tp->phy_crc_errors += val;
8227
8228                 return tp->phy_crc_errors;
8229         }
8230
8231         return get_stat64(&hw_stats->rx_fcs_errors);
8232 }
8233
8234 #define ESTAT_ADD(member) \
8235         estats->member =        old_estats->member + \
8236                                 get_estat64(&hw_stats->member)
8237
8238 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8239 {
8240         struct tg3_ethtool_stats *estats = &tp->estats;
8241         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8242         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8243
8244         if (!hw_stats)
8245                 return old_estats;
8246
8247         ESTAT_ADD(rx_octets);
8248         ESTAT_ADD(rx_fragments);
8249         ESTAT_ADD(rx_ucast_packets);
8250         ESTAT_ADD(rx_mcast_packets);
8251         ESTAT_ADD(rx_bcast_packets);
8252         ESTAT_ADD(rx_fcs_errors);
8253         ESTAT_ADD(rx_align_errors);
8254         ESTAT_ADD(rx_xon_pause_rcvd);
8255         ESTAT_ADD(rx_xoff_pause_rcvd);
8256         ESTAT_ADD(rx_mac_ctrl_rcvd);
8257         ESTAT_ADD(rx_xoff_entered);
8258         ESTAT_ADD(rx_frame_too_long_errors);
8259         ESTAT_ADD(rx_jabbers);
8260         ESTAT_ADD(rx_undersize_packets);
8261         ESTAT_ADD(rx_in_length_errors);
8262         ESTAT_ADD(rx_out_length_errors);
8263         ESTAT_ADD(rx_64_or_less_octet_packets);
8264         ESTAT_ADD(rx_65_to_127_octet_packets);
8265         ESTAT_ADD(rx_128_to_255_octet_packets);
8266         ESTAT_ADD(rx_256_to_511_octet_packets);
8267         ESTAT_ADD(rx_512_to_1023_octet_packets);
8268         ESTAT_ADD(rx_1024_to_1522_octet_packets);
8269         ESTAT_ADD(rx_1523_to_2047_octet_packets);
8270         ESTAT_ADD(rx_2048_to_4095_octet_packets);
8271         ESTAT_ADD(rx_4096_to_8191_octet_packets);
8272         ESTAT_ADD(rx_8192_to_9022_octet_packets);
8273
8274         ESTAT_ADD(tx_octets);
8275         ESTAT_ADD(tx_collisions);
8276         ESTAT_ADD(tx_xon_sent);
8277         ESTAT_ADD(tx_xoff_sent);
8278         ESTAT_ADD(tx_flow_control);
8279         ESTAT_ADD(tx_mac_errors);
8280         ESTAT_ADD(tx_single_collisions);
8281         ESTAT_ADD(tx_mult_collisions);
8282         ESTAT_ADD(tx_deferred);
8283         ESTAT_ADD(tx_excessive_collisions);
8284         ESTAT_ADD(tx_late_collisions);
8285         ESTAT_ADD(tx_collide_2times);
8286         ESTAT_ADD(tx_collide_3times);
8287         ESTAT_ADD(tx_collide_4times);
8288         ESTAT_ADD(tx_collide_5times);
8289         ESTAT_ADD(tx_collide_6times);
8290         ESTAT_ADD(tx_collide_7times);
8291         ESTAT_ADD(tx_collide_8times);
8292         ESTAT_ADD(tx_collide_9times);
8293         ESTAT_ADD(tx_collide_10times);
8294         ESTAT_ADD(tx_collide_11times);
8295         ESTAT_ADD(tx_collide_12times);
8296         ESTAT_ADD(tx_collide_13times);
8297         ESTAT_ADD(tx_collide_14times);
8298         ESTAT_ADD(tx_collide_15times);
8299         ESTAT_ADD(tx_ucast_packets);
8300         ESTAT_ADD(tx_mcast_packets);
8301         ESTAT_ADD(tx_bcast_packets);
8302         ESTAT_ADD(tx_carrier_sense_errors);
8303         ESTAT_ADD(tx_discards);
8304         ESTAT_ADD(tx_errors);
8305
8306         ESTAT_ADD(dma_writeq_full);
8307         ESTAT_ADD(dma_write_prioq_full);
8308         ESTAT_ADD(rxbds_empty);
8309         ESTAT_ADD(rx_discards);
8310         ESTAT_ADD(rx_errors);
8311         ESTAT_ADD(rx_threshold_hit);
8312
8313         ESTAT_ADD(dma_readq_full);
8314         ESTAT_ADD(dma_read_prioq_full);
8315         ESTAT_ADD(tx_comp_queue_full);
8316
8317         ESTAT_ADD(ring_set_send_prod_index);
8318         ESTAT_ADD(ring_status_update);
8319         ESTAT_ADD(nic_irqs);
8320         ESTAT_ADD(nic_avoided_irqs);
8321         ESTAT_ADD(nic_tx_threshold_hit);
8322
8323         return estats;
8324 }
8325
8326 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8327 {
8328         struct tg3 *tp = netdev_priv(dev);
8329         struct net_device_stats *stats = &tp->net_stats;
8330         struct net_device_stats *old_stats = &tp->net_stats_prev;
8331         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8332
8333         if (!hw_stats)
8334                 return old_stats;
8335
8336         stats->rx_packets = old_stats->rx_packets +
8337                 get_stat64(&hw_stats->rx_ucast_packets) +
8338                 get_stat64(&hw_stats->rx_mcast_packets) +
8339                 get_stat64(&hw_stats->rx_bcast_packets);
8340
8341         stats->tx_packets = old_stats->tx_packets +
8342                 get_stat64(&hw_stats->tx_ucast_packets) +
8343                 get_stat64(&hw_stats->tx_mcast_packets) +
8344                 get_stat64(&hw_stats->tx_bcast_packets);
8345
8346         stats->rx_bytes = old_stats->rx_bytes +
8347                 get_stat64(&hw_stats->rx_octets);
8348         stats->tx_bytes = old_stats->tx_bytes +
8349                 get_stat64(&hw_stats->tx_octets);
8350
8351         stats->rx_errors = old_stats->rx_errors +
8352                 get_stat64(&hw_stats->rx_errors);
8353         stats->tx_errors = old_stats->tx_errors +
8354                 get_stat64(&hw_stats->tx_errors) +
8355                 get_stat64(&hw_stats->tx_mac_errors) +
8356                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8357                 get_stat64(&hw_stats->tx_discards);
8358
8359         stats->multicast = old_stats->multicast +
8360                 get_stat64(&hw_stats->rx_mcast_packets);
8361         stats->collisions = old_stats->collisions +
8362                 get_stat64(&hw_stats->tx_collisions);
8363
8364         stats->rx_length_errors = old_stats->rx_length_errors +
8365                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8366                 get_stat64(&hw_stats->rx_undersize_packets);
8367
8368         stats->rx_over_errors = old_stats->rx_over_errors +
8369                 get_stat64(&hw_stats->rxbds_empty);
8370         stats->rx_frame_errors = old_stats->rx_frame_errors +
8371                 get_stat64(&hw_stats->rx_align_errors);
8372         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8373                 get_stat64(&hw_stats->tx_discards);
8374         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8375                 get_stat64(&hw_stats->tx_carrier_sense_errors);
8376
8377         stats->rx_crc_errors = old_stats->rx_crc_errors +
8378                 calc_crc_errors(tp);
8379
8380         stats->rx_missed_errors = old_stats->rx_missed_errors +
8381                 get_stat64(&hw_stats->rx_discards);
8382
8383         return stats;
8384 }
8385
8386 static inline u32 calc_crc(unsigned char *buf, int len)
8387 {
8388         u32 reg;
8389         u32 tmp;
8390         int j, k;
8391
8392         reg = 0xffffffff;
8393
8394         for (j = 0; j < len; j++) {
8395                 reg ^= buf[j];
8396
8397                 for (k = 0; k < 8; k++) {
8398                         tmp = reg & 0x01;
8399
8400                         reg >>= 1;
8401
8402                         if (tmp) {
8403                                 reg ^= 0xedb88320;
8404                         }
8405                 }
8406         }
8407
8408         return ~reg;
8409 }
8410
8411 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8412 {
8413         /* accept or reject all multicast frames */
8414         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8415         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8416         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8417         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8418 }
8419
8420 static void __tg3_set_rx_mode(struct net_device *dev)
8421 {
8422         struct tg3 *tp = netdev_priv(dev);
8423         u32 rx_mode;
8424
8425         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8426                                   RX_MODE_KEEP_VLAN_TAG);
8427
8428         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8429          * flag clear.
8430          */
8431 #if TG3_VLAN_TAG_USED
8432         if (!tp->vlgrp &&
8433             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8434                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8435 #else
8436         /* By definition, VLAN is disabled always in this
8437          * case.
8438          */
8439         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8440                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8441 #endif
8442
8443         if (dev->flags & IFF_PROMISC) {
8444                 /* Promiscuous mode. */
8445                 rx_mode |= RX_MODE_PROMISC;
8446         } else if (dev->flags & IFF_ALLMULTI) {
8447                 /* Accept all multicast. */
8448                 tg3_set_multi (tp, 1);
8449         } else if (dev->mc_count < 1) {
8450                 /* Reject all multicast. */
8451                 tg3_set_multi (tp, 0);
8452         } else {
8453                 /* Accept one or more multicast(s). */
8454                 struct dev_mc_list *mclist;
8455                 unsigned int i;
8456                 u32 mc_filter[4] = { 0, };
8457                 u32 regidx;
8458                 u32 bit;
8459                 u32 crc;
8460
8461                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8462                      i++, mclist = mclist->next) {
8463
8464                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8465                         bit = ~crc & 0x7f;
8466                         regidx = (bit & 0x60) >> 5;
8467                         bit &= 0x1f;
8468                         mc_filter[regidx] |= (1 << bit);
8469                 }
8470
8471                 tw32(MAC_HASH_REG_0, mc_filter[0]);
8472                 tw32(MAC_HASH_REG_1, mc_filter[1]);
8473                 tw32(MAC_HASH_REG_2, mc_filter[2]);
8474                 tw32(MAC_HASH_REG_3, mc_filter[3]);
8475         }
8476
8477         if (rx_mode != tp->rx_mode) {
8478                 tp->rx_mode = rx_mode;
8479                 tw32_f(MAC_RX_MODE, rx_mode);
8480                 udelay(10);
8481         }
8482 }
8483
8484 static void tg3_set_rx_mode(struct net_device *dev)
8485 {
8486         struct tg3 *tp = netdev_priv(dev);
8487
8488         if (!netif_running(dev))
8489                 return;
8490
8491         tg3_full_lock(tp, 0);
8492         __tg3_set_rx_mode(dev);
8493         tg3_full_unlock(tp);
8494 }
8495
8496 #define TG3_REGDUMP_LEN         (32 * 1024)
8497
8498 static int tg3_get_regs_len(struct net_device *dev)
8499 {
8500         return TG3_REGDUMP_LEN;
8501 }
8502
8503 static void tg3_get_regs(struct net_device *dev,
8504                 struct ethtool_regs *regs, void *_p)
8505 {
8506         u32 *p = _p;
8507         struct tg3 *tp = netdev_priv(dev);
8508         u8 *orig_p = _p;
8509         int i;
8510
8511         regs->version = 0;
8512
8513         memset(p, 0, TG3_REGDUMP_LEN);
8514
8515         if (tp->link_config.phy_is_low_power)
8516                 return;
8517
8518         tg3_full_lock(tp, 0);
8519
8520 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
8521 #define GET_REG32_LOOP(base,len)                \
8522 do {    p = (u32 *)(orig_p + (base));           \
8523         for (i = 0; i < len; i += 4)            \
8524                 __GET_REG32((base) + i);        \
8525 } while (0)
8526 #define GET_REG32_1(reg)                        \
8527 do {    p = (u32 *)(orig_p + (reg));            \
8528         __GET_REG32((reg));                     \
8529 } while (0)
8530
8531         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8532         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8533         GET_REG32_LOOP(MAC_MODE, 0x4f0);
8534         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8535         GET_REG32_1(SNDDATAC_MODE);
8536         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8537         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8538         GET_REG32_1(SNDBDC_MODE);
8539         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8540         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8541         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8542         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8543         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8544         GET_REG32_1(RCVDCC_MODE);
8545         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8546         GET_REG32_LOOP(RCVCC_MODE, 0x14);
8547         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8548         GET_REG32_1(MBFREE_MODE);
8549         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8550         GET_REG32_LOOP(MEMARB_MODE, 0x10);
8551         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8552         GET_REG32_LOOP(RDMAC_MODE, 0x08);
8553         GET_REG32_LOOP(WDMAC_MODE, 0x08);
8554         GET_REG32_1(RX_CPU_MODE);
8555         GET_REG32_1(RX_CPU_STATE);
8556         GET_REG32_1(RX_CPU_PGMCTR);
8557         GET_REG32_1(RX_CPU_HWBKPT);
8558         GET_REG32_1(TX_CPU_MODE);
8559         GET_REG32_1(TX_CPU_STATE);
8560         GET_REG32_1(TX_CPU_PGMCTR);
8561         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8562         GET_REG32_LOOP(FTQ_RESET, 0x120);
8563         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8564         GET_REG32_1(DMAC_MODE);
8565         GET_REG32_LOOP(GRC_MODE, 0x4c);
8566         if (tp->tg3_flags & TG3_FLAG_NVRAM)
8567                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8568
8569 #undef __GET_REG32
8570 #undef GET_REG32_LOOP
8571 #undef GET_REG32_1
8572
8573         tg3_full_unlock(tp);
8574 }
8575
8576 static int tg3_get_eeprom_len(struct net_device *dev)
8577 {
8578         struct tg3 *tp = netdev_priv(dev);
8579
8580         return tp->nvram_size;
8581 }
8582
8583 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8584 {
8585         struct tg3 *tp = netdev_priv(dev);
8586         int ret;
8587         u8  *pd;
8588         u32 i, offset, len, b_offset, b_count;
8589         __be32 val;
8590
8591         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
8592                 return -EINVAL;
8593
8594         if (tp->link_config.phy_is_low_power)
8595                 return -EAGAIN;
8596
8597         offset = eeprom->offset;
8598         len = eeprom->len;
8599         eeprom->len = 0;
8600
8601         eeprom->magic = TG3_EEPROM_MAGIC;
8602
8603         if (offset & 3) {
8604                 /* adjustments to start on required 4 byte boundary */
8605                 b_offset = offset & 3;
8606                 b_count = 4 - b_offset;
8607                 if (b_count > len) {
8608                         /* i.e. offset=1 len=2 */
8609                         b_count = len;
8610                 }
8611                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
8612                 if (ret)
8613                         return ret;
8614                 memcpy(data, ((char*)&val) + b_offset, b_count);
8615                 len -= b_count;
8616                 offset += b_count;
8617                 eeprom->len += b_count;
8618         }
8619
8620         /* read bytes upto the last 4 byte boundary */
8621         pd = &data[eeprom->len];
8622         for (i = 0; i < (len - (len & 3)); i += 4) {
8623                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
8624                 if (ret) {
8625                         eeprom->len += i;
8626                         return ret;
8627                 }
8628                 memcpy(pd + i, &val, 4);
8629         }
8630         eeprom->len += i;
8631
8632         if (len & 3) {
8633                 /* read last bytes not ending on 4 byte boundary */
8634                 pd = &data[eeprom->len];
8635                 b_count = len & 3;
8636                 b_offset = offset + len - b_count;
8637                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
8638                 if (ret)
8639                         return ret;
8640                 memcpy(pd, &val, b_count);
8641                 eeprom->len += b_count;
8642         }
8643         return 0;
8644 }
8645
8646 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
8647
8648 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8649 {
8650         struct tg3 *tp = netdev_priv(dev);
8651         int ret;
8652         u32 offset, len, b_offset, odd_len;
8653         u8 *buf;
8654         __be32 start, end;
8655
8656         if (tp->link_config.phy_is_low_power)
8657                 return -EAGAIN;
8658
8659         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
8660             eeprom->magic != TG3_EEPROM_MAGIC)
8661                 return -EINVAL;
8662
8663         offset = eeprom->offset;
8664         len = eeprom->len;
8665
8666         if ((b_offset = (offset & 3))) {
8667                 /* adjustments to start on required 4 byte boundary */
8668                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
8669                 if (ret)
8670                         return ret;
8671                 len += b_offset;
8672                 offset &= ~3;
8673                 if (len < 4)
8674                         len = 4;
8675         }
8676
8677         odd_len = 0;
8678         if (len & 3) {
8679                 /* adjustments to end on required 4 byte boundary */
8680                 odd_len = 1;
8681                 len = (len + 3) & ~3;
8682                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
8683                 if (ret)
8684                         return ret;
8685         }
8686
8687         buf = data;
8688         if (b_offset || odd_len) {
8689                 buf = kmalloc(len, GFP_KERNEL);
8690                 if (!buf)
8691                         return -ENOMEM;
8692                 if (b_offset)
8693                         memcpy(buf, &start, 4);
8694                 if (odd_len)
8695                         memcpy(buf+len-4, &end, 4);
8696                 memcpy(buf + b_offset, data, eeprom->len);
8697         }
8698
8699         ret = tg3_nvram_write_block(tp, offset, len, buf);
8700
8701         if (buf != data)
8702                 kfree(buf);
8703
8704         return ret;
8705 }
8706
8707 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8708 {
8709         struct tg3 *tp = netdev_priv(dev);
8710
8711         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8712                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8713                         return -EAGAIN;
8714                 return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
8715         }
8716
8717         cmd->supported = (SUPPORTED_Autoneg);
8718
8719         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8720                 cmd->supported |= (SUPPORTED_1000baseT_Half |
8721                                    SUPPORTED_1000baseT_Full);
8722
8723         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
8724                 cmd->supported |= (SUPPORTED_100baseT_Half |
8725                                   SUPPORTED_100baseT_Full |
8726                                   SUPPORTED_10baseT_Half |
8727                                   SUPPORTED_10baseT_Full |
8728                                   SUPPORTED_TP);
8729                 cmd->port = PORT_TP;
8730         } else {
8731                 cmd->supported |= SUPPORTED_FIBRE;
8732                 cmd->port = PORT_FIBRE;
8733         }
8734
8735         cmd->advertising = tp->link_config.advertising;
8736         if (netif_running(dev)) {
8737                 cmd->speed = tp->link_config.active_speed;
8738                 cmd->duplex = tp->link_config.active_duplex;
8739         }
8740         cmd->phy_address = PHY_ADDR;
8741         cmd->transceiver = XCVR_INTERNAL;
8742         cmd->autoneg = tp->link_config.autoneg;
8743         cmd->maxtxpkt = 0;
8744         cmd->maxrxpkt = 0;
8745         return 0;
8746 }
8747
8748 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8749 {
8750         struct tg3 *tp = netdev_priv(dev);
8751
8752         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8753                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8754                         return -EAGAIN;
8755                 return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
8756         }
8757
8758         if (cmd->autoneg != AUTONEG_ENABLE &&
8759             cmd->autoneg != AUTONEG_DISABLE)
8760                 return -EINVAL;
8761
8762         if (cmd->autoneg == AUTONEG_DISABLE &&
8763             cmd->duplex != DUPLEX_FULL &&
8764             cmd->duplex != DUPLEX_HALF)
8765                 return -EINVAL;
8766
8767         if (cmd->autoneg == AUTONEG_ENABLE) {
8768                 u32 mask = ADVERTISED_Autoneg |
8769                            ADVERTISED_Pause |
8770                            ADVERTISED_Asym_Pause;
8771
8772                 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8773                         mask |= ADVERTISED_1000baseT_Half |
8774                                 ADVERTISED_1000baseT_Full;
8775
8776                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
8777                         mask |= ADVERTISED_100baseT_Half |
8778                                 ADVERTISED_100baseT_Full |
8779                                 ADVERTISED_10baseT_Half |
8780                                 ADVERTISED_10baseT_Full |
8781                                 ADVERTISED_TP;
8782                 else
8783                         mask |= ADVERTISED_FIBRE;
8784
8785                 if (cmd->advertising & ~mask)
8786                         return -EINVAL;
8787
8788                 mask &= (ADVERTISED_1000baseT_Half |
8789                          ADVERTISED_1000baseT_Full |
8790                          ADVERTISED_100baseT_Half |
8791                          ADVERTISED_100baseT_Full |
8792                          ADVERTISED_10baseT_Half |
8793                          ADVERTISED_10baseT_Full);
8794
8795                 cmd->advertising &= mask;
8796         } else {
8797                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8798                         if (cmd->speed != SPEED_1000)
8799                                 return -EINVAL;
8800
8801                         if (cmd->duplex != DUPLEX_FULL)
8802                                 return -EINVAL;
8803                 } else {
8804                         if (cmd->speed != SPEED_100 &&
8805                             cmd->speed != SPEED_10)
8806                                 return -EINVAL;
8807                 }
8808         }
8809
8810         tg3_full_lock(tp, 0);
8811
8812         tp->link_config.autoneg = cmd->autoneg;
8813         if (cmd->autoneg == AUTONEG_ENABLE) {
8814                 tp->link_config.advertising = (cmd->advertising |
8815                                               ADVERTISED_Autoneg);
8816                 tp->link_config.speed = SPEED_INVALID;
8817                 tp->link_config.duplex = DUPLEX_INVALID;
8818         } else {
8819                 tp->link_config.advertising = 0;
8820                 tp->link_config.speed = cmd->speed;
8821                 tp->link_config.duplex = cmd->duplex;
8822         }
8823
8824         tp->link_config.orig_speed = tp->link_config.speed;
8825         tp->link_config.orig_duplex = tp->link_config.duplex;
8826         tp->link_config.orig_autoneg = tp->link_config.autoneg;
8827
8828         if (netif_running(dev))
8829                 tg3_setup_phy(tp, 1);
8830
8831         tg3_full_unlock(tp);
8832
8833         return 0;
8834 }
8835
8836 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8837 {
8838         struct tg3 *tp = netdev_priv(dev);
8839
8840         strcpy(info->driver, DRV_MODULE_NAME);
8841         strcpy(info->version, DRV_MODULE_VERSION);
8842         strcpy(info->fw_version, tp->fw_ver);
8843         strcpy(info->bus_info, pci_name(tp->pdev));
8844 }
8845
8846 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8847 {
8848         struct tg3 *tp = netdev_priv(dev);
8849
8850         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
8851             device_can_wakeup(&tp->pdev->dev))
8852                 wol->supported = WAKE_MAGIC;
8853         else
8854                 wol->supported = 0;
8855         wol->wolopts = 0;
8856         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
8857             device_can_wakeup(&tp->pdev->dev))
8858                 wol->wolopts = WAKE_MAGIC;
8859         memset(&wol->sopass, 0, sizeof(wol->sopass));
8860 }
8861
8862 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8863 {
8864         struct tg3 *tp = netdev_priv(dev);
8865         struct device *dp = &tp->pdev->dev;
8866
8867         if (wol->wolopts & ~WAKE_MAGIC)
8868                 return -EINVAL;
8869         if ((wol->wolopts & WAKE_MAGIC) &&
8870             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
8871                 return -EINVAL;
8872
8873         spin_lock_bh(&tp->lock);
8874         if (wol->wolopts & WAKE_MAGIC) {
8875                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8876                 device_set_wakeup_enable(dp, true);
8877         } else {
8878                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8879                 device_set_wakeup_enable(dp, false);
8880         }
8881         spin_unlock_bh(&tp->lock);
8882
8883         return 0;
8884 }
8885
8886 static u32 tg3_get_msglevel(struct net_device *dev)
8887 {
8888         struct tg3 *tp = netdev_priv(dev);
8889         return tp->msg_enable;
8890 }
8891
8892 static void tg3_set_msglevel(struct net_device *dev, u32 value)
8893 {
8894         struct tg3 *tp = netdev_priv(dev);
8895         tp->msg_enable = value;
8896 }
8897
8898 static int tg3_set_tso(struct net_device *dev, u32 value)
8899 {
8900         struct tg3 *tp = netdev_priv(dev);
8901
8902         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8903                 if (value)
8904                         return -EINVAL;
8905                 return 0;
8906         }
8907         if ((dev->features & NETIF_F_IPV6_CSUM) &&
8908             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
8909                 if (value) {
8910                         dev->features |= NETIF_F_TSO6;
8911                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8912                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
8913                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
8914                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8915                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8916                                 dev->features |= NETIF_F_TSO_ECN;
8917                 } else
8918                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
8919         }
8920         return ethtool_op_set_tso(dev, value);
8921 }
8922
8923 static int tg3_nway_reset(struct net_device *dev)
8924 {
8925         struct tg3 *tp = netdev_priv(dev);
8926         int r;
8927
8928         if (!netif_running(dev))
8929                 return -EAGAIN;
8930
8931         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8932                 return -EINVAL;
8933
8934         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8935                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8936                         return -EAGAIN;
8937                 r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]);
8938         } else {
8939                 u32 bmcr;
8940
8941                 spin_lock_bh(&tp->lock);
8942                 r = -EINVAL;
8943                 tg3_readphy(tp, MII_BMCR, &bmcr);
8944                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8945                     ((bmcr & BMCR_ANENABLE) ||
8946                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8947                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8948                                                    BMCR_ANENABLE);
8949                         r = 0;
8950                 }
8951                 spin_unlock_bh(&tp->lock);
8952         }
8953
8954         return r;
8955 }
8956
8957 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8958 {
8959         struct tg3 *tp = netdev_priv(dev);
8960
8961         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8962         ering->rx_mini_max_pending = 0;
8963         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8964                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8965         else
8966                 ering->rx_jumbo_max_pending = 0;
8967
8968         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
8969
8970         ering->rx_pending = tp->rx_pending;
8971         ering->rx_mini_pending = 0;
8972         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8973                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8974         else
8975                 ering->rx_jumbo_pending = 0;
8976
8977         ering->tx_pending = tp->tx_pending;
8978 }
8979
8980 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8981 {
8982         struct tg3 *tp = netdev_priv(dev);
8983         int irq_sync = 0, err = 0;
8984
8985         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8986             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
8987             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8988             (ering->tx_pending <= MAX_SKB_FRAGS) ||
8989             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
8990              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
8991                 return -EINVAL;
8992
8993         if (netif_running(dev)) {
8994                 tg3_phy_stop(tp);
8995                 tg3_netif_stop(tp);
8996                 irq_sync = 1;
8997         }
8998
8999         tg3_full_lock(tp, irq_sync);
9000
9001         tp->rx_pending = ering->rx_pending;
9002
9003         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9004             tp->rx_pending > 63)
9005                 tp->rx_pending = 63;
9006         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9007         tp->tx_pending = ering->tx_pending;
9008
9009         if (netif_running(dev)) {
9010                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9011                 err = tg3_restart_hw(tp, 1);
9012                 if (!err)
9013                         tg3_netif_start(tp);
9014         }
9015
9016         tg3_full_unlock(tp);
9017
9018         if (irq_sync && !err)
9019                 tg3_phy_start(tp);
9020
9021         return err;
9022 }
9023
9024 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9025 {
9026         struct tg3 *tp = netdev_priv(dev);
9027
9028         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9029
9030         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9031                 epause->rx_pause = 1;
9032         else
9033                 epause->rx_pause = 0;
9034
9035         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9036                 epause->tx_pause = 1;
9037         else
9038                 epause->tx_pause = 0;
9039 }
9040
9041 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9042 {
9043         struct tg3 *tp = netdev_priv(dev);
9044         int err = 0;
9045
9046         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9047                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9048                         return -EAGAIN;
9049
9050                 if (epause->autoneg) {
9051                         u32 newadv;
9052                         struct phy_device *phydev;
9053
9054                         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
9055
9056                         if (epause->rx_pause) {
9057                                 if (epause->tx_pause)
9058                                         newadv = ADVERTISED_Pause;
9059                                 else
9060                                         newadv = ADVERTISED_Pause |
9061                                                  ADVERTISED_Asym_Pause;
9062                         } else if (epause->tx_pause) {
9063                                 newadv = ADVERTISED_Asym_Pause;
9064                         } else
9065                                 newadv = 0;
9066
9067                         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9068                                 u32 oldadv = phydev->advertising &
9069                                              (ADVERTISED_Pause |
9070                                               ADVERTISED_Asym_Pause);
9071                                 if (oldadv != newadv) {
9072                                         phydev->advertising &=
9073                                                 ~(ADVERTISED_Pause |
9074                                                   ADVERTISED_Asym_Pause);
9075                                         phydev->advertising |= newadv;
9076                                         err = phy_start_aneg(phydev);
9077                                 }
9078                         } else {
9079                                 tp->link_config.advertising &=
9080                                                 ~(ADVERTISED_Pause |
9081                                                   ADVERTISED_Asym_Pause);
9082                                 tp->link_config.advertising |= newadv;
9083                         }
9084                 } else {
9085                         if (epause->rx_pause)
9086                                 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9087                         else
9088                                 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9089
9090                         if (epause->tx_pause)
9091                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9092                         else
9093                                 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9094
9095                         if (netif_running(dev))
9096                                 tg3_setup_flow_control(tp, 0, 0);
9097                 }
9098         } else {
9099                 int irq_sync = 0;
9100
9101                 if (netif_running(dev)) {
9102                         tg3_netif_stop(tp);
9103                         irq_sync = 1;
9104                 }
9105
9106                 tg3_full_lock(tp, irq_sync);
9107
9108                 if (epause->autoneg)
9109                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9110                 else
9111                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9112                 if (epause->rx_pause)
9113                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9114                 else
9115                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9116                 if (epause->tx_pause)
9117                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9118                 else
9119                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9120
9121                 if (netif_running(dev)) {
9122                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9123                         err = tg3_restart_hw(tp, 1);
9124                         if (!err)
9125                                 tg3_netif_start(tp);
9126                 }
9127
9128                 tg3_full_unlock(tp);
9129         }
9130
9131         return err;
9132 }
9133
9134 static u32 tg3_get_rx_csum(struct net_device *dev)
9135 {
9136         struct tg3 *tp = netdev_priv(dev);
9137         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9138 }
9139
9140 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9141 {
9142         struct tg3 *tp = netdev_priv(dev);
9143
9144         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9145                 if (data != 0)
9146                         return -EINVAL;
9147                 return 0;
9148         }
9149
9150         spin_lock_bh(&tp->lock);
9151         if (data)
9152                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9153         else
9154                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9155         spin_unlock_bh(&tp->lock);
9156
9157         return 0;
9158 }
9159
9160 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9161 {
9162         struct tg3 *tp = netdev_priv(dev);
9163
9164         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9165                 if (data != 0)
9166                         return -EINVAL;
9167                 return 0;
9168         }
9169
9170         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9171                 ethtool_op_set_tx_ipv6_csum(dev, data);
9172         else
9173                 ethtool_op_set_tx_csum(dev, data);
9174
9175         return 0;
9176 }
9177
9178 static int tg3_get_sset_count (struct net_device *dev, int sset)
9179 {
9180         switch (sset) {
9181         case ETH_SS_TEST:
9182                 return TG3_NUM_TEST;
9183         case ETH_SS_STATS:
9184                 return TG3_NUM_STATS;
9185         default:
9186                 return -EOPNOTSUPP;
9187         }
9188 }
9189
9190 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9191 {
9192         switch (stringset) {
9193         case ETH_SS_STATS:
9194                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9195                 break;
9196         case ETH_SS_TEST:
9197                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9198                 break;
9199         default:
9200                 WARN_ON(1);     /* we need a WARN() */
9201                 break;
9202         }
9203 }
9204
9205 static int tg3_phys_id(struct net_device *dev, u32 data)
9206 {
9207         struct tg3 *tp = netdev_priv(dev);
9208         int i;
9209
9210         if (!netif_running(tp->dev))
9211                 return -EAGAIN;
9212
9213         if (data == 0)
9214                 data = UINT_MAX / 2;
9215
9216         for (i = 0; i < (data * 2); i++) {
9217                 if ((i % 2) == 0)
9218                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9219                                            LED_CTRL_1000MBPS_ON |
9220                                            LED_CTRL_100MBPS_ON |
9221                                            LED_CTRL_10MBPS_ON |
9222                                            LED_CTRL_TRAFFIC_OVERRIDE |
9223                                            LED_CTRL_TRAFFIC_BLINK |
9224                                            LED_CTRL_TRAFFIC_LED);
9225
9226                 else
9227                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9228                                            LED_CTRL_TRAFFIC_OVERRIDE);
9229
9230                 if (msleep_interruptible(500))
9231                         break;
9232         }
9233         tw32(MAC_LED_CTRL, tp->led_ctrl);
9234         return 0;
9235 }
9236
9237 static void tg3_get_ethtool_stats (struct net_device *dev,
9238                                    struct ethtool_stats *estats, u64 *tmp_stats)
9239 {
9240         struct tg3 *tp = netdev_priv(dev);
9241         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9242 }
9243
9244 #define NVRAM_TEST_SIZE 0x100
9245 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
9246 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
9247 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
9248 #define NVRAM_SELFBOOT_HW_SIZE 0x20
9249 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9250
9251 static int tg3_test_nvram(struct tg3 *tp)
9252 {
9253         u32 csum, magic;
9254         __be32 *buf;
9255         int i, j, k, err = 0, size;
9256
9257         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9258                 return 0;
9259
9260         if (tg3_nvram_read(tp, 0, &magic) != 0)
9261                 return -EIO;
9262
9263         if (magic == TG3_EEPROM_MAGIC)
9264                 size = NVRAM_TEST_SIZE;
9265         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
9266                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9267                     TG3_EEPROM_SB_FORMAT_1) {
9268                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9269                         case TG3_EEPROM_SB_REVISION_0:
9270                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9271                                 break;
9272                         case TG3_EEPROM_SB_REVISION_2:
9273                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9274                                 break;
9275                         case TG3_EEPROM_SB_REVISION_3:
9276                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9277                                 break;
9278                         default:
9279                                 return 0;
9280                         }
9281                 } else
9282                         return 0;
9283         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9284                 size = NVRAM_SELFBOOT_HW_SIZE;
9285         else
9286                 return -EIO;
9287
9288         buf = kmalloc(size, GFP_KERNEL);
9289         if (buf == NULL)
9290                 return -ENOMEM;
9291
9292         err = -EIO;
9293         for (i = 0, j = 0; i < size; i += 4, j++) {
9294                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9295                 if (err)
9296                         break;
9297         }
9298         if (i < size)
9299                 goto out;
9300
9301         /* Selfboot format */
9302         magic = be32_to_cpu(buf[0]);
9303         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9304             TG3_EEPROM_MAGIC_FW) {
9305                 u8 *buf8 = (u8 *) buf, csum8 = 0;
9306
9307                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
9308                     TG3_EEPROM_SB_REVISION_2) {
9309                         /* For rev 2, the csum doesn't include the MBA. */
9310                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9311                                 csum8 += buf8[i];
9312                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9313                                 csum8 += buf8[i];
9314                 } else {
9315                         for (i = 0; i < size; i++)
9316                                 csum8 += buf8[i];
9317                 }
9318
9319                 if (csum8 == 0) {
9320                         err = 0;
9321                         goto out;
9322                 }
9323
9324                 err = -EIO;
9325                 goto out;
9326         }
9327
9328         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
9329             TG3_EEPROM_MAGIC_HW) {
9330                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9331                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9332                 u8 *buf8 = (u8 *) buf;
9333
9334                 /* Separate the parity bits and the data bytes.  */
9335                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9336                         if ((i == 0) || (i == 8)) {
9337                                 int l;
9338                                 u8 msk;
9339
9340                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9341                                         parity[k++] = buf8[i] & msk;
9342                                 i++;
9343                         }
9344                         else if (i == 16) {
9345                                 int l;
9346                                 u8 msk;
9347
9348                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9349                                         parity[k++] = buf8[i] & msk;
9350                                 i++;
9351
9352                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9353                                         parity[k++] = buf8[i] & msk;
9354                                 i++;
9355                         }
9356                         data[j++] = buf8[i];
9357                 }
9358
9359                 err = -EIO;
9360                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9361                         u8 hw8 = hweight8(data[i]);
9362
9363                         if ((hw8 & 0x1) && parity[i])
9364                                 goto out;
9365                         else if (!(hw8 & 0x1) && !parity[i])
9366                                 goto out;
9367                 }
9368                 err = 0;
9369                 goto out;
9370         }
9371
9372         /* Bootstrap checksum at offset 0x10 */
9373         csum = calc_crc((unsigned char *) buf, 0x10);
9374         if (csum != be32_to_cpu(buf[0x10/4]))
9375                 goto out;
9376
9377         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9378         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
9379         if (csum != be32_to_cpu(buf[0xfc/4]))
9380                 goto out;
9381
9382         err = 0;
9383
9384 out:
9385         kfree(buf);
9386         return err;
9387 }
9388
9389 #define TG3_SERDES_TIMEOUT_SEC  2
9390 #define TG3_COPPER_TIMEOUT_SEC  6
9391
9392 static int tg3_test_link(struct tg3 *tp)
9393 {
9394         int i, max;
9395
9396         if (!netif_running(tp->dev))
9397                 return -ENODEV;
9398
9399         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9400                 max = TG3_SERDES_TIMEOUT_SEC;
9401         else
9402                 max = TG3_COPPER_TIMEOUT_SEC;
9403
9404         for (i = 0; i < max; i++) {
9405                 if (netif_carrier_ok(tp->dev))
9406                         return 0;
9407
9408                 if (msleep_interruptible(1000))
9409                         break;
9410         }
9411
9412         return -EIO;
9413 }
9414
9415 /* Only test the commonly used registers */
9416 static int tg3_test_registers(struct tg3 *tp)
9417 {
9418         int i, is_5705, is_5750;
9419         u32 offset, read_mask, write_mask, val, save_val, read_val;
9420         static struct {
9421                 u16 offset;
9422                 u16 flags;
9423 #define TG3_FL_5705     0x1
9424 #define TG3_FL_NOT_5705 0x2
9425 #define TG3_FL_NOT_5788 0x4
9426 #define TG3_FL_NOT_5750 0x8
9427                 u32 read_mask;
9428                 u32 write_mask;
9429         } reg_tbl[] = {
9430                 /* MAC Control Registers */
9431                 { MAC_MODE, TG3_FL_NOT_5705,
9432                         0x00000000, 0x00ef6f8c },
9433                 { MAC_MODE, TG3_FL_5705,
9434                         0x00000000, 0x01ef6b8c },
9435                 { MAC_STATUS, TG3_FL_NOT_5705,
9436                         0x03800107, 0x00000000 },
9437                 { MAC_STATUS, TG3_FL_5705,
9438                         0x03800100, 0x00000000 },
9439                 { MAC_ADDR_0_HIGH, 0x0000,
9440                         0x00000000, 0x0000ffff },
9441                 { MAC_ADDR_0_LOW, 0x0000,
9442                         0x00000000, 0xffffffff },
9443                 { MAC_RX_MTU_SIZE, 0x0000,
9444                         0x00000000, 0x0000ffff },
9445                 { MAC_TX_MODE, 0x0000,
9446                         0x00000000, 0x00000070 },
9447                 { MAC_TX_LENGTHS, 0x0000,
9448                         0x00000000, 0x00003fff },
9449                 { MAC_RX_MODE, TG3_FL_NOT_5705,
9450                         0x00000000, 0x000007fc },
9451                 { MAC_RX_MODE, TG3_FL_5705,
9452                         0x00000000, 0x000007dc },
9453                 { MAC_HASH_REG_0, 0x0000,
9454                         0x00000000, 0xffffffff },
9455                 { MAC_HASH_REG_1, 0x0000,
9456                         0x00000000, 0xffffffff },
9457                 { MAC_HASH_REG_2, 0x0000,
9458                         0x00000000, 0xffffffff },
9459                 { MAC_HASH_REG_3, 0x0000,
9460                         0x00000000, 0xffffffff },
9461
9462                 /* Receive Data and Receive BD Initiator Control Registers. */
9463                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9464                         0x00000000, 0xffffffff },
9465                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9466                         0x00000000, 0xffffffff },
9467                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9468                         0x00000000, 0x00000003 },
9469                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9470                         0x00000000, 0xffffffff },
9471                 { RCVDBDI_STD_BD+0, 0x0000,
9472                         0x00000000, 0xffffffff },
9473                 { RCVDBDI_STD_BD+4, 0x0000,
9474                         0x00000000, 0xffffffff },
9475                 { RCVDBDI_STD_BD+8, 0x0000,
9476                         0x00000000, 0xffff0002 },
9477                 { RCVDBDI_STD_BD+0xc, 0x0000,
9478                         0x00000000, 0xffffffff },
9479
9480                 /* Receive BD Initiator Control Registers. */
9481                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9482                         0x00000000, 0xffffffff },
9483                 { RCVBDI_STD_THRESH, TG3_FL_5705,
9484                         0x00000000, 0x000003ff },
9485                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9486                         0x00000000, 0xffffffff },
9487
9488                 /* Host Coalescing Control Registers. */
9489                 { HOSTCC_MODE, TG3_FL_NOT_5705,
9490                         0x00000000, 0x00000004 },
9491                 { HOSTCC_MODE, TG3_FL_5705,
9492                         0x00000000, 0x000000f6 },
9493                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9494                         0x00000000, 0xffffffff },
9495                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9496                         0x00000000, 0x000003ff },
9497                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9498                         0x00000000, 0xffffffff },
9499                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9500                         0x00000000, 0x000003ff },
9501                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9502                         0x00000000, 0xffffffff },
9503                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9504                         0x00000000, 0x000000ff },
9505                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9506                         0x00000000, 0xffffffff },
9507                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9508                         0x00000000, 0x000000ff },
9509                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9510                         0x00000000, 0xffffffff },
9511                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9512                         0x00000000, 0xffffffff },
9513                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9514                         0x00000000, 0xffffffff },
9515                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9516                         0x00000000, 0x000000ff },
9517                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9518                         0x00000000, 0xffffffff },
9519                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9520                         0x00000000, 0x000000ff },
9521                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9522                         0x00000000, 0xffffffff },
9523                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9524                         0x00000000, 0xffffffff },
9525                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9526                         0x00000000, 0xffffffff },
9527                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9528                         0x00000000, 0xffffffff },
9529                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9530                         0x00000000, 0xffffffff },
9531                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9532                         0xffffffff, 0x00000000 },
9533                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9534                         0xffffffff, 0x00000000 },
9535
9536                 /* Buffer Manager Control Registers. */
9537                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
9538                         0x00000000, 0x007fff80 },
9539                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
9540                         0x00000000, 0x007fffff },
9541                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9542                         0x00000000, 0x0000003f },
9543                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9544                         0x00000000, 0x000001ff },
9545                 { BUFMGR_MB_HIGH_WATER, 0x0000,
9546                         0x00000000, 0x000001ff },
9547                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9548                         0xffffffff, 0x00000000 },
9549                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9550                         0xffffffff, 0x00000000 },
9551
9552                 /* Mailbox Registers */
9553                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9554                         0x00000000, 0x000001ff },
9555                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9556                         0x00000000, 0x000001ff },
9557                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9558                         0x00000000, 0x000007ff },
9559                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9560                         0x00000000, 0x000001ff },
9561
9562                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9563         };
9564
9565         is_5705 = is_5750 = 0;
9566         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9567                 is_5705 = 1;
9568                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9569                         is_5750 = 1;
9570         }
9571
9572         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9573                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9574                         continue;
9575
9576                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9577                         continue;
9578
9579                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9580                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
9581                         continue;
9582
9583                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9584                         continue;
9585
9586                 offset = (u32) reg_tbl[i].offset;
9587                 read_mask = reg_tbl[i].read_mask;
9588                 write_mask = reg_tbl[i].write_mask;
9589
9590                 /* Save the original register content */
9591                 save_val = tr32(offset);
9592
9593                 /* Determine the read-only value. */
9594                 read_val = save_val & read_mask;
9595
9596                 /* Write zero to the register, then make sure the read-only bits
9597                  * are not changed and the read/write bits are all zeros.
9598                  */
9599                 tw32(offset, 0);
9600
9601                 val = tr32(offset);
9602
9603                 /* Test the read-only and read/write bits. */
9604                 if (((val & read_mask) != read_val) || (val & write_mask))
9605                         goto out;
9606
9607                 /* Write ones to all the bits defined by RdMask and WrMask, then
9608                  * make sure the read-only bits are not changed and the
9609                  * read/write bits are all ones.
9610                  */
9611                 tw32(offset, read_mask | write_mask);
9612
9613                 val = tr32(offset);
9614
9615                 /* Test the read-only bits. */
9616                 if ((val & read_mask) != read_val)
9617                         goto out;
9618
9619                 /* Test the read/write bits. */
9620                 if ((val & write_mask) != write_mask)
9621                         goto out;
9622
9623                 tw32(offset, save_val);
9624         }
9625
9626         return 0;
9627
9628 out:
9629         if (netif_msg_hw(tp))
9630                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9631                        offset);
9632         tw32(offset, save_val);
9633         return -EIO;
9634 }
9635
9636 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9637 {
9638         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
9639         int i;
9640         u32 j;
9641
9642         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
9643                 for (j = 0; j < len; j += 4) {
9644                         u32 val;
9645
9646                         tg3_write_mem(tp, offset + j, test_pattern[i]);
9647                         tg3_read_mem(tp, offset + j, &val);
9648                         if (val != test_pattern[i])
9649                                 return -EIO;
9650                 }
9651         }
9652         return 0;
9653 }
9654
9655 static int tg3_test_memory(struct tg3 *tp)
9656 {
9657         static struct mem_entry {
9658                 u32 offset;
9659                 u32 len;
9660         } mem_tbl_570x[] = {
9661                 { 0x00000000, 0x00b50},
9662                 { 0x00002000, 0x1c000},
9663                 { 0xffffffff, 0x00000}
9664         }, mem_tbl_5705[] = {
9665                 { 0x00000100, 0x0000c},
9666                 { 0x00000200, 0x00008},
9667                 { 0x00004000, 0x00800},
9668                 { 0x00006000, 0x01000},
9669                 { 0x00008000, 0x02000},
9670                 { 0x00010000, 0x0e000},
9671                 { 0xffffffff, 0x00000}
9672         }, mem_tbl_5755[] = {
9673                 { 0x00000200, 0x00008},
9674                 { 0x00004000, 0x00800},
9675                 { 0x00006000, 0x00800},
9676                 { 0x00008000, 0x02000},
9677                 { 0x00010000, 0x0c000},
9678                 { 0xffffffff, 0x00000}
9679         }, mem_tbl_5906[] = {
9680                 { 0x00000200, 0x00008},
9681                 { 0x00004000, 0x00400},
9682                 { 0x00006000, 0x00400},
9683                 { 0x00008000, 0x01000},
9684                 { 0x00010000, 0x01000},
9685                 { 0xffffffff, 0x00000}
9686         };
9687         struct mem_entry *mem_tbl;
9688         int err = 0;
9689         int i;
9690
9691         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9692                 mem_tbl = mem_tbl_5755;
9693         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9694                 mem_tbl = mem_tbl_5906;
9695         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
9696                 mem_tbl = mem_tbl_5705;
9697         else
9698                 mem_tbl = mem_tbl_570x;
9699
9700         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9701                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9702                     mem_tbl[i].len)) != 0)
9703                         break;
9704         }
9705
9706         return err;
9707 }
9708
9709 #define TG3_MAC_LOOPBACK        0
9710 #define TG3_PHY_LOOPBACK        1
9711
9712 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
9713 {
9714         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
9715         u32 desc_idx;
9716         struct sk_buff *skb, *rx_skb;
9717         u8 *tx_data;
9718         dma_addr_t map;
9719         int num_pkts, tx_len, rx_len, i, err;
9720         struct tg3_rx_buffer_desc *desc;
9721
9722         if (loopback_mode == TG3_MAC_LOOPBACK) {
9723                 /* HW errata - mac loopback fails in some cases on 5780.
9724                  * Normal traffic and PHY loopback are not affected by
9725                  * errata.
9726                  */
9727                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9728                         return 0;
9729
9730                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
9731                            MAC_MODE_PORT_INT_LPBACK;
9732                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9733                         mac_mode |= MAC_MODE_LINK_POLARITY;
9734                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9735                         mac_mode |= MAC_MODE_PORT_MODE_MII;
9736                 else
9737                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
9738                 tw32(MAC_MODE, mac_mode);
9739         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
9740                 u32 val;
9741
9742                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9743                         u32 phytest;
9744
9745                         if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
9746                                 u32 phy;
9747
9748                                 tg3_writephy(tp, MII_TG3_EPHY_TEST,
9749                                              phytest | MII_TG3_EPHY_SHADOW_EN);
9750                                 if (!tg3_readphy(tp, 0x1b, &phy))
9751                                         tg3_writephy(tp, 0x1b, phy & ~0x20);
9752                                 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
9753                         }
9754                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9755                 } else
9756                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
9757
9758                 tg3_phy_toggle_automdix(tp, 0);
9759
9760                 tg3_writephy(tp, MII_BMCR, val);
9761                 udelay(40);
9762
9763                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
9764                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9765                         tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
9766                         mac_mode |= MAC_MODE_PORT_MODE_MII;
9767                 } else
9768                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
9769
9770                 /* reset to prevent losing 1st rx packet intermittently */
9771                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
9772                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9773                         udelay(10);
9774                         tw32_f(MAC_RX_MODE, tp->rx_mode);
9775                 }
9776                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
9777                         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
9778                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
9779                         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
9780                                 mac_mode |= MAC_MODE_LINK_POLARITY;
9781                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
9782                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
9783                 }
9784                 tw32(MAC_MODE, mac_mode);
9785         }
9786         else
9787                 return -EINVAL;
9788
9789         err = -EIO;
9790
9791         tx_len = 1514;
9792         skb = netdev_alloc_skb(tp->dev, tx_len);
9793         if (!skb)
9794                 return -ENOMEM;
9795
9796         tx_data = skb_put(skb, tx_len);
9797         memcpy(tx_data, tp->dev->dev_addr, 6);
9798         memset(tx_data + 6, 0x0, 8);
9799
9800         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
9801
9802         for (i = 14; i < tx_len; i++)
9803                 tx_data[i] = (u8) (i & 0xff);
9804
9805         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
9806
9807         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9808              HOSTCC_MODE_NOW);
9809
9810         udelay(10);
9811
9812         rx_start_idx = tp->hw_status->idx[0].rx_producer;
9813
9814         num_pkts = 0;
9815
9816         tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
9817
9818         tp->tx_prod++;
9819         num_pkts++;
9820
9821         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
9822                      tp->tx_prod);
9823         tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
9824
9825         udelay(10);
9826
9827         /* 250 usec to allow enough time on some 10/100 Mbps devices.  */
9828         for (i = 0; i < 25; i++) {
9829                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9830                        HOSTCC_MODE_NOW);
9831
9832                 udelay(10);
9833
9834                 tx_idx = tp->hw_status->idx[0].tx_consumer;
9835                 rx_idx = tp->hw_status->idx[0].rx_producer;
9836                 if ((tx_idx == tp->tx_prod) &&
9837                     (rx_idx == (rx_start_idx + num_pkts)))
9838                         break;
9839         }
9840
9841         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
9842         dev_kfree_skb(skb);
9843
9844         if (tx_idx != tp->tx_prod)
9845                 goto out;
9846
9847         if (rx_idx != rx_start_idx + num_pkts)
9848                 goto out;
9849
9850         desc = &tp->rx_rcb[rx_start_idx];
9851         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
9852         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
9853         if (opaque_key != RXD_OPAQUE_RING_STD)
9854                 goto out;
9855
9856         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
9857             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
9858                 goto out;
9859
9860         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
9861         if (rx_len != tx_len)
9862                 goto out;
9863
9864         rx_skb = tp->rx_std_buffers[desc_idx].skb;
9865
9866         map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
9867         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
9868
9869         for (i = 14; i < tx_len; i++) {
9870                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
9871                         goto out;
9872         }
9873         err = 0;
9874
9875         /* tg3_free_rings will unmap and free the rx_skb */
9876 out:
9877         return err;
9878 }
9879
9880 #define TG3_MAC_LOOPBACK_FAILED         1
9881 #define TG3_PHY_LOOPBACK_FAILED         2
9882 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
9883                                          TG3_PHY_LOOPBACK_FAILED)
9884
9885 static int tg3_test_loopback(struct tg3 *tp)
9886 {
9887         int err = 0;
9888         u32 cpmuctrl = 0;
9889
9890         if (!netif_running(tp->dev))
9891                 return TG3_LOOPBACK_FAILED;
9892
9893         err = tg3_reset_hw(tp, 1);
9894         if (err)
9895                 return TG3_LOOPBACK_FAILED;
9896
9897         /* Turn off gphy autopowerdown. */
9898         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
9899                 tg3_phy_toggle_apd(tp, false);
9900
9901         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9902                 int i;
9903                 u32 status;
9904
9905                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
9906
9907                 /* Wait for up to 40 microseconds to acquire lock. */
9908                 for (i = 0; i < 4; i++) {
9909                         status = tr32(TG3_CPMU_MUTEX_GNT);
9910                         if (status == CPMU_MUTEX_GNT_DRIVER)
9911                                 break;
9912                         udelay(10);
9913                 }
9914
9915                 if (status != CPMU_MUTEX_GNT_DRIVER)
9916                         return TG3_LOOPBACK_FAILED;
9917
9918                 /* Turn off link-based power management. */
9919                 cpmuctrl = tr32(TG3_CPMU_CTRL);
9920                 tw32(TG3_CPMU_CTRL,
9921                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
9922                                   CPMU_CTRL_LINK_AWARE_MODE));
9923         }
9924
9925         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
9926                 err |= TG3_MAC_LOOPBACK_FAILED;
9927
9928         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9929                 tw32(TG3_CPMU_CTRL, cpmuctrl);
9930
9931                 /* Release the mutex */
9932                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
9933         }
9934
9935         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9936             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9937                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
9938                         err |= TG3_PHY_LOOPBACK_FAILED;
9939         }
9940
9941         /* Re-enable gphy autopowerdown. */
9942         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
9943                 tg3_phy_toggle_apd(tp, true);
9944
9945         return err;
9946 }
9947
9948 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
9949                           u64 *data)
9950 {
9951         struct tg3 *tp = netdev_priv(dev);
9952
9953         if (tp->link_config.phy_is_low_power)
9954                 tg3_set_power_state(tp, PCI_D0);
9955
9956         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
9957
9958         if (tg3_test_nvram(tp) != 0) {
9959                 etest->flags |= ETH_TEST_FL_FAILED;
9960                 data[0] = 1;
9961         }
9962         if (tg3_test_link(tp) != 0) {
9963                 etest->flags |= ETH_TEST_FL_FAILED;
9964                 data[1] = 1;
9965         }
9966         if (etest->flags & ETH_TEST_FL_OFFLINE) {
9967                 int err, err2 = 0, irq_sync = 0;
9968
9969                 if (netif_running(dev)) {
9970                         tg3_phy_stop(tp);
9971                         tg3_netif_stop(tp);
9972                         irq_sync = 1;
9973                 }
9974
9975                 tg3_full_lock(tp, irq_sync);
9976
9977                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
9978                 err = tg3_nvram_lock(tp);
9979                 tg3_halt_cpu(tp, RX_CPU_BASE);
9980                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9981                         tg3_halt_cpu(tp, TX_CPU_BASE);
9982                 if (!err)
9983                         tg3_nvram_unlock(tp);
9984
9985                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
9986                         tg3_phy_reset(tp);
9987
9988                 if (tg3_test_registers(tp) != 0) {
9989                         etest->flags |= ETH_TEST_FL_FAILED;
9990                         data[2] = 1;
9991                 }
9992                 if (tg3_test_memory(tp) != 0) {
9993                         etest->flags |= ETH_TEST_FL_FAILED;
9994                         data[3] = 1;
9995                 }
9996                 if ((data[4] = tg3_test_loopback(tp)) != 0)
9997                         etest->flags |= ETH_TEST_FL_FAILED;
9998
9999                 tg3_full_unlock(tp);
10000
10001                 if (tg3_test_interrupt(tp) != 0) {
10002                         etest->flags |= ETH_TEST_FL_FAILED;
10003                         data[5] = 1;
10004                 }
10005
10006                 tg3_full_lock(tp, 0);
10007
10008                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10009                 if (netif_running(dev)) {
10010                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10011                         err2 = tg3_restart_hw(tp, 1);
10012                         if (!err2)
10013                                 tg3_netif_start(tp);
10014                 }
10015
10016                 tg3_full_unlock(tp);
10017
10018                 if (irq_sync && !err2)
10019                         tg3_phy_start(tp);
10020         }
10021         if (tp->link_config.phy_is_low_power)
10022                 tg3_set_power_state(tp, PCI_D3hot);
10023
10024 }
10025
10026 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10027 {
10028         struct mii_ioctl_data *data = if_mii(ifr);
10029         struct tg3 *tp = netdev_priv(dev);
10030         int err;
10031
10032         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10033                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10034                         return -EAGAIN;
10035                 return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd);
10036         }
10037
10038         switch(cmd) {
10039         case SIOCGMIIPHY:
10040                 data->phy_id = PHY_ADDR;
10041
10042                 /* fallthru */
10043         case SIOCGMIIREG: {
10044                 u32 mii_regval;
10045
10046                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10047                         break;                  /* We have no PHY */
10048
10049                 if (tp->link_config.phy_is_low_power)
10050                         return -EAGAIN;
10051
10052                 spin_lock_bh(&tp->lock);
10053                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10054                 spin_unlock_bh(&tp->lock);
10055
10056                 data->val_out = mii_regval;
10057
10058                 return err;
10059         }
10060
10061         case SIOCSMIIREG:
10062                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10063                         break;                  /* We have no PHY */
10064
10065                 if (!capable(CAP_NET_ADMIN))
10066                         return -EPERM;
10067
10068                 if (tp->link_config.phy_is_low_power)
10069                         return -EAGAIN;
10070
10071                 spin_lock_bh(&tp->lock);
10072                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10073                 spin_unlock_bh(&tp->lock);
10074
10075                 return err;
10076
10077         default:
10078                 /* do nothing */
10079                 break;
10080         }
10081         return -EOPNOTSUPP;
10082 }
10083
10084 #if TG3_VLAN_TAG_USED
10085 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10086 {
10087         struct tg3 *tp = netdev_priv(dev);
10088
10089         if (!netif_running(dev)) {
10090                 tp->vlgrp = grp;
10091                 return;
10092         }
10093
10094         tg3_netif_stop(tp);
10095
10096         tg3_full_lock(tp, 0);
10097
10098         tp->vlgrp = grp;
10099
10100         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10101         __tg3_set_rx_mode(dev);
10102
10103         tg3_netif_start(tp);
10104
10105         tg3_full_unlock(tp);
10106 }
10107 #endif
10108
10109 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10110 {
10111         struct tg3 *tp = netdev_priv(dev);
10112
10113         memcpy(ec, &tp->coal, sizeof(*ec));
10114         return 0;
10115 }
10116
10117 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10118 {
10119         struct tg3 *tp = netdev_priv(dev);
10120         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10121         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10122
10123         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10124                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10125                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10126                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10127                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10128         }
10129
10130         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10131             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10132             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10133             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10134             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10135             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10136             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10137             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10138             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10139             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10140                 return -EINVAL;
10141
10142         /* No rx interrupts will be generated if both are zero */
10143         if ((ec->rx_coalesce_usecs == 0) &&
10144             (ec->rx_max_coalesced_frames == 0))
10145                 return -EINVAL;
10146
10147         /* No tx interrupts will be generated if both are zero */
10148         if ((ec->tx_coalesce_usecs == 0) &&
10149             (ec->tx_max_coalesced_frames == 0))
10150                 return -EINVAL;
10151
10152         /* Only copy relevant parameters, ignore all others. */
10153         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10154         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10155         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10156         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10157         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10158         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10159         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10160         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10161         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10162
10163         if (netif_running(dev)) {
10164                 tg3_full_lock(tp, 0);
10165                 __tg3_set_coalesce(tp, &tp->coal);
10166                 tg3_full_unlock(tp);
10167         }
10168         return 0;
10169 }
10170
10171 static const struct ethtool_ops tg3_ethtool_ops = {
10172         .get_settings           = tg3_get_settings,
10173         .set_settings           = tg3_set_settings,
10174         .get_drvinfo            = tg3_get_drvinfo,
10175         .get_regs_len           = tg3_get_regs_len,
10176         .get_regs               = tg3_get_regs,
10177         .get_wol                = tg3_get_wol,
10178         .set_wol                = tg3_set_wol,
10179         .get_msglevel           = tg3_get_msglevel,
10180         .set_msglevel           = tg3_set_msglevel,
10181         .nway_reset             = tg3_nway_reset,
10182         .get_link               = ethtool_op_get_link,
10183         .get_eeprom_len         = tg3_get_eeprom_len,
10184         .get_eeprom             = tg3_get_eeprom,
10185         .set_eeprom             = tg3_set_eeprom,
10186         .get_ringparam          = tg3_get_ringparam,
10187         .set_ringparam          = tg3_set_ringparam,
10188         .get_pauseparam         = tg3_get_pauseparam,
10189         .set_pauseparam         = tg3_set_pauseparam,
10190         .get_rx_csum            = tg3_get_rx_csum,
10191         .set_rx_csum            = tg3_set_rx_csum,
10192         .set_tx_csum            = tg3_set_tx_csum,
10193         .set_sg                 = ethtool_op_set_sg,
10194         .set_tso                = tg3_set_tso,
10195         .self_test              = tg3_self_test,
10196         .get_strings            = tg3_get_strings,
10197         .phys_id                = tg3_phys_id,
10198         .get_ethtool_stats      = tg3_get_ethtool_stats,
10199         .get_coalesce           = tg3_get_coalesce,
10200         .set_coalesce           = tg3_set_coalesce,
10201         .get_sset_count         = tg3_get_sset_count,
10202 };
10203
10204 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10205 {
10206         u32 cursize, val, magic;
10207
10208         tp->nvram_size = EEPROM_CHIP_SIZE;
10209
10210         if (tg3_nvram_read(tp, 0, &magic) != 0)
10211                 return;
10212
10213         if ((magic != TG3_EEPROM_MAGIC) &&
10214             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10215             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
10216                 return;
10217
10218         /*
10219          * Size the chip by reading offsets at increasing powers of two.
10220          * When we encounter our validation signature, we know the addressing
10221          * has wrapped around, and thus have our chip size.
10222          */
10223         cursize = 0x10;
10224
10225         while (cursize < tp->nvram_size) {
10226                 if (tg3_nvram_read(tp, cursize, &val) != 0)
10227                         return;
10228
10229                 if (val == magic)
10230                         break;
10231
10232                 cursize <<= 1;
10233         }
10234
10235         tp->nvram_size = cursize;
10236 }
10237
10238 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10239 {
10240         u32 val;
10241
10242         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10243             tg3_nvram_read(tp, 0, &val) != 0)
10244                 return;
10245
10246         /* Selfboot format */
10247         if (val != TG3_EEPROM_MAGIC) {
10248                 tg3_get_eeprom_size(tp);
10249                 return;
10250         }
10251
10252         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
10253                 if (val != 0) {
10254                         /* This is confusing.  We want to operate on the
10255                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
10256                          * call will read from NVRAM and byteswap the data
10257                          * according to the byteswapping settings for all
10258                          * other register accesses.  This ensures the data we
10259                          * want will always reside in the lower 16-bits.
10260                          * However, the data in NVRAM is in LE format, which
10261                          * means the data from the NVRAM read will always be
10262                          * opposite the endianness of the CPU.  The 16-bit
10263                          * byteswap then brings the data to CPU endianness.
10264                          */
10265                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
10266                         return;
10267                 }
10268         }
10269         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10270 }
10271
10272 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10273 {
10274         u32 nvcfg1;
10275
10276         nvcfg1 = tr32(NVRAM_CFG1);
10277         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10278                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10279         }
10280         else {
10281                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10282                 tw32(NVRAM_CFG1, nvcfg1);
10283         }
10284
10285         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
10286             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10287                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10288                         case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10289                                 tp->nvram_jedecnum = JEDEC_ATMEL;
10290                                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10291                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10292                                 break;
10293                         case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10294                                 tp->nvram_jedecnum = JEDEC_ATMEL;
10295                                 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10296                                 break;
10297                         case FLASH_VENDOR_ATMEL_EEPROM:
10298                                 tp->nvram_jedecnum = JEDEC_ATMEL;
10299                                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10300                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10301                                 break;
10302                         case FLASH_VENDOR_ST:
10303                                 tp->nvram_jedecnum = JEDEC_ST;
10304                                 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10305                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10306                                 break;
10307                         case FLASH_VENDOR_SAIFUN:
10308                                 tp->nvram_jedecnum = JEDEC_SAIFUN;
10309                                 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10310                                 break;
10311                         case FLASH_VENDOR_SST_SMALL:
10312                         case FLASH_VENDOR_SST_LARGE:
10313                                 tp->nvram_jedecnum = JEDEC_SST;
10314                                 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10315                                 break;
10316                 }
10317         }
10318         else {
10319                 tp->nvram_jedecnum = JEDEC_ATMEL;
10320                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10321                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10322         }
10323 }
10324
10325 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10326 {
10327         u32 nvcfg1;
10328
10329         nvcfg1 = tr32(NVRAM_CFG1);
10330
10331         /* NVRAM protection for TPM */
10332         if (nvcfg1 & (1 << 27))
10333                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10334
10335         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10336                 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10337                 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10338                         tp->nvram_jedecnum = JEDEC_ATMEL;
10339                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10340                         break;
10341                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10342                         tp->nvram_jedecnum = JEDEC_ATMEL;
10343                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10344                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10345                         break;
10346                 case FLASH_5752VENDOR_ST_M45PE10:
10347                 case FLASH_5752VENDOR_ST_M45PE20:
10348                 case FLASH_5752VENDOR_ST_M45PE40:
10349                         tp->nvram_jedecnum = JEDEC_ST;
10350                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10351                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10352                         break;
10353         }
10354
10355         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10356                 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10357                         case FLASH_5752PAGE_SIZE_256:
10358                                 tp->nvram_pagesize = 256;
10359                                 break;
10360                         case FLASH_5752PAGE_SIZE_512:
10361                                 tp->nvram_pagesize = 512;
10362                                 break;
10363                         case FLASH_5752PAGE_SIZE_1K:
10364                                 tp->nvram_pagesize = 1024;
10365                                 break;
10366                         case FLASH_5752PAGE_SIZE_2K:
10367                                 tp->nvram_pagesize = 2048;
10368                                 break;
10369                         case FLASH_5752PAGE_SIZE_4K:
10370                                 tp->nvram_pagesize = 4096;
10371                                 break;
10372                         case FLASH_5752PAGE_SIZE_264:
10373                                 tp->nvram_pagesize = 264;
10374                                 break;
10375                 }
10376         }
10377         else {
10378                 /* For eeprom, set pagesize to maximum eeprom size */
10379                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10380
10381                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10382                 tw32(NVRAM_CFG1, nvcfg1);
10383         }
10384 }
10385
10386 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10387 {
10388         u32 nvcfg1, protect = 0;
10389
10390         nvcfg1 = tr32(NVRAM_CFG1);
10391
10392         /* NVRAM protection for TPM */
10393         if (nvcfg1 & (1 << 27)) {
10394                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10395                 protect = 1;
10396         }
10397
10398         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10399         switch (nvcfg1) {
10400                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10401                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10402                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10403                 case FLASH_5755VENDOR_ATMEL_FLASH_5:
10404                         tp->nvram_jedecnum = JEDEC_ATMEL;
10405                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10406                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10407                         tp->nvram_pagesize = 264;
10408                         if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10409                             nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10410                                 tp->nvram_size = (protect ? 0x3e200 :
10411                                                   TG3_NVRAM_SIZE_512KB);
10412                         else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10413                                 tp->nvram_size = (protect ? 0x1f200 :
10414                                                   TG3_NVRAM_SIZE_256KB);
10415                         else
10416                                 tp->nvram_size = (protect ? 0x1f200 :
10417                                                   TG3_NVRAM_SIZE_128KB);
10418                         break;
10419                 case FLASH_5752VENDOR_ST_M45PE10:
10420                 case FLASH_5752VENDOR_ST_M45PE20:
10421                 case FLASH_5752VENDOR_ST_M45PE40:
10422                         tp->nvram_jedecnum = JEDEC_ST;
10423                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10424                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10425                         tp->nvram_pagesize = 256;
10426                         if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10427                                 tp->nvram_size = (protect ?
10428                                                   TG3_NVRAM_SIZE_64KB :
10429                                                   TG3_NVRAM_SIZE_128KB);
10430                         else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10431                                 tp->nvram_size = (protect ?
10432                                                   TG3_NVRAM_SIZE_64KB :
10433                                                   TG3_NVRAM_SIZE_256KB);
10434                         else
10435                                 tp->nvram_size = (protect ?
10436                                                   TG3_NVRAM_SIZE_128KB :
10437                                                   TG3_NVRAM_SIZE_512KB);
10438                         break;
10439         }
10440 }
10441
10442 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10443 {
10444         u32 nvcfg1;
10445
10446         nvcfg1 = tr32(NVRAM_CFG1);
10447
10448         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10449                 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10450                 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10451                 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10452                 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10453                         tp->nvram_jedecnum = JEDEC_ATMEL;
10454                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10455                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10456
10457                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10458                         tw32(NVRAM_CFG1, nvcfg1);
10459                         break;
10460                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10461                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10462                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10463                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10464                         tp->nvram_jedecnum = JEDEC_ATMEL;
10465                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10466                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10467                         tp->nvram_pagesize = 264;
10468                         break;
10469                 case FLASH_5752VENDOR_ST_M45PE10:
10470                 case FLASH_5752VENDOR_ST_M45PE20:
10471                 case FLASH_5752VENDOR_ST_M45PE40:
10472                         tp->nvram_jedecnum = JEDEC_ST;
10473                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10474                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10475                         tp->nvram_pagesize = 256;
10476                         break;
10477         }
10478 }
10479
10480 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10481 {
10482         u32 nvcfg1, protect = 0;
10483
10484         nvcfg1 = tr32(NVRAM_CFG1);
10485
10486         /* NVRAM protection for TPM */
10487         if (nvcfg1 & (1 << 27)) {
10488                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10489                 protect = 1;
10490         }
10491
10492         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10493         switch (nvcfg1) {
10494                 case FLASH_5761VENDOR_ATMEL_ADB021D:
10495                 case FLASH_5761VENDOR_ATMEL_ADB041D:
10496                 case FLASH_5761VENDOR_ATMEL_ADB081D:
10497                 case FLASH_5761VENDOR_ATMEL_ADB161D:
10498                 case FLASH_5761VENDOR_ATMEL_MDB021D:
10499                 case FLASH_5761VENDOR_ATMEL_MDB041D:
10500                 case FLASH_5761VENDOR_ATMEL_MDB081D:
10501                 case FLASH_5761VENDOR_ATMEL_MDB161D:
10502                         tp->nvram_jedecnum = JEDEC_ATMEL;
10503                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10504                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10505                         tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10506                         tp->nvram_pagesize = 256;
10507                         break;
10508                 case FLASH_5761VENDOR_ST_A_M45PE20:
10509                 case FLASH_5761VENDOR_ST_A_M45PE40:
10510                 case FLASH_5761VENDOR_ST_A_M45PE80:
10511                 case FLASH_5761VENDOR_ST_A_M45PE16:
10512                 case FLASH_5761VENDOR_ST_M_M45PE20:
10513                 case FLASH_5761VENDOR_ST_M_M45PE40:
10514                 case FLASH_5761VENDOR_ST_M_M45PE80:
10515                 case FLASH_5761VENDOR_ST_M_M45PE16:
10516                         tp->nvram_jedecnum = JEDEC_ST;
10517                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10518                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10519                         tp->nvram_pagesize = 256;
10520                         break;
10521         }
10522
10523         if (protect) {
10524                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10525         } else {
10526                 switch (nvcfg1) {
10527                         case FLASH_5761VENDOR_ATMEL_ADB161D:
10528                         case FLASH_5761VENDOR_ATMEL_MDB161D:
10529                         case FLASH_5761VENDOR_ST_A_M45PE16:
10530                         case FLASH_5761VENDOR_ST_M_M45PE16:
10531                                 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
10532                                 break;
10533                         case FLASH_5761VENDOR_ATMEL_ADB081D:
10534                         case FLASH_5761VENDOR_ATMEL_MDB081D:
10535                         case FLASH_5761VENDOR_ST_A_M45PE80:
10536                         case FLASH_5761VENDOR_ST_M_M45PE80:
10537                                 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
10538                                 break;
10539                         case FLASH_5761VENDOR_ATMEL_ADB041D:
10540                         case FLASH_5761VENDOR_ATMEL_MDB041D:
10541                         case FLASH_5761VENDOR_ST_A_M45PE40:
10542                         case FLASH_5761VENDOR_ST_M_M45PE40:
10543                                 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10544                                 break;
10545                         case FLASH_5761VENDOR_ATMEL_ADB021D:
10546                         case FLASH_5761VENDOR_ATMEL_MDB021D:
10547                         case FLASH_5761VENDOR_ST_A_M45PE20:
10548                         case FLASH_5761VENDOR_ST_M_M45PE20:
10549                                 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10550                                 break;
10551                 }
10552         }
10553 }
10554
10555 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10556 {
10557         tp->nvram_jedecnum = JEDEC_ATMEL;
10558         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10559         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10560 }
10561
10562 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
10563 {
10564         u32 nvcfg1;
10565
10566         nvcfg1 = tr32(NVRAM_CFG1);
10567
10568         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10569         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10570         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10571                 tp->nvram_jedecnum = JEDEC_ATMEL;
10572                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10573                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10574
10575                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10576                 tw32(NVRAM_CFG1, nvcfg1);
10577                 return;
10578         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10579         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10580         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10581         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10582         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10583         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10584         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10585                 tp->nvram_jedecnum = JEDEC_ATMEL;
10586                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10587                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10588
10589                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10590                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10591                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10592                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10593                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10594                         break;
10595                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10596                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10597                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10598                         break;
10599                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10600                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10601                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10602                         break;
10603                 }
10604                 break;
10605         case FLASH_5752VENDOR_ST_M45PE10:
10606         case FLASH_5752VENDOR_ST_M45PE20:
10607         case FLASH_5752VENDOR_ST_M45PE40:
10608                 tp->nvram_jedecnum = JEDEC_ST;
10609                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10610                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10611
10612                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10613                 case FLASH_5752VENDOR_ST_M45PE10:
10614                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10615                         break;
10616                 case FLASH_5752VENDOR_ST_M45PE20:
10617                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10618                         break;
10619                 case FLASH_5752VENDOR_ST_M45PE40:
10620                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10621                         break;
10622                 }
10623                 break;
10624         default:
10625                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
10626                 return;
10627         }
10628
10629         switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10630         case FLASH_5752PAGE_SIZE_256:
10631                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10632                 tp->nvram_pagesize = 256;
10633                 break;
10634         case FLASH_5752PAGE_SIZE_512:
10635                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10636                 tp->nvram_pagesize = 512;
10637                 break;
10638         case FLASH_5752PAGE_SIZE_1K:
10639                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10640                 tp->nvram_pagesize = 1024;
10641                 break;
10642         case FLASH_5752PAGE_SIZE_2K:
10643                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10644                 tp->nvram_pagesize = 2048;
10645                 break;
10646         case FLASH_5752PAGE_SIZE_4K:
10647                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10648                 tp->nvram_pagesize = 4096;
10649                 break;
10650         case FLASH_5752PAGE_SIZE_264:
10651                 tp->nvram_pagesize = 264;
10652                 break;
10653         case FLASH_5752PAGE_SIZE_528:
10654                 tp->nvram_pagesize = 528;
10655                 break;
10656         }
10657 }
10658
10659 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
10660 static void __devinit tg3_nvram_init(struct tg3 *tp)
10661 {
10662         tw32_f(GRC_EEPROM_ADDR,
10663              (EEPROM_ADDR_FSM_RESET |
10664               (EEPROM_DEFAULT_CLOCK_PERIOD <<
10665                EEPROM_ADDR_CLKPERD_SHIFT)));
10666
10667         msleep(1);
10668
10669         /* Enable seeprom accesses. */
10670         tw32_f(GRC_LOCAL_CTRL,
10671              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
10672         udelay(100);
10673
10674         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10675             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
10676                 tp->tg3_flags |= TG3_FLAG_NVRAM;
10677
10678                 if (tg3_nvram_lock(tp)) {
10679                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
10680                                "tg3_nvram_init failed.\n", tp->dev->name);
10681                         return;
10682                 }
10683                 tg3_enable_nvram_access(tp);
10684
10685                 tp->nvram_size = 0;
10686
10687                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10688                         tg3_get_5752_nvram_info(tp);
10689                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10690                         tg3_get_5755_nvram_info(tp);
10691                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10692                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10693                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10694                         tg3_get_5787_nvram_info(tp);
10695                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10696                         tg3_get_5761_nvram_info(tp);
10697                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10698                         tg3_get_5906_nvram_info(tp);
10699                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
10700                         tg3_get_57780_nvram_info(tp);
10701                 else
10702                         tg3_get_nvram_info(tp);
10703
10704                 if (tp->nvram_size == 0)
10705                         tg3_get_nvram_size(tp);
10706
10707                 tg3_disable_nvram_access(tp);
10708                 tg3_nvram_unlock(tp);
10709
10710         } else {
10711                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
10712
10713                 tg3_get_eeprom_size(tp);
10714         }
10715 }
10716
10717 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10718                                     u32 offset, u32 len, u8 *buf)
10719 {
10720         int i, j, rc = 0;
10721         u32 val;
10722
10723         for (i = 0; i < len; i += 4) {
10724                 u32 addr;
10725                 __be32 data;
10726
10727                 addr = offset + i;
10728
10729                 memcpy(&data, buf + i, 4);
10730
10731                 /*
10732                  * The SEEPROM interface expects the data to always be opposite
10733                  * the native endian format.  We accomplish this by reversing
10734                  * all the operations that would have been performed on the
10735                  * data from a call to tg3_nvram_read_be32().
10736                  */
10737                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
10738
10739                 val = tr32(GRC_EEPROM_ADDR);
10740                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10741
10742                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10743                         EEPROM_ADDR_READ);
10744                 tw32(GRC_EEPROM_ADDR, val |
10745                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
10746                         (addr & EEPROM_ADDR_ADDR_MASK) |
10747                         EEPROM_ADDR_START |
10748                         EEPROM_ADDR_WRITE);
10749
10750                 for (j = 0; j < 1000; j++) {
10751                         val = tr32(GRC_EEPROM_ADDR);
10752
10753                         if (val & EEPROM_ADDR_COMPLETE)
10754                                 break;
10755                         msleep(1);
10756                 }
10757                 if (!(val & EEPROM_ADDR_COMPLETE)) {
10758                         rc = -EBUSY;
10759                         break;
10760                 }
10761         }
10762
10763         return rc;
10764 }
10765
10766 /* offset and length are dword aligned */
10767 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
10768                 u8 *buf)
10769 {
10770         int ret = 0;
10771         u32 pagesize = tp->nvram_pagesize;
10772         u32 pagemask = pagesize - 1;
10773         u32 nvram_cmd;
10774         u8 *tmp;
10775
10776         tmp = kmalloc(pagesize, GFP_KERNEL);
10777         if (tmp == NULL)
10778                 return -ENOMEM;
10779
10780         while (len) {
10781                 int j;
10782                 u32 phy_addr, page_off, size;
10783
10784                 phy_addr = offset & ~pagemask;
10785
10786                 for (j = 0; j < pagesize; j += 4) {
10787                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
10788                                                   (__be32 *) (tmp + j));
10789                         if (ret)
10790                                 break;
10791                 }
10792                 if (ret)
10793                         break;
10794
10795                 page_off = offset & pagemask;
10796                 size = pagesize;
10797                 if (len < size)
10798                         size = len;
10799
10800                 len -= size;
10801
10802                 memcpy(tmp + page_off, buf, size);
10803
10804                 offset = offset + (pagesize - page_off);
10805
10806                 tg3_enable_nvram_access(tp);
10807
10808                 /*
10809                  * Before we can erase the flash page, we need
10810                  * to issue a special "write enable" command.
10811                  */
10812                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10813
10814                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10815                         break;
10816
10817                 /* Erase the target page */
10818                 tw32(NVRAM_ADDR, phy_addr);
10819
10820                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
10821                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
10822
10823                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10824                         break;
10825
10826                 /* Issue another write enable to start the write. */
10827                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10828
10829                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10830                         break;
10831
10832                 for (j = 0; j < pagesize; j += 4) {
10833                         __be32 data;
10834
10835                         data = *((__be32 *) (tmp + j));
10836
10837                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
10838
10839                         tw32(NVRAM_ADDR, phy_addr + j);
10840
10841                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
10842                                 NVRAM_CMD_WR;
10843
10844                         if (j == 0)
10845                                 nvram_cmd |= NVRAM_CMD_FIRST;
10846                         else if (j == (pagesize - 4))
10847                                 nvram_cmd |= NVRAM_CMD_LAST;
10848
10849                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10850                                 break;
10851                 }
10852                 if (ret)
10853                         break;
10854         }
10855
10856         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10857         tg3_nvram_exec_cmd(tp, nvram_cmd);
10858
10859         kfree(tmp);
10860
10861         return ret;
10862 }
10863
10864 /* offset and length are dword aligned */
10865 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
10866                 u8 *buf)
10867 {
10868         int i, ret = 0;
10869
10870         for (i = 0; i < len; i += 4, offset += 4) {
10871                 u32 page_off, phy_addr, nvram_cmd;
10872                 __be32 data;
10873
10874                 memcpy(&data, buf + i, 4);
10875                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
10876
10877                 page_off = offset % tp->nvram_pagesize;
10878
10879                 phy_addr = tg3_nvram_phys_addr(tp, offset);
10880
10881                 tw32(NVRAM_ADDR, phy_addr);
10882
10883                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
10884
10885                 if ((page_off == 0) || (i == 0))
10886                         nvram_cmd |= NVRAM_CMD_FIRST;
10887                 if (page_off == (tp->nvram_pagesize - 4))
10888                         nvram_cmd |= NVRAM_CMD_LAST;
10889
10890                 if (i == (len - 4))
10891                         nvram_cmd |= NVRAM_CMD_LAST;
10892
10893                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10894                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
10895                     (tp->nvram_jedecnum == JEDEC_ST) &&
10896                     (nvram_cmd & NVRAM_CMD_FIRST)) {
10897
10898                         if ((ret = tg3_nvram_exec_cmd(tp,
10899                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
10900                                 NVRAM_CMD_DONE)))
10901
10902                                 break;
10903                 }
10904                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10905                         /* We always do complete word writes to eeprom. */
10906                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
10907                 }
10908
10909                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10910                         break;
10911         }
10912         return ret;
10913 }
10914
10915 /* offset and length are dword aligned */
10916 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
10917 {
10918         int ret;
10919
10920         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
10921                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
10922                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
10923                 udelay(40);
10924         }
10925
10926         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
10927                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
10928         }
10929         else {
10930                 u32 grc_mode;
10931
10932                 ret = tg3_nvram_lock(tp);
10933                 if (ret)
10934                         return ret;
10935
10936                 tg3_enable_nvram_access(tp);
10937                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
10938                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
10939                         tw32(NVRAM_WRITE1, 0x406);
10940
10941                 grc_mode = tr32(GRC_MODE);
10942                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
10943
10944                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
10945                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10946
10947                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
10948                                 buf);
10949                 }
10950                 else {
10951                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
10952                                 buf);
10953                 }
10954
10955                 grc_mode = tr32(GRC_MODE);
10956                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
10957
10958                 tg3_disable_nvram_access(tp);
10959                 tg3_nvram_unlock(tp);
10960         }
10961
10962         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
10963                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10964                 udelay(40);
10965         }
10966
10967         return ret;
10968 }
10969
10970 struct subsys_tbl_ent {
10971         u16 subsys_vendor, subsys_devid;
10972         u32 phy_id;
10973 };
10974
10975 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
10976         /* Broadcom boards. */
10977         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
10978         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
10979         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
10980         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
10981         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
10982         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
10983         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
10984         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
10985         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
10986         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
10987         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
10988
10989         /* 3com boards. */
10990         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
10991         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
10992         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
10993         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
10994         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
10995
10996         /* DELL boards. */
10997         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
10998         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
10999         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11000         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11001
11002         /* Compaq boards. */
11003         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11004         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11005         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
11006         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11007         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11008
11009         /* IBM boards. */
11010         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11011 };
11012
11013 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11014 {
11015         int i;
11016
11017         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11018                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11019                      tp->pdev->subsystem_vendor) &&
11020                     (subsys_id_to_phy_id[i].subsys_devid ==
11021                      tp->pdev->subsystem_device))
11022                         return &subsys_id_to_phy_id[i];
11023         }
11024         return NULL;
11025 }
11026
11027 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11028 {
11029         u32 val;
11030         u16 pmcsr;
11031
11032         /* On some early chips the SRAM cannot be accessed in D3hot state,
11033          * so need make sure we're in D0.
11034          */
11035         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11036         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11037         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11038         msleep(1);
11039
11040         /* Make sure register accesses (indirect or otherwise)
11041          * will function correctly.
11042          */
11043         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11044                                tp->misc_host_ctrl);
11045
11046         /* The memory arbiter has to be enabled in order for SRAM accesses
11047          * to succeed.  Normally on powerup the tg3 chip firmware will make
11048          * sure it is enabled, but other entities such as system netboot
11049          * code might disable it.
11050          */
11051         val = tr32(MEMARB_MODE);
11052         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11053
11054         tp->phy_id = PHY_ID_INVALID;
11055         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11056
11057         /* Assume an onboard device and WOL capable by default.  */
11058         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
11059
11060         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11061                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
11062                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11063                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11064                 }
11065                 val = tr32(VCPU_CFGSHDW);
11066                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
11067                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11068                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
11069                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
11070                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11071                 goto done;
11072         }
11073
11074         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11075         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11076                 u32 nic_cfg, led_cfg;
11077                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
11078                 int eeprom_phy_serdes = 0;
11079
11080                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11081                 tp->nic_sram_data_cfg = nic_cfg;
11082
11083                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11084                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11085                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11086                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11087                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11088                     (ver > 0) && (ver < 0x100))
11089                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11090
11091                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11092                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11093
11094                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11095                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11096                         eeprom_phy_serdes = 1;
11097
11098                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11099                 if (nic_phy_id != 0) {
11100                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11101                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11102
11103                         eeprom_phy_id  = (id1 >> 16) << 10;
11104                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
11105                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
11106                 } else
11107                         eeprom_phy_id = 0;
11108
11109                 tp->phy_id = eeprom_phy_id;
11110                 if (eeprom_phy_serdes) {
11111                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
11112                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11113                         else
11114                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11115                 }
11116
11117                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11118                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11119                                     SHASTA_EXT_LED_MODE_MASK);
11120                 else
11121                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11122
11123                 switch (led_cfg) {
11124                 default:
11125                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11126                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11127                         break;
11128
11129                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11130                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11131                         break;
11132
11133                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11134                         tp->led_ctrl = LED_CTRL_MODE_MAC;
11135
11136                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11137                          * read on some older 5700/5701 bootcode.
11138                          */
11139                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11140                             ASIC_REV_5700 ||
11141                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
11142                             ASIC_REV_5701)
11143                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11144
11145                         break;
11146
11147                 case SHASTA_EXT_LED_SHARED:
11148                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
11149                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11150                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11151                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11152                                                  LED_CTRL_MODE_PHY_2);
11153                         break;
11154
11155                 case SHASTA_EXT_LED_MAC:
11156                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11157                         break;
11158
11159                 case SHASTA_EXT_LED_COMBO:
11160                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
11161                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11162                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11163                                                  LED_CTRL_MODE_PHY_2);
11164                         break;
11165
11166                 }
11167
11168                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11169                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11170                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11171                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11172
11173                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11174                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11175
11176                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
11177                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
11178                         if ((tp->pdev->subsystem_vendor ==
11179                              PCI_VENDOR_ID_ARIMA) &&
11180                             (tp->pdev->subsystem_device == 0x205a ||
11181                              tp->pdev->subsystem_device == 0x2063))
11182                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11183                 } else {
11184                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11185                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11186                 }
11187
11188                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11189                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
11190                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11191                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11192                 }
11193
11194                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11195                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11196                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
11197
11198                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11199                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11200                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
11201
11202                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
11203                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
11204                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11205
11206                 if (cfg2 & (1 << 17))
11207                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11208
11209                 /* serdes signal pre-emphasis in register 0x590 set by */
11210                 /* bootcode if bit 18 is set */
11211                 if (cfg2 & (1 << 18))
11212                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
11213
11214                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11215                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
11216                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11217                         tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11218
11219                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11220                         u32 cfg3;
11221
11222                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11223                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11224                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11225                 }
11226
11227                 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11228                         tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11229                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11230                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11231                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11232                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
11233         }
11234 done:
11235         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11236         device_set_wakeup_enable(&tp->pdev->dev,
11237                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
11238 }
11239
11240 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11241 {
11242         int i;
11243         u32 val;
11244
11245         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11246         tw32(OTP_CTRL, cmd);
11247
11248         /* Wait for up to 1 ms for command to execute. */
11249         for (i = 0; i < 100; i++) {
11250                 val = tr32(OTP_STATUS);
11251                 if (val & OTP_STATUS_CMD_DONE)
11252                         break;
11253                 udelay(10);
11254         }
11255
11256         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11257 }
11258
11259 /* Read the gphy configuration from the OTP region of the chip.  The gphy
11260  * configuration is a 32-bit value that straddles the alignment boundary.
11261  * We do two 32-bit reads and then shift and merge the results.
11262  */
11263 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11264 {
11265         u32 bhalf_otp, thalf_otp;
11266
11267         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11268
11269         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11270                 return 0;
11271
11272         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11273
11274         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11275                 return 0;
11276
11277         thalf_otp = tr32(OTP_READ_DATA);
11278
11279         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11280
11281         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11282                 return 0;
11283
11284         bhalf_otp = tr32(OTP_READ_DATA);
11285
11286         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11287 }
11288
11289 static int __devinit tg3_phy_probe(struct tg3 *tp)
11290 {
11291         u32 hw_phy_id_1, hw_phy_id_2;
11292         u32 hw_phy_id, hw_phy_id_masked;
11293         int err;
11294
11295         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11296                 return tg3_phy_init(tp);
11297
11298         /* Reading the PHY ID register can conflict with ASF
11299          * firmware access to the PHY hardware.
11300          */
11301         err = 0;
11302         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11303             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
11304                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11305         } else {
11306                 /* Now read the physical PHY_ID from the chip and verify
11307                  * that it is sane.  If it doesn't look good, we fall back
11308                  * to either the hard-coded table based PHY_ID and failing
11309                  * that the value found in the eeprom area.
11310                  */
11311                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11312                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11313
11314                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
11315                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11316                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
11317
11318                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11319         }
11320
11321         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11322                 tp->phy_id = hw_phy_id;
11323                 if (hw_phy_id_masked == PHY_ID_BCM8002)
11324                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11325                 else
11326                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
11327         } else {
11328                 if (tp->phy_id != PHY_ID_INVALID) {
11329                         /* Do nothing, phy ID already set up in
11330                          * tg3_get_eeprom_hw_cfg().
11331                          */
11332                 } else {
11333                         struct subsys_tbl_ent *p;
11334
11335                         /* No eeprom signature?  Try the hardcoded
11336                          * subsys device table.
11337                          */
11338                         p = lookup_by_subsys(tp);
11339                         if (!p)
11340                                 return -ENODEV;
11341
11342                         tp->phy_id = p->phy_id;
11343                         if (!tp->phy_id ||
11344                             tp->phy_id == PHY_ID_BCM8002)
11345                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11346                 }
11347         }
11348
11349         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
11350             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
11351             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
11352                 u32 bmsr, adv_reg, tg3_ctrl, mask;
11353
11354                 tg3_readphy(tp, MII_BMSR, &bmsr);
11355                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11356                     (bmsr & BMSR_LSTATUS))
11357                         goto skip_phy_reset;
11358
11359                 err = tg3_phy_reset(tp);
11360                 if (err)
11361                         return err;
11362
11363                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11364                            ADVERTISE_100HALF | ADVERTISE_100FULL |
11365                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11366                 tg3_ctrl = 0;
11367                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11368                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11369                                     MII_TG3_CTRL_ADV_1000_FULL);
11370                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11371                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11372                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11373                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
11374                 }
11375
11376                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11377                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11378                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11379                 if (!tg3_copper_is_advertising_all(tp, mask)) {
11380                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11381
11382                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11383                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11384
11385                         tg3_writephy(tp, MII_BMCR,
11386                                      BMCR_ANENABLE | BMCR_ANRESTART);
11387                 }
11388                 tg3_phy_set_wirespeed(tp);
11389
11390                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11391                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11392                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11393         }
11394
11395 skip_phy_reset:
11396         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11397                 err = tg3_init_5401phy_dsp(tp);
11398                 if (err)
11399                         return err;
11400         }
11401
11402         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11403                 err = tg3_init_5401phy_dsp(tp);
11404         }
11405
11406         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
11407                 tp->link_config.advertising =
11408                         (ADVERTISED_1000baseT_Half |
11409                          ADVERTISED_1000baseT_Full |
11410                          ADVERTISED_Autoneg |
11411                          ADVERTISED_FIBRE);
11412         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11413                 tp->link_config.advertising &=
11414                         ~(ADVERTISED_1000baseT_Half |
11415                           ADVERTISED_1000baseT_Full);
11416
11417         return err;
11418 }
11419
11420 static void __devinit tg3_read_partno(struct tg3 *tp)
11421 {
11422         unsigned char vpd_data[256];   /* in little-endian format */
11423         unsigned int i;
11424         u32 magic;
11425
11426         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11427             tg3_nvram_read(tp, 0x0, &magic))
11428                 goto out_not_found;
11429
11430         if (magic == TG3_EEPROM_MAGIC) {
11431                 for (i = 0; i < 256; i += 4) {
11432                         u32 tmp;
11433
11434                         /* The data is in little-endian format in NVRAM.
11435                          * Use the big-endian read routines to preserve
11436                          * the byte order as it exists in NVRAM.
11437                          */
11438                         if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
11439                                 goto out_not_found;
11440
11441                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
11442                 }
11443         } else {
11444                 int vpd_cap;
11445
11446                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11447                 for (i = 0; i < 256; i += 4) {
11448                         u32 tmp, j = 0;
11449                         __le32 v;
11450                         u16 tmp16;
11451
11452                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11453                                               i);
11454                         while (j++ < 100) {
11455                                 pci_read_config_word(tp->pdev, vpd_cap +
11456                                                      PCI_VPD_ADDR, &tmp16);
11457                                 if (tmp16 & 0x8000)
11458                                         break;
11459                                 msleep(1);
11460                         }
11461                         if (!(tmp16 & 0x8000))
11462                                 goto out_not_found;
11463
11464                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11465                                               &tmp);
11466                         v = cpu_to_le32(tmp);
11467                         memcpy(&vpd_data[i], &v, sizeof(v));
11468                 }
11469         }
11470
11471         /* Now parse and find the part number. */
11472         for (i = 0; i < 254; ) {
11473                 unsigned char val = vpd_data[i];
11474                 unsigned int block_end;
11475
11476                 if (val == 0x82 || val == 0x91) {
11477                         i = (i + 3 +
11478                              (vpd_data[i + 1] +
11479                               (vpd_data[i + 2] << 8)));
11480                         continue;
11481                 }
11482
11483                 if (val != 0x90)
11484                         goto out_not_found;
11485
11486                 block_end = (i + 3 +
11487                              (vpd_data[i + 1] +
11488                               (vpd_data[i + 2] << 8)));
11489                 i += 3;
11490
11491                 if (block_end > 256)
11492                         goto out_not_found;
11493
11494                 while (i < (block_end - 2)) {
11495                         if (vpd_data[i + 0] == 'P' &&
11496                             vpd_data[i + 1] == 'N') {
11497                                 int partno_len = vpd_data[i + 2];
11498
11499                                 i += 3;
11500                                 if (partno_len > 24 || (partno_len + i) > 256)
11501                                         goto out_not_found;
11502
11503                                 memcpy(tp->board_part_number,
11504                                        &vpd_data[i], partno_len);
11505
11506                                 /* Success. */
11507                                 return;
11508                         }
11509                         i += 3 + vpd_data[i + 2];
11510                 }
11511
11512                 /* Part number not found. */
11513                 goto out_not_found;
11514         }
11515
11516 out_not_found:
11517         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11518                 strcpy(tp->board_part_number, "BCM95906");
11519         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11520                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
11521                 strcpy(tp->board_part_number, "BCM57780");
11522         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11523                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
11524                 strcpy(tp->board_part_number, "BCM57760");
11525         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11526                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
11527                 strcpy(tp->board_part_number, "BCM57790");
11528         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11529                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
11530                 strcpy(tp->board_part_number, "BCM57788");
11531         else
11532                 strcpy(tp->board_part_number, "none");
11533 }
11534
11535 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11536 {
11537         u32 val;
11538
11539         if (tg3_nvram_read(tp, offset, &val) ||
11540             (val & 0xfc000000) != 0x0c000000 ||
11541             tg3_nvram_read(tp, offset + 4, &val) ||
11542             val != 0)
11543                 return 0;
11544
11545         return 1;
11546 }
11547
11548 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
11549 {
11550         u32 val, offset, start, ver_offset;
11551         int i;
11552         bool newver = false;
11553
11554         if (tg3_nvram_read(tp, 0xc, &offset) ||
11555             tg3_nvram_read(tp, 0x4, &start))
11556                 return;
11557
11558         offset = tg3_nvram_logical_addr(tp, offset);
11559
11560         if (tg3_nvram_read(tp, offset, &val))
11561                 return;
11562
11563         if ((val & 0xfc000000) == 0x0c000000) {
11564                 if (tg3_nvram_read(tp, offset + 4, &val))
11565                         return;
11566
11567                 if (val == 0)
11568                         newver = true;
11569         }
11570
11571         if (newver) {
11572                 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
11573                         return;
11574
11575                 offset = offset + ver_offset - start;
11576                 for (i = 0; i < 16; i += 4) {
11577                         __be32 v;
11578                         if (tg3_nvram_read_be32(tp, offset + i, &v))
11579                                 return;
11580
11581                         memcpy(tp->fw_ver + i, &v, sizeof(v));
11582                 }
11583         } else {
11584                 u32 major, minor;
11585
11586                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
11587                         return;
11588
11589                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
11590                         TG3_NVM_BCVER_MAJSFT;
11591                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
11592                 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
11593         }
11594 }
11595
11596 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
11597 {
11598         u32 val, major, minor;
11599
11600         /* Use native endian representation */
11601         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
11602                 return;
11603
11604         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
11605                 TG3_NVM_HWSB_CFG1_MAJSFT;
11606         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
11607                 TG3_NVM_HWSB_CFG1_MINSFT;
11608
11609         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
11610 }
11611
11612 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
11613 {
11614         u32 offset, major, minor, build;
11615
11616         tp->fw_ver[0] = 's';
11617         tp->fw_ver[1] = 'b';
11618         tp->fw_ver[2] = '\0';
11619
11620         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
11621                 return;
11622
11623         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
11624         case TG3_EEPROM_SB_REVISION_0:
11625                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
11626                 break;
11627         case TG3_EEPROM_SB_REVISION_2:
11628                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
11629                 break;
11630         case TG3_EEPROM_SB_REVISION_3:
11631                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
11632                 break;
11633         default:
11634                 return;
11635         }
11636
11637         if (tg3_nvram_read(tp, offset, &val))
11638                 return;
11639
11640         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
11641                 TG3_EEPROM_SB_EDH_BLD_SHFT;
11642         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
11643                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
11644         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
11645
11646         if (minor > 99 || build > 26)
11647                 return;
11648
11649         snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
11650
11651         if (build > 0) {
11652                 tp->fw_ver[8] = 'a' + build - 1;
11653                 tp->fw_ver[9] = '\0';
11654         }
11655 }
11656
11657 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
11658 {
11659         u32 val, offset, start;
11660         int i, vlen;
11661
11662         for (offset = TG3_NVM_DIR_START;
11663              offset < TG3_NVM_DIR_END;
11664              offset += TG3_NVM_DIRENT_SIZE) {
11665                 if (tg3_nvram_read(tp, offset, &val))
11666                         return;
11667
11668                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
11669                         break;
11670         }
11671
11672         if (offset == TG3_NVM_DIR_END)
11673                 return;
11674
11675         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11676                 start = 0x08000000;
11677         else if (tg3_nvram_read(tp, offset - 4, &start))
11678                 return;
11679
11680         if (tg3_nvram_read(tp, offset + 4, &offset) ||
11681             !tg3_fw_img_is_valid(tp, offset) ||
11682             tg3_nvram_read(tp, offset + 8, &val))
11683                 return;
11684
11685         offset += val - start;
11686
11687         vlen = strlen(tp->fw_ver);
11688
11689         tp->fw_ver[vlen++] = ',';
11690         tp->fw_ver[vlen++] = ' ';
11691
11692         for (i = 0; i < 4; i++) {
11693                 __be32 v;
11694                 if (tg3_nvram_read_be32(tp, offset, &v))
11695                         return;
11696
11697                 offset += sizeof(v);
11698
11699                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
11700                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
11701                         break;
11702                 }
11703
11704                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
11705                 vlen += sizeof(v);
11706         }
11707 }
11708
11709 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
11710 {
11711         int vlen;
11712         u32 apedata;
11713
11714         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
11715             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
11716                 return;
11717
11718         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
11719         if (apedata != APE_SEG_SIG_MAGIC)
11720                 return;
11721
11722         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
11723         if (!(apedata & APE_FW_STATUS_READY))
11724                 return;
11725
11726         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
11727
11728         vlen = strlen(tp->fw_ver);
11729
11730         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
11731                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
11732                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
11733                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
11734                  (apedata & APE_FW_VERSION_BLDMSK));
11735 }
11736
11737 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
11738 {
11739         u32 val;
11740
11741         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
11742                 tp->fw_ver[0] = 's';
11743                 tp->fw_ver[1] = 'b';
11744                 tp->fw_ver[2] = '\0';
11745
11746                 return;
11747         }
11748
11749         if (tg3_nvram_read(tp, 0, &val))
11750                 return;
11751
11752         if (val == TG3_EEPROM_MAGIC)
11753                 tg3_read_bc_ver(tp);
11754         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
11755                 tg3_read_sb_ver(tp, val);
11756         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
11757                 tg3_read_hwsb_ver(tp);
11758         else
11759                 return;
11760
11761         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11762              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
11763                 return;
11764
11765         tg3_read_mgmtfw_ver(tp);
11766
11767         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
11768 }
11769
11770 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
11771
11772 static int __devinit tg3_get_invariants(struct tg3 *tp)
11773 {
11774         static struct pci_device_id write_reorder_chipsets[] = {
11775                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11776                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
11777                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11778                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
11779                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
11780                              PCI_DEVICE_ID_VIA_8385_0) },
11781                 { },
11782         };
11783         u32 misc_ctrl_reg;
11784         u32 pci_state_reg, grc_misc_cfg;
11785         u32 val;
11786         u16 pci_cmd;
11787         int err;
11788
11789         /* Force memory write invalidate off.  If we leave it on,
11790          * then on 5700_BX chips we have to enable a workaround.
11791          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11792          * to match the cacheline size.  The Broadcom driver have this
11793          * workaround but turns MWI off all the times so never uses
11794          * it.  This seems to suggest that the workaround is insufficient.
11795          */
11796         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11797         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
11798         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11799
11800         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11801          * has the register indirect write enable bit set before
11802          * we try to access any of the MMIO registers.  It is also
11803          * critical that the PCI-X hw workaround situation is decided
11804          * before that as well.
11805          */
11806         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11807                               &misc_ctrl_reg);
11808
11809         tp->pci_chip_rev_id = (misc_ctrl_reg >>
11810                                MISC_HOST_CTRL_CHIPREV_SHIFT);
11811         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
11812                 u32 prod_id_asic_rev;
11813
11814                 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
11815                                       &prod_id_asic_rev);
11816                 tp->pci_chip_rev_id = prod_id_asic_rev;
11817         }
11818
11819         /* Wrong chip ID in 5752 A0. This code can be removed later
11820          * as A0 is not in production.
11821          */
11822         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
11823                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
11824
11825         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11826          * we need to disable memory and use config. cycles
11827          * only to access all registers. The 5702/03 chips
11828          * can mistakenly decode the special cycles from the
11829          * ICH chipsets as memory write cycles, causing corruption
11830          * of register and memory space. Only certain ICH bridges
11831          * will drive special cycles with non-zero data during the
11832          * address phase which can fall within the 5703's address
11833          * range. This is not an ICH bug as the PCI spec allows
11834          * non-zero address during special cycles. However, only
11835          * these ICH bridges are known to drive non-zero addresses
11836          * during special cycles.
11837          *
11838          * Since special cycles do not cross PCI bridges, we only
11839          * enable this workaround if the 5703 is on the secondary
11840          * bus of these ICH bridges.
11841          */
11842         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
11843             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
11844                 static struct tg3_dev_id {
11845                         u32     vendor;
11846                         u32     device;
11847                         u32     rev;
11848                 } ich_chipsets[] = {
11849                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
11850                           PCI_ANY_ID },
11851                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
11852                           PCI_ANY_ID },
11853                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
11854                           0xa },
11855                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
11856                           PCI_ANY_ID },
11857                         { },
11858                 };
11859                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
11860                 struct pci_dev *bridge = NULL;
11861
11862                 while (pci_id->vendor != 0) {
11863                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
11864                                                 bridge);
11865                         if (!bridge) {
11866                                 pci_id++;
11867                                 continue;
11868                         }
11869                         if (pci_id->rev != PCI_ANY_ID) {
11870                                 if (bridge->revision > pci_id->rev)
11871                                         continue;
11872                         }
11873                         if (bridge->subordinate &&
11874                             (bridge->subordinate->number ==
11875                              tp->pdev->bus->number)) {
11876
11877                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
11878                                 pci_dev_put(bridge);
11879                                 break;
11880                         }
11881                 }
11882         }
11883
11884         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
11885                 static struct tg3_dev_id {
11886                         u32     vendor;
11887                         u32     device;
11888                 } bridge_chipsets[] = {
11889                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
11890                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
11891                         { },
11892                 };
11893                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
11894                 struct pci_dev *bridge = NULL;
11895
11896                 while (pci_id->vendor != 0) {
11897                         bridge = pci_get_device(pci_id->vendor,
11898                                                 pci_id->device,
11899                                                 bridge);
11900                         if (!bridge) {
11901                                 pci_id++;
11902                                 continue;
11903                         }
11904                         if (bridge->subordinate &&
11905                             (bridge->subordinate->number <=
11906                              tp->pdev->bus->number) &&
11907                             (bridge->subordinate->subordinate >=
11908                              tp->pdev->bus->number)) {
11909                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
11910                                 pci_dev_put(bridge);
11911                                 break;
11912                         }
11913                 }
11914         }
11915
11916         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
11917          * DMA addresses > 40-bit. This bridge may have other additional
11918          * 57xx devices behind it in some 4-port NIC designs for example.
11919          * Any tg3 device found behind the bridge will also need the 40-bit
11920          * DMA workaround.
11921          */
11922         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
11923             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11924                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
11925                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11926                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
11927         }
11928         else {
11929                 struct pci_dev *bridge = NULL;
11930
11931                 do {
11932                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
11933                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
11934                                                 bridge);
11935                         if (bridge && bridge->subordinate &&
11936                             (bridge->subordinate->number <=
11937                              tp->pdev->bus->number) &&
11938                             (bridge->subordinate->subordinate >=
11939                              tp->pdev->bus->number)) {
11940                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11941                                 pci_dev_put(bridge);
11942                                 break;
11943                         }
11944                 } while (bridge);
11945         }
11946
11947         /* Initialize misc host control in PCI block. */
11948         tp->misc_host_ctrl |= (misc_ctrl_reg &
11949                                MISC_HOST_CTRL_CHIPREV);
11950         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11951                                tp->misc_host_ctrl);
11952
11953         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11954             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11955                 tp->pdev_peer = tg3_find_peer(tp);
11956
11957         /* Intentionally exclude ASIC_REV_5906 */
11958         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11959             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11960             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11961             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
11962             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
11963             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11964                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
11965
11966         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
11967             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
11968             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
11969             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
11970             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
11971                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
11972
11973         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
11974             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11975                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
11976
11977         /* 5700 B0 chips do not support checksumming correctly due
11978          * to hardware bugs.
11979          */
11980         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
11981                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
11982         else {
11983                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
11984                 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
11985                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
11986                         tp->dev->features |= NETIF_F_IPV6_CSUM;
11987         }
11988
11989         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
11990                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
11991                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
11992                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
11993                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
11994                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
11995                      tp->pdev_peer == tp->pdev))
11996                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
11997
11998                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
11999                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12000                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12001                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
12002                 } else {
12003                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
12004                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12005                                 ASIC_REV_5750 &&
12006                             tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
12007                                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
12008                 }
12009         }
12010
12011         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12012              (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12013                 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
12014
12015         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12016                               &pci_state_reg);
12017
12018         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12019         if (tp->pcie_cap != 0) {
12020                 u16 lnkctl;
12021
12022                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12023
12024                 pcie_set_readrq(tp->pdev, 4096);
12025
12026                 pci_read_config_word(tp->pdev,
12027                                      tp->pcie_cap + PCI_EXP_LNKCTL,
12028                                      &lnkctl);
12029                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12030                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12031                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
12032                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12033                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12034                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12035                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
12036                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
12037                 }
12038         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
12039                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12040         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12041                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12042                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12043                 if (!tp->pcix_cap) {
12044                         printk(KERN_ERR PFX "Cannot find PCI-X "
12045                                             "capability, aborting.\n");
12046                         return -EIO;
12047                 }
12048
12049                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12050                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12051         }
12052
12053         /* If we have an AMD 762 or VIA K8T800 chipset, write
12054          * reordering to the mailbox registers done by the host
12055          * controller can cause major troubles.  We read back from
12056          * every mailbox register write to force the writes to be
12057          * posted to the chip in order.
12058          */
12059         if (pci_dev_present(write_reorder_chipsets) &&
12060             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12061                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12062
12063         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12064                              &tp->pci_cacheline_sz);
12065         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12066                              &tp->pci_lat_timer);
12067         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12068             tp->pci_lat_timer < 64) {
12069                 tp->pci_lat_timer = 64;
12070                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12071                                       tp->pci_lat_timer);
12072         }
12073
12074         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12075                 /* 5700 BX chips need to have their TX producer index
12076                  * mailboxes written twice to workaround a bug.
12077                  */
12078                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
12079
12080                 /* If we are in PCI-X mode, enable register write workaround.
12081                  *
12082                  * The workaround is to use indirect register accesses
12083                  * for all chip writes not to mailbox registers.
12084                  */
12085                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12086                         u32 pm_reg;
12087
12088                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12089
12090                         /* The chip can have it's power management PCI config
12091                          * space registers clobbered due to this bug.
12092                          * So explicitly force the chip into D0 here.
12093                          */
12094                         pci_read_config_dword(tp->pdev,
12095                                               tp->pm_cap + PCI_PM_CTRL,
12096                                               &pm_reg);
12097                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12098                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
12099                         pci_write_config_dword(tp->pdev,
12100                                                tp->pm_cap + PCI_PM_CTRL,
12101                                                pm_reg);
12102
12103                         /* Also, force SERR#/PERR# in PCI command. */
12104                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12105                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12106                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12107                 }
12108         }
12109
12110         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12111                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12112         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12113                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12114
12115         /* Chip-specific fixup from Broadcom driver */
12116         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12117             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12118                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12119                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12120         }
12121
12122         /* Default fast path register access methods */
12123         tp->read32 = tg3_read32;
12124         tp->write32 = tg3_write32;
12125         tp->read32_mbox = tg3_read32;
12126         tp->write32_mbox = tg3_write32;
12127         tp->write32_tx_mbox = tg3_write32;
12128         tp->write32_rx_mbox = tg3_write32;
12129
12130         /* Various workaround register access methods */
12131         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12132                 tp->write32 = tg3_write_indirect_reg32;
12133         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12134                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12135                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12136                 /*
12137                  * Back to back register writes can cause problems on these
12138                  * chips, the workaround is to read back all reg writes
12139                  * except those to mailbox regs.
12140                  *
12141                  * See tg3_write_indirect_reg32().
12142                  */
12143                 tp->write32 = tg3_write_flush_reg32;
12144         }
12145
12146
12147         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12148             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12149                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12150                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12151                         tp->write32_rx_mbox = tg3_write_flush_reg32;
12152         }
12153
12154         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12155                 tp->read32 = tg3_read_indirect_reg32;
12156                 tp->write32 = tg3_write_indirect_reg32;
12157                 tp->read32_mbox = tg3_read_indirect_mbox;
12158                 tp->write32_mbox = tg3_write_indirect_mbox;
12159                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12160                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12161
12162                 iounmap(tp->regs);
12163                 tp->regs = NULL;
12164
12165                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12166                 pci_cmd &= ~PCI_COMMAND_MEMORY;
12167                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12168         }
12169         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12170                 tp->read32_mbox = tg3_read32_mbox_5906;
12171                 tp->write32_mbox = tg3_write32_mbox_5906;
12172                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12173                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12174         }
12175
12176         if (tp->write32 == tg3_write_indirect_reg32 ||
12177             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12178              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12179               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
12180                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12181
12182         /* Get eeprom hw config before calling tg3_set_power_state().
12183          * In particular, the TG3_FLG2_IS_NIC flag must be
12184          * determined before calling tg3_set_power_state() so that
12185          * we know whether or not to switch out of Vaux power.
12186          * When the flag is set, it means that GPIO1 is used for eeprom
12187          * write protect and also implies that it is a LOM where GPIOs
12188          * are not used to switch power.
12189          */
12190         tg3_get_eeprom_hw_cfg(tp);
12191
12192         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12193                 /* Allow reads and writes to the
12194                  * APE register and memory space.
12195                  */
12196                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12197                                  PCISTATE_ALLOW_APE_SHMEM_WR;
12198                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12199                                        pci_state_reg);
12200         }
12201
12202         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12203             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12204             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12205             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12206                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12207
12208         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12209          * GPIO1 driven high will bring 5700's external PHY out of reset.
12210          * It is also used as eeprom write protect on LOMs.
12211          */
12212         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12213         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12214             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12215                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12216                                        GRC_LCLCTRL_GPIO_OUTPUT1);
12217         /* Unused GPIO3 must be driven as output on 5752 because there
12218          * are no pull-up resistors on unused GPIO pins.
12219          */
12220         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12221                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
12222
12223         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12224             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12225                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12226
12227         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
12228             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
12229                 /* Turn off the debug UART. */
12230                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12231                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12232                         /* Keep VMain power. */
12233                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12234                                               GRC_LCLCTRL_GPIO_OUTPUT0;
12235         }
12236
12237         /* Force the chip into D0. */
12238         err = tg3_set_power_state(tp, PCI_D0);
12239         if (err) {
12240                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12241                        pci_name(tp->pdev));
12242                 return err;
12243         }
12244
12245         /* Derive initial jumbo mode from MTU assigned in
12246          * ether_setup() via the alloc_etherdev() call
12247          */
12248         if (tp->dev->mtu > ETH_DATA_LEN &&
12249             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12250                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
12251
12252         /* Determine WakeOnLan speed to use. */
12253         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12254             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12255             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12256             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12257                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12258         } else {
12259                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12260         }
12261
12262         /* A few boards don't want Ethernet@WireSpeed phy feature */
12263         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12264             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12265              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
12266              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
12267             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
12268             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
12269                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12270
12271         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12272             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12273                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12274         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12275                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12276
12277         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
12278             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906 &&
12279             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12280             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) {
12281                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12282                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12283                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12284                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
12285                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12286                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12287                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
12288                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12289                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
12290                 } else
12291                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12292         }
12293
12294         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12295             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12296                 tp->phy_otp = tg3_read_otp_phycfg(tp);
12297                 if (tp->phy_otp == 0)
12298                         tp->phy_otp = TG3_OTP_DEFAULT;
12299         }
12300
12301         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
12302                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12303         else
12304                 tp->mi_mode = MAC_MI_MODE_BASE;
12305
12306         tp->coalesce_mode = 0;
12307         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12308             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12309                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12310
12311         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12312             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12313                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12314
12315         if ((tp->pci_chip_rev_id == CHIPREV_ID_57780_A1 &&
12316              tr32(RCVLPC_STATS_ENABLE) & RCVLPC_STATSENAB_ASF_FIX) ||
12317             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0)
12318                 tp->tg3_flags3 |= TG3_FLG3_TOGGLE_10_100_L1PLLPD;
12319
12320         err = tg3_mdio_init(tp);
12321         if (err)
12322                 return err;
12323
12324         /* Initialize data/descriptor byte/word swapping. */
12325         val = tr32(GRC_MODE);
12326         val &= GRC_MODE_HOST_STACKUP;
12327         tw32(GRC_MODE, val | tp->grc_mode);
12328
12329         tg3_switch_clocks(tp);
12330
12331         /* Clear this out for sanity. */
12332         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12333
12334         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12335                               &pci_state_reg);
12336         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12337             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12338                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12339
12340                 if (chiprevid == CHIPREV_ID_5701_A0 ||
12341                     chiprevid == CHIPREV_ID_5701_B0 ||
12342                     chiprevid == CHIPREV_ID_5701_B2 ||
12343                     chiprevid == CHIPREV_ID_5701_B5) {
12344                         void __iomem *sram_base;
12345
12346                         /* Write some dummy words into the SRAM status block
12347                          * area, see if it reads back correctly.  If the return
12348                          * value is bad, force enable the PCIX workaround.
12349                          */
12350                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12351
12352                         writel(0x00000000, sram_base);
12353                         writel(0x00000000, sram_base + 4);
12354                         writel(0xffffffff, sram_base + 4);
12355                         if (readl(sram_base) != 0x00000000)
12356                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12357                 }
12358         }
12359
12360         udelay(50);
12361         tg3_nvram_init(tp);
12362
12363         grc_misc_cfg = tr32(GRC_MISC_CFG);
12364         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12365
12366         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12367             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12368              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12369                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12370
12371         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12372             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12373                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12374         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12375                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12376                                       HOSTCC_MODE_CLRTICK_TXBD);
12377
12378                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12379                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12380                                        tp->misc_host_ctrl);
12381         }
12382
12383         /* Preserve the APE MAC_MODE bits */
12384         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
12385                 tp->mac_mode = tr32(MAC_MODE) |
12386                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
12387         else
12388                 tp->mac_mode = TG3_DEF_MAC_MODE;
12389
12390         /* these are limited to 10/100 only */
12391         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12392              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12393             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12394              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12395              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12396               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12397               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12398             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12399              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
12400               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12401               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
12402             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
12403             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12404                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12405
12406         err = tg3_phy_probe(tp);
12407         if (err) {
12408                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12409                        pci_name(tp->pdev), err);
12410                 /* ... but do not return immediately ... */
12411                 tg3_mdio_fini(tp);
12412         }
12413
12414         tg3_read_partno(tp);
12415         tg3_read_fw_ver(tp);
12416
12417         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12418                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12419         } else {
12420                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12421                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12422                 else
12423                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12424         }
12425
12426         /* 5700 {AX,BX} chips have a broken status block link
12427          * change bit implementation, so we must use the
12428          * status register in those cases.
12429          */
12430         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12431                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12432         else
12433                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12434
12435         /* The led_ctrl is set during tg3_phy_probe, here we might
12436          * have to force the link status polling mechanism based
12437          * upon subsystem IDs.
12438          */
12439         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
12440             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12441             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12442                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12443                                   TG3_FLAG_USE_LINKCHG_REG);
12444         }
12445
12446         /* For all SERDES we poll the MAC status register. */
12447         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
12448                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
12449         else
12450                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
12451
12452         tp->rx_offset = NET_IP_ALIGN;
12453         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12454             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
12455                 tp->rx_offset = 0;
12456
12457         tp->rx_std_max_post = TG3_RX_RING_SIZE;
12458
12459         /* Increment the rx prod index on the rx std ring by at most
12460          * 8 for these chips to workaround hw errata.
12461          */
12462         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12463             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12464             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12465                 tp->rx_std_max_post = 8;
12466
12467         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12468                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12469                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
12470
12471         return err;
12472 }
12473
12474 #ifdef CONFIG_SPARC
12475 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12476 {
12477         struct net_device *dev = tp->dev;
12478         struct pci_dev *pdev = tp->pdev;
12479         struct device_node *dp = pci_device_to_OF_node(pdev);
12480         const unsigned char *addr;
12481         int len;
12482
12483         addr = of_get_property(dp, "local-mac-address", &len);
12484         if (addr && len == 6) {
12485                 memcpy(dev->dev_addr, addr, 6);
12486                 memcpy(dev->perm_addr, dev->dev_addr, 6);
12487                 return 0;
12488         }
12489         return -ENODEV;
12490 }
12491
12492 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12493 {
12494         struct net_device *dev = tp->dev;
12495
12496         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
12497         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
12498         return 0;
12499 }
12500 #endif
12501
12502 static int __devinit tg3_get_device_address(struct tg3 *tp)
12503 {
12504         struct net_device *dev = tp->dev;
12505         u32 hi, lo, mac_offset;
12506         int addr_ok = 0;
12507
12508 #ifdef CONFIG_SPARC
12509         if (!tg3_get_macaddr_sparc(tp))
12510                 return 0;
12511 #endif
12512
12513         mac_offset = 0x7c;
12514         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12515             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12516                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12517                         mac_offset = 0xcc;
12518                 if (tg3_nvram_lock(tp))
12519                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12520                 else
12521                         tg3_nvram_unlock(tp);
12522         }
12523         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12524                 mac_offset = 0x10;
12525
12526         /* First try to get it from MAC address mailbox. */
12527         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12528         if ((hi >> 16) == 0x484b) {
12529                 dev->dev_addr[0] = (hi >>  8) & 0xff;
12530                 dev->dev_addr[1] = (hi >>  0) & 0xff;
12531
12532                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12533                 dev->dev_addr[2] = (lo >> 24) & 0xff;
12534                 dev->dev_addr[3] = (lo >> 16) & 0xff;
12535                 dev->dev_addr[4] = (lo >>  8) & 0xff;
12536                 dev->dev_addr[5] = (lo >>  0) & 0xff;
12537
12538                 /* Some old bootcode may report a 0 MAC address in SRAM */
12539                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12540         }
12541         if (!addr_ok) {
12542                 /* Next, try NVRAM. */
12543                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
12544                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
12545                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
12546                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
12547                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
12548                 }
12549                 /* Finally just fetch it out of the MAC control regs. */
12550                 else {
12551                         hi = tr32(MAC_ADDR_0_HIGH);
12552                         lo = tr32(MAC_ADDR_0_LOW);
12553
12554                         dev->dev_addr[5] = lo & 0xff;
12555                         dev->dev_addr[4] = (lo >> 8) & 0xff;
12556                         dev->dev_addr[3] = (lo >> 16) & 0xff;
12557                         dev->dev_addr[2] = (lo >> 24) & 0xff;
12558                         dev->dev_addr[1] = hi & 0xff;
12559                         dev->dev_addr[0] = (hi >> 8) & 0xff;
12560                 }
12561         }
12562
12563         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
12564 #ifdef CONFIG_SPARC
12565                 if (!tg3_get_default_macaddr_sparc(tp))
12566                         return 0;
12567 #endif
12568                 return -EINVAL;
12569         }
12570         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
12571         return 0;
12572 }
12573
12574 #define BOUNDARY_SINGLE_CACHELINE       1
12575 #define BOUNDARY_MULTI_CACHELINE        2
12576
12577 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12578 {
12579         int cacheline_size;
12580         u8 byte;
12581         int goal;
12582
12583         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12584         if (byte == 0)
12585                 cacheline_size = 1024;
12586         else
12587                 cacheline_size = (int) byte * 4;
12588
12589         /* On 5703 and later chips, the boundary bits have no
12590          * effect.
12591          */
12592         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12593             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12594             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12595                 goto out;
12596
12597 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12598         goal = BOUNDARY_MULTI_CACHELINE;
12599 #else
12600 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12601         goal = BOUNDARY_SINGLE_CACHELINE;
12602 #else
12603         goal = 0;
12604 #endif
12605 #endif
12606
12607         if (!goal)
12608                 goto out;
12609
12610         /* PCI controllers on most RISC systems tend to disconnect
12611          * when a device tries to burst across a cache-line boundary.
12612          * Therefore, letting tg3 do so just wastes PCI bandwidth.
12613          *
12614          * Unfortunately, for PCI-E there are only limited
12615          * write-side controls for this, and thus for reads
12616          * we will still get the disconnects.  We'll also waste
12617          * these PCI cycles for both read and write for chips
12618          * other than 5700 and 5701 which do not implement the
12619          * boundary bits.
12620          */
12621         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12622             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
12623                 switch (cacheline_size) {
12624                 case 16:
12625                 case 32:
12626                 case 64:
12627                 case 128:
12628                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12629                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
12630                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
12631                         } else {
12632                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12633                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12634                         }
12635                         break;
12636
12637                 case 256:
12638                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
12639                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
12640                         break;
12641
12642                 default:
12643                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12644                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12645                         break;
12646                 }
12647         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12648                 switch (cacheline_size) {
12649                 case 16:
12650                 case 32:
12651                 case 64:
12652                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12653                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12654                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
12655                                 break;
12656                         }
12657                         /* fallthrough */
12658                 case 128:
12659                 default:
12660                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12661                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
12662                         break;
12663                 }
12664         } else {
12665                 switch (cacheline_size) {
12666                 case 16:
12667                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12668                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
12669                                         DMA_RWCTRL_WRITE_BNDRY_16);
12670                                 break;
12671                         }
12672                         /* fallthrough */
12673                 case 32:
12674                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12675                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
12676                                         DMA_RWCTRL_WRITE_BNDRY_32);
12677                                 break;
12678                         }
12679                         /* fallthrough */
12680                 case 64:
12681                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12682                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
12683                                         DMA_RWCTRL_WRITE_BNDRY_64);
12684                                 break;
12685                         }
12686                         /* fallthrough */
12687                 case 128:
12688                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12689                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
12690                                         DMA_RWCTRL_WRITE_BNDRY_128);
12691                                 break;
12692                         }
12693                         /* fallthrough */
12694                 case 256:
12695                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
12696                                 DMA_RWCTRL_WRITE_BNDRY_256);
12697                         break;
12698                 case 512:
12699                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
12700                                 DMA_RWCTRL_WRITE_BNDRY_512);
12701                         break;
12702                 case 1024:
12703                 default:
12704                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
12705                                 DMA_RWCTRL_WRITE_BNDRY_1024);
12706                         break;
12707                 }
12708         }
12709
12710 out:
12711         return val;
12712 }
12713
12714 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
12715 {
12716         struct tg3_internal_buffer_desc test_desc;
12717         u32 sram_dma_descs;
12718         int i, ret;
12719
12720         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
12721
12722         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
12723         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
12724         tw32(RDMAC_STATUS, 0);
12725         tw32(WDMAC_STATUS, 0);
12726
12727         tw32(BUFMGR_MODE, 0);
12728         tw32(FTQ_RESET, 0);
12729
12730         test_desc.addr_hi = ((u64) buf_dma) >> 32;
12731         test_desc.addr_lo = buf_dma & 0xffffffff;
12732         test_desc.nic_mbuf = 0x00002100;
12733         test_desc.len = size;
12734
12735         /*
12736          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12737          * the *second* time the tg3 driver was getting loaded after an
12738          * initial scan.
12739          *
12740          * Broadcom tells me:
12741          *   ...the DMA engine is connected to the GRC block and a DMA
12742          *   reset may affect the GRC block in some unpredictable way...
12743          *   The behavior of resets to individual blocks has not been tested.
12744          *
12745          * Broadcom noted the GRC reset will also reset all sub-components.
12746          */
12747         if (to_device) {
12748                 test_desc.cqid_sqid = (13 << 8) | 2;
12749
12750                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
12751                 udelay(40);
12752         } else {
12753                 test_desc.cqid_sqid = (16 << 8) | 7;
12754
12755                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
12756                 udelay(40);
12757         }
12758         test_desc.flags = 0x00000005;
12759
12760         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
12761                 u32 val;
12762
12763                 val = *(((u32 *)&test_desc) + i);
12764                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
12765                                        sram_dma_descs + (i * sizeof(u32)));
12766                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
12767         }
12768         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
12769
12770         if (to_device) {
12771                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
12772         } else {
12773                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
12774         }
12775
12776         ret = -ENODEV;
12777         for (i = 0; i < 40; i++) {
12778                 u32 val;
12779
12780                 if (to_device)
12781                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
12782                 else
12783                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
12784                 if ((val & 0xffff) == sram_dma_descs) {
12785                         ret = 0;
12786                         break;
12787                 }
12788
12789                 udelay(100);
12790         }
12791
12792         return ret;
12793 }
12794
12795 #define TEST_BUFFER_SIZE        0x2000
12796
12797 static int __devinit tg3_test_dma(struct tg3 *tp)
12798 {
12799         dma_addr_t buf_dma;
12800         u32 *buf, saved_dma_rwctrl;
12801         int ret;
12802
12803         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
12804         if (!buf) {
12805                 ret = -ENOMEM;
12806                 goto out_nofree;
12807         }
12808
12809         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
12810                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
12811
12812         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
12813
12814         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12815                 /* DMA read watermark not used on PCIE */
12816                 tp->dma_rwctrl |= 0x00180000;
12817         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
12818                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
12819                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
12820                         tp->dma_rwctrl |= 0x003f0000;
12821                 else
12822                         tp->dma_rwctrl |= 0x003f000f;
12823         } else {
12824                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12825                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
12826                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
12827                         u32 read_water = 0x7;
12828
12829                         /* If the 5704 is behind the EPB bridge, we can
12830                          * do the less restrictive ONE_DMA workaround for
12831                          * better performance.
12832                          */
12833                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
12834                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12835                                 tp->dma_rwctrl |= 0x8000;
12836                         else if (ccval == 0x6 || ccval == 0x7)
12837                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
12838
12839                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
12840                                 read_water = 4;
12841                         /* Set bit 23 to enable PCIX hw bug fix */
12842                         tp->dma_rwctrl |=
12843                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
12844                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
12845                                 (1 << 23);
12846                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
12847                         /* 5780 always in PCIX mode */
12848                         tp->dma_rwctrl |= 0x00144000;
12849                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12850                         /* 5714 always in PCIX mode */
12851                         tp->dma_rwctrl |= 0x00148000;
12852                 } else {
12853                         tp->dma_rwctrl |= 0x001b000f;
12854                 }
12855         }
12856
12857         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12858             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12859                 tp->dma_rwctrl &= 0xfffffff0;
12860
12861         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12862             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
12863                 /* Remove this if it causes problems for some boards. */
12864                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
12865
12866                 /* On 5700/5701 chips, we need to set this bit.
12867                  * Otherwise the chip will issue cacheline transactions
12868                  * to streamable DMA memory with not all the byte
12869                  * enables turned on.  This is an error on several
12870                  * RISC PCI controllers, in particular sparc64.
12871                  *
12872                  * On 5703/5704 chips, this bit has been reassigned
12873                  * a different meaning.  In particular, it is used
12874                  * on those chips to enable a PCI-X workaround.
12875                  */
12876                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
12877         }
12878
12879         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12880
12881 #if 0
12882         /* Unneeded, already done by tg3_get_invariants.  */
12883         tg3_switch_clocks(tp);
12884 #endif
12885
12886         ret = 0;
12887         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12888             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
12889                 goto out;
12890
12891         /* It is best to perform DMA test with maximum write burst size
12892          * to expose the 5700/5701 write DMA bug.
12893          */
12894         saved_dma_rwctrl = tp->dma_rwctrl;
12895         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12896         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12897
12898         while (1) {
12899                 u32 *p = buf, i;
12900
12901                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
12902                         p[i] = i;
12903
12904                 /* Send the buffer to the chip. */
12905                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
12906                 if (ret) {
12907                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
12908                         break;
12909                 }
12910
12911 #if 0
12912                 /* validate data reached card RAM correctly. */
12913                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12914                         u32 val;
12915                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
12916                         if (le32_to_cpu(val) != p[i]) {
12917                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
12918                                 /* ret = -ENODEV here? */
12919                         }
12920                         p[i] = 0;
12921                 }
12922 #endif
12923                 /* Now read it back. */
12924                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
12925                 if (ret) {
12926                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
12927
12928                         break;
12929                 }
12930
12931                 /* Verify it. */
12932                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12933                         if (p[i] == i)
12934                                 continue;
12935
12936                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12937                             DMA_RWCTRL_WRITE_BNDRY_16) {
12938                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12939                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12940                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12941                                 break;
12942                         } else {
12943                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
12944                                 ret = -ENODEV;
12945                                 goto out;
12946                         }
12947                 }
12948
12949                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
12950                         /* Success. */
12951                         ret = 0;
12952                         break;
12953                 }
12954         }
12955         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12956             DMA_RWCTRL_WRITE_BNDRY_16) {
12957                 static struct pci_device_id dma_wait_state_chipsets[] = {
12958                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
12959                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
12960                         { },
12961                 };
12962
12963                 /* DMA test passed without adjusting DMA boundary,
12964                  * now look for chipsets that are known to expose the
12965                  * DMA bug without failing the test.
12966                  */
12967                 if (pci_dev_present(dma_wait_state_chipsets)) {
12968                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12969                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12970                 }
12971                 else
12972                         /* Safe to use the calculated DMA boundary. */
12973                         tp->dma_rwctrl = saved_dma_rwctrl;
12974
12975                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12976         }
12977
12978 out:
12979         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
12980 out_nofree:
12981         return ret;
12982 }
12983
12984 static void __devinit tg3_init_link_config(struct tg3 *tp)
12985 {
12986         tp->link_config.advertising =
12987                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12988                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12989                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
12990                  ADVERTISED_Autoneg | ADVERTISED_MII);
12991         tp->link_config.speed = SPEED_INVALID;
12992         tp->link_config.duplex = DUPLEX_INVALID;
12993         tp->link_config.autoneg = AUTONEG_ENABLE;
12994         tp->link_config.active_speed = SPEED_INVALID;
12995         tp->link_config.active_duplex = DUPLEX_INVALID;
12996         tp->link_config.phy_is_low_power = 0;
12997         tp->link_config.orig_speed = SPEED_INVALID;
12998         tp->link_config.orig_duplex = DUPLEX_INVALID;
12999         tp->link_config.orig_autoneg = AUTONEG_INVALID;
13000 }
13001
13002 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13003 {
13004         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13005                 tp->bufmgr_config.mbuf_read_dma_low_water =
13006                         DEFAULT_MB_RDMA_LOW_WATER_5705;
13007                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13008                         DEFAULT_MB_MACRX_LOW_WATER_5705;
13009                 tp->bufmgr_config.mbuf_high_water =
13010                         DEFAULT_MB_HIGH_WATER_5705;
13011                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13012                         tp->bufmgr_config.mbuf_mac_rx_low_water =
13013                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
13014                         tp->bufmgr_config.mbuf_high_water =
13015                                 DEFAULT_MB_HIGH_WATER_5906;
13016                 }
13017
13018                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13019                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13020                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13021                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13022                 tp->bufmgr_config.mbuf_high_water_jumbo =
13023                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13024         } else {
13025                 tp->bufmgr_config.mbuf_read_dma_low_water =
13026                         DEFAULT_MB_RDMA_LOW_WATER;
13027                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13028                         DEFAULT_MB_MACRX_LOW_WATER;
13029                 tp->bufmgr_config.mbuf_high_water =
13030                         DEFAULT_MB_HIGH_WATER;
13031
13032                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13033                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13034                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13035                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13036                 tp->bufmgr_config.mbuf_high_water_jumbo =
13037                         DEFAULT_MB_HIGH_WATER_JUMBO;
13038         }
13039
13040         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13041         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13042 }
13043
13044 static char * __devinit tg3_phy_string(struct tg3 *tp)
13045 {
13046         switch (tp->phy_id & PHY_ID_MASK) {
13047         case PHY_ID_BCM5400:    return "5400";
13048         case PHY_ID_BCM5401:    return "5401";
13049         case PHY_ID_BCM5411:    return "5411";
13050         case PHY_ID_BCM5701:    return "5701";
13051         case PHY_ID_BCM5703:    return "5703";
13052         case PHY_ID_BCM5704:    return "5704";
13053         case PHY_ID_BCM5705:    return "5705";
13054         case PHY_ID_BCM5750:    return "5750";
13055         case PHY_ID_BCM5752:    return "5752";
13056         case PHY_ID_BCM5714:    return "5714";
13057         case PHY_ID_BCM5780:    return "5780";
13058         case PHY_ID_BCM5755:    return "5755";
13059         case PHY_ID_BCM5787:    return "5787";
13060         case PHY_ID_BCM5784:    return "5784";
13061         case PHY_ID_BCM5756:    return "5722/5756";
13062         case PHY_ID_BCM5906:    return "5906";
13063         case PHY_ID_BCM5761:    return "5761";
13064         case PHY_ID_BCM8002:    return "8002/serdes";
13065         case 0:                 return "serdes";
13066         default:                return "unknown";
13067         }
13068 }
13069
13070 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13071 {
13072         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13073                 strcpy(str, "PCI Express");
13074                 return str;
13075         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13076                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13077
13078                 strcpy(str, "PCIX:");
13079
13080                 if ((clock_ctrl == 7) ||
13081                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13082                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13083                         strcat(str, "133MHz");
13084                 else if (clock_ctrl == 0)
13085                         strcat(str, "33MHz");
13086                 else if (clock_ctrl == 2)
13087                         strcat(str, "50MHz");
13088                 else if (clock_ctrl == 4)
13089                         strcat(str, "66MHz");
13090                 else if (clock_ctrl == 6)
13091                         strcat(str, "100MHz");
13092         } else {
13093                 strcpy(str, "PCI:");
13094                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13095                         strcat(str, "66MHz");
13096                 else
13097                         strcat(str, "33MHz");
13098         }
13099         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13100                 strcat(str, ":32-bit");
13101         else
13102                 strcat(str, ":64-bit");
13103         return str;
13104 }
13105
13106 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
13107 {
13108         struct pci_dev *peer;
13109         unsigned int func, devnr = tp->pdev->devfn & ~7;
13110
13111         for (func = 0; func < 8; func++) {
13112                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13113                 if (peer && peer != tp->pdev)
13114                         break;
13115                 pci_dev_put(peer);
13116         }
13117         /* 5704 can be configured in single-port mode, set peer to
13118          * tp->pdev in that case.
13119          */
13120         if (!peer) {
13121                 peer = tp->pdev;
13122                 return peer;
13123         }
13124
13125         /*
13126          * We don't need to keep the refcount elevated; there's no way
13127          * to remove one half of this device without removing the other
13128          */
13129         pci_dev_put(peer);
13130
13131         return peer;
13132 }
13133
13134 static void __devinit tg3_init_coal(struct tg3 *tp)
13135 {
13136         struct ethtool_coalesce *ec = &tp->coal;
13137
13138         memset(ec, 0, sizeof(*ec));
13139         ec->cmd = ETHTOOL_GCOALESCE;
13140         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13141         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13142         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13143         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13144         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13145         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13146         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13147         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13148         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13149
13150         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13151                                  HOSTCC_MODE_CLRTICK_TXBD)) {
13152                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13153                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13154                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13155                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13156         }
13157
13158         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13159                 ec->rx_coalesce_usecs_irq = 0;
13160                 ec->tx_coalesce_usecs_irq = 0;
13161                 ec->stats_block_coalesce_usecs = 0;
13162         }
13163 }
13164
13165 static const struct net_device_ops tg3_netdev_ops = {
13166         .ndo_open               = tg3_open,
13167         .ndo_stop               = tg3_close,
13168         .ndo_start_xmit         = tg3_start_xmit,
13169         .ndo_get_stats          = tg3_get_stats,
13170         .ndo_validate_addr      = eth_validate_addr,
13171         .ndo_set_multicast_list = tg3_set_rx_mode,
13172         .ndo_set_mac_address    = tg3_set_mac_addr,
13173         .ndo_do_ioctl           = tg3_ioctl,
13174         .ndo_tx_timeout         = tg3_tx_timeout,
13175         .ndo_change_mtu         = tg3_change_mtu,
13176 #if TG3_VLAN_TAG_USED
13177         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13178 #endif
13179 #ifdef CONFIG_NET_POLL_CONTROLLER
13180         .ndo_poll_controller    = tg3_poll_controller,
13181 #endif
13182 };
13183
13184 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13185         .ndo_open               = tg3_open,
13186         .ndo_stop               = tg3_close,
13187         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
13188         .ndo_get_stats          = tg3_get_stats,
13189         .ndo_validate_addr      = eth_validate_addr,
13190         .ndo_set_multicast_list = tg3_set_rx_mode,
13191         .ndo_set_mac_address    = tg3_set_mac_addr,
13192         .ndo_do_ioctl           = tg3_ioctl,
13193         .ndo_tx_timeout         = tg3_tx_timeout,
13194         .ndo_change_mtu         = tg3_change_mtu,
13195 #if TG3_VLAN_TAG_USED
13196         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13197 #endif
13198 #ifdef CONFIG_NET_POLL_CONTROLLER
13199         .ndo_poll_controller    = tg3_poll_controller,
13200 #endif
13201 };
13202
13203 static int __devinit tg3_init_one(struct pci_dev *pdev,
13204                                   const struct pci_device_id *ent)
13205 {
13206         static int tg3_version_printed = 0;
13207         struct net_device *dev;
13208         struct tg3 *tp;
13209         int err, pm_cap;
13210         char str[40];
13211         u64 dma_mask, persist_dma_mask;
13212
13213         if (tg3_version_printed++ == 0)
13214                 printk(KERN_INFO "%s", version);
13215
13216         err = pci_enable_device(pdev);
13217         if (err) {
13218                 printk(KERN_ERR PFX "Cannot enable PCI device, "
13219                        "aborting.\n");
13220                 return err;
13221         }
13222
13223         err = pci_request_regions(pdev, DRV_MODULE_NAME);
13224         if (err) {
13225                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13226                        "aborting.\n");
13227                 goto err_out_disable_pdev;
13228         }
13229
13230         pci_set_master(pdev);
13231
13232         /* Find power-management capability. */
13233         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13234         if (pm_cap == 0) {
13235                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13236                        "aborting.\n");
13237                 err = -EIO;
13238                 goto err_out_free_res;
13239         }
13240
13241         dev = alloc_etherdev(sizeof(*tp));
13242         if (!dev) {
13243                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13244                 err = -ENOMEM;
13245                 goto err_out_free_res;
13246         }
13247
13248         SET_NETDEV_DEV(dev, &pdev->dev);
13249
13250 #if TG3_VLAN_TAG_USED
13251         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
13252 #endif
13253
13254         tp = netdev_priv(dev);
13255         tp->pdev = pdev;
13256         tp->dev = dev;
13257         tp->pm_cap = pm_cap;
13258         tp->rx_mode = TG3_DEF_RX_MODE;
13259         tp->tx_mode = TG3_DEF_TX_MODE;
13260
13261         if (tg3_debug > 0)
13262                 tp->msg_enable = tg3_debug;
13263         else
13264                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13265
13266         /* The word/byte swap controls here control register access byte
13267          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
13268          * setting below.
13269          */
13270         tp->misc_host_ctrl =
13271                 MISC_HOST_CTRL_MASK_PCI_INT |
13272                 MISC_HOST_CTRL_WORD_SWAP |
13273                 MISC_HOST_CTRL_INDIR_ACCESS |
13274                 MISC_HOST_CTRL_PCISTATE_RW;
13275
13276         /* The NONFRM (non-frame) byte/word swap controls take effect
13277          * on descriptor entries, anything which isn't packet data.
13278          *
13279          * The StrongARM chips on the board (one for tx, one for rx)
13280          * are running in big-endian mode.
13281          */
13282         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13283                         GRC_MODE_WSWAP_NONFRM_DATA);
13284 #ifdef __BIG_ENDIAN
13285         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13286 #endif
13287         spin_lock_init(&tp->lock);
13288         spin_lock_init(&tp->indirect_lock);
13289         INIT_WORK(&tp->reset_task, tg3_reset_task);
13290
13291         tp->regs = pci_ioremap_bar(pdev, BAR_0);
13292         if (!tp->regs) {
13293                 printk(KERN_ERR PFX "Cannot map device registers, "
13294                        "aborting.\n");
13295                 err = -ENOMEM;
13296                 goto err_out_free_dev;
13297         }
13298
13299         tg3_init_link_config(tp);
13300
13301         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13302         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13303         tp->tx_pending = TG3_DEF_TX_RING_PENDING;
13304
13305         netif_napi_add(dev, &tp->napi, tg3_poll, 64);
13306         dev->ethtool_ops = &tg3_ethtool_ops;
13307         dev->watchdog_timeo = TG3_TX_TIMEOUT;
13308         dev->irq = pdev->irq;
13309
13310         err = tg3_get_invariants(tp);
13311         if (err) {
13312                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13313                        "aborting.\n");
13314                 goto err_out_iounmap;
13315         }
13316
13317         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13318             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13319                 dev->netdev_ops = &tg3_netdev_ops;
13320         else
13321                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
13322
13323
13324         /* The EPB bridge inside 5714, 5715, and 5780 and any
13325          * device behind the EPB cannot support DMA addresses > 40-bit.
13326          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13327          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13328          * do DMA address check in tg3_start_xmit().
13329          */
13330         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
13331                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
13332         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
13333                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
13334 #ifdef CONFIG_HIGHMEM
13335                 dma_mask = DMA_BIT_MASK(64);
13336 #endif
13337         } else
13338                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
13339
13340         /* Configure DMA attributes. */
13341         if (dma_mask > DMA_BIT_MASK(32)) {
13342                 err = pci_set_dma_mask(pdev, dma_mask);
13343                 if (!err) {
13344                         dev->features |= NETIF_F_HIGHDMA;
13345                         err = pci_set_consistent_dma_mask(pdev,
13346                                                           persist_dma_mask);
13347                         if (err < 0) {
13348                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13349                                        "DMA for consistent allocations\n");
13350                                 goto err_out_iounmap;
13351                         }
13352                 }
13353         }
13354         if (err || dma_mask == DMA_BIT_MASK(32)) {
13355                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
13356                 if (err) {
13357                         printk(KERN_ERR PFX "No usable DMA configuration, "
13358                                "aborting.\n");
13359                         goto err_out_iounmap;
13360                 }
13361         }
13362
13363         tg3_init_bufmgr_config(tp);
13364
13365         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
13366                 tp->fw_needed = FIRMWARE_TG3;
13367
13368         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13369                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13370         }
13371         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13372             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13373             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
13374             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13375             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13376                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13377         } else {
13378                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
13379                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13380                         tp->fw_needed = FIRMWARE_TG3TSO5;
13381                 else
13382                         tp->fw_needed = FIRMWARE_TG3TSO;
13383         }
13384
13385         /* TSO is on by default on chips that support hardware TSO.
13386          * Firmware TSO on older chips gives lower performance, so it
13387          * is off by default, but can be enabled using ethtool.
13388          */
13389         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13390                 if (dev->features & NETIF_F_IP_CSUM)
13391                         dev->features |= NETIF_F_TSO;
13392                 if ((dev->features & NETIF_F_IPV6_CSUM) &&
13393                     (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
13394                         dev->features |= NETIF_F_TSO6;
13395                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13396                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13397                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
13398                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13399                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13400                         dev->features |= NETIF_F_TSO_ECN;
13401         }
13402
13403
13404         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
13405             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
13406             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
13407                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
13408                 tp->rx_pending = 63;
13409         }
13410
13411         err = tg3_get_device_address(tp);
13412         if (err) {
13413                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
13414                        "aborting.\n");
13415                 goto err_out_fw;
13416         }
13417
13418         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13419                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
13420                 if (!tp->aperegs) {
13421                         printk(KERN_ERR PFX "Cannot map APE registers, "
13422                                "aborting.\n");
13423                         err = -ENOMEM;
13424                         goto err_out_fw;
13425                 }
13426
13427                 tg3_ape_lock_init(tp);
13428
13429                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
13430                         tg3_read_dash_ver(tp);
13431         }
13432
13433         /*
13434          * Reset chip in case UNDI or EFI driver did not shutdown
13435          * DMA self test will enable WDMAC and we'll see (spurious)
13436          * pending DMA on the PCI bus at that point.
13437          */
13438         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
13439             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
13440                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
13441                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13442         }
13443
13444         err = tg3_test_dma(tp);
13445         if (err) {
13446                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
13447                 goto err_out_apeunmap;
13448         }
13449
13450         /* flow control autonegotiation is default behavior */
13451         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
13452         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
13453
13454         tg3_init_coal(tp);
13455
13456         pci_set_drvdata(pdev, dev);
13457
13458         err = register_netdev(dev);
13459         if (err) {
13460                 printk(KERN_ERR PFX "Cannot register net device, "
13461                        "aborting.\n");
13462                 goto err_out_apeunmap;
13463         }
13464
13465         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
13466                dev->name,
13467                tp->board_part_number,
13468                tp->pci_chip_rev_id,
13469                tg3_bus_string(tp, str),
13470                dev->dev_addr);
13471
13472         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
13473                 printk(KERN_INFO
13474                        "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
13475                        tp->dev->name,
13476                        tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
13477                        dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
13478         else
13479                 printk(KERN_INFO
13480                        "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
13481                        tp->dev->name, tg3_phy_string(tp),
13482                        ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13483                         ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13484                          "10/100/1000Base-T")),
13485                        (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
13486
13487         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
13488                dev->name,
13489                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13490                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13491                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13492                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
13493                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
13494         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13495                dev->name, tp->dma_rwctrl,
13496                (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
13497                 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
13498
13499         return 0;
13500
13501 err_out_apeunmap:
13502         if (tp->aperegs) {
13503                 iounmap(tp->aperegs);
13504                 tp->aperegs = NULL;
13505         }
13506
13507 err_out_fw:
13508         if (tp->fw)
13509                 release_firmware(tp->fw);
13510
13511 err_out_iounmap:
13512         if (tp->regs) {
13513                 iounmap(tp->regs);
13514                 tp->regs = NULL;
13515         }
13516
13517 err_out_free_dev:
13518         free_netdev(dev);
13519
13520 err_out_free_res:
13521         pci_release_regions(pdev);
13522
13523 err_out_disable_pdev:
13524         pci_disable_device(pdev);
13525         pci_set_drvdata(pdev, NULL);
13526         return err;
13527 }
13528
13529 static void __devexit tg3_remove_one(struct pci_dev *pdev)
13530 {
13531         struct net_device *dev = pci_get_drvdata(pdev);
13532
13533         if (dev) {
13534                 struct tg3 *tp = netdev_priv(dev);
13535
13536                 if (tp->fw)
13537                         release_firmware(tp->fw);
13538
13539                 flush_scheduled_work();
13540
13541                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
13542                         tg3_phy_fini(tp);
13543                         tg3_mdio_fini(tp);
13544                 }
13545
13546                 unregister_netdev(dev);
13547                 if (tp->aperegs) {
13548                         iounmap(tp->aperegs);
13549                         tp->aperegs = NULL;
13550                 }
13551                 if (tp->regs) {
13552                         iounmap(tp->regs);
13553                         tp->regs = NULL;
13554                 }
13555                 free_netdev(dev);
13556                 pci_release_regions(pdev);
13557                 pci_disable_device(pdev);
13558                 pci_set_drvdata(pdev, NULL);
13559         }
13560 }
13561
13562 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13563 {
13564         struct net_device *dev = pci_get_drvdata(pdev);
13565         struct tg3 *tp = netdev_priv(dev);
13566         pci_power_t target_state;
13567         int err;
13568
13569         /* PCI register 4 needs to be saved whether netif_running() or not.
13570          * MSI address and data need to be saved if using MSI and
13571          * netif_running().
13572          */
13573         pci_save_state(pdev);
13574
13575         if (!netif_running(dev))
13576                 return 0;
13577
13578         flush_scheduled_work();
13579         tg3_phy_stop(tp);
13580         tg3_netif_stop(tp);
13581
13582         del_timer_sync(&tp->timer);
13583
13584         tg3_full_lock(tp, 1);
13585         tg3_disable_ints(tp);
13586         tg3_full_unlock(tp);
13587
13588         netif_device_detach(dev);
13589
13590         tg3_full_lock(tp, 0);
13591         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13592         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
13593         tg3_full_unlock(tp);
13594
13595         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
13596
13597         err = tg3_set_power_state(tp, target_state);
13598         if (err) {
13599                 int err2;
13600
13601                 tg3_full_lock(tp, 0);
13602
13603                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13604                 err2 = tg3_restart_hw(tp, 1);
13605                 if (err2)
13606                         goto out;
13607
13608                 tp->timer.expires = jiffies + tp->timer_offset;
13609                 add_timer(&tp->timer);
13610
13611                 netif_device_attach(dev);
13612                 tg3_netif_start(tp);
13613
13614 out:
13615                 tg3_full_unlock(tp);
13616
13617                 if (!err2)
13618                         tg3_phy_start(tp);
13619         }
13620
13621         return err;
13622 }
13623
13624 static int tg3_resume(struct pci_dev *pdev)
13625 {
13626         struct net_device *dev = pci_get_drvdata(pdev);
13627         struct tg3 *tp = netdev_priv(dev);
13628         int err;
13629
13630         pci_restore_state(tp->pdev);
13631
13632         if (!netif_running(dev))
13633                 return 0;
13634
13635         err = tg3_set_power_state(tp, PCI_D0);
13636         if (err)
13637                 return err;
13638
13639         netif_device_attach(dev);
13640
13641         tg3_full_lock(tp, 0);
13642
13643         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13644         err = tg3_restart_hw(tp, 1);
13645         if (err)
13646                 goto out;
13647
13648         tp->timer.expires = jiffies + tp->timer_offset;
13649         add_timer(&tp->timer);
13650
13651         tg3_netif_start(tp);
13652
13653 out:
13654         tg3_full_unlock(tp);
13655
13656         if (!err)
13657                 tg3_phy_start(tp);
13658
13659         return err;
13660 }
13661
13662 static struct pci_driver tg3_driver = {
13663         .name           = DRV_MODULE_NAME,
13664         .id_table       = tg3_pci_tbl,
13665         .probe          = tg3_init_one,
13666         .remove         = __devexit_p(tg3_remove_one),
13667         .suspend        = tg3_suspend,
13668         .resume         = tg3_resume
13669 };
13670
13671 static int __init tg3_init(void)
13672 {
13673         return pci_register_driver(&tg3_driver);
13674 }
13675
13676 static void __exit tg3_cleanup(void)
13677 {
13678         pci_unregister_driver(&tg3_driver);
13679 }
13680
13681 module_init(tg3_init);
13682 module_exit(tg3_cleanup);